Vladimir Vana / mbed

pro vyuku PSS v Jecne

TARGET_NUCLEO_F103RB/core_cm0.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:
vladvana
Date:
Sun Sep 24 12:31:52 2017 +0000
Revision:
0:23d1f73bf130
podklady pro cviceni z PSS

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vladvana 0:23d1f73bf130 1 /**************************************************************************//**
vladvana 0:23d1f73bf130 2 * @file core_cm0.h
vladvana 0:23d1f73bf130 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
vladvana 0:23d1f73bf130 4 * @version V4.10
vladvana 0:23d1f73bf130 5 * @date 18. March 2015
vladvana 0:23d1f73bf130 6 *
vladvana 0:23d1f73bf130 7 * @note
vladvana 0:23d1f73bf130 8 *
vladvana 0:23d1f73bf130 9 ******************************************************************************/
vladvana 0:23d1f73bf130 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
vladvana 0:23d1f73bf130 11
vladvana 0:23d1f73bf130 12 All rights reserved.
vladvana 0:23d1f73bf130 13 Redistribution and use in source and binary forms, with or without
vladvana 0:23d1f73bf130 14 modification, are permitted provided that the following conditions are met:
vladvana 0:23d1f73bf130 15 - Redistributions of source code must retain the above copyright
vladvana 0:23d1f73bf130 16 notice, this list of conditions and the following disclaimer.
vladvana 0:23d1f73bf130 17 - Redistributions in binary form must reproduce the above copyright
vladvana 0:23d1f73bf130 18 notice, this list of conditions and the following disclaimer in the
vladvana 0:23d1f73bf130 19 documentation and/or other materials provided with the distribution.
vladvana 0:23d1f73bf130 20 - Neither the name of ARM nor the names of its contributors may be used
vladvana 0:23d1f73bf130 21 to endorse or promote products derived from this software without
vladvana 0:23d1f73bf130 22 specific prior written permission.
vladvana 0:23d1f73bf130 23 *
vladvana 0:23d1f73bf130 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana 0:23d1f73bf130 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana 0:23d1f73bf130 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vladvana 0:23d1f73bf130 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vladvana 0:23d1f73bf130 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vladvana 0:23d1f73bf130 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vladvana 0:23d1f73bf130 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vladvana 0:23d1f73bf130 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vladvana 0:23d1f73bf130 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vladvana 0:23d1f73bf130 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vladvana 0:23d1f73bf130 34 POSSIBILITY OF SUCH DAMAGE.
vladvana 0:23d1f73bf130 35 ---------------------------------------------------------------------------*/
vladvana 0:23d1f73bf130 36
vladvana 0:23d1f73bf130 37
vladvana 0:23d1f73bf130 38 #if defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 39 #pragma system_include /* treat file as system include file for MISRA check */
vladvana 0:23d1f73bf130 40 #endif
vladvana 0:23d1f73bf130 41
vladvana 0:23d1f73bf130 42 #ifndef __CORE_CM0_H_GENERIC
vladvana 0:23d1f73bf130 43 #define __CORE_CM0_H_GENERIC
vladvana 0:23d1f73bf130 44
vladvana 0:23d1f73bf130 45 #ifdef __cplusplus
vladvana 0:23d1f73bf130 46 extern "C" {
vladvana 0:23d1f73bf130 47 #endif
vladvana 0:23d1f73bf130 48
vladvana 0:23d1f73bf130 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
vladvana 0:23d1f73bf130 50 CMSIS violates the following MISRA-C:2004 rules:
vladvana 0:23d1f73bf130 51
vladvana 0:23d1f73bf130 52 \li Required Rule 8.5, object/function definition in header file.<br>
vladvana 0:23d1f73bf130 53 Function definitions in header files are used to allow 'inlining'.
vladvana 0:23d1f73bf130 54
vladvana 0:23d1f73bf130 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
vladvana 0:23d1f73bf130 56 Unions are used for effective representation of core registers.
vladvana 0:23d1f73bf130 57
vladvana 0:23d1f73bf130 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
vladvana 0:23d1f73bf130 59 Function-like macros are used to allow more efficient code.
vladvana 0:23d1f73bf130 60 */
vladvana 0:23d1f73bf130 61
vladvana 0:23d1f73bf130 62
vladvana 0:23d1f73bf130 63 /*******************************************************************************
vladvana 0:23d1f73bf130 64 * CMSIS definitions
vladvana 0:23d1f73bf130 65 ******************************************************************************/
vladvana 0:23d1f73bf130 66 /** \ingroup Cortex_M0
vladvana 0:23d1f73bf130 67 @{
vladvana 0:23d1f73bf130 68 */
vladvana 0:23d1f73bf130 69
vladvana 0:23d1f73bf130 70 /* CMSIS CM0 definitions */
vladvana 0:23d1f73bf130 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
vladvana 0:23d1f73bf130 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
vladvana 0:23d1f73bf130 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
vladvana 0:23d1f73bf130 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
vladvana 0:23d1f73bf130 75
vladvana 0:23d1f73bf130 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
vladvana 0:23d1f73bf130 77
vladvana 0:23d1f73bf130 78
vladvana 0:23d1f73bf130 79 #if defined ( __CC_ARM )
vladvana 0:23d1f73bf130 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
vladvana 0:23d1f73bf130 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
vladvana 0:23d1f73bf130 82 #define __STATIC_INLINE static __inline
vladvana 0:23d1f73bf130 83
vladvana 0:23d1f73bf130 84 #elif defined ( __GNUC__ )
vladvana 0:23d1f73bf130 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
vladvana 0:23d1f73bf130 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
vladvana 0:23d1f73bf130 87 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 88
vladvana 0:23d1f73bf130 89 #elif defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
vladvana 0:23d1f73bf130 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
vladvana 0:23d1f73bf130 92 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 93
vladvana 0:23d1f73bf130 94 #elif defined ( __TMS470__ )
vladvana 0:23d1f73bf130 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
vladvana 0:23d1f73bf130 96 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 97
vladvana 0:23d1f73bf130 98 #elif defined ( __TASKING__ )
vladvana 0:23d1f73bf130 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
vladvana 0:23d1f73bf130 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
vladvana 0:23d1f73bf130 101 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 102
vladvana 0:23d1f73bf130 103 #elif defined ( __CSMC__ )
vladvana 0:23d1f73bf130 104 #define __packed
vladvana 0:23d1f73bf130 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
vladvana 0:23d1f73bf130 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
vladvana 0:23d1f73bf130 107 #define __STATIC_INLINE static inline
vladvana 0:23d1f73bf130 108
vladvana 0:23d1f73bf130 109 #endif
vladvana 0:23d1f73bf130 110
vladvana 0:23d1f73bf130 111 /** __FPU_USED indicates whether an FPU is used or not.
vladvana 0:23d1f73bf130 112 This core does not support an FPU at all
vladvana 0:23d1f73bf130 113 */
vladvana 0:23d1f73bf130 114 #define __FPU_USED 0
vladvana 0:23d1f73bf130 115
vladvana 0:23d1f73bf130 116 #if defined ( __CC_ARM )
vladvana 0:23d1f73bf130 117 #if defined __TARGET_FPU_VFP
vladvana 0:23d1f73bf130 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 119 #endif
vladvana 0:23d1f73bf130 120
vladvana 0:23d1f73bf130 121 #elif defined ( __GNUC__ )
vladvana 0:23d1f73bf130 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
vladvana 0:23d1f73bf130 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 124 #endif
vladvana 0:23d1f73bf130 125
vladvana 0:23d1f73bf130 126 #elif defined ( __ICCARM__ )
vladvana 0:23d1f73bf130 127 #if defined __ARMVFP__
vladvana 0:23d1f73bf130 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 129 #endif
vladvana 0:23d1f73bf130 130
vladvana 0:23d1f73bf130 131 #elif defined ( __TMS470__ )
vladvana 0:23d1f73bf130 132 #if defined __TI__VFP_SUPPORT____
vladvana 0:23d1f73bf130 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 134 #endif
vladvana 0:23d1f73bf130 135
vladvana 0:23d1f73bf130 136 #elif defined ( __TASKING__ )
vladvana 0:23d1f73bf130 137 #if defined __FPU_VFP__
vladvana 0:23d1f73bf130 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 139 #endif
vladvana 0:23d1f73bf130 140
vladvana 0:23d1f73bf130 141 #elif defined ( __CSMC__ ) /* Cosmic */
vladvana 0:23d1f73bf130 142 #if ( __CSMC__ & 0x400) // FPU present for parser
vladvana 0:23d1f73bf130 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vladvana 0:23d1f73bf130 144 #endif
vladvana 0:23d1f73bf130 145 #endif
vladvana 0:23d1f73bf130 146
vladvana 0:23d1f73bf130 147 #include <stdint.h> /* standard types definitions */
vladvana 0:23d1f73bf130 148 #include <core_cmInstr.h> /* Core Instruction Access */
vladvana 0:23d1f73bf130 149 #include <core_cmFunc.h> /* Core Function Access */
vladvana 0:23d1f73bf130 150
vladvana 0:23d1f73bf130 151 #ifdef __cplusplus
vladvana 0:23d1f73bf130 152 }
vladvana 0:23d1f73bf130 153 #endif
vladvana 0:23d1f73bf130 154
vladvana 0:23d1f73bf130 155 #endif /* __CORE_CM0_H_GENERIC */
vladvana 0:23d1f73bf130 156
vladvana 0:23d1f73bf130 157 #ifndef __CMSIS_GENERIC
vladvana 0:23d1f73bf130 158
vladvana 0:23d1f73bf130 159 #ifndef __CORE_CM0_H_DEPENDANT
vladvana 0:23d1f73bf130 160 #define __CORE_CM0_H_DEPENDANT
vladvana 0:23d1f73bf130 161
vladvana 0:23d1f73bf130 162 #ifdef __cplusplus
vladvana 0:23d1f73bf130 163 extern "C" {
vladvana 0:23d1f73bf130 164 #endif
vladvana 0:23d1f73bf130 165
vladvana 0:23d1f73bf130 166 /* check device defines and use defaults */
vladvana 0:23d1f73bf130 167 #if defined __CHECK_DEVICE_DEFINES
vladvana 0:23d1f73bf130 168 #ifndef __CM0_REV
vladvana 0:23d1f73bf130 169 #define __CM0_REV 0x0000
vladvana 0:23d1f73bf130 170 #warning "__CM0_REV not defined in device header file; using default!"
vladvana 0:23d1f73bf130 171 #endif
vladvana 0:23d1f73bf130 172
vladvana 0:23d1f73bf130 173 #ifndef __NVIC_PRIO_BITS
vladvana 0:23d1f73bf130 174 #define __NVIC_PRIO_BITS 2
vladvana 0:23d1f73bf130 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
vladvana 0:23d1f73bf130 176 #endif
vladvana 0:23d1f73bf130 177
vladvana 0:23d1f73bf130 178 #ifndef __Vendor_SysTickConfig
vladvana 0:23d1f73bf130 179 #define __Vendor_SysTickConfig 0
vladvana 0:23d1f73bf130 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
vladvana 0:23d1f73bf130 181 #endif
vladvana 0:23d1f73bf130 182 #endif
vladvana 0:23d1f73bf130 183
vladvana 0:23d1f73bf130 184 /* IO definitions (access restrictions to peripheral registers) */
vladvana 0:23d1f73bf130 185 /**
vladvana 0:23d1f73bf130 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
vladvana 0:23d1f73bf130 187
vladvana 0:23d1f73bf130 188 <strong>IO Type Qualifiers</strong> are used
vladvana 0:23d1f73bf130 189 \li to specify the access to peripheral variables.
vladvana 0:23d1f73bf130 190 \li for automatic generation of peripheral register debug information.
vladvana 0:23d1f73bf130 191 */
vladvana 0:23d1f73bf130 192 #ifdef __cplusplus
vladvana 0:23d1f73bf130 193 #define __I volatile /*!< Defines 'read only' permissions */
vladvana 0:23d1f73bf130 194 #else
vladvana 0:23d1f73bf130 195 #define __I volatile const /*!< Defines 'read only' permissions */
vladvana 0:23d1f73bf130 196 #endif
vladvana 0:23d1f73bf130 197 #define __O volatile /*!< Defines 'write only' permissions */
vladvana 0:23d1f73bf130 198 #define __IO volatile /*!< Defines 'read / write' permissions */
vladvana 0:23d1f73bf130 199
vladvana 0:23d1f73bf130 200 /*@} end of group Cortex_M0 */
vladvana 0:23d1f73bf130 201
vladvana 0:23d1f73bf130 202
vladvana 0:23d1f73bf130 203
vladvana 0:23d1f73bf130 204 /*******************************************************************************
vladvana 0:23d1f73bf130 205 * Register Abstraction
vladvana 0:23d1f73bf130 206 Core Register contain:
vladvana 0:23d1f73bf130 207 - Core Register
vladvana 0:23d1f73bf130 208 - Core NVIC Register
vladvana 0:23d1f73bf130 209 - Core SCB Register
vladvana 0:23d1f73bf130 210 - Core SysTick Register
vladvana 0:23d1f73bf130 211 ******************************************************************************/
vladvana 0:23d1f73bf130 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
vladvana 0:23d1f73bf130 213 \brief Type definitions and defines for Cortex-M processor based devices.
vladvana 0:23d1f73bf130 214 */
vladvana 0:23d1f73bf130 215
vladvana 0:23d1f73bf130 216 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 217 \defgroup CMSIS_CORE Status and Control Registers
vladvana 0:23d1f73bf130 218 \brief Core Register type definitions.
vladvana 0:23d1f73bf130 219 @{
vladvana 0:23d1f73bf130 220 */
vladvana 0:23d1f73bf130 221
vladvana 0:23d1f73bf130 222 /** \brief Union type to access the Application Program Status Register (APSR).
vladvana 0:23d1f73bf130 223 */
vladvana 0:23d1f73bf130 224 typedef union
vladvana 0:23d1f73bf130 225 {
vladvana 0:23d1f73bf130 226 struct
vladvana 0:23d1f73bf130 227 {
vladvana 0:23d1f73bf130 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
vladvana 0:23d1f73bf130 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vladvana 0:23d1f73bf130 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vladvana 0:23d1f73bf130 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vladvana 0:23d1f73bf130 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vladvana 0:23d1f73bf130 233 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 234 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 235 } APSR_Type;
vladvana 0:23d1f73bf130 236
vladvana 0:23d1f73bf130 237 /* APSR Register Definitions */
vladvana 0:23d1f73bf130 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
vladvana 0:23d1f73bf130 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
vladvana 0:23d1f73bf130 240
vladvana 0:23d1f73bf130 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
vladvana 0:23d1f73bf130 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
vladvana 0:23d1f73bf130 243
vladvana 0:23d1f73bf130 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
vladvana 0:23d1f73bf130 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
vladvana 0:23d1f73bf130 246
vladvana 0:23d1f73bf130 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
vladvana 0:23d1f73bf130 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
vladvana 0:23d1f73bf130 249
vladvana 0:23d1f73bf130 250
vladvana 0:23d1f73bf130 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
vladvana 0:23d1f73bf130 252 */
vladvana 0:23d1f73bf130 253 typedef union
vladvana 0:23d1f73bf130 254 {
vladvana 0:23d1f73bf130 255 struct
vladvana 0:23d1f73bf130 256 {
vladvana 0:23d1f73bf130 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vladvana 0:23d1f73bf130 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
vladvana 0:23d1f73bf130 259 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 260 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 261 } IPSR_Type;
vladvana 0:23d1f73bf130 262
vladvana 0:23d1f73bf130 263 /* IPSR Register Definitions */
vladvana 0:23d1f73bf130 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
vladvana 0:23d1f73bf130 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
vladvana 0:23d1f73bf130 266
vladvana 0:23d1f73bf130 267
vladvana 0:23d1f73bf130 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
vladvana 0:23d1f73bf130 269 */
vladvana 0:23d1f73bf130 270 typedef union
vladvana 0:23d1f73bf130 271 {
vladvana 0:23d1f73bf130 272 struct
vladvana 0:23d1f73bf130 273 {
vladvana 0:23d1f73bf130 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vladvana 0:23d1f73bf130 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
vladvana 0:23d1f73bf130 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
vladvana 0:23d1f73bf130 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
vladvana 0:23d1f73bf130 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vladvana 0:23d1f73bf130 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vladvana 0:23d1f73bf130 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vladvana 0:23d1f73bf130 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vladvana 0:23d1f73bf130 282 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 283 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 284 } xPSR_Type;
vladvana 0:23d1f73bf130 285
vladvana 0:23d1f73bf130 286 /* xPSR Register Definitions */
vladvana 0:23d1f73bf130 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
vladvana 0:23d1f73bf130 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
vladvana 0:23d1f73bf130 289
vladvana 0:23d1f73bf130 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
vladvana 0:23d1f73bf130 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
vladvana 0:23d1f73bf130 292
vladvana 0:23d1f73bf130 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
vladvana 0:23d1f73bf130 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
vladvana 0:23d1f73bf130 295
vladvana 0:23d1f73bf130 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
vladvana 0:23d1f73bf130 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
vladvana 0:23d1f73bf130 298
vladvana 0:23d1f73bf130 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
vladvana 0:23d1f73bf130 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
vladvana 0:23d1f73bf130 301
vladvana 0:23d1f73bf130 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
vladvana 0:23d1f73bf130 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
vladvana 0:23d1f73bf130 304
vladvana 0:23d1f73bf130 305
vladvana 0:23d1f73bf130 306 /** \brief Union type to access the Control Registers (CONTROL).
vladvana 0:23d1f73bf130 307 */
vladvana 0:23d1f73bf130 308 typedef union
vladvana 0:23d1f73bf130 309 {
vladvana 0:23d1f73bf130 310 struct
vladvana 0:23d1f73bf130 311 {
vladvana 0:23d1f73bf130 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
vladvana 0:23d1f73bf130 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
vladvana 0:23d1f73bf130 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
vladvana 0:23d1f73bf130 315 } b; /*!< Structure used for bit access */
vladvana 0:23d1f73bf130 316 uint32_t w; /*!< Type used for word access */
vladvana 0:23d1f73bf130 317 } CONTROL_Type;
vladvana 0:23d1f73bf130 318
vladvana 0:23d1f73bf130 319 /* CONTROL Register Definitions */
vladvana 0:23d1f73bf130 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
vladvana 0:23d1f73bf130 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
vladvana 0:23d1f73bf130 322
vladvana 0:23d1f73bf130 323 /*@} end of group CMSIS_CORE */
vladvana 0:23d1f73bf130 324
vladvana 0:23d1f73bf130 325
vladvana 0:23d1f73bf130 326 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
vladvana 0:23d1f73bf130 328 \brief Type definitions for the NVIC Registers
vladvana 0:23d1f73bf130 329 @{
vladvana 0:23d1f73bf130 330 */
vladvana 0:23d1f73bf130 331
vladvana 0:23d1f73bf130 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
vladvana 0:23d1f73bf130 333 */
vladvana 0:23d1f73bf130 334 typedef struct
vladvana 0:23d1f73bf130 335 {
vladvana 0:23d1f73bf130 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
vladvana 0:23d1f73bf130 337 uint32_t RESERVED0[31];
vladvana 0:23d1f73bf130 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
vladvana 0:23d1f73bf130 339 uint32_t RSERVED1[31];
vladvana 0:23d1f73bf130 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
vladvana 0:23d1f73bf130 341 uint32_t RESERVED2[31];
vladvana 0:23d1f73bf130 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
vladvana 0:23d1f73bf130 343 uint32_t RESERVED3[31];
vladvana 0:23d1f73bf130 344 uint32_t RESERVED4[64];
vladvana 0:23d1f73bf130 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
vladvana 0:23d1f73bf130 346 } NVIC_Type;
vladvana 0:23d1f73bf130 347
vladvana 0:23d1f73bf130 348 /*@} end of group CMSIS_NVIC */
vladvana 0:23d1f73bf130 349
vladvana 0:23d1f73bf130 350
vladvana 0:23d1f73bf130 351 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 352 \defgroup CMSIS_SCB System Control Block (SCB)
vladvana 0:23d1f73bf130 353 \brief Type definitions for the System Control Block Registers
vladvana 0:23d1f73bf130 354 @{
vladvana 0:23d1f73bf130 355 */
vladvana 0:23d1f73bf130 356
vladvana 0:23d1f73bf130 357 /** \brief Structure type to access the System Control Block (SCB).
vladvana 0:23d1f73bf130 358 */
vladvana 0:23d1f73bf130 359 typedef struct
vladvana 0:23d1f73bf130 360 {
vladvana 0:23d1f73bf130 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
vladvana 0:23d1f73bf130 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
vladvana 0:23d1f73bf130 363 uint32_t RESERVED0;
vladvana 0:23d1f73bf130 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
vladvana 0:23d1f73bf130 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
vladvana 0:23d1f73bf130 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
vladvana 0:23d1f73bf130 367 uint32_t RESERVED1;
vladvana 0:23d1f73bf130 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
vladvana 0:23d1f73bf130 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
vladvana 0:23d1f73bf130 370 } SCB_Type;
vladvana 0:23d1f73bf130 371
vladvana 0:23d1f73bf130 372 /* SCB CPUID Register Definitions */
vladvana 0:23d1f73bf130 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
vladvana 0:23d1f73bf130 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
vladvana 0:23d1f73bf130 375
vladvana 0:23d1f73bf130 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
vladvana 0:23d1f73bf130 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
vladvana 0:23d1f73bf130 378
vladvana 0:23d1f73bf130 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
vladvana 0:23d1f73bf130 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
vladvana 0:23d1f73bf130 381
vladvana 0:23d1f73bf130 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
vladvana 0:23d1f73bf130 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
vladvana 0:23d1f73bf130 384
vladvana 0:23d1f73bf130 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
vladvana 0:23d1f73bf130 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
vladvana 0:23d1f73bf130 387
vladvana 0:23d1f73bf130 388 /* SCB Interrupt Control State Register Definitions */
vladvana 0:23d1f73bf130 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
vladvana 0:23d1f73bf130 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
vladvana 0:23d1f73bf130 391
vladvana 0:23d1f73bf130 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
vladvana 0:23d1f73bf130 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
vladvana 0:23d1f73bf130 394
vladvana 0:23d1f73bf130 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
vladvana 0:23d1f73bf130 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
vladvana 0:23d1f73bf130 397
vladvana 0:23d1f73bf130 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
vladvana 0:23d1f73bf130 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
vladvana 0:23d1f73bf130 400
vladvana 0:23d1f73bf130 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
vladvana 0:23d1f73bf130 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
vladvana 0:23d1f73bf130 403
vladvana 0:23d1f73bf130 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
vladvana 0:23d1f73bf130 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
vladvana 0:23d1f73bf130 406
vladvana 0:23d1f73bf130 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
vladvana 0:23d1f73bf130 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
vladvana 0:23d1f73bf130 409
vladvana 0:23d1f73bf130 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
vladvana 0:23d1f73bf130 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
vladvana 0:23d1f73bf130 412
vladvana 0:23d1f73bf130 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
vladvana 0:23d1f73bf130 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
vladvana 0:23d1f73bf130 415
vladvana 0:23d1f73bf130 416 /* SCB Application Interrupt and Reset Control Register Definitions */
vladvana 0:23d1f73bf130 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
vladvana 0:23d1f73bf130 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
vladvana 0:23d1f73bf130 419
vladvana 0:23d1f73bf130 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
vladvana 0:23d1f73bf130 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
vladvana 0:23d1f73bf130 422
vladvana 0:23d1f73bf130 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
vladvana 0:23d1f73bf130 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
vladvana 0:23d1f73bf130 425
vladvana 0:23d1f73bf130 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
vladvana 0:23d1f73bf130 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
vladvana 0:23d1f73bf130 428
vladvana 0:23d1f73bf130 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
vladvana 0:23d1f73bf130 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
vladvana 0:23d1f73bf130 431
vladvana 0:23d1f73bf130 432 /* SCB System Control Register Definitions */
vladvana 0:23d1f73bf130 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
vladvana 0:23d1f73bf130 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
vladvana 0:23d1f73bf130 435
vladvana 0:23d1f73bf130 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
vladvana 0:23d1f73bf130 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
vladvana 0:23d1f73bf130 438
vladvana 0:23d1f73bf130 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
vladvana 0:23d1f73bf130 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
vladvana 0:23d1f73bf130 441
vladvana 0:23d1f73bf130 442 /* SCB Configuration Control Register Definitions */
vladvana 0:23d1f73bf130 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
vladvana 0:23d1f73bf130 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
vladvana 0:23d1f73bf130 445
vladvana 0:23d1f73bf130 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
vladvana 0:23d1f73bf130 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
vladvana 0:23d1f73bf130 448
vladvana 0:23d1f73bf130 449 /* SCB System Handler Control and State Register Definitions */
vladvana 0:23d1f73bf130 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
vladvana 0:23d1f73bf130 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
vladvana 0:23d1f73bf130 452
vladvana 0:23d1f73bf130 453 /*@} end of group CMSIS_SCB */
vladvana 0:23d1f73bf130 454
vladvana 0:23d1f73bf130 455
vladvana 0:23d1f73bf130 456 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
vladvana 0:23d1f73bf130 458 \brief Type definitions for the System Timer Registers.
vladvana 0:23d1f73bf130 459 @{
vladvana 0:23d1f73bf130 460 */
vladvana 0:23d1f73bf130 461
vladvana 0:23d1f73bf130 462 /** \brief Structure type to access the System Timer (SysTick).
vladvana 0:23d1f73bf130 463 */
vladvana 0:23d1f73bf130 464 typedef struct
vladvana 0:23d1f73bf130 465 {
vladvana 0:23d1f73bf130 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
vladvana 0:23d1f73bf130 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
vladvana 0:23d1f73bf130 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
vladvana 0:23d1f73bf130 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
vladvana 0:23d1f73bf130 470 } SysTick_Type;
vladvana 0:23d1f73bf130 471
vladvana 0:23d1f73bf130 472 /* SysTick Control / Status Register Definitions */
vladvana 0:23d1f73bf130 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
vladvana 0:23d1f73bf130 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
vladvana 0:23d1f73bf130 475
vladvana 0:23d1f73bf130 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
vladvana 0:23d1f73bf130 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
vladvana 0:23d1f73bf130 478
vladvana 0:23d1f73bf130 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
vladvana 0:23d1f73bf130 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
vladvana 0:23d1f73bf130 481
vladvana 0:23d1f73bf130 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
vladvana 0:23d1f73bf130 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
vladvana 0:23d1f73bf130 484
vladvana 0:23d1f73bf130 485 /* SysTick Reload Register Definitions */
vladvana 0:23d1f73bf130 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
vladvana 0:23d1f73bf130 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
vladvana 0:23d1f73bf130 488
vladvana 0:23d1f73bf130 489 /* SysTick Current Register Definitions */
vladvana 0:23d1f73bf130 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
vladvana 0:23d1f73bf130 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
vladvana 0:23d1f73bf130 492
vladvana 0:23d1f73bf130 493 /* SysTick Calibration Register Definitions */
vladvana 0:23d1f73bf130 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
vladvana 0:23d1f73bf130 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
vladvana 0:23d1f73bf130 496
vladvana 0:23d1f73bf130 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
vladvana 0:23d1f73bf130 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
vladvana 0:23d1f73bf130 499
vladvana 0:23d1f73bf130 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
vladvana 0:23d1f73bf130 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
vladvana 0:23d1f73bf130 502
vladvana 0:23d1f73bf130 503 /*@} end of group CMSIS_SysTick */
vladvana 0:23d1f73bf130 504
vladvana 0:23d1f73bf130 505
vladvana 0:23d1f73bf130 506 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
vladvana 0:23d1f73bf130 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
vladvana 0:23d1f73bf130 509 are only accessible over DAP and not via processor. Therefore
vladvana 0:23d1f73bf130 510 they are not covered by the Cortex-M0 header file.
vladvana 0:23d1f73bf130 511 @{
vladvana 0:23d1f73bf130 512 */
vladvana 0:23d1f73bf130 513 /*@} end of group CMSIS_CoreDebug */
vladvana 0:23d1f73bf130 514
vladvana 0:23d1f73bf130 515
vladvana 0:23d1f73bf130 516 /** \ingroup CMSIS_core_register
vladvana 0:23d1f73bf130 517 \defgroup CMSIS_core_base Core Definitions
vladvana 0:23d1f73bf130 518 \brief Definitions for base addresses, unions, and structures.
vladvana 0:23d1f73bf130 519 @{
vladvana 0:23d1f73bf130 520 */
vladvana 0:23d1f73bf130 521
vladvana 0:23d1f73bf130 522 /* Memory mapping of Cortex-M0 Hardware */
vladvana 0:23d1f73bf130 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
vladvana 0:23d1f73bf130 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
vladvana 0:23d1f73bf130 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
vladvana 0:23d1f73bf130 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
vladvana 0:23d1f73bf130 527
vladvana 0:23d1f73bf130 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
vladvana 0:23d1f73bf130 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
vladvana 0:23d1f73bf130 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
vladvana 0:23d1f73bf130 531
vladvana 0:23d1f73bf130 532
vladvana 0:23d1f73bf130 533 /*@} */
vladvana 0:23d1f73bf130 534
vladvana 0:23d1f73bf130 535
vladvana 0:23d1f73bf130 536
vladvana 0:23d1f73bf130 537 /*******************************************************************************
vladvana 0:23d1f73bf130 538 * Hardware Abstraction Layer
vladvana 0:23d1f73bf130 539 Core Function Interface contains:
vladvana 0:23d1f73bf130 540 - Core NVIC Functions
vladvana 0:23d1f73bf130 541 - Core SysTick Functions
vladvana 0:23d1f73bf130 542 - Core Register Access Functions
vladvana 0:23d1f73bf130 543 ******************************************************************************/
vladvana 0:23d1f73bf130 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
vladvana 0:23d1f73bf130 545 */
vladvana 0:23d1f73bf130 546
vladvana 0:23d1f73bf130 547
vladvana 0:23d1f73bf130 548
vladvana 0:23d1f73bf130 549 /* ########################## NVIC functions #################################### */
vladvana 0:23d1f73bf130 550 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
vladvana 0:23d1f73bf130 552 \brief Functions that manage interrupts and exceptions via the NVIC.
vladvana 0:23d1f73bf130 553 @{
vladvana 0:23d1f73bf130 554 */
vladvana 0:23d1f73bf130 555
vladvana 0:23d1f73bf130 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
vladvana 0:23d1f73bf130 557 /* The following MACROS handle generation of the register offset and byte masks */
vladvana 0:23d1f73bf130 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
vladvana 0:23d1f73bf130 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
vladvana 0:23d1f73bf130 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
vladvana 0:23d1f73bf130 561
vladvana 0:23d1f73bf130 562
vladvana 0:23d1f73bf130 563 /** \brief Enable External Interrupt
vladvana 0:23d1f73bf130 564
vladvana 0:23d1f73bf130 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
vladvana 0:23d1f73bf130 566
vladvana 0:23d1f73bf130 567 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 568 */
vladvana 0:23d1f73bf130 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 570 {
vladvana 0:23d1f73bf130 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 572 }
vladvana 0:23d1f73bf130 573
vladvana 0:23d1f73bf130 574
vladvana 0:23d1f73bf130 575 /** \brief Disable External Interrupt
vladvana 0:23d1f73bf130 576
vladvana 0:23d1f73bf130 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
vladvana 0:23d1f73bf130 578
vladvana 0:23d1f73bf130 579 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 580 */
vladvana 0:23d1f73bf130 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 582 {
vladvana 0:23d1f73bf130 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 584 }
vladvana 0:23d1f73bf130 585
vladvana 0:23d1f73bf130 586
vladvana 0:23d1f73bf130 587 /** \brief Get Pending Interrupt
vladvana 0:23d1f73bf130 588
vladvana 0:23d1f73bf130 589 The function reads the pending register in the NVIC and returns the pending bit
vladvana 0:23d1f73bf130 590 for the specified interrupt.
vladvana 0:23d1f73bf130 591
vladvana 0:23d1f73bf130 592 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 593
vladvana 0:23d1f73bf130 594 \return 0 Interrupt status is not pending.
vladvana 0:23d1f73bf130 595 \return 1 Interrupt status is pending.
vladvana 0:23d1f73bf130 596 */
vladvana 0:23d1f73bf130 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 598 {
vladvana 0:23d1f73bf130 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vladvana 0:23d1f73bf130 600 }
vladvana 0:23d1f73bf130 601
vladvana 0:23d1f73bf130 602
vladvana 0:23d1f73bf130 603 /** \brief Set Pending Interrupt
vladvana 0:23d1f73bf130 604
vladvana 0:23d1f73bf130 605 The function sets the pending bit of an external interrupt.
vladvana 0:23d1f73bf130 606
vladvana 0:23d1f73bf130 607 \param [in] IRQn Interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 608 */
vladvana 0:23d1f73bf130 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 610 {
vladvana 0:23d1f73bf130 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 612 }
vladvana 0:23d1f73bf130 613
vladvana 0:23d1f73bf130 614
vladvana 0:23d1f73bf130 615 /** \brief Clear Pending Interrupt
vladvana 0:23d1f73bf130 616
vladvana 0:23d1f73bf130 617 The function clears the pending bit of an external interrupt.
vladvana 0:23d1f73bf130 618
vladvana 0:23d1f73bf130 619 \param [in] IRQn External interrupt number. Value cannot be negative.
vladvana 0:23d1f73bf130 620 */
vladvana 0:23d1f73bf130 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 622 {
vladvana 0:23d1f73bf130 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vladvana 0:23d1f73bf130 624 }
vladvana 0:23d1f73bf130 625
vladvana 0:23d1f73bf130 626
vladvana 0:23d1f73bf130 627 /** \brief Set Interrupt Priority
vladvana 0:23d1f73bf130 628
vladvana 0:23d1f73bf130 629 The function sets the priority of an interrupt.
vladvana 0:23d1f73bf130 630
vladvana 0:23d1f73bf130 631 \note The priority cannot be set for every core interrupt.
vladvana 0:23d1f73bf130 632
vladvana 0:23d1f73bf130 633 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 634 \param [in] priority Priority to set.
vladvana 0:23d1f73bf130 635 */
vladvana 0:23d1f73bf130 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
vladvana 0:23d1f73bf130 637 {
vladvana 0:23d1f73bf130 638 if((int32_t)(IRQn) < 0) {
vladvana 0:23d1f73bf130 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
vladvana 0:23d1f73bf130 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
vladvana 0:23d1f73bf130 641 }
vladvana 0:23d1f73bf130 642 else {
vladvana 0:23d1f73bf130 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
vladvana 0:23d1f73bf130 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
vladvana 0:23d1f73bf130 645 }
vladvana 0:23d1f73bf130 646 }
vladvana 0:23d1f73bf130 647
vladvana 0:23d1f73bf130 648
vladvana 0:23d1f73bf130 649 /** \brief Get Interrupt Priority
vladvana 0:23d1f73bf130 650
vladvana 0:23d1f73bf130 651 The function reads the priority of an interrupt. The interrupt
vladvana 0:23d1f73bf130 652 number can be positive to specify an external (device specific)
vladvana 0:23d1f73bf130 653 interrupt, or negative to specify an internal (core) interrupt.
vladvana 0:23d1f73bf130 654
vladvana 0:23d1f73bf130 655
vladvana 0:23d1f73bf130 656 \param [in] IRQn Interrupt number.
vladvana 0:23d1f73bf130 657 \return Interrupt Priority. Value is aligned automatically to the implemented
vladvana 0:23d1f73bf130 658 priority bits of the microcontroller.
vladvana 0:23d1f73bf130 659 */
vladvana 0:23d1f73bf130 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
vladvana 0:23d1f73bf130 661 {
vladvana 0:23d1f73bf130 662
vladvana 0:23d1f73bf130 663 if((int32_t)(IRQn) < 0) {
vladvana 0:23d1f73bf130 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
vladvana 0:23d1f73bf130 665 }
vladvana 0:23d1f73bf130 666 else {
vladvana 0:23d1f73bf130 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
vladvana 0:23d1f73bf130 668 }
vladvana 0:23d1f73bf130 669 }
vladvana 0:23d1f73bf130 670
vladvana 0:23d1f73bf130 671
vladvana 0:23d1f73bf130 672 /** \brief System Reset
vladvana 0:23d1f73bf130 673
vladvana 0:23d1f73bf130 674 The function initiates a system reset request to reset the MCU.
vladvana 0:23d1f73bf130 675 */
vladvana 0:23d1f73bf130 676 __STATIC_INLINE void NVIC_SystemReset(void)
vladvana 0:23d1f73bf130 677 {
vladvana 0:23d1f73bf130 678 __DSB(); /* Ensure all outstanding memory accesses included
vladvana 0:23d1f73bf130 679 buffered write are completed before reset */
vladvana 0:23d1f73bf130 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
vladvana 0:23d1f73bf130 681 SCB_AIRCR_SYSRESETREQ_Msk);
vladvana 0:23d1f73bf130 682 __DSB(); /* Ensure completion of memory access */
vladvana 0:23d1f73bf130 683 while(1) { __NOP(); } /* wait until reset */
vladvana 0:23d1f73bf130 684 }
vladvana 0:23d1f73bf130 685
vladvana 0:23d1f73bf130 686 /*@} end of CMSIS_Core_NVICFunctions */
vladvana 0:23d1f73bf130 687
vladvana 0:23d1f73bf130 688
vladvana 0:23d1f73bf130 689
vladvana 0:23d1f73bf130 690 /* ################################## SysTick function ############################################ */
vladvana 0:23d1f73bf130 691 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
vladvana 0:23d1f73bf130 693 \brief Functions that configure the System.
vladvana 0:23d1f73bf130 694 @{
vladvana 0:23d1f73bf130 695 */
vladvana 0:23d1f73bf130 696
vladvana 0:23d1f73bf130 697 #if (__Vendor_SysTickConfig == 0)
vladvana 0:23d1f73bf130 698
vladvana 0:23d1f73bf130 699 /** \brief System Tick Configuration
vladvana 0:23d1f73bf130 700
vladvana 0:23d1f73bf130 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
vladvana 0:23d1f73bf130 702 Counter is in free running mode to generate periodic interrupts.
vladvana 0:23d1f73bf130 703
vladvana 0:23d1f73bf130 704 \param [in] ticks Number of ticks between two interrupts.
vladvana 0:23d1f73bf130 705
vladvana 0:23d1f73bf130 706 \return 0 Function succeeded.
vladvana 0:23d1f73bf130 707 \return 1 Function failed.
vladvana 0:23d1f73bf130 708
vladvana 0:23d1f73bf130 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
vladvana 0:23d1f73bf130 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
vladvana 0:23d1f73bf130 711 must contain a vendor-specific implementation of this function.
vladvana 0:23d1f73bf130 712
vladvana 0:23d1f73bf130 713 */
vladvana 0:23d1f73bf130 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
vladvana 0:23d1f73bf130 715 {
vladvana 0:23d1f73bf130 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
vladvana 0:23d1f73bf130 717
vladvana 0:23d1f73bf130 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
vladvana 0:23d1f73bf130 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
vladvana 0:23d1f73bf130 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
vladvana 0:23d1f73bf130 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
vladvana 0:23d1f73bf130 722 SysTick_CTRL_TICKINT_Msk |
vladvana 0:23d1f73bf130 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
vladvana 0:23d1f73bf130 724 return (0UL); /* Function successful */
vladvana 0:23d1f73bf130 725 }
vladvana 0:23d1f73bf130 726
vladvana 0:23d1f73bf130 727 #endif
vladvana 0:23d1f73bf130 728
vladvana 0:23d1f73bf130 729 /*@} end of CMSIS_Core_SysTickFunctions */
vladvana 0:23d1f73bf130 730
vladvana 0:23d1f73bf130 731
vladvana 0:23d1f73bf130 732
vladvana 0:23d1f73bf130 733
vladvana 0:23d1f73bf130 734 #ifdef __cplusplus
vladvana 0:23d1f73bf130 735 }
vladvana 0:23d1f73bf130 736 #endif
vladvana 0:23d1f73bf130 737
vladvana 0:23d1f73bf130 738 #endif /* __CORE_CM0_H_DEPENDANT */
vladvana 0:23d1f73bf130 739
vladvana 0:23d1f73bf130 740 #endif /* __CMSIS_GENERIC */