Vladimir Vana / mbed

pro vyuku PSS v Jecne

TARGET_NUCLEO_F103RB/core_caFunc.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:
vladvana
Date:
Sun Sep 24 12:31:52 2017 +0000
Revision:
0:23d1f73bf130
podklady pro cviceni z PSS

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vladvana 0:23d1f73bf130 1 /**************************************************************************//**
vladvana 0:23d1f73bf130 2 * @file core_caFunc.h
vladvana 0:23d1f73bf130 3 * @brief CMSIS Cortex-A Core Function Access Header File
vladvana 0:23d1f73bf130 4 * @version V3.10
vladvana 0:23d1f73bf130 5 * @date 30 Oct 2013
vladvana 0:23d1f73bf130 6 *
vladvana 0:23d1f73bf130 7 * @note
vladvana 0:23d1f73bf130 8 *
vladvana 0:23d1f73bf130 9 ******************************************************************************/
vladvana 0:23d1f73bf130 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
vladvana 0:23d1f73bf130 11
vladvana 0:23d1f73bf130 12 All rights reserved.
vladvana 0:23d1f73bf130 13 Redistribution and use in source and binary forms, with or without
vladvana 0:23d1f73bf130 14 modification, are permitted provided that the following conditions are met:
vladvana 0:23d1f73bf130 15 - Redistributions of source code must retain the above copyright
vladvana 0:23d1f73bf130 16 notice, this list of conditions and the following disclaimer.
vladvana 0:23d1f73bf130 17 - Redistributions in binary form must reproduce the above copyright
vladvana 0:23d1f73bf130 18 notice, this list of conditions and the following disclaimer in the
vladvana 0:23d1f73bf130 19 documentation and/or other materials provided with the distribution.
vladvana 0:23d1f73bf130 20 - Neither the name of ARM nor the names of its contributors may be used
vladvana 0:23d1f73bf130 21 to endorse or promote products derived from this software without
vladvana 0:23d1f73bf130 22 specific prior written permission.
vladvana 0:23d1f73bf130 23 *
vladvana 0:23d1f73bf130 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana 0:23d1f73bf130 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana 0:23d1f73bf130 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vladvana 0:23d1f73bf130 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vladvana 0:23d1f73bf130 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vladvana 0:23d1f73bf130 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vladvana 0:23d1f73bf130 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vladvana 0:23d1f73bf130 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vladvana 0:23d1f73bf130 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vladvana 0:23d1f73bf130 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vladvana 0:23d1f73bf130 34 POSSIBILITY OF SUCH DAMAGE.
vladvana 0:23d1f73bf130 35 ---------------------------------------------------------------------------*/
vladvana 0:23d1f73bf130 36
vladvana 0:23d1f73bf130 37
vladvana 0:23d1f73bf130 38 #ifndef __CORE_CAFUNC_H__
vladvana 0:23d1f73bf130 39 #define __CORE_CAFUNC_H__
vladvana 0:23d1f73bf130 40
vladvana 0:23d1f73bf130 41
vladvana 0:23d1f73bf130 42 /* ########################### Core Function Access ########################### */
vladvana 0:23d1f73bf130 43 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
vladvana 0:23d1f73bf130 45 @{
vladvana 0:23d1f73bf130 46 */
vladvana 0:23d1f73bf130 47
vladvana 0:23d1f73bf130 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
vladvana 0:23d1f73bf130 49 /* ARM armcc specific functions */
vladvana 0:23d1f73bf130 50
vladvana 0:23d1f73bf130 51 #if (__ARMCC_VERSION < 400677)
vladvana 0:23d1f73bf130 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
vladvana 0:23d1f73bf130 53 #endif
vladvana 0:23d1f73bf130 54
vladvana 0:23d1f73bf130 55 #define MODE_USR 0x10
vladvana 0:23d1f73bf130 56 #define MODE_FIQ 0x11
vladvana 0:23d1f73bf130 57 #define MODE_IRQ 0x12
vladvana 0:23d1f73bf130 58 #define MODE_SVC 0x13
vladvana 0:23d1f73bf130 59 #define MODE_MON 0x16
vladvana 0:23d1f73bf130 60 #define MODE_ABT 0x17
vladvana 0:23d1f73bf130 61 #define MODE_HYP 0x1A
vladvana 0:23d1f73bf130 62 #define MODE_UND 0x1B
vladvana 0:23d1f73bf130 63 #define MODE_SYS 0x1F
vladvana 0:23d1f73bf130 64
vladvana 0:23d1f73bf130 65 /** \brief Get APSR Register
vladvana 0:23d1f73bf130 66
vladvana 0:23d1f73bf130 67 This function returns the content of the APSR Register.
vladvana 0:23d1f73bf130 68
vladvana 0:23d1f73bf130 69 \return APSR Register value
vladvana 0:23d1f73bf130 70 */
vladvana 0:23d1f73bf130 71 __STATIC_INLINE uint32_t __get_APSR(void)
vladvana 0:23d1f73bf130 72 {
vladvana 0:23d1f73bf130 73 register uint32_t __regAPSR __ASM("apsr");
vladvana 0:23d1f73bf130 74 return(__regAPSR);
vladvana 0:23d1f73bf130 75 }
vladvana 0:23d1f73bf130 76
vladvana 0:23d1f73bf130 77
vladvana 0:23d1f73bf130 78 /** \brief Get CPSR Register
vladvana 0:23d1f73bf130 79
vladvana 0:23d1f73bf130 80 This function returns the content of the CPSR Register.
vladvana 0:23d1f73bf130 81
vladvana 0:23d1f73bf130 82 \return CPSR Register value
vladvana 0:23d1f73bf130 83 */
vladvana 0:23d1f73bf130 84 __STATIC_INLINE uint32_t __get_CPSR(void)
vladvana 0:23d1f73bf130 85 {
vladvana 0:23d1f73bf130 86 register uint32_t __regCPSR __ASM("cpsr");
vladvana 0:23d1f73bf130 87 return(__regCPSR);
vladvana 0:23d1f73bf130 88 }
vladvana 0:23d1f73bf130 89
vladvana 0:23d1f73bf130 90 /** \brief Set Stack Pointer
vladvana 0:23d1f73bf130 91
vladvana 0:23d1f73bf130 92 This function assigns the given value to the current stack pointer.
vladvana 0:23d1f73bf130 93
vladvana 0:23d1f73bf130 94 \param [in] topOfStack Stack Pointer value to set
vladvana 0:23d1f73bf130 95 */
vladvana 0:23d1f73bf130 96 register uint32_t __regSP __ASM("sp");
vladvana 0:23d1f73bf130 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
vladvana 0:23d1f73bf130 98 {
vladvana 0:23d1f73bf130 99 __regSP = topOfStack;
vladvana 0:23d1f73bf130 100 }
vladvana 0:23d1f73bf130 101
vladvana 0:23d1f73bf130 102
vladvana 0:23d1f73bf130 103 /** \brief Get link register
vladvana 0:23d1f73bf130 104
vladvana 0:23d1f73bf130 105 This function returns the value of the link register
vladvana 0:23d1f73bf130 106
vladvana 0:23d1f73bf130 107 \return Value of link register
vladvana 0:23d1f73bf130 108 */
vladvana 0:23d1f73bf130 109 register uint32_t __reglr __ASM("lr");
vladvana 0:23d1f73bf130 110 __STATIC_INLINE uint32_t __get_LR(void)
vladvana 0:23d1f73bf130 111 {
vladvana 0:23d1f73bf130 112 return(__reglr);
vladvana 0:23d1f73bf130 113 }
vladvana 0:23d1f73bf130 114
vladvana 0:23d1f73bf130 115 /** \brief Set link register
vladvana 0:23d1f73bf130 116
vladvana 0:23d1f73bf130 117 This function sets the value of the link register
vladvana 0:23d1f73bf130 118
vladvana 0:23d1f73bf130 119 \param [in] lr LR value to set
vladvana 0:23d1f73bf130 120 */
vladvana 0:23d1f73bf130 121 __STATIC_INLINE void __set_LR(uint32_t lr)
vladvana 0:23d1f73bf130 122 {
vladvana 0:23d1f73bf130 123 __reglr = lr;
vladvana 0:23d1f73bf130 124 }
vladvana 0:23d1f73bf130 125
vladvana 0:23d1f73bf130 126 /** \brief Set Process Stack Pointer
vladvana 0:23d1f73bf130 127
vladvana 0:23d1f73bf130 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
vladvana 0:23d1f73bf130 129
vladvana 0:23d1f73bf130 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
vladvana 0:23d1f73bf130 131 */
vladvana 0:23d1f73bf130 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
vladvana 0:23d1f73bf130 133 {
vladvana 0:23d1f73bf130 134 ARM
vladvana 0:23d1f73bf130 135 PRESERVE8
vladvana 0:23d1f73bf130 136
vladvana 0:23d1f73bf130 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
vladvana 0:23d1f73bf130 138 MRS R1, CPSR
vladvana 0:23d1f73bf130 139 CPS #MODE_SYS ;no effect in USR mode
vladvana 0:23d1f73bf130 140 MOV SP, R0
vladvana 0:23d1f73bf130 141 MSR CPSR_c, R1 ;no effect in USR mode
vladvana 0:23d1f73bf130 142 ISB
vladvana 0:23d1f73bf130 143 BX LR
vladvana 0:23d1f73bf130 144
vladvana 0:23d1f73bf130 145 }
vladvana 0:23d1f73bf130 146
vladvana 0:23d1f73bf130 147 /** \brief Set User Mode
vladvana 0:23d1f73bf130 148
vladvana 0:23d1f73bf130 149 This function changes the processor state to User Mode
vladvana 0:23d1f73bf130 150 */
vladvana 0:23d1f73bf130 151 __STATIC_ASM void __set_CPS_USR(void)
vladvana 0:23d1f73bf130 152 {
vladvana 0:23d1f73bf130 153 ARM
vladvana 0:23d1f73bf130 154
vladvana 0:23d1f73bf130 155 CPS #MODE_USR
vladvana 0:23d1f73bf130 156 BX LR
vladvana 0:23d1f73bf130 157 }
vladvana 0:23d1f73bf130 158
vladvana 0:23d1f73bf130 159
vladvana 0:23d1f73bf130 160 /** \brief Enable FIQ
vladvana 0:23d1f73bf130 161
vladvana 0:23d1f73bf130 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
vladvana 0:23d1f73bf130 163 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 164 */
vladvana 0:23d1f73bf130 165 #define __enable_fault_irq __enable_fiq
vladvana 0:23d1f73bf130 166
vladvana 0:23d1f73bf130 167
vladvana 0:23d1f73bf130 168 /** \brief Disable FIQ
vladvana 0:23d1f73bf130 169
vladvana 0:23d1f73bf130 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
vladvana 0:23d1f73bf130 171 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 172 */
vladvana 0:23d1f73bf130 173 #define __disable_fault_irq __disable_fiq
vladvana 0:23d1f73bf130 174
vladvana 0:23d1f73bf130 175
vladvana 0:23d1f73bf130 176 /** \brief Get FPSCR
vladvana 0:23d1f73bf130 177
vladvana 0:23d1f73bf130 178 This function returns the current value of the Floating Point Status/Control register.
vladvana 0:23d1f73bf130 179
vladvana 0:23d1f73bf130 180 \return Floating Point Status/Control register value
vladvana 0:23d1f73bf130 181 */
vladvana 0:23d1f73bf130 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
vladvana 0:23d1f73bf130 183 {
vladvana 0:23d1f73bf130 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vladvana 0:23d1f73bf130 185 register uint32_t __regfpscr __ASM("fpscr");
vladvana 0:23d1f73bf130 186 return(__regfpscr);
vladvana 0:23d1f73bf130 187 #else
vladvana 0:23d1f73bf130 188 return(0);
vladvana 0:23d1f73bf130 189 #endif
vladvana 0:23d1f73bf130 190 }
vladvana 0:23d1f73bf130 191
vladvana 0:23d1f73bf130 192
vladvana 0:23d1f73bf130 193 /** \brief Set FPSCR
vladvana 0:23d1f73bf130 194
vladvana 0:23d1f73bf130 195 This function assigns the given value to the Floating Point Status/Control register.
vladvana 0:23d1f73bf130 196
vladvana 0:23d1f73bf130 197 \param [in] fpscr Floating Point Status/Control value to set
vladvana 0:23d1f73bf130 198 */
vladvana 0:23d1f73bf130 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
vladvana 0:23d1f73bf130 200 {
vladvana 0:23d1f73bf130 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vladvana 0:23d1f73bf130 202 register uint32_t __regfpscr __ASM("fpscr");
vladvana 0:23d1f73bf130 203 __regfpscr = (fpscr);
vladvana 0:23d1f73bf130 204 #endif
vladvana 0:23d1f73bf130 205 }
vladvana 0:23d1f73bf130 206
vladvana 0:23d1f73bf130 207 /** \brief Get FPEXC
vladvana 0:23d1f73bf130 208
vladvana 0:23d1f73bf130 209 This function returns the current value of the Floating Point Exception Control register.
vladvana 0:23d1f73bf130 210
vladvana 0:23d1f73bf130 211 \return Floating Point Exception Control register value
vladvana 0:23d1f73bf130 212 */
vladvana 0:23d1f73bf130 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
vladvana 0:23d1f73bf130 214 {
vladvana 0:23d1f73bf130 215 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 216 register uint32_t __regfpexc __ASM("fpexc");
vladvana 0:23d1f73bf130 217 return(__regfpexc);
vladvana 0:23d1f73bf130 218 #else
vladvana 0:23d1f73bf130 219 return(0);
vladvana 0:23d1f73bf130 220 #endif
vladvana 0:23d1f73bf130 221 }
vladvana 0:23d1f73bf130 222
vladvana 0:23d1f73bf130 223
vladvana 0:23d1f73bf130 224 /** \brief Set FPEXC
vladvana 0:23d1f73bf130 225
vladvana 0:23d1f73bf130 226 This function assigns the given value to the Floating Point Exception Control register.
vladvana 0:23d1f73bf130 227
vladvana 0:23d1f73bf130 228 \param [in] fpscr Floating Point Exception Control value to set
vladvana 0:23d1f73bf130 229 */
vladvana 0:23d1f73bf130 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
vladvana 0:23d1f73bf130 231 {
vladvana 0:23d1f73bf130 232 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 233 register uint32_t __regfpexc __ASM("fpexc");
vladvana 0:23d1f73bf130 234 __regfpexc = (fpexc);
vladvana 0:23d1f73bf130 235 #endif
vladvana 0:23d1f73bf130 236 }
vladvana 0:23d1f73bf130 237
vladvana 0:23d1f73bf130 238 /** \brief Get CPACR
vladvana 0:23d1f73bf130 239
vladvana 0:23d1f73bf130 240 This function returns the current value of the Coprocessor Access Control register.
vladvana 0:23d1f73bf130 241
vladvana 0:23d1f73bf130 242 \return Coprocessor Access Control register value
vladvana 0:23d1f73bf130 243 */
vladvana 0:23d1f73bf130 244 __STATIC_INLINE uint32_t __get_CPACR(void)
vladvana 0:23d1f73bf130 245 {
vladvana 0:23d1f73bf130 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
vladvana 0:23d1f73bf130 247 return __regCPACR;
vladvana 0:23d1f73bf130 248 }
vladvana 0:23d1f73bf130 249
vladvana 0:23d1f73bf130 250 /** \brief Set CPACR
vladvana 0:23d1f73bf130 251
vladvana 0:23d1f73bf130 252 This function assigns the given value to the Coprocessor Access Control register.
vladvana 0:23d1f73bf130 253
vladvana 0:23d1f73bf130 254 \param [in] cpacr Coprocessor Acccess Control value to set
vladvana 0:23d1f73bf130 255 */
vladvana 0:23d1f73bf130 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
vladvana 0:23d1f73bf130 257 {
vladvana 0:23d1f73bf130 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
vladvana 0:23d1f73bf130 259 __regCPACR = cpacr;
vladvana 0:23d1f73bf130 260 __ISB();
vladvana 0:23d1f73bf130 261 }
vladvana 0:23d1f73bf130 262
vladvana 0:23d1f73bf130 263 /** \brief Get CBAR
vladvana 0:23d1f73bf130 264
vladvana 0:23d1f73bf130 265 This function returns the value of the Configuration Base Address register.
vladvana 0:23d1f73bf130 266
vladvana 0:23d1f73bf130 267 \return Configuration Base Address register value
vladvana 0:23d1f73bf130 268 */
vladvana 0:23d1f73bf130 269 __STATIC_INLINE uint32_t __get_CBAR() {
vladvana 0:23d1f73bf130 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
vladvana 0:23d1f73bf130 271 return(__regCBAR);
vladvana 0:23d1f73bf130 272 }
vladvana 0:23d1f73bf130 273
vladvana 0:23d1f73bf130 274 /** \brief Get TTBR0
vladvana 0:23d1f73bf130 275
vladvana 0:23d1f73bf130 276 This function returns the value of the Translation Table Base Register 0.
vladvana 0:23d1f73bf130 277
vladvana 0:23d1f73bf130 278 \return Translation Table Base Register 0 value
vladvana 0:23d1f73bf130 279 */
vladvana 0:23d1f73bf130 280 __STATIC_INLINE uint32_t __get_TTBR0() {
vladvana 0:23d1f73bf130 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
vladvana 0:23d1f73bf130 282 return(__regTTBR0);
vladvana 0:23d1f73bf130 283 }
vladvana 0:23d1f73bf130 284
vladvana 0:23d1f73bf130 285 /** \brief Set TTBR0
vladvana 0:23d1f73bf130 286
vladvana 0:23d1f73bf130 287 This function assigns the given value to the Translation Table Base Register 0.
vladvana 0:23d1f73bf130 288
vladvana 0:23d1f73bf130 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
vladvana 0:23d1f73bf130 290 */
vladvana 0:23d1f73bf130 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
vladvana 0:23d1f73bf130 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
vladvana 0:23d1f73bf130 293 __regTTBR0 = ttbr0;
vladvana 0:23d1f73bf130 294 __ISB();
vladvana 0:23d1f73bf130 295 }
vladvana 0:23d1f73bf130 296
vladvana 0:23d1f73bf130 297 /** \brief Get DACR
vladvana 0:23d1f73bf130 298
vladvana 0:23d1f73bf130 299 This function returns the value of the Domain Access Control Register.
vladvana 0:23d1f73bf130 300
vladvana 0:23d1f73bf130 301 \return Domain Access Control Register value
vladvana 0:23d1f73bf130 302 */
vladvana 0:23d1f73bf130 303 __STATIC_INLINE uint32_t __get_DACR() {
vladvana 0:23d1f73bf130 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
vladvana 0:23d1f73bf130 305 return(__regDACR);
vladvana 0:23d1f73bf130 306 }
vladvana 0:23d1f73bf130 307
vladvana 0:23d1f73bf130 308 /** \brief Set DACR
vladvana 0:23d1f73bf130 309
vladvana 0:23d1f73bf130 310 This function assigns the given value to the Domain Access Control Register.
vladvana 0:23d1f73bf130 311
vladvana 0:23d1f73bf130 312 \param [in] dacr Domain Access Control Register value to set
vladvana 0:23d1f73bf130 313 */
vladvana 0:23d1f73bf130 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
vladvana 0:23d1f73bf130 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
vladvana 0:23d1f73bf130 316 __regDACR = dacr;
vladvana 0:23d1f73bf130 317 __ISB();
vladvana 0:23d1f73bf130 318 }
vladvana 0:23d1f73bf130 319
vladvana 0:23d1f73bf130 320 /******************************** Cache and BTAC enable ****************************************************/
vladvana 0:23d1f73bf130 321
vladvana 0:23d1f73bf130 322 /** \brief Set SCTLR
vladvana 0:23d1f73bf130 323
vladvana 0:23d1f73bf130 324 This function assigns the given value to the System Control Register.
vladvana 0:23d1f73bf130 325
vladvana 0:23d1f73bf130 326 \param [in] sctlr System Control Register value to set
vladvana 0:23d1f73bf130 327 */
vladvana 0:23d1f73bf130 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
vladvana 0:23d1f73bf130 329 {
vladvana 0:23d1f73bf130 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
vladvana 0:23d1f73bf130 331 __regSCTLR = sctlr;
vladvana 0:23d1f73bf130 332 }
vladvana 0:23d1f73bf130 333
vladvana 0:23d1f73bf130 334 /** \brief Get SCTLR
vladvana 0:23d1f73bf130 335
vladvana 0:23d1f73bf130 336 This function returns the value of the System Control Register.
vladvana 0:23d1f73bf130 337
vladvana 0:23d1f73bf130 338 \return System Control Register value
vladvana 0:23d1f73bf130 339 */
vladvana 0:23d1f73bf130 340 __STATIC_INLINE uint32_t __get_SCTLR() {
vladvana 0:23d1f73bf130 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
vladvana 0:23d1f73bf130 342 return(__regSCTLR);
vladvana 0:23d1f73bf130 343 }
vladvana 0:23d1f73bf130 344
vladvana 0:23d1f73bf130 345 /** \brief Enable Caches
vladvana 0:23d1f73bf130 346
vladvana 0:23d1f73bf130 347 Enable Caches
vladvana 0:23d1f73bf130 348 */
vladvana 0:23d1f73bf130 349 __STATIC_INLINE void __enable_caches(void) {
vladvana 0:23d1f73bf130 350 // Set I bit 12 to enable I Cache
vladvana 0:23d1f73bf130 351 // Set C bit 2 to enable D Cache
vladvana 0:23d1f73bf130 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
vladvana 0:23d1f73bf130 353 }
vladvana 0:23d1f73bf130 354
vladvana 0:23d1f73bf130 355 /** \brief Disable Caches
vladvana 0:23d1f73bf130 356
vladvana 0:23d1f73bf130 357 Disable Caches
vladvana 0:23d1f73bf130 358 */
vladvana 0:23d1f73bf130 359 __STATIC_INLINE void __disable_caches(void) {
vladvana 0:23d1f73bf130 360 // Clear I bit 12 to disable I Cache
vladvana 0:23d1f73bf130 361 // Clear C bit 2 to disable D Cache
vladvana 0:23d1f73bf130 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
vladvana 0:23d1f73bf130 363 __ISB();
vladvana 0:23d1f73bf130 364 }
vladvana 0:23d1f73bf130 365
vladvana 0:23d1f73bf130 366 /** \brief Enable BTAC
vladvana 0:23d1f73bf130 367
vladvana 0:23d1f73bf130 368 Enable BTAC
vladvana 0:23d1f73bf130 369 */
vladvana 0:23d1f73bf130 370 __STATIC_INLINE void __enable_btac(void) {
vladvana 0:23d1f73bf130 371 // Set Z bit 11 to enable branch prediction
vladvana 0:23d1f73bf130 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
vladvana 0:23d1f73bf130 373 __ISB();
vladvana 0:23d1f73bf130 374 }
vladvana 0:23d1f73bf130 375
vladvana 0:23d1f73bf130 376 /** \brief Disable BTAC
vladvana 0:23d1f73bf130 377
vladvana 0:23d1f73bf130 378 Disable BTAC
vladvana 0:23d1f73bf130 379 */
vladvana 0:23d1f73bf130 380 __STATIC_INLINE void __disable_btac(void) {
vladvana 0:23d1f73bf130 381 // Clear Z bit 11 to disable branch prediction
vladvana 0:23d1f73bf130 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
vladvana 0:23d1f73bf130 383 }
vladvana 0:23d1f73bf130 384
vladvana 0:23d1f73bf130 385
vladvana 0:23d1f73bf130 386 /** \brief Enable MMU
vladvana 0:23d1f73bf130 387
vladvana 0:23d1f73bf130 388 Enable MMU
vladvana 0:23d1f73bf130 389 */
vladvana 0:23d1f73bf130 390 __STATIC_INLINE void __enable_mmu(void) {
vladvana 0:23d1f73bf130 391 // Set M bit 0 to enable the MMU
vladvana 0:23d1f73bf130 392 // Set AFE bit to enable simplified access permissions model
vladvana 0:23d1f73bf130 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
vladvana 0:23d1f73bf130 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
vladvana 0:23d1f73bf130 395 __ISB();
vladvana 0:23d1f73bf130 396 }
vladvana 0:23d1f73bf130 397
vladvana 0:23d1f73bf130 398 /** \brief Disable MMU
vladvana 0:23d1f73bf130 399
vladvana 0:23d1f73bf130 400 Disable MMU
vladvana 0:23d1f73bf130 401 */
vladvana 0:23d1f73bf130 402 __STATIC_INLINE void __disable_mmu(void) {
vladvana 0:23d1f73bf130 403 // Clear M bit 0 to disable the MMU
vladvana 0:23d1f73bf130 404 __set_SCTLR( __get_SCTLR() & ~1);
vladvana 0:23d1f73bf130 405 __ISB();
vladvana 0:23d1f73bf130 406 }
vladvana 0:23d1f73bf130 407
vladvana 0:23d1f73bf130 408 /******************************** TLB maintenance operations ************************************************/
vladvana 0:23d1f73bf130 409 /** \brief Invalidate the whole tlb
vladvana 0:23d1f73bf130 410
vladvana 0:23d1f73bf130 411 TLBIALL. Invalidate the whole tlb
vladvana 0:23d1f73bf130 412 */
vladvana 0:23d1f73bf130 413
vladvana 0:23d1f73bf130 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
vladvana 0:23d1f73bf130 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
vladvana 0:23d1f73bf130 416 __TLBIALL = 0;
vladvana 0:23d1f73bf130 417 __DSB();
vladvana 0:23d1f73bf130 418 __ISB();
vladvana 0:23d1f73bf130 419 }
vladvana 0:23d1f73bf130 420
vladvana 0:23d1f73bf130 421 /******************************** BTB maintenance operations ************************************************/
vladvana 0:23d1f73bf130 422 /** \brief Invalidate entire branch predictor array
vladvana 0:23d1f73bf130 423
vladvana 0:23d1f73bf130 424 BPIALL. Branch Predictor Invalidate All.
vladvana 0:23d1f73bf130 425 */
vladvana 0:23d1f73bf130 426
vladvana 0:23d1f73bf130 427 __STATIC_INLINE void __v7_inv_btac(void) {
vladvana 0:23d1f73bf130 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
vladvana 0:23d1f73bf130 429 __BPIALL = 0;
vladvana 0:23d1f73bf130 430 __DSB(); //ensure completion of the invalidation
vladvana 0:23d1f73bf130 431 __ISB(); //ensure instruction fetch path sees new state
vladvana 0:23d1f73bf130 432 }
vladvana 0:23d1f73bf130 433
vladvana 0:23d1f73bf130 434
vladvana 0:23d1f73bf130 435 /******************************** L1 cache operations ******************************************************/
vladvana 0:23d1f73bf130 436
vladvana 0:23d1f73bf130 437 /** \brief Invalidate the whole I$
vladvana 0:23d1f73bf130 438
vladvana 0:23d1f73bf130 439 ICIALLU. Instruction Cache Invalidate All to PoU
vladvana 0:23d1f73bf130 440 */
vladvana 0:23d1f73bf130 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
vladvana 0:23d1f73bf130 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
vladvana 0:23d1f73bf130 443 __ICIALLU = 0;
vladvana 0:23d1f73bf130 444 __DSB(); //ensure completion of the invalidation
vladvana 0:23d1f73bf130 445 __ISB(); //ensure instruction fetch path sees new I cache state
vladvana 0:23d1f73bf130 446 }
vladvana 0:23d1f73bf130 447
vladvana 0:23d1f73bf130 448 /** \brief Clean D$ by MVA
vladvana 0:23d1f73bf130 449
vladvana 0:23d1f73bf130 450 DCCMVAC. Data cache clean by MVA to PoC
vladvana 0:23d1f73bf130 451 */
vladvana 0:23d1f73bf130 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
vladvana 0:23d1f73bf130 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
vladvana 0:23d1f73bf130 454 __DCCMVAC = (uint32_t)va;
vladvana 0:23d1f73bf130 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vladvana 0:23d1f73bf130 456 }
vladvana 0:23d1f73bf130 457
vladvana 0:23d1f73bf130 458 /** \brief Invalidate D$ by MVA
vladvana 0:23d1f73bf130 459
vladvana 0:23d1f73bf130 460 DCIMVAC. Data cache invalidate by MVA to PoC
vladvana 0:23d1f73bf130 461 */
vladvana 0:23d1f73bf130 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
vladvana 0:23d1f73bf130 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
vladvana 0:23d1f73bf130 464 __DCIMVAC = (uint32_t)va;
vladvana 0:23d1f73bf130 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vladvana 0:23d1f73bf130 466 }
vladvana 0:23d1f73bf130 467
vladvana 0:23d1f73bf130 468 /** \brief Clean and Invalidate D$ by MVA
vladvana 0:23d1f73bf130 469
vladvana 0:23d1f73bf130 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
vladvana 0:23d1f73bf130 471 */
vladvana 0:23d1f73bf130 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
vladvana 0:23d1f73bf130 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
vladvana 0:23d1f73bf130 474 __DCCIMVAC = (uint32_t)va;
vladvana 0:23d1f73bf130 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vladvana 0:23d1f73bf130 476 }
vladvana 0:23d1f73bf130 477
vladvana 0:23d1f73bf130 478 /** \brief Clean and Invalidate the entire data or unified cache
vladvana 0:23d1f73bf130 479
vladvana 0:23d1f73bf130 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
vladvana 0:23d1f73bf130 481 */
vladvana 0:23d1f73bf130 482 #pragma push
vladvana 0:23d1f73bf130 483 #pragma arm
vladvana 0:23d1f73bf130 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
vladvana 0:23d1f73bf130 485 ARM
vladvana 0:23d1f73bf130 486
vladvana 0:23d1f73bf130 487 PUSH {R4-R11}
vladvana 0:23d1f73bf130 488
vladvana 0:23d1f73bf130 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
vladvana 0:23d1f73bf130 490 ANDS R3, R6, #0x07000000 // Extract coherency level
vladvana 0:23d1f73bf130 491 MOV R3, R3, LSR #23 // Total cache levels << 1
vladvana 0:23d1f73bf130 492 BEQ Finished // If 0, no need to clean
vladvana 0:23d1f73bf130 493
vladvana 0:23d1f73bf130 494 MOV R10, #0 // R10 holds current cache level << 1
vladvana 0:23d1f73bf130 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
vladvana 0:23d1f73bf130 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
vladvana 0:23d1f73bf130 497 AND R1, R1, #7 // Isolate those lower 3 bits
vladvana 0:23d1f73bf130 498 CMP R1, #2
vladvana 0:23d1f73bf130 499 BLT Skip // No cache or only instruction cache at this level
vladvana 0:23d1f73bf130 500
vladvana 0:23d1f73bf130 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
vladvana 0:23d1f73bf130 502 ISB // ISB to sync the change to the CacheSizeID reg
vladvana 0:23d1f73bf130 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
vladvana 0:23d1f73bf130 504 AND R2, R1, #7 // Extract the line length field
vladvana 0:23d1f73bf130 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
vladvana 0:23d1f73bf130 506 LDR R4, =0x3FF
vladvana 0:23d1f73bf130 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
vladvana 0:23d1f73bf130 508 CLZ R5, R4 // R5 is the bit position of the way size increment
vladvana 0:23d1f73bf130 509 LDR R7, =0x7FFF
vladvana 0:23d1f73bf130 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
vladvana 0:23d1f73bf130 511
vladvana 0:23d1f73bf130 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
vladvana 0:23d1f73bf130 513
vladvana 0:23d1f73bf130 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
vladvana 0:23d1f73bf130 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
vladvana 0:23d1f73bf130 516 CMP R0, #0
vladvana 0:23d1f73bf130 517 BNE Dccsw
vladvana 0:23d1f73bf130 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
vladvana 0:23d1f73bf130 519 B cont
vladvana 0:23d1f73bf130 520 Dccsw CMP R0, #1
vladvana 0:23d1f73bf130 521 BNE Dccisw
vladvana 0:23d1f73bf130 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
vladvana 0:23d1f73bf130 523 B cont
vladvana 0:23d1f73bf130 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
vladvana 0:23d1f73bf130 525 cont SUBS R9, R9, #1 // Decrement the Way number
vladvana 0:23d1f73bf130 526 BGE Loop3
vladvana 0:23d1f73bf130 527 SUBS R7, R7, #1 // Decrement the Set number
vladvana 0:23d1f73bf130 528 BGE Loop2
vladvana 0:23d1f73bf130 529 Skip ADD R10, R10, #2 // Increment the cache number
vladvana 0:23d1f73bf130 530 CMP R3, R10
vladvana 0:23d1f73bf130 531 BGT Loop1
vladvana 0:23d1f73bf130 532
vladvana 0:23d1f73bf130 533 Finished
vladvana 0:23d1f73bf130 534 DSB
vladvana 0:23d1f73bf130 535 POP {R4-R11}
vladvana 0:23d1f73bf130 536 BX lr
vladvana 0:23d1f73bf130 537
vladvana 0:23d1f73bf130 538 }
vladvana 0:23d1f73bf130 539 #pragma pop
vladvana 0:23d1f73bf130 540
vladvana 0:23d1f73bf130 541
vladvana 0:23d1f73bf130 542 /** \brief Invalidate the whole D$
vladvana 0:23d1f73bf130 543
vladvana 0:23d1f73bf130 544 DCISW. Invalidate by Set/Way
vladvana 0:23d1f73bf130 545 */
vladvana 0:23d1f73bf130 546
vladvana 0:23d1f73bf130 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
vladvana 0:23d1f73bf130 548 __v7_all_cache(0);
vladvana 0:23d1f73bf130 549 }
vladvana 0:23d1f73bf130 550
vladvana 0:23d1f73bf130 551 /** \brief Clean the whole D$
vladvana 0:23d1f73bf130 552
vladvana 0:23d1f73bf130 553 DCCSW. Clean by Set/Way
vladvana 0:23d1f73bf130 554 */
vladvana 0:23d1f73bf130 555
vladvana 0:23d1f73bf130 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
vladvana 0:23d1f73bf130 557 __v7_all_cache(1);
vladvana 0:23d1f73bf130 558 }
vladvana 0:23d1f73bf130 559
vladvana 0:23d1f73bf130 560 /** \brief Clean and invalidate the whole D$
vladvana 0:23d1f73bf130 561
vladvana 0:23d1f73bf130 562 DCCISW. Clean and Invalidate by Set/Way
vladvana 0:23d1f73bf130 563 */
vladvana 0:23d1f73bf130 564
vladvana 0:23d1f73bf130 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
vladvana 0:23d1f73bf130 566 __v7_all_cache(2);
vladvana 0:23d1f73bf130 567 }
vladvana 0:23d1f73bf130 568
vladvana 0:23d1f73bf130 569 #include "core_ca_mmu.h"
vladvana 0:23d1f73bf130 570
vladvana 0:23d1f73bf130 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
vladvana 0:23d1f73bf130 572
vladvana 0:23d1f73bf130 573 #error IAR Compiler support not implemented for Cortex-A
vladvana 0:23d1f73bf130 574
vladvana 0:23d1f73bf130 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
vladvana 0:23d1f73bf130 576 /* GNU gcc specific functions */
vladvana 0:23d1f73bf130 577
vladvana 0:23d1f73bf130 578 #define MODE_USR 0x10
vladvana 0:23d1f73bf130 579 #define MODE_FIQ 0x11
vladvana 0:23d1f73bf130 580 #define MODE_IRQ 0x12
vladvana 0:23d1f73bf130 581 #define MODE_SVC 0x13
vladvana 0:23d1f73bf130 582 #define MODE_MON 0x16
vladvana 0:23d1f73bf130 583 #define MODE_ABT 0x17
vladvana 0:23d1f73bf130 584 #define MODE_HYP 0x1A
vladvana 0:23d1f73bf130 585 #define MODE_UND 0x1B
vladvana 0:23d1f73bf130 586 #define MODE_SYS 0x1F
vladvana 0:23d1f73bf130 587
vladvana 0:23d1f73bf130 588
vladvana 0:23d1f73bf130 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
vladvana 0:23d1f73bf130 590 {
vladvana 0:23d1f73bf130 591 __ASM volatile ("cpsie i");
vladvana 0:23d1f73bf130 592 }
vladvana 0:23d1f73bf130 593
vladvana 0:23d1f73bf130 594 /** \brief Disable IRQ Interrupts
vladvana 0:23d1f73bf130 595
vladvana 0:23d1f73bf130 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
vladvana 0:23d1f73bf130 597 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 598 */
vladvana 0:23d1f73bf130 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
vladvana 0:23d1f73bf130 600 {
vladvana 0:23d1f73bf130 601 uint32_t result;
vladvana 0:23d1f73bf130 602
vladvana 0:23d1f73bf130 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
vladvana 0:23d1f73bf130 604 __ASM volatile ("cpsid i");
vladvana 0:23d1f73bf130 605 return(result & 0x80);
vladvana 0:23d1f73bf130 606 }
vladvana 0:23d1f73bf130 607
vladvana 0:23d1f73bf130 608
vladvana 0:23d1f73bf130 609 /** \brief Get APSR Register
vladvana 0:23d1f73bf130 610
vladvana 0:23d1f73bf130 611 This function returns the content of the APSR Register.
vladvana 0:23d1f73bf130 612
vladvana 0:23d1f73bf130 613 \return APSR Register value
vladvana 0:23d1f73bf130 614 */
vladvana 0:23d1f73bf130 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
vladvana 0:23d1f73bf130 616 {
vladvana 0:23d1f73bf130 617 #if 1
vladvana 0:23d1f73bf130 618 register uint32_t __regAPSR;
vladvana 0:23d1f73bf130 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
vladvana 0:23d1f73bf130 620 #else
vladvana 0:23d1f73bf130 621 register uint32_t __regAPSR __ASM("apsr");
vladvana 0:23d1f73bf130 622 #endif
vladvana 0:23d1f73bf130 623 return(__regAPSR);
vladvana 0:23d1f73bf130 624 }
vladvana 0:23d1f73bf130 625
vladvana 0:23d1f73bf130 626
vladvana 0:23d1f73bf130 627 /** \brief Get CPSR Register
vladvana 0:23d1f73bf130 628
vladvana 0:23d1f73bf130 629 This function returns the content of the CPSR Register.
vladvana 0:23d1f73bf130 630
vladvana 0:23d1f73bf130 631 \return CPSR Register value
vladvana 0:23d1f73bf130 632 */
vladvana 0:23d1f73bf130 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
vladvana 0:23d1f73bf130 634 {
vladvana 0:23d1f73bf130 635 #if 1
vladvana 0:23d1f73bf130 636 register uint32_t __regCPSR;
vladvana 0:23d1f73bf130 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
vladvana 0:23d1f73bf130 638 #else
vladvana 0:23d1f73bf130 639 register uint32_t __regCPSR __ASM("cpsr");
vladvana 0:23d1f73bf130 640 #endif
vladvana 0:23d1f73bf130 641 return(__regCPSR);
vladvana 0:23d1f73bf130 642 }
vladvana 0:23d1f73bf130 643
vladvana 0:23d1f73bf130 644 #if 0
vladvana 0:23d1f73bf130 645 /** \brief Set Stack Pointer
vladvana 0:23d1f73bf130 646
vladvana 0:23d1f73bf130 647 This function assigns the given value to the current stack pointer.
vladvana 0:23d1f73bf130 648
vladvana 0:23d1f73bf130 649 \param [in] topOfStack Stack Pointer value to set
vladvana 0:23d1f73bf130 650 */
vladvana 0:23d1f73bf130 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
vladvana 0:23d1f73bf130 652 {
vladvana 0:23d1f73bf130 653 register uint32_t __regSP __ASM("sp");
vladvana 0:23d1f73bf130 654 __regSP = topOfStack;
vladvana 0:23d1f73bf130 655 }
vladvana 0:23d1f73bf130 656 #endif
vladvana 0:23d1f73bf130 657
vladvana 0:23d1f73bf130 658 /** \brief Get link register
vladvana 0:23d1f73bf130 659
vladvana 0:23d1f73bf130 660 This function returns the value of the link register
vladvana 0:23d1f73bf130 661
vladvana 0:23d1f73bf130 662 \return Value of link register
vladvana 0:23d1f73bf130 663 */
vladvana 0:23d1f73bf130 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
vladvana 0:23d1f73bf130 665 {
vladvana 0:23d1f73bf130 666 register uint32_t __reglr __ASM("lr");
vladvana 0:23d1f73bf130 667 return(__reglr);
vladvana 0:23d1f73bf130 668 }
vladvana 0:23d1f73bf130 669
vladvana 0:23d1f73bf130 670 #if 0
vladvana 0:23d1f73bf130 671 /** \brief Set link register
vladvana 0:23d1f73bf130 672
vladvana 0:23d1f73bf130 673 This function sets the value of the link register
vladvana 0:23d1f73bf130 674
vladvana 0:23d1f73bf130 675 \param [in] lr LR value to set
vladvana 0:23d1f73bf130 676 */
vladvana 0:23d1f73bf130 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
vladvana 0:23d1f73bf130 678 {
vladvana 0:23d1f73bf130 679 register uint32_t __reglr __ASM("lr");
vladvana 0:23d1f73bf130 680 __reglr = lr;
vladvana 0:23d1f73bf130 681 }
vladvana 0:23d1f73bf130 682 #endif
vladvana 0:23d1f73bf130 683
vladvana 0:23d1f73bf130 684 /** \brief Set Process Stack Pointer
vladvana 0:23d1f73bf130 685
vladvana 0:23d1f73bf130 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
vladvana 0:23d1f73bf130 687
vladvana 0:23d1f73bf130 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
vladvana 0:23d1f73bf130 689 */
vladvana 0:23d1f73bf130 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
vladvana 0:23d1f73bf130 691 {
vladvana 0:23d1f73bf130 692 __asm__ volatile (
vladvana 0:23d1f73bf130 693 ".ARM;"
vladvana 0:23d1f73bf130 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
vladvana 0:23d1f73bf130 695
vladvana 0:23d1f73bf130 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
vladvana 0:23d1f73bf130 697 "MRS R1, CPSR;"
vladvana 0:23d1f73bf130 698 "CPS %0;" /* ;no effect in USR mode */
vladvana 0:23d1f73bf130 699 "MOV SP, R0;"
vladvana 0:23d1f73bf130 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
vladvana 0:23d1f73bf130 701 "ISB;"
vladvana 0:23d1f73bf130 702 //"BX LR;"
vladvana 0:23d1f73bf130 703 :
vladvana 0:23d1f73bf130 704 : "i"(MODE_SYS)
vladvana 0:23d1f73bf130 705 : "r0", "r1");
vladvana 0:23d1f73bf130 706 return;
vladvana 0:23d1f73bf130 707 }
vladvana 0:23d1f73bf130 708
vladvana 0:23d1f73bf130 709 /** \brief Set User Mode
vladvana 0:23d1f73bf130 710
vladvana 0:23d1f73bf130 711 This function changes the processor state to User Mode
vladvana 0:23d1f73bf130 712 */
vladvana 0:23d1f73bf130 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
vladvana 0:23d1f73bf130 714 {
vladvana 0:23d1f73bf130 715 __asm__ volatile (
vladvana 0:23d1f73bf130 716 ".ARM;"
vladvana 0:23d1f73bf130 717
vladvana 0:23d1f73bf130 718 "CPS %0;"
vladvana 0:23d1f73bf130 719 //"BX LR;"
vladvana 0:23d1f73bf130 720 :
vladvana 0:23d1f73bf130 721 : "i"(MODE_USR)
vladvana 0:23d1f73bf130 722 : );
vladvana 0:23d1f73bf130 723 return;
vladvana 0:23d1f73bf130 724 }
vladvana 0:23d1f73bf130 725
vladvana 0:23d1f73bf130 726
vladvana 0:23d1f73bf130 727 /** \brief Enable FIQ
vladvana 0:23d1f73bf130 728
vladvana 0:23d1f73bf130 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
vladvana 0:23d1f73bf130 730 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 731 */
vladvana 0:23d1f73bf130 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
vladvana 0:23d1f73bf130 733
vladvana 0:23d1f73bf130 734
vladvana 0:23d1f73bf130 735 /** \brief Disable FIQ
vladvana 0:23d1f73bf130 736
vladvana 0:23d1f73bf130 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
vladvana 0:23d1f73bf130 738 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 739 */
vladvana 0:23d1f73bf130 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
vladvana 0:23d1f73bf130 741
vladvana 0:23d1f73bf130 742
vladvana 0:23d1f73bf130 743 /** \brief Get FPSCR
vladvana 0:23d1f73bf130 744
vladvana 0:23d1f73bf130 745 This function returns the current value of the Floating Point Status/Control register.
vladvana 0:23d1f73bf130 746
vladvana 0:23d1f73bf130 747 \return Floating Point Status/Control register value
vladvana 0:23d1f73bf130 748 */
vladvana 0:23d1f73bf130 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
vladvana 0:23d1f73bf130 750 {
vladvana 0:23d1f73bf130 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vladvana 0:23d1f73bf130 752 #if 1
vladvana 0:23d1f73bf130 753 uint32_t result;
vladvana 0:23d1f73bf130 754
vladvana 0:23d1f73bf130 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
vladvana 0:23d1f73bf130 756 return (result);
vladvana 0:23d1f73bf130 757 #else
vladvana 0:23d1f73bf130 758 register uint32_t __regfpscr __ASM("fpscr");
vladvana 0:23d1f73bf130 759 return(__regfpscr);
vladvana 0:23d1f73bf130 760 #endif
vladvana 0:23d1f73bf130 761 #else
vladvana 0:23d1f73bf130 762 return(0);
vladvana 0:23d1f73bf130 763 #endif
vladvana 0:23d1f73bf130 764 }
vladvana 0:23d1f73bf130 765
vladvana 0:23d1f73bf130 766
vladvana 0:23d1f73bf130 767 /** \brief Set FPSCR
vladvana 0:23d1f73bf130 768
vladvana 0:23d1f73bf130 769 This function assigns the given value to the Floating Point Status/Control register.
vladvana 0:23d1f73bf130 770
vladvana 0:23d1f73bf130 771 \param [in] fpscr Floating Point Status/Control value to set
vladvana 0:23d1f73bf130 772 */
vladvana 0:23d1f73bf130 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
vladvana 0:23d1f73bf130 774 {
vladvana 0:23d1f73bf130 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vladvana 0:23d1f73bf130 776 #if 1
vladvana 0:23d1f73bf130 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
vladvana 0:23d1f73bf130 778 #else
vladvana 0:23d1f73bf130 779 register uint32_t __regfpscr __ASM("fpscr");
vladvana 0:23d1f73bf130 780 __regfpscr = (fpscr);
vladvana 0:23d1f73bf130 781 #endif
vladvana 0:23d1f73bf130 782 #endif
vladvana 0:23d1f73bf130 783 }
vladvana 0:23d1f73bf130 784
vladvana 0:23d1f73bf130 785 /** \brief Get FPEXC
vladvana 0:23d1f73bf130 786
vladvana 0:23d1f73bf130 787 This function returns the current value of the Floating Point Exception Control register.
vladvana 0:23d1f73bf130 788
vladvana 0:23d1f73bf130 789 \return Floating Point Exception Control register value
vladvana 0:23d1f73bf130 790 */
vladvana 0:23d1f73bf130 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
vladvana 0:23d1f73bf130 792 {
vladvana 0:23d1f73bf130 793 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 794 #if 1
vladvana 0:23d1f73bf130 795 uint32_t result;
vladvana 0:23d1f73bf130 796
vladvana 0:23d1f73bf130 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
vladvana 0:23d1f73bf130 798 return (result);
vladvana 0:23d1f73bf130 799 #else
vladvana 0:23d1f73bf130 800 register uint32_t __regfpexc __ASM("fpexc");
vladvana 0:23d1f73bf130 801 return(__regfpexc);
vladvana 0:23d1f73bf130 802 #endif
vladvana 0:23d1f73bf130 803 #else
vladvana 0:23d1f73bf130 804 return(0);
vladvana 0:23d1f73bf130 805 #endif
vladvana 0:23d1f73bf130 806 }
vladvana 0:23d1f73bf130 807
vladvana 0:23d1f73bf130 808
vladvana 0:23d1f73bf130 809 /** \brief Set FPEXC
vladvana 0:23d1f73bf130 810
vladvana 0:23d1f73bf130 811 This function assigns the given value to the Floating Point Exception Control register.
vladvana 0:23d1f73bf130 812
vladvana 0:23d1f73bf130 813 \param [in] fpscr Floating Point Exception Control value to set
vladvana 0:23d1f73bf130 814 */
vladvana 0:23d1f73bf130 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
vladvana 0:23d1f73bf130 816 {
vladvana 0:23d1f73bf130 817 #if (__FPU_PRESENT == 1)
vladvana 0:23d1f73bf130 818 #if 1
vladvana 0:23d1f73bf130 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
vladvana 0:23d1f73bf130 820 #else
vladvana 0:23d1f73bf130 821 register uint32_t __regfpexc __ASM("fpexc");
vladvana 0:23d1f73bf130 822 __regfpexc = (fpexc);
vladvana 0:23d1f73bf130 823 #endif
vladvana 0:23d1f73bf130 824 #endif
vladvana 0:23d1f73bf130 825 }
vladvana 0:23d1f73bf130 826
vladvana 0:23d1f73bf130 827 /** \brief Get CPACR
vladvana 0:23d1f73bf130 828
vladvana 0:23d1f73bf130 829 This function returns the current value of the Coprocessor Access Control register.
vladvana 0:23d1f73bf130 830
vladvana 0:23d1f73bf130 831 \return Coprocessor Access Control register value
vladvana 0:23d1f73bf130 832 */
vladvana 0:23d1f73bf130 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
vladvana 0:23d1f73bf130 834 {
vladvana 0:23d1f73bf130 835 #if 1
vladvana 0:23d1f73bf130 836 register uint32_t __regCPACR;
vladvana 0:23d1f73bf130 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
vladvana 0:23d1f73bf130 838 #else
vladvana 0:23d1f73bf130 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
vladvana 0:23d1f73bf130 840 #endif
vladvana 0:23d1f73bf130 841 return __regCPACR;
vladvana 0:23d1f73bf130 842 }
vladvana 0:23d1f73bf130 843
vladvana 0:23d1f73bf130 844 /** \brief Set CPACR
vladvana 0:23d1f73bf130 845
vladvana 0:23d1f73bf130 846 This function assigns the given value to the Coprocessor Access Control register.
vladvana 0:23d1f73bf130 847
vladvana 0:23d1f73bf130 848 \param [in] cpacr Coprocessor Acccess Control value to set
vladvana 0:23d1f73bf130 849 */
vladvana 0:23d1f73bf130 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
vladvana 0:23d1f73bf130 851 {
vladvana 0:23d1f73bf130 852 #if 1
vladvana 0:23d1f73bf130 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
vladvana 0:23d1f73bf130 854 #else
vladvana 0:23d1f73bf130 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
vladvana 0:23d1f73bf130 856 __regCPACR = cpacr;
vladvana 0:23d1f73bf130 857 #endif
vladvana 0:23d1f73bf130 858 __ISB();
vladvana 0:23d1f73bf130 859 }
vladvana 0:23d1f73bf130 860
vladvana 0:23d1f73bf130 861 /** \brief Get CBAR
vladvana 0:23d1f73bf130 862
vladvana 0:23d1f73bf130 863 This function returns the value of the Configuration Base Address register.
vladvana 0:23d1f73bf130 864
vladvana 0:23d1f73bf130 865 \return Configuration Base Address register value
vladvana 0:23d1f73bf130 866 */
vladvana 0:23d1f73bf130 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
vladvana 0:23d1f73bf130 868 #if 1
vladvana 0:23d1f73bf130 869 register uint32_t __regCBAR;
vladvana 0:23d1f73bf130 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
vladvana 0:23d1f73bf130 871 #else
vladvana 0:23d1f73bf130 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
vladvana 0:23d1f73bf130 873 #endif
vladvana 0:23d1f73bf130 874 return(__regCBAR);
vladvana 0:23d1f73bf130 875 }
vladvana 0:23d1f73bf130 876
vladvana 0:23d1f73bf130 877 /** \brief Get TTBR0
vladvana 0:23d1f73bf130 878
vladvana 0:23d1f73bf130 879 This function returns the value of the Translation Table Base Register 0.
vladvana 0:23d1f73bf130 880
vladvana 0:23d1f73bf130 881 \return Translation Table Base Register 0 value
vladvana 0:23d1f73bf130 882 */
vladvana 0:23d1f73bf130 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
vladvana 0:23d1f73bf130 884 #if 1
vladvana 0:23d1f73bf130 885 register uint32_t __regTTBR0;
vladvana 0:23d1f73bf130 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
vladvana 0:23d1f73bf130 887 #else
vladvana 0:23d1f73bf130 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
vladvana 0:23d1f73bf130 889 #endif
vladvana 0:23d1f73bf130 890 return(__regTTBR0);
vladvana 0:23d1f73bf130 891 }
vladvana 0:23d1f73bf130 892
vladvana 0:23d1f73bf130 893 /** \brief Set TTBR0
vladvana 0:23d1f73bf130 894
vladvana 0:23d1f73bf130 895 This function assigns the given value to the Translation Table Base Register 0.
vladvana 0:23d1f73bf130 896
vladvana 0:23d1f73bf130 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
vladvana 0:23d1f73bf130 898 */
vladvana 0:23d1f73bf130 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
vladvana 0:23d1f73bf130 900 #if 1
vladvana 0:23d1f73bf130 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
vladvana 0:23d1f73bf130 902 #else
vladvana 0:23d1f73bf130 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
vladvana 0:23d1f73bf130 904 __regTTBR0 = ttbr0;
vladvana 0:23d1f73bf130 905 #endif
vladvana 0:23d1f73bf130 906 __ISB();
vladvana 0:23d1f73bf130 907 }
vladvana 0:23d1f73bf130 908
vladvana 0:23d1f73bf130 909 /** \brief Get DACR
vladvana 0:23d1f73bf130 910
vladvana 0:23d1f73bf130 911 This function returns the value of the Domain Access Control Register.
vladvana 0:23d1f73bf130 912
vladvana 0:23d1f73bf130 913 \return Domain Access Control Register value
vladvana 0:23d1f73bf130 914 */
vladvana 0:23d1f73bf130 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
vladvana 0:23d1f73bf130 916 #if 1
vladvana 0:23d1f73bf130 917 register uint32_t __regDACR;
vladvana 0:23d1f73bf130 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
vladvana 0:23d1f73bf130 919 #else
vladvana 0:23d1f73bf130 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
vladvana 0:23d1f73bf130 921 #endif
vladvana 0:23d1f73bf130 922 return(__regDACR);
vladvana 0:23d1f73bf130 923 }
vladvana 0:23d1f73bf130 924
vladvana 0:23d1f73bf130 925 /** \brief Set DACR
vladvana 0:23d1f73bf130 926
vladvana 0:23d1f73bf130 927 This function assigns the given value to the Domain Access Control Register.
vladvana 0:23d1f73bf130 928
vladvana 0:23d1f73bf130 929 \param [in] dacr Domain Access Control Register value to set
vladvana 0:23d1f73bf130 930 */
vladvana 0:23d1f73bf130 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
vladvana 0:23d1f73bf130 932 #if 1
vladvana 0:23d1f73bf130 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
vladvana 0:23d1f73bf130 934 #else
vladvana 0:23d1f73bf130 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
vladvana 0:23d1f73bf130 936 __regDACR = dacr;
vladvana 0:23d1f73bf130 937 #endif
vladvana 0:23d1f73bf130 938 __ISB();
vladvana 0:23d1f73bf130 939 }
vladvana 0:23d1f73bf130 940
vladvana 0:23d1f73bf130 941 /******************************** Cache and BTAC enable ****************************************************/
vladvana 0:23d1f73bf130 942
vladvana 0:23d1f73bf130 943 /** \brief Set SCTLR
vladvana 0:23d1f73bf130 944
vladvana 0:23d1f73bf130 945 This function assigns the given value to the System Control Register.
vladvana 0:23d1f73bf130 946
vladvana 0:23d1f73bf130 947 \param [in] sctlr System Control Register value to set
vladvana 0:23d1f73bf130 948 */
vladvana 0:23d1f73bf130 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
vladvana 0:23d1f73bf130 950 {
vladvana 0:23d1f73bf130 951 #if 1
vladvana 0:23d1f73bf130 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
vladvana 0:23d1f73bf130 953 #else
vladvana 0:23d1f73bf130 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
vladvana 0:23d1f73bf130 955 __regSCTLR = sctlr;
vladvana 0:23d1f73bf130 956 #endif
vladvana 0:23d1f73bf130 957 }
vladvana 0:23d1f73bf130 958
vladvana 0:23d1f73bf130 959 /** \brief Get SCTLR
vladvana 0:23d1f73bf130 960
vladvana 0:23d1f73bf130 961 This function returns the value of the System Control Register.
vladvana 0:23d1f73bf130 962
vladvana 0:23d1f73bf130 963 \return System Control Register value
vladvana 0:23d1f73bf130 964 */
vladvana 0:23d1f73bf130 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
vladvana 0:23d1f73bf130 966 #if 1
vladvana 0:23d1f73bf130 967 register uint32_t __regSCTLR;
vladvana 0:23d1f73bf130 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
vladvana 0:23d1f73bf130 969 #else
vladvana 0:23d1f73bf130 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
vladvana 0:23d1f73bf130 971 #endif
vladvana 0:23d1f73bf130 972 return(__regSCTLR);
vladvana 0:23d1f73bf130 973 }
vladvana 0:23d1f73bf130 974
vladvana 0:23d1f73bf130 975 /** \brief Enable Caches
vladvana 0:23d1f73bf130 976
vladvana 0:23d1f73bf130 977 Enable Caches
vladvana 0:23d1f73bf130 978 */
vladvana 0:23d1f73bf130 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
vladvana 0:23d1f73bf130 980 // Set I bit 12 to enable I Cache
vladvana 0:23d1f73bf130 981 // Set C bit 2 to enable D Cache
vladvana 0:23d1f73bf130 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
vladvana 0:23d1f73bf130 983 }
vladvana 0:23d1f73bf130 984
vladvana 0:23d1f73bf130 985 /** \brief Disable Caches
vladvana 0:23d1f73bf130 986
vladvana 0:23d1f73bf130 987 Disable Caches
vladvana 0:23d1f73bf130 988 */
vladvana 0:23d1f73bf130 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
vladvana 0:23d1f73bf130 990 // Clear I bit 12 to disable I Cache
vladvana 0:23d1f73bf130 991 // Clear C bit 2 to disable D Cache
vladvana 0:23d1f73bf130 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
vladvana 0:23d1f73bf130 993 __ISB();
vladvana 0:23d1f73bf130 994 }
vladvana 0:23d1f73bf130 995
vladvana 0:23d1f73bf130 996 /** \brief Enable BTAC
vladvana 0:23d1f73bf130 997
vladvana 0:23d1f73bf130 998 Enable BTAC
vladvana 0:23d1f73bf130 999 */
vladvana 0:23d1f73bf130 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
vladvana 0:23d1f73bf130 1001 // Set Z bit 11 to enable branch prediction
vladvana 0:23d1f73bf130 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
vladvana 0:23d1f73bf130 1003 __ISB();
vladvana 0:23d1f73bf130 1004 }
vladvana 0:23d1f73bf130 1005
vladvana 0:23d1f73bf130 1006 /** \brief Disable BTAC
vladvana 0:23d1f73bf130 1007
vladvana 0:23d1f73bf130 1008 Disable BTAC
vladvana 0:23d1f73bf130 1009 */
vladvana 0:23d1f73bf130 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
vladvana 0:23d1f73bf130 1011 // Clear Z bit 11 to disable branch prediction
vladvana 0:23d1f73bf130 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
vladvana 0:23d1f73bf130 1013 }
vladvana 0:23d1f73bf130 1014
vladvana 0:23d1f73bf130 1015
vladvana 0:23d1f73bf130 1016 /** \brief Enable MMU
vladvana 0:23d1f73bf130 1017
vladvana 0:23d1f73bf130 1018 Enable MMU
vladvana 0:23d1f73bf130 1019 */
vladvana 0:23d1f73bf130 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
vladvana 0:23d1f73bf130 1021 // Set M bit 0 to enable the MMU
vladvana 0:23d1f73bf130 1022 // Set AFE bit to enable simplified access permissions model
vladvana 0:23d1f73bf130 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
vladvana 0:23d1f73bf130 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
vladvana 0:23d1f73bf130 1025 __ISB();
vladvana 0:23d1f73bf130 1026 }
vladvana 0:23d1f73bf130 1027
vladvana 0:23d1f73bf130 1028 /** \brief Disable MMU
vladvana 0:23d1f73bf130 1029
vladvana 0:23d1f73bf130 1030 Disable MMU
vladvana 0:23d1f73bf130 1031 */
vladvana 0:23d1f73bf130 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
vladvana 0:23d1f73bf130 1033 // Clear M bit 0 to disable the MMU
vladvana 0:23d1f73bf130 1034 __set_SCTLR( __get_SCTLR() & ~1);
vladvana 0:23d1f73bf130 1035 __ISB();
vladvana 0:23d1f73bf130 1036 }
vladvana 0:23d1f73bf130 1037
vladvana 0:23d1f73bf130 1038 /******************************** TLB maintenance operations ************************************************/
vladvana 0:23d1f73bf130 1039 /** \brief Invalidate the whole tlb
vladvana 0:23d1f73bf130 1040
vladvana 0:23d1f73bf130 1041 TLBIALL. Invalidate the whole tlb
vladvana 0:23d1f73bf130 1042 */
vladvana 0:23d1f73bf130 1043
vladvana 0:23d1f73bf130 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
vladvana 0:23d1f73bf130 1045 #if 1
vladvana 0:23d1f73bf130 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
vladvana 0:23d1f73bf130 1047 #else
vladvana 0:23d1f73bf130 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
vladvana 0:23d1f73bf130 1049 __TLBIALL = 0;
vladvana 0:23d1f73bf130 1050 #endif
vladvana 0:23d1f73bf130 1051 __DSB();
vladvana 0:23d1f73bf130 1052 __ISB();
vladvana 0:23d1f73bf130 1053 }
vladvana 0:23d1f73bf130 1054
vladvana 0:23d1f73bf130 1055 /******************************** BTB maintenance operations ************************************************/
vladvana 0:23d1f73bf130 1056 /** \brief Invalidate entire branch predictor array
vladvana 0:23d1f73bf130 1057
vladvana 0:23d1f73bf130 1058 BPIALL. Branch Predictor Invalidate All.
vladvana 0:23d1f73bf130 1059 */
vladvana 0:23d1f73bf130 1060
vladvana 0:23d1f73bf130 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
vladvana 0:23d1f73bf130 1062 #if 1
vladvana 0:23d1f73bf130 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
vladvana 0:23d1f73bf130 1064 #else
vladvana 0:23d1f73bf130 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
vladvana 0:23d1f73bf130 1066 __BPIALL = 0;
vladvana 0:23d1f73bf130 1067 #endif
vladvana 0:23d1f73bf130 1068 __DSB(); //ensure completion of the invalidation
vladvana 0:23d1f73bf130 1069 __ISB(); //ensure instruction fetch path sees new state
vladvana 0:23d1f73bf130 1070 }
vladvana 0:23d1f73bf130 1071
vladvana 0:23d1f73bf130 1072
vladvana 0:23d1f73bf130 1073 /******************************** L1 cache operations ******************************************************/
vladvana 0:23d1f73bf130 1074
vladvana 0:23d1f73bf130 1075 /** \brief Invalidate the whole I$
vladvana 0:23d1f73bf130 1076
vladvana 0:23d1f73bf130 1077 ICIALLU. Instruction Cache Invalidate All to PoU
vladvana 0:23d1f73bf130 1078 */
vladvana 0:23d1f73bf130 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
vladvana 0:23d1f73bf130 1080 #if 1
vladvana 0:23d1f73bf130 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
vladvana 0:23d1f73bf130 1082 #else
vladvana 0:23d1f73bf130 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
vladvana 0:23d1f73bf130 1084 __ICIALLU = 0;
vladvana 0:23d1f73bf130 1085 #endif
vladvana 0:23d1f73bf130 1086 __DSB(); //ensure completion of the invalidation
vladvana 0:23d1f73bf130 1087 __ISB(); //ensure instruction fetch path sees new I cache state
vladvana 0:23d1f73bf130 1088 }
vladvana 0:23d1f73bf130 1089
vladvana 0:23d1f73bf130 1090 /** \brief Clean D$ by MVA
vladvana 0:23d1f73bf130 1091
vladvana 0:23d1f73bf130 1092 DCCMVAC. Data cache clean by MVA to PoC
vladvana 0:23d1f73bf130 1093 */
vladvana 0:23d1f73bf130 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
vladvana 0:23d1f73bf130 1095 #if 1
vladvana 0:23d1f73bf130 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
vladvana 0:23d1f73bf130 1097 #else
vladvana 0:23d1f73bf130 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
vladvana 0:23d1f73bf130 1099 __DCCMVAC = (uint32_t)va;
vladvana 0:23d1f73bf130 1100 #endif
vladvana 0:23d1f73bf130 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vladvana 0:23d1f73bf130 1102 }
vladvana 0:23d1f73bf130 1103
vladvana 0:23d1f73bf130 1104 /** \brief Invalidate D$ by MVA
vladvana 0:23d1f73bf130 1105
vladvana 0:23d1f73bf130 1106 DCIMVAC. Data cache invalidate by MVA to PoC
vladvana 0:23d1f73bf130 1107 */
vladvana 0:23d1f73bf130 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
vladvana 0:23d1f73bf130 1109 #if 1
vladvana 0:23d1f73bf130 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
vladvana 0:23d1f73bf130 1111 #else
vladvana 0:23d1f73bf130 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
vladvana 0:23d1f73bf130 1113 __DCIMVAC = (uint32_t)va;
vladvana 0:23d1f73bf130 1114 #endif
vladvana 0:23d1f73bf130 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vladvana 0:23d1f73bf130 1116 }
vladvana 0:23d1f73bf130 1117
vladvana 0:23d1f73bf130 1118 /** \brief Clean and Invalidate D$ by MVA
vladvana 0:23d1f73bf130 1119
vladvana 0:23d1f73bf130 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
vladvana 0:23d1f73bf130 1121 */
vladvana 0:23d1f73bf130 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
vladvana 0:23d1f73bf130 1123 #if 1
vladvana 0:23d1f73bf130 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
vladvana 0:23d1f73bf130 1125 #else
vladvana 0:23d1f73bf130 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
vladvana 0:23d1f73bf130 1127 __DCCIMVAC = (uint32_t)va;
vladvana 0:23d1f73bf130 1128 #endif
vladvana 0:23d1f73bf130 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vladvana 0:23d1f73bf130 1130 }
vladvana 0:23d1f73bf130 1131
vladvana 0:23d1f73bf130 1132 /** \brief Clean and Invalidate the entire data or unified cache
vladvana 0:23d1f73bf130 1133
vladvana 0:23d1f73bf130 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
vladvana 0:23d1f73bf130 1135 */
vladvana 0:23d1f73bf130 1136 extern void __v7_all_cache(uint32_t op);
vladvana 0:23d1f73bf130 1137
vladvana 0:23d1f73bf130 1138
vladvana 0:23d1f73bf130 1139 /** \brief Invalidate the whole D$
vladvana 0:23d1f73bf130 1140
vladvana 0:23d1f73bf130 1141 DCISW. Invalidate by Set/Way
vladvana 0:23d1f73bf130 1142 */
vladvana 0:23d1f73bf130 1143
vladvana 0:23d1f73bf130 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
vladvana 0:23d1f73bf130 1145 __v7_all_cache(0);
vladvana 0:23d1f73bf130 1146 }
vladvana 0:23d1f73bf130 1147
vladvana 0:23d1f73bf130 1148 /** \brief Clean the whole D$
vladvana 0:23d1f73bf130 1149
vladvana 0:23d1f73bf130 1150 DCCSW. Clean by Set/Way
vladvana 0:23d1f73bf130 1151 */
vladvana 0:23d1f73bf130 1152
vladvana 0:23d1f73bf130 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
vladvana 0:23d1f73bf130 1154 __v7_all_cache(1);
vladvana 0:23d1f73bf130 1155 }
vladvana 0:23d1f73bf130 1156
vladvana 0:23d1f73bf130 1157 /** \brief Clean and invalidate the whole D$
vladvana 0:23d1f73bf130 1158
vladvana 0:23d1f73bf130 1159 DCCISW. Clean and Invalidate by Set/Way
vladvana 0:23d1f73bf130 1160 */
vladvana 0:23d1f73bf130 1161
vladvana 0:23d1f73bf130 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
vladvana 0:23d1f73bf130 1163 __v7_all_cache(2);
vladvana 0:23d1f73bf130 1164 }
vladvana 0:23d1f73bf130 1165
vladvana 0:23d1f73bf130 1166 #include "core_ca_mmu.h"
vladvana 0:23d1f73bf130 1167
vladvana 0:23d1f73bf130 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
vladvana 0:23d1f73bf130 1169
vladvana 0:23d1f73bf130 1170 #error TASKING Compiler support not implemented for Cortex-A
vladvana 0:23d1f73bf130 1171
vladvana 0:23d1f73bf130 1172 #endif
vladvana 0:23d1f73bf130 1173
vladvana 0:23d1f73bf130 1174 /*@} end of CMSIS_Core_RegAccFunctions */
vladvana 0:23d1f73bf130 1175
vladvana 0:23d1f73bf130 1176
vladvana 0:23d1f73bf130 1177 #endif /* __CORE_CAFUNC_H__ */