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TARGET_NUCLEO_F103RB/stm32f1xx_hal_tim.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:: vladvana
Date:: Sun Sep 24 12:31:52 2017 +0000
Revision:: 0:23d1f73bf130

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User	Revision	Line number	New contents of line
vladvana	0:23d1f73bf130	1	/**
vladvana	0:23d1f73bf130	2	******************************************************************************
vladvana	0:23d1f73bf130	3	* @file stm32f1xx_hal_tim.h
vladvana	0:23d1f73bf130	4	* @author MCD Application Team
vladvana	0:23d1f73bf130	5	* @version V1.0.0
vladvana	0:23d1f73bf130	6	* @date 15-December-2014
vladvana	0:23d1f73bf130	7	* @brief Header file of TIM HAL module.
vladvana	0:23d1f73bf130	8	******************************************************************************
vladvana	0:23d1f73bf130	9	* @attention
vladvana	0:23d1f73bf130	10	*
vladvana	0:23d1f73bf130	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana	0:23d1f73bf130	12	*
vladvana	0:23d1f73bf130	13	* Redistribution and use in source and binary forms, with or without modification,
vladvana	0:23d1f73bf130	14	* are permitted provided that the following conditions are met:
vladvana	0:23d1f73bf130	15	* 1. Redistributions of source code must retain the above copyright notice,
vladvana	0:23d1f73bf130	16	* this list of conditions and the following disclaimer.
vladvana	0:23d1f73bf130	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana	0:23d1f73bf130	18	* this list of conditions and the following disclaimer in the documentation
vladvana	0:23d1f73bf130	19	* and/or other materials provided with the distribution.
vladvana	0:23d1f73bf130	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana	0:23d1f73bf130	21	* may be used to endorse or promote products derived from this software
vladvana	0:23d1f73bf130	22	* without specific prior written permission.
vladvana	0:23d1f73bf130	23	*
vladvana	0:23d1f73bf130	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana	0:23d1f73bf130	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana	0:23d1f73bf130	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana	0:23d1f73bf130	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana	0:23d1f73bf130	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana	0:23d1f73bf130	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana	0:23d1f73bf130	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana	0:23d1f73bf130	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana	0:23d1f73bf130	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana	0:23d1f73bf130	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana	0:23d1f73bf130	34	*
vladvana	0:23d1f73bf130	35	******************************************************************************
vladvana	0:23d1f73bf130	36	*/
vladvana	0:23d1f73bf130	37
vladvana	0:23d1f73bf130	38	/* Define to prevent recursive inclusion -------------------------------------*/
vladvana	0:23d1f73bf130	39	#ifndef __STM32F1xx_HAL_TIM_H
vladvana	0:23d1f73bf130	40	#define __STM32F1xx_HAL_TIM_H
vladvana	0:23d1f73bf130	41
vladvana	0:23d1f73bf130	42	#ifdef __cplusplus
vladvana	0:23d1f73bf130	43	extern "C" {
vladvana	0:23d1f73bf130	44	#endif
vladvana	0:23d1f73bf130	45
vladvana	0:23d1f73bf130	46	/* Includes ------------------------------------------------------------------*/
vladvana	0:23d1f73bf130	47	#include "stm32f1xx_hal_def.h"
vladvana	0:23d1f73bf130	48
vladvana	0:23d1f73bf130	49	/** @addtogroup STM32F1xx_HAL_Driver
vladvana	0:23d1f73bf130	50	* @{
vladvana	0:23d1f73bf130	51	*/
vladvana	0:23d1f73bf130	52
vladvana	0:23d1f73bf130	53	/** @addtogroup TIM
vladvana	0:23d1f73bf130	54	* @{
vladvana	0:23d1f73bf130	55	*/
vladvana	0:23d1f73bf130	56
vladvana	0:23d1f73bf130	57	/* Exported types ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	58	/** @defgroup TIM_Exported_Types TIM Exported Types
vladvana	0:23d1f73bf130	59	* @{
vladvana	0:23d1f73bf130	60	*/
vladvana	0:23d1f73bf130	61	/**
vladvana	0:23d1f73bf130	62	* @brief TIM Time base Configuration Structure definition
vladvana	0:23d1f73bf130	63	*/
vladvana	0:23d1f73bf130	64	typedef struct
vladvana	0:23d1f73bf130	65	{
vladvana	0:23d1f73bf130	66	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
vladvana	0:23d1f73bf130	67	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
vladvana	0:23d1f73bf130	68
vladvana	0:23d1f73bf130	69	uint32_t CounterMode; /*!< Specifies the counter mode.
vladvana	0:23d1f73bf130	70	This parameter can be a value of @ref TIM_Counter_Mode */
vladvana	0:23d1f73bf130	71
vladvana	0:23d1f73bf130	72	uint32_t Period; /*!< Specifies the period value to be loaded into the active
vladvana	0:23d1f73bf130	73	Auto-Reload Register at the next update event.
vladvana	0:23d1f73bf130	74	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
vladvana	0:23d1f73bf130	75
vladvana	0:23d1f73bf130	76	uint32_t ClockDivision; /*!< Specifies the clock division.
vladvana	0:23d1f73bf130	77	This parameter can be a value of @ref TIM_ClockDivision */
vladvana	0:23d1f73bf130	78
vladvana	0:23d1f73bf130	79	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
vladvana	0:23d1f73bf130	80	reaches zero, an update event is generated and counting restarts
vladvana	0:23d1f73bf130	81	from the RCR value (N).
vladvana	0:23d1f73bf130	82	This means in PWM mode that (N+1) corresponds to:
vladvana	0:23d1f73bf130	83	- the number of PWM periods in edge-aligned mode
vladvana	0:23d1f73bf130	84	- the number of half PWM period in center-aligned mode
vladvana	0:23d1f73bf130	85	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
vladvana	0:23d1f73bf130	86	@note This parameter is valid only for TIM1 and TIM8. */
vladvana	0:23d1f73bf130	87	} TIM_Base_InitTypeDef;
vladvana	0:23d1f73bf130	88
vladvana	0:23d1f73bf130	89	/**
vladvana	0:23d1f73bf130	90	* @brief TIM Output Compare Configuration Structure definition
vladvana	0:23d1f73bf130	91	*/
vladvana	0:23d1f73bf130	92	typedef struct
vladvana	0:23d1f73bf130	93	{
vladvana	0:23d1f73bf130	94	uint32_t OCMode; /*!< Specifies the TIM mode.
vladvana	0:23d1f73bf130	95	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
vladvana	0:23d1f73bf130	96
vladvana	0:23d1f73bf130	97	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
vladvana	0:23d1f73bf130	98	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
vladvana	0:23d1f73bf130	99
vladvana	0:23d1f73bf130	100	uint32_t OCPolarity; /*!< Specifies the output polarity.
vladvana	0:23d1f73bf130	101	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
vladvana	0:23d1f73bf130	102
vladvana	0:23d1f73bf130	103	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
vladvana	0:23d1f73bf130	104	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
vladvana	0:23d1f73bf130	105	@note This parameter is valid only for TIM1 and TIM8. */
vladvana	0:23d1f73bf130	106
vladvana	0:23d1f73bf130	107	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
vladvana	0:23d1f73bf130	108	This parameter can be a value of @ref TIM_Output_Fast_State
vladvana	0:23d1f73bf130	109	@note This parameter is valid only in PWM1 and PWM2 mode. */
vladvana	0:23d1f73bf130	110
vladvana	0:23d1f73bf130	111
vladvana	0:23d1f73bf130	112	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
vladvana	0:23d1f73bf130	113	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
vladvana	0:23d1f73bf130	114	@note This parameter is valid only for TIM1 and TIM8. */
vladvana	0:23d1f73bf130	115
vladvana	0:23d1f73bf130	116	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
vladvana	0:23d1f73bf130	117	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
vladvana	0:23d1f73bf130	118	@note This parameter is valid only for TIM1 and TIM8. */
vladvana	0:23d1f73bf130	119	} TIM_OC_InitTypeDef;
vladvana	0:23d1f73bf130	120
vladvana	0:23d1f73bf130	121	/**
vladvana	0:23d1f73bf130	122	* @brief TIM One Pulse Mode Configuration Structure definition
vladvana	0:23d1f73bf130	123	*/
vladvana	0:23d1f73bf130	124	typedef struct
vladvana	0:23d1f73bf130	125	{
vladvana	0:23d1f73bf130	126	uint32_t OCMode; /*!< Specifies the TIM mode.
vladvana	0:23d1f73bf130	127	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
vladvana	0:23d1f73bf130	128
vladvana	0:23d1f73bf130	129	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
vladvana	0:23d1f73bf130	130	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
vladvana	0:23d1f73bf130	131
vladvana	0:23d1f73bf130	132	uint32_t OCPolarity; /*!< Specifies the output polarity.
vladvana	0:23d1f73bf130	133	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
vladvana	0:23d1f73bf130	134
vladvana	0:23d1f73bf130	135	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
vladvana	0:23d1f73bf130	136	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
vladvana	0:23d1f73bf130	137	@note This parameter is valid only for TIM1 and TIM8. */
vladvana	0:23d1f73bf130	138
vladvana	0:23d1f73bf130	139	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
vladvana	0:23d1f73bf130	140	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
vladvana	0:23d1f73bf130	141	@note This parameter is valid only for TIM1 and TIM8. */
vladvana	0:23d1f73bf130	142
vladvana	0:23d1f73bf130	143	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
vladvana	0:23d1f73bf130	144	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
vladvana	0:23d1f73bf130	145	@note This parameter is valid only for TIM1 and TIM8. */
vladvana	0:23d1f73bf130	146
vladvana	0:23d1f73bf130	147	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
vladvana	0:23d1f73bf130	148	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
vladvana	0:23d1f73bf130	149
vladvana	0:23d1f73bf130	150	uint32_t ICSelection; /*!< Specifies the input.
vladvana	0:23d1f73bf130	151	This parameter can be a value of @ref TIM_Input_Capture_Selection */
vladvana	0:23d1f73bf130	152
vladvana	0:23d1f73bf130	153	uint32_t ICFilter; /*!< Specifies the input capture filter.
vladvana	0:23d1f73bf130	154	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
vladvana	0:23d1f73bf130	155	} TIM_OnePulse_InitTypeDef;
vladvana	0:23d1f73bf130	156
vladvana	0:23d1f73bf130	157
vladvana	0:23d1f73bf130	158	/**
vladvana	0:23d1f73bf130	159	* @brief TIM Input Capture Configuration Structure definition
vladvana	0:23d1f73bf130	160	*/
vladvana	0:23d1f73bf130	161	typedef struct
vladvana	0:23d1f73bf130	162	{
vladvana	0:23d1f73bf130	163	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
vladvana	0:23d1f73bf130	164	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
vladvana	0:23d1f73bf130	165
vladvana	0:23d1f73bf130	166	uint32_t ICSelection; /*!< Specifies the input.
vladvana	0:23d1f73bf130	167	This parameter can be a value of @ref TIM_Input_Capture_Selection */
vladvana	0:23d1f73bf130	168
vladvana	0:23d1f73bf130	169	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
vladvana	0:23d1f73bf130	170	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
vladvana	0:23d1f73bf130	171
vladvana	0:23d1f73bf130	172	uint32_t ICFilter; /*!< Specifies the input capture filter.
vladvana	0:23d1f73bf130	173	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
vladvana	0:23d1f73bf130	174	} TIM_IC_InitTypeDef;
vladvana	0:23d1f73bf130	175
vladvana	0:23d1f73bf130	176	/**
vladvana	0:23d1f73bf130	177	* @brief TIM Encoder Configuration Structure definition
vladvana	0:23d1f73bf130	178	*/
vladvana	0:23d1f73bf130	179	typedef struct
vladvana	0:23d1f73bf130	180	{
vladvana	0:23d1f73bf130	181	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
vladvana	0:23d1f73bf130	182	This parameter can be a value of @ref TIM_Encoder_Mode */
vladvana	0:23d1f73bf130	183
vladvana	0:23d1f73bf130	184	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
vladvana	0:23d1f73bf130	185	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
vladvana	0:23d1f73bf130	186
vladvana	0:23d1f73bf130	187	uint32_t IC1Selection; /*!< Specifies the input.
vladvana	0:23d1f73bf130	188	This parameter can be a value of @ref TIM_Input_Capture_Selection */
vladvana	0:23d1f73bf130	189
vladvana	0:23d1f73bf130	190	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
vladvana	0:23d1f73bf130	191	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
vladvana	0:23d1f73bf130	192
vladvana	0:23d1f73bf130	193	uint32_t IC1Filter; /*!< Specifies the input capture filter.
vladvana	0:23d1f73bf130	194	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
vladvana	0:23d1f73bf130	195
vladvana	0:23d1f73bf130	196	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
vladvana	0:23d1f73bf130	197	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
vladvana	0:23d1f73bf130	198
vladvana	0:23d1f73bf130	199	uint32_t IC2Selection; /*!< Specifies the input.
vladvana	0:23d1f73bf130	200	This parameter can be a value of @ref TIM_Input_Capture_Selection */
vladvana	0:23d1f73bf130	201
vladvana	0:23d1f73bf130	202	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
vladvana	0:23d1f73bf130	203	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
vladvana	0:23d1f73bf130	204
vladvana	0:23d1f73bf130	205	uint32_t IC2Filter; /*!< Specifies the input capture filter.
vladvana	0:23d1f73bf130	206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
vladvana	0:23d1f73bf130	207	} TIM_Encoder_InitTypeDef;
vladvana	0:23d1f73bf130	208
vladvana	0:23d1f73bf130	209
vladvana	0:23d1f73bf130	210	/**
vladvana	0:23d1f73bf130	211	* @brief TIM Clock Configuration Handle Structure definition
vladvana	0:23d1f73bf130	212	*/
vladvana	0:23d1f73bf130	213	typedef struct
vladvana	0:23d1f73bf130	214	{
vladvana	0:23d1f73bf130	215	uint32_t ClockSource; /*!< TIM clock sources
vladvana	0:23d1f73bf130	216	This parameter can be a value of @ref TIM_Clock_Source */
vladvana	0:23d1f73bf130	217	uint32_t ClockPolarity; /*!< TIM clock polarity
vladvana	0:23d1f73bf130	218	This parameter can be a value of @ref TIM_Clock_Polarity */
vladvana	0:23d1f73bf130	219	uint32_t ClockPrescaler; /*!< TIM clock prescaler
vladvana	0:23d1f73bf130	220	This parameter can be a value of @ref TIM_Clock_Prescaler */
vladvana	0:23d1f73bf130	221	uint32_t ClockFilter; /*!< TIM clock filter
vladvana	0:23d1f73bf130	222	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
vladvana	0:23d1f73bf130	223	}TIM_ClockConfigTypeDef;
vladvana	0:23d1f73bf130	224
vladvana	0:23d1f73bf130	225	/**
vladvana	0:23d1f73bf130	226	* @brief TIM Clear Input Configuration Handle Structure definition
vladvana	0:23d1f73bf130	227	*/
vladvana	0:23d1f73bf130	228	typedef struct
vladvana	0:23d1f73bf130	229	{
vladvana	0:23d1f73bf130	230	uint32_t ClearInputState; /*!< TIM clear Input state
vladvana	0:23d1f73bf130	231	This parameter can be ENABLE or DISABLE */
vladvana	0:23d1f73bf130	232	uint32_t ClearInputSource; /*!< TIM clear Input sources
vladvana	0:23d1f73bf130	233	This parameter can be a value of @ref TIM_ClearInput_Source */
vladvana	0:23d1f73bf130	234	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
vladvana	0:23d1f73bf130	235	This parameter can be a value of @ref TIM_ClearInput_Polarity */
vladvana	0:23d1f73bf130	236	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
vladvana	0:23d1f73bf130	237	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
vladvana	0:23d1f73bf130	238	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
vladvana	0:23d1f73bf130	239	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
vladvana	0:23d1f73bf130	240	}TIM_ClearInputConfigTypeDef;
vladvana	0:23d1f73bf130	241
vladvana	0:23d1f73bf130	242	/**
vladvana	0:23d1f73bf130	243	* @brief TIM Slave configuration Structure definition
vladvana	0:23d1f73bf130	244	*/
vladvana	0:23d1f73bf130	245	typedef struct {
vladvana	0:23d1f73bf130	246	uint32_t SlaveMode; /*!< Slave mode selection
vladvana	0:23d1f73bf130	247	This parameter can be a value of @ref TIM_Slave_Mode */
vladvana	0:23d1f73bf130	248	uint32_t InputTrigger; /*!< Input Trigger source
vladvana	0:23d1f73bf130	249	This parameter can be a value of @ref TIM_Trigger_Selection */
vladvana	0:23d1f73bf130	250	uint32_t TriggerPolarity; /*!< Input Trigger polarity
vladvana	0:23d1f73bf130	251	This parameter can be a value of @ref TIM_Trigger_Polarity */
vladvana	0:23d1f73bf130	252	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
vladvana	0:23d1f73bf130	253	This parameter can be a value of @ref TIM_Trigger_Prescaler */
vladvana	0:23d1f73bf130	254	uint32_t TriggerFilter; /*!< Input trigger filter
vladvana	0:23d1f73bf130	255	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
vladvana	0:23d1f73bf130	256
vladvana	0:23d1f73bf130	257	}TIM_SlaveConfigTypeDef;
vladvana	0:23d1f73bf130	258
vladvana	0:23d1f73bf130	259	/**
vladvana	0:23d1f73bf130	260	* @brief HAL State structures definition
vladvana	0:23d1f73bf130	261	*/
vladvana	0:23d1f73bf130	262	typedef enum
vladvana	0:23d1f73bf130	263	{
vladvana	0:23d1f73bf130	264	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
vladvana	0:23d1f73bf130	265	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
vladvana	0:23d1f73bf130	266	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
vladvana	0:23d1f73bf130	267	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
vladvana	0:23d1f73bf130	268	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
vladvana	0:23d1f73bf130	269	}HAL_TIM_StateTypeDef;
vladvana	0:23d1f73bf130	270
vladvana	0:23d1f73bf130	271	/**
vladvana	0:23d1f73bf130	272	* @brief HAL Active channel structures definition
vladvana	0:23d1f73bf130	273	*/
vladvana	0:23d1f73bf130	274	typedef enum
vladvana	0:23d1f73bf130	275	{
vladvana	0:23d1f73bf130	276	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
vladvana	0:23d1f73bf130	277	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
vladvana	0:23d1f73bf130	278	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
vladvana	0:23d1f73bf130	279	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
vladvana	0:23d1f73bf130	280	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
vladvana	0:23d1f73bf130	281	}HAL_TIM_ActiveChannel;
vladvana	0:23d1f73bf130	282
vladvana	0:23d1f73bf130	283	/**
vladvana	0:23d1f73bf130	284	* @brief TIM Time Base Handle Structure definition
vladvana	0:23d1f73bf130	285	*/
vladvana	0:23d1f73bf130	286	typedef struct
vladvana	0:23d1f73bf130	287	{
vladvana	0:23d1f73bf130	288	TIM_TypeDef Instance; /!< Register base address */
vladvana	0:23d1f73bf130	289	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
vladvana	0:23d1f73bf130	290	HAL_TIM_ActiveChannel Channel; /!< Active channel /
vladvana	0:23d1f73bf130	291	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
vladvana	0:23d1f73bf130	292	This array is accessed by a @ref TIM_DMA_Handle_index */
vladvana	0:23d1f73bf130	293	HAL_LockTypeDef Lock; /!< Locking object /
vladvana	0:23d1f73bf130	294	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
vladvana	0:23d1f73bf130	295	}TIM_HandleTypeDef;
vladvana	0:23d1f73bf130	296
vladvana	0:23d1f73bf130	297	/**
vladvana	0:23d1f73bf130	298	* @}
vladvana	0:23d1f73bf130	299	*/
vladvana	0:23d1f73bf130	300
vladvana	0:23d1f73bf130	301	/* Exported constants --------------------------------------------------------*/
vladvana	0:23d1f73bf130	302	/** @defgroup TIM_Exported_Constants TIM Exported Constants
vladvana	0:23d1f73bf130	303	* @{
vladvana	0:23d1f73bf130	304	*/
vladvana	0:23d1f73bf130	305
vladvana	0:23d1f73bf130	306	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
vladvana	0:23d1f73bf130	307	* @{
vladvana	0:23d1f73bf130	308	*/
vladvana	0:23d1f73bf130	309	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
vladvana	0:23d1f73bf130	310	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
vladvana	0:23d1f73bf130	311	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
vladvana	0:23d1f73bf130	312	/**
vladvana	0:23d1f73bf130	313	* @}
vladvana	0:23d1f73bf130	314	*/
vladvana	0:23d1f73bf130	315
vladvana	0:23d1f73bf130	316	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
vladvana	0:23d1f73bf130	317	* @{
vladvana	0:23d1f73bf130	318	*/
vladvana	0:23d1f73bf130	319	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
vladvana	0:23d1f73bf130	320	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
vladvana	0:23d1f73bf130	321	/**
vladvana	0:23d1f73bf130	322	* @}
vladvana	0:23d1f73bf130	323	*/
vladvana	0:23d1f73bf130	324
vladvana	0:23d1f73bf130	325	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
vladvana	0:23d1f73bf130	326	* @{
vladvana	0:23d1f73bf130	327	*/
vladvana	0:23d1f73bf130	328	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
vladvana	0:23d1f73bf130	329	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
vladvana	0:23d1f73bf130	330	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
vladvana	0:23d1f73bf130	331	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
vladvana	0:23d1f73bf130	332	/**
vladvana	0:23d1f73bf130	333	* @}
vladvana	0:23d1f73bf130	334	*/
vladvana	0:23d1f73bf130	335
vladvana	0:23d1f73bf130	336	/** @defgroup TIM_Counter_Mode TIM Counter Mode
vladvana	0:23d1f73bf130	337	* @{
vladvana	0:23d1f73bf130	338	*/
vladvana	0:23d1f73bf130	339	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	340	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
vladvana	0:23d1f73bf130	341	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
vladvana	0:23d1f73bf130	342	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
vladvana	0:23d1f73bf130	343	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
vladvana	0:23d1f73bf130	344	/**
vladvana	0:23d1f73bf130	345	* @}
vladvana	0:23d1f73bf130	346	*/
vladvana	0:23d1f73bf130	347
vladvana	0:23d1f73bf130	348	/** @defgroup TIM_ClockDivision TIM ClockDivision
vladvana	0:23d1f73bf130	349	* @{
vladvana	0:23d1f73bf130	350	*/
vladvana	0:23d1f73bf130	351	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	352	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
vladvana	0:23d1f73bf130	353	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
vladvana	0:23d1f73bf130	354	/**
vladvana	0:23d1f73bf130	355	* @}
vladvana	0:23d1f73bf130	356	*/
vladvana	0:23d1f73bf130	357
vladvana	0:23d1f73bf130	358	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
vladvana	0:23d1f73bf130	359	* @{
vladvana	0:23d1f73bf130	360	*/
vladvana	0:23d1f73bf130	361	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	362	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
vladvana	0:23d1f73bf130	363	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
vladvana	0:23d1f73bf130	364	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
vladvana	0:23d1f73bf130	365	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
vladvana	0:23d1f73bf130	366	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
vladvana	0:23d1f73bf130	367	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
vladvana	0:23d1f73bf130	368	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
vladvana	0:23d1f73bf130	369	/**
vladvana	0:23d1f73bf130	370	* @}
vladvana	0:23d1f73bf130	371	*/
vladvana	0:23d1f73bf130	372
vladvana	0:23d1f73bf130	373	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
vladvana	0:23d1f73bf130	374	* @{
vladvana	0:23d1f73bf130	375	*/
vladvana	0:23d1f73bf130	376	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	377	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
vladvana	0:23d1f73bf130	378	/**
vladvana	0:23d1f73bf130	379	* @}
vladvana	0:23d1f73bf130	380	*/
vladvana	0:23d1f73bf130	381
vladvana	0:23d1f73bf130	382	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
vladvana	0:23d1f73bf130	383	* @{
vladvana	0:23d1f73bf130	384	*/
vladvana	0:23d1f73bf130	385	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	386	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
vladvana	0:23d1f73bf130	387	/**
vladvana	0:23d1f73bf130	388	* @}
vladvana	0:23d1f73bf130	389	*/
vladvana	0:23d1f73bf130	390
vladvana	0:23d1f73bf130	391	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
vladvana	0:23d1f73bf130	392	* @{
vladvana	0:23d1f73bf130	393	*/
vladvana	0:23d1f73bf130	394	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	395	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
vladvana	0:23d1f73bf130	396	/**
vladvana	0:23d1f73bf130	397	* @}
vladvana	0:23d1f73bf130	398	*/
vladvana	0:23d1f73bf130	399
vladvana	0:23d1f73bf130	400	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
vladvana	0:23d1f73bf130	401	* @{
vladvana	0:23d1f73bf130	402	*/
vladvana	0:23d1f73bf130	403	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	404	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
vladvana	0:23d1f73bf130	405	/**
vladvana	0:23d1f73bf130	406	* @}
vladvana	0:23d1f73bf130	407	*/
vladvana	0:23d1f73bf130	408
vladvana	0:23d1f73bf130	409	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
vladvana	0:23d1f73bf130	410	* @{
vladvana	0:23d1f73bf130	411	*/
vladvana	0:23d1f73bf130	412	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	413	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
vladvana	0:23d1f73bf130	414	/**
vladvana	0:23d1f73bf130	415	* @}
vladvana	0:23d1f73bf130	416	*/
vladvana	0:23d1f73bf130	417
vladvana	0:23d1f73bf130	418	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
vladvana	0:23d1f73bf130	419	* @{
vladvana	0:23d1f73bf130	420	*/
vladvana	0:23d1f73bf130	421	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
vladvana	0:23d1f73bf130	422	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	423	/**
vladvana	0:23d1f73bf130	424	* @}
vladvana	0:23d1f73bf130	425	*/
vladvana	0:23d1f73bf130	426
vladvana	0:23d1f73bf130	427	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
vladvana	0:23d1f73bf130	428	* @{
vladvana	0:23d1f73bf130	429	*/
vladvana	0:23d1f73bf130	430	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
vladvana	0:23d1f73bf130	431	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	432	/**
vladvana	0:23d1f73bf130	433	* @}
vladvana	0:23d1f73bf130	434	*/
vladvana	0:23d1f73bf130	435
vladvana	0:23d1f73bf130	436	/** @defgroup TIM_Channel TIM Channel
vladvana	0:23d1f73bf130	437	* @{
vladvana	0:23d1f73bf130	438	*/
vladvana	0:23d1f73bf130	439	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	440	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
vladvana	0:23d1f73bf130	441	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
vladvana	0:23d1f73bf130	442	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
vladvana	0:23d1f73bf130	443	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
vladvana	0:23d1f73bf130	444	/**
vladvana	0:23d1f73bf130	445	* @}
vladvana	0:23d1f73bf130	446	*/
vladvana	0:23d1f73bf130	447
vladvana	0:23d1f73bf130	448	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
vladvana	0:23d1f73bf130	449	* @{
vladvana	0:23d1f73bf130	450	*/
vladvana	0:23d1f73bf130	451	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
vladvana	0:23d1f73bf130	452	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
vladvana	0:23d1f73bf130	453	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
vladvana	0:23d1f73bf130	454	/**
vladvana	0:23d1f73bf130	455	* @}
vladvana	0:23d1f73bf130	456	*/
vladvana	0:23d1f73bf130	457
vladvana	0:23d1f73bf130	458	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
vladvana	0:23d1f73bf130	459	* @{
vladvana	0:23d1f73bf130	460	*/
vladvana	0:23d1f73bf130	461	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
vladvana	0:23d1f73bf130	462	connected to IC1, IC2, IC3 or IC4, respectively */
vladvana	0:23d1f73bf130	463	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
vladvana	0:23d1f73bf130	464	connected to IC2, IC1, IC4 or IC3, respectively */
vladvana	0:23d1f73bf130	465	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
vladvana	0:23d1f73bf130	466	/**
vladvana	0:23d1f73bf130	467	* @}
vladvana	0:23d1f73bf130	468	*/
vladvana	0:23d1f73bf130	469
vladvana	0:23d1f73bf130	470	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
vladvana	0:23d1f73bf130	471	* @{
vladvana	0:23d1f73bf130	472	*/
vladvana	0:23d1f73bf130	473	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
vladvana	0:23d1f73bf130	474	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
vladvana	0:23d1f73bf130	475	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
vladvana	0:23d1f73bf130	476	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
vladvana	0:23d1f73bf130	477	/**
vladvana	0:23d1f73bf130	478	* @}
vladvana	0:23d1f73bf130	479	*/
vladvana	0:23d1f73bf130	480
vladvana	0:23d1f73bf130	481	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
vladvana	0:23d1f73bf130	482	* @{
vladvana	0:23d1f73bf130	483	*/
vladvana	0:23d1f73bf130	484	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
vladvana	0:23d1f73bf130	485	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	486	/**
vladvana	0:23d1f73bf130	487	* @}
vladvana	0:23d1f73bf130	488	*/
vladvana	0:23d1f73bf130	489
vladvana	0:23d1f73bf130	490	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
vladvana	0:23d1f73bf130	491	* @{
vladvana	0:23d1f73bf130	492	*/
vladvana	0:23d1f73bf130	493	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
vladvana	0:23d1f73bf130	494	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
vladvana	0:23d1f73bf130	495	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
vladvana	0:23d1f73bf130	496	/**
vladvana	0:23d1f73bf130	497	* @}
vladvana	0:23d1f73bf130	498	*/
vladvana	0:23d1f73bf130	499
vladvana	0:23d1f73bf130	500	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
vladvana	0:23d1f73bf130	501	* @{
vladvana	0:23d1f73bf130	502	*/
vladvana	0:23d1f73bf130	503	#define TIM_IT_UPDATE (TIM_DIER_UIE)
vladvana	0:23d1f73bf130	504	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
vladvana	0:23d1f73bf130	505	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
vladvana	0:23d1f73bf130	506	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
vladvana	0:23d1f73bf130	507	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
vladvana	0:23d1f73bf130	508	#define TIM_IT_COM (TIM_DIER_COMIE)
vladvana	0:23d1f73bf130	509	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
vladvana	0:23d1f73bf130	510	#define TIM_IT_BREAK (TIM_DIER_BIE)
vladvana	0:23d1f73bf130	511	/**
vladvana	0:23d1f73bf130	512	* @}
vladvana	0:23d1f73bf130	513	*/
vladvana	0:23d1f73bf130	514
vladvana	0:23d1f73bf130	515	/** @defgroup TIM_Commutation_Source TIM Commutation Source
vladvana	0:23d1f73bf130	516	* @{
vladvana	0:23d1f73bf130	517	*/
vladvana	0:23d1f73bf130	518	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
vladvana	0:23d1f73bf130	519	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	520
vladvana	0:23d1f73bf130	521	/**
vladvana	0:23d1f73bf130	522	* @}
vladvana	0:23d1f73bf130	523	*/
vladvana	0:23d1f73bf130	524
vladvana	0:23d1f73bf130	525	/** @defgroup TIM_DMA_sources TIM DMA Sources
vladvana	0:23d1f73bf130	526	* @{
vladvana	0:23d1f73bf130	527	*/
vladvana	0:23d1f73bf130	528	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
vladvana	0:23d1f73bf130	529	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
vladvana	0:23d1f73bf130	530	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
vladvana	0:23d1f73bf130	531	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
vladvana	0:23d1f73bf130	532	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
vladvana	0:23d1f73bf130	533	#define TIM_DMA_COM (TIM_DIER_COMDE)
vladvana	0:23d1f73bf130	534	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
vladvana	0:23d1f73bf130	535	/**
vladvana	0:23d1f73bf130	536	* @}
vladvana	0:23d1f73bf130	537	*/
vladvana	0:23d1f73bf130	538
vladvana	0:23d1f73bf130	539	/** @defgroup TIM_Event_Source TIM Event Source
vladvana	0:23d1f73bf130	540	* @{
vladvana	0:23d1f73bf130	541	*/
vladvana	0:23d1f73bf130	542	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
vladvana	0:23d1f73bf130	543	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
vladvana	0:23d1f73bf130	544	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
vladvana	0:23d1f73bf130	545	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
vladvana	0:23d1f73bf130	546	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
vladvana	0:23d1f73bf130	547	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
vladvana	0:23d1f73bf130	548	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
vladvana	0:23d1f73bf130	549	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
vladvana	0:23d1f73bf130	550	/**
vladvana	0:23d1f73bf130	551	* @}
vladvana	0:23d1f73bf130	552	*/
vladvana	0:23d1f73bf130	553
vladvana	0:23d1f73bf130	554	/** @defgroup TIM_Flag_definition TIM Flag Definition
vladvana	0:23d1f73bf130	555	* @{
vladvana	0:23d1f73bf130	556	*/
vladvana	0:23d1f73bf130	557	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
vladvana	0:23d1f73bf130	558	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
vladvana	0:23d1f73bf130	559	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
vladvana	0:23d1f73bf130	560	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
vladvana	0:23d1f73bf130	561	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
vladvana	0:23d1f73bf130	562	#define TIM_FLAG_COM (TIM_SR_COMIF)
vladvana	0:23d1f73bf130	563	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
vladvana	0:23d1f73bf130	564	#define TIM_FLAG_BREAK (TIM_SR_BIF)
vladvana	0:23d1f73bf130	565	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
vladvana	0:23d1f73bf130	566	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
vladvana	0:23d1f73bf130	567	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
vladvana	0:23d1f73bf130	568	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
vladvana	0:23d1f73bf130	569	/**
vladvana	0:23d1f73bf130	570	* @}
vladvana	0:23d1f73bf130	571	*/
vladvana	0:23d1f73bf130	572
vladvana	0:23d1f73bf130	573	/** @defgroup TIM_Clock_Source TIM Clock Source
vladvana	0:23d1f73bf130	574	* @{
vladvana	0:23d1f73bf130	575	*/
vladvana	0:23d1f73bf130	576	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
vladvana	0:23d1f73bf130	577	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
vladvana	0:23d1f73bf130	578	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	579	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
vladvana	0:23d1f73bf130	580	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
vladvana	0:23d1f73bf130	581	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
vladvana	0:23d1f73bf130	582	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
vladvana	0:23d1f73bf130	583	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
vladvana	0:23d1f73bf130	584	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
vladvana	0:23d1f73bf130	585	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
vladvana	0:23d1f73bf130	586	/**
vladvana	0:23d1f73bf130	587	* @}
vladvana	0:23d1f73bf130	588	*/
vladvana	0:23d1f73bf130	589
vladvana	0:23d1f73bf130	590	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
vladvana	0:23d1f73bf130	591	* @{
vladvana	0:23d1f73bf130	592	*/
vladvana	0:23d1f73bf130	593	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
vladvana	0:23d1f73bf130	594	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
vladvana	0:23d1f73bf130	595	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
vladvana	0:23d1f73bf130	596	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
vladvana	0:23d1f73bf130	597	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
vladvana	0:23d1f73bf130	598	/**
vladvana	0:23d1f73bf130	599	* @}
vladvana	0:23d1f73bf130	600	*/
vladvana	0:23d1f73bf130	601
vladvana	0:23d1f73bf130	602	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
vladvana	0:23d1f73bf130	603	* @{
vladvana	0:23d1f73bf130	604	*/
vladvana	0:23d1f73bf130	605	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
vladvana	0:23d1f73bf130	606	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
vladvana	0:23d1f73bf130	607	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
vladvana	0:23d1f73bf130	608	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
vladvana	0:23d1f73bf130	609	/**
vladvana	0:23d1f73bf130	610	* @}
vladvana	0:23d1f73bf130	611	*/
vladvana	0:23d1f73bf130	612
vladvana	0:23d1f73bf130	613	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
vladvana	0:23d1f73bf130	614	* @{
vladvana	0:23d1f73bf130	615	*/
vladvana	0:23d1f73bf130	616	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
vladvana	0:23d1f73bf130	617	#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
vladvana	0:23d1f73bf130	618	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	619	/**
vladvana	0:23d1f73bf130	620	* @}
vladvana	0:23d1f73bf130	621	*/
vladvana	0:23d1f73bf130	622
vladvana	0:23d1f73bf130	623	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
vladvana	0:23d1f73bf130	624	* @{
vladvana	0:23d1f73bf130	625	*/
vladvana	0:23d1f73bf130	626	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
vladvana	0:23d1f73bf130	627	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
vladvana	0:23d1f73bf130	628	/**
vladvana	0:23d1f73bf130	629	* @}
vladvana	0:23d1f73bf130	630	*/
vladvana	0:23d1f73bf130	631
vladvana	0:23d1f73bf130	632	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
vladvana	0:23d1f73bf130	633	* @{
vladvana	0:23d1f73bf130	634	*/
vladvana	0:23d1f73bf130	635	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
vladvana	0:23d1f73bf130	636	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
vladvana	0:23d1f73bf130	637	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
vladvana	0:23d1f73bf130	638	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
vladvana	0:23d1f73bf130	639	/**
vladvana	0:23d1f73bf130	640	* @}
vladvana	0:23d1f73bf130	641	*/
vladvana	0:23d1f73bf130	642
vladvana	0:23d1f73bf130	643	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
vladvana	0:23d1f73bf130	644	* @{
vladvana	0:23d1f73bf130	645	*/
vladvana	0:23d1f73bf130	646	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
vladvana	0:23d1f73bf130	647	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	648	/**
vladvana	0:23d1f73bf130	649	* @}
vladvana	0:23d1f73bf130	650	*/
vladvana	0:23d1f73bf130	651
vladvana	0:23d1f73bf130	652	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
vladvana	0:23d1f73bf130	653	* @{
vladvana	0:23d1f73bf130	654	*/
vladvana	0:23d1f73bf130	655	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
vladvana	0:23d1f73bf130	656	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	657	/**
vladvana	0:23d1f73bf130	658	* @}
vladvana	0:23d1f73bf130	659	*/
vladvana	0:23d1f73bf130	660
vladvana	0:23d1f73bf130	661	/** @defgroup TIM_Lock_level TIM Lock level
vladvana	0:23d1f73bf130	662	* @{
vladvana	0:23d1f73bf130	663	*/
vladvana	0:23d1f73bf130	664	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	665	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
vladvana	0:23d1f73bf130	666	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
vladvana	0:23d1f73bf130	667	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
vladvana	0:23d1f73bf130	668	/**
vladvana	0:23d1f73bf130	669	* @}
vladvana	0:23d1f73bf130	670	*/
vladvana	0:23d1f73bf130	671
vladvana	0:23d1f73bf130	672	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
vladvana	0:23d1f73bf130	673	* @{
vladvana	0:23d1f73bf130	674	*/
vladvana	0:23d1f73bf130	675	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
vladvana	0:23d1f73bf130	676	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	677	/**
vladvana	0:23d1f73bf130	678	* @}
vladvana	0:23d1f73bf130	679	*/
vladvana	0:23d1f73bf130	680
vladvana	0:23d1f73bf130	681	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
vladvana	0:23d1f73bf130	682	* @{
vladvana	0:23d1f73bf130	683	*/
vladvana	0:23d1f73bf130	684	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	685	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
vladvana	0:23d1f73bf130	686	/**
vladvana	0:23d1f73bf130	687	* @}
vladvana	0:23d1f73bf130	688	*/
vladvana	0:23d1f73bf130	689	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
vladvana	0:23d1f73bf130	690	* @{
vladvana	0:23d1f73bf130	691	*/
vladvana	0:23d1f73bf130	692	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
vladvana	0:23d1f73bf130	693	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	694	/**
vladvana	0:23d1f73bf130	695	* @}
vladvana	0:23d1f73bf130	696	*/
vladvana	0:23d1f73bf130	697
vladvana	0:23d1f73bf130	698	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
vladvana	0:23d1f73bf130	699	* @{
vladvana	0:23d1f73bf130	700	*/
vladvana	0:23d1f73bf130	701	#define TIM_TRGO_RESET ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	702	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
vladvana	0:23d1f73bf130	703	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
vladvana	0:23d1f73bf130	704	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
vladvana	0:23d1f73bf130	705	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
vladvana	0:23d1f73bf130	706	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
vladvana	0:23d1f73bf130	707	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
vladvana	0:23d1f73bf130	708	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
vladvana	0:23d1f73bf130	709	/**
vladvana	0:23d1f73bf130	710	* @}
vladvana	0:23d1f73bf130	711	*/
vladvana	0:23d1f73bf130	712
vladvana	0:23d1f73bf130	713	/** @defgroup TIM_Slave_Mode TIM Slave Mode
vladvana	0:23d1f73bf130	714	* @{
vladvana	0:23d1f73bf130	715	*/
vladvana	0:23d1f73bf130	716	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	717	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
vladvana	0:23d1f73bf130	718	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
vladvana	0:23d1f73bf130	719	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
vladvana	0:23d1f73bf130	720	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
vladvana	0:23d1f73bf130	721	/**
vladvana	0:23d1f73bf130	722	* @}
vladvana	0:23d1f73bf130	723	*/
vladvana	0:23d1f73bf130	724
vladvana	0:23d1f73bf130	725	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
vladvana	0:23d1f73bf130	726	* @{
vladvana	0:23d1f73bf130	727	*/
vladvana	0:23d1f73bf130	728	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
vladvana	0:23d1f73bf130	729	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	730	/**
vladvana	0:23d1f73bf130	731	* @}
vladvana	0:23d1f73bf130	732	*/
vladvana	0:23d1f73bf130	733
vladvana	0:23d1f73bf130	734	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
vladvana	0:23d1f73bf130	735	* @{
vladvana	0:23d1f73bf130	736	*/
vladvana	0:23d1f73bf130	737	#define TIM_TS_ITR0 ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	738	#define TIM_TS_ITR1 ((uint32_t)0x0010)
vladvana	0:23d1f73bf130	739	#define TIM_TS_ITR2 ((uint32_t)0x0020)
vladvana	0:23d1f73bf130	740	#define TIM_TS_ITR3 ((uint32_t)0x0030)
vladvana	0:23d1f73bf130	741	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
vladvana	0:23d1f73bf130	742	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
vladvana	0:23d1f73bf130	743	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
vladvana	0:23d1f73bf130	744	#define TIM_TS_ETRF ((uint32_t)0x0070)
vladvana	0:23d1f73bf130	745	#define TIM_TS_NONE ((uint32_t)0xFFFF)
vladvana	0:23d1f73bf130	746	/**
vladvana	0:23d1f73bf130	747	* @}
vladvana	0:23d1f73bf130	748	*/
vladvana	0:23d1f73bf130	749
vladvana	0:23d1f73bf130	750	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
vladvana	0:23d1f73bf130	751	* @{
vladvana	0:23d1f73bf130	752	*/
vladvana	0:23d1f73bf130	753	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
vladvana	0:23d1f73bf130	754	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
vladvana	0:23d1f73bf130	755	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
vladvana	0:23d1f73bf130	756	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
vladvana	0:23d1f73bf130	757	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
vladvana	0:23d1f73bf130	758	/**
vladvana	0:23d1f73bf130	759	* @}
vladvana	0:23d1f73bf130	760	*/
vladvana	0:23d1f73bf130	761
vladvana	0:23d1f73bf130	762	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
vladvana	0:23d1f73bf130	763	* @{
vladvana	0:23d1f73bf130	764	*/
vladvana	0:23d1f73bf130	765	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
vladvana	0:23d1f73bf130	766	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
vladvana	0:23d1f73bf130	767	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
vladvana	0:23d1f73bf130	768	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
vladvana	0:23d1f73bf130	769	/**
vladvana	0:23d1f73bf130	770	* @}
vladvana	0:23d1f73bf130	771	*/
vladvana	0:23d1f73bf130	772
vladvana	0:23d1f73bf130	773	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
vladvana	0:23d1f73bf130	774	* @{
vladvana	0:23d1f73bf130	775	*/
vladvana	0:23d1f73bf130	776	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	777	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
vladvana	0:23d1f73bf130	778	/**
vladvana	0:23d1f73bf130	779	* @}
vladvana	0:23d1f73bf130	780	*/
vladvana	0:23d1f73bf130	781
vladvana	0:23d1f73bf130	782	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
vladvana	0:23d1f73bf130	783	* @{
vladvana	0:23d1f73bf130	784	*/
vladvana	0:23d1f73bf130	785	#define TIM_DMABASE_CR1 (0x00000000)
vladvana	0:23d1f73bf130	786	#define TIM_DMABASE_CR2 (0x00000001)
vladvana	0:23d1f73bf130	787	#define TIM_DMABASE_SMCR (0x00000002)
vladvana	0:23d1f73bf130	788	#define TIM_DMABASE_DIER (0x00000003)
vladvana	0:23d1f73bf130	789	#define TIM_DMABASE_SR (0x00000004)
vladvana	0:23d1f73bf130	790	#define TIM_DMABASE_EGR (0x00000005)
vladvana	0:23d1f73bf130	791	#define TIM_DMABASE_CCMR1 (0x00000006)
vladvana	0:23d1f73bf130	792	#define TIM_DMABASE_CCMR2 (0x00000007)
vladvana	0:23d1f73bf130	793	#define TIM_DMABASE_CCER (0x00000008)
vladvana	0:23d1f73bf130	794	#define TIM_DMABASE_CNT (0x00000009)
vladvana	0:23d1f73bf130	795	#define TIM_DMABASE_PSC (0x0000000A)
vladvana	0:23d1f73bf130	796	#define TIM_DMABASE_ARR (0x0000000B)
vladvana	0:23d1f73bf130	797	#define TIM_DMABASE_RCR (0x0000000C)
vladvana	0:23d1f73bf130	798	#define TIM_DMABASE_CCR1 (0x0000000D)
vladvana	0:23d1f73bf130	799	#define TIM_DMABASE_CCR2 (0x0000000E)
vladvana	0:23d1f73bf130	800	#define TIM_DMABASE_CCR3 (0x0000000F)
vladvana	0:23d1f73bf130	801	#define TIM_DMABASE_CCR4 (0x00000010)
vladvana	0:23d1f73bf130	802	#define TIM_DMABASE_BDTR (0x00000011)
vladvana	0:23d1f73bf130	803	#define TIM_DMABASE_DCR (0x00000012)
vladvana	0:23d1f73bf130	804	/**
vladvana	0:23d1f73bf130	805	* @}
vladvana	0:23d1f73bf130	806	*/
vladvana	0:23d1f73bf130	807
vladvana	0:23d1f73bf130	808	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
vladvana	0:23d1f73bf130	809	* @{
vladvana	0:23d1f73bf130	810	*/
vladvana	0:23d1f73bf130	811	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
vladvana	0:23d1f73bf130	812	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
vladvana	0:23d1f73bf130	813	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
vladvana	0:23d1f73bf130	814	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
vladvana	0:23d1f73bf130	815	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
vladvana	0:23d1f73bf130	816	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
vladvana	0:23d1f73bf130	817	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
vladvana	0:23d1f73bf130	818	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
vladvana	0:23d1f73bf130	819	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
vladvana	0:23d1f73bf130	820	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
vladvana	0:23d1f73bf130	821	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
vladvana	0:23d1f73bf130	822	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
vladvana	0:23d1f73bf130	823	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
vladvana	0:23d1f73bf130	824	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
vladvana	0:23d1f73bf130	825	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
vladvana	0:23d1f73bf130	826	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
vladvana	0:23d1f73bf130	827	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
vladvana	0:23d1f73bf130	828	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
vladvana	0:23d1f73bf130	829	/**
vladvana	0:23d1f73bf130	830	* @}
vladvana	0:23d1f73bf130	831	*/
vladvana	0:23d1f73bf130	832
vladvana	0:23d1f73bf130	833	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
vladvana	0:23d1f73bf130	834	* @{
vladvana	0:23d1f73bf130	835	*/
vladvana	0:23d1f73bf130	836	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
vladvana	0:23d1f73bf130	837	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
vladvana	0:23d1f73bf130	838	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
vladvana	0:23d1f73bf130	839	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
vladvana	0:23d1f73bf130	840	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
vladvana	0:23d1f73bf130	841	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
vladvana	0:23d1f73bf130	842	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
vladvana	0:23d1f73bf130	843	/**
vladvana	0:23d1f73bf130	844	* @}
vladvana	0:23d1f73bf130	845	*/
vladvana	0:23d1f73bf130	846
vladvana	0:23d1f73bf130	847	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
vladvana	0:23d1f73bf130	848	* @{
vladvana	0:23d1f73bf130	849	*/
vladvana	0:23d1f73bf130	850	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
vladvana	0:23d1f73bf130	851	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	852	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
vladvana	0:23d1f73bf130	853	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
vladvana	0:23d1f73bf130	854	/**
vladvana	0:23d1f73bf130	855	* @}
vladvana	0:23d1f73bf130	856	*/
vladvana	0:23d1f73bf130	857
vladvana	0:23d1f73bf130	858	/**
vladvana	0:23d1f73bf130	859	* @}
vladvana	0:23d1f73bf130	860	*/
vladvana	0:23d1f73bf130	861
vladvana	0:23d1f73bf130	862	/* Private Constants -----------------------------------------------------------*/
vladvana	0:23d1f73bf130	863	/** @defgroup TIM_Private_Constants TIM Private Constants
vladvana	0:23d1f73bf130	864	* @{
vladvana	0:23d1f73bf130	865	*/
vladvana	0:23d1f73bf130	866
vladvana	0:23d1f73bf130	867	/* The counter of a timer instance is disabled only if all the CCx
vladvana	0:23d1f73bf130	868	channels have been disabled */
vladvana	0:23d1f73bf130	869	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
vladvana	0:23d1f73bf130	870
vladvana	0:23d1f73bf130	871	/* The counter of a timer instance is disabled only if all the CCx and CCxN
vladvana	0:23d1f73bf130	872	channels have been disabled */
vladvana	0:23d1f73bf130	873	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
vladvana	0:23d1f73bf130	874	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
vladvana	0:23d1f73bf130	875
vladvana	0:23d1f73bf130	876	/**
vladvana	0:23d1f73bf130	877	* @}
vladvana	0:23d1f73bf130	878	*/
vladvana	0:23d1f73bf130	879
vladvana	0:23d1f73bf130	880	/* Private Macros -----------------------------------------------------------*/
vladvana	0:23d1f73bf130	881	/** @defgroup TIM_Private_Macros TIM Private Macros
vladvana	0:23d1f73bf130	882	* @{
vladvana	0:23d1f73bf130	883	*/
vladvana	0:23d1f73bf130	884
vladvana	0:23d1f73bf130	885	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
vladvana	0:23d1f73bf130	886	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
vladvana	0:23d1f73bf130	887	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
vladvana	0:23d1f73bf130	888	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
vladvana	0:23d1f73bf130	889	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
vladvana	0:23d1f73bf130	890
vladvana	0:23d1f73bf130	891	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
vladvana	0:23d1f73bf130	892	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
vladvana	0:23d1f73bf130	893	((DIV) == TIM_CLOCKDIVISION_DIV4))
vladvana	0:23d1f73bf130	894
vladvana	0:23d1f73bf130	895	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
vladvana	0:23d1f73bf130	896	((MODE) == TIM_OCMODE_PWM2))
vladvana	0:23d1f73bf130	897
vladvana	0:23d1f73bf130	898	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
vladvana	0:23d1f73bf130	899	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
vladvana	0:23d1f73bf130	900	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
vladvana	0:23d1f73bf130	901	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
vladvana	0:23d1f73bf130	902	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
vladvana	0:23d1f73bf130	903	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
vladvana	0:23d1f73bf130	904
vladvana	0:23d1f73bf130	905	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
vladvana	0:23d1f73bf130	906	((STATE) == TIM_OCFAST_ENABLE))
vladvana	0:23d1f73bf130	907
vladvana	0:23d1f73bf130	908	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
vladvana	0:23d1f73bf130	909	((POLARITY) == TIM_OCPOLARITY_LOW))
vladvana	0:23d1f73bf130	910
vladvana	0:23d1f73bf130	911	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
vladvana	0:23d1f73bf130	912	((POLARITY) == TIM_OCNPOLARITY_LOW))
vladvana	0:23d1f73bf130	913
vladvana	0:23d1f73bf130	914	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
vladvana	0:23d1f73bf130	915	((STATE) == TIM_OCIDLESTATE_RESET))
vladvana	0:23d1f73bf130	916
vladvana	0:23d1f73bf130	917	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
vladvana	0:23d1f73bf130	918	((STATE) == TIM_OCNIDLESTATE_RESET))
vladvana	0:23d1f73bf130	919
vladvana	0:23d1f73bf130	920	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	921	((CHANNEL) == TIM_CHANNEL_2) \|\| \
vladvana	0:23d1f73bf130	922	((CHANNEL) == TIM_CHANNEL_3) \|\| \
vladvana	0:23d1f73bf130	923	((CHANNEL) == TIM_CHANNEL_4) \|\| \
vladvana	0:23d1f73bf130	924	((CHANNEL) == TIM_CHANNEL_ALL))
vladvana	0:23d1f73bf130	925
vladvana	0:23d1f73bf130	926	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	927	((CHANNEL) == TIM_CHANNEL_2))
vladvana	0:23d1f73bf130	928
vladvana	0:23d1f73bf130	929	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	930	((CHANNEL) == TIM_CHANNEL_2) \|\| \
vladvana	0:23d1f73bf130	931	((CHANNEL) == TIM_CHANNEL_3))
vladvana	0:23d1f73bf130	932
vladvana	0:23d1f73bf130	933	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
vladvana	0:23d1f73bf130	934	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
vladvana	0:23d1f73bf130	935	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
vladvana	0:23d1f73bf130	936
vladvana	0:23d1f73bf130	937	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
vladvana	0:23d1f73bf130	938	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
vladvana	0:23d1f73bf130	939	((SELECTION) == TIM_ICSELECTION_TRC))
vladvana	0:23d1f73bf130	940
vladvana	0:23d1f73bf130	941	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
vladvana	0:23d1f73bf130	942	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
vladvana	0:23d1f73bf130	943	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
vladvana	0:23d1f73bf130	944	((PRESCALER) == TIM_ICPSC_DIV8))
vladvana	0:23d1f73bf130	945
vladvana	0:23d1f73bf130	946	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
vladvana	0:23d1f73bf130	947	((MODE) == TIM_OPMODE_REPETITIVE))
vladvana	0:23d1f73bf130	948
vladvana	0:23d1f73bf130	949	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
vladvana	0:23d1f73bf130	950	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
vladvana	0:23d1f73bf130	951	((MODE) == TIM_ENCODERMODE_TI12))
vladvana	0:23d1f73bf130	952
vladvana	0:23d1f73bf130	953	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
vladvana	0:23d1f73bf130	954
vladvana	0:23d1f73bf130	955	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
vladvana	0:23d1f73bf130	956
vladvana	0:23d1f73bf130	957	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
vladvana	0:23d1f73bf130	958	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
vladvana	0:23d1f73bf130	959	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
vladvana	0:23d1f73bf130	960	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
vladvana	0:23d1f73bf130	961	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
vladvana	0:23d1f73bf130	962	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
vladvana	0:23d1f73bf130	963	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
vladvana	0:23d1f73bf130	964	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
vladvana	0:23d1f73bf130	965	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
vladvana	0:23d1f73bf130	966	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
vladvana	0:23d1f73bf130	967
vladvana	0:23d1f73bf130	968	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
vladvana	0:23d1f73bf130	969	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
vladvana	0:23d1f73bf130	970	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
vladvana	0:23d1f73bf130	971	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
vladvana	0:23d1f73bf130	972	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
vladvana	0:23d1f73bf130	973
vladvana	0:23d1f73bf130	974	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
vladvana	0:23d1f73bf130	975	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
vladvana	0:23d1f73bf130	976	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
vladvana	0:23d1f73bf130	977	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
vladvana	0:23d1f73bf130	978
vladvana	0:23d1f73bf130	979	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
vladvana	0:23d1f73bf130	980
vladvana	0:23d1f73bf130	981	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
vladvana	0:23d1f73bf130	982	((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
vladvana	0:23d1f73bf130	983	((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
vladvana	0:23d1f73bf130	984
vladvana	0:23d1f73bf130	985	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
vladvana	0:23d1f73bf130	986	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
vladvana	0:23d1f73bf130	987
vladvana	0:23d1f73bf130	988	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
vladvana	0:23d1f73bf130	989	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
vladvana	0:23d1f73bf130	990	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
vladvana	0:23d1f73bf130	991	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
vladvana	0:23d1f73bf130	992
vladvana	0:23d1f73bf130	993	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
vladvana	0:23d1f73bf130	994
vladvana	0:23d1f73bf130	995	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
vladvana	0:23d1f73bf130	996	((STATE) == TIM_OSSR_DISABLE))
vladvana	0:23d1f73bf130	997
vladvana	0:23d1f73bf130	998	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
vladvana	0:23d1f73bf130	999	((STATE) == TIM_OSSI_DISABLE))
vladvana	0:23d1f73bf130	1000
vladvana	0:23d1f73bf130	1001	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
vladvana	0:23d1f73bf130	1002	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
vladvana	0:23d1f73bf130	1003	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
vladvana	0:23d1f73bf130	1004	((LEVEL) == TIM_LOCKLEVEL_3))
vladvana	0:23d1f73bf130	1005
vladvana	0:23d1f73bf130	1006	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
vladvana	0:23d1f73bf130	1007	((STATE) == TIM_BREAK_DISABLE))
vladvana	0:23d1f73bf130	1008
vladvana	0:23d1f73bf130	1009	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
vladvana	0:23d1f73bf130	1010	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
vladvana	0:23d1f73bf130	1011
vladvana	0:23d1f73bf130	1012	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
vladvana	0:23d1f73bf130	1013	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
vladvana	0:23d1f73bf130	1014
vladvana	0:23d1f73bf130	1015	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
vladvana	0:23d1f73bf130	1016	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
vladvana	0:23d1f73bf130	1017	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
vladvana	0:23d1f73bf130	1018	((SOURCE) == TIM_TRGO_OC1) \|\| \
vladvana	0:23d1f73bf130	1019	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
vladvana	0:23d1f73bf130	1020	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
vladvana	0:23d1f73bf130	1021	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
vladvana	0:23d1f73bf130	1022	((SOURCE) == TIM_TRGO_OC4REF))
vladvana	0:23d1f73bf130	1023
vladvana	0:23d1f73bf130	1024	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
vladvana	0:23d1f73bf130	1025	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
vladvana	0:23d1f73bf130	1026	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
vladvana	0:23d1f73bf130	1027	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
vladvana	0:23d1f73bf130	1028	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
vladvana	0:23d1f73bf130	1029
vladvana	0:23d1f73bf130	1030	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
vladvana	0:23d1f73bf130	1031	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
vladvana	0:23d1f73bf130	1032
vladvana	0:23d1f73bf130	1033	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
vladvana	0:23d1f73bf130	1034	((SELECTION) == TIM_TS_ITR1) \|\| \
vladvana	0:23d1f73bf130	1035	((SELECTION) == TIM_TS_ITR2) \|\| \
vladvana	0:23d1f73bf130	1036	((SELECTION) == TIM_TS_ITR3) \|\| \
vladvana	0:23d1f73bf130	1037	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
vladvana	0:23d1f73bf130	1038	((SELECTION) == TIM_TS_TI1FP1) \|\| \
vladvana	0:23d1f73bf130	1039	((SELECTION) == TIM_TS_TI2FP2) \|\| \
vladvana	0:23d1f73bf130	1040	((SELECTION) == TIM_TS_ETRF))
vladvana	0:23d1f73bf130	1041
vladvana	0:23d1f73bf130	1042	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
vladvana	0:23d1f73bf130	1043	((SELECTION) == TIM_TS_ITR1) \|\| \
vladvana	0:23d1f73bf130	1044	((SELECTION) == TIM_TS_ITR2) \|\| \
vladvana	0:23d1f73bf130	1045	((SELECTION) == TIM_TS_ITR3) \|\| \
vladvana	0:23d1f73bf130	1046	((SELECTION) == TIM_TS_NONE))
vladvana	0:23d1f73bf130	1047
vladvana	0:23d1f73bf130	1048	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
vladvana	0:23d1f73bf130	1049	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
vladvana	0:23d1f73bf130	1050	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
vladvana	0:23d1f73bf130	1051	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
vladvana	0:23d1f73bf130	1052	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
vladvana	0:23d1f73bf130	1053
vladvana	0:23d1f73bf130	1054	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
vladvana	0:23d1f73bf130	1055	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
vladvana	0:23d1f73bf130	1056	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
vladvana	0:23d1f73bf130	1057	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
vladvana	0:23d1f73bf130	1058
vladvana	0:23d1f73bf130	1059	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
vladvana	0:23d1f73bf130	1060
vladvana	0:23d1f73bf130	1061	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
vladvana	0:23d1f73bf130	1062	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
vladvana	0:23d1f73bf130	1063
vladvana	0:23d1f73bf130	1064	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
vladvana	0:23d1f73bf130	1065	((BASE) == TIM_DMABASE_CR2) \|\| \
vladvana	0:23d1f73bf130	1066	((BASE) == TIM_DMABASE_SMCR) \|\| \
vladvana	0:23d1f73bf130	1067	((BASE) == TIM_DMABASE_DIER) \|\| \
vladvana	0:23d1f73bf130	1068	((BASE) == TIM_DMABASE_SR) \|\| \
vladvana	0:23d1f73bf130	1069	((BASE) == TIM_DMABASE_EGR) \|\| \
vladvana	0:23d1f73bf130	1070	((BASE) == TIM_DMABASE_CCMR1) \|\| \
vladvana	0:23d1f73bf130	1071	((BASE) == TIM_DMABASE_CCMR2) \|\| \
vladvana	0:23d1f73bf130	1072	((BASE) == TIM_DMABASE_CCER) \|\| \
vladvana	0:23d1f73bf130	1073	((BASE) == TIM_DMABASE_CNT) \|\| \
vladvana	0:23d1f73bf130	1074	((BASE) == TIM_DMABASE_PSC) \|\| \
vladvana	0:23d1f73bf130	1075	((BASE) == TIM_DMABASE_ARR) \|\| \
vladvana	0:23d1f73bf130	1076	((BASE) == TIM_DMABASE_RCR) \|\| \
vladvana	0:23d1f73bf130	1077	((BASE) == TIM_DMABASE_CCR1) \|\| \
vladvana	0:23d1f73bf130	1078	((BASE) == TIM_DMABASE_CCR2) \|\| \
vladvana	0:23d1f73bf130	1079	((BASE) == TIM_DMABASE_CCR3) \|\| \
vladvana	0:23d1f73bf130	1080	((BASE) == TIM_DMABASE_CCR4) \|\| \
vladvana	0:23d1f73bf130	1081	((BASE) == TIM_DMABASE_BDTR) \|\| \
vladvana	0:23d1f73bf130	1082	((BASE) == TIM_DMABASE_DCR))
vladvana	0:23d1f73bf130	1083
vladvana	0:23d1f73bf130	1084	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
vladvana	0:23d1f73bf130	1085	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1086	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1087	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1088	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1089	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1090	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1091	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1092	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1093	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1094	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1095	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1096	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1097	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1098	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1099	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1100	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
vladvana	0:23d1f73bf130	1101	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
vladvana	0:23d1f73bf130	1102
vladvana	0:23d1f73bf130	1103	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
vladvana	0:23d1f73bf130	1104
vladvana	0:23d1f73bf130	1105	/** @brief Set TIM IC prescaler
vladvana	0:23d1f73bf130	1106	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1107	* @param __CHANNEL__: specifies TIM Channel
vladvana	0:23d1f73bf130	1108	* @param __ICPSC__: specifies the prescaler value.
vladvana	0:23d1f73bf130	1109	* @retval None
vladvana	0:23d1f73bf130	1110	*/
vladvana	0:23d1f73bf130	1111	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
vladvana	0:23d1f73bf130	1112	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
vladvana	0:23d1f73bf130	1113	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
vladvana	0:23d1f73bf130	1114	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
vladvana	0:23d1f73bf130	1115	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
vladvana	0:23d1f73bf130	1116
vladvana	0:23d1f73bf130	1117	/** @brief Reset TIM IC prescaler
vladvana	0:23d1f73bf130	1118	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1119	* @param __CHANNEL__: specifies TIM Channel
vladvana	0:23d1f73bf130	1120	* @retval None
vladvana	0:23d1f73bf130	1121	*/
vladvana	0:23d1f73bf130	1122	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
vladvana	0:23d1f73bf130	1123	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
vladvana	0:23d1f73bf130	1124	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
vladvana	0:23d1f73bf130	1125	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
vladvana	0:23d1f73bf130	1126	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
vladvana	0:23d1f73bf130	1127
vladvana	0:23d1f73bf130	1128
vladvana	0:23d1f73bf130	1129	/** @brief Set TIM IC polarity
vladvana	0:23d1f73bf130	1130	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1131	* @param __CHANNEL__: specifies TIM Channel
vladvana	0:23d1f73bf130	1132	* @param __POLARITY__: specifies TIM Channel Polarity
vladvana	0:23d1f73bf130	1133	* @retval None
vladvana	0:23d1f73bf130	1134	*/
vladvana	0:23d1f73bf130	1135	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
vladvana	0:23d1f73bf130	1136	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
vladvana	0:23d1f73bf130	1137	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
vladvana	0:23d1f73bf130	1138	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
vladvana	0:23d1f73bf130	1139	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
vladvana	0:23d1f73bf130	1140
vladvana	0:23d1f73bf130	1141	/** @brief Reset TIM IC polarity
vladvana	0:23d1f73bf130	1142	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1143	* @param __CHANNEL__: specifies TIM Channel
vladvana	0:23d1f73bf130	1144	* @retval None
vladvana	0:23d1f73bf130	1145	*/
vladvana	0:23d1f73bf130	1146	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
vladvana	0:23d1f73bf130	1147	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
vladvana	0:23d1f73bf130	1148	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
vladvana	0:23d1f73bf130	1149	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
vladvana	0:23d1f73bf130	1150	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
vladvana	0:23d1f73bf130	1151
vladvana	0:23d1f73bf130	1152	/**
vladvana	0:23d1f73bf130	1153	* @}
vladvana	0:23d1f73bf130	1154	*/
vladvana	0:23d1f73bf130	1155
vladvana	0:23d1f73bf130	1156	/* Private Functions --------------------------------------------------------*/
vladvana	0:23d1f73bf130	1157	/** @addtogroup TIM_Private_Functions
vladvana	0:23d1f73bf130	1158	* @{
vladvana	0:23d1f73bf130	1159	*/
vladvana	0:23d1f73bf130	1160	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
vladvana	0:23d1f73bf130	1161	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
vladvana	0:23d1f73bf130	1162	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
vladvana	0:23d1f73bf130	1163	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
vladvana	0:23d1f73bf130	1164	void TIM_DMAError(DMA_HandleTypeDef *hdma);
vladvana	0:23d1f73bf130	1165	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
vladvana	0:23d1f73bf130	1166	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
vladvana	0:23d1f73bf130	1167	/**
vladvana	0:23d1f73bf130	1168	* @}
vladvana	0:23d1f73bf130	1169	*/
vladvana	0:23d1f73bf130	1170
vladvana	0:23d1f73bf130	1171	/* Exported macros -----------------------------------------------------------*/
vladvana	0:23d1f73bf130	1172	/** @defgroup TIM_Exported_Macros TIM Exported Macros
vladvana	0:23d1f73bf130	1173	* @{
vladvana	0:23d1f73bf130	1174	*/
vladvana	0:23d1f73bf130	1175
vladvana	0:23d1f73bf130	1176	/** @brief Reset TIM handle state
vladvana	0:23d1f73bf130	1177	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1178	* @retval None
vladvana	0:23d1f73bf130	1179	*/
vladvana	0:23d1f73bf130	1180	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
vladvana	0:23d1f73bf130	1181
vladvana	0:23d1f73bf130	1182	/**
vladvana	0:23d1f73bf130	1183	* @brief Enable the TIM peripheral.
vladvana	0:23d1f73bf130	1184	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1185	* @retval None
vladvana	0:23d1f73bf130	1186	*/
vladvana	0:23d1f73bf130	1187	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
vladvana	0:23d1f73bf130	1188
vladvana	0:23d1f73bf130	1189	/**
vladvana	0:23d1f73bf130	1190	* @brief Enable the TIM main Output.
vladvana	0:23d1f73bf130	1191	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1192	* @retval None
vladvana	0:23d1f73bf130	1193	*/
vladvana	0:23d1f73bf130	1194	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
vladvana	0:23d1f73bf130	1195
vladvana	0:23d1f73bf130	1196	/**
vladvana	0:23d1f73bf130	1197	* @brief Disable the TIM peripheral.
vladvana	0:23d1f73bf130	1198	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1199	* @retval None
vladvana	0:23d1f73bf130	1200	*/
vladvana	0:23d1f73bf130	1201	#define __HAL_TIM_DISABLE(__HANDLE__) \
vladvana	0:23d1f73bf130	1202	do { \
vladvana	0:23d1f73bf130	1203	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
vladvana	0:23d1f73bf130	1204	{ \
vladvana	0:23d1f73bf130	1205	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
vladvana	0:23d1f73bf130	1206	{ \
vladvana	0:23d1f73bf130	1207	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
vladvana	0:23d1f73bf130	1208	} \
vladvana	0:23d1f73bf130	1209	} \
vladvana	0:23d1f73bf130	1210	} while(0)
vladvana	0:23d1f73bf130	1211	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
vladvana	0:23d1f73bf130	1212	channels have been disabled */
vladvana	0:23d1f73bf130	1213	/**
vladvana	0:23d1f73bf130	1214	* @brief Disable the TIM main Output.
vladvana	0:23d1f73bf130	1215	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1216	* @retval None
vladvana	0:23d1f73bf130	1217	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
vladvana	0:23d1f73bf130	1218	*/
vladvana	0:23d1f73bf130	1219	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
vladvana	0:23d1f73bf130	1220	do { \
vladvana	0:23d1f73bf130	1221	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
vladvana	0:23d1f73bf130	1222	{ \
vladvana	0:23d1f73bf130	1223	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
vladvana	0:23d1f73bf130	1224	{ \
vladvana	0:23d1f73bf130	1225	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
vladvana	0:23d1f73bf130	1226	} \
vladvana	0:23d1f73bf130	1227	} \
vladvana	0:23d1f73bf130	1228	} while(0)
vladvana	0:23d1f73bf130	1229
vladvana	0:23d1f73bf130	1230	/**
vladvana	0:23d1f73bf130	1231	* @brief Enables the specified TIM interrupt.
vladvana	0:23d1f73bf130	1232	* @param __HANDLE__: specifies the TIM Handle.
vladvana	0:23d1f73bf130	1233	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
vladvana	0:23d1f73bf130	1234	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1235	* @arg TIM_IT_UPDATE: Update interrupt
vladvana	0:23d1f73bf130	1236	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
vladvana	0:23d1f73bf130	1237	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
vladvana	0:23d1f73bf130	1238	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
vladvana	0:23d1f73bf130	1239	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
vladvana	0:23d1f73bf130	1240	* @arg TIM_IT_COM: Commutation interrupt
vladvana	0:23d1f73bf130	1241	* @arg TIM_IT_TRIGGER: Trigger interrupt
vladvana	0:23d1f73bf130	1242	* @arg TIM_IT_BREAK: Break interrupt
vladvana	0:23d1f73bf130	1243	* @retval None
vladvana	0:23d1f73bf130	1244	*/
vladvana	0:23d1f73bf130	1245	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
vladvana	0:23d1f73bf130	1246
vladvana	0:23d1f73bf130	1247	/**
vladvana	0:23d1f73bf130	1248	* @brief Disables the specified TIM interrupt.
vladvana	0:23d1f73bf130	1249	* @param __HANDLE__: specifies the TIM Handle.
vladvana	0:23d1f73bf130	1250	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
vladvana	0:23d1f73bf130	1251	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1252	* @arg TIM_IT_UPDATE: Update interrupt
vladvana	0:23d1f73bf130	1253	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
vladvana	0:23d1f73bf130	1254	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
vladvana	0:23d1f73bf130	1255	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
vladvana	0:23d1f73bf130	1256	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
vladvana	0:23d1f73bf130	1257	* @arg TIM_IT_COM: Commutation interrupt
vladvana	0:23d1f73bf130	1258	* @arg TIM_IT_TRIGGER: Trigger interrupt
vladvana	0:23d1f73bf130	1259	* @arg TIM_IT_BREAK: Break interrupt
vladvana	0:23d1f73bf130	1260	* @retval None
vladvana	0:23d1f73bf130	1261	*/
vladvana	0:23d1f73bf130	1262	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
vladvana	0:23d1f73bf130	1263
vladvana	0:23d1f73bf130	1264	/**
vladvana	0:23d1f73bf130	1265	* @brief Enables the specified DMA request.
vladvana	0:23d1f73bf130	1266	* @param __HANDLE__: specifies the TIM Handle.
vladvana	0:23d1f73bf130	1267	* @param __DMA__: specifies the TIM DMA request to enable.
vladvana	0:23d1f73bf130	1268	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1269	* @arg TIM_DMA_UPDATE: Update DMA request
vladvana	0:23d1f73bf130	1270	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
vladvana	0:23d1f73bf130	1271	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
vladvana	0:23d1f73bf130	1272	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
vladvana	0:23d1f73bf130	1273	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
vladvana	0:23d1f73bf130	1274	* @arg TIM_DMA_COM: Commutation DMA request
vladvana	0:23d1f73bf130	1275	* @arg TIM_DMA_TRIGGER: Trigger DMA request
vladvana	0:23d1f73bf130	1276	* @retval None
vladvana	0:23d1f73bf130	1277	*/
vladvana	0:23d1f73bf130	1278	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
vladvana	0:23d1f73bf130	1279
vladvana	0:23d1f73bf130	1280	/**
vladvana	0:23d1f73bf130	1281	* @brief Disables the specified DMA request.
vladvana	0:23d1f73bf130	1282	* @param __HANDLE__: specifies the TIM Handle.
vladvana	0:23d1f73bf130	1283	* @param __DMA__: specifies the TIM DMA request to disable.
vladvana	0:23d1f73bf130	1284	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1285	* @arg TIM_DMA_UPDATE: Update DMA request
vladvana	0:23d1f73bf130	1286	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
vladvana	0:23d1f73bf130	1287	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
vladvana	0:23d1f73bf130	1288	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
vladvana	0:23d1f73bf130	1289	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
vladvana	0:23d1f73bf130	1290	* @arg TIM_DMA_COM: Commutation DMA request
vladvana	0:23d1f73bf130	1291	* @arg TIM_DMA_TRIGGER: Trigger DMA request
vladvana	0:23d1f73bf130	1292	* @retval None
vladvana	0:23d1f73bf130	1293	*/
vladvana	0:23d1f73bf130	1294	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
vladvana	0:23d1f73bf130	1295
vladvana	0:23d1f73bf130	1296	/**
vladvana	0:23d1f73bf130	1297	* @brief Checks whether the specified TIM interrupt flag is set or not.
vladvana	0:23d1f73bf130	1298	* @param __HANDLE__: specifies the TIM Handle.
vladvana	0:23d1f73bf130	1299	* @param __FLAG__: specifies the TIM interrupt flag to check.
vladvana	0:23d1f73bf130	1300	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1301	* @arg TIM_FLAG_UPDATE: Update interrupt flag
vladvana	0:23d1f73bf130	1302	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
vladvana	0:23d1f73bf130	1303	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
vladvana	0:23d1f73bf130	1304	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
vladvana	0:23d1f73bf130	1305	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
vladvana	0:23d1f73bf130	1306	* @arg TIM_FLAG_COM: Commutation interrupt flag
vladvana	0:23d1f73bf130	1307	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
vladvana	0:23d1f73bf130	1308	* @arg TIM_FLAG_BREAK: Break interrupt flag
vladvana	0:23d1f73bf130	1309	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
vladvana	0:23d1f73bf130	1310	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
vladvana	0:23d1f73bf130	1311	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
vladvana	0:23d1f73bf130	1312	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
vladvana	0:23d1f73bf130	1313	* @retval The new state of __FLAG__ (TRUE or FALSE).
vladvana	0:23d1f73bf130	1314	*/
vladvana	0:23d1f73bf130	1315	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
vladvana	0:23d1f73bf130	1316
vladvana	0:23d1f73bf130	1317	/**
vladvana	0:23d1f73bf130	1318	* @brief Clears the specified TIM interrupt flag.
vladvana	0:23d1f73bf130	1319	* @param __HANDLE__: specifies the TIM Handle.
vladvana	0:23d1f73bf130	1320	* @param __FLAG__: specifies the TIM interrupt flag to clear.
vladvana	0:23d1f73bf130	1321	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1322	* @arg TIM_FLAG_UPDATE: Update interrupt flag
vladvana	0:23d1f73bf130	1323	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
vladvana	0:23d1f73bf130	1324	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
vladvana	0:23d1f73bf130	1325	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
vladvana	0:23d1f73bf130	1326	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
vladvana	0:23d1f73bf130	1327	* @arg TIM_FLAG_COM: Commutation interrupt flag
vladvana	0:23d1f73bf130	1328	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
vladvana	0:23d1f73bf130	1329	* @arg TIM_FLAG_BREAK: Break interrupt flag
vladvana	0:23d1f73bf130	1330	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
vladvana	0:23d1f73bf130	1331	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
vladvana	0:23d1f73bf130	1332	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
vladvana	0:23d1f73bf130	1333	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
vladvana	0:23d1f73bf130	1334	* @retval The new state of __FLAG__ (TRUE or FALSE).
vladvana	0:23d1f73bf130	1335	*/
vladvana	0:23d1f73bf130	1336	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
vladvana	0:23d1f73bf130	1337
vladvana	0:23d1f73bf130	1338	/**
vladvana	0:23d1f73bf130	1339	* @brief Checks whether the specified TIM interrupt has occurred or not.
vladvana	0:23d1f73bf130	1340	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1341	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
vladvana	0:23d1f73bf130	1342	* @retval The state of TIM_IT (SET or RESET).
vladvana	0:23d1f73bf130	1343	*/
vladvana	0:23d1f73bf130	1344	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
vladvana	0:23d1f73bf130	1345
vladvana	0:23d1f73bf130	1346	/**
vladvana	0:23d1f73bf130	1347	* @brief Clear the TIM interrupt pending bits
vladvana	0:23d1f73bf130	1348	* @param __HANDLE__: TIM handle
vladvana	0:23d1f73bf130	1349	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
vladvana	0:23d1f73bf130	1350	* @retval None
vladvana	0:23d1f73bf130	1351	*/
vladvana	0:23d1f73bf130	1352	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
vladvana	0:23d1f73bf130	1353
vladvana	0:23d1f73bf130	1354	/**
vladvana	0:23d1f73bf130	1355	* @brief Indicates whether or not the TIM Counter is used as downcounter
vladvana	0:23d1f73bf130	1356	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1357	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
vladvana	0:23d1f73bf130	1358	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
vladvana	0:23d1f73bf130	1359	mode.
vladvana	0:23d1f73bf130	1360	*/
vladvana	0:23d1f73bf130	1361	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
vladvana	0:23d1f73bf130	1362
vladvana	0:23d1f73bf130	1363	/**
vladvana	0:23d1f73bf130	1364	* @brief Sets the TIM active prescaler register value on update event.
vladvana	0:23d1f73bf130	1365	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1366	* @param __PRESC__: specifies the active prescaler register new value.
vladvana	0:23d1f73bf130	1367	* @retval None
vladvana	0:23d1f73bf130	1368	*/
vladvana	0:23d1f73bf130	1369	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
vladvana	0:23d1f73bf130	1370
vladvana	0:23d1f73bf130	1371	/**
vladvana	0:23d1f73bf130	1372	* @brief Sets the TIM Capture Compare Register value on runtime without
vladvana	0:23d1f73bf130	1373	* calling another time ConfigChannel function.
vladvana	0:23d1f73bf130	1374	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1375	* @param __CHANNEL__ : TIM Channels to be configured.
vladvana	0:23d1f73bf130	1376	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1377	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
vladvana	0:23d1f73bf130	1378	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
vladvana	0:23d1f73bf130	1379	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
vladvana	0:23d1f73bf130	1380	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
vladvana	0:23d1f73bf130	1381	* @param __COMPARE__: specifies the Capture Compare register new value.
vladvana	0:23d1f73bf130	1382	* @retval None
vladvana	0:23d1f73bf130	1383	*/
vladvana	0:23d1f73bf130	1384	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
vladvana	0:23d1f73bf130	1385	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
vladvana	0:23d1f73bf130	1386
vladvana	0:23d1f73bf130	1387	/**
vladvana	0:23d1f73bf130	1388	* @brief Gets the TIM Capture Compare Register value on runtime
vladvana	0:23d1f73bf130	1389	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1390	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
vladvana	0:23d1f73bf130	1391	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1392	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
vladvana	0:23d1f73bf130	1393	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
vladvana	0:23d1f73bf130	1394	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
vladvana	0:23d1f73bf130	1395	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
vladvana	0:23d1f73bf130	1396	* @retval None
vladvana	0:23d1f73bf130	1397	*/
vladvana	0:23d1f73bf130	1398	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
vladvana	0:23d1f73bf130	1399	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
vladvana	0:23d1f73bf130	1400
vladvana	0:23d1f73bf130	1401	/**
vladvana	0:23d1f73bf130	1402	* @brief Sets the TIM Counter Register value on runtime.
vladvana	0:23d1f73bf130	1403	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1404	* @param __COUNTER__: specifies the Counter register new value.
vladvana	0:23d1f73bf130	1405	* @retval None
vladvana	0:23d1f73bf130	1406	*/
vladvana	0:23d1f73bf130	1407	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
vladvana	0:23d1f73bf130	1408
vladvana	0:23d1f73bf130	1409	/**
vladvana	0:23d1f73bf130	1410	* @brief Gets the TIM Counter Register value on runtime.
vladvana	0:23d1f73bf130	1411	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1412	* @retval None
vladvana	0:23d1f73bf130	1413	*/
vladvana	0:23d1f73bf130	1414	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
vladvana	0:23d1f73bf130	1415	((__HANDLE__)->Instance->CNT)
vladvana	0:23d1f73bf130	1416
vladvana	0:23d1f73bf130	1417	/**
vladvana	0:23d1f73bf130	1418	* @brief Sets the TIM Autoreload Register value on runtime without calling
vladvana	0:23d1f73bf130	1419	* another time any Init function.
vladvana	0:23d1f73bf130	1420	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1421	* @param __AUTORELOAD__: specifies the Counter register new value.
vladvana	0:23d1f73bf130	1422	* @retval None
vladvana	0:23d1f73bf130	1423	*/
vladvana	0:23d1f73bf130	1424	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
vladvana	0:23d1f73bf130	1425	do{ \
vladvana	0:23d1f73bf130	1426	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
vladvana	0:23d1f73bf130	1427	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
vladvana	0:23d1f73bf130	1428	} while(0)
vladvana	0:23d1f73bf130	1429
vladvana	0:23d1f73bf130	1430	/**
vladvana	0:23d1f73bf130	1431	* @brief Gets the TIM Autoreload Register value on runtime
vladvana	0:23d1f73bf130	1432	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1433	* @retval None
vladvana	0:23d1f73bf130	1434	*/
vladvana	0:23d1f73bf130	1435	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
vladvana	0:23d1f73bf130	1436	((__HANDLE__)->Instance->ARR)
vladvana	0:23d1f73bf130	1437
vladvana	0:23d1f73bf130	1438	/**
vladvana	0:23d1f73bf130	1439	* @brief Sets the TIM Clock Division value on runtime without calling
vladvana	0:23d1f73bf130	1440	* another time any Init function.
vladvana	0:23d1f73bf130	1441	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1442	* @param __CKD__: specifies the clock division value.
vladvana	0:23d1f73bf130	1443	* This parameter can be one of the following value:
vladvana	0:23d1f73bf130	1444	* @arg TIM_CLOCKDIVISION_DIV1
vladvana	0:23d1f73bf130	1445	* @arg TIM_CLOCKDIVISION_DIV2
vladvana	0:23d1f73bf130	1446	* @arg TIM_CLOCKDIVISION_DIV4
vladvana	0:23d1f73bf130	1447	* @retval None
vladvana	0:23d1f73bf130	1448	*/
vladvana	0:23d1f73bf130	1449	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
vladvana	0:23d1f73bf130	1450	do{ \
vladvana	0:23d1f73bf130	1451	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
vladvana	0:23d1f73bf130	1452	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
vladvana	0:23d1f73bf130	1453	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
vladvana	0:23d1f73bf130	1454	} while(0)
vladvana	0:23d1f73bf130	1455
vladvana	0:23d1f73bf130	1456	/**
vladvana	0:23d1f73bf130	1457	* @brief Gets the TIM Clock Division value on runtime
vladvana	0:23d1f73bf130	1458	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1459	* @retval None
vladvana	0:23d1f73bf130	1460	*/
vladvana	0:23d1f73bf130	1461	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
vladvana	0:23d1f73bf130	1462	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
vladvana	0:23d1f73bf130	1463
vladvana	0:23d1f73bf130	1464	/**
vladvana	0:23d1f73bf130	1465	* @brief Sets the TIM Input Capture prescaler on runtime without calling
vladvana	0:23d1f73bf130	1466	* another time HAL_TIM_IC_ConfigChannel() function.
vladvana	0:23d1f73bf130	1467	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1468	* @param __CHANNEL__ : TIM Channels to be configured.
vladvana	0:23d1f73bf130	1469	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1470	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
vladvana	0:23d1f73bf130	1471	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
vladvana	0:23d1f73bf130	1472	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
vladvana	0:23d1f73bf130	1473	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
vladvana	0:23d1f73bf130	1474	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
vladvana	0:23d1f73bf130	1475	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1476	* @arg TIM_ICPSC_DIV1: no prescaler
vladvana	0:23d1f73bf130	1477	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
vladvana	0:23d1f73bf130	1478	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
vladvana	0:23d1f73bf130	1479	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
vladvana	0:23d1f73bf130	1480	* @retval None
vladvana	0:23d1f73bf130	1481	*/
vladvana	0:23d1f73bf130	1482	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
vladvana	0:23d1f73bf130	1483	do{ \
vladvana	0:23d1f73bf130	1484	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
vladvana	0:23d1f73bf130	1485	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
vladvana	0:23d1f73bf130	1486	} while(0)
vladvana	0:23d1f73bf130	1487
vladvana	0:23d1f73bf130	1488	/**
vladvana	0:23d1f73bf130	1489	* @brief Gets the TIM Input Capture prescaler on runtime
vladvana	0:23d1f73bf130	1490	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1491	* @param __CHANNEL__: TIM Channels to be configured.
vladvana	0:23d1f73bf130	1492	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1493	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
vladvana	0:23d1f73bf130	1494	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
vladvana	0:23d1f73bf130	1495	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
vladvana	0:23d1f73bf130	1496	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
vladvana	0:23d1f73bf130	1497	* @retval None
vladvana	0:23d1f73bf130	1498	*/
vladvana	0:23d1f73bf130	1499	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
vladvana	0:23d1f73bf130	1500	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
vladvana	0:23d1f73bf130	1501	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
vladvana	0:23d1f73bf130	1502	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
vladvana	0:23d1f73bf130	1503	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
vladvana	0:23d1f73bf130	1504
vladvana	0:23d1f73bf130	1505	/**
vladvana	0:23d1f73bf130	1506	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
vladvana	0:23d1f73bf130	1507	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1508	* @note When the USR bit of the TIMx_CR1 register is set, only counter
vladvana	0:23d1f73bf130	1509	* overflow/underflow generates an update interrupt or DMA request (if
vladvana	0:23d1f73bf130	1510	* enabled)
vladvana	0:23d1f73bf130	1511	* @retval None
vladvana	0:23d1f73bf130	1512	*/
vladvana	0:23d1f73bf130	1513	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
vladvana	0:23d1f73bf130	1514	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
vladvana	0:23d1f73bf130	1515
vladvana	0:23d1f73bf130	1516	/**
vladvana	0:23d1f73bf130	1517	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
vladvana	0:23d1f73bf130	1518	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1519	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
vladvana	0:23d1f73bf130	1520	* following events generate an update interrupt or DMA request (if
vladvana	0:23d1f73bf130	1521	* enabled):
vladvana	0:23d1f73bf130	1522	* (+) Counter overflow/underflow
vladvana	0:23d1f73bf130	1523	* (+) Setting the UG bit
vladvana	0:23d1f73bf130	1524	* (+) Update generation through the slave mode controller
vladvana	0:23d1f73bf130	1525	* @retval None
vladvana	0:23d1f73bf130	1526	*/
vladvana	0:23d1f73bf130	1527	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
vladvana	0:23d1f73bf130	1528	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
vladvana	0:23d1f73bf130	1529
vladvana	0:23d1f73bf130	1530	/**
vladvana	0:23d1f73bf130	1531	* @brief Sets the TIM Capture x input polarity on runtime.
vladvana	0:23d1f73bf130	1532	* @param __HANDLE__: TIM handle.
vladvana	0:23d1f73bf130	1533	* @param __CHANNEL__: TIM Channels to be configured.
vladvana	0:23d1f73bf130	1534	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1535	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
vladvana	0:23d1f73bf130	1536	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
vladvana	0:23d1f73bf130	1537	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
vladvana	0:23d1f73bf130	1538	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
vladvana	0:23d1f73bf130	1539	* @param __POLARITY__: Polarity for TIx source
vladvana	0:23d1f73bf130	1540	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
vladvana	0:23d1f73bf130	1541	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
vladvana	0:23d1f73bf130	1542	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
vladvana	0:23d1f73bf130	1543	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
vladvana	0:23d1f73bf130	1544	* @retval None
vladvana	0:23d1f73bf130	1545	*/
vladvana	0:23d1f73bf130	1546	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
vladvana	0:23d1f73bf130	1547	do{ \
vladvana	0:23d1f73bf130	1548	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
vladvana	0:23d1f73bf130	1549	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
vladvana	0:23d1f73bf130	1550	}while(0)
vladvana	0:23d1f73bf130	1551
vladvana	0:23d1f73bf130	1552	/**
vladvana	0:23d1f73bf130	1553	* @}
vladvana	0:23d1f73bf130	1554	*/
vladvana	0:23d1f73bf130	1555
vladvana	0:23d1f73bf130	1556	/* Include TIM HAL Extension module */
vladvana	0:23d1f73bf130	1557	#include "stm32f1xx_hal_tim_ex.h"
vladvana	0:23d1f73bf130	1558
vladvana	0:23d1f73bf130	1559	/* Exported functions --------------------------------------------------------*/
vladvana	0:23d1f73bf130	1560	/** @addtogroup TIM_Exported_Functions
vladvana	0:23d1f73bf130	1561	* @{
vladvana	0:23d1f73bf130	1562	*/
vladvana	0:23d1f73bf130	1563
vladvana	0:23d1f73bf130	1564	/** @addtogroup TIM_Exported_Functions_Group1
vladvana	0:23d1f73bf130	1565	* @{
vladvana	0:23d1f73bf130	1566	*/
vladvana	0:23d1f73bf130	1567	/* Time Base functions ********************************************************/
vladvana	0:23d1f73bf130	1568	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1569	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1570	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1571	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1572	/* Blocking mode: Polling */
vladvana	0:23d1f73bf130	1573	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1574	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1575	/* Non-Blocking mode: Interrupt */
vladvana	0:23d1f73bf130	1576	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1577	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1578	/* Non-Blocking mode: DMA */
vladvana	0:23d1f73bf130	1579	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
vladvana	0:23d1f73bf130	1580	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1581	/**
vladvana	0:23d1f73bf130	1582	* @}
vladvana	0:23d1f73bf130	1583	*/
vladvana	0:23d1f73bf130	1584
vladvana	0:23d1f73bf130	1585	/** @addtogroup TIM_Exported_Functions_Group2
vladvana	0:23d1f73bf130	1586	* @{
vladvana	0:23d1f73bf130	1587	*/
vladvana	0:23d1f73bf130	1588	/* Timer Output Compare functions **********************************************/
vladvana	0:23d1f73bf130	1589	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1590	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1591	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1592	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1593	/* Blocking mode: Polling */
vladvana	0:23d1f73bf130	1594	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1595	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1596	/* Non-Blocking mode: Interrupt */
vladvana	0:23d1f73bf130	1597	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1598	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1599	/* Non-Blocking mode: DMA */
vladvana	0:23d1f73bf130	1600	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
vladvana	0:23d1f73bf130	1601	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1602
vladvana	0:23d1f73bf130	1603	/**
vladvana	0:23d1f73bf130	1604	* @}
vladvana	0:23d1f73bf130	1605	*/
vladvana	0:23d1f73bf130	1606
vladvana	0:23d1f73bf130	1607	/** @addtogroup TIM_Exported_Functions_Group3
vladvana	0:23d1f73bf130	1608	* @{
vladvana	0:23d1f73bf130	1609	*/
vladvana	0:23d1f73bf130	1610	/* Timer PWM functions *********************************************************/
vladvana	0:23d1f73bf130	1611	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1612	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1613	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1614	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1615	/* Blocking mode: Polling */
vladvana	0:23d1f73bf130	1616	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1617	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1618	/* Non-Blocking mode: Interrupt */
vladvana	0:23d1f73bf130	1619	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1620	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1621	/* Non-Blocking mode: DMA */
vladvana	0:23d1f73bf130	1622	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
vladvana	0:23d1f73bf130	1623	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1624	/**
vladvana	0:23d1f73bf130	1625	* @}
vladvana	0:23d1f73bf130	1626	*/
vladvana	0:23d1f73bf130	1627
vladvana	0:23d1f73bf130	1628	/** @addtogroup TIM_Exported_Functions_Group4
vladvana	0:23d1f73bf130	1629	* @{
vladvana	0:23d1f73bf130	1630	*/
vladvana	0:23d1f73bf130	1631	/* Timer Input Capture functions ***********************************************/
vladvana	0:23d1f73bf130	1632	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1633	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1634	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1635	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1636	/* Blocking mode: Polling */
vladvana	0:23d1f73bf130	1637	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1638	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1639	/* Non-Blocking mode: Interrupt */
vladvana	0:23d1f73bf130	1640	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1641	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1642	/* Non-Blocking mode: DMA */
vladvana	0:23d1f73bf130	1643	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
vladvana	0:23d1f73bf130	1644	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1645	/**
vladvana	0:23d1f73bf130	1646	* @}
vladvana	0:23d1f73bf130	1647	*/
vladvana	0:23d1f73bf130	1648
vladvana	0:23d1f73bf130	1649	/** @addtogroup TIM_Exported_Functions_Group5
vladvana	0:23d1f73bf130	1650	* @{
vladvana	0:23d1f73bf130	1651	*/
vladvana	0:23d1f73bf130	1652	/* Timer One Pulse functions ***************************************************/
vladvana	0:23d1f73bf130	1653	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
vladvana	0:23d1f73bf130	1654	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1655	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1656	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1657	/* Blocking mode: Polling */
vladvana	0:23d1f73bf130	1658	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
vladvana	0:23d1f73bf130	1659	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
vladvana	0:23d1f73bf130	1660	/* Non-Blocking mode: Interrupt */
vladvana	0:23d1f73bf130	1661	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
vladvana	0:23d1f73bf130	1662	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
vladvana	0:23d1f73bf130	1663	/**
vladvana	0:23d1f73bf130	1664	* @}
vladvana	0:23d1f73bf130	1665	*/
vladvana	0:23d1f73bf130	1666
vladvana	0:23d1f73bf130	1667	/** @addtogroup TIM_Exported_Functions_Group6
vladvana	0:23d1f73bf130	1668	* @{
vladvana	0:23d1f73bf130	1669	*/
vladvana	0:23d1f73bf130	1670	/* Timer Encoder functions *****************************************************/
vladvana	0:23d1f73bf130	1671	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
vladvana	0:23d1f73bf130	1672	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1673	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1674	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1675	/* Blocking mode: Polling */
vladvana	0:23d1f73bf130	1676	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1677	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1678	/* Non-Blocking mode: Interrupt */
vladvana	0:23d1f73bf130	1679	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1680	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1681	/* Non-Blocking mode: DMA */
vladvana	0:23d1f73bf130	1682	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
vladvana	0:23d1f73bf130	1683	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1684
vladvana	0:23d1f73bf130	1685	/**
vladvana	0:23d1f73bf130	1686	* @}
vladvana	0:23d1f73bf130	1687	*/
vladvana	0:23d1f73bf130	1688
vladvana	0:23d1f73bf130	1689	/** @addtogroup TIM_Exported_Functions_Group7
vladvana	0:23d1f73bf130	1690	* @{
vladvana	0:23d1f73bf130	1691	*/
vladvana	0:23d1f73bf130	1692	/* Interrupt Handler functions **********************************************/
vladvana	0:23d1f73bf130	1693	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1694	/**
vladvana	0:23d1f73bf130	1695	* @}
vladvana	0:23d1f73bf130	1696	*/
vladvana	0:23d1f73bf130	1697
vladvana	0:23d1f73bf130	1698	/** @addtogroup TIM_Exported_Functions_Group8
vladvana	0:23d1f73bf130	1699	* @{
vladvana	0:23d1f73bf130	1700	*/
vladvana	0:23d1f73bf130	1701	/* Control functions *********************************************************/
vladvana	0:23d1f73bf130	1702	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
vladvana	0:23d1f73bf130	1703	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
vladvana	0:23d1f73bf130	1704	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
vladvana	0:23d1f73bf130	1705	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
vladvana	0:23d1f73bf130	1706	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
vladvana	0:23d1f73bf130	1707	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
vladvana	0:23d1f73bf130	1708	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
vladvana	0:23d1f73bf130	1709	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
vladvana	0:23d1f73bf130	1710	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
vladvana	0:23d1f73bf130	1711	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
vladvana	0:23d1f73bf130	1712	uint32_t *BurstBuffer, uint32_t BurstLength);
vladvana	0:23d1f73bf130	1713	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
vladvana	0:23d1f73bf130	1714	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
vladvana	0:23d1f73bf130	1715	uint32_t *BurstBuffer, uint32_t BurstLength);
vladvana	0:23d1f73bf130	1716	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
vladvana	0:23d1f73bf130	1717	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
vladvana	0:23d1f73bf130	1718	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
vladvana	0:23d1f73bf130	1719
vladvana	0:23d1f73bf130	1720	/**
vladvana	0:23d1f73bf130	1721	* @}
vladvana	0:23d1f73bf130	1722	*/
vladvana	0:23d1f73bf130	1723
vladvana	0:23d1f73bf130	1724	/** @addtogroup TIM_Exported_Functions_Group9
vladvana	0:23d1f73bf130	1725	* @{
vladvana	0:23d1f73bf130	1726	*/
vladvana	0:23d1f73bf130	1727	/* Callback in non blocking modes (Interrupt and DMA) *************************/
vladvana	0:23d1f73bf130	1728	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1729	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1730	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1731	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1732	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1733	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1734	/**
vladvana	0:23d1f73bf130	1735	* @}
vladvana	0:23d1f73bf130	1736	*/
vladvana	0:23d1f73bf130	1737
vladvana	0:23d1f73bf130	1738	/** @addtogroup TIM_Exported_Functions_Group10
vladvana	0:23d1f73bf130	1739	* @{
vladvana	0:23d1f73bf130	1740	*/
vladvana	0:23d1f73bf130	1741	/* Peripheral State functions **************************************************/
vladvana	0:23d1f73bf130	1742	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1743	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1744	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1745	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1746	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1747	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
vladvana	0:23d1f73bf130	1748
vladvana	0:23d1f73bf130	1749	/**
vladvana	0:23d1f73bf130	1750	* @}
vladvana	0:23d1f73bf130	1751	*/
vladvana	0:23d1f73bf130	1752
vladvana	0:23d1f73bf130	1753	/**
vladvana	0:23d1f73bf130	1754	* @}
vladvana	0:23d1f73bf130	1755	*/
vladvana	0:23d1f73bf130	1756
vladvana	0:23d1f73bf130	1757	/**
vladvana	0:23d1f73bf130	1758	* @}
vladvana	0:23d1f73bf130	1759	*/
vladvana	0:23d1f73bf130	1760
vladvana	0:23d1f73bf130	1761	/**
vladvana	0:23d1f73bf130	1762	* @}
vladvana	0:23d1f73bf130	1763	*/
vladvana	0:23d1f73bf130	1764
vladvana	0:23d1f73bf130	1765	#ifdef __cplusplus
vladvana	0:23d1f73bf130	1766	}
vladvana	0:23d1f73bf130	1767	#endif
vladvana	0:23d1f73bf130	1768
vladvana	0:23d1f73bf130	1769	#endif /* __STM32F1xx_HAL_TIM_H */
vladvana	0:23d1f73bf130	1770
vladvana	0:23d1f73bf130	1771	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	24 Sep 2017
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
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Followers:	1

TARGET_NUCLEO_F103RB/stm32f1xx_hal_tim.h@0:23d1f73bf130, 2017-09-24 (annotated)

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