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TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc_ex.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:: vladvana
Date:: Sun Sep 24 12:31:52 2017 +0000
Revision:: 0:23d1f73bf130

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User	Revision	Line number	New contents of line
vladvana	0:23d1f73bf130	1	/**
vladvana	0:23d1f73bf130	2	******************************************************************************
vladvana	0:23d1f73bf130	3	* @file stm32f1xx_hal_rcc_ex.h
vladvana	0:23d1f73bf130	4	* @author MCD Application Team
vladvana	0:23d1f73bf130	5	* @version V1.0.0
vladvana	0:23d1f73bf130	6	* @date 15-December-2014
vladvana	0:23d1f73bf130	7	* @brief Header file of RCC HAL Extension module.
vladvana	0:23d1f73bf130	8	******************************************************************************
vladvana	0:23d1f73bf130	9	* @attention
vladvana	0:23d1f73bf130	10	*
vladvana	0:23d1f73bf130	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana	0:23d1f73bf130	12	*
vladvana	0:23d1f73bf130	13	* Redistribution and use in source and binary forms, with or without modification,
vladvana	0:23d1f73bf130	14	* are permitted provided that the following conditions are met:
vladvana	0:23d1f73bf130	15	* 1. Redistributions of source code must retain the above copyright notice,
vladvana	0:23d1f73bf130	16	* this list of conditions and the following disclaimer.
vladvana	0:23d1f73bf130	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana	0:23d1f73bf130	18	* this list of conditions and the following disclaimer in the documentation
vladvana	0:23d1f73bf130	19	* and/or other materials provided with the distribution.
vladvana	0:23d1f73bf130	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana	0:23d1f73bf130	21	* may be used to endorse or promote products derived from this software
vladvana	0:23d1f73bf130	22	* without specific prior written permission.
vladvana	0:23d1f73bf130	23	*
vladvana	0:23d1f73bf130	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana	0:23d1f73bf130	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana	0:23d1f73bf130	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana	0:23d1f73bf130	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana	0:23d1f73bf130	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana	0:23d1f73bf130	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana	0:23d1f73bf130	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana	0:23d1f73bf130	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana	0:23d1f73bf130	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana	0:23d1f73bf130	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana	0:23d1f73bf130	34	*
vladvana	0:23d1f73bf130	35	******************************************************************************
vladvana	0:23d1f73bf130	36	*/
vladvana	0:23d1f73bf130	37
vladvana	0:23d1f73bf130	38	/* Define to prevent recursive inclusion -------------------------------------*/
vladvana	0:23d1f73bf130	39	#ifndef __STM32F1xx_HAL_RCC_EX_H
vladvana	0:23d1f73bf130	40	#define __STM32F1xx_HAL_RCC_EX_H
vladvana	0:23d1f73bf130	41
vladvana	0:23d1f73bf130	42	#ifdef __cplusplus
vladvana	0:23d1f73bf130	43	extern "C" {
vladvana	0:23d1f73bf130	44	#endif
vladvana	0:23d1f73bf130	45
vladvana	0:23d1f73bf130	46	/* Includes ------------------------------------------------------------------*/
vladvana	0:23d1f73bf130	47	#include "stm32f1xx_hal_def.h"
vladvana	0:23d1f73bf130	48
vladvana	0:23d1f73bf130	49	/** @addtogroup STM32F1xx_HAL_Driver
vladvana	0:23d1f73bf130	50	* @{
vladvana	0:23d1f73bf130	51	*/
vladvana	0:23d1f73bf130	52
vladvana	0:23d1f73bf130	53	/** @addtogroup RCCEx
vladvana	0:23d1f73bf130	54	* @{
vladvana	0:23d1f73bf130	55	*/
vladvana	0:23d1f73bf130	56
vladvana	0:23d1f73bf130	57	/** @addtogroup RCCEx_Private_Constants
vladvana	0:23d1f73bf130	58	* @{
vladvana	0:23d1f73bf130	59	*/
vladvana	0:23d1f73bf130	60
vladvana	0:23d1f73bf130	61	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	62
vladvana	0:23d1f73bf130	63	/* Alias word address of PLLI2SON bit */
vladvana	0:23d1f73bf130	64	#define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
vladvana	0:23d1f73bf130	65	#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	66
vladvana	0:23d1f73bf130	67	/** @defgroup RCCEx_PLL_Timeout PLL I2S Timeout
vladvana	0:23d1f73bf130	68	* @{
vladvana	0:23d1f73bf130	69	*/
vladvana	0:23d1f73bf130	70	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
vladvana	0:23d1f73bf130	71	/**
vladvana	0:23d1f73bf130	72	* @}
vladvana	0:23d1f73bf130	73	*/
vladvana	0:23d1f73bf130	74
vladvana	0:23d1f73bf130	75	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	76
vladvana	0:23d1f73bf130	77	#define CR_REG_INDEX ((uint8_t)1)
vladvana	0:23d1f73bf130	78
vladvana	0:23d1f73bf130	79	/**
vladvana	0:23d1f73bf130	80	* @}
vladvana	0:23d1f73bf130	81	*/
vladvana	0:23d1f73bf130	82
vladvana	0:23d1f73bf130	83	/** @addtogroup RCCEx_Private_Macros
vladvana	0:23d1f73bf130	84	* @{
vladvana	0:23d1f73bf130	85	*/
vladvana	0:23d1f73bf130	86
vladvana	0:23d1f73bf130	87	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	88	#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) \|\| \
vladvana	0:23d1f73bf130	89	((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
vladvana	0:23d1f73bf130	90	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	91
vladvana	0:23d1f73bf130	92	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	93	#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV2) \|\| \
vladvana	0:23d1f73bf130	94	((__DIV__) == RCC_HSE_PREDIV_DIV3) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV4) \|\| \
vladvana	0:23d1f73bf130	95	((__DIV__) == RCC_HSE_PREDIV_DIV5) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV6) \|\| \
vladvana	0:23d1f73bf130	96	((__DIV__) == RCC_HSE_PREDIV_DIV7) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV8) \|\| \
vladvana	0:23d1f73bf130	97	((__DIV__) == RCC_HSE_PREDIV_DIV9) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV10) \|\| \
vladvana	0:23d1f73bf130	98	((__DIV__) == RCC_HSE_PREDIV_DIV11) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV12) \|\| \
vladvana	0:23d1f73bf130	99	((__DIV__) == RCC_HSE_PREDIV_DIV13) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV14) \|\| \
vladvana	0:23d1f73bf130	100	((__DIV__) == RCC_HSE_PREDIV_DIV15) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV16))
vladvana	0:23d1f73bf130	101
vladvana	0:23d1f73bf130	102	#else
vladvana	0:23d1f73bf130	103	#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV2))
vladvana	0:23d1f73bf130	104	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	105
vladvana	0:23d1f73bf130	106	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	107	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
vladvana	0:23d1f73bf130	108	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
vladvana	0:23d1f73bf130	109	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
vladvana	0:23d1f73bf130	110	((__MUL__) == RCC_PLL_MUL6_5))
vladvana	0:23d1f73bf130	111
vladvana	0:23d1f73bf130	112	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
vladvana	0:23d1f73bf130	113	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
vladvana	0:23d1f73bf130	114	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
vladvana	0:23d1f73bf130	115	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
vladvana	0:23d1f73bf130	116	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
vladvana	0:23d1f73bf130	117
vladvana	0:23d1f73bf130	118	#else
vladvana	0:23d1f73bf130	119	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
vladvana	0:23d1f73bf130	120	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
vladvana	0:23d1f73bf130	121	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
vladvana	0:23d1f73bf130	122	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
vladvana	0:23d1f73bf130	123	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
vladvana	0:23d1f73bf130	124	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
vladvana	0:23d1f73bf130	125	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
vladvana	0:23d1f73bf130	126	((__MUL__) == RCC_PLL_MUL16))
vladvana	0:23d1f73bf130	127
vladvana	0:23d1f73bf130	128	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
vladvana	0:23d1f73bf130	129	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
vladvana	0:23d1f73bf130	130	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
vladvana	0:23d1f73bf130	131
vladvana	0:23d1f73bf130	132	#endif /* STM32F105xC \|\| STM32F107xC*/
vladvana	0:23d1f73bf130	133
vladvana	0:23d1f73bf130	134	#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) \|\| ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) \|\| \
vladvana	0:23d1f73bf130	135	((__ADCCLK__) == RCC_ADCPCLK2_DIV6) \|\| ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
vladvana	0:23d1f73bf130	136
vladvana	0:23d1f73bf130	137	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	138	#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
vladvana	0:23d1f73bf130	139
vladvana	0:23d1f73bf130	140	#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
vladvana	0:23d1f73bf130	141
vladvana	0:23d1f73bf130	142	#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBPLLCLK_DIV2) \|\| ((__USBCLK__) == RCC_USBPLLCLK_DIV3))
vladvana	0:23d1f73bf130	143
vladvana	0:23d1f73bf130	144	#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) \|\| ((__MUL__) == RCC_PLLI2S_MUL9) \|\| \
vladvana	0:23d1f73bf130	145	((__MUL__) == RCC_PLLI2S_MUL10) \|\| ((__MUL__) == RCC_PLLI2S_MUL11) \|\| \
vladvana	0:23d1f73bf130	146	((__MUL__) == RCC_PLLI2S_MUL12) \|\| ((__MUL__) == RCC_PLLI2S_MUL13) \|\| \
vladvana	0:23d1f73bf130	147	((__MUL__) == RCC_PLLI2S_MUL14) \|\| ((__MUL__) == RCC_PLLI2S_MUL16) \|\| \
vladvana	0:23d1f73bf130	148	((__MUL__) == RCC_PLLI2S_MUL20))
vladvana	0:23d1f73bf130	149
vladvana	0:23d1f73bf130	150	#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV2) \|\| \
vladvana	0:23d1f73bf130	151	((__DIV__) == RCC_HSE_PREDIV2_DIV3) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV4) \|\| \
vladvana	0:23d1f73bf130	152	((__DIV__) == RCC_HSE_PREDIV2_DIV5) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV6) \|\| \
vladvana	0:23d1f73bf130	153	((__DIV__) == RCC_HSE_PREDIV2_DIV7) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV8) \|\| \
vladvana	0:23d1f73bf130	154	((__DIV__) == RCC_HSE_PREDIV2_DIV9) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV10) \|\| \
vladvana	0:23d1f73bf130	155	((__DIV__) == RCC_HSE_PREDIV2_DIV11) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV12) \|\| \
vladvana	0:23d1f73bf130	156	((__DIV__) == RCC_HSE_PREDIV2_DIV13) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV14) \|\| \
vladvana	0:23d1f73bf130	157	((__DIV__) == RCC_HSE_PREDIV2_DIV15) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
vladvana	0:23d1f73bf130	158
vladvana	0:23d1f73bf130	159	#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) \|\| ((__PLL__) == RCC_PLL2_OFF) \|\| \
vladvana	0:23d1f73bf130	160	((__PLL__) == RCC_PLL2_ON))
vladvana	0:23d1f73bf130	161
vladvana	0:23d1f73bf130	162	#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) \|\| ((__MUL__) == RCC_PLL2_MUL9) \|\| \
vladvana	0:23d1f73bf130	163	((__MUL__) == RCC_PLL2_MUL10) \|\| ((__MUL__) == RCC_PLL2_MUL11) \|\| \
vladvana	0:23d1f73bf130	164	((__MUL__) == RCC_PLL2_MUL12) \|\| ((__MUL__) == RCC_PLL2_MUL13) \|\| \
vladvana	0:23d1f73bf130	165	((__MUL__) == RCC_PLL2_MUL14) \|\| ((__MUL__) == RCC_PLL2_MUL16) \|\| \
vladvana	0:23d1f73bf130	166	((__MUL__) == RCC_PLL2_MUL20))
vladvana	0:23d1f73bf130	167
vladvana	0:23d1f73bf130	168	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
vladvana	0:23d1f73bf130	169	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
vladvana	0:23d1f73bf130	170	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
vladvana	0:23d1f73bf130	171	(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \|\| \
vladvana	0:23d1f73bf130	172	(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) \|\| \
vladvana	0:23d1f73bf130	173	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
vladvana	0:23d1f73bf130	174
vladvana	0:23d1f73bf130	175	#elif defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	176
vladvana	0:23d1f73bf130	177	#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
vladvana	0:23d1f73bf130	178
vladvana	0:23d1f73bf130	179	#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
vladvana	0:23d1f73bf130	180
vladvana	0:23d1f73bf130	181	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
vladvana	0:23d1f73bf130	182	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
vladvana	0:23d1f73bf130	183	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
vladvana	0:23d1f73bf130	184	(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \|\| \
vladvana	0:23d1f73bf130	185	(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) \|\| \
vladvana	0:23d1f73bf130	186	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
vladvana	0:23d1f73bf130	187
vladvana	0:23d1f73bf130	188
vladvana	0:23d1f73bf130	189	#elif defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB)
vladvana	0:23d1f73bf130	190
vladvana	0:23d1f73bf130	191	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
vladvana	0:23d1f73bf130	192	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
vladvana	0:23d1f73bf130	193	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
vladvana	0:23d1f73bf130	194	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
vladvana	0:23d1f73bf130	195
vladvana	0:23d1f73bf130	196	#else
vladvana	0:23d1f73bf130	197
vladvana	0:23d1f73bf130	198	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
vladvana	0:23d1f73bf130	199	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
vladvana	0:23d1f73bf130	200	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
vladvana	0:23d1f73bf130	201
vladvana	0:23d1f73bf130	202	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	203
vladvana	0:23d1f73bf130	204	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	205
vladvana	0:23d1f73bf130	206	#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBPLLCLK_DIV1) \|\| ((__USBCLK__) == RCC_USBPLLCLK_DIV1_5))
vladvana	0:23d1f73bf130	207
vladvana	0:23d1f73bf130	208	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	209
vladvana	0:23d1f73bf130	210	/**
vladvana	0:23d1f73bf130	211	* @}
vladvana	0:23d1f73bf130	212	*/
vladvana	0:23d1f73bf130	213
vladvana	0:23d1f73bf130	214	/* Exported types ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	215
vladvana	0:23d1f73bf130	216	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
vladvana	0:23d1f73bf130	217	* @{
vladvana	0:23d1f73bf130	218	*/
vladvana	0:23d1f73bf130	219
vladvana	0:23d1f73bf130	220	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	221	/**
vladvana	0:23d1f73bf130	222	* @brief RCC PLL2 configuration structure definition
vladvana	0:23d1f73bf130	223	*/
vladvana	0:23d1f73bf130	224	typedef struct
vladvana	0:23d1f73bf130	225	{
vladvana	0:23d1f73bf130	226	uint32_t PLL2State; /*!< The new state of the PLL2.
vladvana	0:23d1f73bf130	227	This parameter can be a value of @ref RCCEx_PLL2_Config */
vladvana	0:23d1f73bf130	228
vladvana	0:23d1f73bf130	229	uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
vladvana	0:23d1f73bf130	230	This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
vladvana	0:23d1f73bf130	231
vladvana	0:23d1f73bf130	232	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	233	uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
vladvana	0:23d1f73bf130	234	This parameter can be a value of @ref RCCEx_Prediv2_Factor */
vladvana	0:23d1f73bf130	235
vladvana	0:23d1f73bf130	236	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	237	} RCC_PLL2InitTypeDef;
vladvana	0:23d1f73bf130	238
vladvana	0:23d1f73bf130	239	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	240
vladvana	0:23d1f73bf130	241	/**
vladvana	0:23d1f73bf130	242	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
vladvana	0:23d1f73bf130	243	*/
vladvana	0:23d1f73bf130	244	typedef struct
vladvana	0:23d1f73bf130	245	{
vladvana	0:23d1f73bf130	246	uint32_t OscillatorType; /*!< The oscillators to be configured.
vladvana	0:23d1f73bf130	247	This parameter can be a value of @ref RCC_Oscillator_Type */
vladvana	0:23d1f73bf130	248
vladvana	0:23d1f73bf130	249	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	250	uint32_t Prediv1Source; /*!< The Prediv1 source value.
vladvana	0:23d1f73bf130	251	This parameter can be a value of @ref RCCEx_Prediv1_Source */
vladvana	0:23d1f73bf130	252	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	253
vladvana	0:23d1f73bf130	254	uint32_t HSEState; /*!< The new state of the HSE.
vladvana	0:23d1f73bf130	255	This parameter can be a value of @ref __HAL_RCC_HSE_CONFIG */
vladvana	0:23d1f73bf130	256
vladvana	0:23d1f73bf130	257	uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
vladvana	0:23d1f73bf130	258	This parameter can be a value of @ref RCCEx_Prediv1_Factor */
vladvana	0:23d1f73bf130	259
vladvana	0:23d1f73bf130	260	uint32_t LSEState; /*!< The new state of the LSE.
vladvana	0:23d1f73bf130	261	This parameter can be a value of @ref __HAL_RCC_LSE_CONFIG */
vladvana	0:23d1f73bf130	262
vladvana	0:23d1f73bf130	263	uint32_t HSIState; /*!< The new state of the HSI.
vladvana	0:23d1f73bf130	264	This parameter can be a value of @ref RCC_HSI_Config */
vladvana	0:23d1f73bf130	265
vladvana	0:23d1f73bf130	266	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
vladvana	0:23d1f73bf130	267	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
vladvana	0:23d1f73bf130	268
vladvana	0:23d1f73bf130	269	uint32_t LSIState; /*!< The new state of the LSI.
vladvana	0:23d1f73bf130	270	This parameter can be a value of @ref RCC_LSI_Config */
vladvana	0:23d1f73bf130	271
vladvana	0:23d1f73bf130	272	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
vladvana	0:23d1f73bf130	273
vladvana	0:23d1f73bf130	274	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	275	RCC_PLL2InitTypeDef PLL2; /!< PLL2 structure parameters /
vladvana	0:23d1f73bf130	276	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	277	} RCC_OscInitTypeDef;
vladvana	0:23d1f73bf130	278
vladvana	0:23d1f73bf130	279	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	280	/**
vladvana	0:23d1f73bf130	281	* @brief RCC PLLI2S configuration structure definition
vladvana	0:23d1f73bf130	282	*/
vladvana	0:23d1f73bf130	283	typedef struct
vladvana	0:23d1f73bf130	284	{
vladvana	0:23d1f73bf130	285	uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
vladvana	0:23d1f73bf130	286	This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
vladvana	0:23d1f73bf130	287
vladvana	0:23d1f73bf130	288	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	289	uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
vladvana	0:23d1f73bf130	290	This parameter can be a value of @ref RCCEx_Prediv2_Factor */
vladvana	0:23d1f73bf130	291
vladvana	0:23d1f73bf130	292	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	293	} RCC_PLLI2SInitTypeDef;
vladvana	0:23d1f73bf130	294	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	295
vladvana	0:23d1f73bf130	296	/**
vladvana	0:23d1f73bf130	297	* @brief RCC extended clocks structure definition
vladvana	0:23d1f73bf130	298	*/
vladvana	0:23d1f73bf130	299	typedef struct
vladvana	0:23d1f73bf130	300	{
vladvana	0:23d1f73bf130	301	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
vladvana	0:23d1f73bf130	302	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
vladvana	0:23d1f73bf130	303
vladvana	0:23d1f73bf130	304	uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
vladvana	0:23d1f73bf130	305	This parameter can be a value of @ref RCC_RTC_Clock_Source */
vladvana	0:23d1f73bf130	306
vladvana	0:23d1f73bf130	307	uint32_t AdcClockSelection; /*!< ADC clock source
vladvana	0:23d1f73bf130	308	This parameter can be a value of @ref RCCEx_ADC_Prescaler */
vladvana	0:23d1f73bf130	309
vladvana	0:23d1f73bf130	310	#if defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
vladvana	0:23d1f73bf130	311	uint32_t I2s2ClockSelection; /*!< I2S2 clock source
vladvana	0:23d1f73bf130	312	This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
vladvana	0:23d1f73bf130	313
vladvana	0:23d1f73bf130	314	uint32_t I2s3ClockSelection; /*!< I2S3 clock source
vladvana	0:23d1f73bf130	315	This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
vladvana	0:23d1f73bf130	316
vladvana	0:23d1f73bf130	317	#if defined (STM32F105xC) \|\| defined (STM32F107xC)
vladvana	0:23d1f73bf130	318	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
vladvana	0:23d1f73bf130	319	This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
vladvana	0:23d1f73bf130	320
vladvana	0:23d1f73bf130	321	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	322	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	323
vladvana	0:23d1f73bf130	324	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
vladvana	0:23d1f73bf130	325	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	326	uint32_t UsbClockSelection; /*!< USB clock source
vladvana	0:23d1f73bf130	327	This parameter can be a value of @ref RCCEx_USB_Prescaler */
vladvana	0:23d1f73bf130	328
vladvana	0:23d1f73bf130	329	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	330	} RCC_PeriphCLKInitTypeDef;
vladvana	0:23d1f73bf130	331
vladvana	0:23d1f73bf130	332	/**
vladvana	0:23d1f73bf130	333	* @}
vladvana	0:23d1f73bf130	334	*/
vladvana	0:23d1f73bf130	335
vladvana	0:23d1f73bf130	336	/* Exported constants --------------------------------------------------------*/
vladvana	0:23d1f73bf130	337
vladvana	0:23d1f73bf130	338	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
vladvana	0:23d1f73bf130	339	* @{
vladvana	0:23d1f73bf130	340	*/
vladvana	0:23d1f73bf130	341
vladvana	0:23d1f73bf130	342	/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
vladvana	0:23d1f73bf130	343	* @{
vladvana	0:23d1f73bf130	344	*/
vladvana	0:23d1f73bf130	345	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
vladvana	0:23d1f73bf130	346	#define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
vladvana	0:23d1f73bf130	347	#if defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
vladvana	0:23d1f73bf130	348	#define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
vladvana	0:23d1f73bf130	349	#define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
vladvana	0:23d1f73bf130	350	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	351	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
vladvana	0:23d1f73bf130	352	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	353	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
vladvana	0:23d1f73bf130	354	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	355
vladvana	0:23d1f73bf130	356	/**
vladvana	0:23d1f73bf130	357	* @}
vladvana	0:23d1f73bf130	358	*/
vladvana	0:23d1f73bf130	359
vladvana	0:23d1f73bf130	360	/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
vladvana	0:23d1f73bf130	361	* @{
vladvana	0:23d1f73bf130	362	*/
vladvana	0:23d1f73bf130	363	#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
vladvana	0:23d1f73bf130	364	#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
vladvana	0:23d1f73bf130	365	#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
vladvana	0:23d1f73bf130	366	#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
vladvana	0:23d1f73bf130	367
vladvana	0:23d1f73bf130	368	/**
vladvana	0:23d1f73bf130	369	* @}
vladvana	0:23d1f73bf130	370	*/
vladvana	0:23d1f73bf130	371
vladvana	0:23d1f73bf130	372	#if defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
vladvana	0:23d1f73bf130	373	/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
vladvana	0:23d1f73bf130	374	* @{
vladvana	0:23d1f73bf130	375	*/
vladvana	0:23d1f73bf130	376	#define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	377	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	378	#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
vladvana	0:23d1f73bf130	379	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	380
vladvana	0:23d1f73bf130	381	/**
vladvana	0:23d1f73bf130	382	* @}
vladvana	0:23d1f73bf130	383	*/
vladvana	0:23d1f73bf130	384
vladvana	0:23d1f73bf130	385	/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
vladvana	0:23d1f73bf130	386	* @{
vladvana	0:23d1f73bf130	387	*/
vladvana	0:23d1f73bf130	388	#define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	389	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	390	#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
vladvana	0:23d1f73bf130	391	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	392
vladvana	0:23d1f73bf130	393	/**
vladvana	0:23d1f73bf130	394	* @}
vladvana	0:23d1f73bf130	395	*/
vladvana	0:23d1f73bf130	396
vladvana	0:23d1f73bf130	397	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	398
vladvana	0:23d1f73bf130	399	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	400
vladvana	0:23d1f73bf130	401	/** @defgroup RCCEx_USB_Prescaler USB Prescaler
vladvana	0:23d1f73bf130	402	* @{
vladvana	0:23d1f73bf130	403	*/
vladvana	0:23d1f73bf130	404	#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE
vladvana	0:23d1f73bf130	405	#define RCC_USBPLLCLK_DIV1_5 ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	406
vladvana	0:23d1f73bf130	407	/**
vladvana	0:23d1f73bf130	408	* @}
vladvana	0:23d1f73bf130	409	*/
vladvana	0:23d1f73bf130	410
vladvana	0:23d1f73bf130	411	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	412
vladvana	0:23d1f73bf130	413
vladvana	0:23d1f73bf130	414	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	415	/** @defgroup RCCEx_USB_Prescaler USB Prescaler
vladvana	0:23d1f73bf130	416	* @{
vladvana	0:23d1f73bf130	417	*/
vladvana	0:23d1f73bf130	418	#define RCC_USBPLLCLK_DIV2 RCC_CFGR_OTGFSPRE
vladvana	0:23d1f73bf130	419	#define RCC_USBPLLCLK_DIV3 ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	420
vladvana	0:23d1f73bf130	421	/**
vladvana	0:23d1f73bf130	422	* @}
vladvana	0:23d1f73bf130	423	*/
vladvana	0:23d1f73bf130	424
vladvana	0:23d1f73bf130	425	/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
vladvana	0:23d1f73bf130	426	* @{
vladvana	0:23d1f73bf130	427	*/
vladvana	0:23d1f73bf130	428
vladvana	0:23d1f73bf130	429	#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /!< PLLI2S input clock 8 */
vladvana	0:23d1f73bf130	430	#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /!< PLLI2S input clock 9 */
vladvana	0:23d1f73bf130	431	#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /!< PLLI2S input clock 10 */
vladvana	0:23d1f73bf130	432	#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /!< PLLI2S input clock 11 */
vladvana	0:23d1f73bf130	433	#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /!< PLLI2S input clock 12 */
vladvana	0:23d1f73bf130	434	#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /!< PLLI2S input clock 13 */
vladvana	0:23d1f73bf130	435	#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /!< PLLI2S input clock 14 */
vladvana	0:23d1f73bf130	436	#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /!< PLLI2S input clock 16 */
vladvana	0:23d1f73bf130	437	#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /!< PLLI2S input clock 20 */
vladvana	0:23d1f73bf130	438
vladvana	0:23d1f73bf130	439	/**
vladvana	0:23d1f73bf130	440	* @}
vladvana	0:23d1f73bf130	441	*/
vladvana	0:23d1f73bf130	442	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	443
vladvana	0:23d1f73bf130	444	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	445	/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
vladvana	0:23d1f73bf130	446	* @{
vladvana	0:23d1f73bf130	447	*/
vladvana	0:23d1f73bf130	448
vladvana	0:23d1f73bf130	449	#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
vladvana	0:23d1f73bf130	450	#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
vladvana	0:23d1f73bf130	451
vladvana	0:23d1f73bf130	452	/**
vladvana	0:23d1f73bf130	453	* @}
vladvana	0:23d1f73bf130	454	*/
vladvana	0:23d1f73bf130	455	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	456
vladvana	0:23d1f73bf130	457	/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
vladvana	0:23d1f73bf130	458	* @{
vladvana	0:23d1f73bf130	459	*/
vladvana	0:23d1f73bf130	460
vladvana	0:23d1f73bf130	461	#define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	462
vladvana	0:23d1f73bf130	463	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	464	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
vladvana	0:23d1f73bf130	465	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
vladvana	0:23d1f73bf130	466	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
vladvana	0:23d1f73bf130	467	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
vladvana	0:23d1f73bf130	468	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
vladvana	0:23d1f73bf130	469	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
vladvana	0:23d1f73bf130	470	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
vladvana	0:23d1f73bf130	471	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
vladvana	0:23d1f73bf130	472	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
vladvana	0:23d1f73bf130	473	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
vladvana	0:23d1f73bf130	474	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
vladvana	0:23d1f73bf130	475	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
vladvana	0:23d1f73bf130	476	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
vladvana	0:23d1f73bf130	477	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
vladvana	0:23d1f73bf130	478	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
vladvana	0:23d1f73bf130	479	#else
vladvana	0:23d1f73bf130	480	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
vladvana	0:23d1f73bf130	481	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	482
vladvana	0:23d1f73bf130	483	/**
vladvana	0:23d1f73bf130	484	* @}
vladvana	0:23d1f73bf130	485	*/
vladvana	0:23d1f73bf130	486
vladvana	0:23d1f73bf130	487	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	488	/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
vladvana	0:23d1f73bf130	489	* @{
vladvana	0:23d1f73bf130	490	*/
vladvana	0:23d1f73bf130	491
vladvana	0:23d1f73bf130	492	#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /!< PREDIV2 input clock not divided /
vladvana	0:23d1f73bf130	493	#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /!< PREDIV2 input clock divided by 2 /
vladvana	0:23d1f73bf130	494	#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /!< PREDIV2 input clock divided by 3 /
vladvana	0:23d1f73bf130	495	#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /!< PREDIV2 input clock divided by 4 /
vladvana	0:23d1f73bf130	496	#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /!< PREDIV2 input clock divided by 5 /
vladvana	0:23d1f73bf130	497	#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /!< PREDIV2 input clock divided by 6 /
vladvana	0:23d1f73bf130	498	#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /!< PREDIV2 input clock divided by 7 /
vladvana	0:23d1f73bf130	499	#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /!< PREDIV2 input clock divided by 8 /
vladvana	0:23d1f73bf130	500	#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /!< PREDIV2 input clock divided by 9 /
vladvana	0:23d1f73bf130	501	#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /!< PREDIV2 input clock divided by 10 /
vladvana	0:23d1f73bf130	502	#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /!< PREDIV2 input clock divided by 11 /
vladvana	0:23d1f73bf130	503	#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /!< PREDIV2 input clock divided by 12 /
vladvana	0:23d1f73bf130	504	#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /!< PREDIV2 input clock divided by 13 /
vladvana	0:23d1f73bf130	505	#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /!< PREDIV2 input clock divided by 14 /
vladvana	0:23d1f73bf130	506	#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /!< PREDIV2 input clock divided by 15 /
vladvana	0:23d1f73bf130	507	#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /!< PREDIV2 input clock divided by 16 /
vladvana	0:23d1f73bf130	508
vladvana	0:23d1f73bf130	509	/**
vladvana	0:23d1f73bf130	510	* @}
vladvana	0:23d1f73bf130	511	*/
vladvana	0:23d1f73bf130	512
vladvana	0:23d1f73bf130	513	/** @defgroup RCCEx_PLL2_Config PLL Config
vladvana	0:23d1f73bf130	514	* @{
vladvana	0:23d1f73bf130	515	*/
vladvana	0:23d1f73bf130	516	#define RCC_PLL2_NONE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	517	#define RCC_PLL2_OFF ((uint32_t)0x00000001)
vladvana	0:23d1f73bf130	518	#define RCC_PLL2_ON ((uint32_t)0x00000002)
vladvana	0:23d1f73bf130	519
vladvana	0:23d1f73bf130	520	/**
vladvana	0:23d1f73bf130	521	* @}
vladvana	0:23d1f73bf130	522	*/
vladvana	0:23d1f73bf130	523
vladvana	0:23d1f73bf130	524	/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
vladvana	0:23d1f73bf130	525	* @{
vladvana	0:23d1f73bf130	526	*/
vladvana	0:23d1f73bf130	527
vladvana	0:23d1f73bf130	528	#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /!< PLL2 input clock 8 */
vladvana	0:23d1f73bf130	529	#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /!< PLL2 input clock 9 */
vladvana	0:23d1f73bf130	530	#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /!< PLL2 input clock 10 */
vladvana	0:23d1f73bf130	531	#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /!< PLL2 input clock 11 */
vladvana	0:23d1f73bf130	532	#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /!< PLL2 input clock 12 */
vladvana	0:23d1f73bf130	533	#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /!< PLL2 input clock 13 */
vladvana	0:23d1f73bf130	534	#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /!< PLL2 input clock 14 */
vladvana	0:23d1f73bf130	535	#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /!< PLL2 input clock 16 */
vladvana	0:23d1f73bf130	536	#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /!< PLL2 input clock 20 */
vladvana	0:23d1f73bf130	537
vladvana	0:23d1f73bf130	538	/**
vladvana	0:23d1f73bf130	539	* @}
vladvana	0:23d1f73bf130	540	*/
vladvana	0:23d1f73bf130	541
vladvana	0:23d1f73bf130	542	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	543
vladvana	0:23d1f73bf130	544	/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
vladvana	0:23d1f73bf130	545	* @{
vladvana	0:23d1f73bf130	546	*/
vladvana	0:23d1f73bf130	547
vladvana	0:23d1f73bf130	548	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	549	#else
vladvana	0:23d1f73bf130	550	#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
vladvana	0:23d1f73bf130	551	#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
vladvana	0:23d1f73bf130	552	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	553	#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
vladvana	0:23d1f73bf130	554	#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
vladvana	0:23d1f73bf130	555	#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
vladvana	0:23d1f73bf130	556	#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
vladvana	0:23d1f73bf130	557	#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
vladvana	0:23d1f73bf130	558	#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
vladvana	0:23d1f73bf130	559	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	560	#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
vladvana	0:23d1f73bf130	561	#else
vladvana	0:23d1f73bf130	562	#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
vladvana	0:23d1f73bf130	563	#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
vladvana	0:23d1f73bf130	564	#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
vladvana	0:23d1f73bf130	565	#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
vladvana	0:23d1f73bf130	566	#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
vladvana	0:23d1f73bf130	567	#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
vladvana	0:23d1f73bf130	568	#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
vladvana	0:23d1f73bf130	569	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	570
vladvana	0:23d1f73bf130	571	/**
vladvana	0:23d1f73bf130	572	* @}
vladvana	0:23d1f73bf130	573	*/
vladvana	0:23d1f73bf130	574
vladvana	0:23d1f73bf130	575	/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
vladvana	0:23d1f73bf130	576	* @{
vladvana	0:23d1f73bf130	577	*/
vladvana	0:23d1f73bf130	578	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
vladvana	0:23d1f73bf130	579	#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
vladvana	0:23d1f73bf130	580	#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
vladvana	0:23d1f73bf130	581	#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
vladvana	0:23d1f73bf130	582	#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
vladvana	0:23d1f73bf130	583	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	584	#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
vladvana	0:23d1f73bf130	585	#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
vladvana	0:23d1f73bf130	586	#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
vladvana	0:23d1f73bf130	587	#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
vladvana	0:23d1f73bf130	588	#endif /* STM32F105xC \|\| STM32F107xC*/
vladvana	0:23d1f73bf130	589	/**
vladvana	0:23d1f73bf130	590	* @}
vladvana	0:23d1f73bf130	591	*/
vladvana	0:23d1f73bf130	592
vladvana	0:23d1f73bf130	593	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	594	/** @defgroup RCCEx_Interrupt RCCEx Interrupt
vladvana	0:23d1f73bf130	595	* @{
vladvana	0:23d1f73bf130	596	*/
vladvana	0:23d1f73bf130	597	#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
vladvana	0:23d1f73bf130	598	#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
vladvana	0:23d1f73bf130	599	/**
vladvana	0:23d1f73bf130	600	* @}
vladvana	0:23d1f73bf130	601	*/
vladvana	0:23d1f73bf130	602
vladvana	0:23d1f73bf130	603	/** @defgroup RCCEx_Flag RCCEx Flag
vladvana	0:23d1f73bf130	604	* Elements values convention: 0XXYYYYYb
vladvana	0:23d1f73bf130	605	* - YYYYY : Flag position in the register
vladvana	0:23d1f73bf130	606	* - XX : Register index
vladvana	0:23d1f73bf130	607	* - 01: CR register
vladvana	0:23d1f73bf130	608	* @{
vladvana	0:23d1f73bf130	609	*/
vladvana	0:23d1f73bf130	610	/* Flags in the CR register */
vladvana	0:23d1f73bf130	611	#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLL2RDY)))
vladvana	0:23d1f73bf130	612	#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLL3RDY)))
vladvana	0:23d1f73bf130	613	/**
vladvana	0:23d1f73bf130	614	* @}
vladvana	0:23d1f73bf130	615	*/
vladvana	0:23d1f73bf130	616	#endif /* STM32F105xC \|\| STM32F107xC*/
vladvana	0:23d1f73bf130	617
vladvana	0:23d1f73bf130	618	/**
vladvana	0:23d1f73bf130	619	* @}
vladvana	0:23d1f73bf130	620	*/
vladvana	0:23d1f73bf130	621
vladvana	0:23d1f73bf130	622	/* Exported macro ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	623	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
vladvana	0:23d1f73bf130	624	* @{
vladvana	0:23d1f73bf130	625	*/
vladvana	0:23d1f73bf130	626
vladvana	0:23d1f73bf130	627	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
vladvana	0:23d1f73bf130	628	* @brief Enable or disable the AHB1 peripheral clock.
vladvana	0:23d1f73bf130	629	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	630	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	631	* using it.
vladvana	0:23d1f73bf130	632	* @{
vladvana	0:23d1f73bf130	633	*/
vladvana	0:23d1f73bf130	634
vladvana	0:23d1f73bf130	635	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	636	defined (STM32F105xC) \|\| defined (STM32F107xC) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	637	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	638	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	639	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
vladvana	0:23d1f73bf130	640	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	641	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
vladvana	0:23d1f73bf130	642	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	643	} while(0)
vladvana	0:23d1f73bf130	644
vladvana	0:23d1f73bf130	645	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
vladvana	0:23d1f73bf130	646	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F100xE */
vladvana	0:23d1f73bf130	647
vladvana	0:23d1f73bf130	648	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	649	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	650	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	651	SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
vladvana	0:23d1f73bf130	652	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	653	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
vladvana	0:23d1f73bf130	654	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	655	} while(0)
vladvana	0:23d1f73bf130	656
vladvana	0:23d1f73bf130	657	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
vladvana	0:23d1f73bf130	658	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F100xE */
vladvana	0:23d1f73bf130	659
vladvana	0:23d1f73bf130	660	#if defined (STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	661	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	662	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	663	SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
vladvana	0:23d1f73bf130	664	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	665	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
vladvana	0:23d1f73bf130	666	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	667	} while(0)
vladvana	0:23d1f73bf130	668
vladvana	0:23d1f73bf130	669
vladvana	0:23d1f73bf130	670	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
vladvana	0:23d1f73bf130	671	#endif /* STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	672
vladvana	0:23d1f73bf130	673	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	674	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	675	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	676	SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
vladvana	0:23d1f73bf130	677	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	678	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
vladvana	0:23d1f73bf130	679	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	680	} while(0)
vladvana	0:23d1f73bf130	681
vladvana	0:23d1f73bf130	682
vladvana	0:23d1f73bf130	683	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
vladvana	0:23d1f73bf130	684	#endif /* STM32F105xC \|\| STM32F107xC*/
vladvana	0:23d1f73bf130	685
vladvana	0:23d1f73bf130	686	#if defined(STM32F107xC)
vladvana	0:23d1f73bf130	687	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	688	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	689	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
vladvana	0:23d1f73bf130	690	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	691	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
vladvana	0:23d1f73bf130	692	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	693	} while(0)
vladvana	0:23d1f73bf130	694
vladvana	0:23d1f73bf130	695	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	696	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	697	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
vladvana	0:23d1f73bf130	698	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	699	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
vladvana	0:23d1f73bf130	700	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	701	} while(0)
vladvana	0:23d1f73bf130	702
vladvana	0:23d1f73bf130	703	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	704	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	705	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
vladvana	0:23d1f73bf130	706	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	707	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
vladvana	0:23d1f73bf130	708	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	709	} while(0)
vladvana	0:23d1f73bf130	710
vladvana	0:23d1f73bf130	711	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
vladvana	0:23d1f73bf130	712	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
vladvana	0:23d1f73bf130	713	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
vladvana	0:23d1f73bf130	714
vladvana	0:23d1f73bf130	715	/**
vladvana	0:23d1f73bf130	716	* @brief Enable ETHERNET clock.
vladvana	0:23d1f73bf130	717	*/
vladvana	0:23d1f73bf130	718	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	719	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
vladvana	0:23d1f73bf130	720	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
vladvana	0:23d1f73bf130	721	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
vladvana	0:23d1f73bf130	722	} while(0)
vladvana	0:23d1f73bf130	723	/**
vladvana	0:23d1f73bf130	724	* @brief Disable ETHERNET clock.
vladvana	0:23d1f73bf130	725	*/
vladvana	0:23d1f73bf130	726	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
vladvana	0:23d1f73bf130	727	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
vladvana	0:23d1f73bf130	728	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
vladvana	0:23d1f73bf130	729	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
vladvana	0:23d1f73bf130	730	} while(0)
vladvana	0:23d1f73bf130	731
vladvana	0:23d1f73bf130	732	#endif /* STM32F107xC*/
vladvana	0:23d1f73bf130	733
vladvana	0:23d1f73bf130	734	/**
vladvana	0:23d1f73bf130	735	* @}
vladvana	0:23d1f73bf130	736	*/
vladvana	0:23d1f73bf130	737
vladvana	0:23d1f73bf130	738	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
vladvana	0:23d1f73bf130	739	* @brief Get the enable or disable status of the AHB1 peripheral clock.
vladvana	0:23d1f73bf130	740	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	741	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	742	* using it.
vladvana	0:23d1f73bf130	743	* @{
vladvana	0:23d1f73bf130	744	*/
vladvana	0:23d1f73bf130	745
vladvana	0:23d1f73bf130	746	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	747	defined (STM32F105xC) \|\| defined (STM32F107xC) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	748	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
vladvana	0:23d1f73bf130	749	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
vladvana	0:23d1f73bf130	750	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F100xE */
vladvana	0:23d1f73bf130	751	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	752	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
vladvana	0:23d1f73bf130	753	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
vladvana	0:23d1f73bf130	754	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F100xE */
vladvana	0:23d1f73bf130	755	#if defined (STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	756	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
vladvana	0:23d1f73bf130	757	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
vladvana	0:23d1f73bf130	758	#endif /* STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	759	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	760	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
vladvana	0:23d1f73bf130	761	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
vladvana	0:23d1f73bf130	762	#endif /* STM32F105xC \|\| STM32F107xC*/
vladvana	0:23d1f73bf130	763	#if defined(STM32F107xC)
vladvana	0:23d1f73bf130	764	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
vladvana	0:23d1f73bf130	765	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
vladvana	0:23d1f73bf130	766	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
vladvana	0:23d1f73bf130	767	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
vladvana	0:23d1f73bf130	768	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
vladvana	0:23d1f73bf130	769	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
vladvana	0:23d1f73bf130	770	#endif /* STM32F107xC*/
vladvana	0:23d1f73bf130	771
vladvana	0:23d1f73bf130	772	/**
vladvana	0:23d1f73bf130	773	* @}
vladvana	0:23d1f73bf130	774	*/
vladvana	0:23d1f73bf130	775
vladvana	0:23d1f73bf130	776	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
vladvana	0:23d1f73bf130	777	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
vladvana	0:23d1f73bf130	778	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	779	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	780	* using it.
vladvana	0:23d1f73bf130	781	* @{
vladvana	0:23d1f73bf130	782	*/
vladvana	0:23d1f73bf130	783
vladvana	0:23d1f73bf130	784	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	785	defined(STM32F105xC) \|\|defined (STM32F107xC)
vladvana	0:23d1f73bf130	786	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	787	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	788	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
vladvana	0:23d1f73bf130	789	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	790	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
vladvana	0:23d1f73bf130	791	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	792	} while(0)
vladvana	0:23d1f73bf130	793
vladvana	0:23d1f73bf130	794	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
vladvana	0:23d1f73bf130	795	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	796
vladvana	0:23d1f73bf130	797	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| \
vladvana	0:23d1f73bf130	798	defined(STM32F101xG) \|\| defined(STM32F102xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
vladvana	0:23d1f73bf130	799	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	800	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	801	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	802	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
vladvana	0:23d1f73bf130	803	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	804	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
vladvana	0:23d1f73bf130	805	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	806	} while(0)
vladvana	0:23d1f73bf130	807
vladvana	0:23d1f73bf130	808	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	809	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	810	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
vladvana	0:23d1f73bf130	811	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	812	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
vladvana	0:23d1f73bf130	813	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	814	} while(0)
vladvana	0:23d1f73bf130	815
vladvana	0:23d1f73bf130	816	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	817	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	818	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
vladvana	0:23d1f73bf130	819	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	820	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
vladvana	0:23d1f73bf130	821	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	822	} while(0)
vladvana	0:23d1f73bf130	823
vladvana	0:23d1f73bf130	824	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	825	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	826	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
vladvana	0:23d1f73bf130	827	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	828	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
vladvana	0:23d1f73bf130	829	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	830	} while(0)
vladvana	0:23d1f73bf130	831
vladvana	0:23d1f73bf130	832	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
vladvana	0:23d1f73bf130	833	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
vladvana	0:23d1f73bf130	834	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
vladvana	0:23d1f73bf130	835	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
vladvana	0:23d1f73bf130	836	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	837
vladvana	0:23d1f73bf130	838	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	839	#define __HAL_RCC_USB_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	840	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	841	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
vladvana	0:23d1f73bf130	842	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	843	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
vladvana	0:23d1f73bf130	844	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	845	} while(0)
vladvana	0:23d1f73bf130	846
vladvana	0:23d1f73bf130	847	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
vladvana	0:23d1f73bf130	848	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	849
vladvana	0:23d1f73bf130	850	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	851	defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	852	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	853	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	854	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
vladvana	0:23d1f73bf130	855	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	856	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
vladvana	0:23d1f73bf130	857	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	858	} while(0)
vladvana	0:23d1f73bf130	859
vladvana	0:23d1f73bf130	860	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	861	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	862	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
vladvana	0:23d1f73bf130	863	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	864	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
vladvana	0:23d1f73bf130	865	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	866	} while(0)
vladvana	0:23d1f73bf130	867
vladvana	0:23d1f73bf130	868	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	869	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	870	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
vladvana	0:23d1f73bf130	871	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	872	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
vladvana	0:23d1f73bf130	873	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	874	} while(0)
vladvana	0:23d1f73bf130	875
vladvana	0:23d1f73bf130	876	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	877	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	878	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
vladvana	0:23d1f73bf130	879	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	880	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
vladvana	0:23d1f73bf130	881	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	882	} while(0)
vladvana	0:23d1f73bf130	883
vladvana	0:23d1f73bf130	884	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	885	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	886	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
vladvana	0:23d1f73bf130	887	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	888	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
vladvana	0:23d1f73bf130	889	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	890	} while(0)
vladvana	0:23d1f73bf130	891
vladvana	0:23d1f73bf130	892	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	893	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	894	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
vladvana	0:23d1f73bf130	895	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	896	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
vladvana	0:23d1f73bf130	897	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	898	} while(0)
vladvana	0:23d1f73bf130	899
vladvana	0:23d1f73bf130	900	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	901	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	902	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
vladvana	0:23d1f73bf130	903	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	904	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
vladvana	0:23d1f73bf130	905	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	906	} while(0)
vladvana	0:23d1f73bf130	907
vladvana	0:23d1f73bf130	908	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
vladvana	0:23d1f73bf130	909	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
vladvana	0:23d1f73bf130	910	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
vladvana	0:23d1f73bf130	911	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
vladvana	0:23d1f73bf130	912	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
vladvana	0:23d1f73bf130	913	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
vladvana	0:23d1f73bf130	914	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
vladvana	0:23d1f73bf130	915	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	916
vladvana	0:23d1f73bf130	917	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	918	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	919	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	920	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
vladvana	0:23d1f73bf130	921	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	922	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
vladvana	0:23d1f73bf130	923	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	924	} while(0)
vladvana	0:23d1f73bf130	925
vladvana	0:23d1f73bf130	926	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	927	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	928	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
vladvana	0:23d1f73bf130	929	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	930	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
vladvana	0:23d1f73bf130	931	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	932	} while(0)
vladvana	0:23d1f73bf130	933
vladvana	0:23d1f73bf130	934	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	935	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	936	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
vladvana	0:23d1f73bf130	937	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	938	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
vladvana	0:23d1f73bf130	939	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	940	} while(0)
vladvana	0:23d1f73bf130	941
vladvana	0:23d1f73bf130	942	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	943	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
vladvana	0:23d1f73bf130	945	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
vladvana	0:23d1f73bf130	947	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	948	} while(0)
vladvana	0:23d1f73bf130	949
vladvana	0:23d1f73bf130	950	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
vladvana	0:23d1f73bf130	951	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
vladvana	0:23d1f73bf130	952	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
vladvana	0:23d1f73bf130	953	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
vladvana	0:23d1f73bf130	954	#endif /* STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	955
vladvana	0:23d1f73bf130	956	#ifdef STM32F100xE
vladvana	0:23d1f73bf130	957	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	958	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	959	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
vladvana	0:23d1f73bf130	960	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	961	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
vladvana	0:23d1f73bf130	962	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	963	} while(0)
vladvana	0:23d1f73bf130	964
vladvana	0:23d1f73bf130	965	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	966	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	967	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
vladvana	0:23d1f73bf130	968	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	969	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
vladvana	0:23d1f73bf130	970	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	971	} while(0)
vladvana	0:23d1f73bf130	972
vladvana	0:23d1f73bf130	973	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	974	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	975	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
vladvana	0:23d1f73bf130	976	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	977	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
vladvana	0:23d1f73bf130	978	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	979	} while(0)
vladvana	0:23d1f73bf130	980
vladvana	0:23d1f73bf130	981	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	982	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	983	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
vladvana	0:23d1f73bf130	984	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	985	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
vladvana	0:23d1f73bf130	986	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	987	} while(0)
vladvana	0:23d1f73bf130	988
vladvana	0:23d1f73bf130	989	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	990	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	991	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
vladvana	0:23d1f73bf130	992	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	993	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
vladvana	0:23d1f73bf130	994	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	995	} while(0)
vladvana	0:23d1f73bf130	996
vladvana	0:23d1f73bf130	997	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	998	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	999	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
vladvana	0:23d1f73bf130	1000	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1001	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
vladvana	0:23d1f73bf130	1002	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1003	} while(0)
vladvana	0:23d1f73bf130	1004
vladvana	0:23d1f73bf130	1005	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1006	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1007	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
vladvana	0:23d1f73bf130	1008	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1009	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
vladvana	0:23d1f73bf130	1010	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1011	} while(0)
vladvana	0:23d1f73bf130	1012
vladvana	0:23d1f73bf130	1013	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
vladvana	0:23d1f73bf130	1014	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
vladvana	0:23d1f73bf130	1015	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
vladvana	0:23d1f73bf130	1016	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
vladvana	0:23d1f73bf130	1017	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
vladvana	0:23d1f73bf130	1018	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
vladvana	0:23d1f73bf130	1019	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
vladvana	0:23d1f73bf130	1020	#endif /* STM32F100xE */
vladvana	0:23d1f73bf130	1021
vladvana	0:23d1f73bf130	1022	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1023	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1024	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1025	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
vladvana	0:23d1f73bf130	1026	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1027	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
vladvana	0:23d1f73bf130	1028	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1029	} while(0)
vladvana	0:23d1f73bf130	1030
vladvana	0:23d1f73bf130	1031	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
vladvana	0:23d1f73bf130	1032	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1033
vladvana	0:23d1f73bf130	1034	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1035	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1036	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1037	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
vladvana	0:23d1f73bf130	1038	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1039	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
vladvana	0:23d1f73bf130	1040	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1041	} while(0)
vladvana	0:23d1f73bf130	1042
vladvana	0:23d1f73bf130	1043	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1044	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1045	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
vladvana	0:23d1f73bf130	1046	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1047	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
vladvana	0:23d1f73bf130	1048	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1049	} while(0)
vladvana	0:23d1f73bf130	1050
vladvana	0:23d1f73bf130	1051	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1052	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1053	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
vladvana	0:23d1f73bf130	1054	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1055	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
vladvana	0:23d1f73bf130	1056	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1057	} while(0)
vladvana	0:23d1f73bf130	1058
vladvana	0:23d1f73bf130	1059	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
vladvana	0:23d1f73bf130	1060	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
vladvana	0:23d1f73bf130	1061	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
vladvana	0:23d1f73bf130	1062	#endif /* STM32F101xG \|\| STM32F103xG*/
vladvana	0:23d1f73bf130	1063
vladvana	0:23d1f73bf130	1064	/**
vladvana	0:23d1f73bf130	1065	* @}
vladvana	0:23d1f73bf130	1066	*/
vladvana	0:23d1f73bf130	1067
vladvana	0:23d1f73bf130	1068	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
vladvana	0:23d1f73bf130	1069	* @brief Get the enable or disable status of the APB1 peripheral clock.
vladvana	0:23d1f73bf130	1070	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	1071	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	1072	* using it.
vladvana	0:23d1f73bf130	1073	* @{
vladvana	0:23d1f73bf130	1074	*/
vladvana	0:23d1f73bf130	1075
vladvana	0:23d1f73bf130	1076	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	1077	defined(STM32F105xC) \|\|defined (STM32F107xC)
vladvana	0:23d1f73bf130	1078	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
vladvana	0:23d1f73bf130	1079	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
vladvana	0:23d1f73bf130	1080	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1081	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| \
vladvana	0:23d1f73bf130	1082	defined(STM32F101xG) \|\| defined(STM32F102xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
vladvana	0:23d1f73bf130	1083	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1084	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
vladvana	0:23d1f73bf130	1085	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
vladvana	0:23d1f73bf130	1086	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
vladvana	0:23d1f73bf130	1087	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
vladvana	0:23d1f73bf130	1088	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
vladvana	0:23d1f73bf130	1089	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
vladvana	0:23d1f73bf130	1090	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
vladvana	0:23d1f73bf130	1091	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
vladvana	0:23d1f73bf130	1092	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1093	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1094	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
vladvana	0:23d1f73bf130	1095	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
vladvana	0:23d1f73bf130	1096	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1097	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	1098	defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1099	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
vladvana	0:23d1f73bf130	1100	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
vladvana	0:23d1f73bf130	1101	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
vladvana	0:23d1f73bf130	1102	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
vladvana	0:23d1f73bf130	1103	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
vladvana	0:23d1f73bf130	1104	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
vladvana	0:23d1f73bf130	1105	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
vladvana	0:23d1f73bf130	1106	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
vladvana	0:23d1f73bf130	1107	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
vladvana	0:23d1f73bf130	1108	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
vladvana	0:23d1f73bf130	1109	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
vladvana	0:23d1f73bf130	1110	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
vladvana	0:23d1f73bf130	1111	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
vladvana	0:23d1f73bf130	1112	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
vladvana	0:23d1f73bf130	1113	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1114	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	1115	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
vladvana	0:23d1f73bf130	1116	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
vladvana	0:23d1f73bf130	1117	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
vladvana	0:23d1f73bf130	1118	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
vladvana	0:23d1f73bf130	1119	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
vladvana	0:23d1f73bf130	1120	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
vladvana	0:23d1f73bf130	1121	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
vladvana	0:23d1f73bf130	1122	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
vladvana	0:23d1f73bf130	1123	#endif /* STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	1124	#ifdef STM32F100xE
vladvana	0:23d1f73bf130	1125	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
vladvana	0:23d1f73bf130	1126	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
vladvana	0:23d1f73bf130	1127	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
vladvana	0:23d1f73bf130	1128	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
vladvana	0:23d1f73bf130	1129	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
vladvana	0:23d1f73bf130	1130	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
vladvana	0:23d1f73bf130	1131	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
vladvana	0:23d1f73bf130	1132	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
vladvana	0:23d1f73bf130	1133	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
vladvana	0:23d1f73bf130	1134	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
vladvana	0:23d1f73bf130	1135	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
vladvana	0:23d1f73bf130	1136	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
vladvana	0:23d1f73bf130	1137	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
vladvana	0:23d1f73bf130	1138	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
vladvana	0:23d1f73bf130	1139	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
vladvana	0:23d1f73bf130	1140	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
vladvana	0:23d1f73bf130	1141	#endif /* STM32F100xE */
vladvana	0:23d1f73bf130	1142	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1143	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
vladvana	0:23d1f73bf130	1144	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
vladvana	0:23d1f73bf130	1145	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1146	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1147	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
vladvana	0:23d1f73bf130	1148	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
vladvana	0:23d1f73bf130	1149	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
vladvana	0:23d1f73bf130	1150	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
vladvana	0:23d1f73bf130	1151	#endif /* STM32F101xG \|\| STM32F103xG*/
vladvana	0:23d1f73bf130	1152
vladvana	0:23d1f73bf130	1153	/**
vladvana	0:23d1f73bf130	1154	* @}
vladvana	0:23d1f73bf130	1155	*/
vladvana	0:23d1f73bf130	1156
vladvana	0:23d1f73bf130	1157	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
vladvana	0:23d1f73bf130	1158	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
vladvana	0:23d1f73bf130	1159	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	1160	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	1161	* using it.
vladvana	0:23d1f73bf130	1162	* @{
vladvana	0:23d1f73bf130	1163	*/
vladvana	0:23d1f73bf130	1164
vladvana	0:23d1f73bf130	1165	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F105xC) \|\| \
vladvana	0:23d1f73bf130	1166	defined(STM32F107xC) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1167	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1168	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1169	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
vladvana	0:23d1f73bf130	1170	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1171	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
vladvana	0:23d1f73bf130	1172	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1173	} while(0)
vladvana	0:23d1f73bf130	1174
vladvana	0:23d1f73bf130	1175	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
vladvana	0:23d1f73bf130	1176	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1177
vladvana	0:23d1f73bf130	1178	#if defined (STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	1179	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1180	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1181	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
vladvana	0:23d1f73bf130	1182	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1183	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
vladvana	0:23d1f73bf130	1184	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1185	} while(0)
vladvana	0:23d1f73bf130	1186
vladvana	0:23d1f73bf130	1187	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1188	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1189	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
vladvana	0:23d1f73bf130	1190	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1191	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
vladvana	0:23d1f73bf130	1192	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1193	} while(0)
vladvana	0:23d1f73bf130	1194
vladvana	0:23d1f73bf130	1195	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1196	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1197	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
vladvana	0:23d1f73bf130	1198	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1199	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
vladvana	0:23d1f73bf130	1200	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1201	} while(0)
vladvana	0:23d1f73bf130	1202
vladvana	0:23d1f73bf130	1203	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
vladvana	0:23d1f73bf130	1204	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
vladvana	0:23d1f73bf130	1205	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
vladvana	0:23d1f73bf130	1206	#endif /* STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	1207
vladvana	0:23d1f73bf130	1208	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| \
vladvana	0:23d1f73bf130	1209	defined(STM32F100xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	1210	defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1211	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1212	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1213	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
vladvana	0:23d1f73bf130	1214	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1215	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
vladvana	0:23d1f73bf130	1216	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1217	} while(0)
vladvana	0:23d1f73bf130	1218
vladvana	0:23d1f73bf130	1219	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
vladvana	0:23d1f73bf130	1220	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1221
vladvana	0:23d1f73bf130	1222	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1223	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1224	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1225	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
vladvana	0:23d1f73bf130	1226	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1227	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
vladvana	0:23d1f73bf130	1228	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1229	} while(0)
vladvana	0:23d1f73bf130	1230
vladvana	0:23d1f73bf130	1231	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1232	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1233	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
vladvana	0:23d1f73bf130	1234	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1235	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
vladvana	0:23d1f73bf130	1236	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1237	} while(0)
vladvana	0:23d1f73bf130	1238
vladvana	0:23d1f73bf130	1239	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
vladvana	0:23d1f73bf130	1240	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
vladvana	0:23d1f73bf130	1241	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
vladvana	0:23d1f73bf130	1242
vladvana	0:23d1f73bf130	1243	#if defined (STM32F103xE) \|\| defined (STM32F103xG)
vladvana	0:23d1f73bf130	1244	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1245	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1246	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
vladvana	0:23d1f73bf130	1247	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1248	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
vladvana	0:23d1f73bf130	1249	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1250	} while(0)
vladvana	0:23d1f73bf130	1251
vladvana	0:23d1f73bf130	1252	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1253	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1254	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
vladvana	0:23d1f73bf130	1255	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1256	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
vladvana	0:23d1f73bf130	1257	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1258	} while(0)
vladvana	0:23d1f73bf130	1259
vladvana	0:23d1f73bf130	1260	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
vladvana	0:23d1f73bf130	1261	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
vladvana	0:23d1f73bf130	1262	#endif /* STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1263
vladvana	0:23d1f73bf130	1264	#if defined (STM32F100xE)
vladvana	0:23d1f73bf130	1265	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1266	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1267	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
vladvana	0:23d1f73bf130	1268	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1269	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
vladvana	0:23d1f73bf130	1270	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1271	} while(0)
vladvana	0:23d1f73bf130	1272
vladvana	0:23d1f73bf130	1273	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1274	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1275	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
vladvana	0:23d1f73bf130	1276	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1277	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
vladvana	0:23d1f73bf130	1278	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1279	} while(0)
vladvana	0:23d1f73bf130	1280
vladvana	0:23d1f73bf130	1281	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
vladvana	0:23d1f73bf130	1282	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
vladvana	0:23d1f73bf130	1283	#endif /* STM32F100xE */
vladvana	0:23d1f73bf130	1284
vladvana	0:23d1f73bf130	1285	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1286	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1287	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1288	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
vladvana	0:23d1f73bf130	1289	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1290	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
vladvana	0:23d1f73bf130	1291	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1292	} while(0)
vladvana	0:23d1f73bf130	1293
vladvana	0:23d1f73bf130	1294	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1295	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1296	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
vladvana	0:23d1f73bf130	1297	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1298	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
vladvana	0:23d1f73bf130	1299	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1300	} while(0)
vladvana	0:23d1f73bf130	1301
vladvana	0:23d1f73bf130	1302	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	1303	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	1304	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
vladvana	0:23d1f73bf130	1305	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	1306	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
vladvana	0:23d1f73bf130	1307	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	1308	} while(0)
vladvana	0:23d1f73bf130	1309
vladvana	0:23d1f73bf130	1310	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
vladvana	0:23d1f73bf130	1311	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
vladvana	0:23d1f73bf130	1312	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
vladvana	0:23d1f73bf130	1313	#endif /* STM32F101xG \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1314
vladvana	0:23d1f73bf130	1315	/**
vladvana	0:23d1f73bf130	1316	* @}
vladvana	0:23d1f73bf130	1317	*/
vladvana	0:23d1f73bf130	1318
vladvana	0:23d1f73bf130	1319	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
vladvana	0:23d1f73bf130	1320	* @brief Get the enable or disable status of the APB2 peripheral clock.
vladvana	0:23d1f73bf130	1321	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	1322	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	1323	* using it.
vladvana	0:23d1f73bf130	1324	* @{
vladvana	0:23d1f73bf130	1325	*/
vladvana	0:23d1f73bf130	1326
vladvana	0:23d1f73bf130	1327	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F105xC) \|\| \
vladvana	0:23d1f73bf130	1328	defined(STM32F107xC) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1329	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
vladvana	0:23d1f73bf130	1330	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
vladvana	0:23d1f73bf130	1331	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1332	#if defined (STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	1333	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
vladvana	0:23d1f73bf130	1334	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
vladvana	0:23d1f73bf130	1335	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
vladvana	0:23d1f73bf130	1336	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
vladvana	0:23d1f73bf130	1337	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
vladvana	0:23d1f73bf130	1338	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
vladvana	0:23d1f73bf130	1339	#endif /* STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	1340	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| \
vladvana	0:23d1f73bf130	1341	defined(STM32F100xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	1342	defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1343	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
vladvana	0:23d1f73bf130	1344	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
vladvana	0:23d1f73bf130	1345	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1346	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1347	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
vladvana	0:23d1f73bf130	1348	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
vladvana	0:23d1f73bf130	1349	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
vladvana	0:23d1f73bf130	1350	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
vladvana	0:23d1f73bf130	1351	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
vladvana	0:23d1f73bf130	1352	#if defined (STM32F103xE) \|\| defined (STM32F103xG)
vladvana	0:23d1f73bf130	1353	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
vladvana	0:23d1f73bf130	1354	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
vladvana	0:23d1f73bf130	1355	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
vladvana	0:23d1f73bf130	1356	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
vladvana	0:23d1f73bf130	1357	#endif /* STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1358	#if defined (STM32F100xE)
vladvana	0:23d1f73bf130	1359	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
vladvana	0:23d1f73bf130	1360	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
vladvana	0:23d1f73bf130	1361	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
vladvana	0:23d1f73bf130	1362	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
vladvana	0:23d1f73bf130	1363	#endif /* STM32F100xE */
vladvana	0:23d1f73bf130	1364	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1365	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
vladvana	0:23d1f73bf130	1366	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
vladvana	0:23d1f73bf130	1367	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
vladvana	0:23d1f73bf130	1368	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
vladvana	0:23d1f73bf130	1369	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
vladvana	0:23d1f73bf130	1370	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
vladvana	0:23d1f73bf130	1371	#endif /* STM32F101xG \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1372
vladvana	0:23d1f73bf130	1373	/**
vladvana	0:23d1f73bf130	1374	* @}
vladvana	0:23d1f73bf130	1375	*/
vladvana	0:23d1f73bf130	1376
vladvana	0:23d1f73bf130	1377	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1378	/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
vladvana	0:23d1f73bf130	1379	* @brief Force or release AHB peripheral reset.
vladvana	0:23d1f73bf130	1380	* @{
vladvana	0:23d1f73bf130	1381	*/
vladvana	0:23d1f73bf130	1382	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
vladvana	0:23d1f73bf130	1383	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_OTGFSRST))
vladvana	0:23d1f73bf130	1384	#if defined(STM32F107xC)
vladvana	0:23d1f73bf130	1385	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ETHMACRST))
vladvana	0:23d1f73bf130	1386	#endif /* STM32F107xC */
vladvana	0:23d1f73bf130	1387
vladvana	0:23d1f73bf130	1388	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
vladvana	0:23d1f73bf130	1389	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
vladvana	0:23d1f73bf130	1390	#if defined(STM32F107xC)
vladvana	0:23d1f73bf130	1391	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
vladvana	0:23d1f73bf130	1392	#endif /* STM32F107xC */
vladvana	0:23d1f73bf130	1393
vladvana	0:23d1f73bf130	1394	/**
vladvana	0:23d1f73bf130	1395	* @}
vladvana	0:23d1f73bf130	1396	*/
vladvana	0:23d1f73bf130	1397	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1398
vladvana	0:23d1f73bf130	1399	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
vladvana	0:23d1f73bf130	1400	* @brief Force or release APB1 peripheral reset.
vladvana	0:23d1f73bf130	1401	* @{
vladvana	0:23d1f73bf130	1402	*/
vladvana	0:23d1f73bf130	1403
vladvana	0:23d1f73bf130	1404	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	1405	defined(STM32F105xC) \|\|defined (STM32F107xC)
vladvana	0:23d1f73bf130	1406	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
vladvana	0:23d1f73bf130	1407
vladvana	0:23d1f73bf130	1408	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
vladvana	0:23d1f73bf130	1409	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1410
vladvana	0:23d1f73bf130	1411	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| \
vladvana	0:23d1f73bf130	1412	defined(STM32F101xG) \|\| defined(STM32F102xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
vladvana	0:23d1f73bf130	1413	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1414	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
vladvana	0:23d1f73bf130	1415	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
vladvana	0:23d1f73bf130	1416	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
vladvana	0:23d1f73bf130	1417	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
vladvana	0:23d1f73bf130	1418
vladvana	0:23d1f73bf130	1419	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
vladvana	0:23d1f73bf130	1420	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
vladvana	0:23d1f73bf130	1421	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
vladvana	0:23d1f73bf130	1422	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
vladvana	0:23d1f73bf130	1423	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1424
vladvana	0:23d1f73bf130	1425	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1426	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
vladvana	0:23d1f73bf130	1427	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
vladvana	0:23d1f73bf130	1428	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1429
vladvana	0:23d1f73bf130	1430	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	1431	defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1432	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
vladvana	0:23d1f73bf130	1433	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
vladvana	0:23d1f73bf130	1434	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
vladvana	0:23d1f73bf130	1435	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
vladvana	0:23d1f73bf130	1436	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
vladvana	0:23d1f73bf130	1437	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
vladvana	0:23d1f73bf130	1438	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
vladvana	0:23d1f73bf130	1439
vladvana	0:23d1f73bf130	1440	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
vladvana	0:23d1f73bf130	1441	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
vladvana	0:23d1f73bf130	1442	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
vladvana	0:23d1f73bf130	1443	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
vladvana	0:23d1f73bf130	1444	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
vladvana	0:23d1f73bf130	1445	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
vladvana	0:23d1f73bf130	1446	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
vladvana	0:23d1f73bf130	1447	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1448
vladvana	0:23d1f73bf130	1449	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	1450	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
vladvana	0:23d1f73bf130	1451	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
vladvana	0:23d1f73bf130	1452	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
vladvana	0:23d1f73bf130	1453	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
vladvana	0:23d1f73bf130	1454
vladvana	0:23d1f73bf130	1455	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
vladvana	0:23d1f73bf130	1456	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
vladvana	0:23d1f73bf130	1457	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
vladvana	0:23d1f73bf130	1458	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
vladvana	0:23d1f73bf130	1459	#endif /* STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	1460
vladvana	0:23d1f73bf130	1461	#if defined (STM32F100xE)
vladvana	0:23d1f73bf130	1462	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
vladvana	0:23d1f73bf130	1463	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
vladvana	0:23d1f73bf130	1464	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
vladvana	0:23d1f73bf130	1465	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
vladvana	0:23d1f73bf130	1466	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
vladvana	0:23d1f73bf130	1467	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
vladvana	0:23d1f73bf130	1468	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
vladvana	0:23d1f73bf130	1469
vladvana	0:23d1f73bf130	1470	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
vladvana	0:23d1f73bf130	1471	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
vladvana	0:23d1f73bf130	1472	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
vladvana	0:23d1f73bf130	1473	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
vladvana	0:23d1f73bf130	1474	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
vladvana	0:23d1f73bf130	1475	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
vladvana	0:23d1f73bf130	1476	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
vladvana	0:23d1f73bf130	1477	#endif /* STM32F100xE */
vladvana	0:23d1f73bf130	1478
vladvana	0:23d1f73bf130	1479	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1480	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
vladvana	0:23d1f73bf130	1481
vladvana	0:23d1f73bf130	1482	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
vladvana	0:23d1f73bf130	1483	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1484
vladvana	0:23d1f73bf130	1485	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1486	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
vladvana	0:23d1f73bf130	1487	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
vladvana	0:23d1f73bf130	1488	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
vladvana	0:23d1f73bf130	1489
vladvana	0:23d1f73bf130	1490	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
vladvana	0:23d1f73bf130	1491	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
vladvana	0:23d1f73bf130	1492	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
vladvana	0:23d1f73bf130	1493	#endif /* STM32F101xG \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1494
vladvana	0:23d1f73bf130	1495	/**
vladvana	0:23d1f73bf130	1496	* @}
vladvana	0:23d1f73bf130	1497	*/
vladvana	0:23d1f73bf130	1498
vladvana	0:23d1f73bf130	1499	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
vladvana	0:23d1f73bf130	1500	* @brief Force or release APB2 peripheral reset.
vladvana	0:23d1f73bf130	1501	* @{
vladvana	0:23d1f73bf130	1502	*/
vladvana	0:23d1f73bf130	1503
vladvana	0:23d1f73bf130	1504	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F105xC) \|\| \
vladvana	0:23d1f73bf130	1505	defined(STM32F107xC) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1506	#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC2RST))
vladvana	0:23d1f73bf130	1507
vladvana	0:23d1f73bf130	1508	#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
vladvana	0:23d1f73bf130	1509	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1510
vladvana	0:23d1f73bf130	1511	#if defined (STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	1512	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
vladvana	0:23d1f73bf130	1513	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
vladvana	0:23d1f73bf130	1514	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
vladvana	0:23d1f73bf130	1515
vladvana	0:23d1f73bf130	1516	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
vladvana	0:23d1f73bf130	1517	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
vladvana	0:23d1f73bf130	1518	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
vladvana	0:23d1f73bf130	1519	#endif /* STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	1520
vladvana	0:23d1f73bf130	1521	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| \
vladvana	0:23d1f73bf130	1522	defined(STM32F100xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
vladvana	0:23d1f73bf130	1523	defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1524	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPERST))
vladvana	0:23d1f73bf130	1525
vladvana	0:23d1f73bf130	1526	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
vladvana	0:23d1f73bf130	1527	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1528
vladvana	0:23d1f73bf130	1529	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1530	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPFRST))
vladvana	0:23d1f73bf130	1531	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPGRST))
vladvana	0:23d1f73bf130	1532
vladvana	0:23d1f73bf130	1533	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
vladvana	0:23d1f73bf130	1534	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
vladvana	0:23d1f73bf130	1535	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
vladvana	0:23d1f73bf130	1536
vladvana	0:23d1f73bf130	1537	#if defined (STM32F103xE) \|\| defined (STM32F103xG)
vladvana	0:23d1f73bf130	1538	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
vladvana	0:23d1f73bf130	1539	#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC3RST))
vladvana	0:23d1f73bf130	1540
vladvana	0:23d1f73bf130	1541	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
vladvana	0:23d1f73bf130	1542	#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
vladvana	0:23d1f73bf130	1543	#endif /* STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1544
vladvana	0:23d1f73bf130	1545	#if defined (STM32F100xE)
vladvana	0:23d1f73bf130	1546	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPFRST))
vladvana	0:23d1f73bf130	1547	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPGRST))
vladvana	0:23d1f73bf130	1548
vladvana	0:23d1f73bf130	1549	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
vladvana	0:23d1f73bf130	1550	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
vladvana	0:23d1f73bf130	1551	#endif /* STM32F100xE */
vladvana	0:23d1f73bf130	1552
vladvana	0:23d1f73bf130	1553	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1554	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
vladvana	0:23d1f73bf130	1555	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
vladvana	0:23d1f73bf130	1556	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
vladvana	0:23d1f73bf130	1557
vladvana	0:23d1f73bf130	1558	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
vladvana	0:23d1f73bf130	1559	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
vladvana	0:23d1f73bf130	1560	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
vladvana	0:23d1f73bf130	1561	#endif /* STM32F101xG \|\| STM32F103xG*/
vladvana	0:23d1f73bf130	1562
vladvana	0:23d1f73bf130	1563	/**
vladvana	0:23d1f73bf130	1564	* @}
vladvana	0:23d1f73bf130	1565	*/
vladvana	0:23d1f73bf130	1566
vladvana	0:23d1f73bf130	1567	/** @defgroup RCCEx_HSE_Configuration HSE Configuration
vladvana	0:23d1f73bf130	1568	* @{
vladvana	0:23d1f73bf130	1569	*/
vladvana	0:23d1f73bf130	1570
vladvana	0:23d1f73bf130	1571	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	1572	/**
vladvana	0:23d1f73bf130	1573	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
vladvana	0:23d1f73bf130	1574	* @note Predivision factor can not be changed if PLL is used as system clock
vladvana	0:23d1f73bf130	1575	* In this case, you have to select another source of the system clock, disable the PLL and
vladvana	0:23d1f73bf130	1576	* then change the HSE predivision factor.
vladvana	0:23d1f73bf130	1577	* @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
vladvana	0:23d1f73bf130	1578	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
vladvana	0:23d1f73bf130	1579	*/
vladvana	0:23d1f73bf130	1580	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
vladvana	0:23d1f73bf130	1581	#else
vladvana	0:23d1f73bf130	1582	/**
vladvana	0:23d1f73bf130	1583	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
vladvana	0:23d1f73bf130	1584	* @note Predivision factor can not be changed if PLL is used as system clock
vladvana	0:23d1f73bf130	1585	* In this case, you have to select another source of the system clock, disable the PLL and
vladvana	0:23d1f73bf130	1586	* then change the HSE predivision factor.
vladvana	0:23d1f73bf130	1587	* @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
vladvana	0:23d1f73bf130	1588	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
vladvana	0:23d1f73bf130	1589	*/
vladvana	0:23d1f73bf130	1590	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
vladvana	0:23d1f73bf130	1591	MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
vladvana	0:23d1f73bf130	1592
vladvana	0:23d1f73bf130	1593	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1594
vladvana	0:23d1f73bf130	1595	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE)
vladvana	0:23d1f73bf130	1596	/**
vladvana	0:23d1f73bf130	1597	* @brief Macro to get prediv1 factor for PLL.
vladvana	0:23d1f73bf130	1598	*/
vladvana	0:23d1f73bf130	1599	#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
vladvana	0:23d1f73bf130	1600
vladvana	0:23d1f73bf130	1601	#else
vladvana	0:23d1f73bf130	1602	/**
vladvana	0:23d1f73bf130	1603	* @brief Macro to get prediv1 factor for PLL.
vladvana	0:23d1f73bf130	1604	*/
vladvana	0:23d1f73bf130	1605	#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
vladvana	0:23d1f73bf130	1606
vladvana	0:23d1f73bf130	1607	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
vladvana	0:23d1f73bf130	1608
vladvana	0:23d1f73bf130	1609	/**
vladvana	0:23d1f73bf130	1610	* @}
vladvana	0:23d1f73bf130	1611	*/
vladvana	0:23d1f73bf130	1612
vladvana	0:23d1f73bf130	1613	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1614	/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
vladvana	0:23d1f73bf130	1615	* @{
vladvana	0:23d1f73bf130	1616	*/
vladvana	0:23d1f73bf130	1617
vladvana	0:23d1f73bf130	1618	/** @brief Macros to enable the main PLLI2S.
vladvana	0:23d1f73bf130	1619	* @note After enabling the main PLLI2S, the application software should wait on
vladvana	0:23d1f73bf130	1620	* PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
vladvana	0:23d1f73bf130	1621	* be used as system clock source.
vladvana	0:23d1f73bf130	1622	* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
vladvana	0:23d1f73bf130	1623	*/
vladvana	0:23d1f73bf130	1624	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
vladvana	0:23d1f73bf130	1625
vladvana	0:23d1f73bf130	1626	/** @brief Macros to disable the main PLLI2S.
vladvana	0:23d1f73bf130	1627	* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
vladvana	0:23d1f73bf130	1628	*/
vladvana	0:23d1f73bf130	1629	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
vladvana	0:23d1f73bf130	1630
vladvana	0:23d1f73bf130	1631	/** @brief macros to configure the main PLLI2S multiplication factor.
vladvana	0:23d1f73bf130	1632	* @note This function must be used only when the main PLLI2S is disabled.
vladvana	0:23d1f73bf130	1633	*
vladvana	0:23d1f73bf130	1634	* @param __PLLI2SMUL__: specifies the multiplication factor for PLLI2S VCO output clock
vladvana	0:23d1f73bf130	1635	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1636	* @arg RCC_PLLI2S_MUL8: PLLI2SVCO = PLLI2S clock entry x 8
vladvana	0:23d1f73bf130	1637	* @arg RCC_PLLI2S_MUL9: PLLI2SVCO = PLLI2S clock entry x 9
vladvana	0:23d1f73bf130	1638	* @arg RCC_PLLI2S_MUL10: PLLI2SVCO = PLLI2S clock entry x 10
vladvana	0:23d1f73bf130	1639	* @arg RCC_PLLI2S_MUL11: PLLI2SVCO = PLLI2S clock entry x 11
vladvana	0:23d1f73bf130	1640	* @arg RCC_PLLI2S_MUL12: PLLI2SVCO = PLLI2S clock entry x 12
vladvana	0:23d1f73bf130	1641	* @arg RCC_PLLI2S_MUL13: PLLI2SVCO = PLLI2S clock entry x 13
vladvana	0:23d1f73bf130	1642	* @arg RCC_PLLI2S_MUL14: PLLI2SVCO = PLLI2S clock entry x 14
vladvana	0:23d1f73bf130	1643	* @arg RCC_PLLI2S_MUL16: PLLI2SVCO = PLLI2S clock entry x 16
vladvana	0:23d1f73bf130	1644	* @arg RCC_PLLI2S_MUL20: PLLI2SVCO = PLLI2S clock entry x 20
vladvana	0:23d1f73bf130	1645	*
vladvana	0:23d1f73bf130	1646	*/
vladvana	0:23d1f73bf130	1647	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
vladvana	0:23d1f73bf130	1648	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
vladvana	0:23d1f73bf130	1649
vladvana	0:23d1f73bf130	1650	/**
vladvana	0:23d1f73bf130	1651	* @}
vladvana	0:23d1f73bf130	1652	*/
vladvana	0:23d1f73bf130	1653
vladvana	0:23d1f73bf130	1654	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1655
vladvana	0:23d1f73bf130	1656	/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
vladvana	0:23d1f73bf130	1657	* @brief Macros to configure clock source of different peripherals.
vladvana	0:23d1f73bf130	1658	* @{
vladvana	0:23d1f73bf130	1659	*/
vladvana	0:23d1f73bf130	1660
vladvana	0:23d1f73bf130	1661	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
vladvana	0:23d1f73bf130	1662	/** @brief Macro to configure the USB clock.
vladvana	0:23d1f73bf130	1663	* @param __USBCLKSOURCE__: specifies the USB clock source.
vladvana	0:23d1f73bf130	1664	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1665	* @arg RCC_USBPLLCLK_DIV1: PLL clock divided by 1 selected as USB clock
vladvana	0:23d1f73bf130	1666	* @arg RCC_USBPLLCLK_DIV1_5: PLL clock divided by 1.5 selected as USB clock
vladvana	0:23d1f73bf130	1667	*/
vladvana	0:23d1f73bf130	1668	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
vladvana	0:23d1f73bf130	1669	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
vladvana	0:23d1f73bf130	1670
vladvana	0:23d1f73bf130	1671	/** @brief Macro to get the USB clock (USBCLK).
vladvana	0:23d1f73bf130	1672	* @retval The clock source can be one of the following values:
vladvana	0:23d1f73bf130	1673	* @arg RCC_USBPLLCLK_DIV1: PLL clock divided by 1 selected as USB clock
vladvana	0:23d1f73bf130	1674	* @arg RCC_USBPLLCLK_DIV1_5: PLL clock divided by 1.5 selected as USB clock
vladvana	0:23d1f73bf130	1675	*/
vladvana	0:23d1f73bf130	1676	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
vladvana	0:23d1f73bf130	1677
vladvana	0:23d1f73bf130	1678	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
vladvana	0:23d1f73bf130	1679
vladvana	0:23d1f73bf130	1680	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1681
vladvana	0:23d1f73bf130	1682	/** @brief Macro to configure the USB OTSclock.
vladvana	0:23d1f73bf130	1683	* @param __USBCLKSOURCE__: specifies the USB clock source.
vladvana	0:23d1f73bf130	1684	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1685	* @arg RCC_USBPLLCLK_DIV2: PLL clock divided by 2 selected as USB OTG FS clock
vladvana	0:23d1f73bf130	1686	* @arg RCC_USBPLLCLK_DIV3: PLL clock divided by 3 selected as USB OTG FS clock
vladvana	0:23d1f73bf130	1687	*/
vladvana	0:23d1f73bf130	1688	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
vladvana	0:23d1f73bf130	1689	MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
vladvana	0:23d1f73bf130	1690
vladvana	0:23d1f73bf130	1691	/** @brief Macro to get the USB clock (USBCLK).
vladvana	0:23d1f73bf130	1692	* @retval The clock source can be one of the following values:
vladvana	0:23d1f73bf130	1693	* @arg RCC_USBPLLCLK_DIV2: PLL clock divided by 2 selected as USB OTG FS clock
vladvana	0:23d1f73bf130	1694	* @arg RCC_USBPLLCLK_DIV3: PLL clock divided by 3 selected as USB OTG FS clock
vladvana	0:23d1f73bf130	1695	*/
vladvana	0:23d1f73bf130	1696	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
vladvana	0:23d1f73bf130	1697
vladvana	0:23d1f73bf130	1698	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1699
vladvana	0:23d1f73bf130	1700	/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
vladvana	0:23d1f73bf130	1701	* @param __ADCCLKSOURCE__: specifies the ADC clock source.
vladvana	0:23d1f73bf130	1702	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1703	* @arg RCC_ADCPCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC clock
vladvana	0:23d1f73bf130	1704	* @arg RCC_ADCPCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC clock
vladvana	0:23d1f73bf130	1705	* @arg RCC_ADCPCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC clock
vladvana	0:23d1f73bf130	1706	* @arg RCC_ADCPCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC clock
vladvana	0:23d1f73bf130	1707	*/
vladvana	0:23d1f73bf130	1708	#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
vladvana	0:23d1f73bf130	1709	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
vladvana	0:23d1f73bf130	1710
vladvana	0:23d1f73bf130	1711	/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
vladvana	0:23d1f73bf130	1712	* @retval The clock source can be one of the following values:
vladvana	0:23d1f73bf130	1713	* @arg RCC_ADCPCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC clock
vladvana	0:23d1f73bf130	1714	* @arg RCC_ADCPCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC clock
vladvana	0:23d1f73bf130	1715	* @arg RCC_ADCPCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC clock
vladvana	0:23d1f73bf130	1716	* @arg RCC_ADCPCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC clock
vladvana	0:23d1f73bf130	1717	*/
vladvana	0:23d1f73bf130	1718	#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
vladvana	0:23d1f73bf130	1719
vladvana	0:23d1f73bf130	1720	/**
vladvana	0:23d1f73bf130	1721	* @}
vladvana	0:23d1f73bf130	1722	*/
vladvana	0:23d1f73bf130	1723
vladvana	0:23d1f73bf130	1724	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1725
vladvana	0:23d1f73bf130	1726	/** @addtogroup RCCEx_HSE_Configuration
vladvana	0:23d1f73bf130	1727	* @{
vladvana	0:23d1f73bf130	1728	*/
vladvana	0:23d1f73bf130	1729
vladvana	0:23d1f73bf130	1730	/**
vladvana	0:23d1f73bf130	1731	* @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
vladvana	0:23d1f73bf130	1732	* @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
vladvana	0:23d1f73bf130	1733	* In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
vladvana	0:23d1f73bf130	1734	* then change the PREDIV2 factor.
vladvana	0:23d1f73bf130	1735	* @param __HSE_PREDIV2_VALUE__: specifies the PREDIV2 value applied to PLL2 & PLLI2S.
vladvana	0:23d1f73bf130	1736	* This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
vladvana	0:23d1f73bf130	1737	*/
vladvana	0:23d1f73bf130	1738	#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
vladvana	0:23d1f73bf130	1739	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
vladvana	0:23d1f73bf130	1740
vladvana	0:23d1f73bf130	1741	/**
vladvana	0:23d1f73bf130	1742	* @brief Macro to get prediv2 factor for PLL2 & PLL3.
vladvana	0:23d1f73bf130	1743	*/
vladvana	0:23d1f73bf130	1744	#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
vladvana	0:23d1f73bf130	1745
vladvana	0:23d1f73bf130	1746	/**
vladvana	0:23d1f73bf130	1747	* @}
vladvana	0:23d1f73bf130	1748	*/
vladvana	0:23d1f73bf130	1749
vladvana	0:23d1f73bf130	1750	/** @addtogroup RCCEx_PLLI2S_Configuration
vladvana	0:23d1f73bf130	1751	* @{
vladvana	0:23d1f73bf130	1752	*/
vladvana	0:23d1f73bf130	1753
vladvana	0:23d1f73bf130	1754	/** @brief Macros to enable the main PLL2.
vladvana	0:23d1f73bf130	1755	* @note After enabling the main PLL2, the application software should wait on
vladvana	0:23d1f73bf130	1756	* PLL2RDY flag to be set indicating that PLL2 clock is stable and can
vladvana	0:23d1f73bf130	1757	* be used as system clock source.
vladvana	0:23d1f73bf130	1758	* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
vladvana	0:23d1f73bf130	1759	*/
vladvana	0:23d1f73bf130	1760	#define __HAL_RCC_PLL2_ENABLE() ((__IO uint32_t ) CR_PLL2ON_BB = ENABLE)
vladvana	0:23d1f73bf130	1761
vladvana	0:23d1f73bf130	1762	/** @brief Macros to disable the main PLL2.
vladvana	0:23d1f73bf130	1763	* @note The main PLL2 can not be disabled if it is used indirectly as system clock source
vladvana	0:23d1f73bf130	1764	* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
vladvana	0:23d1f73bf130	1765	*/
vladvana	0:23d1f73bf130	1766	#define __HAL_RCC_PLL2_DISABLE() ((__IO uint32_t ) CR_PLL2ON_BB = DISABLE)
vladvana	0:23d1f73bf130	1767
vladvana	0:23d1f73bf130	1768	/** @brief macros to configure the main PLL2 multiplication factor.
vladvana	0:23d1f73bf130	1769	* @note This function must be used only when the main PLL2 is disabled.
vladvana	0:23d1f73bf130	1770	*
vladvana	0:23d1f73bf130	1771	* @param __PLL2MUL__: specifies the multiplication factor for PLL2 VCO output clock
vladvana	0:23d1f73bf130	1772	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1773	* @arg RCC_PLL2_MUL8: PLL2VCO = PLL2 clock entry x 8
vladvana	0:23d1f73bf130	1774	* @arg RCC_PLL2_MUL9: PLL2VCO = PLL2 clock entry x 9
vladvana	0:23d1f73bf130	1775	* @arg RCC_PLL2_MUL10: PLL2VCO = PLL2 clock entry x 10
vladvana	0:23d1f73bf130	1776	* @arg RCC_PLL2_MUL11: PLL2VCO = PLL2 clock entry x 11
vladvana	0:23d1f73bf130	1777	* @arg RCC_PLL2_MUL12: PLL2VCO = PLL2 clock entry x 12
vladvana	0:23d1f73bf130	1778	* @arg RCC_PLL2_MUL13: PLL2VCO = PLL2 clock entry x 13
vladvana	0:23d1f73bf130	1779	* @arg RCC_PLL2_MUL14: PLL2VCO = PLL2 clock entry x 14
vladvana	0:23d1f73bf130	1780	* @arg RCC_PLL2_MUL16: PLL2VCO = PLL2 clock entry x 16
vladvana	0:23d1f73bf130	1781	* @arg RCC_PLL2_MUL20: PLL2VCO = PLL2 clock entry x 20
vladvana	0:23d1f73bf130	1782	*
vladvana	0:23d1f73bf130	1783	*/
vladvana	0:23d1f73bf130	1784	#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
vladvana	0:23d1f73bf130	1785	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
vladvana	0:23d1f73bf130	1786
vladvana	0:23d1f73bf130	1787	/**
vladvana	0:23d1f73bf130	1788	* @}
vladvana	0:23d1f73bf130	1789	*/
vladvana	0:23d1f73bf130	1790
vladvana	0:23d1f73bf130	1791	/** @defgroup RCCEx_I2S_Configuration I2S Configuration
vladvana	0:23d1f73bf130	1792	* @brief Macros to configure clock source of I2S peripherals.
vladvana	0:23d1f73bf130	1793	* @{
vladvana	0:23d1f73bf130	1794	*/
vladvana	0:23d1f73bf130	1795
vladvana	0:23d1f73bf130	1796	/** @brief Macro to configure the I2S2 clock.
vladvana	0:23d1f73bf130	1797	* @param __I2S2CLKSOURCE__: specifies the I2S2 clock source.
vladvana	0:23d1f73bf130	1798	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1799	* @arg RCC_I2S2CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
vladvana	0:23d1f73bf130	1800	* @arg RCC_I2S2CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
vladvana	0:23d1f73bf130	1801	*/
vladvana	0:23d1f73bf130	1802	#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
vladvana	0:23d1f73bf130	1803	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
vladvana	0:23d1f73bf130	1804
vladvana	0:23d1f73bf130	1805	/** @brief Macro to get the I2S2 clock (I2S2CLK).
vladvana	0:23d1f73bf130	1806	* @retval The clock source can be one of the following values:
vladvana	0:23d1f73bf130	1807	* @arg RCC_I2S2CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
vladvana	0:23d1f73bf130	1808	* @arg RCC_I2S2CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
vladvana	0:23d1f73bf130	1809	*/
vladvana	0:23d1f73bf130	1810	#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
vladvana	0:23d1f73bf130	1811
vladvana	0:23d1f73bf130	1812	/** @brief Macro to configure the I2S3 clock.
vladvana	0:23d1f73bf130	1813	* @param __I2S2CLKSOURCE__: specifies the I2S3 clock source.
vladvana	0:23d1f73bf130	1814	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1815	* @arg RCC_I2S3CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
vladvana	0:23d1f73bf130	1816	* @arg RCC_I2S3CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
vladvana	0:23d1f73bf130	1817	*/
vladvana	0:23d1f73bf130	1818	#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
vladvana	0:23d1f73bf130	1819	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
vladvana	0:23d1f73bf130	1820
vladvana	0:23d1f73bf130	1821	/** @brief Macro to get the I2S3 clock (I2S3CLK).
vladvana	0:23d1f73bf130	1822	* @retval The clock source can be one of the following values:
vladvana	0:23d1f73bf130	1823	* @arg RCC_I2S3CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
vladvana	0:23d1f73bf130	1824	* @arg RCC_I2S3CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
vladvana	0:23d1f73bf130	1825	*/
vladvana	0:23d1f73bf130	1826	#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
vladvana	0:23d1f73bf130	1827
vladvana	0:23d1f73bf130	1828	/**
vladvana	0:23d1f73bf130	1829	* @}
vladvana	0:23d1f73bf130	1830	*/
vladvana	0:23d1f73bf130	1831
vladvana	0:23d1f73bf130	1832	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1833	/**
vladvana	0:23d1f73bf130	1834	* @}
vladvana	0:23d1f73bf130	1835	*/
vladvana	0:23d1f73bf130	1836
vladvana	0:23d1f73bf130	1837	/* Exported functions --------------------------------------------------------*/
vladvana	0:23d1f73bf130	1838	/** @addtogroup RCCEx_Exported_Functions
vladvana	0:23d1f73bf130	1839	* @{
vladvana	0:23d1f73bf130	1840	*/
vladvana	0:23d1f73bf130	1841
vladvana	0:23d1f73bf130	1842	/** @addtogroup RCCEx_Exported_Functions_Group1
vladvana	0:23d1f73bf130	1843	* @{
vladvana	0:23d1f73bf130	1844	*/
vladvana	0:23d1f73bf130	1845
vladvana	0:23d1f73bf130	1846	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
vladvana	0:23d1f73bf130	1847	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
vladvana	0:23d1f73bf130	1848	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
vladvana	0:23d1f73bf130	1849
vladvana	0:23d1f73bf130	1850	/**
vladvana	0:23d1f73bf130	1851	* @}
vladvana	0:23d1f73bf130	1852	*/
vladvana	0:23d1f73bf130	1853
vladvana	0:23d1f73bf130	1854	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
vladvana	0:23d1f73bf130	1855	/** @addtogroup RCCEx_Exported_Functions_Group2
vladvana	0:23d1f73bf130	1856	* @{
vladvana	0:23d1f73bf130	1857	*/
vladvana	0:23d1f73bf130	1858	HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
vladvana	0:23d1f73bf130	1859	HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
vladvana	0:23d1f73bf130	1860
vladvana	0:23d1f73bf130	1861	/**
vladvana	0:23d1f73bf130	1862	* @}
vladvana	0:23d1f73bf130	1863	*/
vladvana	0:23d1f73bf130	1864
vladvana	0:23d1f73bf130	1865	/** @addtogroup RCCEx_Exported_Functions_Group3
vladvana	0:23d1f73bf130	1866	* @{
vladvana	0:23d1f73bf130	1867	*/
vladvana	0:23d1f73bf130	1868	HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
vladvana	0:23d1f73bf130	1869	HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
vladvana	0:23d1f73bf130	1870
vladvana	0:23d1f73bf130	1871	/**
vladvana	0:23d1f73bf130	1872	* @}
vladvana	0:23d1f73bf130	1873	*/
vladvana	0:23d1f73bf130	1874	#endif /* STM32F105xC \|\| STM32F107xC */
vladvana	0:23d1f73bf130	1875
vladvana	0:23d1f73bf130	1876	/**
vladvana	0:23d1f73bf130	1877	* @}
vladvana	0:23d1f73bf130	1878	*/
vladvana	0:23d1f73bf130	1879
vladvana	0:23d1f73bf130	1880	/**
vladvana	0:23d1f73bf130	1881	* @}
vladvana	0:23d1f73bf130	1882	*/
vladvana	0:23d1f73bf130	1883
vladvana	0:23d1f73bf130	1884	/**
vladvana	0:23d1f73bf130	1885	* @}
vladvana	0:23d1f73bf130	1886	*/
vladvana	0:23d1f73bf130	1887
vladvana	0:23d1f73bf130	1888	#ifdef __cplusplus
vladvana	0:23d1f73bf130	1889	}
vladvana	0:23d1f73bf130	1890	#endif
vladvana	0:23d1f73bf130	1891
vladvana	0:23d1f73bf130	1892	#endif /* __STM32F1xx_HAL_RCC_EX_H */
vladvana	0:23d1f73bf130	1893
vladvana	0:23d1f73bf130	1894	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
vladvana	0:23d1f73bf130	1895

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Type:	Program
Created:	24 Sep 2017
Imports:	1
Forks:	0
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TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc_ex.h@0:23d1f73bf130, 2017-09-24 (annotated)

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