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TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:: vladvana
Date:: Sun Sep 24 12:31:52 2017 +0000
Revision:: 0:23d1f73bf130

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User	Revision	Line number	New contents of line
vladvana	0:23d1f73bf130	1	/**
vladvana	0:23d1f73bf130	2	******************************************************************************
vladvana	0:23d1f73bf130	3	* @file stm32f1xx_hal_rcc.h
vladvana	0:23d1f73bf130	4	* @author MCD Application Team
vladvana	0:23d1f73bf130	5	* @version V1.0.0
vladvana	0:23d1f73bf130	6	* @date 15-December-2014
vladvana	0:23d1f73bf130	7	* @brief Header file of RCC HAL module.
vladvana	0:23d1f73bf130	8	******************************************************************************
vladvana	0:23d1f73bf130	9	* @attention
vladvana	0:23d1f73bf130	10	*
vladvana	0:23d1f73bf130	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana	0:23d1f73bf130	12	*
vladvana	0:23d1f73bf130	13	* Redistribution and use in source and binary forms, with or without modification,
vladvana	0:23d1f73bf130	14	* are permitted provided that the following conditions are met:
vladvana	0:23d1f73bf130	15	* 1. Redistributions of source code must retain the above copyright notice,
vladvana	0:23d1f73bf130	16	* this list of conditions and the following disclaimer.
vladvana	0:23d1f73bf130	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana	0:23d1f73bf130	18	* this list of conditions and the following disclaimer in the documentation
vladvana	0:23d1f73bf130	19	* and/or other materials provided with the distribution.
vladvana	0:23d1f73bf130	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana	0:23d1f73bf130	21	* may be used to endorse or promote products derived from this software
vladvana	0:23d1f73bf130	22	* without specific prior written permission.
vladvana	0:23d1f73bf130	23	*
vladvana	0:23d1f73bf130	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana	0:23d1f73bf130	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana	0:23d1f73bf130	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana	0:23d1f73bf130	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana	0:23d1f73bf130	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana	0:23d1f73bf130	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana	0:23d1f73bf130	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana	0:23d1f73bf130	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana	0:23d1f73bf130	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana	0:23d1f73bf130	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana	0:23d1f73bf130	34	*
vladvana	0:23d1f73bf130	35	******************************************************************************
vladvana	0:23d1f73bf130	36	*/
vladvana	0:23d1f73bf130	37
vladvana	0:23d1f73bf130	38	/* Define to prevent recursive inclusion -------------------------------------*/
vladvana	0:23d1f73bf130	39	#ifndef __STM32F1xx_HAL_RCC_H
vladvana	0:23d1f73bf130	40	#define __STM32F1xx_HAL_RCC_H
vladvana	0:23d1f73bf130	41
vladvana	0:23d1f73bf130	42	#ifdef __cplusplus
vladvana	0:23d1f73bf130	43	extern "C" {
vladvana	0:23d1f73bf130	44	#endif
vladvana	0:23d1f73bf130	45
vladvana	0:23d1f73bf130	46	/* Includes ------------------------------------------------------------------*/
vladvana	0:23d1f73bf130	47	#include "stm32f1xx_hal_def.h"
vladvana	0:23d1f73bf130	48
vladvana	0:23d1f73bf130	49	/** @addtogroup STM32F1xx_HAL_Driver
vladvana	0:23d1f73bf130	50	* @{
vladvana	0:23d1f73bf130	51	*/
vladvana	0:23d1f73bf130	52
vladvana	0:23d1f73bf130	53	/** @addtogroup RCC
vladvana	0:23d1f73bf130	54	* @{
vladvana	0:23d1f73bf130	55	*/
vladvana	0:23d1f73bf130	56
vladvana	0:23d1f73bf130	57	/** @addtogroup RCC_Private_Constants
vladvana	0:23d1f73bf130	58	* @{
vladvana	0:23d1f73bf130	59	*/
vladvana	0:23d1f73bf130	60
vladvana	0:23d1f73bf130	61	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
vladvana	0:23d1f73bf130	62	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
vladvana	0:23d1f73bf130	63	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
vladvana	0:23d1f73bf130	64	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
vladvana	0:23d1f73bf130	65	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
vladvana	0:23d1f73bf130	66	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
vladvana	0:23d1f73bf130	67	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
vladvana	0:23d1f73bf130	68	#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
vladvana	0:23d1f73bf130	69
vladvana	0:23d1f73bf130	70	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
vladvana	0:23d1f73bf130	71	* @brief RCC registers bit address in the alias region
vladvana	0:23d1f73bf130	72	* @{
vladvana	0:23d1f73bf130	73	*/
vladvana	0:23d1f73bf130	74	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
vladvana	0:23d1f73bf130	75	#define RCC_CR_OFFSET 0x00
vladvana	0:23d1f73bf130	76	#define RCC_CFGR_OFFSET 0x04
vladvana	0:23d1f73bf130	77	#define RCC_CIR_OFFSET 0x08
vladvana	0:23d1f73bf130	78	#define RCC_BDCR_OFFSET 0x20
vladvana	0:23d1f73bf130	79	#define RCC_CSR_OFFSET 0x24
vladvana	0:23d1f73bf130	80	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
vladvana	0:23d1f73bf130	81	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
vladvana	0:23d1f73bf130	82	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
vladvana	0:23d1f73bf130	83	#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
vladvana	0:23d1f73bf130	84	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
vladvana	0:23d1f73bf130	85
vladvana	0:23d1f73bf130	86	/* --- CR Register ---*/
vladvana	0:23d1f73bf130	87	/* Alias word address of HSION bit */
vladvana	0:23d1f73bf130	88	#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
vladvana	0:23d1f73bf130	89	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	90	/* Alias word address of HSEON bit */
vladvana	0:23d1f73bf130	91	#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
vladvana	0:23d1f73bf130	92	#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	93	/* Alias word address of CSSON bit */
vladvana	0:23d1f73bf130	94	#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
vladvana	0:23d1f73bf130	95	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	96	/* Alias word address of PLLON bit */
vladvana	0:23d1f73bf130	97	#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
vladvana	0:23d1f73bf130	98	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	99
vladvana	0:23d1f73bf130	100	/* --- CSR Register ---*/
vladvana	0:23d1f73bf130	101	/* Alias word address of LSION bit */
vladvana	0:23d1f73bf130	102	#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
vladvana	0:23d1f73bf130	103	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	104
vladvana	0:23d1f73bf130	105	/* --- BDCR Register ---*/
vladvana	0:23d1f73bf130	106	/* Alias word address of LSEON bit */
vladvana	0:23d1f73bf130	107	#define LSEON_BITNUMBER POSITION_VAL(RCC_BDCR_LSEON)
vladvana	0:23d1f73bf130	108	#define BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	109
vladvana	0:23d1f73bf130	110	/* Alias word address of LSEON bit */
vladvana	0:23d1f73bf130	111	#define LSEBYP_BITNUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
vladvana	0:23d1f73bf130	112	#define BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	113
vladvana	0:23d1f73bf130	114	/* Alias word address of RTCEN bit */
vladvana	0:23d1f73bf130	115	#define RTCEN_BITNUMBER POSITION_VAL(RCC_BDCR_RTCEN)
vladvana	0:23d1f73bf130	116	#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	117
vladvana	0:23d1f73bf130	118	/* Alias word address of BDRST bit */
vladvana	0:23d1f73bf130	119	#define BDRST_BITNUMBER POSITION_VAL(RCC_BDCR_BDRST)
vladvana	0:23d1f73bf130	120	#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (BDRST_BITNUMBER * 4)))
vladvana	0:23d1f73bf130	121
vladvana	0:23d1f73bf130	122	/* CR register byte 2 (Bits[23:16]) base address */
vladvana	0:23d1f73bf130	123	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
vladvana	0:23d1f73bf130	124
vladvana	0:23d1f73bf130	125	/* CIR register byte 1 (Bits[15:8]) base address */
vladvana	0:23d1f73bf130	126	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
vladvana	0:23d1f73bf130	127
vladvana	0:23d1f73bf130	128	/* CIR register byte 2 (Bits[23:16]) base address */
vladvana	0:23d1f73bf130	129	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
vladvana	0:23d1f73bf130	130
vladvana	0:23d1f73bf130	131	/* Defines used for Flags */
vladvana	0:23d1f73bf130	132	#define CR_REG_INDEX ((uint8_t)1)
vladvana	0:23d1f73bf130	133	#define BDCR_REG_INDEX ((uint8_t)2)
vladvana	0:23d1f73bf130	134	#define CSR_REG_INDEX ((uint8_t)3)
vladvana	0:23d1f73bf130	135
vladvana	0:23d1f73bf130	136	#define RCC_FLAG_MASK ((uint8_t)0x1F)
vladvana	0:23d1f73bf130	137
vladvana	0:23d1f73bf130	138	/**
vladvana	0:23d1f73bf130	139	* @}
vladvana	0:23d1f73bf130	140	*/
vladvana	0:23d1f73bf130	141
vladvana	0:23d1f73bf130	142	/** @addtogroup RCC_Private_Macros
vladvana	0:23d1f73bf130	143	* @{
vladvana	0:23d1f73bf130	144	*/
vladvana	0:23d1f73bf130	145
vladvana	0:23d1f73bf130	146	/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
vladvana	0:23d1f73bf130	147	* @{
vladvana	0:23d1f73bf130	148	*/
vladvana	0:23d1f73bf130	149	#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
vladvana	0:23d1f73bf130	150	#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
vladvana	0:23d1f73bf130	151	#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
vladvana	0:23d1f73bf130	152	#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
vladvana	0:23d1f73bf130	153	/**
vladvana	0:23d1f73bf130	154	* @}
vladvana	0:23d1f73bf130	155	*/
vladvana	0:23d1f73bf130	156
vladvana	0:23d1f73bf130	157	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
vladvana	0:23d1f73bf130	158
vladvana	0:23d1f73bf130	159	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
vladvana	0:23d1f73bf130	160
vladvana	0:23d1f73bf130	161	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
vladvana	0:23d1f73bf130	162
vladvana	0:23d1f73bf130	163	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
vladvana	0:23d1f73bf130	164	((__HSE__) == RCC_HSE_BYPASS))
vladvana	0:23d1f73bf130	165
vladvana	0:23d1f73bf130	166	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
vladvana	0:23d1f73bf130	167	((__LSE__) == RCC_LSE_BYPASS))
vladvana	0:23d1f73bf130	168
vladvana	0:23d1f73bf130	169	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) \|\| \
vladvana	0:23d1f73bf130	170	((__SOURCE__) == RCC_PLLSOURCE_HSE))
vladvana	0:23d1f73bf130	171
vladvana	0:23d1f73bf130	172	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
vladvana	0:23d1f73bf130	173	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
vladvana	0:23d1f73bf130	174	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
vladvana	0:23d1f73bf130	175	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
vladvana	0:23d1f73bf130	176	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
vladvana	0:23d1f73bf130	177
vladvana	0:23d1f73bf130	178	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
vladvana	0:23d1f73bf130	179
vladvana	0:23d1f73bf130	180	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
vladvana	0:23d1f73bf130	181	((__PLL__) == RCC_PLL_ON))
vladvana	0:23d1f73bf130	182
vladvana	0:23d1f73bf130	183	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
vladvana	0:23d1f73bf130	184	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
vladvana	0:23d1f73bf130	185	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
vladvana	0:23d1f73bf130	186
vladvana	0:23d1f73bf130	187	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
vladvana	0:23d1f73bf130	188	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
vladvana	0:23d1f73bf130	189	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
vladvana	0:23d1f73bf130	190	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
vladvana	0:23d1f73bf130	191	((__HCLK__) == RCC_SYSCLK_DIV512))
vladvana	0:23d1f73bf130	192
vladvana	0:23d1f73bf130	193	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
vladvana	0:23d1f73bf130	194	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
vladvana	0:23d1f73bf130	195	((__PCLK__) == RCC_HCLK_DIV16))
vladvana	0:23d1f73bf130	196
vladvana	0:23d1f73bf130	197	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
vladvana	0:23d1f73bf130	198
vladvana	0:23d1f73bf130	199	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
vladvana	0:23d1f73bf130	200
vladvana	0:23d1f73bf130	201	/**
vladvana	0:23d1f73bf130	202	* @}
vladvana	0:23d1f73bf130	203	*/
vladvana	0:23d1f73bf130	204
vladvana	0:23d1f73bf130	205	/* Exported types ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	206
vladvana	0:23d1f73bf130	207	/** @defgroup RCC_Exported_Types RCC Exported Types
vladvana	0:23d1f73bf130	208	* @{
vladvana	0:23d1f73bf130	209	*/
vladvana	0:23d1f73bf130	210
vladvana	0:23d1f73bf130	211	/**
vladvana	0:23d1f73bf130	212	* @brief RCC PLL configuration structure definition
vladvana	0:23d1f73bf130	213	*/
vladvana	0:23d1f73bf130	214	typedef struct
vladvana	0:23d1f73bf130	215	{
vladvana	0:23d1f73bf130	216	uint32_t PLLState; /*!< The new state of the PLL.
vladvana	0:23d1f73bf130	217	This parameter can be a value of @ref __HAL_RCC_PLL_CONFIG */
vladvana	0:23d1f73bf130	218
vladvana	0:23d1f73bf130	219	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
vladvana	0:23d1f73bf130	220	This parameter must be a value of @ref RCC_PLL_Clock_Source */
vladvana	0:23d1f73bf130	221
vladvana	0:23d1f73bf130	222	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
vladvana	0:23d1f73bf130	223	This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
vladvana	0:23d1f73bf130	224	} RCC_PLLInitTypeDef;
vladvana	0:23d1f73bf130	225
vladvana	0:23d1f73bf130	226	/**
vladvana	0:23d1f73bf130	227	* @brief RCC System, AHB and APB busses clock configuration structure definition
vladvana	0:23d1f73bf130	228	*/
vladvana	0:23d1f73bf130	229	typedef struct
vladvana	0:23d1f73bf130	230	{
vladvana	0:23d1f73bf130	231	uint32_t ClockType; /*!< The clock to be configured.
vladvana	0:23d1f73bf130	232	This parameter can be a value of @ref RCC_System_Clock_Type */
vladvana	0:23d1f73bf130	233
vladvana	0:23d1f73bf130	234	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
vladvana	0:23d1f73bf130	235	This parameter can be a value of @ref RCC_System_Clock_Source */
vladvana	0:23d1f73bf130	236
vladvana	0:23d1f73bf130	237	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
vladvana	0:23d1f73bf130	238	This parameter can be a value of @ref RCC_AHB_Clock_Source */
vladvana	0:23d1f73bf130	239
vladvana	0:23d1f73bf130	240	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
vladvana	0:23d1f73bf130	241	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
vladvana	0:23d1f73bf130	242
vladvana	0:23d1f73bf130	243	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
vladvana	0:23d1f73bf130	244	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
vladvana	0:23d1f73bf130	245
vladvana	0:23d1f73bf130	246	} RCC_ClkInitTypeDef;
vladvana	0:23d1f73bf130	247
vladvana	0:23d1f73bf130	248	/**
vladvana	0:23d1f73bf130	249	* @}
vladvana	0:23d1f73bf130	250	*/
vladvana	0:23d1f73bf130	251
vladvana	0:23d1f73bf130	252	/**
vladvana	0:23d1f73bf130	253	* @}
vladvana	0:23d1f73bf130	254	*/
vladvana	0:23d1f73bf130	255
vladvana	0:23d1f73bf130	256	/* Exported constants --------------------------------------------------------*/
vladvana	0:23d1f73bf130	257	/** @defgroup RCC_Exported_Constants RCC Exported Constants
vladvana	0:23d1f73bf130	258	* @{
vladvana	0:23d1f73bf130	259	*/
vladvana	0:23d1f73bf130	260
vladvana	0:23d1f73bf130	261	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
vladvana	0:23d1f73bf130	262	* @{
vladvana	0:23d1f73bf130	263	*/
vladvana	0:23d1f73bf130	264
vladvana	0:23d1f73bf130	265	#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
vladvana	0:23d1f73bf130	266	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /!< HSE clock selected as PLL entry clock source /
vladvana	0:23d1f73bf130	267
vladvana	0:23d1f73bf130	268	/**
vladvana	0:23d1f73bf130	269	* @}
vladvana	0:23d1f73bf130	270	*/
vladvana	0:23d1f73bf130	271
vladvana	0:23d1f73bf130	272	/** @defgroup RCC_Oscillator_Type Oscillator Type
vladvana	0:23d1f73bf130	273	* @{
vladvana	0:23d1f73bf130	274	*/
vladvana	0:23d1f73bf130	275	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	276	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
vladvana	0:23d1f73bf130	277	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
vladvana	0:23d1f73bf130	278	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
vladvana	0:23d1f73bf130	279	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
vladvana	0:23d1f73bf130	280
vladvana	0:23d1f73bf130	281	/**
vladvana	0:23d1f73bf130	282	* @}
vladvana	0:23d1f73bf130	283	*/
vladvana	0:23d1f73bf130	284
vladvana	0:23d1f73bf130	285	/** @defgroup __HAL_RCC_HSE_CONFIG HSE Config
vladvana	0:23d1f73bf130	286	* @{
vladvana	0:23d1f73bf130	287	*/
vladvana	0:23d1f73bf130	288	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
vladvana	0:23d1f73bf130	289	#define RCC_HSE_ON ((uint32_t)0x00000001) /!< HSE clock activation /
vladvana	0:23d1f73bf130	290	#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for HSE clock /
vladvana	0:23d1f73bf130	291
vladvana	0:23d1f73bf130	292	/**
vladvana	0:23d1f73bf130	293	* @}
vladvana	0:23d1f73bf130	294	*/
vladvana	0:23d1f73bf130	295
vladvana	0:23d1f73bf130	296	/** @defgroup __HAL_RCC_LSE_CONFIG LSE Config
vladvana	0:23d1f73bf130	297	* @{
vladvana	0:23d1f73bf130	298	*/
vladvana	0:23d1f73bf130	299	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
vladvana	0:23d1f73bf130	300	#define RCC_LSE_ON ((uint32_t)0x00000001) /!< LSE clock activation /
vladvana	0:23d1f73bf130	301	#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for LSE clock /
vladvana	0:23d1f73bf130	302
vladvana	0:23d1f73bf130	303	/**
vladvana	0:23d1f73bf130	304	* @}
vladvana	0:23d1f73bf130	305	*/
vladvana	0:23d1f73bf130	306
vladvana	0:23d1f73bf130	307	/** @defgroup RCC_HSI_Config HSI Config
vladvana	0:23d1f73bf130	308	* @{
vladvana	0:23d1f73bf130	309	*/
vladvana	0:23d1f73bf130	310	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
vladvana	0:23d1f73bf130	311	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
vladvana	0:23d1f73bf130	312
vladvana	0:23d1f73bf130	313	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
vladvana	0:23d1f73bf130	314
vladvana	0:23d1f73bf130	315	/**
vladvana	0:23d1f73bf130	316	* @}
vladvana	0:23d1f73bf130	317	*/
vladvana	0:23d1f73bf130	318
vladvana	0:23d1f73bf130	319	/** @defgroup RCC_LSI_Config LSI Config
vladvana	0:23d1f73bf130	320	* @{
vladvana	0:23d1f73bf130	321	*/
vladvana	0:23d1f73bf130	322	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
vladvana	0:23d1f73bf130	323	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
vladvana	0:23d1f73bf130	324
vladvana	0:23d1f73bf130	325	/**
vladvana	0:23d1f73bf130	326	* @}
vladvana	0:23d1f73bf130	327	*/
vladvana	0:23d1f73bf130	328
vladvana	0:23d1f73bf130	329	/** @defgroup __HAL_RCC_PLL_CONFIG PLL Config
vladvana	0:23d1f73bf130	330	* @{
vladvana	0:23d1f73bf130	331	*/
vladvana	0:23d1f73bf130	332	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
vladvana	0:23d1f73bf130	333	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
vladvana	0:23d1f73bf130	334	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
vladvana	0:23d1f73bf130	335
vladvana	0:23d1f73bf130	336	/**
vladvana	0:23d1f73bf130	337	* @}
vladvana	0:23d1f73bf130	338	*/
vladvana	0:23d1f73bf130	339
vladvana	0:23d1f73bf130	340	/** @defgroup RCC_System_Clock_Type System Clock Type
vladvana	0:23d1f73bf130	341	* @{
vladvana	0:23d1f73bf130	342	*/
vladvana	0:23d1f73bf130	343	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
vladvana	0:23d1f73bf130	344	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
vladvana	0:23d1f73bf130	345	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
vladvana	0:23d1f73bf130	346	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
vladvana	0:23d1f73bf130	347
vladvana	0:23d1f73bf130	348	/**
vladvana	0:23d1f73bf130	349	* @}
vladvana	0:23d1f73bf130	350	*/
vladvana	0:23d1f73bf130	351
vladvana	0:23d1f73bf130	352	/** @defgroup RCC_System_Clock_Source System Clock Source
vladvana	0:23d1f73bf130	353	* @{
vladvana	0:23d1f73bf130	354	*/
vladvana	0:23d1f73bf130	355	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
vladvana	0:23d1f73bf130	356	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
vladvana	0:23d1f73bf130	357	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
vladvana	0:23d1f73bf130	358
vladvana	0:23d1f73bf130	359	/**
vladvana	0:23d1f73bf130	360	* @}
vladvana	0:23d1f73bf130	361	*/
vladvana	0:23d1f73bf130	362
vladvana	0:23d1f73bf130	363	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
vladvana	0:23d1f73bf130	364	* @{
vladvana	0:23d1f73bf130	365	*/
vladvana	0:23d1f73bf130	366	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
vladvana	0:23d1f73bf130	367	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
vladvana	0:23d1f73bf130	368	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
vladvana	0:23d1f73bf130	369
vladvana	0:23d1f73bf130	370	/**
vladvana	0:23d1f73bf130	371	* @}
vladvana	0:23d1f73bf130	372	*/
vladvana	0:23d1f73bf130	373
vladvana	0:23d1f73bf130	374	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
vladvana	0:23d1f73bf130	375	* @{
vladvana	0:23d1f73bf130	376	*/
vladvana	0:23d1f73bf130	377	#define RCC_SYSCLK_DIV1 (RCC_CFGR_HPRE_DIV1) /!< SYSCLK not divided /
vladvana	0:23d1f73bf130	378	#define RCC_SYSCLK_DIV2 (RCC_CFGR_HPRE_DIV2) /!< SYSCLK divided by 2 /
vladvana	0:23d1f73bf130	379	#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_DIV4) /!< SYSCLK divided by 4 /
vladvana	0:23d1f73bf130	380	#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_DIV8) /!< SYSCLK divided by 8 /
vladvana	0:23d1f73bf130	381	#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_DIV16) /!< SYSCLK divided by 16 /
vladvana	0:23d1f73bf130	382	#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_DIV64) /!< SYSCLK divided by 64 /
vladvana	0:23d1f73bf130	383	#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_DIV128) /!< SYSCLK divided by 128 /
vladvana	0:23d1f73bf130	384	#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_DIV256) /!< SYSCLK divided by 256 /
vladvana	0:23d1f73bf130	385	#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_DIV512) /!< SYSCLK divided by 512 /
vladvana	0:23d1f73bf130	386
vladvana	0:23d1f73bf130	387	/**
vladvana	0:23d1f73bf130	388	* @}
vladvana	0:23d1f73bf130	389	*/
vladvana	0:23d1f73bf130	390
vladvana	0:23d1f73bf130	391	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
vladvana	0:23d1f73bf130	392	* @{
vladvana	0:23d1f73bf130	393	*/
vladvana	0:23d1f73bf130	394	#define RCC_HCLK_DIV1 (RCC_CFGR_PPRE1_DIV1) /!< HCLK not divided /
vladvana	0:23d1f73bf130	395	#define RCC_HCLK_DIV2 (RCC_CFGR_PPRE1_DIV2) /!< HCLK divided by 2 /
vladvana	0:23d1f73bf130	396	#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE1_DIV4) /!< HCLK divided by 4 /
vladvana	0:23d1f73bf130	397	#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE1_DIV8) /!< HCLK divided by 8 /
vladvana	0:23d1f73bf130	398	#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE1_DIV16) /!< HCLK divided by 16 /
vladvana	0:23d1f73bf130	399
vladvana	0:23d1f73bf130	400	/**
vladvana	0:23d1f73bf130	401	* @}
vladvana	0:23d1f73bf130	402	*/
vladvana	0:23d1f73bf130	403
vladvana	0:23d1f73bf130	404	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
vladvana	0:23d1f73bf130	405	* @{
vladvana	0:23d1f73bf130	406	*/
vladvana	0:23d1f73bf130	407	#define RCC_RTCCLKSOURCE_LSE (RCC_BDCR_RTCSEL_LSE) /!< LSE oscillator clock used as RTC clock /
vladvana	0:23d1f73bf130	408	#define RCC_RTCCLKSOURCE_LSI (RCC_BDCR_RTCSEL_LSI) /!< LSI oscillator clock used as RTC clock /
vladvana	0:23d1f73bf130	409	#define RCC_RTCCLKSOURCE_HSE_DIV128 (RCC_BDCR_RTCSEL_HSE) /!< HSE oscillator clock divided by 128 used as RTC clock /
vladvana	0:23d1f73bf130	410	/**
vladvana	0:23d1f73bf130	411	* @}
vladvana	0:23d1f73bf130	412	*/
vladvana	0:23d1f73bf130	413
vladvana	0:23d1f73bf130	414	/** @defgroup RCC_MCO_Index MCO Index
vladvana	0:23d1f73bf130	415	* @{
vladvana	0:23d1f73bf130	416	*/
vladvana	0:23d1f73bf130	417	#define RCC_MCO1 ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	418	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
vladvana	0:23d1f73bf130	419
vladvana	0:23d1f73bf130	420	/**
vladvana	0:23d1f73bf130	421	* @}
vladvana	0:23d1f73bf130	422	*/
vladvana	0:23d1f73bf130	423
vladvana	0:23d1f73bf130	424	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
vladvana	0:23d1f73bf130	425	* @{
vladvana	0:23d1f73bf130	426	*/
vladvana	0:23d1f73bf130	427	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
vladvana	0:23d1f73bf130	428
vladvana	0:23d1f73bf130	429	/**
vladvana	0:23d1f73bf130	430	* @}
vladvana	0:23d1f73bf130	431	*/
vladvana	0:23d1f73bf130	432
vladvana	0:23d1f73bf130	433	/** @defgroup RCC_Interrupt Interrupts
vladvana	0:23d1f73bf130	434	* @{
vladvana	0:23d1f73bf130	435	*/
vladvana	0:23d1f73bf130	436	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
vladvana	0:23d1f73bf130	437	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
vladvana	0:23d1f73bf130	438	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
vladvana	0:23d1f73bf130	439	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
vladvana	0:23d1f73bf130	440	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
vladvana	0:23d1f73bf130	441	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
vladvana	0:23d1f73bf130	442	/**
vladvana	0:23d1f73bf130	443	* @}
vladvana	0:23d1f73bf130	444	*/
vladvana	0:23d1f73bf130	445
vladvana	0:23d1f73bf130	446	/** @defgroup RCC_Flag Flags
vladvana	0:23d1f73bf130	447	* Elements values convention: 0XXYYYYYb
vladvana	0:23d1f73bf130	448	* - YYYYY : Flag position in the register
vladvana	0:23d1f73bf130	449	* - XX : Register index
vladvana	0:23d1f73bf130	450	* - 01: CR register
vladvana	0:23d1f73bf130	451	* - 10: BDCR register
vladvana	0:23d1f73bf130	452	* - 11: CSR register
vladvana	0:23d1f73bf130	453	* @{
vladvana	0:23d1f73bf130	454	*/
vladvana	0:23d1f73bf130	455	/* Flags in the CR register */
vladvana	0:23d1f73bf130	456	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< Internal High Speed clock ready flag /
vladvana	0:23d1f73bf130	457	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< External High Speed clock ready flag /
vladvana	0:23d1f73bf130	458	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL clock ready flag /
vladvana	0:23d1f73bf130	459
vladvana	0:23d1f73bf130	460	/* Flags in the BDCR register */
vladvana	0:23d1f73bf130	461	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< External Low Speed oscillator Ready /
vladvana	0:23d1f73bf130	462
vladvana	0:23d1f73bf130	463	/* Flags in the CSR register */
vladvana	0:23d1f73bf130	464	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< Internal Low Speed oscillator Ready /
vladvana	0:23d1f73bf130	465	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
vladvana	0:23d1f73bf130	466	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
vladvana	0:23d1f73bf130	467	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PORRSTF))) /!< POR/PDR reset flag /
vladvana	0:23d1f73bf130	468	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
vladvana	0:23d1f73bf130	469	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
vladvana	0:23d1f73bf130	470	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
vladvana	0:23d1f73bf130	471	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
vladvana	0:23d1f73bf130	472
vladvana	0:23d1f73bf130	473	/**
vladvana	0:23d1f73bf130	474	* @}
vladvana	0:23d1f73bf130	475	*/
vladvana	0:23d1f73bf130	476
vladvana	0:23d1f73bf130	477	/**
vladvana	0:23d1f73bf130	478	* @}
vladvana	0:23d1f73bf130	479	*/
vladvana	0:23d1f73bf130	480
vladvana	0:23d1f73bf130	481	/* Exported macro ------------------------------------------------------------*/
vladvana	0:23d1f73bf130	482
vladvana	0:23d1f73bf130	483	/** @defgroup RCC_Exported_Macros RCC Exported Macros
vladvana	0:23d1f73bf130	484	* @{
vladvana	0:23d1f73bf130	485	*/
vladvana	0:23d1f73bf130	486
vladvana	0:23d1f73bf130	487	/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
vladvana	0:23d1f73bf130	488	* @brief Enable or disable the AHB1 peripheral clock.
vladvana	0:23d1f73bf130	489	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	490	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	491	* using it.
vladvana	0:23d1f73bf130	492	* @{
vladvana	0:23d1f73bf130	493	*/
vladvana	0:23d1f73bf130	494	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	495	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	496	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
vladvana	0:23d1f73bf130	497	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	498	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
vladvana	0:23d1f73bf130	499	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	500	} while(0)
vladvana	0:23d1f73bf130	501
vladvana	0:23d1f73bf130	502	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	503	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	504	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
vladvana	0:23d1f73bf130	505	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	506	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
vladvana	0:23d1f73bf130	507	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	508	} while(0)
vladvana	0:23d1f73bf130	509
vladvana	0:23d1f73bf130	510	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	511	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	512	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
vladvana	0:23d1f73bf130	513	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	514	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
vladvana	0:23d1f73bf130	515	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	516	} while(0)
vladvana	0:23d1f73bf130	517
vladvana	0:23d1f73bf130	518	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	519	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	520	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
vladvana	0:23d1f73bf130	521	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	522	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
vladvana	0:23d1f73bf130	523	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	524	} while(0)
vladvana	0:23d1f73bf130	525
vladvana	0:23d1f73bf130	526	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
vladvana	0:23d1f73bf130	527	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
vladvana	0:23d1f73bf130	528	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
vladvana	0:23d1f73bf130	529	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
vladvana	0:23d1f73bf130	530
vladvana	0:23d1f73bf130	531	/**
vladvana	0:23d1f73bf130	532	* @}
vladvana	0:23d1f73bf130	533	*/
vladvana	0:23d1f73bf130	534
vladvana	0:23d1f73bf130	535	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
vladvana	0:23d1f73bf130	536	* @brief Get the enable or disable status of the AHB peripheral clock.
vladvana	0:23d1f73bf130	537	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	538	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	539	* using it.
vladvana	0:23d1f73bf130	540	* @{
vladvana	0:23d1f73bf130	541	*/
vladvana	0:23d1f73bf130	542
vladvana	0:23d1f73bf130	543	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
vladvana	0:23d1f73bf130	544	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
vladvana	0:23d1f73bf130	545	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
vladvana	0:23d1f73bf130	546	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
vladvana	0:23d1f73bf130	547	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
vladvana	0:23d1f73bf130	548	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
vladvana	0:23d1f73bf130	549	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
vladvana	0:23d1f73bf130	550	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
vladvana	0:23d1f73bf130	551
vladvana	0:23d1f73bf130	552	/**
vladvana	0:23d1f73bf130	553	* @}
vladvana	0:23d1f73bf130	554	*/
vladvana	0:23d1f73bf130	555
vladvana	0:23d1f73bf130	556	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
vladvana	0:23d1f73bf130	557	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
vladvana	0:23d1f73bf130	558	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	559	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	560	* using it.
vladvana	0:23d1f73bf130	561	* @{
vladvana	0:23d1f73bf130	562	*/
vladvana	0:23d1f73bf130	563	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	564	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	565	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
vladvana	0:23d1f73bf130	566	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	567	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
vladvana	0:23d1f73bf130	568	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	569	} while(0)
vladvana	0:23d1f73bf130	570
vladvana	0:23d1f73bf130	571	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	572	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	573	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
vladvana	0:23d1f73bf130	574	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	575	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
vladvana	0:23d1f73bf130	576	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	577	} while(0)
vladvana	0:23d1f73bf130	578
vladvana	0:23d1f73bf130	579	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	580	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	581	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
vladvana	0:23d1f73bf130	582	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	583	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
vladvana	0:23d1f73bf130	584	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	585	} while(0)
vladvana	0:23d1f73bf130	586
vladvana	0:23d1f73bf130	587	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	588	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	589	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
vladvana	0:23d1f73bf130	590	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	591	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
vladvana	0:23d1f73bf130	592	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	593	} while(0)
vladvana	0:23d1f73bf130	594
vladvana	0:23d1f73bf130	595	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	596	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	597	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
vladvana	0:23d1f73bf130	598	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	599	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
vladvana	0:23d1f73bf130	600	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	601	} while(0)
vladvana	0:23d1f73bf130	602
vladvana	0:23d1f73bf130	603	#define __HAL_RCC_BKP_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	604	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	605	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
vladvana	0:23d1f73bf130	606	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	607	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
vladvana	0:23d1f73bf130	608	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	609	} while(0)
vladvana	0:23d1f73bf130	610
vladvana	0:23d1f73bf130	611	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	612	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	613	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
vladvana	0:23d1f73bf130	614	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	615	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
vladvana	0:23d1f73bf130	616	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	617	} while(0)
vladvana	0:23d1f73bf130	618
vladvana	0:23d1f73bf130	619	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
vladvana	0:23d1f73bf130	620	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
vladvana	0:23d1f73bf130	621	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
vladvana	0:23d1f73bf130	622	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
vladvana	0:23d1f73bf130	623	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
vladvana	0:23d1f73bf130	624
vladvana	0:23d1f73bf130	625	#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
vladvana	0:23d1f73bf130	626	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
vladvana	0:23d1f73bf130	627
vladvana	0:23d1f73bf130	628	/**
vladvana	0:23d1f73bf130	629	* @}
vladvana	0:23d1f73bf130	630	*/
vladvana	0:23d1f73bf130	631
vladvana	0:23d1f73bf130	632	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
vladvana	0:23d1f73bf130	633	* @brief Get the enable or disable status of the APB1 peripheral clock.
vladvana	0:23d1f73bf130	634	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	635	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	636	* using it.
vladvana	0:23d1f73bf130	637	* @{
vladvana	0:23d1f73bf130	638	*/
vladvana	0:23d1f73bf130	639
vladvana	0:23d1f73bf130	640	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
vladvana	0:23d1f73bf130	641	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
vladvana	0:23d1f73bf130	642	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
vladvana	0:23d1f73bf130	643	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
vladvana	0:23d1f73bf130	644	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
vladvana	0:23d1f73bf130	645	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
vladvana	0:23d1f73bf130	646	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
vladvana	0:23d1f73bf130	647	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
vladvana	0:23d1f73bf130	648	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
vladvana	0:23d1f73bf130	649	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
vladvana	0:23d1f73bf130	650	#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
vladvana	0:23d1f73bf130	651	#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
vladvana	0:23d1f73bf130	652	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
vladvana	0:23d1f73bf130	653	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
vladvana	0:23d1f73bf130	654
vladvana	0:23d1f73bf130	655	/**
vladvana	0:23d1f73bf130	656	* @}
vladvana	0:23d1f73bf130	657	*/
vladvana	0:23d1f73bf130	658
vladvana	0:23d1f73bf130	659	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
vladvana	0:23d1f73bf130	660	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
vladvana	0:23d1f73bf130	661	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	662	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	663	* using it.
vladvana	0:23d1f73bf130	664	* @{
vladvana	0:23d1f73bf130	665	*/
vladvana	0:23d1f73bf130	666	#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	667	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	668	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
vladvana	0:23d1f73bf130	669	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	670	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
vladvana	0:23d1f73bf130	671	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	672	} while(0)
vladvana	0:23d1f73bf130	673
vladvana	0:23d1f73bf130	674	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	675	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	676	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
vladvana	0:23d1f73bf130	677	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	678	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
vladvana	0:23d1f73bf130	679	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	680	} while(0)
vladvana	0:23d1f73bf130	681
vladvana	0:23d1f73bf130	682	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	683	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	684	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
vladvana	0:23d1f73bf130	685	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	686	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
vladvana	0:23d1f73bf130	687	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	688	} while(0)
vladvana	0:23d1f73bf130	689
vladvana	0:23d1f73bf130	690	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	691	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	692	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
vladvana	0:23d1f73bf130	693	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	694	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
vladvana	0:23d1f73bf130	695	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	696	} while(0)
vladvana	0:23d1f73bf130	697
vladvana	0:23d1f73bf130	698	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	699	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	700	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
vladvana	0:23d1f73bf130	701	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	702	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
vladvana	0:23d1f73bf130	703	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	704	} while(0)
vladvana	0:23d1f73bf130	705
vladvana	0:23d1f73bf130	706	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	707	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	708	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
vladvana	0:23d1f73bf130	709	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	710	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
vladvana	0:23d1f73bf130	711	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	712	} while(0)
vladvana	0:23d1f73bf130	713
vladvana	0:23d1f73bf130	714	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	715	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	716	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
vladvana	0:23d1f73bf130	717	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	718	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
vladvana	0:23d1f73bf130	719	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	720	} while(0)
vladvana	0:23d1f73bf130	721
vladvana	0:23d1f73bf130	722	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	723	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	724	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
vladvana	0:23d1f73bf130	725	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	726	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
vladvana	0:23d1f73bf130	727	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	728	} while(0)
vladvana	0:23d1f73bf130	729
vladvana	0:23d1f73bf130	730	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
vladvana	0:23d1f73bf130	731	__IO uint32_t tmpreg; \
vladvana	0:23d1f73bf130	732	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
vladvana	0:23d1f73bf130	733	/* Delay after an RCC peripheral clock enabling */ \
vladvana	0:23d1f73bf130	734	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
vladvana	0:23d1f73bf130	735	UNUSED(tmpreg); \
vladvana	0:23d1f73bf130	736	} while(0)
vladvana	0:23d1f73bf130	737
vladvana	0:23d1f73bf130	738	#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
vladvana	0:23d1f73bf130	739	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
vladvana	0:23d1f73bf130	740	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
vladvana	0:23d1f73bf130	741	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
vladvana	0:23d1f73bf130	742	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
vladvana	0:23d1f73bf130	743	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
vladvana	0:23d1f73bf130	744
vladvana	0:23d1f73bf130	745	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
vladvana	0:23d1f73bf130	746	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
vladvana	0:23d1f73bf130	747	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
vladvana	0:23d1f73bf130	748
vladvana	0:23d1f73bf130	749	/**
vladvana	0:23d1f73bf130	750	* @}
vladvana	0:23d1f73bf130	751	*/
vladvana	0:23d1f73bf130	752
vladvana	0:23d1f73bf130	753	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
vladvana	0:23d1f73bf130	754	* @brief Get the enable or disable status of the APB2 peripheral clock.
vladvana	0:23d1f73bf130	755	* @note After reset, the peripheral clock (used for registers read/write access)
vladvana	0:23d1f73bf130	756	* is disabled and the application software has to enable this clock before
vladvana	0:23d1f73bf130	757	* using it.
vladvana	0:23d1f73bf130	758	* @{
vladvana	0:23d1f73bf130	759	*/
vladvana	0:23d1f73bf130	760
vladvana	0:23d1f73bf130	761	#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
vladvana	0:23d1f73bf130	762	#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
vladvana	0:23d1f73bf130	763	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
vladvana	0:23d1f73bf130	764	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
vladvana	0:23d1f73bf130	765	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
vladvana	0:23d1f73bf130	766	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
vladvana	0:23d1f73bf130	767	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
vladvana	0:23d1f73bf130	768	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
vladvana	0:23d1f73bf130	769	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
vladvana	0:23d1f73bf130	770	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
vladvana	0:23d1f73bf130	771	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
vladvana	0:23d1f73bf130	772	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
vladvana	0:23d1f73bf130	773	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
vladvana	0:23d1f73bf130	774	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
vladvana	0:23d1f73bf130	775	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
vladvana	0:23d1f73bf130	776	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
vladvana	0:23d1f73bf130	777	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
vladvana	0:23d1f73bf130	778	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
vladvana	0:23d1f73bf130	779
vladvana	0:23d1f73bf130	780	/**
vladvana	0:23d1f73bf130	781	* @}
vladvana	0:23d1f73bf130	782	*/
vladvana	0:23d1f73bf130	783
vladvana	0:23d1f73bf130	784	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
vladvana	0:23d1f73bf130	785	* @brief Force or release APB1 peripheral reset.
vladvana	0:23d1f73bf130	786	* @{
vladvana	0:23d1f73bf130	787	*/
vladvana	0:23d1f73bf130	788	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
vladvana	0:23d1f73bf130	789	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
vladvana	0:23d1f73bf130	790	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
vladvana	0:23d1f73bf130	791	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
vladvana	0:23d1f73bf130	792	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
vladvana	0:23d1f73bf130	793	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
vladvana	0:23d1f73bf130	794
vladvana	0:23d1f73bf130	795	#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_BKPRST))
vladvana	0:23d1f73bf130	796	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
vladvana	0:23d1f73bf130	797
vladvana	0:23d1f73bf130	798	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
vladvana	0:23d1f73bf130	799	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
vladvana	0:23d1f73bf130	800	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
vladvana	0:23d1f73bf130	801	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
vladvana	0:23d1f73bf130	802	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
vladvana	0:23d1f73bf130	803	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
vladvana	0:23d1f73bf130	804
vladvana	0:23d1f73bf130	805	#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
vladvana	0:23d1f73bf130	806	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
vladvana	0:23d1f73bf130	807
vladvana	0:23d1f73bf130	808	/**
vladvana	0:23d1f73bf130	809	* @}
vladvana	0:23d1f73bf130	810	*/
vladvana	0:23d1f73bf130	811
vladvana	0:23d1f73bf130	812	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
vladvana	0:23d1f73bf130	813	* @brief Force or release APB2 peripheral reset.
vladvana	0:23d1f73bf130	814	* @{
vladvana	0:23d1f73bf130	815	*/
vladvana	0:23d1f73bf130	816	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
vladvana	0:23d1f73bf130	817	#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_AFIORST))
vladvana	0:23d1f73bf130	818	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPARST))
vladvana	0:23d1f73bf130	819	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPBRST))
vladvana	0:23d1f73bf130	820	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPCRST))
vladvana	0:23d1f73bf130	821	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPDRST))
vladvana	0:23d1f73bf130	822	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
vladvana	0:23d1f73bf130	823
vladvana	0:23d1f73bf130	824	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
vladvana	0:23d1f73bf130	825	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
vladvana	0:23d1f73bf130	826	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
vladvana	0:23d1f73bf130	827
vladvana	0:23d1f73bf130	828	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
vladvana	0:23d1f73bf130	829	#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
vladvana	0:23d1f73bf130	830	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
vladvana	0:23d1f73bf130	831	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
vladvana	0:23d1f73bf130	832	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
vladvana	0:23d1f73bf130	833	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
vladvana	0:23d1f73bf130	834	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
vladvana	0:23d1f73bf130	835
vladvana	0:23d1f73bf130	836	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
vladvana	0:23d1f73bf130	837	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
vladvana	0:23d1f73bf130	838	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
vladvana	0:23d1f73bf130	839
vladvana	0:23d1f73bf130	840	/**
vladvana	0:23d1f73bf130	841	* @}
vladvana	0:23d1f73bf130	842	*/
vladvana	0:23d1f73bf130	843
vladvana	0:23d1f73bf130	844	/** @defgroup RCC_HSI_Configuration HSI Configuration
vladvana	0:23d1f73bf130	845	* @{
vladvana	0:23d1f73bf130	846	*/
vladvana	0:23d1f73bf130	847
vladvana	0:23d1f73bf130	848	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
vladvana	0:23d1f73bf130	849	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
vladvana	0:23d1f73bf130	850	* @note HSI can not be stopped if it is used as system clock source. In this case,
vladvana	0:23d1f73bf130	851	* you have to select another source of the system clock then stop the HSI.
vladvana	0:23d1f73bf130	852	* @note After enabling the HSI, the application software should wait on HSIRDY
vladvana	0:23d1f73bf130	853	* flag to be set indicating that HSI clock is stable and can be used as
vladvana	0:23d1f73bf130	854	* system clock source.
vladvana	0:23d1f73bf130	855	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
vladvana	0:23d1f73bf130	856	* clock cycles.
vladvana	0:23d1f73bf130	857	*/
vladvana	0:23d1f73bf130	858	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
vladvana	0:23d1f73bf130	859	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
vladvana	0:23d1f73bf130	860
vladvana	0:23d1f73bf130	861	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
vladvana	0:23d1f73bf130	862	* @note The calibration is used to compensate for the variations in voltage
vladvana	0:23d1f73bf130	863	* and temperature that influence the frequency of the internal HSI RC.
vladvana	0:23d1f73bf130	864	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
vladvana	0:23d1f73bf130	865	* (default is RCC_HSICALIBRATION_DEFAULT).
vladvana	0:23d1f73bf130	866	* This parameter must be a number between 0 and 0x1F.
vladvana	0:23d1f73bf130	867	*/
vladvana	0:23d1f73bf130	868	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
vladvana	0:23d1f73bf130	869	(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
vladvana	0:23d1f73bf130	870
vladvana	0:23d1f73bf130	871	/**
vladvana	0:23d1f73bf130	872	* @}
vladvana	0:23d1f73bf130	873	*/
vladvana	0:23d1f73bf130	874
vladvana	0:23d1f73bf130	875	/** @defgroup RCC_LSI_Configuration LSI Configuration
vladvana	0:23d1f73bf130	876	* @{
vladvana	0:23d1f73bf130	877	*/
vladvana	0:23d1f73bf130	878
vladvana	0:23d1f73bf130	879	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
vladvana	0:23d1f73bf130	880	* @note After enabling the LSI, the application software should wait on
vladvana	0:23d1f73bf130	881	* LSIRDY flag to be set indicating that LSI clock is stable and can
vladvana	0:23d1f73bf130	882	* be used to clock the IWDG and/or the RTC.
vladvana	0:23d1f73bf130	883	* @note LSI can not be disabled if the IWDG is running.
vladvana	0:23d1f73bf130	884	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
vladvana	0:23d1f73bf130	885	* clock cycles.
vladvana	0:23d1f73bf130	886	*/
vladvana	0:23d1f73bf130	887	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
vladvana	0:23d1f73bf130	888	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
vladvana	0:23d1f73bf130	889
vladvana	0:23d1f73bf130	890	/**
vladvana	0:23d1f73bf130	891	* @}
vladvana	0:23d1f73bf130	892	*/
vladvana	0:23d1f73bf130	893
vladvana	0:23d1f73bf130	894	/** @defgroup RCC_HSE_Configuration HSE Configuration
vladvana	0:23d1f73bf130	895	* @{
vladvana	0:23d1f73bf130	896	*/
vladvana	0:23d1f73bf130	897
vladvana	0:23d1f73bf130	898	/**
vladvana	0:23d1f73bf130	899	* @brief Macro to configure the External High Speed oscillator (HSE).
vladvana	0:23d1f73bf130	900	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
vladvana	0:23d1f73bf130	901	* software should wait on HSERDY flag to be set indicating that HSE clock
vladvana	0:23d1f73bf130	902	* is stable and can be used to clock the PLL and/or system clock.
vladvana	0:23d1f73bf130	903	* @note HSE state can not be changed if it is used directly or through the
vladvana	0:23d1f73bf130	904	* PLL as system clock. In this case, you have to select another source
vladvana	0:23d1f73bf130	905	* of the system clock then change the HSE state (ex. disable it).
vladvana	0:23d1f73bf130	906	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
vladvana	0:23d1f73bf130	907	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
vladvana	0:23d1f73bf130	908	* was previously enabled you have to enable it again after calling this
vladvana	0:23d1f73bf130	909	* function.
vladvana	0:23d1f73bf130	910	* @param __STATE__: specifies the new state of the HSE.
vladvana	0:23d1f73bf130	911	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	912	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
vladvana	0:23d1f73bf130	913	* 6 HSE oscillator clock cycles.
vladvana	0:23d1f73bf130	914	* @arg RCC_HSE_ON: turn ON the HSE oscillator
vladvana	0:23d1f73bf130	915	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
vladvana	0:23d1f73bf130	916	*/
vladvana	0:23d1f73bf130	917	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
vladvana	0:23d1f73bf130	918	do { \
vladvana	0:23d1f73bf130	919	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
vladvana	0:23d1f73bf130	920	if((__STATE__) == RCC_HSE_ON) \
vladvana	0:23d1f73bf130	921	{ \
vladvana	0:23d1f73bf130	922	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
vladvana	0:23d1f73bf130	923	SET_BIT(RCC->CR, RCC_CR_HSEON); \
vladvana	0:23d1f73bf130	924	} \
vladvana	0:23d1f73bf130	925	else if((__STATE__) == RCC_HSE_BYPASS) \
vladvana	0:23d1f73bf130	926	{ \
vladvana	0:23d1f73bf130	927	((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__)); \
vladvana	0:23d1f73bf130	928	} \
vladvana	0:23d1f73bf130	929	else \
vladvana	0:23d1f73bf130	930	{ \
vladvana	0:23d1f73bf130	931	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
vladvana	0:23d1f73bf130	932	} \
vladvana	0:23d1f73bf130	933	} while(0)
vladvana	0:23d1f73bf130	934
vladvana	0:23d1f73bf130	935	/**
vladvana	0:23d1f73bf130	936	* @}
vladvana	0:23d1f73bf130	937	*/
vladvana	0:23d1f73bf130	938
vladvana	0:23d1f73bf130	939	/** @defgroup RCC_LSE_Configuration LSE Configuration
vladvana	0:23d1f73bf130	940	* @{
vladvana	0:23d1f73bf130	941	*/
vladvana	0:23d1f73bf130	942
vladvana	0:23d1f73bf130	943	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
vladvana	0:23d1f73bf130	944	*/
vladvana	0:23d1f73bf130	945	#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
vladvana	0:23d1f73bf130	946	do{ \
vladvana	0:23d1f73bf130	947	if ((__LSE_STATE__) == RCC_LSE_OFF) \
vladvana	0:23d1f73bf130	948	{ \
vladvana	0:23d1f73bf130	949	(__IO uint32_t ) BDCR_LSEON_BB = DISABLE; \
vladvana	0:23d1f73bf130	950	(__IO uint32_t ) BDCR_LSEBYP_BB = DISABLE; \
vladvana	0:23d1f73bf130	951	} \
vladvana	0:23d1f73bf130	952	else if ((__LSE_STATE__) == RCC_LSE_ON) \
vladvana	0:23d1f73bf130	953	{ \
vladvana	0:23d1f73bf130	954	(__IO uint32_t ) BDCR_LSEBYP_BB = DISABLE; \
vladvana	0:23d1f73bf130	955	(__IO uint32_t ) BDCR_LSEON_BB = ENABLE; \
vladvana	0:23d1f73bf130	956	} \
vladvana	0:23d1f73bf130	957	else \
vladvana	0:23d1f73bf130	958	{ \
vladvana	0:23d1f73bf130	959	(__IO uint32_t ) BDCR_LSEON_BB = DISABLE; \
vladvana	0:23d1f73bf130	960	(__IO uint32_t ) BDCR_LSEBYP_BB = ENABLE; \
vladvana	0:23d1f73bf130	961	} \
vladvana	0:23d1f73bf130	962	}while(0)
vladvana	0:23d1f73bf130	963
vladvana	0:23d1f73bf130	964
vladvana	0:23d1f73bf130	965	/**
vladvana	0:23d1f73bf130	966	* @}
vladvana	0:23d1f73bf130	967	*/
vladvana	0:23d1f73bf130	968
vladvana	0:23d1f73bf130	969	/** @defgroup RCC_PLL_Configuration PLL Configuration
vladvana	0:23d1f73bf130	970	* @{
vladvana	0:23d1f73bf130	971	*/
vladvana	0:23d1f73bf130	972
vladvana	0:23d1f73bf130	973	/** @brief Macros to enable the main PLL.
vladvana	0:23d1f73bf130	974	* @note After enabling the main PLL, the application software should wait on
vladvana	0:23d1f73bf130	975	* PLLRDY flag to be set indicating that PLL clock is stable and can
vladvana	0:23d1f73bf130	976	* be used as system clock source.
vladvana	0:23d1f73bf130	977	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
vladvana	0:23d1f73bf130	978	*/
vladvana	0:23d1f73bf130	979	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
vladvana	0:23d1f73bf130	980
vladvana	0:23d1f73bf130	981	/** @brief Macros to disable the main PLL.
vladvana	0:23d1f73bf130	982	* @note The main PLL can not be disabled if it is used as system clock source
vladvana	0:23d1f73bf130	983	*/
vladvana	0:23d1f73bf130	984	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
vladvana	0:23d1f73bf130	985
vladvana	0:23d1f73bf130	986	/** @brief macros to configure the main PLL clock source and multiplication factors.
vladvana	0:23d1f73bf130	987	* @note This function must be used only when the main PLL is disabled.
vladvana	0:23d1f73bf130	988	*
vladvana	0:23d1f73bf130	989	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
vladvana	0:23d1f73bf130	990	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	991	* @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL clock entry
vladvana	0:23d1f73bf130	992	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
vladvana	0:23d1f73bf130	993	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
vladvana	0:23d1f73bf130	994	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	995	* @arg RCC_PLL_MUL2: PLLVCO = PLL clock entry x 2 (*)
vladvana	0:23d1f73bf130	996	* @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 (*)
vladvana	0:23d1f73bf130	997	* @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
vladvana	0:23d1f73bf130	998	* @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
vladvana	0:23d1f73bf130	999	* @arg RCC_PLL_MUL6_5: PLLVCO = PLL clock entry x 6.5 (**)
vladvana	0:23d1f73bf130	1000	* @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
vladvana	0:23d1f73bf130	1001	* @arg RCC_PLL_MUL9: PLLVCO = PLL clock entry x 9
vladvana	0:23d1f73bf130	1002	* @arg RCC_PLL_MUL10: PLLVCO = PLL clock entry x 10 (*)
vladvana	0:23d1f73bf130	1003	* @arg RCC_PLL_MUL11: PLLVCO = PLL clock entry x 11 (*)
vladvana	0:23d1f73bf130	1004	* @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 (*)
vladvana	0:23d1f73bf130	1005	* @arg RCC_PLL_MUL13: PLLVCO = PLL clock entry x 13 (*)
vladvana	0:23d1f73bf130	1006	* @arg RCC_PLL_MUL14: PLLVCO = PLL clock entry x 14 (*)
vladvana	0:23d1f73bf130	1007	* @arg RCC_PLL_MUL15: PLLVCO = PLL clock entry x 15 (*)
vladvana	0:23d1f73bf130	1008	* @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 (*)
vladvana	0:23d1f73bf130	1009	* @note (*) These values are not available in STM32F105xx & STM32F107xx devices.
vladvana	0:23d1f73bf130	1010	* @note (**) This value is available in STM32F105xx & STM32F107xx devices only.
vladvana	0:23d1f73bf130	1011	*
vladvana	0:23d1f73bf130	1012	*/
vladvana	0:23d1f73bf130	1013	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
vladvana	0:23d1f73bf130	1014	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) \| (__PLLMUL__) ))
vladvana	0:23d1f73bf130	1015	/**
vladvana	0:23d1f73bf130	1016	* @}
vladvana	0:23d1f73bf130	1017	*/
vladvana	0:23d1f73bf130	1018
vladvana	0:23d1f73bf130	1019	/** @defgroup RCC_Get_Clock_source Get Clock source
vladvana	0:23d1f73bf130	1020	* @{
vladvana	0:23d1f73bf130	1021	*/
vladvana	0:23d1f73bf130	1022
vladvana	0:23d1f73bf130	1023	/** @brief Macro to get the clock source used as system clock.
vladvana	0:23d1f73bf130	1024	* @retval The clock source used as system clock. The returned value can be one
vladvana	0:23d1f73bf130	1025	* of the following:
vladvana	0:23d1f73bf130	1026	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
vladvana	0:23d1f73bf130	1027	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
vladvana	0:23d1f73bf130	1028	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
vladvana	0:23d1f73bf130	1029	*/
vladvana	0:23d1f73bf130	1030	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
vladvana	0:23d1f73bf130	1031
vladvana	0:23d1f73bf130	1032	/** @brief Get oscillator clock selected as PLL input clock
vladvana	0:23d1f73bf130	1033	* @retval The clock source used for PLL entry. The returned value can be one
vladvana	0:23d1f73bf130	1034	* of the following:
vladvana	0:23d1f73bf130	1035	* @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL input clock
vladvana	0:23d1f73bf130	1036	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
vladvana	0:23d1f73bf130	1037	*/
vladvana	0:23d1f73bf130	1038	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
vladvana	0:23d1f73bf130	1039
vladvana	0:23d1f73bf130	1040	/**
vladvana	0:23d1f73bf130	1041	* @}
vladvana	0:23d1f73bf130	1042	*/
vladvana	0:23d1f73bf130	1043	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
vladvana	0:23d1f73bf130	1044	* @{
vladvana	0:23d1f73bf130	1045	*/
vladvana	0:23d1f73bf130	1046
vladvana	0:23d1f73bf130	1047	/** @brief Macro to configures the RTC clock (RTCCLK).
vladvana	0:23d1f73bf130	1048	* @note As the RTC clock configuration bits are in the Backup domain and write
vladvana	0:23d1f73bf130	1049	* access is denied to this domain after reset, you have to enable write
vladvana	0:23d1f73bf130	1050	* access using the Power Backup Access macro before to configure
vladvana	0:23d1f73bf130	1051	* the RTC clock source (to be done once after reset).
vladvana	0:23d1f73bf130	1052	* @note Once the RTC clock is configured it can't be changed unless the
vladvana	0:23d1f73bf130	1053	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
vladvana	0:23d1f73bf130	1054	* a Power On Reset (POR).
vladvana	0:23d1f73bf130	1055	*
vladvana	0:23d1f73bf130	1056	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
vladvana	0:23d1f73bf130	1057	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1058	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
vladvana	0:23d1f73bf130	1059	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
vladvana	0:23d1f73bf130	1060	* @arg RCC_RTCCLKSOURCE_HSE_DIV128: HSE divided by 128 selected as RTC clock
vladvana	0:23d1f73bf130	1061	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
vladvana	0:23d1f73bf130	1062	* work in STOP and STANDBY modes, and can be used as wakeup source.
vladvana	0:23d1f73bf130	1063	* However, when the HSE clock is used as RTC clock source, the RTC
vladvana	0:23d1f73bf130	1064	* cannot be used in STOP and STANDBY modes.
vladvana	0:23d1f73bf130	1065	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
vladvana	0:23d1f73bf130	1066	* RTC clock source).
vladvana	0:23d1f73bf130	1067	*/
vladvana	0:23d1f73bf130	1068	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
vladvana	0:23d1f73bf130	1069
vladvana	0:23d1f73bf130	1070
vladvana	0:23d1f73bf130	1071	/** @brief macros to get the RTC clock source.
vladvana	0:23d1f73bf130	1072	*/
vladvana	0:23d1f73bf130	1073	#define __HAL_RCC_GET_RTC_SOURCE() READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)
vladvana	0:23d1f73bf130	1074
vladvana	0:23d1f73bf130	1075	/** @brief Macros to enable the the RTC clock.
vladvana	0:23d1f73bf130	1076	* @note These macros must be used only after the RTC clock source was selected.
vladvana	0:23d1f73bf130	1077	*/
vladvana	0:23d1f73bf130	1078	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
vladvana	0:23d1f73bf130	1079
vladvana	0:23d1f73bf130	1080	/** @brief Macros to disable the the RTC clock.
vladvana	0:23d1f73bf130	1081	* @note These macros must be used only after the RTC clock source was selected.
vladvana	0:23d1f73bf130	1082	*/
vladvana	0:23d1f73bf130	1083	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
vladvana	0:23d1f73bf130	1084
vladvana	0:23d1f73bf130	1085	/** @brief Macros to force the Backup domain reset.
vladvana	0:23d1f73bf130	1086	* @note This function resets the entire Backup domain.
vladvana	0:23d1f73bf130	1087	*/
vladvana	0:23d1f73bf130	1088	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
vladvana	0:23d1f73bf130	1089
vladvana	0:23d1f73bf130	1090	/** @brief Macros to release the Backup domain reset.
vladvana	0:23d1f73bf130	1091	*/
vladvana	0:23d1f73bf130	1092	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
vladvana	0:23d1f73bf130	1093
vladvana	0:23d1f73bf130	1094
vladvana	0:23d1f73bf130	1095	/**
vladvana	0:23d1f73bf130	1096	* @}
vladvana	0:23d1f73bf130	1097	*/
vladvana	0:23d1f73bf130	1098
vladvana	0:23d1f73bf130	1099	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
vladvana	0:23d1f73bf130	1100	* @brief macros to manage the specified RCC Flags and interrupts.
vladvana	0:23d1f73bf130	1101	* @{
vladvana	0:23d1f73bf130	1102	*/
vladvana	0:23d1f73bf130	1103
vladvana	0:23d1f73bf130	1104	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
vladvana	0:23d1f73bf130	1105	* the selected interrupts.).
vladvana	0:23d1f73bf130	1106	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
vladvana	0:23d1f73bf130	1107	* This parameter can be any combination of the following values:
vladvana	0:23d1f73bf130	1108	* @arg RCC_IT_LSIRDY: LSI ready interrupt
vladvana	0:23d1f73bf130	1109	* @arg RCC_IT_LSERDY: LSE ready interrupt
vladvana	0:23d1f73bf130	1110	* @arg RCC_IT_HSIRDY: HSI ready interrupt
vladvana	0:23d1f73bf130	1111	* @arg RCC_IT_HSERDY: HSE ready interrupt
vladvana	0:23d1f73bf130	1112	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
vladvana	0:23d1f73bf130	1113	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
vladvana	0:23d1f73bf130	1114	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
vladvana	0:23d1f73bf130	1115	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
vladvana	0:23d1f73bf130	1116	*/
vladvana	0:23d1f73bf130	1117	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
vladvana	0:23d1f73bf130	1118
vladvana	0:23d1f73bf130	1119	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
vladvana	0:23d1f73bf130	1120	* the selected interrupts).
vladvana	0:23d1f73bf130	1121	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
vladvana	0:23d1f73bf130	1122	* This parameter can be any combination of the following values:
vladvana	0:23d1f73bf130	1123	* @arg RCC_IT_LSIRDY: LSI ready interrupt
vladvana	0:23d1f73bf130	1124	* @arg RCC_IT_LSERDY: LSE ready interrupt
vladvana	0:23d1f73bf130	1125	* @arg RCC_IT_HSIRDY: HSI ready interrupt
vladvana	0:23d1f73bf130	1126	* @arg RCC_IT_HSERDY: HSE ready interrupt
vladvana	0:23d1f73bf130	1127	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
vladvana	0:23d1f73bf130	1128	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
vladvana	0:23d1f73bf130	1129	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
vladvana	0:23d1f73bf130	1130	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
vladvana	0:23d1f73bf130	1131	*/
vladvana	0:23d1f73bf130	1132	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
vladvana	0:23d1f73bf130	1133
vladvana	0:23d1f73bf130	1134	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
vladvana	0:23d1f73bf130	1135	* bits to clear the selected interrupt pending bits.
vladvana	0:23d1f73bf130	1136	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
vladvana	0:23d1f73bf130	1137	* This parameter can be any combination of the following values:
vladvana	0:23d1f73bf130	1138	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
vladvana	0:23d1f73bf130	1139	* @arg RCC_IT_LSERDY: LSE ready interrupt.
vladvana	0:23d1f73bf130	1140	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
vladvana	0:23d1f73bf130	1141	* @arg RCC_IT_HSERDY: HSE ready interrupt.
vladvana	0:23d1f73bf130	1142	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
vladvana	0:23d1f73bf130	1143	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
vladvana	0:23d1f73bf130	1144	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
vladvana	0:23d1f73bf130	1145	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
vladvana	0:23d1f73bf130	1146	* @arg RCC_IT_CSS: Clock Security System interrupt
vladvana	0:23d1f73bf130	1147	*/
vladvana	0:23d1f73bf130	1148	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
vladvana	0:23d1f73bf130	1149
vladvana	0:23d1f73bf130	1150	/** @brief Check the RCC's interrupt has occurred or not.
vladvana	0:23d1f73bf130	1151	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
vladvana	0:23d1f73bf130	1152	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1153	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
vladvana	0:23d1f73bf130	1154	* @arg RCC_IT_LSERDY: LSE ready interrupt.
vladvana	0:23d1f73bf130	1155	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
vladvana	0:23d1f73bf130	1156	* @arg RCC_IT_HSERDY: HSE ready interrupt.
vladvana	0:23d1f73bf130	1157	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
vladvana	0:23d1f73bf130	1158	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
vladvana	0:23d1f73bf130	1159	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
vladvana	0:23d1f73bf130	1160	* @arg RCC_IT_CSS: Clock Security System interrupt
vladvana	0:23d1f73bf130	1161	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
vladvana	0:23d1f73bf130	1162	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
vladvana	0:23d1f73bf130	1163	*/
vladvana	0:23d1f73bf130	1164	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
vladvana	0:23d1f73bf130	1165
vladvana	0:23d1f73bf130	1166	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
vladvana	0:23d1f73bf130	1167	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
vladvana	0:23d1f73bf130	1168	*/
vladvana	0:23d1f73bf130	1169	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
vladvana	0:23d1f73bf130	1170
vladvana	0:23d1f73bf130	1171	/** @brief Check RCC flag is set or not.
vladvana	0:23d1f73bf130	1172	* @param __FLAG__: specifies the flag to check.
vladvana	0:23d1f73bf130	1173	* This parameter can be one of the following values:
vladvana	0:23d1f73bf130	1174	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
vladvana	0:23d1f73bf130	1175	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
vladvana	0:23d1f73bf130	1176	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
vladvana	0:23d1f73bf130	1177	* @arg RCC_FLAG_PLL2RDY: Main PLL2 clock ready.(*)
vladvana	0:23d1f73bf130	1178	* @arg RCC_FLAG_PLLI2SRDY: Main PLLI2S clock ready.(*)
vladvana	0:23d1f73bf130	1179	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
vladvana	0:23d1f73bf130	1180	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
vladvana	0:23d1f73bf130	1181	* @arg RCC_FLAG_PINRST: Pin reset.
vladvana	0:23d1f73bf130	1182	* @arg RCC_FLAG_PORRST: POR/PDR reset.
vladvana	0:23d1f73bf130	1183	* @arg RCC_FLAG_SFTRST: Software reset.
vladvana	0:23d1f73bf130	1184	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
vladvana	0:23d1f73bf130	1185	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
vladvana	0:23d1f73bf130	1186	* @arg RCC_FLAG_LPWRRST: Low Power reset.
vladvana	0:23d1f73bf130	1187	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
vladvana	0:23d1f73bf130	1188	* @retval The new state of __FLAG__ (TRUE or FALSE).
vladvana	0:23d1f73bf130	1189	*/
vladvana	0:23d1f73bf130	1190	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
vladvana	0:23d1f73bf130	1191	/**
vladvana	0:23d1f73bf130	1192	* @}
vladvana	0:23d1f73bf130	1193	*/
vladvana	0:23d1f73bf130	1194
vladvana	0:23d1f73bf130	1195	/**
vladvana	0:23d1f73bf130	1196	* @}
vladvana	0:23d1f73bf130	1197	*/
vladvana	0:23d1f73bf130	1198
vladvana	0:23d1f73bf130	1199	/* Include RCC HAL Extension module */
vladvana	0:23d1f73bf130	1200	#include "stm32f1xx_hal_rcc_ex.h"
vladvana	0:23d1f73bf130	1201
vladvana	0:23d1f73bf130	1202	/* Exported functions --------------------------------------------------------*/
vladvana	0:23d1f73bf130	1203	/** @addtogroup RCC_Exported_Functions
vladvana	0:23d1f73bf130	1204	* @{
vladvana	0:23d1f73bf130	1205	*/
vladvana	0:23d1f73bf130	1206
vladvana	0:23d1f73bf130	1207	/** @addtogroup RCC_Exported_Functions_Group1
vladvana	0:23d1f73bf130	1208	* @{
vladvana	0:23d1f73bf130	1209	*/
vladvana	0:23d1f73bf130	1210
vladvana	0:23d1f73bf130	1211	/* Initialization and de-initialization functions ******************************/
vladvana	0:23d1f73bf130	1212	void HAL_RCC_DeInit(void);
vladvana	0:23d1f73bf130	1213	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
vladvana	0:23d1f73bf130	1214	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
vladvana	0:23d1f73bf130	1215
vladvana	0:23d1f73bf130	1216	/**
vladvana	0:23d1f73bf130	1217	* @}
vladvana	0:23d1f73bf130	1218	*/
vladvana	0:23d1f73bf130	1219
vladvana	0:23d1f73bf130	1220	/** @addtogroup RCC_Exported_Functions_Group2
vladvana	0:23d1f73bf130	1221	* @{
vladvana	0:23d1f73bf130	1222	*/
vladvana	0:23d1f73bf130	1223
vladvana	0:23d1f73bf130	1224	/* Peripheral Control functions ************************************************/
vladvana	0:23d1f73bf130	1225	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
vladvana	0:23d1f73bf130	1226	void HAL_RCC_EnableCSS(void);
vladvana	0:23d1f73bf130	1227	void HAL_RCC_DisableCSS(void);
vladvana	0:23d1f73bf130	1228	uint32_t HAL_RCC_GetSysClockFreq(void);
vladvana	0:23d1f73bf130	1229	uint32_t HAL_RCC_GetHCLKFreq(void);
vladvana	0:23d1f73bf130	1230	uint32_t HAL_RCC_GetPCLK1Freq(void);
vladvana	0:23d1f73bf130	1231	uint32_t HAL_RCC_GetPCLK2Freq(void);
vladvana	0:23d1f73bf130	1232	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
vladvana	0:23d1f73bf130	1233	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
vladvana	0:23d1f73bf130	1234
vladvana	0:23d1f73bf130	1235	/* CSS NMI IRQ handler */
vladvana	0:23d1f73bf130	1236	void HAL_RCC_NMI_IRQHandler(void);
vladvana	0:23d1f73bf130	1237
vladvana	0:23d1f73bf130	1238	/* User Callbacks in non blocking mode (IT mode) */
vladvana	0:23d1f73bf130	1239	void HAL_RCC_CSSCallback(void);
vladvana	0:23d1f73bf130	1240
vladvana	0:23d1f73bf130	1241	/**
vladvana	0:23d1f73bf130	1242	* @}
vladvana	0:23d1f73bf130	1243	*/
vladvana	0:23d1f73bf130	1244
vladvana	0:23d1f73bf130	1245	/**
vladvana	0:23d1f73bf130	1246	* @}
vladvana	0:23d1f73bf130	1247	*/
vladvana	0:23d1f73bf130	1248
vladvana	0:23d1f73bf130	1249	/**
vladvana	0:23d1f73bf130	1250	* @}
vladvana	0:23d1f73bf130	1251	*/
vladvana	0:23d1f73bf130	1252
vladvana	0:23d1f73bf130	1253	/**
vladvana	0:23d1f73bf130	1254	* @}
vladvana	0:23d1f73bf130	1255	*/
vladvana	0:23d1f73bf130	1256
vladvana	0:23d1f73bf130	1257	#ifdef __cplusplus
vladvana	0:23d1f73bf130	1258	}
vladvana	0:23d1f73bf130	1259	#endif
vladvana	0:23d1f73bf130	1260
vladvana	0:23d1f73bf130	1261	#endif /* __STM32F1xx_HAL_RCC_H */
vladvana	0:23d1f73bf130	1262
vladvana	0:23d1f73bf130	1263	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	24 Sep 2017
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc.h@0:23d1f73bf130, 2017-09-24 (annotated)

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