Vladimir Vana / mbed

pro vyuku PSS v Jecne

TARGET_NUCLEO_F103RB/stm32f1xx_hal_dma.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:
vladvana
Date:
Sun Sep 24 12:31:52 2017 +0000
Revision:
0:23d1f73bf130
podklady pro cviceni z PSS

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vladvana 0:23d1f73bf130 1 /**
vladvana 0:23d1f73bf130 2 ******************************************************************************
vladvana 0:23d1f73bf130 3 * @file stm32f1xx_hal_dma.h
vladvana 0:23d1f73bf130 4 * @author MCD Application Team
vladvana 0:23d1f73bf130 5 * @version V1.0.0
vladvana 0:23d1f73bf130 6 * @date 15-December-2014
vladvana 0:23d1f73bf130 7 * @brief Header file of DMA HAL module.
vladvana 0:23d1f73bf130 8 ******************************************************************************
vladvana 0:23d1f73bf130 9 * @attention
vladvana 0:23d1f73bf130 10 *
vladvana 0:23d1f73bf130 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana 0:23d1f73bf130 12 *
vladvana 0:23d1f73bf130 13 * Redistribution and use in source and binary forms, with or without modification,
vladvana 0:23d1f73bf130 14 * are permitted provided that the following conditions are met:
vladvana 0:23d1f73bf130 15 * 1. Redistributions of source code must retain the above copyright notice,
vladvana 0:23d1f73bf130 16 * this list of conditions and the following disclaimer.
vladvana 0:23d1f73bf130 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana 0:23d1f73bf130 18 * this list of conditions and the following disclaimer in the documentation
vladvana 0:23d1f73bf130 19 * and/or other materials provided with the distribution.
vladvana 0:23d1f73bf130 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana 0:23d1f73bf130 21 * may be used to endorse or promote products derived from this software
vladvana 0:23d1f73bf130 22 * without specific prior written permission.
vladvana 0:23d1f73bf130 23 *
vladvana 0:23d1f73bf130 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana 0:23d1f73bf130 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana 0:23d1f73bf130 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana 0:23d1f73bf130 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana 0:23d1f73bf130 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana 0:23d1f73bf130 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana 0:23d1f73bf130 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana 0:23d1f73bf130 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana 0:23d1f73bf130 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana 0:23d1f73bf130 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana 0:23d1f73bf130 34 *
vladvana 0:23d1f73bf130 35 ******************************************************************************
vladvana 0:23d1f73bf130 36 */
vladvana 0:23d1f73bf130 37
vladvana 0:23d1f73bf130 38 /* Define to prevent recursive inclusion -------------------------------------*/
vladvana 0:23d1f73bf130 39 #ifndef __STM32F1xx_HAL_DMA_H
vladvana 0:23d1f73bf130 40 #define __STM32F1xx_HAL_DMA_H
vladvana 0:23d1f73bf130 41
vladvana 0:23d1f73bf130 42 #ifdef __cplusplus
vladvana 0:23d1f73bf130 43 extern "C" {
vladvana 0:23d1f73bf130 44 #endif
vladvana 0:23d1f73bf130 45
vladvana 0:23d1f73bf130 46 /* Includes ------------------------------------------------------------------*/
vladvana 0:23d1f73bf130 47 #include "stm32f1xx_hal_def.h"
vladvana 0:23d1f73bf130 48
vladvana 0:23d1f73bf130 49 /** @addtogroup STM32F1xx_HAL_Driver
vladvana 0:23d1f73bf130 50 * @{
vladvana 0:23d1f73bf130 51 */
vladvana 0:23d1f73bf130 52
vladvana 0:23d1f73bf130 53 /** @addtogroup DMA
vladvana 0:23d1f73bf130 54 * @{
vladvana 0:23d1f73bf130 55 */
vladvana 0:23d1f73bf130 56
vladvana 0:23d1f73bf130 57 /* Exported types ------------------------------------------------------------*/
vladvana 0:23d1f73bf130 58 /** @defgroup DMA_Exported_Types DMA Exported Types
vladvana 0:23d1f73bf130 59 * @{
vladvana 0:23d1f73bf130 60 */
vladvana 0:23d1f73bf130 61
vladvana 0:23d1f73bf130 62 /**
vladvana 0:23d1f73bf130 63 * @brief DMA Configuration Structure definition
vladvana 0:23d1f73bf130 64 */
vladvana 0:23d1f73bf130 65 typedef struct
vladvana 0:23d1f73bf130 66 {
vladvana 0:23d1f73bf130 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
vladvana 0:23d1f73bf130 68 from memory to memory or from peripheral to memory.
vladvana 0:23d1f73bf130 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
vladvana 0:23d1f73bf130 70
vladvana 0:23d1f73bf130 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
vladvana 0:23d1f73bf130 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
vladvana 0:23d1f73bf130 73
vladvana 0:23d1f73bf130 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
vladvana 0:23d1f73bf130 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
vladvana 0:23d1f73bf130 76
vladvana 0:23d1f73bf130 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
vladvana 0:23d1f73bf130 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
vladvana 0:23d1f73bf130 79
vladvana 0:23d1f73bf130 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
vladvana 0:23d1f73bf130 81 This parameter can be a value of @ref DMA_Memory_data_size */
vladvana 0:23d1f73bf130 82
vladvana 0:23d1f73bf130 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
vladvana 0:23d1f73bf130 84 This parameter can be a value of @ref DMA_mode
vladvana 0:23d1f73bf130 85 @note The circular buffer mode cannot be used if the memory-to-memory
vladvana 0:23d1f73bf130 86 data transfer is configured on the selected Channel */
vladvana 0:23d1f73bf130 87
vladvana 0:23d1f73bf130 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
vladvana 0:23d1f73bf130 89 This parameter can be a value of @ref DMA_Priority_level */
vladvana 0:23d1f73bf130 90
vladvana 0:23d1f73bf130 91 } DMA_InitTypeDef;
vladvana 0:23d1f73bf130 92
vladvana 0:23d1f73bf130 93 /**
vladvana 0:23d1f73bf130 94 * @brief DMA Configuration enumeration values definition
vladvana 0:23d1f73bf130 95 */
vladvana 0:23d1f73bf130 96 typedef enum
vladvana 0:23d1f73bf130 97 {
vladvana 0:23d1f73bf130 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
vladvana 0:23d1f73bf130 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
vladvana 0:23d1f73bf130 100
vladvana 0:23d1f73bf130 101 } DMA_ControlTypeDef;
vladvana 0:23d1f73bf130 102
vladvana 0:23d1f73bf130 103 /**
vladvana 0:23d1f73bf130 104 * @brief HAL DMA State structures definition
vladvana 0:23d1f73bf130 105 */
vladvana 0:23d1f73bf130 106 typedef enum
vladvana 0:23d1f73bf130 107 {
vladvana 0:23d1f73bf130 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
vladvana 0:23d1f73bf130 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
vladvana 0:23d1f73bf130 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
vladvana 0:23d1f73bf130 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
vladvana 0:23d1f73bf130 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
vladvana 0:23d1f73bf130 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
vladvana 0:23d1f73bf130 114
vladvana 0:23d1f73bf130 115 }HAL_DMA_StateTypeDef;
vladvana 0:23d1f73bf130 116
vladvana 0:23d1f73bf130 117 /**
vladvana 0:23d1f73bf130 118 * @brief HAL DMA Error Code structure definition
vladvana 0:23d1f73bf130 119 */
vladvana 0:23d1f73bf130 120 typedef enum
vladvana 0:23d1f73bf130 121 {
vladvana 0:23d1f73bf130 122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
vladvana 0:23d1f73bf130 123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
vladvana 0:23d1f73bf130 124
vladvana 0:23d1f73bf130 125 }HAL_DMA_LevelCompleteTypeDef;
vladvana 0:23d1f73bf130 126
vladvana 0:23d1f73bf130 127 /**
vladvana 0:23d1f73bf130 128 * @brief DMA handle Structure definition
vladvana 0:23d1f73bf130 129 */
vladvana 0:23d1f73bf130 130 typedef struct __DMA_HandleTypeDef
vladvana 0:23d1f73bf130 131 {
vladvana 0:23d1f73bf130 132 DMA_Channel_TypeDef *Instance; /*!< Register base address */
vladvana 0:23d1f73bf130 133
vladvana 0:23d1f73bf130 134 DMA_InitTypeDef Init; /*!< DMA communication parameters */
vladvana 0:23d1f73bf130 135
vladvana 0:23d1f73bf130 136 HAL_LockTypeDef Lock; /*!< DMA locking object */
vladvana 0:23d1f73bf130 137
vladvana 0:23d1f73bf130 138 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
vladvana 0:23d1f73bf130 139
vladvana 0:23d1f73bf130 140 void *Parent; /*!< Parent object state */
vladvana 0:23d1f73bf130 141
vladvana 0:23d1f73bf130 142 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
vladvana 0:23d1f73bf130 143
vladvana 0:23d1f73bf130 144 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
vladvana 0:23d1f73bf130 145
vladvana 0:23d1f73bf130 146 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
vladvana 0:23d1f73bf130 147
vladvana 0:23d1f73bf130 148 __IO uint32_t ErrorCode; /*!< DMA Error code */
vladvana 0:23d1f73bf130 149
vladvana 0:23d1f73bf130 150 } DMA_HandleTypeDef;
vladvana 0:23d1f73bf130 151 /**
vladvana 0:23d1f73bf130 152 * @}
vladvana 0:23d1f73bf130 153 */
vladvana 0:23d1f73bf130 154
vladvana 0:23d1f73bf130 155 /* Exported constants --------------------------------------------------------*/
vladvana 0:23d1f73bf130 156 /** @defgroup DMA_Exported_Constants DMA Exported Constants
vladvana 0:23d1f73bf130 157 * @{
vladvana 0:23d1f73bf130 158 */
vladvana 0:23d1f73bf130 159
vladvana 0:23d1f73bf130 160 /** @defgroup DMA_Error_Codes DMA Error Codes
vladvana 0:23d1f73bf130 161 * @{
vladvana 0:23d1f73bf130 162 */
vladvana 0:23d1f73bf130 163 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
vladvana 0:23d1f73bf130 164 #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
vladvana 0:23d1f73bf130 165 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
vladvana 0:23d1f73bf130 166
vladvana 0:23d1f73bf130 167 /**
vladvana 0:23d1f73bf130 168 * @}
vladvana 0:23d1f73bf130 169 */
vladvana 0:23d1f73bf130 170
vladvana 0:23d1f73bf130 171
vladvana 0:23d1f73bf130 172
vladvana 0:23d1f73bf130 173 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
vladvana 0:23d1f73bf130 174 * @{
vladvana 0:23d1f73bf130 175 */
vladvana 0:23d1f73bf130 176 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
vladvana 0:23d1f73bf130 177 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
vladvana 0:23d1f73bf130 178 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
vladvana 0:23d1f73bf130 179
vladvana 0:23d1f73bf130 180 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
vladvana 0:23d1f73bf130 181 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
vladvana 0:23d1f73bf130 182 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
vladvana 0:23d1f73bf130 183 /**
vladvana 0:23d1f73bf130 184 * @}
vladvana 0:23d1f73bf130 185 */
vladvana 0:23d1f73bf130 186
vladvana 0:23d1f73bf130 187 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
vladvana 0:23d1f73bf130 188 * @{
vladvana 0:23d1f73bf130 189 */
vladvana 0:23d1f73bf130 190 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
vladvana 0:23d1f73bf130 191 /**
vladvana 0:23d1f73bf130 192 * @}
vladvana 0:23d1f73bf130 193 */
vladvana 0:23d1f73bf130 194
vladvana 0:23d1f73bf130 195 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
vladvana 0:23d1f73bf130 196 * @{
vladvana 0:23d1f73bf130 197 */
vladvana 0:23d1f73bf130 198 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
vladvana 0:23d1f73bf130 199 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
vladvana 0:23d1f73bf130 200
vladvana 0:23d1f73bf130 201 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
vladvana 0:23d1f73bf130 202 ((STATE) == DMA_PINC_DISABLE))
vladvana 0:23d1f73bf130 203 /**
vladvana 0:23d1f73bf130 204 * @}
vladvana 0:23d1f73bf130 205 */
vladvana 0:23d1f73bf130 206
vladvana 0:23d1f73bf130 207 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
vladvana 0:23d1f73bf130 208 * @{
vladvana 0:23d1f73bf130 209 */
vladvana 0:23d1f73bf130 210 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
vladvana 0:23d1f73bf130 211 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
vladvana 0:23d1f73bf130 212
vladvana 0:23d1f73bf130 213 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
vladvana 0:23d1f73bf130 214 ((STATE) == DMA_MINC_DISABLE))
vladvana 0:23d1f73bf130 215 /**
vladvana 0:23d1f73bf130 216 * @}
vladvana 0:23d1f73bf130 217 */
vladvana 0:23d1f73bf130 218
vladvana 0:23d1f73bf130 219 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
vladvana 0:23d1f73bf130 220 * @{
vladvana 0:23d1f73bf130 221 */
vladvana 0:23d1f73bf130 222 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
vladvana 0:23d1f73bf130 223 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
vladvana 0:23d1f73bf130 224 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
vladvana 0:23d1f73bf130 225
vladvana 0:23d1f73bf130 226 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
vladvana 0:23d1f73bf130 227 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
vladvana 0:23d1f73bf130 228 ((SIZE) == DMA_PDATAALIGN_WORD))
vladvana 0:23d1f73bf130 229 /**
vladvana 0:23d1f73bf130 230 * @}
vladvana 0:23d1f73bf130 231 */
vladvana 0:23d1f73bf130 232
vladvana 0:23d1f73bf130 233
vladvana 0:23d1f73bf130 234 /** @defgroup DMA_Memory_data_size DMA Memory data size
vladvana 0:23d1f73bf130 235 * @{
vladvana 0:23d1f73bf130 236 */
vladvana 0:23d1f73bf130 237 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
vladvana 0:23d1f73bf130 238 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
vladvana 0:23d1f73bf130 239 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
vladvana 0:23d1f73bf130 240
vladvana 0:23d1f73bf130 241 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
vladvana 0:23d1f73bf130 242 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
vladvana 0:23d1f73bf130 243 ((SIZE) == DMA_MDATAALIGN_WORD ))
vladvana 0:23d1f73bf130 244 /**
vladvana 0:23d1f73bf130 245 * @}
vladvana 0:23d1f73bf130 246 */
vladvana 0:23d1f73bf130 247
vladvana 0:23d1f73bf130 248 /** @defgroup DMA_mode DMA mode
vladvana 0:23d1f73bf130 249 * @{
vladvana 0:23d1f73bf130 250 */
vladvana 0:23d1f73bf130 251 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
vladvana 0:23d1f73bf130 252 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
vladvana 0:23d1f73bf130 253
vladvana 0:23d1f73bf130 254 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
vladvana 0:23d1f73bf130 255 ((MODE) == DMA_CIRCULAR))
vladvana 0:23d1f73bf130 256 /**
vladvana 0:23d1f73bf130 257 * @}
vladvana 0:23d1f73bf130 258 */
vladvana 0:23d1f73bf130 259
vladvana 0:23d1f73bf130 260 /** @defgroup DMA_Priority_level DMA Priority level
vladvana 0:23d1f73bf130 261 * @{
vladvana 0:23d1f73bf130 262 */
vladvana 0:23d1f73bf130 263 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
vladvana 0:23d1f73bf130 264 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
vladvana 0:23d1f73bf130 265 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
vladvana 0:23d1f73bf130 266 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
vladvana 0:23d1f73bf130 267
vladvana 0:23d1f73bf130 268 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
vladvana 0:23d1f73bf130 269 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
vladvana 0:23d1f73bf130 270 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
vladvana 0:23d1f73bf130 271 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
vladvana 0:23d1f73bf130 272 /**
vladvana 0:23d1f73bf130 273 * @}
vladvana 0:23d1f73bf130 274 */
vladvana 0:23d1f73bf130 275
vladvana 0:23d1f73bf130 276
vladvana 0:23d1f73bf130 277 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
vladvana 0:23d1f73bf130 278 * @{
vladvana 0:23d1f73bf130 279 */
vladvana 0:23d1f73bf130 280
vladvana 0:23d1f73bf130 281 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
vladvana 0:23d1f73bf130 282 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
vladvana 0:23d1f73bf130 283 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
vladvana 0:23d1f73bf130 284
vladvana 0:23d1f73bf130 285 /**
vladvana 0:23d1f73bf130 286 * @}
vladvana 0:23d1f73bf130 287 */
vladvana 0:23d1f73bf130 288
vladvana 0:23d1f73bf130 289 /** @defgroup DMA_flag_definitions DMA flag definitions
vladvana 0:23d1f73bf130 290 * @{
vladvana 0:23d1f73bf130 291 */
vladvana 0:23d1f73bf130 292
vladvana 0:23d1f73bf130 293 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
vladvana 0:23d1f73bf130 294 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
vladvana 0:23d1f73bf130 295 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
vladvana 0:23d1f73bf130 296 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
vladvana 0:23d1f73bf130 297 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
vladvana 0:23d1f73bf130 298 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
vladvana 0:23d1f73bf130 299 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
vladvana 0:23d1f73bf130 300 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
vladvana 0:23d1f73bf130 301 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
vladvana 0:23d1f73bf130 302 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
vladvana 0:23d1f73bf130 303 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
vladvana 0:23d1f73bf130 304 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
vladvana 0:23d1f73bf130 305 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
vladvana 0:23d1f73bf130 306 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
vladvana 0:23d1f73bf130 307 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
vladvana 0:23d1f73bf130 308 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
vladvana 0:23d1f73bf130 309 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
vladvana 0:23d1f73bf130 310 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
vladvana 0:23d1f73bf130 311 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
vladvana 0:23d1f73bf130 312 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
vladvana 0:23d1f73bf130 313 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
vladvana 0:23d1f73bf130 314 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
vladvana 0:23d1f73bf130 315 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
vladvana 0:23d1f73bf130 316 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
vladvana 0:23d1f73bf130 317 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
vladvana 0:23d1f73bf130 318 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
vladvana 0:23d1f73bf130 319 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
vladvana 0:23d1f73bf130 320 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
vladvana 0:23d1f73bf130 321
vladvana 0:23d1f73bf130 322
vladvana 0:23d1f73bf130 323 /**
vladvana 0:23d1f73bf130 324 * @}
vladvana 0:23d1f73bf130 325 */
vladvana 0:23d1f73bf130 326
vladvana 0:23d1f73bf130 327 /**
vladvana 0:23d1f73bf130 328 * @}
vladvana 0:23d1f73bf130 329 */
vladvana 0:23d1f73bf130 330
vladvana 0:23d1f73bf130 331 /* Exported macros -----------------------------------------------------------*/
vladvana 0:23d1f73bf130 332 /** @defgroup DMA_Exported_Macros DMA Exported Macros
vladvana 0:23d1f73bf130 333 * @{
vladvana 0:23d1f73bf130 334 */
vladvana 0:23d1f73bf130 335
vladvana 0:23d1f73bf130 336 /** @brief Reset DMA handle state
vladvana 0:23d1f73bf130 337 * @param __HANDLE__: DMA handle.
vladvana 0:23d1f73bf130 338 * @retval None
vladvana 0:23d1f73bf130 339 */
vladvana 0:23d1f73bf130 340 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
vladvana 0:23d1f73bf130 341
vladvana 0:23d1f73bf130 342 /**
vladvana 0:23d1f73bf130 343 * @brief Enable the specified DMA Channel.
vladvana 0:23d1f73bf130 344 * @param __HANDLE__: DMA handle
vladvana 0:23d1f73bf130 345 * @retval None.
vladvana 0:23d1f73bf130 346 */
vladvana 0:23d1f73bf130 347 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
vladvana 0:23d1f73bf130 348
vladvana 0:23d1f73bf130 349 /**
vladvana 0:23d1f73bf130 350 * @brief Disable the specified DMA Channel.
vladvana 0:23d1f73bf130 351 * @param __HANDLE__: DMA handle
vladvana 0:23d1f73bf130 352 * @retval None.
vladvana 0:23d1f73bf130 353 */
vladvana 0:23d1f73bf130 354 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
vladvana 0:23d1f73bf130 355
vladvana 0:23d1f73bf130 356
vladvana 0:23d1f73bf130 357 /* Interrupt & Flag management */
vladvana 0:23d1f73bf130 358
vladvana 0:23d1f73bf130 359 /**
vladvana 0:23d1f73bf130 360 * @brief Enables the specified DMA Channel interrupts.
vladvana 0:23d1f73bf130 361 * @param __HANDLE__: DMA handle
vladvana 0:23d1f73bf130 362 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
vladvana 0:23d1f73bf130 363 * This parameter can be any combination of the following values:
vladvana 0:23d1f73bf130 364 * @arg DMA_IT_TC: Transfer complete interrupt mask
vladvana 0:23d1f73bf130 365 * @arg DMA_IT_HT: Half transfer complete interrupt mask
vladvana 0:23d1f73bf130 366 * @arg DMA_IT_TE: Transfer error interrupt mask
vladvana 0:23d1f73bf130 367 * @retval None
vladvana 0:23d1f73bf130 368 */
vladvana 0:23d1f73bf130 369 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
vladvana 0:23d1f73bf130 370
vladvana 0:23d1f73bf130 371 /**
vladvana 0:23d1f73bf130 372 * @brief Disables the specified DMA Channel interrupts.
vladvana 0:23d1f73bf130 373 * @param __HANDLE__: DMA handle
vladvana 0:23d1f73bf130 374 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
vladvana 0:23d1f73bf130 375 * This parameter can be any combination of the following values:
vladvana 0:23d1f73bf130 376 * @arg DMA_IT_TC: Transfer complete interrupt mask
vladvana 0:23d1f73bf130 377 * @arg DMA_IT_HT: Half transfer complete interrupt mask
vladvana 0:23d1f73bf130 378 * @arg DMA_IT_TE: Transfer error interrupt mask
vladvana 0:23d1f73bf130 379 * @retval None
vladvana 0:23d1f73bf130 380 */
vladvana 0:23d1f73bf130 381 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
vladvana 0:23d1f73bf130 382
vladvana 0:23d1f73bf130 383 /**
vladvana 0:23d1f73bf130 384 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
vladvana 0:23d1f73bf130 385 * @param __HANDLE__: DMA handle
vladvana 0:23d1f73bf130 386 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
vladvana 0:23d1f73bf130 387 * This parameter can be one of the following values:
vladvana 0:23d1f73bf130 388 * @arg DMA_IT_TC: Transfer complete interrupt mask
vladvana 0:23d1f73bf130 389 * @arg DMA_IT_HT: Half transfer complete interrupt mask
vladvana 0:23d1f73bf130 390 * @arg DMA_IT_TE: Transfer error interrupt mask
vladvana 0:23d1f73bf130 391 * @retval The state of DMA_IT (SET or RESET).
vladvana 0:23d1f73bf130 392 */
vladvana 0:23d1f73bf130 393 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
vladvana 0:23d1f73bf130 394
vladvana 0:23d1f73bf130 395 /**
vladvana 0:23d1f73bf130 396 * @}
vladvana 0:23d1f73bf130 397 */
vladvana 0:23d1f73bf130 398
vladvana 0:23d1f73bf130 399 /* Include DMA HAL Extension module */
vladvana 0:23d1f73bf130 400 #include "stm32f1xx_hal_dma_ex.h"
vladvana 0:23d1f73bf130 401
vladvana 0:23d1f73bf130 402 /* Exported functions --------------------------------------------------------*/
vladvana 0:23d1f73bf130 403 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
vladvana 0:23d1f73bf130 404 * @{
vladvana 0:23d1f73bf130 405 */
vladvana 0:23d1f73bf130 406
vladvana 0:23d1f73bf130 407 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
vladvana 0:23d1f73bf130 408 * @{
vladvana 0:23d1f73bf130 409 */
vladvana 0:23d1f73bf130 410 /* Initialization and de-initialization functions *****************************/
vladvana 0:23d1f73bf130 411 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
vladvana 0:23d1f73bf130 412 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
vladvana 0:23d1f73bf130 413 /**
vladvana 0:23d1f73bf130 414 * @}
vladvana 0:23d1f73bf130 415 */
vladvana 0:23d1f73bf130 416
vladvana 0:23d1f73bf130 417 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
vladvana 0:23d1f73bf130 418 * @{
vladvana 0:23d1f73bf130 419 */
vladvana 0:23d1f73bf130 420 /* IO operation functions *****************************************************/
vladvana 0:23d1f73bf130 421 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
vladvana 0:23d1f73bf130 422 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
vladvana 0:23d1f73bf130 423 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
vladvana 0:23d1f73bf130 424 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
vladvana 0:23d1f73bf130 425 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
vladvana 0:23d1f73bf130 426 /**
vladvana 0:23d1f73bf130 427 * @}
vladvana 0:23d1f73bf130 428 */
vladvana 0:23d1f73bf130 429
vladvana 0:23d1f73bf130 430 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
vladvana 0:23d1f73bf130 431 * @{
vladvana 0:23d1f73bf130 432 */
vladvana 0:23d1f73bf130 433 /* Peripheral State and Error functions ***************************************/
vladvana 0:23d1f73bf130 434 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
vladvana 0:23d1f73bf130 435 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
vladvana 0:23d1f73bf130 436 /**
vladvana 0:23d1f73bf130 437 * @}
vladvana 0:23d1f73bf130 438 */
vladvana 0:23d1f73bf130 439
vladvana 0:23d1f73bf130 440 /**
vladvana 0:23d1f73bf130 441 * @}
vladvana 0:23d1f73bf130 442 */
vladvana 0:23d1f73bf130 443
vladvana 0:23d1f73bf130 444 /**
vladvana 0:23d1f73bf130 445 * @}
vladvana 0:23d1f73bf130 446 */
vladvana 0:23d1f73bf130 447
vladvana 0:23d1f73bf130 448 /**
vladvana 0:23d1f73bf130 449 * @}
vladvana 0:23d1f73bf130 450 */
vladvana 0:23d1f73bf130 451
vladvana 0:23d1f73bf130 452 #ifdef __cplusplus
vladvana 0:23d1f73bf130 453 }
vladvana 0:23d1f73bf130 454 #endif
vladvana 0:23d1f73bf130 455
vladvana 0:23d1f73bf130 456 #endif /* __STM32F1xx_HAL_DMA_H */
vladvana 0:23d1f73bf130 457
vladvana 0:23d1f73bf130 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/