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TARGET_NUCLEO_F103RB/stm32f103xb.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:: vladvana
Date:: Sun Sep 24 12:31:52 2017 +0000
Revision:: 0:23d1f73bf130

podklady pro cviceni z PSS

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User	Revision	Line number	New contents of line
vladvana	0:23d1f73bf130	1	/**
vladvana	0:23d1f73bf130	2	******************************************************************************
vladvana	0:23d1f73bf130	3	* @file stm32f103xb.h
vladvana	0:23d1f73bf130	4	* @author MCD Application Team
vladvana	0:23d1f73bf130	5	* @version V4.0.0
vladvana	0:23d1f73bf130	6	* @date 16-December-2014
vladvana	0:23d1f73bf130	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
vladvana	0:23d1f73bf130	8	* This file contains all the peripheral register's definitions, bits
vladvana	0:23d1f73bf130	9	* definitions and memory mapping for STM32F1xx devices.
vladvana	0:23d1f73bf130	10	*
vladvana	0:23d1f73bf130	11	* This file contains:
vladvana	0:23d1f73bf130	12	* - Data structures and the address mapping for all peripherals
vladvana	0:23d1f73bf130	13	* - Peripheral's registers declarations and bits definition
vladvana	0:23d1f73bf130	14	* - Macros to access peripherals registers hardware
vladvana	0:23d1f73bf130	15	*
vladvana	0:23d1f73bf130	16	******************************************************************************
vladvana	0:23d1f73bf130	17	* @attention
vladvana	0:23d1f73bf130	18	*
vladvana	0:23d1f73bf130	19	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vladvana	0:23d1f73bf130	20	*
vladvana	0:23d1f73bf130	21	* Redistribution and use in source and binary forms, with or without modification,
vladvana	0:23d1f73bf130	22	* are permitted provided that the following conditions are met:
vladvana	0:23d1f73bf130	23	* 1. Redistributions of source code must retain the above copyright notice,
vladvana	0:23d1f73bf130	24	* this list of conditions and the following disclaimer.
vladvana	0:23d1f73bf130	25	* 2. Redistributions in binary form must reproduce the above copyright notice,
vladvana	0:23d1f73bf130	26	* this list of conditions and the following disclaimer in the documentation
vladvana	0:23d1f73bf130	27	* and/or other materials provided with the distribution.
vladvana	0:23d1f73bf130	28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
vladvana	0:23d1f73bf130	29	* may be used to endorse or promote products derived from this software
vladvana	0:23d1f73bf130	30	* without specific prior written permission.
vladvana	0:23d1f73bf130	31	*
vladvana	0:23d1f73bf130	32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana	0:23d1f73bf130	33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana	0:23d1f73bf130	34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vladvana	0:23d1f73bf130	35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vladvana	0:23d1f73bf130	36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vladvana	0:23d1f73bf130	37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vladvana	0:23d1f73bf130	38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vladvana	0:23d1f73bf130	39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vladvana	0:23d1f73bf130	40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vladvana	0:23d1f73bf130	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vladvana	0:23d1f73bf130	42	*
vladvana	0:23d1f73bf130	43	******************************************************************************
vladvana	0:23d1f73bf130	44	*/
vladvana	0:23d1f73bf130	45
vladvana	0:23d1f73bf130	46
vladvana	0:23d1f73bf130	47	/** @addtogroup CMSIS
vladvana	0:23d1f73bf130	48	* @{
vladvana	0:23d1f73bf130	49	*/
vladvana	0:23d1f73bf130	50
vladvana	0:23d1f73bf130	51	/** @addtogroup stm32f103xb
vladvana	0:23d1f73bf130	52	* @{
vladvana	0:23d1f73bf130	53	*/
vladvana	0:23d1f73bf130	54
vladvana	0:23d1f73bf130	55	#ifndef __STM32F103xB_H
vladvana	0:23d1f73bf130	56	#define __STM32F103xB_H
vladvana	0:23d1f73bf130	57
vladvana	0:23d1f73bf130	58	#ifdef __cplusplus
vladvana	0:23d1f73bf130	59	extern "C" {
vladvana	0:23d1f73bf130	60	#endif
vladvana	0:23d1f73bf130	61
vladvana	0:23d1f73bf130	62	/** @addtogroup Configuration_section_for_CMSIS
vladvana	0:23d1f73bf130	63	* @{
vladvana	0:23d1f73bf130	64	*/
vladvana	0:23d1f73bf130	65	/**
vladvana	0:23d1f73bf130	66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
vladvana	0:23d1f73bf130	67	*/
vladvana	0:23d1f73bf130	68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
vladvana	0:23d1f73bf130	69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
vladvana	0:23d1f73bf130	70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
vladvana	0:23d1f73bf130	71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
vladvana	0:23d1f73bf130	72
vladvana	0:23d1f73bf130	73	/**
vladvana	0:23d1f73bf130	74	* @}
vladvana	0:23d1f73bf130	75	*/
vladvana	0:23d1f73bf130	76
vladvana	0:23d1f73bf130	77	/** @addtogroup Peripheral_interrupt_number_definition
vladvana	0:23d1f73bf130	78	* @{
vladvana	0:23d1f73bf130	79	*/
vladvana	0:23d1f73bf130	80
vladvana	0:23d1f73bf130	81	/**
vladvana	0:23d1f73bf130	82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
vladvana	0:23d1f73bf130	83	* in @ref Library_configuration_section
vladvana	0:23d1f73bf130	84	*/
vladvana	0:23d1f73bf130	85
vladvana	0:23d1f73bf130	86	/!< Interrupt Number Definition /
vladvana	0:23d1f73bf130	87	typedef enum
vladvana	0:23d1f73bf130	88	{
vladvana	0:23d1f73bf130	89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
vladvana	0:23d1f73bf130	90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
vladvana	0:23d1f73bf130	91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
vladvana	0:23d1f73bf130	92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
vladvana	0:23d1f73bf130	93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
vladvana	0:23d1f73bf130	94	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
vladvana	0:23d1f73bf130	95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
vladvana	0:23d1f73bf130	96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
vladvana	0:23d1f73bf130	97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
vladvana	0:23d1f73bf130	98
vladvana	0:23d1f73bf130	99	/**** STM32 specific Interrupt Numbers *******************************************************/
vladvana	0:23d1f73bf130	100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
vladvana	0:23d1f73bf130	101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
vladvana	0:23d1f73bf130	102	TAMPER_IRQn = 2, /!< Tamper Interrupt /
vladvana	0:23d1f73bf130	103	RTC_IRQn = 3, /!< RTC global Interrupt /
vladvana	0:23d1f73bf130	104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
vladvana	0:23d1f73bf130	105	RCC_IRQn = 5, /!< RCC global Interrupt /
vladvana	0:23d1f73bf130	106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
vladvana	0:23d1f73bf130	107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
vladvana	0:23d1f73bf130	108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
vladvana	0:23d1f73bf130	109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
vladvana	0:23d1f73bf130	110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
vladvana	0:23d1f73bf130	111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
vladvana	0:23d1f73bf130	112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
vladvana	0:23d1f73bf130	113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
vladvana	0:23d1f73bf130	114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
vladvana	0:23d1f73bf130	115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
vladvana	0:23d1f73bf130	116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
vladvana	0:23d1f73bf130	117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
vladvana	0:23d1f73bf130	118	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
vladvana	0:23d1f73bf130	119	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
vladvana	0:23d1f73bf130	120	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
vladvana	0:23d1f73bf130	121	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
vladvana	0:23d1f73bf130	122	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
vladvana	0:23d1f73bf130	123	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
vladvana	0:23d1f73bf130	124	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
vladvana	0:23d1f73bf130	125	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
vladvana	0:23d1f73bf130	126	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
vladvana	0:23d1f73bf130	127	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
vladvana	0:23d1f73bf130	128	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
vladvana	0:23d1f73bf130	129	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
vladvana	0:23d1f73bf130	130	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
vladvana	0:23d1f73bf130	131	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
vladvana	0:23d1f73bf130	132	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
vladvana	0:23d1f73bf130	133	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
vladvana	0:23d1f73bf130	134	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
vladvana	0:23d1f73bf130	135	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
vladvana	0:23d1f73bf130	136	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
vladvana	0:23d1f73bf130	137	USART1_IRQn = 37, /!< USART1 global Interrupt /
vladvana	0:23d1f73bf130	138	USART2_IRQn = 38, /!< USART2 global Interrupt /
vladvana	0:23d1f73bf130	139	USART3_IRQn = 39, /!< USART3 global Interrupt /
vladvana	0:23d1f73bf130	140	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
vladvana	0:23d1f73bf130	141	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
vladvana	0:23d1f73bf130	142	USBWakeUp_IRQn = 42, /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
vladvana	0:23d1f73bf130	143	} IRQn_Type;
vladvana	0:23d1f73bf130	144
vladvana	0:23d1f73bf130	145
vladvana	0:23d1f73bf130	146	/**
vladvana	0:23d1f73bf130	147	* @}
vladvana	0:23d1f73bf130	148	*/
vladvana	0:23d1f73bf130	149
vladvana	0:23d1f73bf130	150	#include "core_cm3.h"
vladvana	0:23d1f73bf130	151	#include "system_stm32f1xx.h"
vladvana	0:23d1f73bf130	152	#include <stdint.h>
vladvana	0:23d1f73bf130	153
vladvana	0:23d1f73bf130	154	/** @addtogroup Peripheral_registers_structures
vladvana	0:23d1f73bf130	155	* @{
vladvana	0:23d1f73bf130	156	*/
vladvana	0:23d1f73bf130	157
vladvana	0:23d1f73bf130	158	/**
vladvana	0:23d1f73bf130	159	* @brief Analog to Digital Converter
vladvana	0:23d1f73bf130	160	*/
vladvana	0:23d1f73bf130	161
vladvana	0:23d1f73bf130	162	typedef struct
vladvana	0:23d1f73bf130	163	{
vladvana	0:23d1f73bf130	164	__IO uint32_t SR;
vladvana	0:23d1f73bf130	165	__IO uint32_t CR1;
vladvana	0:23d1f73bf130	166	__IO uint32_t CR2;
vladvana	0:23d1f73bf130	167	__IO uint32_t SMPR1;
vladvana	0:23d1f73bf130	168	__IO uint32_t SMPR2;
vladvana	0:23d1f73bf130	169	__IO uint32_t JOFR1;
vladvana	0:23d1f73bf130	170	__IO uint32_t JOFR2;
vladvana	0:23d1f73bf130	171	__IO uint32_t JOFR3;
vladvana	0:23d1f73bf130	172	__IO uint32_t JOFR4;
vladvana	0:23d1f73bf130	173	__IO uint32_t HTR;
vladvana	0:23d1f73bf130	174	__IO uint32_t LTR;
vladvana	0:23d1f73bf130	175	__IO uint32_t SQR1;
vladvana	0:23d1f73bf130	176	__IO uint32_t SQR2;
vladvana	0:23d1f73bf130	177	__IO uint32_t SQR3;
vladvana	0:23d1f73bf130	178	__IO uint32_t JSQR;
vladvana	0:23d1f73bf130	179	__IO uint32_t JDR1;
vladvana	0:23d1f73bf130	180	__IO uint32_t JDR2;
vladvana	0:23d1f73bf130	181	__IO uint32_t JDR3;
vladvana	0:23d1f73bf130	182	__IO uint32_t JDR4;
vladvana	0:23d1f73bf130	183	__IO uint32_t DR;
vladvana	0:23d1f73bf130	184	} ADC_TypeDef;
vladvana	0:23d1f73bf130	185
vladvana	0:23d1f73bf130	186	/**
vladvana	0:23d1f73bf130	187	* @brief Backup Registers
vladvana	0:23d1f73bf130	188	*/
vladvana	0:23d1f73bf130	189
vladvana	0:23d1f73bf130	190	typedef struct
vladvana	0:23d1f73bf130	191	{
vladvana	0:23d1f73bf130	192	uint32_t RESERVED0;
vladvana	0:23d1f73bf130	193	__IO uint32_t DR1;
vladvana	0:23d1f73bf130	194	__IO uint32_t DR2;
vladvana	0:23d1f73bf130	195	__IO uint32_t DR3;
vladvana	0:23d1f73bf130	196	__IO uint32_t DR4;
vladvana	0:23d1f73bf130	197	__IO uint32_t DR5;
vladvana	0:23d1f73bf130	198	__IO uint32_t DR6;
vladvana	0:23d1f73bf130	199	__IO uint32_t DR7;
vladvana	0:23d1f73bf130	200	__IO uint32_t DR8;
vladvana	0:23d1f73bf130	201	__IO uint32_t DR9;
vladvana	0:23d1f73bf130	202	__IO uint32_t DR10;
vladvana	0:23d1f73bf130	203	__IO uint32_t RTCCR;
vladvana	0:23d1f73bf130	204	__IO uint32_t CR;
vladvana	0:23d1f73bf130	205	__IO uint32_t CSR;
vladvana	0:23d1f73bf130	206	} BKP_TypeDef;
vladvana	0:23d1f73bf130	207
vladvana	0:23d1f73bf130	208	/**
vladvana	0:23d1f73bf130	209	* @brief Controller Area Network TxMailBox
vladvana	0:23d1f73bf130	210	*/
vladvana	0:23d1f73bf130	211
vladvana	0:23d1f73bf130	212	typedef struct
vladvana	0:23d1f73bf130	213	{
vladvana	0:23d1f73bf130	214	__IO uint32_t TIR;
vladvana	0:23d1f73bf130	215	__IO uint32_t TDTR;
vladvana	0:23d1f73bf130	216	__IO uint32_t TDLR;
vladvana	0:23d1f73bf130	217	__IO uint32_t TDHR;
vladvana	0:23d1f73bf130	218	} CAN_TxMailBox_TypeDef;
vladvana	0:23d1f73bf130	219
vladvana	0:23d1f73bf130	220	/**
vladvana	0:23d1f73bf130	221	* @brief Controller Area Network FIFOMailBox
vladvana	0:23d1f73bf130	222	*/
vladvana	0:23d1f73bf130	223
vladvana	0:23d1f73bf130	224	typedef struct
vladvana	0:23d1f73bf130	225	{
vladvana	0:23d1f73bf130	226	__IO uint32_t RIR;
vladvana	0:23d1f73bf130	227	__IO uint32_t RDTR;
vladvana	0:23d1f73bf130	228	__IO uint32_t RDLR;
vladvana	0:23d1f73bf130	229	__IO uint32_t RDHR;
vladvana	0:23d1f73bf130	230	} CAN_FIFOMailBox_TypeDef;
vladvana	0:23d1f73bf130	231
vladvana	0:23d1f73bf130	232	/**
vladvana	0:23d1f73bf130	233	* @brief Controller Area Network FilterRegister
vladvana	0:23d1f73bf130	234	*/
vladvana	0:23d1f73bf130	235
vladvana	0:23d1f73bf130	236	typedef struct
vladvana	0:23d1f73bf130	237	{
vladvana	0:23d1f73bf130	238	__IO uint32_t FR1;
vladvana	0:23d1f73bf130	239	__IO uint32_t FR2;
vladvana	0:23d1f73bf130	240	} CAN_FilterRegister_TypeDef;
vladvana	0:23d1f73bf130	241
vladvana	0:23d1f73bf130	242	/**
vladvana	0:23d1f73bf130	243	* @brief Controller Area Network
vladvana	0:23d1f73bf130	244	*/
vladvana	0:23d1f73bf130	245
vladvana	0:23d1f73bf130	246	typedef struct
vladvana	0:23d1f73bf130	247	{
vladvana	0:23d1f73bf130	248	__IO uint32_t MCR;
vladvana	0:23d1f73bf130	249	__IO uint32_t MSR;
vladvana	0:23d1f73bf130	250	__IO uint32_t TSR;
vladvana	0:23d1f73bf130	251	__IO uint32_t RF0R;
vladvana	0:23d1f73bf130	252	__IO uint32_t RF1R;
vladvana	0:23d1f73bf130	253	__IO uint32_t IER;
vladvana	0:23d1f73bf130	254	__IO uint32_t ESR;
vladvana	0:23d1f73bf130	255	__IO uint32_t BTR;
vladvana	0:23d1f73bf130	256	uint32_t RESERVED0[88];
vladvana	0:23d1f73bf130	257	CAN_TxMailBox_TypeDef sTxMailBox[3];
vladvana	0:23d1f73bf130	258	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
vladvana	0:23d1f73bf130	259	uint32_t RESERVED1[12];
vladvana	0:23d1f73bf130	260	__IO uint32_t FMR;
vladvana	0:23d1f73bf130	261	__IO uint32_t FM1R;
vladvana	0:23d1f73bf130	262	uint32_t RESERVED2;
vladvana	0:23d1f73bf130	263	__IO uint32_t FS1R;
vladvana	0:23d1f73bf130	264	uint32_t RESERVED3;
vladvana	0:23d1f73bf130	265	__IO uint32_t FFA1R;
vladvana	0:23d1f73bf130	266	uint32_t RESERVED4;
vladvana	0:23d1f73bf130	267	__IO uint32_t FA1R;
vladvana	0:23d1f73bf130	268	uint32_t RESERVED5[8];
vladvana	0:23d1f73bf130	269	CAN_FilterRegister_TypeDef sFilterRegister[14];
vladvana	0:23d1f73bf130	270	} CAN_TypeDef;
vladvana	0:23d1f73bf130	271
vladvana	0:23d1f73bf130	272	/**
vladvana	0:23d1f73bf130	273	* @brief CRC calculation unit
vladvana	0:23d1f73bf130	274	*/
vladvana	0:23d1f73bf130	275
vladvana	0:23d1f73bf130	276	typedef struct
vladvana	0:23d1f73bf130	277	{
vladvana	0:23d1f73bf130	278	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
vladvana	0:23d1f73bf130	279	__IO uint32_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
vladvana	0:23d1f73bf130	280	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
vladvana	0:23d1f73bf130	281	} CRC_TypeDef;
vladvana	0:23d1f73bf130	282
vladvana	0:23d1f73bf130	283
vladvana	0:23d1f73bf130	284	/**
vladvana	0:23d1f73bf130	285	* @brief Debug MCU
vladvana	0:23d1f73bf130	286	*/
vladvana	0:23d1f73bf130	287
vladvana	0:23d1f73bf130	288	typedef struct
vladvana	0:23d1f73bf130	289	{
vladvana	0:23d1f73bf130	290	__IO uint32_t IDCODE;
vladvana	0:23d1f73bf130	291	__IO uint32_t CR;
vladvana	0:23d1f73bf130	292	}DBGMCU_TypeDef;
vladvana	0:23d1f73bf130	293
vladvana	0:23d1f73bf130	294	/**
vladvana	0:23d1f73bf130	295	* @brief DMA Controller
vladvana	0:23d1f73bf130	296	*/
vladvana	0:23d1f73bf130	297
vladvana	0:23d1f73bf130	298	typedef struct
vladvana	0:23d1f73bf130	299	{
vladvana	0:23d1f73bf130	300	__IO uint32_t CCR;
vladvana	0:23d1f73bf130	301	__IO uint32_t CNDTR;
vladvana	0:23d1f73bf130	302	__IO uint32_t CPAR;
vladvana	0:23d1f73bf130	303	__IO uint32_t CMAR;
vladvana	0:23d1f73bf130	304	} DMA_Channel_TypeDef;
vladvana	0:23d1f73bf130	305
vladvana	0:23d1f73bf130	306	typedef struct
vladvana	0:23d1f73bf130	307	{
vladvana	0:23d1f73bf130	308	__IO uint32_t ISR;
vladvana	0:23d1f73bf130	309	__IO uint32_t IFCR;
vladvana	0:23d1f73bf130	310	} DMA_TypeDef;
vladvana	0:23d1f73bf130	311
vladvana	0:23d1f73bf130	312
vladvana	0:23d1f73bf130	313
vladvana	0:23d1f73bf130	314	/**
vladvana	0:23d1f73bf130	315	* @brief External Interrupt/Event Controller
vladvana	0:23d1f73bf130	316	*/
vladvana	0:23d1f73bf130	317
vladvana	0:23d1f73bf130	318	typedef struct
vladvana	0:23d1f73bf130	319	{
vladvana	0:23d1f73bf130	320	__IO uint32_t IMR;
vladvana	0:23d1f73bf130	321	__IO uint32_t EMR;
vladvana	0:23d1f73bf130	322	__IO uint32_t RTSR;
vladvana	0:23d1f73bf130	323	__IO uint32_t FTSR;
vladvana	0:23d1f73bf130	324	__IO uint32_t SWIER;
vladvana	0:23d1f73bf130	325	__IO uint32_t PR;
vladvana	0:23d1f73bf130	326	} EXTI_TypeDef;
vladvana	0:23d1f73bf130	327
vladvana	0:23d1f73bf130	328	/**
vladvana	0:23d1f73bf130	329	* @brief FLASH Registers
vladvana	0:23d1f73bf130	330	*/
vladvana	0:23d1f73bf130	331
vladvana	0:23d1f73bf130	332	typedef struct
vladvana	0:23d1f73bf130	333	{
vladvana	0:23d1f73bf130	334	__IO uint32_t ACR;
vladvana	0:23d1f73bf130	335	__IO uint32_t KEYR;
vladvana	0:23d1f73bf130	336	__IO uint32_t OPTKEYR;
vladvana	0:23d1f73bf130	337	__IO uint32_t SR;
vladvana	0:23d1f73bf130	338	__IO uint32_t CR;
vladvana	0:23d1f73bf130	339	__IO uint32_t AR;
vladvana	0:23d1f73bf130	340	__IO uint32_t RESERVED;
vladvana	0:23d1f73bf130	341	__IO uint32_t OBR;
vladvana	0:23d1f73bf130	342	__IO uint32_t WRPR;
vladvana	0:23d1f73bf130	343	} FLASH_TypeDef;
vladvana	0:23d1f73bf130	344
vladvana	0:23d1f73bf130	345	/**
vladvana	0:23d1f73bf130	346	* @brief Option Bytes Registers
vladvana	0:23d1f73bf130	347	*/
vladvana	0:23d1f73bf130	348
vladvana	0:23d1f73bf130	349	typedef struct
vladvana	0:23d1f73bf130	350	{
vladvana	0:23d1f73bf130	351	__IO uint16_t RDP;
vladvana	0:23d1f73bf130	352	__IO uint16_t USER;
vladvana	0:23d1f73bf130	353	__IO uint16_t Data0;
vladvana	0:23d1f73bf130	354	__IO uint16_t Data1;
vladvana	0:23d1f73bf130	355	__IO uint16_t WRP0;
vladvana	0:23d1f73bf130	356	__IO uint16_t WRP1;
vladvana	0:23d1f73bf130	357	__IO uint16_t WRP2;
vladvana	0:23d1f73bf130	358	__IO uint16_t WRP3;
vladvana	0:23d1f73bf130	359	} OB_TypeDef;
vladvana	0:23d1f73bf130	360
vladvana	0:23d1f73bf130	361	/**
vladvana	0:23d1f73bf130	362	* @brief General Purpose I/O
vladvana	0:23d1f73bf130	363	*/
vladvana	0:23d1f73bf130	364
vladvana	0:23d1f73bf130	365	typedef struct
vladvana	0:23d1f73bf130	366	{
vladvana	0:23d1f73bf130	367	__IO uint32_t CRL;
vladvana	0:23d1f73bf130	368	__IO uint32_t CRH;
vladvana	0:23d1f73bf130	369	__IO uint32_t IDR;
vladvana	0:23d1f73bf130	370	__IO uint32_t ODR;
vladvana	0:23d1f73bf130	371	__IO uint32_t BSRR;
vladvana	0:23d1f73bf130	372	__IO uint32_t BRR;
vladvana	0:23d1f73bf130	373	__IO uint32_t LCKR;
vladvana	0:23d1f73bf130	374	} GPIO_TypeDef;
vladvana	0:23d1f73bf130	375
vladvana	0:23d1f73bf130	376	/**
vladvana	0:23d1f73bf130	377	* @brief Alternate Function I/O
vladvana	0:23d1f73bf130	378	*/
vladvana	0:23d1f73bf130	379
vladvana	0:23d1f73bf130	380	typedef struct
vladvana	0:23d1f73bf130	381	{
vladvana	0:23d1f73bf130	382	__IO uint32_t EVCR;
vladvana	0:23d1f73bf130	383	__IO uint32_t MAPR;
vladvana	0:23d1f73bf130	384	__IO uint32_t EXTICR[4];
vladvana	0:23d1f73bf130	385	uint32_t RESERVED0;
vladvana	0:23d1f73bf130	386	__IO uint32_t MAPR2;
vladvana	0:23d1f73bf130	387	} AFIO_TypeDef;
vladvana	0:23d1f73bf130	388	/**
vladvana	0:23d1f73bf130	389	* @brief Inter Integrated Circuit Interface
vladvana	0:23d1f73bf130	390	*/
vladvana	0:23d1f73bf130	391
vladvana	0:23d1f73bf130	392	typedef struct
vladvana	0:23d1f73bf130	393	{
vladvana	0:23d1f73bf130	394	__IO uint32_t CR1;
vladvana	0:23d1f73bf130	395	__IO uint32_t CR2;
vladvana	0:23d1f73bf130	396	__IO uint32_t OAR1;
vladvana	0:23d1f73bf130	397	__IO uint32_t OAR2;
vladvana	0:23d1f73bf130	398	__IO uint32_t DR;
vladvana	0:23d1f73bf130	399	__IO uint32_t SR1;
vladvana	0:23d1f73bf130	400	__IO uint32_t SR2;
vladvana	0:23d1f73bf130	401	__IO uint32_t CCR;
vladvana	0:23d1f73bf130	402	__IO uint32_t TRISE;
vladvana	0:23d1f73bf130	403	} I2C_TypeDef;
vladvana	0:23d1f73bf130	404
vladvana	0:23d1f73bf130	405	/**
vladvana	0:23d1f73bf130	406	* @brief Independent WATCHDOG
vladvana	0:23d1f73bf130	407	*/
vladvana	0:23d1f73bf130	408
vladvana	0:23d1f73bf130	409	typedef struct
vladvana	0:23d1f73bf130	410	{
vladvana	0:23d1f73bf130	411	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
vladvana	0:23d1f73bf130	412	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
vladvana	0:23d1f73bf130	413	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
vladvana	0:23d1f73bf130	414	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
vladvana	0:23d1f73bf130	415	} IWDG_TypeDef;
vladvana	0:23d1f73bf130	416
vladvana	0:23d1f73bf130	417	/**
vladvana	0:23d1f73bf130	418	* @brief Power Control
vladvana	0:23d1f73bf130	419	*/
vladvana	0:23d1f73bf130	420
vladvana	0:23d1f73bf130	421	typedef struct
vladvana	0:23d1f73bf130	422	{
vladvana	0:23d1f73bf130	423	__IO uint32_t CR;
vladvana	0:23d1f73bf130	424	__IO uint32_t CSR;
vladvana	0:23d1f73bf130	425	} PWR_TypeDef;
vladvana	0:23d1f73bf130	426
vladvana	0:23d1f73bf130	427	/**
vladvana	0:23d1f73bf130	428	* @brief Reset and Clock Control
vladvana	0:23d1f73bf130	429	*/
vladvana	0:23d1f73bf130	430
vladvana	0:23d1f73bf130	431	typedef struct
vladvana	0:23d1f73bf130	432	{
vladvana	0:23d1f73bf130	433	__IO uint32_t CR;
vladvana	0:23d1f73bf130	434	__IO uint32_t CFGR;
vladvana	0:23d1f73bf130	435	__IO uint32_t CIR;
vladvana	0:23d1f73bf130	436	__IO uint32_t APB2RSTR;
vladvana	0:23d1f73bf130	437	__IO uint32_t APB1RSTR;
vladvana	0:23d1f73bf130	438	__IO uint32_t AHBENR;
vladvana	0:23d1f73bf130	439	__IO uint32_t APB2ENR;
vladvana	0:23d1f73bf130	440	__IO uint32_t APB1ENR;
vladvana	0:23d1f73bf130	441	__IO uint32_t BDCR;
vladvana	0:23d1f73bf130	442	__IO uint32_t CSR;
vladvana	0:23d1f73bf130	443
vladvana	0:23d1f73bf130	444
vladvana	0:23d1f73bf130	445	} RCC_TypeDef;
vladvana	0:23d1f73bf130	446
vladvana	0:23d1f73bf130	447	/**
vladvana	0:23d1f73bf130	448	* @brief Real-Time Clock
vladvana	0:23d1f73bf130	449	*/
vladvana	0:23d1f73bf130	450
vladvana	0:23d1f73bf130	451	typedef struct
vladvana	0:23d1f73bf130	452	{
vladvana	0:23d1f73bf130	453	__IO uint32_t CRH;
vladvana	0:23d1f73bf130	454	__IO uint32_t CRL;
vladvana	0:23d1f73bf130	455	__IO uint32_t PRLH;
vladvana	0:23d1f73bf130	456	__IO uint32_t PRLL;
vladvana	0:23d1f73bf130	457	__IO uint32_t DIVH;
vladvana	0:23d1f73bf130	458	__IO uint32_t DIVL;
vladvana	0:23d1f73bf130	459	__IO uint32_t CNTH;
vladvana	0:23d1f73bf130	460	__IO uint32_t CNTL;
vladvana	0:23d1f73bf130	461	__IO uint32_t ALRH;
vladvana	0:23d1f73bf130	462	__IO uint32_t ALRL;
vladvana	0:23d1f73bf130	463	} RTC_TypeDef;
vladvana	0:23d1f73bf130	464
vladvana	0:23d1f73bf130	465	/**
vladvana	0:23d1f73bf130	466	* @brief SD host Interface
vladvana	0:23d1f73bf130	467	*/
vladvana	0:23d1f73bf130	468
vladvana	0:23d1f73bf130	469	typedef struct
vladvana	0:23d1f73bf130	470	{
vladvana	0:23d1f73bf130	471	__IO uint32_t POWER;
vladvana	0:23d1f73bf130	472	__IO uint32_t CLKCR;
vladvana	0:23d1f73bf130	473	__IO uint32_t ARG;
vladvana	0:23d1f73bf130	474	__IO uint32_t CMD;
vladvana	0:23d1f73bf130	475	__I uint32_t RESPCMD;
vladvana	0:23d1f73bf130	476	__I uint32_t RESP1;
vladvana	0:23d1f73bf130	477	__I uint32_t RESP2;
vladvana	0:23d1f73bf130	478	__I uint32_t RESP3;
vladvana	0:23d1f73bf130	479	__I uint32_t RESP4;
vladvana	0:23d1f73bf130	480	__IO uint32_t DTIMER;
vladvana	0:23d1f73bf130	481	__IO uint32_t DLEN;
vladvana	0:23d1f73bf130	482	__IO uint32_t DCTRL;
vladvana	0:23d1f73bf130	483	__I uint32_t DCOUNT;
vladvana	0:23d1f73bf130	484	__I uint32_t STA;
vladvana	0:23d1f73bf130	485	__IO uint32_t ICR;
vladvana	0:23d1f73bf130	486	__IO uint32_t MASK;
vladvana	0:23d1f73bf130	487	uint32_t RESERVED0[2];
vladvana	0:23d1f73bf130	488	__I uint32_t FIFOCNT;
vladvana	0:23d1f73bf130	489	uint32_t RESERVED1[13];
vladvana	0:23d1f73bf130	490	__IO uint32_t FIFO;
vladvana	0:23d1f73bf130	491	} SDIO_TypeDef;
vladvana	0:23d1f73bf130	492
vladvana	0:23d1f73bf130	493	/**
vladvana	0:23d1f73bf130	494	* @brief Serial Peripheral Interface
vladvana	0:23d1f73bf130	495	*/
vladvana	0:23d1f73bf130	496
vladvana	0:23d1f73bf130	497	typedef struct
vladvana	0:23d1f73bf130	498	{
vladvana	0:23d1f73bf130	499	__IO uint32_t CR1;
vladvana	0:23d1f73bf130	500	__IO uint32_t CR2;
vladvana	0:23d1f73bf130	501	__IO uint32_t SR;
vladvana	0:23d1f73bf130	502	__IO uint32_t DR;
vladvana	0:23d1f73bf130	503	__IO uint32_t CRCPR;
vladvana	0:23d1f73bf130	504	__IO uint32_t RXCRCR;
vladvana	0:23d1f73bf130	505	__IO uint32_t TXCRCR;
vladvana	0:23d1f73bf130	506	__IO uint32_t I2SCFGR;
vladvana	0:23d1f73bf130	507	} SPI_TypeDef;
vladvana	0:23d1f73bf130	508
vladvana	0:23d1f73bf130	509	/**
vladvana	0:23d1f73bf130	510	* @brief TIM Timers
vladvana	0:23d1f73bf130	511	*/
vladvana	0:23d1f73bf130	512	typedef struct
vladvana	0:23d1f73bf130	513	{
vladvana	0:23d1f73bf130	514	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
vladvana	0:23d1f73bf130	515	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
vladvana	0:23d1f73bf130	516	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
vladvana	0:23d1f73bf130	517	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
vladvana	0:23d1f73bf130	518	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
vladvana	0:23d1f73bf130	519	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
vladvana	0:23d1f73bf130	520	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
vladvana	0:23d1f73bf130	521	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
vladvana	0:23d1f73bf130	522	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
vladvana	0:23d1f73bf130	523	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
vladvana	0:23d1f73bf130	524	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
vladvana	0:23d1f73bf130	525	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
vladvana	0:23d1f73bf130	526	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
vladvana	0:23d1f73bf130	527	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
vladvana	0:23d1f73bf130	528	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
vladvana	0:23d1f73bf130	529	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
vladvana	0:23d1f73bf130	530	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
vladvana	0:23d1f73bf130	531	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
vladvana	0:23d1f73bf130	532	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
vladvana	0:23d1f73bf130	533	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
vladvana	0:23d1f73bf130	534	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
vladvana	0:23d1f73bf130	535	}TIM_TypeDef;
vladvana	0:23d1f73bf130	536
vladvana	0:23d1f73bf130	537
vladvana	0:23d1f73bf130	538	/**
vladvana	0:23d1f73bf130	539	* @brief Universal Synchronous Asynchronous Receiver Transmitter
vladvana	0:23d1f73bf130	540	*/
vladvana	0:23d1f73bf130	541
vladvana	0:23d1f73bf130	542	typedef struct
vladvana	0:23d1f73bf130	543	{
vladvana	0:23d1f73bf130	544	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
vladvana	0:23d1f73bf130	545	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
vladvana	0:23d1f73bf130	546	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
vladvana	0:23d1f73bf130	547	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
vladvana	0:23d1f73bf130	548	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
vladvana	0:23d1f73bf130	549	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
vladvana	0:23d1f73bf130	550	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
vladvana	0:23d1f73bf130	551	} USART_TypeDef;
vladvana	0:23d1f73bf130	552
vladvana	0:23d1f73bf130	553	/**
vladvana	0:23d1f73bf130	554	* @brief Universal Serial Bus Full Speed Device
vladvana	0:23d1f73bf130	555	*/
vladvana	0:23d1f73bf130	556
vladvana	0:23d1f73bf130	557	typedef struct
vladvana	0:23d1f73bf130	558	{
vladvana	0:23d1f73bf130	559	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
vladvana	0:23d1f73bf130	560	__IO uint16_t RESERVED0; /!< Reserved /
vladvana	0:23d1f73bf130	561	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
vladvana	0:23d1f73bf130	562	__IO uint16_t RESERVED1; /!< Reserved /
vladvana	0:23d1f73bf130	563	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
vladvana	0:23d1f73bf130	564	__IO uint16_t RESERVED2; /!< Reserved /
vladvana	0:23d1f73bf130	565	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
vladvana	0:23d1f73bf130	566	__IO uint16_t RESERVED3; /!< Reserved /
vladvana	0:23d1f73bf130	567	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
vladvana	0:23d1f73bf130	568	__IO uint16_t RESERVED4; /!< Reserved /
vladvana	0:23d1f73bf130	569	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
vladvana	0:23d1f73bf130	570	__IO uint16_t RESERVED5; /!< Reserved /
vladvana	0:23d1f73bf130	571	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
vladvana	0:23d1f73bf130	572	__IO uint16_t RESERVED6; /!< Reserved /
vladvana	0:23d1f73bf130	573	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
vladvana	0:23d1f73bf130	574	__IO uint16_t RESERVED7[17]; /!< Reserved /
vladvana	0:23d1f73bf130	575	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
vladvana	0:23d1f73bf130	576	__IO uint16_t RESERVED8; /!< Reserved /
vladvana	0:23d1f73bf130	577	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
vladvana	0:23d1f73bf130	578	__IO uint16_t RESERVED9; /!< Reserved /
vladvana	0:23d1f73bf130	579	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
vladvana	0:23d1f73bf130	580	__IO uint16_t RESERVEDA; /!< Reserved /
vladvana	0:23d1f73bf130	581	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
vladvana	0:23d1f73bf130	582	__IO uint16_t RESERVEDB; /!< Reserved /
vladvana	0:23d1f73bf130	583	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
vladvana	0:23d1f73bf130	584	__IO uint16_t RESERVEDC; /!< Reserved /
vladvana	0:23d1f73bf130	585	} USB_TypeDef;
vladvana	0:23d1f73bf130	586
vladvana	0:23d1f73bf130	587
vladvana	0:23d1f73bf130	588	/**
vladvana	0:23d1f73bf130	589	* @brief Window WATCHDOG
vladvana	0:23d1f73bf130	590	*/
vladvana	0:23d1f73bf130	591
vladvana	0:23d1f73bf130	592	typedef struct
vladvana	0:23d1f73bf130	593	{
vladvana	0:23d1f73bf130	594	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
vladvana	0:23d1f73bf130	595	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
vladvana	0:23d1f73bf130	596	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
vladvana	0:23d1f73bf130	597	} WWDG_TypeDef;
vladvana	0:23d1f73bf130	598
vladvana	0:23d1f73bf130	599	/**
vladvana	0:23d1f73bf130	600	* @}
vladvana	0:23d1f73bf130	601	*/
vladvana	0:23d1f73bf130	602
vladvana	0:23d1f73bf130	603	/** @addtogroup Peripheral_memory_map
vladvana	0:23d1f73bf130	604	* @{
vladvana	0:23d1f73bf130	605	*/
vladvana	0:23d1f73bf130	606
vladvana	0:23d1f73bf130	607
vladvana	0:23d1f73bf130	608	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
vladvana	0:23d1f73bf130	609	#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /!< FLASH END address of bank1 /
vladvana	0:23d1f73bf130	610	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
vladvana	0:23d1f73bf130	611	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
vladvana	0:23d1f73bf130	612
vladvana	0:23d1f73bf130	613	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
vladvana	0:23d1f73bf130	614	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
vladvana	0:23d1f73bf130	615
vladvana	0:23d1f73bf130	616
vladvana	0:23d1f73bf130	617	/!< Peripheral memory map /
vladvana	0:23d1f73bf130	618	#define APB1PERIPH_BASE PERIPH_BASE
vladvana	0:23d1f73bf130	619	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
vladvana	0:23d1f73bf130	620	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
vladvana	0:23d1f73bf130	621
vladvana	0:23d1f73bf130	622	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
vladvana	0:23d1f73bf130	623	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
vladvana	0:23d1f73bf130	624	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
vladvana	0:23d1f73bf130	625	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
vladvana	0:23d1f73bf130	626	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
vladvana	0:23d1f73bf130	627	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
vladvana	0:23d1f73bf130	628	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
vladvana	0:23d1f73bf130	629	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
vladvana	0:23d1f73bf130	630	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
vladvana	0:23d1f73bf130	631	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
vladvana	0:23d1f73bf130	632	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
vladvana	0:23d1f73bf130	633	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
vladvana	0:23d1f73bf130	634	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
vladvana	0:23d1f73bf130	635	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
vladvana	0:23d1f73bf130	636	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
vladvana	0:23d1f73bf130	637	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
vladvana	0:23d1f73bf130	638	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
vladvana	0:23d1f73bf130	639	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
vladvana	0:23d1f73bf130	640	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
vladvana	0:23d1f73bf130	641	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
vladvana	0:23d1f73bf130	642	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
vladvana	0:23d1f73bf130	643	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
vladvana	0:23d1f73bf130	644	#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
vladvana	0:23d1f73bf130	645	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
vladvana	0:23d1f73bf130	646	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
vladvana	0:23d1f73bf130	647	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
vladvana	0:23d1f73bf130	648
vladvana	0:23d1f73bf130	649	#define SDIO_BASE (PERIPH_BASE + 0x18000)
vladvana	0:23d1f73bf130	650
vladvana	0:23d1f73bf130	651	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
vladvana	0:23d1f73bf130	652	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
vladvana	0:23d1f73bf130	653	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
vladvana	0:23d1f73bf130	654	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
vladvana	0:23d1f73bf130	655	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
vladvana	0:23d1f73bf130	656	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
vladvana	0:23d1f73bf130	657	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
vladvana	0:23d1f73bf130	658	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
vladvana	0:23d1f73bf130	659	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
vladvana	0:23d1f73bf130	660	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
vladvana	0:23d1f73bf130	661
vladvana	0:23d1f73bf130	662	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
vladvana	0:23d1f73bf130	663	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
vladvana	0:23d1f73bf130	664
vladvana	0:23d1f73bf130	665
vladvana	0:23d1f73bf130	666
vladvana	0:23d1f73bf130	667	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
vladvana	0:23d1f73bf130	668
vladvana	0:23d1f73bf130	669	/* USB device FS */
vladvana	0:23d1f73bf130	670	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
vladvana	0:23d1f73bf130	671	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
vladvana	0:23d1f73bf130	672
vladvana	0:23d1f73bf130	673
vladvana	0:23d1f73bf130	674	/**
vladvana	0:23d1f73bf130	675	* @}
vladvana	0:23d1f73bf130	676	*/
vladvana	0:23d1f73bf130	677
vladvana	0:23d1f73bf130	678	/** @addtogroup Peripheral_declaration
vladvana	0:23d1f73bf130	679	* @{
vladvana	0:23d1f73bf130	680	*/
vladvana	0:23d1f73bf130	681
vladvana	0:23d1f73bf130	682	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
vladvana	0:23d1f73bf130	683	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
vladvana	0:23d1f73bf130	684	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
vladvana	0:23d1f73bf130	685	#define RTC ((RTC_TypeDef *) RTC_BASE)
vladvana	0:23d1f73bf130	686	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
vladvana	0:23d1f73bf130	687	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
vladvana	0:23d1f73bf130	688	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
vladvana	0:23d1f73bf130	689	#define USART2 ((USART_TypeDef *) USART2_BASE)
vladvana	0:23d1f73bf130	690	#define USART3 ((USART_TypeDef *) USART3_BASE)
vladvana	0:23d1f73bf130	691	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
vladvana	0:23d1f73bf130	692	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
vladvana	0:23d1f73bf130	693	#define USB ((USB_TypeDef *) USB_BASE)
vladvana	0:23d1f73bf130	694	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
vladvana	0:23d1f73bf130	695	#define BKP ((BKP_TypeDef *) BKP_BASE)
vladvana	0:23d1f73bf130	696	#define PWR ((PWR_TypeDef *) PWR_BASE)
vladvana	0:23d1f73bf130	697	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
vladvana	0:23d1f73bf130	698	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
vladvana	0:23d1f73bf130	699	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
vladvana	0:23d1f73bf130	700	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
vladvana	0:23d1f73bf130	701	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
vladvana	0:23d1f73bf130	702	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
vladvana	0:23d1f73bf130	703	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
vladvana	0:23d1f73bf130	704	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
vladvana	0:23d1f73bf130	705	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
vladvana	0:23d1f73bf130	706	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
vladvana	0:23d1f73bf130	707	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
vladvana	0:23d1f73bf130	708	#define USART1 ((USART_TypeDef *) USART1_BASE)
vladvana	0:23d1f73bf130	709	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
vladvana	0:23d1f73bf130	710	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
vladvana	0:23d1f73bf130	711	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
vladvana	0:23d1f73bf130	712	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
vladvana	0:23d1f73bf130	713	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
vladvana	0:23d1f73bf130	714	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
vladvana	0:23d1f73bf130	715	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
vladvana	0:23d1f73bf130	716	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
vladvana	0:23d1f73bf130	717	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
vladvana	0:23d1f73bf130	718	#define RCC ((RCC_TypeDef *) RCC_BASE)
vladvana	0:23d1f73bf130	719	#define CRC ((CRC_TypeDef *) CRC_BASE)
vladvana	0:23d1f73bf130	720	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
vladvana	0:23d1f73bf130	721	#define OB ((OB_TypeDef *) OB_BASE)
vladvana	0:23d1f73bf130	722	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
vladvana	0:23d1f73bf130	723
vladvana	0:23d1f73bf130	724
vladvana	0:23d1f73bf130	725	/**
vladvana	0:23d1f73bf130	726	* @}
vladvana	0:23d1f73bf130	727	*/
vladvana	0:23d1f73bf130	728
vladvana	0:23d1f73bf130	729	/** @addtogroup Exported_constants
vladvana	0:23d1f73bf130	730	* @{
vladvana	0:23d1f73bf130	731	*/
vladvana	0:23d1f73bf130	732
vladvana	0:23d1f73bf130	733	/** @addtogroup Peripheral_Registers_Bits_Definition
vladvana	0:23d1f73bf130	734	* @{
vladvana	0:23d1f73bf130	735	*/
vladvana	0:23d1f73bf130	736
vladvana	0:23d1f73bf130	737	/******************************************************************************/
vladvana	0:23d1f73bf130	738	/* Peripheral Registers_Bits_Definition */
vladvana	0:23d1f73bf130	739	/******************************************************************************/
vladvana	0:23d1f73bf130	740
vladvana	0:23d1f73bf130	741	/******************************************************************************/
vladvana	0:23d1f73bf130	742	/* */
vladvana	0:23d1f73bf130	743	/* CRC calculation unit (CRC) */
vladvana	0:23d1f73bf130	744	/* */
vladvana	0:23d1f73bf130	745	/******************************************************************************/
vladvana	0:23d1f73bf130	746
vladvana	0:23d1f73bf130	747	/***************** Bit definition for CRC_DR register *******************/
vladvana	0:23d1f73bf130	748	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
vladvana	0:23d1f73bf130	749
vladvana	0:23d1f73bf130	750	/***************** Bit definition for CRC_IDR register ******************/
vladvana	0:23d1f73bf130	751	#define CRC_IDR_IDR ((uint32_t)0x000000FF) /!< General-purpose 8-bit data register bits /
vladvana	0:23d1f73bf130	752
vladvana	0:23d1f73bf130	753	/****************** Bit definition for CRC_CR register ******************/
vladvana	0:23d1f73bf130	754	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
vladvana	0:23d1f73bf130	755
vladvana	0:23d1f73bf130	756	/******************************************************************************/
vladvana	0:23d1f73bf130	757	/* */
vladvana	0:23d1f73bf130	758	/* Power Control */
vladvana	0:23d1f73bf130	759	/* */
vladvana	0:23d1f73bf130	760	/******************************************************************************/
vladvana	0:23d1f73bf130	761
vladvana	0:23d1f73bf130	762	/****************** Bit definition for PWR_CR register ******************/
vladvana	0:23d1f73bf130	763	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
vladvana	0:23d1f73bf130	764	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
vladvana	0:23d1f73bf130	765	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
vladvana	0:23d1f73bf130	766	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
vladvana	0:23d1f73bf130	767	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
vladvana	0:23d1f73bf130	768
vladvana	0:23d1f73bf130	769	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
vladvana	0:23d1f73bf130	770	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
vladvana	0:23d1f73bf130	771	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
vladvana	0:23d1f73bf130	772	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
vladvana	0:23d1f73bf130	773
vladvana	0:23d1f73bf130	774	/!< PVD level configuration /
vladvana	0:23d1f73bf130	775	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
vladvana	0:23d1f73bf130	776	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
vladvana	0:23d1f73bf130	777	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
vladvana	0:23d1f73bf130	778	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
vladvana	0:23d1f73bf130	779	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
vladvana	0:23d1f73bf130	780	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
vladvana	0:23d1f73bf130	781	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
vladvana	0:23d1f73bf130	782	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
vladvana	0:23d1f73bf130	783
vladvana	0:23d1f73bf130	784	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
vladvana	0:23d1f73bf130	785
vladvana	0:23d1f73bf130	786
vladvana	0:23d1f73bf130	787	/***************** Bit definition for PWR_CSR register ******************/
vladvana	0:23d1f73bf130	788	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
vladvana	0:23d1f73bf130	789	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
vladvana	0:23d1f73bf130	790	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
vladvana	0:23d1f73bf130	791	#define PWR_CSR_EWUP ((uint32_t)0x00000100) /!< Enable WKUP pin /
vladvana	0:23d1f73bf130	792
vladvana	0:23d1f73bf130	793	/******************************************************************************/
vladvana	0:23d1f73bf130	794	/* */
vladvana	0:23d1f73bf130	795	/* Backup registers */
vladvana	0:23d1f73bf130	796	/* */
vladvana	0:23d1f73bf130	797	/******************************************************************************/
vladvana	0:23d1f73bf130	798
vladvana	0:23d1f73bf130	799	/***************** Bit definition for BKP_DR1 register ******************/
vladvana	0:23d1f73bf130	800	#define BKP_DR1_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	801
vladvana	0:23d1f73bf130	802	/***************** Bit definition for BKP_DR2 register ******************/
vladvana	0:23d1f73bf130	803	#define BKP_DR2_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	804
vladvana	0:23d1f73bf130	805	/***************** Bit definition for BKP_DR3 register ******************/
vladvana	0:23d1f73bf130	806	#define BKP_DR3_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	807
vladvana	0:23d1f73bf130	808	/***************** Bit definition for BKP_DR4 register ******************/
vladvana	0:23d1f73bf130	809	#define BKP_DR4_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	810
vladvana	0:23d1f73bf130	811	/***************** Bit definition for BKP_DR5 register ******************/
vladvana	0:23d1f73bf130	812	#define BKP_DR5_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	813
vladvana	0:23d1f73bf130	814	/***************** Bit definition for BKP_DR6 register ******************/
vladvana	0:23d1f73bf130	815	#define BKP_DR6_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	816
vladvana	0:23d1f73bf130	817	/***************** Bit definition for BKP_DR7 register ******************/
vladvana	0:23d1f73bf130	818	#define BKP_DR7_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	819
vladvana	0:23d1f73bf130	820	/***************** Bit definition for BKP_DR8 register ******************/
vladvana	0:23d1f73bf130	821	#define BKP_DR8_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	822
vladvana	0:23d1f73bf130	823	/***************** Bit definition for BKP_DR9 register ******************/
vladvana	0:23d1f73bf130	824	#define BKP_DR9_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	825
vladvana	0:23d1f73bf130	826	/***************** Bit definition for BKP_DR10 register *****************/
vladvana	0:23d1f73bf130	827	#define BKP_DR10_D ((uint32_t)0x0000FFFF) /!< Backup data /
vladvana	0:23d1f73bf130	828
vladvana	0:23d1f73bf130	829	#define RTC_BKP_NUMBER 10
vladvana	0:23d1f73bf130	830
vladvana	0:23d1f73bf130	831	/**************** Bit definition for BKP_RTCCR register *****************/
vladvana	0:23d1f73bf130	832	#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /!< Calibration value /
vladvana	0:23d1f73bf130	833	#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /!< Calibration Clock Output /
vladvana	0:23d1f73bf130	834	#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /!< Alarm or Second Output Enable /
vladvana	0:23d1f73bf130	835	#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /!< Alarm or Second Output Selection /
vladvana	0:23d1f73bf130	836
vladvana	0:23d1f73bf130	837	/****************** Bit definition for BKP_CR register ******************/
vladvana	0:23d1f73bf130	838	#define BKP_CR_TPE ((uint32_t)0x00000001) /!< TAMPER pin enable /
vladvana	0:23d1f73bf130	839	#define BKP_CR_TPAL ((uint32_t)0x00000002) /!< TAMPER pin active level /
vladvana	0:23d1f73bf130	840
vladvana	0:23d1f73bf130	841	/***************** Bit definition for BKP_CSR register ******************/
vladvana	0:23d1f73bf130	842	#define BKP_CSR_CTE ((uint32_t)0x00000001) /!< Clear Tamper event /
vladvana	0:23d1f73bf130	843	#define BKP_CSR_CTI ((uint32_t)0x00000002) /!< Clear Tamper Interrupt /
vladvana	0:23d1f73bf130	844	#define BKP_CSR_TPIE ((uint32_t)0x00000004) /!< TAMPER Pin interrupt enable /
vladvana	0:23d1f73bf130	845	#define BKP_CSR_TEF ((uint32_t)0x00000100) /!< Tamper Event Flag /
vladvana	0:23d1f73bf130	846	#define BKP_CSR_TIF ((uint32_t)0x00000200) /!< Tamper Interrupt Flag /
vladvana	0:23d1f73bf130	847
vladvana	0:23d1f73bf130	848	/******************************************************************************/
vladvana	0:23d1f73bf130	849	/* */
vladvana	0:23d1f73bf130	850	/* Reset and Clock Control */
vladvana	0:23d1f73bf130	851	/* */
vladvana	0:23d1f73bf130	852	/******************************************************************************/
vladvana	0:23d1f73bf130	853
vladvana	0:23d1f73bf130	854	/****************** Bit definition for RCC_CR register ******************/
vladvana	0:23d1f73bf130	855	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
vladvana	0:23d1f73bf130	856	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
vladvana	0:23d1f73bf130	857	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
vladvana	0:23d1f73bf130	858	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
vladvana	0:23d1f73bf130	859	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
vladvana	0:23d1f73bf130	860	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
vladvana	0:23d1f73bf130	861	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
vladvana	0:23d1f73bf130	862	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
vladvana	0:23d1f73bf130	863	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
vladvana	0:23d1f73bf130	864	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
vladvana	0:23d1f73bf130	865
vladvana	0:23d1f73bf130	866
vladvana	0:23d1f73bf130	867	/***************** Bit definition for RCC_CFGR register *****************/
vladvana	0:23d1f73bf130	868	/!< SW configuration /
vladvana	0:23d1f73bf130	869	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
vladvana	0:23d1f73bf130	870	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	871	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	872
vladvana	0:23d1f73bf130	873	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
vladvana	0:23d1f73bf130	874	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
vladvana	0:23d1f73bf130	875	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
vladvana	0:23d1f73bf130	876
vladvana	0:23d1f73bf130	877	/!< SWS configuration /
vladvana	0:23d1f73bf130	878	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
vladvana	0:23d1f73bf130	879	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
vladvana	0:23d1f73bf130	880	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
vladvana	0:23d1f73bf130	881
vladvana	0:23d1f73bf130	882	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
vladvana	0:23d1f73bf130	883	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
vladvana	0:23d1f73bf130	884	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
vladvana	0:23d1f73bf130	885
vladvana	0:23d1f73bf130	886	/!< HPRE configuration /
vladvana	0:23d1f73bf130	887	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
vladvana	0:23d1f73bf130	888	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	889	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	890	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
vladvana	0:23d1f73bf130	891	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
vladvana	0:23d1f73bf130	892
vladvana	0:23d1f73bf130	893	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
vladvana	0:23d1f73bf130	894	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
vladvana	0:23d1f73bf130	895	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
vladvana	0:23d1f73bf130	896	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
vladvana	0:23d1f73bf130	897	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
vladvana	0:23d1f73bf130	898	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
vladvana	0:23d1f73bf130	899	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
vladvana	0:23d1f73bf130	900	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
vladvana	0:23d1f73bf130	901	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
vladvana	0:23d1f73bf130	902
vladvana	0:23d1f73bf130	903	/!< PPRE1 configuration /
vladvana	0:23d1f73bf130	904	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
vladvana	0:23d1f73bf130	905	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
vladvana	0:23d1f73bf130	906	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
vladvana	0:23d1f73bf130	907	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
vladvana	0:23d1f73bf130	908
vladvana	0:23d1f73bf130	909	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
vladvana	0:23d1f73bf130	910	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
vladvana	0:23d1f73bf130	911	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
vladvana	0:23d1f73bf130	912	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
vladvana	0:23d1f73bf130	913	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
vladvana	0:23d1f73bf130	914
vladvana	0:23d1f73bf130	915	/!< PPRE2 configuration /
vladvana	0:23d1f73bf130	916	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
vladvana	0:23d1f73bf130	917	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
vladvana	0:23d1f73bf130	918	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
vladvana	0:23d1f73bf130	919	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
vladvana	0:23d1f73bf130	920
vladvana	0:23d1f73bf130	921	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
vladvana	0:23d1f73bf130	922	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
vladvana	0:23d1f73bf130	923	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
vladvana	0:23d1f73bf130	924	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
vladvana	0:23d1f73bf130	925	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
vladvana	0:23d1f73bf130	926
vladvana	0:23d1f73bf130	927	/!< ADCPPRE configuration /
vladvana	0:23d1f73bf130	928	#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /!< ADCPRE[1:0] bits (ADC prescaler) /
vladvana	0:23d1f73bf130	929	#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /!< Bit 0 /
vladvana	0:23d1f73bf130	930	#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /!< Bit 1 /
vladvana	0:23d1f73bf130	931
vladvana	0:23d1f73bf130	932	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
vladvana	0:23d1f73bf130	933	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
vladvana	0:23d1f73bf130	934	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
vladvana	0:23d1f73bf130	935	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
vladvana	0:23d1f73bf130	936
vladvana	0:23d1f73bf130	937	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
vladvana	0:23d1f73bf130	938
vladvana	0:23d1f73bf130	939	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
vladvana	0:23d1f73bf130	940
vladvana	0:23d1f73bf130	941	/!< PLLMUL configuration /
vladvana	0:23d1f73bf130	942	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
vladvana	0:23d1f73bf130	943	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
vladvana	0:23d1f73bf130	944	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
vladvana	0:23d1f73bf130	945	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
vladvana	0:23d1f73bf130	946	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
vladvana	0:23d1f73bf130	947
vladvana	0:23d1f73bf130	948	#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /!< HSE clock not divided for PLL entry /
vladvana	0:23d1f73bf130	949	#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /!< HSE clock divided by 2 for PLL entry /
vladvana	0:23d1f73bf130	950
vladvana	0:23d1f73bf130	951	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
vladvana	0:23d1f73bf130	952	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
vladvana	0:23d1f73bf130	953	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
vladvana	0:23d1f73bf130	954	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
vladvana	0:23d1f73bf130	955	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
vladvana	0:23d1f73bf130	956	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
vladvana	0:23d1f73bf130	957	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
vladvana	0:23d1f73bf130	958	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
vladvana	0:23d1f73bf130	959	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
vladvana	0:23d1f73bf130	960	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
vladvana	0:23d1f73bf130	961	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
vladvana	0:23d1f73bf130	962	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
vladvana	0:23d1f73bf130	963	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
vladvana	0:23d1f73bf130	964	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
vladvana	0:23d1f73bf130	965	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
vladvana	0:23d1f73bf130	966	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB Device prescaler /
vladvana	0:23d1f73bf130	967
vladvana	0:23d1f73bf130	968	/!< MCO configuration /
vladvana	0:23d1f73bf130	969	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
vladvana	0:23d1f73bf130	970	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	971	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	972	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	973
vladvana	0:23d1f73bf130	974	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
vladvana	0:23d1f73bf130	975	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
vladvana	0:23d1f73bf130	976	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
vladvana	0:23d1f73bf130	977	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
vladvana	0:23d1f73bf130	978	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
vladvana	0:23d1f73bf130	979
vladvana	0:23d1f73bf130	980	/!<*************** Bit definition for RCC_CIR register ******************/
vladvana	0:23d1f73bf130	981	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
vladvana	0:23d1f73bf130	982	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
vladvana	0:23d1f73bf130	983	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
vladvana	0:23d1f73bf130	984	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
vladvana	0:23d1f73bf130	985	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
vladvana	0:23d1f73bf130	986	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
vladvana	0:23d1f73bf130	987	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
vladvana	0:23d1f73bf130	988	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
vladvana	0:23d1f73bf130	989	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
vladvana	0:23d1f73bf130	990	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
vladvana	0:23d1f73bf130	991	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
vladvana	0:23d1f73bf130	992	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
vladvana	0:23d1f73bf130	993	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
vladvana	0:23d1f73bf130	994	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
vladvana	0:23d1f73bf130	995	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
vladvana	0:23d1f73bf130	996	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
vladvana	0:23d1f73bf130	997	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
vladvana	0:23d1f73bf130	998
vladvana	0:23d1f73bf130	999
vladvana	0:23d1f73bf130	1000	/*************** Bit definition for RCC_APB2RSTR register ***************/
vladvana	0:23d1f73bf130	1001	#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /!< Alternate Function I/O reset /
vladvana	0:23d1f73bf130	1002	#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /!< I/O port A reset /
vladvana	0:23d1f73bf130	1003	#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /!< I/O port B reset /
vladvana	0:23d1f73bf130	1004	#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /!< I/O port C reset /
vladvana	0:23d1f73bf130	1005	#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /!< I/O port D reset /
vladvana	0:23d1f73bf130	1006	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC 1 interface reset /
vladvana	0:23d1f73bf130	1007
vladvana	0:23d1f73bf130	1008	#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /!< ADC 2 interface reset /
vladvana	0:23d1f73bf130	1009
vladvana	0:23d1f73bf130	1010	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 Timer reset /
vladvana	0:23d1f73bf130	1011	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI 1 reset /
vladvana	0:23d1f73bf130	1012	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
vladvana	0:23d1f73bf130	1013
vladvana	0:23d1f73bf130	1014
vladvana	0:23d1f73bf130	1015	#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /!< I/O port E reset /
vladvana	0:23d1f73bf130	1016
vladvana	0:23d1f73bf130	1017
vladvana	0:23d1f73bf130	1018
vladvana	0:23d1f73bf130	1019
vladvana	0:23d1f73bf130	1020	/*************** Bit definition for RCC_APB1RSTR register ***************/
vladvana	0:23d1f73bf130	1021	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
vladvana	0:23d1f73bf130	1022	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
vladvana	0:23d1f73bf130	1023	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
vladvana	0:23d1f73bf130	1024	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
vladvana	0:23d1f73bf130	1025	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
vladvana	0:23d1f73bf130	1026
vladvana	0:23d1f73bf130	1027	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /!< CAN1 reset /
vladvana	0:23d1f73bf130	1028
vladvana	0:23d1f73bf130	1029	#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /!< Backup interface reset /
vladvana	0:23d1f73bf130	1030	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
vladvana	0:23d1f73bf130	1031
vladvana	0:23d1f73bf130	1032	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
vladvana	0:23d1f73bf130	1033	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
vladvana	0:23d1f73bf130	1034	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
vladvana	0:23d1f73bf130	1035	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
vladvana	0:23d1f73bf130	1036
vladvana	0:23d1f73bf130	1037	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB Device reset /
vladvana	0:23d1f73bf130	1038
vladvana	0:23d1f73bf130	1039
vladvana	0:23d1f73bf130	1040
vladvana	0:23d1f73bf130	1041
vladvana	0:23d1f73bf130	1042
vladvana	0:23d1f73bf130	1043
vladvana	0:23d1f73bf130	1044	/**************** Bit definition for RCC_AHBENR register ****************/
vladvana	0:23d1f73bf130	1045	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
vladvana	0:23d1f73bf130	1046	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
vladvana	0:23d1f73bf130	1047	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
vladvana	0:23d1f73bf130	1048	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
vladvana	0:23d1f73bf130	1049
vladvana	0:23d1f73bf130	1050
vladvana	0:23d1f73bf130	1051
vladvana	0:23d1f73bf130	1052
vladvana	0:23d1f73bf130	1053	/**************** Bit definition for RCC_APB2ENR register ***************/
vladvana	0:23d1f73bf130	1054	#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /!< Alternate Function I/O clock enable /
vladvana	0:23d1f73bf130	1055	#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /!< I/O port A clock enable /
vladvana	0:23d1f73bf130	1056	#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /!< I/O port B clock enable /
vladvana	0:23d1f73bf130	1057	#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /!< I/O port C clock enable /
vladvana	0:23d1f73bf130	1058	#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /!< I/O port D clock enable /
vladvana	0:23d1f73bf130	1059	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC 1 interface clock enable /
vladvana	0:23d1f73bf130	1060
vladvana	0:23d1f73bf130	1061	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /!< ADC 2 interface clock enable /
vladvana	0:23d1f73bf130	1062
vladvana	0:23d1f73bf130	1063	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 Timer clock enable /
vladvana	0:23d1f73bf130	1064	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI 1 clock enable /
vladvana	0:23d1f73bf130	1065	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
vladvana	0:23d1f73bf130	1066
vladvana	0:23d1f73bf130	1067
vladvana	0:23d1f73bf130	1068	#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /!< I/O port E clock enable /
vladvana	0:23d1f73bf130	1069
vladvana	0:23d1f73bf130	1070
vladvana	0:23d1f73bf130	1071
vladvana	0:23d1f73bf130	1072
vladvana	0:23d1f73bf130	1073	/*************** Bit definition for RCC_APB1ENR register ****************/
vladvana	0:23d1f73bf130	1074	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
vladvana	0:23d1f73bf130	1075	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
vladvana	0:23d1f73bf130	1076	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
vladvana	0:23d1f73bf130	1077	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
vladvana	0:23d1f73bf130	1078	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
vladvana	0:23d1f73bf130	1079
vladvana	0:23d1f73bf130	1080	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /!< CAN1 clock enable /
vladvana	0:23d1f73bf130	1081
vladvana	0:23d1f73bf130	1082	#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /!< Backup interface clock enable /
vladvana	0:23d1f73bf130	1083	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
vladvana	0:23d1f73bf130	1084
vladvana	0:23d1f73bf130	1085	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
vladvana	0:23d1f73bf130	1086	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
vladvana	0:23d1f73bf130	1087	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
vladvana	0:23d1f73bf130	1088	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
vladvana	0:23d1f73bf130	1089
vladvana	0:23d1f73bf130	1090	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB Device clock enable /
vladvana	0:23d1f73bf130	1091
vladvana	0:23d1f73bf130	1092
vladvana	0:23d1f73bf130	1093
vladvana	0:23d1f73bf130	1094
vladvana	0:23d1f73bf130	1095
vladvana	0:23d1f73bf130	1096
vladvana	0:23d1f73bf130	1097	/***************** Bit definition for RCC_BDCR register *****************/
vladvana	0:23d1f73bf130	1098	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
vladvana	0:23d1f73bf130	1099	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
vladvana	0:23d1f73bf130	1100	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
vladvana	0:23d1f73bf130	1101
vladvana	0:23d1f73bf130	1102	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
vladvana	0:23d1f73bf130	1103	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
vladvana	0:23d1f73bf130	1104	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
vladvana	0:23d1f73bf130	1105
vladvana	0:23d1f73bf130	1106	/!< RTC congiguration /
vladvana	0:23d1f73bf130	1107	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
vladvana	0:23d1f73bf130	1108	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
vladvana	0:23d1f73bf130	1109	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
vladvana	0:23d1f73bf130	1110	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
vladvana	0:23d1f73bf130	1111
vladvana	0:23d1f73bf130	1112	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
vladvana	0:23d1f73bf130	1113	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
vladvana	0:23d1f73bf130	1114
vladvana	0:23d1f73bf130	1115	/***************** Bit definition for RCC_CSR register ******************/
vladvana	0:23d1f73bf130	1116	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
vladvana	0:23d1f73bf130	1117	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
vladvana	0:23d1f73bf130	1118	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
vladvana	0:23d1f73bf130	1119	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
vladvana	0:23d1f73bf130	1120	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
vladvana	0:23d1f73bf130	1121	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
vladvana	0:23d1f73bf130	1122	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
vladvana	0:23d1f73bf130	1123	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
vladvana	0:23d1f73bf130	1124	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
vladvana	0:23d1f73bf130	1125
vladvana	0:23d1f73bf130	1126
vladvana	0:23d1f73bf130	1127
vladvana	0:23d1f73bf130	1128	/******************************************************************************/
vladvana	0:23d1f73bf130	1129	/* */
vladvana	0:23d1f73bf130	1130	/* General Purpose and Alternate Function I/O */
vladvana	0:23d1f73bf130	1131	/* */
vladvana	0:23d1f73bf130	1132	/******************************************************************************/
vladvana	0:23d1f73bf130	1133
vladvana	0:23d1f73bf130	1134	/***************** Bit definition for GPIO_CRL register *****************/
vladvana	0:23d1f73bf130	1135	#define GPIO_CRL_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
vladvana	0:23d1f73bf130	1136
vladvana	0:23d1f73bf130	1137	#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
vladvana	0:23d1f73bf130	1138	#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	1139	#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	1140
vladvana	0:23d1f73bf130	1141	#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
vladvana	0:23d1f73bf130	1142	#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	1143	#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	1144
vladvana	0:23d1f73bf130	1145	#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
vladvana	0:23d1f73bf130	1146	#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /!< Bit 0 /
vladvana	0:23d1f73bf130	1147	#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /!< Bit 1 /
vladvana	0:23d1f73bf130	1148
vladvana	0:23d1f73bf130	1149	#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
vladvana	0:23d1f73bf130	1150	#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1151	#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1152
vladvana	0:23d1f73bf130	1153	#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
vladvana	0:23d1f73bf130	1154	#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1155	#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1156
vladvana	0:23d1f73bf130	1157	#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
vladvana	0:23d1f73bf130	1158	#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1159	#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1160
vladvana	0:23d1f73bf130	1161	#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
vladvana	0:23d1f73bf130	1162	#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1163	#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1164
vladvana	0:23d1f73bf130	1165	#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
vladvana	0:23d1f73bf130	1166	#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1167	#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1168
vladvana	0:23d1f73bf130	1169	#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
vladvana	0:23d1f73bf130	1170
vladvana	0:23d1f73bf130	1171	#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
vladvana	0:23d1f73bf130	1172	#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /!< Bit 0 /
vladvana	0:23d1f73bf130	1173	#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /!< Bit 1 /
vladvana	0:23d1f73bf130	1174
vladvana	0:23d1f73bf130	1175	#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
vladvana	0:23d1f73bf130	1176	#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /!< Bit 0 /
vladvana	0:23d1f73bf130	1177	#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /!< Bit 1 /
vladvana	0:23d1f73bf130	1178
vladvana	0:23d1f73bf130	1179	#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
vladvana	0:23d1f73bf130	1180	#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	1181	#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	1182
vladvana	0:23d1f73bf130	1183	#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
vladvana	0:23d1f73bf130	1184	#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1185	#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1186
vladvana	0:23d1f73bf130	1187	#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
vladvana	0:23d1f73bf130	1188	#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1189	#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1190
vladvana	0:23d1f73bf130	1191	#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
vladvana	0:23d1f73bf130	1192	#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1193	#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1194
vladvana	0:23d1f73bf130	1195	#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
vladvana	0:23d1f73bf130	1196	#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1197	#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1198
vladvana	0:23d1f73bf130	1199	#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
vladvana	0:23d1f73bf130	1200	#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1201	#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1202
vladvana	0:23d1f73bf130	1203	/***************** Bit definition for GPIO_CRH register *****************/
vladvana	0:23d1f73bf130	1204	#define GPIO_CRH_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
vladvana	0:23d1f73bf130	1205
vladvana	0:23d1f73bf130	1206	#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
vladvana	0:23d1f73bf130	1207	#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	1208	#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	1209
vladvana	0:23d1f73bf130	1210	#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
vladvana	0:23d1f73bf130	1211	#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	1212	#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	1213
vladvana	0:23d1f73bf130	1214	#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
vladvana	0:23d1f73bf130	1215	#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /!< Bit 0 /
vladvana	0:23d1f73bf130	1216	#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /!< Bit 1 /
vladvana	0:23d1f73bf130	1217
vladvana	0:23d1f73bf130	1218	#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
vladvana	0:23d1f73bf130	1219	#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1220	#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1221
vladvana	0:23d1f73bf130	1222	#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
vladvana	0:23d1f73bf130	1223	#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1224	#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1225
vladvana	0:23d1f73bf130	1226	#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
vladvana	0:23d1f73bf130	1227	#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1228	#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1229
vladvana	0:23d1f73bf130	1230	#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
vladvana	0:23d1f73bf130	1231	#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1232	#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1233
vladvana	0:23d1f73bf130	1234	#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
vladvana	0:23d1f73bf130	1235	#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1236	#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1237
vladvana	0:23d1f73bf130	1238	#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
vladvana	0:23d1f73bf130	1239
vladvana	0:23d1f73bf130	1240	#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
vladvana	0:23d1f73bf130	1241	#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /!< Bit 0 /
vladvana	0:23d1f73bf130	1242	#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /!< Bit 1 /
vladvana	0:23d1f73bf130	1243
vladvana	0:23d1f73bf130	1244	#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
vladvana	0:23d1f73bf130	1245	#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /!< Bit 0 /
vladvana	0:23d1f73bf130	1246	#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /!< Bit 1 /
vladvana	0:23d1f73bf130	1247
vladvana	0:23d1f73bf130	1248	#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
vladvana	0:23d1f73bf130	1249	#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	1250	#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	1251
vladvana	0:23d1f73bf130	1252	#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
vladvana	0:23d1f73bf130	1253	#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1254	#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1255
vladvana	0:23d1f73bf130	1256	#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
vladvana	0:23d1f73bf130	1257	#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1258	#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1259
vladvana	0:23d1f73bf130	1260	#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
vladvana	0:23d1f73bf130	1261	#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1262	#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1263
vladvana	0:23d1f73bf130	1264	#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
vladvana	0:23d1f73bf130	1265	#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1266	#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1267
vladvana	0:23d1f73bf130	1268	#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
vladvana	0:23d1f73bf130	1269	#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1270	#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1271
vladvana	0:23d1f73bf130	1272	/!<*************** Bit definition for GPIO_IDR register *****************/
vladvana	0:23d1f73bf130	1273	#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /!< Port input data, bit 0 /
vladvana	0:23d1f73bf130	1274	#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /!< Port input data, bit 1 /
vladvana	0:23d1f73bf130	1275	#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /!< Port input data, bit 2 /
vladvana	0:23d1f73bf130	1276	#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /!< Port input data, bit 3 /
vladvana	0:23d1f73bf130	1277	#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /!< Port input data, bit 4 /
vladvana	0:23d1f73bf130	1278	#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /!< Port input data, bit 5 /
vladvana	0:23d1f73bf130	1279	#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /!< Port input data, bit 6 /
vladvana	0:23d1f73bf130	1280	#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /!< Port input data, bit 7 /
vladvana	0:23d1f73bf130	1281	#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /!< Port input data, bit 8 /
vladvana	0:23d1f73bf130	1282	#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /!< Port input data, bit 9 /
vladvana	0:23d1f73bf130	1283	#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /!< Port input data, bit 10 /
vladvana	0:23d1f73bf130	1284	#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /!< Port input data, bit 11 /
vladvana	0:23d1f73bf130	1285	#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /!< Port input data, bit 12 /
vladvana	0:23d1f73bf130	1286	#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /!< Port input data, bit 13 /
vladvana	0:23d1f73bf130	1287	#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /!< Port input data, bit 14 /
vladvana	0:23d1f73bf130	1288	#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /!< Port input data, bit 15 /
vladvana	0:23d1f73bf130	1289
vladvana	0:23d1f73bf130	1290	/***************** Bit definition for GPIO_ODR register *****************/
vladvana	0:23d1f73bf130	1291	#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /!< Port output data, bit 0 /
vladvana	0:23d1f73bf130	1292	#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /!< Port output data, bit 1 /
vladvana	0:23d1f73bf130	1293	#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /!< Port output data, bit 2 /
vladvana	0:23d1f73bf130	1294	#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /!< Port output data, bit 3 /
vladvana	0:23d1f73bf130	1295	#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /!< Port output data, bit 4 /
vladvana	0:23d1f73bf130	1296	#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /!< Port output data, bit 5 /
vladvana	0:23d1f73bf130	1297	#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /!< Port output data, bit 6 /
vladvana	0:23d1f73bf130	1298	#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /!< Port output data, bit 7 /
vladvana	0:23d1f73bf130	1299	#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /!< Port output data, bit 8 /
vladvana	0:23d1f73bf130	1300	#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /!< Port output data, bit 9 /
vladvana	0:23d1f73bf130	1301	#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /!< Port output data, bit 10 /
vladvana	0:23d1f73bf130	1302	#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /!< Port output data, bit 11 /
vladvana	0:23d1f73bf130	1303	#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /!< Port output data, bit 12 /
vladvana	0:23d1f73bf130	1304	#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /!< Port output data, bit 13 /
vladvana	0:23d1f73bf130	1305	#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /!< Port output data, bit 14 /
vladvana	0:23d1f73bf130	1306	#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /!< Port output data, bit 15 /
vladvana	0:23d1f73bf130	1307
vladvana	0:23d1f73bf130	1308	/**************** Bit definition for GPIO_BSRR register *****************/
vladvana	0:23d1f73bf130	1309	#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /!< Port x Set bit 0 /
vladvana	0:23d1f73bf130	1310	#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /!< Port x Set bit 1 /
vladvana	0:23d1f73bf130	1311	#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /!< Port x Set bit 2 /
vladvana	0:23d1f73bf130	1312	#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /!< Port x Set bit 3 /
vladvana	0:23d1f73bf130	1313	#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /!< Port x Set bit 4 /
vladvana	0:23d1f73bf130	1314	#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /!< Port x Set bit 5 /
vladvana	0:23d1f73bf130	1315	#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /!< Port x Set bit 6 /
vladvana	0:23d1f73bf130	1316	#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /!< Port x Set bit 7 /
vladvana	0:23d1f73bf130	1317	#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /!< Port x Set bit 8 /
vladvana	0:23d1f73bf130	1318	#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /!< Port x Set bit 9 /
vladvana	0:23d1f73bf130	1319	#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /!< Port x Set bit 10 /
vladvana	0:23d1f73bf130	1320	#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /!< Port x Set bit 11 /
vladvana	0:23d1f73bf130	1321	#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /!< Port x Set bit 12 /
vladvana	0:23d1f73bf130	1322	#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /!< Port x Set bit 13 /
vladvana	0:23d1f73bf130	1323	#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /!< Port x Set bit 14 /
vladvana	0:23d1f73bf130	1324	#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /!< Port x Set bit 15 /
vladvana	0:23d1f73bf130	1325
vladvana	0:23d1f73bf130	1326	#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /!< Port x Reset bit 0 /
vladvana	0:23d1f73bf130	1327	#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /!< Port x Reset bit 1 /
vladvana	0:23d1f73bf130	1328	#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /!< Port x Reset bit 2 /
vladvana	0:23d1f73bf130	1329	#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /!< Port x Reset bit 3 /
vladvana	0:23d1f73bf130	1330	#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /!< Port x Reset bit 4 /
vladvana	0:23d1f73bf130	1331	#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /!< Port x Reset bit 5 /
vladvana	0:23d1f73bf130	1332	#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /!< Port x Reset bit 6 /
vladvana	0:23d1f73bf130	1333	#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /!< Port x Reset bit 7 /
vladvana	0:23d1f73bf130	1334	#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /!< Port x Reset bit 8 /
vladvana	0:23d1f73bf130	1335	#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /!< Port x Reset bit 9 /
vladvana	0:23d1f73bf130	1336	#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /!< Port x Reset bit 10 /
vladvana	0:23d1f73bf130	1337	#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /!< Port x Reset bit 11 /
vladvana	0:23d1f73bf130	1338	#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /!< Port x Reset bit 12 /
vladvana	0:23d1f73bf130	1339	#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /!< Port x Reset bit 13 /
vladvana	0:23d1f73bf130	1340	#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /!< Port x Reset bit 14 /
vladvana	0:23d1f73bf130	1341	#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /!< Port x Reset bit 15 /
vladvana	0:23d1f73bf130	1342
vladvana	0:23d1f73bf130	1343	/***************** Bit definition for GPIO_BRR register *****************/
vladvana	0:23d1f73bf130	1344	#define GPIO_BRR_BR0 ((uint32_t)0x0001) /!< Port x Reset bit 0 /
vladvana	0:23d1f73bf130	1345	#define GPIO_BRR_BR1 ((uint32_t)0x0002) /!< Port x Reset bit 1 /
vladvana	0:23d1f73bf130	1346	#define GPIO_BRR_BR2 ((uint32_t)0x0004) /!< Port x Reset bit 2 /
vladvana	0:23d1f73bf130	1347	#define GPIO_BRR_BR3 ((uint32_t)0x0008) /!< Port x Reset bit 3 /
vladvana	0:23d1f73bf130	1348	#define GPIO_BRR_BR4 ((uint32_t)0x0010) /!< Port x Reset bit 4 /
vladvana	0:23d1f73bf130	1349	#define GPIO_BRR_BR5 ((uint32_t)0x0020) /!< Port x Reset bit 5 /
vladvana	0:23d1f73bf130	1350	#define GPIO_BRR_BR6 ((uint32_t)0x0040) /!< Port x Reset bit 6 /
vladvana	0:23d1f73bf130	1351	#define GPIO_BRR_BR7 ((uint32_t)0x0080) /!< Port x Reset bit 7 /
vladvana	0:23d1f73bf130	1352	#define GPIO_BRR_BR8 ((uint32_t)0x0100) /!< Port x Reset bit 8 /
vladvana	0:23d1f73bf130	1353	#define GPIO_BRR_BR9 ((uint32_t)0x0200) /!< Port x Reset bit 9 /
vladvana	0:23d1f73bf130	1354	#define GPIO_BRR_BR10 ((uint32_t)0x0400) /!< Port x Reset bit 10 /
vladvana	0:23d1f73bf130	1355	#define GPIO_BRR_BR11 ((uint32_t)0x0800) /!< Port x Reset bit 11 /
vladvana	0:23d1f73bf130	1356	#define GPIO_BRR_BR12 ((uint32_t)0x1000) /!< Port x Reset bit 12 /
vladvana	0:23d1f73bf130	1357	#define GPIO_BRR_BR13 ((uint32_t)0x2000) /!< Port x Reset bit 13 /
vladvana	0:23d1f73bf130	1358	#define GPIO_BRR_BR14 ((uint32_t)0x4000) /!< Port x Reset bit 14 /
vladvana	0:23d1f73bf130	1359	#define GPIO_BRR_BR15 ((uint32_t)0x8000) /!< Port x Reset bit 15 /
vladvana	0:23d1f73bf130	1360
vladvana	0:23d1f73bf130	1361	/**************** Bit definition for GPIO_LCKR register *****************/
vladvana	0:23d1f73bf130	1362	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /!< Port x Lock bit 0 /
vladvana	0:23d1f73bf130	1363	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /!< Port x Lock bit 1 /
vladvana	0:23d1f73bf130	1364	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /!< Port x Lock bit 2 /
vladvana	0:23d1f73bf130	1365	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /!< Port x Lock bit 3 /
vladvana	0:23d1f73bf130	1366	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /!< Port x Lock bit 4 /
vladvana	0:23d1f73bf130	1367	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /!< Port x Lock bit 5 /
vladvana	0:23d1f73bf130	1368	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /!< Port x Lock bit 6 /
vladvana	0:23d1f73bf130	1369	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /!< Port x Lock bit 7 /
vladvana	0:23d1f73bf130	1370	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /!< Port x Lock bit 8 /
vladvana	0:23d1f73bf130	1371	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /!< Port x Lock bit 9 /
vladvana	0:23d1f73bf130	1372	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /!< Port x Lock bit 10 /
vladvana	0:23d1f73bf130	1373	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /!< Port x Lock bit 11 /
vladvana	0:23d1f73bf130	1374	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /!< Port x Lock bit 12 /
vladvana	0:23d1f73bf130	1375	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /!< Port x Lock bit 13 /
vladvana	0:23d1f73bf130	1376	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /!< Port x Lock bit 14 /
vladvana	0:23d1f73bf130	1377	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /!< Port x Lock bit 15 /
vladvana	0:23d1f73bf130	1378	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /!< Lock key /
vladvana	0:23d1f73bf130	1379
vladvana	0:23d1f73bf130	1380	/----------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	1381
vladvana	0:23d1f73bf130	1382	/**************** Bit definition for AFIO_EVCR register *****************/
vladvana	0:23d1f73bf130	1383	#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /!< PIN[3:0] bits (Pin selection) /
vladvana	0:23d1f73bf130	1384	#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	1385	#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	1386	#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	1387	#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	1388
vladvana	0:23d1f73bf130	1389	/!< PIN configuration /
vladvana	0:23d1f73bf130	1390	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
vladvana	0:23d1f73bf130	1391	#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /!< Pin 1 selected /
vladvana	0:23d1f73bf130	1392	#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /!< Pin 2 selected /
vladvana	0:23d1f73bf130	1393	#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /!< Pin 3 selected /
vladvana	0:23d1f73bf130	1394	#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /!< Pin 4 selected /
vladvana	0:23d1f73bf130	1395	#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /!< Pin 5 selected /
vladvana	0:23d1f73bf130	1396	#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /!< Pin 6 selected /
vladvana	0:23d1f73bf130	1397	#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /!< Pin 7 selected /
vladvana	0:23d1f73bf130	1398	#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /!< Pin 8 selected /
vladvana	0:23d1f73bf130	1399	#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /!< Pin 9 selected /
vladvana	0:23d1f73bf130	1400	#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /!< Pin 10 selected /
vladvana	0:23d1f73bf130	1401	#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /!< Pin 11 selected /
vladvana	0:23d1f73bf130	1402	#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /!< Pin 12 selected /
vladvana	0:23d1f73bf130	1403	#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /!< Pin 13 selected /
vladvana	0:23d1f73bf130	1404	#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /!< Pin 14 selected /
vladvana	0:23d1f73bf130	1405	#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /!< Pin 15 selected /
vladvana	0:23d1f73bf130	1406
vladvana	0:23d1f73bf130	1407	#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /!< PORT[2:0] bits (Port selection) /
vladvana	0:23d1f73bf130	1408	#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	1409	#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	1410	#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /!< Bit 2 /
vladvana	0:23d1f73bf130	1411
vladvana	0:23d1f73bf130	1412	/!< PORT configuration /
vladvana	0:23d1f73bf130	1413	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
vladvana	0:23d1f73bf130	1414	#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /!< Port B selected /
vladvana	0:23d1f73bf130	1415	#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /!< Port C selected /
vladvana	0:23d1f73bf130	1416	#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /!< Port D selected /
vladvana	0:23d1f73bf130	1417	#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /!< Port E selected /
vladvana	0:23d1f73bf130	1418
vladvana	0:23d1f73bf130	1419	#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /!< Event Output Enable /
vladvana	0:23d1f73bf130	1420
vladvana	0:23d1f73bf130	1421	/**************** Bit definition for AFIO_MAPR register *****************/
vladvana	0:23d1f73bf130	1422	#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /!< SPI1 remapping /
vladvana	0:23d1f73bf130	1423	#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /!< I2C1 remapping /
vladvana	0:23d1f73bf130	1424	#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /!< USART1 remapping /
vladvana	0:23d1f73bf130	1425	#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /!< USART2 remapping /
vladvana	0:23d1f73bf130	1426
vladvana	0:23d1f73bf130	1427	#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /!< USART3_REMAP[1:0] bits (USART3 remapping) /
vladvana	0:23d1f73bf130	1428	#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	1429	#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	1430
vladvana	0:23d1f73bf130	1431	/* USART3_REMAP configuration */
vladvana	0:23d1f73bf130	1432	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
vladvana	0:23d1f73bf130	1433	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
vladvana	0:23d1f73bf130	1434	#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
vladvana	0:23d1f73bf130	1435
vladvana	0:23d1f73bf130	1436	#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
vladvana	0:23d1f73bf130	1437	#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /!< Bit 0 /
vladvana	0:23d1f73bf130	1438	#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /!< Bit 1 /
vladvana	0:23d1f73bf130	1439
vladvana	0:23d1f73bf130	1440	/!< TIM1_REMAP configuration /
vladvana	0:23d1f73bf130	1441	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
vladvana	0:23d1f73bf130	1442	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
vladvana	0:23d1f73bf130	1443	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
vladvana	0:23d1f73bf130	1444
vladvana	0:23d1f73bf130	1445	#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
vladvana	0:23d1f73bf130	1446	#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /!< Bit 0 /
vladvana	0:23d1f73bf130	1447	#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /!< Bit 1 /
vladvana	0:23d1f73bf130	1448
vladvana	0:23d1f73bf130	1449	/!< TIM2_REMAP configuration /
vladvana	0:23d1f73bf130	1450	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
vladvana	0:23d1f73bf130	1451	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
vladvana	0:23d1f73bf130	1452	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
vladvana	0:23d1f73bf130	1453	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
vladvana	0:23d1f73bf130	1454
vladvana	0:23d1f73bf130	1455	#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
vladvana	0:23d1f73bf130	1456	#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	1457	#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	1458
vladvana	0:23d1f73bf130	1459	/!< TIM3_REMAP configuration /
vladvana	0:23d1f73bf130	1460	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
vladvana	0:23d1f73bf130	1461	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
vladvana	0:23d1f73bf130	1462	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
vladvana	0:23d1f73bf130	1463
vladvana	0:23d1f73bf130	1464	#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /!< TIM4_REMAP bit (TIM4 remapping) /
vladvana	0:23d1f73bf130	1465
vladvana	0:23d1f73bf130	1466	#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) /
vladvana	0:23d1f73bf130	1467	#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1468	#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1469
vladvana	0:23d1f73bf130	1470	/!< CAN_REMAP configuration /
vladvana	0:23d1f73bf130	1471	#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /!< CANRX mapped to PA11, CANTX mapped to PA12 /
vladvana	0:23d1f73bf130	1472	#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /!< CANRX mapped to PB8, CANTX mapped to PB9 /
vladvana	0:23d1f73bf130	1473	#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /!< CANRX mapped to PD0, CANTX mapped to PD1 /
vladvana	0:23d1f73bf130	1474
vladvana	0:23d1f73bf130	1475	#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
vladvana	0:23d1f73bf130	1476
vladvana	0:23d1f73bf130	1477	/!< SWJ_CFG configuration /
vladvana	0:23d1f73bf130	1478	#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
vladvana	0:23d1f73bf130	1479	#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	1480	#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	1481	#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	1482
vladvana	0:23d1f73bf130	1483	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
vladvana	0:23d1f73bf130	1484	#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
vladvana	0:23d1f73bf130	1485	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /!< JTAG-DP Disabled and SW-DP Enabled /
vladvana	0:23d1f73bf130	1486	#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /!< JTAG-DP Disabled and SW-DP Disabled /
vladvana	0:23d1f73bf130	1487
vladvana	0:23d1f73bf130	1488
vladvana	0:23d1f73bf130	1489	/*************** Bit definition for AFIO_EXTICR1 register ***************/
vladvana	0:23d1f73bf130	1490	#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
vladvana	0:23d1f73bf130	1491	#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
vladvana	0:23d1f73bf130	1492	#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
vladvana	0:23d1f73bf130	1493	#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
vladvana	0:23d1f73bf130	1494
vladvana	0:23d1f73bf130	1495	/!< EXTI0 configuration /
vladvana	0:23d1f73bf130	1496	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
vladvana	0:23d1f73bf130	1497	#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
vladvana	0:23d1f73bf130	1498	#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
vladvana	0:23d1f73bf130	1499	#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
vladvana	0:23d1f73bf130	1500	#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
vladvana	0:23d1f73bf130	1501	#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
vladvana	0:23d1f73bf130	1502	#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!< PG[0] pin /
vladvana	0:23d1f73bf130	1503
vladvana	0:23d1f73bf130	1504	/!< EXTI1 configuration /
vladvana	0:23d1f73bf130	1505	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
vladvana	0:23d1f73bf130	1506	#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
vladvana	0:23d1f73bf130	1507	#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
vladvana	0:23d1f73bf130	1508	#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
vladvana	0:23d1f73bf130	1509	#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
vladvana	0:23d1f73bf130	1510	#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
vladvana	0:23d1f73bf130	1511	#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!< PG[1] pin /
vladvana	0:23d1f73bf130	1512
vladvana	0:23d1f73bf130	1513	/!< EXTI2 configuration /
vladvana	0:23d1f73bf130	1514	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
vladvana	0:23d1f73bf130	1515	#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
vladvana	0:23d1f73bf130	1516	#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
vladvana	0:23d1f73bf130	1517	#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
vladvana	0:23d1f73bf130	1518	#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
vladvana	0:23d1f73bf130	1519	#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
vladvana	0:23d1f73bf130	1520	#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!< PG[2] pin /
vladvana	0:23d1f73bf130	1521
vladvana	0:23d1f73bf130	1522	/!< EXTI3 configuration /
vladvana	0:23d1f73bf130	1523	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
vladvana	0:23d1f73bf130	1524	#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
vladvana	0:23d1f73bf130	1525	#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
vladvana	0:23d1f73bf130	1526	#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
vladvana	0:23d1f73bf130	1527	#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
vladvana	0:23d1f73bf130	1528	#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
vladvana	0:23d1f73bf130	1529	#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!< PG[3] pin /
vladvana	0:23d1f73bf130	1530
vladvana	0:23d1f73bf130	1531	/*************** Bit definition for AFIO_EXTICR2 register ***************/
vladvana	0:23d1f73bf130	1532	#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
vladvana	0:23d1f73bf130	1533	#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
vladvana	0:23d1f73bf130	1534	#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
vladvana	0:23d1f73bf130	1535	#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
vladvana	0:23d1f73bf130	1536
vladvana	0:23d1f73bf130	1537	/!< EXTI4 configuration /
vladvana	0:23d1f73bf130	1538	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
vladvana	0:23d1f73bf130	1539	#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
vladvana	0:23d1f73bf130	1540	#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
vladvana	0:23d1f73bf130	1541	#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
vladvana	0:23d1f73bf130	1542	#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
vladvana	0:23d1f73bf130	1543	#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
vladvana	0:23d1f73bf130	1544	#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!< PG[4] pin /
vladvana	0:23d1f73bf130	1545
vladvana	0:23d1f73bf130	1546	/* EXTI5 configuration */
vladvana	0:23d1f73bf130	1547	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
vladvana	0:23d1f73bf130	1548	#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
vladvana	0:23d1f73bf130	1549	#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
vladvana	0:23d1f73bf130	1550	#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
vladvana	0:23d1f73bf130	1551	#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
vladvana	0:23d1f73bf130	1552	#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
vladvana	0:23d1f73bf130	1553	#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!< PG[5] pin /
vladvana	0:23d1f73bf130	1554
vladvana	0:23d1f73bf130	1555	/!< EXTI6 configuration /
vladvana	0:23d1f73bf130	1556	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
vladvana	0:23d1f73bf130	1557	#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
vladvana	0:23d1f73bf130	1558	#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
vladvana	0:23d1f73bf130	1559	#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
vladvana	0:23d1f73bf130	1560	#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
vladvana	0:23d1f73bf130	1561	#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
vladvana	0:23d1f73bf130	1562	#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!< PG[6] pin /
vladvana	0:23d1f73bf130	1563
vladvana	0:23d1f73bf130	1564	/!< EXTI7 configuration /
vladvana	0:23d1f73bf130	1565	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
vladvana	0:23d1f73bf130	1566	#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
vladvana	0:23d1f73bf130	1567	#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
vladvana	0:23d1f73bf130	1568	#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
vladvana	0:23d1f73bf130	1569	#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
vladvana	0:23d1f73bf130	1570	#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
vladvana	0:23d1f73bf130	1571	#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!< PG[7] pin /
vladvana	0:23d1f73bf130	1572
vladvana	0:23d1f73bf130	1573	/*************** Bit definition for AFIO_EXTICR3 register ***************/
vladvana	0:23d1f73bf130	1574	#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
vladvana	0:23d1f73bf130	1575	#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
vladvana	0:23d1f73bf130	1576	#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
vladvana	0:23d1f73bf130	1577	#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
vladvana	0:23d1f73bf130	1578
vladvana	0:23d1f73bf130	1579	/!< EXTI8 configuration /
vladvana	0:23d1f73bf130	1580	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
vladvana	0:23d1f73bf130	1581	#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
vladvana	0:23d1f73bf130	1582	#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
vladvana	0:23d1f73bf130	1583	#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
vladvana	0:23d1f73bf130	1584	#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
vladvana	0:23d1f73bf130	1585	#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
vladvana	0:23d1f73bf130	1586	#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!< PG[8] pin /
vladvana	0:23d1f73bf130	1587
vladvana	0:23d1f73bf130	1588	/!< EXTI9 configuration /
vladvana	0:23d1f73bf130	1589	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
vladvana	0:23d1f73bf130	1590	#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
vladvana	0:23d1f73bf130	1591	#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
vladvana	0:23d1f73bf130	1592	#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
vladvana	0:23d1f73bf130	1593	#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
vladvana	0:23d1f73bf130	1594	#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
vladvana	0:23d1f73bf130	1595	#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!< PG[9] pin /
vladvana	0:23d1f73bf130	1596
vladvana	0:23d1f73bf130	1597	/!< EXTI10 configuration /
vladvana	0:23d1f73bf130	1598	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
vladvana	0:23d1f73bf130	1599	#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
vladvana	0:23d1f73bf130	1600	#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
vladvana	0:23d1f73bf130	1601	#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
vladvana	0:23d1f73bf130	1602	#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
vladvana	0:23d1f73bf130	1603	#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
vladvana	0:23d1f73bf130	1604	#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!< PG[10] pin /
vladvana	0:23d1f73bf130	1605
vladvana	0:23d1f73bf130	1606	/!< EXTI11 configuration /
vladvana	0:23d1f73bf130	1607	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
vladvana	0:23d1f73bf130	1608	#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
vladvana	0:23d1f73bf130	1609	#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
vladvana	0:23d1f73bf130	1610	#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
vladvana	0:23d1f73bf130	1611	#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
vladvana	0:23d1f73bf130	1612	#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
vladvana	0:23d1f73bf130	1613	#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!< PG[11] pin /
vladvana	0:23d1f73bf130	1614
vladvana	0:23d1f73bf130	1615	/*************** Bit definition for AFIO_EXTICR4 register ***************/
vladvana	0:23d1f73bf130	1616	#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
vladvana	0:23d1f73bf130	1617	#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
vladvana	0:23d1f73bf130	1618	#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
vladvana	0:23d1f73bf130	1619	#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
vladvana	0:23d1f73bf130	1620
vladvana	0:23d1f73bf130	1621	/* EXTI12 configuration */
vladvana	0:23d1f73bf130	1622	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
vladvana	0:23d1f73bf130	1623	#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
vladvana	0:23d1f73bf130	1624	#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
vladvana	0:23d1f73bf130	1625	#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
vladvana	0:23d1f73bf130	1626	#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
vladvana	0:23d1f73bf130	1627	#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
vladvana	0:23d1f73bf130	1628	#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!< PG[12] pin /
vladvana	0:23d1f73bf130	1629
vladvana	0:23d1f73bf130	1630	/* EXTI13 configuration */
vladvana	0:23d1f73bf130	1631	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
vladvana	0:23d1f73bf130	1632	#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
vladvana	0:23d1f73bf130	1633	#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
vladvana	0:23d1f73bf130	1634	#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
vladvana	0:23d1f73bf130	1635	#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
vladvana	0:23d1f73bf130	1636	#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
vladvana	0:23d1f73bf130	1637	#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!< PG[13] pin /
vladvana	0:23d1f73bf130	1638
vladvana	0:23d1f73bf130	1639	/!< EXTI14 configuration /
vladvana	0:23d1f73bf130	1640	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
vladvana	0:23d1f73bf130	1641	#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
vladvana	0:23d1f73bf130	1642	#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
vladvana	0:23d1f73bf130	1643	#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
vladvana	0:23d1f73bf130	1644	#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
vladvana	0:23d1f73bf130	1645	#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
vladvana	0:23d1f73bf130	1646	#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!< PG[14] pin /
vladvana	0:23d1f73bf130	1647
vladvana	0:23d1f73bf130	1648	/!< EXTI15 configuration /
vladvana	0:23d1f73bf130	1649	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
vladvana	0:23d1f73bf130	1650	#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
vladvana	0:23d1f73bf130	1651	#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
vladvana	0:23d1f73bf130	1652	#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
vladvana	0:23d1f73bf130	1653	#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
vladvana	0:23d1f73bf130	1654	#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
vladvana	0:23d1f73bf130	1655	#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!< PG[15] pin /
vladvana	0:23d1f73bf130	1656
vladvana	0:23d1f73bf130	1657	/**************** Bit definition for AFIO_MAPR2 register ****************/
vladvana	0:23d1f73bf130	1658
vladvana	0:23d1f73bf130	1659
vladvana	0:23d1f73bf130	1660
vladvana	0:23d1f73bf130	1661	/******************************************************************************/
vladvana	0:23d1f73bf130	1662	/* */
vladvana	0:23d1f73bf130	1663	/* SystemTick */
vladvana	0:23d1f73bf130	1664	/* */
vladvana	0:23d1f73bf130	1665	/******************************************************************************/
vladvana	0:23d1f73bf130	1666
vladvana	0:23d1f73bf130	1667	/*************** Bit definition for SysTick_CTRL register ***************/
vladvana	0:23d1f73bf130	1668	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
vladvana	0:23d1f73bf130	1669	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
vladvana	0:23d1f73bf130	1670	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
vladvana	0:23d1f73bf130	1671	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
vladvana	0:23d1f73bf130	1672
vladvana	0:23d1f73bf130	1673	/*************** Bit definition for SysTick_LOAD register ***************/
vladvana	0:23d1f73bf130	1674	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
vladvana	0:23d1f73bf130	1675
vladvana	0:23d1f73bf130	1676	/*************** Bit definition for SysTick_VAL register ****************/
vladvana	0:23d1f73bf130	1677	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
vladvana	0:23d1f73bf130	1678
vladvana	0:23d1f73bf130	1679	/*************** Bit definition for SysTick_CALIB register **************/
vladvana	0:23d1f73bf130	1680	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
vladvana	0:23d1f73bf130	1681	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
vladvana	0:23d1f73bf130	1682	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
vladvana	0:23d1f73bf130	1683
vladvana	0:23d1f73bf130	1684	/******************************************************************************/
vladvana	0:23d1f73bf130	1685	/* */
vladvana	0:23d1f73bf130	1686	/* Nested Vectored Interrupt Controller */
vladvana	0:23d1f73bf130	1687	/* */
vladvana	0:23d1f73bf130	1688	/******************************************************************************/
vladvana	0:23d1f73bf130	1689
vladvana	0:23d1f73bf130	1690	/**************** Bit definition for NVIC_ISER register *****************/
vladvana	0:23d1f73bf130	1691	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
vladvana	0:23d1f73bf130	1692	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
vladvana	0:23d1f73bf130	1693	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
vladvana	0:23d1f73bf130	1694	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
vladvana	0:23d1f73bf130	1695	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
vladvana	0:23d1f73bf130	1696	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
vladvana	0:23d1f73bf130	1697	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
vladvana	0:23d1f73bf130	1698	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
vladvana	0:23d1f73bf130	1699	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
vladvana	0:23d1f73bf130	1700	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
vladvana	0:23d1f73bf130	1701	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
vladvana	0:23d1f73bf130	1702	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
vladvana	0:23d1f73bf130	1703	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
vladvana	0:23d1f73bf130	1704	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
vladvana	0:23d1f73bf130	1705	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
vladvana	0:23d1f73bf130	1706	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
vladvana	0:23d1f73bf130	1707	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
vladvana	0:23d1f73bf130	1708	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
vladvana	0:23d1f73bf130	1709	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
vladvana	0:23d1f73bf130	1710	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
vladvana	0:23d1f73bf130	1711	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
vladvana	0:23d1f73bf130	1712	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
vladvana	0:23d1f73bf130	1713	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
vladvana	0:23d1f73bf130	1714	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
vladvana	0:23d1f73bf130	1715	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
vladvana	0:23d1f73bf130	1716	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
vladvana	0:23d1f73bf130	1717	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
vladvana	0:23d1f73bf130	1718	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
vladvana	0:23d1f73bf130	1719	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
vladvana	0:23d1f73bf130	1720	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
vladvana	0:23d1f73bf130	1721	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
vladvana	0:23d1f73bf130	1722	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
vladvana	0:23d1f73bf130	1723	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
vladvana	0:23d1f73bf130	1724
vladvana	0:23d1f73bf130	1725	/**************** Bit definition for NVIC_ICER register *****************/
vladvana	0:23d1f73bf130	1726	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
vladvana	0:23d1f73bf130	1727	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
vladvana	0:23d1f73bf130	1728	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
vladvana	0:23d1f73bf130	1729	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
vladvana	0:23d1f73bf130	1730	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
vladvana	0:23d1f73bf130	1731	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
vladvana	0:23d1f73bf130	1732	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
vladvana	0:23d1f73bf130	1733	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
vladvana	0:23d1f73bf130	1734	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
vladvana	0:23d1f73bf130	1735	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
vladvana	0:23d1f73bf130	1736	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
vladvana	0:23d1f73bf130	1737	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
vladvana	0:23d1f73bf130	1738	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
vladvana	0:23d1f73bf130	1739	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
vladvana	0:23d1f73bf130	1740	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
vladvana	0:23d1f73bf130	1741	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
vladvana	0:23d1f73bf130	1742	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
vladvana	0:23d1f73bf130	1743	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
vladvana	0:23d1f73bf130	1744	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
vladvana	0:23d1f73bf130	1745	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
vladvana	0:23d1f73bf130	1746	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
vladvana	0:23d1f73bf130	1747	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
vladvana	0:23d1f73bf130	1748	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
vladvana	0:23d1f73bf130	1749	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
vladvana	0:23d1f73bf130	1750	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
vladvana	0:23d1f73bf130	1751	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
vladvana	0:23d1f73bf130	1752	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
vladvana	0:23d1f73bf130	1753	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
vladvana	0:23d1f73bf130	1754	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
vladvana	0:23d1f73bf130	1755	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
vladvana	0:23d1f73bf130	1756	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
vladvana	0:23d1f73bf130	1757	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
vladvana	0:23d1f73bf130	1758	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
vladvana	0:23d1f73bf130	1759
vladvana	0:23d1f73bf130	1760	/**************** Bit definition for NVIC_ISPR register *****************/
vladvana	0:23d1f73bf130	1761	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
vladvana	0:23d1f73bf130	1762	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
vladvana	0:23d1f73bf130	1763	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
vladvana	0:23d1f73bf130	1764	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
vladvana	0:23d1f73bf130	1765	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
vladvana	0:23d1f73bf130	1766	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
vladvana	0:23d1f73bf130	1767	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
vladvana	0:23d1f73bf130	1768	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
vladvana	0:23d1f73bf130	1769	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
vladvana	0:23d1f73bf130	1770	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
vladvana	0:23d1f73bf130	1771	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
vladvana	0:23d1f73bf130	1772	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
vladvana	0:23d1f73bf130	1773	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
vladvana	0:23d1f73bf130	1774	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
vladvana	0:23d1f73bf130	1775	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
vladvana	0:23d1f73bf130	1776	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
vladvana	0:23d1f73bf130	1777	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
vladvana	0:23d1f73bf130	1778	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
vladvana	0:23d1f73bf130	1779	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
vladvana	0:23d1f73bf130	1780	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
vladvana	0:23d1f73bf130	1781	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
vladvana	0:23d1f73bf130	1782	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
vladvana	0:23d1f73bf130	1783	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
vladvana	0:23d1f73bf130	1784	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
vladvana	0:23d1f73bf130	1785	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
vladvana	0:23d1f73bf130	1786	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
vladvana	0:23d1f73bf130	1787	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
vladvana	0:23d1f73bf130	1788	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
vladvana	0:23d1f73bf130	1789	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
vladvana	0:23d1f73bf130	1790	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
vladvana	0:23d1f73bf130	1791	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
vladvana	0:23d1f73bf130	1792	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
vladvana	0:23d1f73bf130	1793	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
vladvana	0:23d1f73bf130	1794
vladvana	0:23d1f73bf130	1795	/**************** Bit definition for NVIC_ICPR register *****************/
vladvana	0:23d1f73bf130	1796	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
vladvana	0:23d1f73bf130	1797	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
vladvana	0:23d1f73bf130	1798	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
vladvana	0:23d1f73bf130	1799	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
vladvana	0:23d1f73bf130	1800	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
vladvana	0:23d1f73bf130	1801	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
vladvana	0:23d1f73bf130	1802	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
vladvana	0:23d1f73bf130	1803	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
vladvana	0:23d1f73bf130	1804	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
vladvana	0:23d1f73bf130	1805	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
vladvana	0:23d1f73bf130	1806	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
vladvana	0:23d1f73bf130	1807	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
vladvana	0:23d1f73bf130	1808	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
vladvana	0:23d1f73bf130	1809	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
vladvana	0:23d1f73bf130	1810	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
vladvana	0:23d1f73bf130	1811	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
vladvana	0:23d1f73bf130	1812	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
vladvana	0:23d1f73bf130	1813	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
vladvana	0:23d1f73bf130	1814	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
vladvana	0:23d1f73bf130	1815	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
vladvana	0:23d1f73bf130	1816	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
vladvana	0:23d1f73bf130	1817	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
vladvana	0:23d1f73bf130	1818	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
vladvana	0:23d1f73bf130	1819	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
vladvana	0:23d1f73bf130	1820	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
vladvana	0:23d1f73bf130	1821	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
vladvana	0:23d1f73bf130	1822	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
vladvana	0:23d1f73bf130	1823	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
vladvana	0:23d1f73bf130	1824	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
vladvana	0:23d1f73bf130	1825	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
vladvana	0:23d1f73bf130	1826	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
vladvana	0:23d1f73bf130	1827	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
vladvana	0:23d1f73bf130	1828	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
vladvana	0:23d1f73bf130	1829
vladvana	0:23d1f73bf130	1830	/**************** Bit definition for NVIC_IABR register *****************/
vladvana	0:23d1f73bf130	1831	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
vladvana	0:23d1f73bf130	1832	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
vladvana	0:23d1f73bf130	1833	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
vladvana	0:23d1f73bf130	1834	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
vladvana	0:23d1f73bf130	1835	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
vladvana	0:23d1f73bf130	1836	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
vladvana	0:23d1f73bf130	1837	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
vladvana	0:23d1f73bf130	1838	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
vladvana	0:23d1f73bf130	1839	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
vladvana	0:23d1f73bf130	1840	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
vladvana	0:23d1f73bf130	1841	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
vladvana	0:23d1f73bf130	1842	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
vladvana	0:23d1f73bf130	1843	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
vladvana	0:23d1f73bf130	1844	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
vladvana	0:23d1f73bf130	1845	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
vladvana	0:23d1f73bf130	1846	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
vladvana	0:23d1f73bf130	1847	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
vladvana	0:23d1f73bf130	1848	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
vladvana	0:23d1f73bf130	1849	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
vladvana	0:23d1f73bf130	1850	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
vladvana	0:23d1f73bf130	1851	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
vladvana	0:23d1f73bf130	1852	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
vladvana	0:23d1f73bf130	1853	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
vladvana	0:23d1f73bf130	1854	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
vladvana	0:23d1f73bf130	1855	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
vladvana	0:23d1f73bf130	1856	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
vladvana	0:23d1f73bf130	1857	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
vladvana	0:23d1f73bf130	1858	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
vladvana	0:23d1f73bf130	1859	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
vladvana	0:23d1f73bf130	1860	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
vladvana	0:23d1f73bf130	1861	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
vladvana	0:23d1f73bf130	1862	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
vladvana	0:23d1f73bf130	1863	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
vladvana	0:23d1f73bf130	1864
vladvana	0:23d1f73bf130	1865	/**************** Bit definition for NVIC_PRI0 register *****************/
vladvana	0:23d1f73bf130	1866	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
vladvana	0:23d1f73bf130	1867	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
vladvana	0:23d1f73bf130	1868	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
vladvana	0:23d1f73bf130	1869	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
vladvana	0:23d1f73bf130	1870
vladvana	0:23d1f73bf130	1871	/**************** Bit definition for NVIC_PRI1 register *****************/
vladvana	0:23d1f73bf130	1872	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
vladvana	0:23d1f73bf130	1873	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
vladvana	0:23d1f73bf130	1874	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
vladvana	0:23d1f73bf130	1875	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
vladvana	0:23d1f73bf130	1876
vladvana	0:23d1f73bf130	1877	/**************** Bit definition for NVIC_PRI2 register *****************/
vladvana	0:23d1f73bf130	1878	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
vladvana	0:23d1f73bf130	1879	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
vladvana	0:23d1f73bf130	1880	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
vladvana	0:23d1f73bf130	1881	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
vladvana	0:23d1f73bf130	1882
vladvana	0:23d1f73bf130	1883	/**************** Bit definition for NVIC_PRI3 register *****************/
vladvana	0:23d1f73bf130	1884	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
vladvana	0:23d1f73bf130	1885	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
vladvana	0:23d1f73bf130	1886	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
vladvana	0:23d1f73bf130	1887	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
vladvana	0:23d1f73bf130	1888
vladvana	0:23d1f73bf130	1889	/**************** Bit definition for NVIC_PRI4 register *****************/
vladvana	0:23d1f73bf130	1890	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
vladvana	0:23d1f73bf130	1891	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
vladvana	0:23d1f73bf130	1892	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
vladvana	0:23d1f73bf130	1893	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
vladvana	0:23d1f73bf130	1894
vladvana	0:23d1f73bf130	1895	/**************** Bit definition for NVIC_PRI5 register *****************/
vladvana	0:23d1f73bf130	1896	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
vladvana	0:23d1f73bf130	1897	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
vladvana	0:23d1f73bf130	1898	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
vladvana	0:23d1f73bf130	1899	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
vladvana	0:23d1f73bf130	1900
vladvana	0:23d1f73bf130	1901	/**************** Bit definition for NVIC_PRI6 register *****************/
vladvana	0:23d1f73bf130	1902	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
vladvana	0:23d1f73bf130	1903	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
vladvana	0:23d1f73bf130	1904	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
vladvana	0:23d1f73bf130	1905	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
vladvana	0:23d1f73bf130	1906
vladvana	0:23d1f73bf130	1907	/**************** Bit definition for NVIC_PRI7 register *****************/
vladvana	0:23d1f73bf130	1908	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
vladvana	0:23d1f73bf130	1909	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
vladvana	0:23d1f73bf130	1910	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
vladvana	0:23d1f73bf130	1911	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
vladvana	0:23d1f73bf130	1912
vladvana	0:23d1f73bf130	1913	/**************** Bit definition for SCB_CPUID register *****************/
vladvana	0:23d1f73bf130	1914	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
vladvana	0:23d1f73bf130	1915	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
vladvana	0:23d1f73bf130	1916	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
vladvana	0:23d1f73bf130	1917	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
vladvana	0:23d1f73bf130	1918	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
vladvana	0:23d1f73bf130	1919
vladvana	0:23d1f73bf130	1920	/***************** Bit definition for SCB_ICSR register *****************/
vladvana	0:23d1f73bf130	1921	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
vladvana	0:23d1f73bf130	1922	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
vladvana	0:23d1f73bf130	1923	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
vladvana	0:23d1f73bf130	1924	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
vladvana	0:23d1f73bf130	1925	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
vladvana	0:23d1f73bf130	1926	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
vladvana	0:23d1f73bf130	1927	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
vladvana	0:23d1f73bf130	1928	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
vladvana	0:23d1f73bf130	1929	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
vladvana	0:23d1f73bf130	1930	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
vladvana	0:23d1f73bf130	1931
vladvana	0:23d1f73bf130	1932	/***************** Bit definition for SCB_VTOR register *****************/
vladvana	0:23d1f73bf130	1933	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
vladvana	0:23d1f73bf130	1934	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
vladvana	0:23d1f73bf130	1935
vladvana	0:23d1f73bf130	1936	/!<************** Bit definition for SCB_AIRCR register *****************/
vladvana	0:23d1f73bf130	1937	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
vladvana	0:23d1f73bf130	1938	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
vladvana	0:23d1f73bf130	1939	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
vladvana	0:23d1f73bf130	1940
vladvana	0:23d1f73bf130	1941	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
vladvana	0:23d1f73bf130	1942	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
vladvana	0:23d1f73bf130	1943	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
vladvana	0:23d1f73bf130	1944	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
vladvana	0:23d1f73bf130	1945
vladvana	0:23d1f73bf130	1946	/* prority group configuration */
vladvana	0:23d1f73bf130	1947	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
vladvana	0:23d1f73bf130	1948	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
vladvana	0:23d1f73bf130	1949	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
vladvana	0:23d1f73bf130	1950	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
vladvana	0:23d1f73bf130	1951	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
vladvana	0:23d1f73bf130	1952	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
vladvana	0:23d1f73bf130	1953	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
vladvana	0:23d1f73bf130	1954	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
vladvana	0:23d1f73bf130	1955
vladvana	0:23d1f73bf130	1956	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
vladvana	0:23d1f73bf130	1957	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
vladvana	0:23d1f73bf130	1958
vladvana	0:23d1f73bf130	1959	/***************** Bit definition for SCB_SCR register ******************/
vladvana	0:23d1f73bf130	1960	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
vladvana	0:23d1f73bf130	1961	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
vladvana	0:23d1f73bf130	1962	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
vladvana	0:23d1f73bf130	1963
vladvana	0:23d1f73bf130	1964	/****************** Bit definition for SCB_CCR register *****************/
vladvana	0:23d1f73bf130	1965	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
vladvana	0:23d1f73bf130	1966	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
vladvana	0:23d1f73bf130	1967	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
vladvana	0:23d1f73bf130	1968	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
vladvana	0:23d1f73bf130	1969	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
vladvana	0:23d1f73bf130	1970	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
vladvana	0:23d1f73bf130	1971
vladvana	0:23d1f73bf130	1972	/***************** Bit definition for SCB_SHPR register ******************/
vladvana	0:23d1f73bf130	1973	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
vladvana	0:23d1f73bf130	1974	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
vladvana	0:23d1f73bf130	1975	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
vladvana	0:23d1f73bf130	1976	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
vladvana	0:23d1f73bf130	1977
vladvana	0:23d1f73bf130	1978	/**************** Bit definition for SCB_SHCSR register *****************/
vladvana	0:23d1f73bf130	1979	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
vladvana	0:23d1f73bf130	1980	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
vladvana	0:23d1f73bf130	1981	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
vladvana	0:23d1f73bf130	1982	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
vladvana	0:23d1f73bf130	1983	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
vladvana	0:23d1f73bf130	1984	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
vladvana	0:23d1f73bf130	1985	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
vladvana	0:23d1f73bf130	1986	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
vladvana	0:23d1f73bf130	1987	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
vladvana	0:23d1f73bf130	1988	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
vladvana	0:23d1f73bf130	1989	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
vladvana	0:23d1f73bf130	1990	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
vladvana	0:23d1f73bf130	1991	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
vladvana	0:23d1f73bf130	1992	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
vladvana	0:23d1f73bf130	1993
vladvana	0:23d1f73bf130	1994	/***************** Bit definition for SCB_CFSR register *****************/
vladvana	0:23d1f73bf130	1995	/!< MFSR /
vladvana	0:23d1f73bf130	1996	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
vladvana	0:23d1f73bf130	1997	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
vladvana	0:23d1f73bf130	1998	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
vladvana	0:23d1f73bf130	1999	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
vladvana	0:23d1f73bf130	2000	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
vladvana	0:23d1f73bf130	2001	/!< BFSR /
vladvana	0:23d1f73bf130	2002	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
vladvana	0:23d1f73bf130	2003	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
vladvana	0:23d1f73bf130	2004	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
vladvana	0:23d1f73bf130	2005	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
vladvana	0:23d1f73bf130	2006	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
vladvana	0:23d1f73bf130	2007	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
vladvana	0:23d1f73bf130	2008	/!< UFSR /
vladvana	0:23d1f73bf130	2009	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to execute an undefined instruction /
vladvana	0:23d1f73bf130	2010	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
vladvana	0:23d1f73bf130	2011	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
vladvana	0:23d1f73bf130	2012	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
vladvana	0:23d1f73bf130	2013	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
vladvana	0:23d1f73bf130	2014	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
vladvana	0:23d1f73bf130	2015
vladvana	0:23d1f73bf130	2016	/***************** Bit definition for SCB_HFSR register *****************/
vladvana	0:23d1f73bf130	2017	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
vladvana	0:23d1f73bf130	2018	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
vladvana	0:23d1f73bf130	2019	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
vladvana	0:23d1f73bf130	2020
vladvana	0:23d1f73bf130	2021	/***************** Bit definition for SCB_DFSR register *****************/
vladvana	0:23d1f73bf130	2022	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
vladvana	0:23d1f73bf130	2023	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
vladvana	0:23d1f73bf130	2024	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
vladvana	0:23d1f73bf130	2025	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
vladvana	0:23d1f73bf130	2026	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
vladvana	0:23d1f73bf130	2027
vladvana	0:23d1f73bf130	2028	/***************** Bit definition for SCB_MMFAR register ****************/
vladvana	0:23d1f73bf130	2029	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
vladvana	0:23d1f73bf130	2030
vladvana	0:23d1f73bf130	2031	/***************** Bit definition for SCB_BFAR register *****************/
vladvana	0:23d1f73bf130	2032	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
vladvana	0:23d1f73bf130	2033
vladvana	0:23d1f73bf130	2034	/***************** Bit definition for SCB_afsr register *****************/
vladvana	0:23d1f73bf130	2035	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
vladvana	0:23d1f73bf130	2036
vladvana	0:23d1f73bf130	2037	/******************************************************************************/
vladvana	0:23d1f73bf130	2038	/* */
vladvana	0:23d1f73bf130	2039	/* External Interrupt/Event Controller */
vladvana	0:23d1f73bf130	2040	/* */
vladvana	0:23d1f73bf130	2041	/******************************************************************************/
vladvana	0:23d1f73bf130	2042
vladvana	0:23d1f73bf130	2043	/***************** Bit definition for EXTI_IMR register *****************/
vladvana	0:23d1f73bf130	2044	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
vladvana	0:23d1f73bf130	2045	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
vladvana	0:23d1f73bf130	2046	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
vladvana	0:23d1f73bf130	2047	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
vladvana	0:23d1f73bf130	2048	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
vladvana	0:23d1f73bf130	2049	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
vladvana	0:23d1f73bf130	2050	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
vladvana	0:23d1f73bf130	2051	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
vladvana	0:23d1f73bf130	2052	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
vladvana	0:23d1f73bf130	2053	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
vladvana	0:23d1f73bf130	2054	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
vladvana	0:23d1f73bf130	2055	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
vladvana	0:23d1f73bf130	2056	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
vladvana	0:23d1f73bf130	2057	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
vladvana	0:23d1f73bf130	2058	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
vladvana	0:23d1f73bf130	2059	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
vladvana	0:23d1f73bf130	2060	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
vladvana	0:23d1f73bf130	2061	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
vladvana	0:23d1f73bf130	2062	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
vladvana	0:23d1f73bf130	2063	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
vladvana	0:23d1f73bf130	2064
vladvana	0:23d1f73bf130	2065	/***************** Bit definition for EXTI_EMR register *****************/
vladvana	0:23d1f73bf130	2066	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
vladvana	0:23d1f73bf130	2067	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
vladvana	0:23d1f73bf130	2068	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
vladvana	0:23d1f73bf130	2069	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
vladvana	0:23d1f73bf130	2070	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
vladvana	0:23d1f73bf130	2071	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
vladvana	0:23d1f73bf130	2072	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
vladvana	0:23d1f73bf130	2073	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
vladvana	0:23d1f73bf130	2074	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
vladvana	0:23d1f73bf130	2075	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
vladvana	0:23d1f73bf130	2076	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
vladvana	0:23d1f73bf130	2077	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
vladvana	0:23d1f73bf130	2078	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
vladvana	0:23d1f73bf130	2079	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
vladvana	0:23d1f73bf130	2080	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
vladvana	0:23d1f73bf130	2081	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
vladvana	0:23d1f73bf130	2082	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
vladvana	0:23d1f73bf130	2083	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
vladvana	0:23d1f73bf130	2084	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
vladvana	0:23d1f73bf130	2085	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
vladvana	0:23d1f73bf130	2086
vladvana	0:23d1f73bf130	2087	/**************** Bit definition for EXTI_RTSR register *****************/
vladvana	0:23d1f73bf130	2088	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
vladvana	0:23d1f73bf130	2089	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
vladvana	0:23d1f73bf130	2090	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
vladvana	0:23d1f73bf130	2091	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
vladvana	0:23d1f73bf130	2092	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
vladvana	0:23d1f73bf130	2093	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
vladvana	0:23d1f73bf130	2094	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
vladvana	0:23d1f73bf130	2095	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
vladvana	0:23d1f73bf130	2096	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
vladvana	0:23d1f73bf130	2097	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
vladvana	0:23d1f73bf130	2098	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
vladvana	0:23d1f73bf130	2099	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
vladvana	0:23d1f73bf130	2100	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
vladvana	0:23d1f73bf130	2101	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
vladvana	0:23d1f73bf130	2102	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
vladvana	0:23d1f73bf130	2103	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
vladvana	0:23d1f73bf130	2104	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
vladvana	0:23d1f73bf130	2105	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
vladvana	0:23d1f73bf130	2106	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
vladvana	0:23d1f73bf130	2107	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
vladvana	0:23d1f73bf130	2108
vladvana	0:23d1f73bf130	2109	/**************** Bit definition for EXTI_FTSR register *****************/
vladvana	0:23d1f73bf130	2110	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
vladvana	0:23d1f73bf130	2111	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
vladvana	0:23d1f73bf130	2112	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
vladvana	0:23d1f73bf130	2113	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
vladvana	0:23d1f73bf130	2114	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
vladvana	0:23d1f73bf130	2115	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
vladvana	0:23d1f73bf130	2116	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
vladvana	0:23d1f73bf130	2117	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
vladvana	0:23d1f73bf130	2118	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
vladvana	0:23d1f73bf130	2119	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
vladvana	0:23d1f73bf130	2120	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
vladvana	0:23d1f73bf130	2121	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
vladvana	0:23d1f73bf130	2122	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
vladvana	0:23d1f73bf130	2123	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
vladvana	0:23d1f73bf130	2124	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
vladvana	0:23d1f73bf130	2125	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
vladvana	0:23d1f73bf130	2126	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
vladvana	0:23d1f73bf130	2127	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
vladvana	0:23d1f73bf130	2128	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
vladvana	0:23d1f73bf130	2129	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
vladvana	0:23d1f73bf130	2130
vladvana	0:23d1f73bf130	2131	/**************** Bit definition for EXTI_SWIER register ****************/
vladvana	0:23d1f73bf130	2132	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
vladvana	0:23d1f73bf130	2133	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
vladvana	0:23d1f73bf130	2134	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
vladvana	0:23d1f73bf130	2135	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
vladvana	0:23d1f73bf130	2136	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
vladvana	0:23d1f73bf130	2137	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
vladvana	0:23d1f73bf130	2138	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
vladvana	0:23d1f73bf130	2139	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
vladvana	0:23d1f73bf130	2140	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
vladvana	0:23d1f73bf130	2141	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
vladvana	0:23d1f73bf130	2142	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
vladvana	0:23d1f73bf130	2143	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
vladvana	0:23d1f73bf130	2144	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
vladvana	0:23d1f73bf130	2145	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
vladvana	0:23d1f73bf130	2146	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
vladvana	0:23d1f73bf130	2147	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
vladvana	0:23d1f73bf130	2148	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
vladvana	0:23d1f73bf130	2149	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
vladvana	0:23d1f73bf130	2150	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
vladvana	0:23d1f73bf130	2151	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
vladvana	0:23d1f73bf130	2152
vladvana	0:23d1f73bf130	2153	/***************** Bit definition for EXTI_PR register ******************/
vladvana	0:23d1f73bf130	2154	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
vladvana	0:23d1f73bf130	2155	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
vladvana	0:23d1f73bf130	2156	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
vladvana	0:23d1f73bf130	2157	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
vladvana	0:23d1f73bf130	2158	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
vladvana	0:23d1f73bf130	2159	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
vladvana	0:23d1f73bf130	2160	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
vladvana	0:23d1f73bf130	2161	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
vladvana	0:23d1f73bf130	2162	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
vladvana	0:23d1f73bf130	2163	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
vladvana	0:23d1f73bf130	2164	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
vladvana	0:23d1f73bf130	2165	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
vladvana	0:23d1f73bf130	2166	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
vladvana	0:23d1f73bf130	2167	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
vladvana	0:23d1f73bf130	2168	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
vladvana	0:23d1f73bf130	2169	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
vladvana	0:23d1f73bf130	2170	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
vladvana	0:23d1f73bf130	2171	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
vladvana	0:23d1f73bf130	2172	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
vladvana	0:23d1f73bf130	2173	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
vladvana	0:23d1f73bf130	2174
vladvana	0:23d1f73bf130	2175	/******************************************************************************/
vladvana	0:23d1f73bf130	2176	/* */
vladvana	0:23d1f73bf130	2177	/* DMA Controller */
vladvana	0:23d1f73bf130	2178	/* */
vladvana	0:23d1f73bf130	2179	/******************************************************************************/
vladvana	0:23d1f73bf130	2180
vladvana	0:23d1f73bf130	2181	/***************** Bit definition for DMA_ISR register ******************/
vladvana	0:23d1f73bf130	2182	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
vladvana	0:23d1f73bf130	2183	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
vladvana	0:23d1f73bf130	2184	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
vladvana	0:23d1f73bf130	2185	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
vladvana	0:23d1f73bf130	2186	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
vladvana	0:23d1f73bf130	2187	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
vladvana	0:23d1f73bf130	2188	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
vladvana	0:23d1f73bf130	2189	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
vladvana	0:23d1f73bf130	2190	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
vladvana	0:23d1f73bf130	2191	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
vladvana	0:23d1f73bf130	2192	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
vladvana	0:23d1f73bf130	2193	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
vladvana	0:23d1f73bf130	2194	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
vladvana	0:23d1f73bf130	2195	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
vladvana	0:23d1f73bf130	2196	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
vladvana	0:23d1f73bf130	2197	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
vladvana	0:23d1f73bf130	2198	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
vladvana	0:23d1f73bf130	2199	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
vladvana	0:23d1f73bf130	2200	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
vladvana	0:23d1f73bf130	2201	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
vladvana	0:23d1f73bf130	2202	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
vladvana	0:23d1f73bf130	2203	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
vladvana	0:23d1f73bf130	2204	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
vladvana	0:23d1f73bf130	2205	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
vladvana	0:23d1f73bf130	2206	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
vladvana	0:23d1f73bf130	2207	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
vladvana	0:23d1f73bf130	2208	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
vladvana	0:23d1f73bf130	2209	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
vladvana	0:23d1f73bf130	2210
vladvana	0:23d1f73bf130	2211	/***************** Bit definition for DMA_IFCR register *****************/
vladvana	0:23d1f73bf130	2212	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
vladvana	0:23d1f73bf130	2213	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
vladvana	0:23d1f73bf130	2214	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
vladvana	0:23d1f73bf130	2215	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
vladvana	0:23d1f73bf130	2216	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
vladvana	0:23d1f73bf130	2217	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
vladvana	0:23d1f73bf130	2218	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
vladvana	0:23d1f73bf130	2219	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
vladvana	0:23d1f73bf130	2220	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
vladvana	0:23d1f73bf130	2221	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
vladvana	0:23d1f73bf130	2222	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
vladvana	0:23d1f73bf130	2223	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
vladvana	0:23d1f73bf130	2224	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
vladvana	0:23d1f73bf130	2225	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
vladvana	0:23d1f73bf130	2226	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
vladvana	0:23d1f73bf130	2227	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
vladvana	0:23d1f73bf130	2228	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
vladvana	0:23d1f73bf130	2229	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
vladvana	0:23d1f73bf130	2230	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
vladvana	0:23d1f73bf130	2231	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
vladvana	0:23d1f73bf130	2232	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
vladvana	0:23d1f73bf130	2233	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
vladvana	0:23d1f73bf130	2234	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
vladvana	0:23d1f73bf130	2235	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
vladvana	0:23d1f73bf130	2236	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
vladvana	0:23d1f73bf130	2237	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
vladvana	0:23d1f73bf130	2238	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
vladvana	0:23d1f73bf130	2239	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
vladvana	0:23d1f73bf130	2240
vladvana	0:23d1f73bf130	2241	/***************** Bit definition for DMA_CCR register *****************/
vladvana	0:23d1f73bf130	2242	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
vladvana	0:23d1f73bf130	2243	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
vladvana	0:23d1f73bf130	2244	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
vladvana	0:23d1f73bf130	2245	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
vladvana	0:23d1f73bf130	2246	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
vladvana	0:23d1f73bf130	2247	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
vladvana	0:23d1f73bf130	2248	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
vladvana	0:23d1f73bf130	2249	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
vladvana	0:23d1f73bf130	2250
vladvana	0:23d1f73bf130	2251	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
vladvana	0:23d1f73bf130	2252	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
vladvana	0:23d1f73bf130	2253	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
vladvana	0:23d1f73bf130	2254
vladvana	0:23d1f73bf130	2255	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
vladvana	0:23d1f73bf130	2256	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	2257	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	2258
vladvana	0:23d1f73bf130	2259	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
vladvana	0:23d1f73bf130	2260	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2261	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2262
vladvana	0:23d1f73bf130	2263	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
vladvana	0:23d1f73bf130	2264
vladvana	0:23d1f73bf130	2265	/**************** Bit definition for DMA_CNDTR register ****************/
vladvana	0:23d1f73bf130	2266	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
vladvana	0:23d1f73bf130	2267
vladvana	0:23d1f73bf130	2268	/**************** Bit definition for DMA_CPAR register *****************/
vladvana	0:23d1f73bf130	2269	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
vladvana	0:23d1f73bf130	2270
vladvana	0:23d1f73bf130	2271	/**************** Bit definition for DMA_CMAR register *****************/
vladvana	0:23d1f73bf130	2272	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
vladvana	0:23d1f73bf130	2273
vladvana	0:23d1f73bf130	2274	/******************************************************************************/
vladvana	0:23d1f73bf130	2275	/* */
vladvana	0:23d1f73bf130	2276	/* Analog to Digital Converter */
vladvana	0:23d1f73bf130	2277	/* */
vladvana	0:23d1f73bf130	2278	/******************************************************************************/
vladvana	0:23d1f73bf130	2279
vladvana	0:23d1f73bf130	2280	/****************** Bit definition for ADC_SR register ******************/
vladvana	0:23d1f73bf130	2281	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
vladvana	0:23d1f73bf130	2282	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
vladvana	0:23d1f73bf130	2283	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
vladvana	0:23d1f73bf130	2284	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
vladvana	0:23d1f73bf130	2285	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
vladvana	0:23d1f73bf130	2286
vladvana	0:23d1f73bf130	2287	/***************** Bit definition for ADC_CR1 register ******************/
vladvana	0:23d1f73bf130	2288	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
vladvana	0:23d1f73bf130	2289	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2290	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2291	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2292	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	2293	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	2294
vladvana	0:23d1f73bf130	2295	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
vladvana	0:23d1f73bf130	2296	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
vladvana	0:23d1f73bf130	2297	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
vladvana	0:23d1f73bf130	2298	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
vladvana	0:23d1f73bf130	2299	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
vladvana	0:23d1f73bf130	2300	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
vladvana	0:23d1f73bf130	2301	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
vladvana	0:23d1f73bf130	2302	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
vladvana	0:23d1f73bf130	2303
vladvana	0:23d1f73bf130	2304	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
vladvana	0:23d1f73bf130	2305	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2306	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2307	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2308
vladvana	0:23d1f73bf130	2309	#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /!< DUALMOD[3:0] bits (Dual mode selection) /
vladvana	0:23d1f73bf130	2310	#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2311	#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2312	#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2313	#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2314
vladvana	0:23d1f73bf130	2315	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
vladvana	0:23d1f73bf130	2316	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
vladvana	0:23d1f73bf130	2317
vladvana	0:23d1f73bf130	2318
vladvana	0:23d1f73bf130	2319	/***************** Bit definition for ADC_CR2 register ******************/
vladvana	0:23d1f73bf130	2320	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
vladvana	0:23d1f73bf130	2321	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
vladvana	0:23d1f73bf130	2322	#define ADC_CR2_CAL ((uint32_t)0x00000004) /!< A/D Calibration /
vladvana	0:23d1f73bf130	2323	#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /!< Reset Calibration /
vladvana	0:23d1f73bf130	2324	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
vladvana	0:23d1f73bf130	2325	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
vladvana	0:23d1f73bf130	2326
vladvana	0:23d1f73bf130	2327	#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /!< JEXTSEL[2:0] bits (External event select for injected group) /
vladvana	0:23d1f73bf130	2328	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2329	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2330	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2331
vladvana	0:23d1f73bf130	2332	#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /!< External Trigger Conversion mode for injected channels /
vladvana	0:23d1f73bf130	2333
vladvana	0:23d1f73bf130	2334	#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
vladvana	0:23d1f73bf130	2335	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2336	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2337	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2338
vladvana	0:23d1f73bf130	2339	#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /!< External Trigger Conversion mode for regular channels /
vladvana	0:23d1f73bf130	2340	#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /!< Start Conversion of injected channels /
vladvana	0:23d1f73bf130	2341	#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /!< Start Conversion of regular channels /
vladvana	0:23d1f73bf130	2342	#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
vladvana	0:23d1f73bf130	2343
vladvana	0:23d1f73bf130	2344	/**************** Bit definition for ADC_SMPR1 register *****************/
vladvana	0:23d1f73bf130	2345	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
vladvana	0:23d1f73bf130	2346	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2347	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2348	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2349
vladvana	0:23d1f73bf130	2350	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
vladvana	0:23d1f73bf130	2351	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
vladvana	0:23d1f73bf130	2352	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
vladvana	0:23d1f73bf130	2353	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
vladvana	0:23d1f73bf130	2354
vladvana	0:23d1f73bf130	2355	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
vladvana	0:23d1f73bf130	2356	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
vladvana	0:23d1f73bf130	2357	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
vladvana	0:23d1f73bf130	2358	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
vladvana	0:23d1f73bf130	2359
vladvana	0:23d1f73bf130	2360	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
vladvana	0:23d1f73bf130	2361	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	2362	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	2363	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
vladvana	0:23d1f73bf130	2364
vladvana	0:23d1f73bf130	2365	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
vladvana	0:23d1f73bf130	2366	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2367	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2368	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2369
vladvana	0:23d1f73bf130	2370	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 15 Sample time selection) /
vladvana	0:23d1f73bf130	2371	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2372	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2373	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2374
vladvana	0:23d1f73bf130	2375	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
vladvana	0:23d1f73bf130	2376	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2377	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2378	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2379
vladvana	0:23d1f73bf130	2380	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
vladvana	0:23d1f73bf130	2381	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2382	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2383	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2384
vladvana	0:23d1f73bf130	2385	/**************** Bit definition for ADC_SMPR2 register *****************/
vladvana	0:23d1f73bf130	2386	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
vladvana	0:23d1f73bf130	2387	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2388	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2389	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2390
vladvana	0:23d1f73bf130	2391	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
vladvana	0:23d1f73bf130	2392	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
vladvana	0:23d1f73bf130	2393	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
vladvana	0:23d1f73bf130	2394	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
vladvana	0:23d1f73bf130	2395
vladvana	0:23d1f73bf130	2396	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
vladvana	0:23d1f73bf130	2397	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
vladvana	0:23d1f73bf130	2398	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
vladvana	0:23d1f73bf130	2399	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
vladvana	0:23d1f73bf130	2400
vladvana	0:23d1f73bf130	2401	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
vladvana	0:23d1f73bf130	2402	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	2403	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	2404	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
vladvana	0:23d1f73bf130	2405
vladvana	0:23d1f73bf130	2406	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
vladvana	0:23d1f73bf130	2407	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2408	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2409	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2410
vladvana	0:23d1f73bf130	2411	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
vladvana	0:23d1f73bf130	2412	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2413	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2414	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2415
vladvana	0:23d1f73bf130	2416	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
vladvana	0:23d1f73bf130	2417	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2418	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2419	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2420
vladvana	0:23d1f73bf130	2421	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
vladvana	0:23d1f73bf130	2422	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2423	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2424	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2425
vladvana	0:23d1f73bf130	2426	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
vladvana	0:23d1f73bf130	2427	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2428	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2429	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2430
vladvana	0:23d1f73bf130	2431	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
vladvana	0:23d1f73bf130	2432	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2433	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2434	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2435
vladvana	0:23d1f73bf130	2436	/**************** Bit definition for ADC_JOFR1 register *****************/
vladvana	0:23d1f73bf130	2437	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
vladvana	0:23d1f73bf130	2438
vladvana	0:23d1f73bf130	2439	/**************** Bit definition for ADC_JOFR2 register *****************/
vladvana	0:23d1f73bf130	2440	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
vladvana	0:23d1f73bf130	2441
vladvana	0:23d1f73bf130	2442	/**************** Bit definition for ADC_JOFR3 register *****************/
vladvana	0:23d1f73bf130	2443	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
vladvana	0:23d1f73bf130	2444
vladvana	0:23d1f73bf130	2445	/**************** Bit definition for ADC_JOFR4 register *****************/
vladvana	0:23d1f73bf130	2446	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
vladvana	0:23d1f73bf130	2447
vladvana	0:23d1f73bf130	2448	/***************** Bit definition for ADC_HTR register ******************/
vladvana	0:23d1f73bf130	2449	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
vladvana	0:23d1f73bf130	2450
vladvana	0:23d1f73bf130	2451	/***************** Bit definition for ADC_LTR register ******************/
vladvana	0:23d1f73bf130	2452	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
vladvana	0:23d1f73bf130	2453
vladvana	0:23d1f73bf130	2454	/***************** Bit definition for ADC_SQR1 register *****************/
vladvana	0:23d1f73bf130	2455	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2456	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2457	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2458	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2459	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	2460	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	2461
vladvana	0:23d1f73bf130	2462	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2463	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
vladvana	0:23d1f73bf130	2464	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
vladvana	0:23d1f73bf130	2465	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
vladvana	0:23d1f73bf130	2466	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
vladvana	0:23d1f73bf130	2467	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
vladvana	0:23d1f73bf130	2468
vladvana	0:23d1f73bf130	2469	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2470	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	2471	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	2472	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2473	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2474	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2475
vladvana	0:23d1f73bf130	2476	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2477	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2478	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2479	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2480	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2481	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2482
vladvana	0:23d1f73bf130	2483	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
vladvana	0:23d1f73bf130	2484	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2485	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2486	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2487	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2488
vladvana	0:23d1f73bf130	2489	/***************** Bit definition for ADC_SQR2 register *****************/
vladvana	0:23d1f73bf130	2490	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2491	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2492	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2493	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2494	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	2495	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	2496
vladvana	0:23d1f73bf130	2497	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2498	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
vladvana	0:23d1f73bf130	2499	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
vladvana	0:23d1f73bf130	2500	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
vladvana	0:23d1f73bf130	2501	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
vladvana	0:23d1f73bf130	2502	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
vladvana	0:23d1f73bf130	2503
vladvana	0:23d1f73bf130	2504	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2505	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	2506	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	2507	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2508	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2509	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2510
vladvana	0:23d1f73bf130	2511	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2512	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2513	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2514	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2515	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2516	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2517
vladvana	0:23d1f73bf130	2518	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2519	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2520	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2521	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2522	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2523	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2524
vladvana	0:23d1f73bf130	2525	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2526	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2527	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2528	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2529	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2530	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2531
vladvana	0:23d1f73bf130	2532	/***************** Bit definition for ADC_SQR3 register *****************/
vladvana	0:23d1f73bf130	2533	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
vladvana	0:23d1f73bf130	2534	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2535	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2536	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2537	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	2538	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	2539
vladvana	0:23d1f73bf130	2540	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
vladvana	0:23d1f73bf130	2541	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
vladvana	0:23d1f73bf130	2542	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
vladvana	0:23d1f73bf130	2543	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
vladvana	0:23d1f73bf130	2544	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
vladvana	0:23d1f73bf130	2545	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
vladvana	0:23d1f73bf130	2546
vladvana	0:23d1f73bf130	2547	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
vladvana	0:23d1f73bf130	2548	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	2549	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	2550	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2551	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2552	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2553
vladvana	0:23d1f73bf130	2554	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2555	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2556	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2557	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2558	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2559	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2560
vladvana	0:23d1f73bf130	2561	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2562	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2563	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2564	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2565	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2566	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2567
vladvana	0:23d1f73bf130	2568	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
vladvana	0:23d1f73bf130	2569	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2570	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2571	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2572	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2573	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2574
vladvana	0:23d1f73bf130	2575	/***************** Bit definition for ADC_JSQR register *****************/
vladvana	0:23d1f73bf130	2576	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
vladvana	0:23d1f73bf130	2577	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2578	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2579	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2580	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	2581	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	2582
vladvana	0:23d1f73bf130	2583	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
vladvana	0:23d1f73bf130	2584	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
vladvana	0:23d1f73bf130	2585	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
vladvana	0:23d1f73bf130	2586	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
vladvana	0:23d1f73bf130	2587	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
vladvana	0:23d1f73bf130	2588	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
vladvana	0:23d1f73bf130	2589
vladvana	0:23d1f73bf130	2590	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
vladvana	0:23d1f73bf130	2591	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	2592	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	2593	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2594	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2595	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2596
vladvana	0:23d1f73bf130	2597	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
vladvana	0:23d1f73bf130	2598	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2599	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2600	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
vladvana	0:23d1f73bf130	2601	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
vladvana	0:23d1f73bf130	2602	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
vladvana	0:23d1f73bf130	2603
vladvana	0:23d1f73bf130	2604	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
vladvana	0:23d1f73bf130	2605	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
vladvana	0:23d1f73bf130	2606	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
vladvana	0:23d1f73bf130	2607
vladvana	0:23d1f73bf130	2608	/***************** Bit definition for ADC_JDR1 register *****************/
vladvana	0:23d1f73bf130	2609	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
vladvana	0:23d1f73bf130	2610
vladvana	0:23d1f73bf130	2611	/***************** Bit definition for ADC_JDR2 register *****************/
vladvana	0:23d1f73bf130	2612	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
vladvana	0:23d1f73bf130	2613
vladvana	0:23d1f73bf130	2614	/***************** Bit definition for ADC_JDR3 register *****************/
vladvana	0:23d1f73bf130	2615	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
vladvana	0:23d1f73bf130	2616
vladvana	0:23d1f73bf130	2617	/***************** Bit definition for ADC_JDR4 register *****************/
vladvana	0:23d1f73bf130	2618	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
vladvana	0:23d1f73bf130	2619
vladvana	0:23d1f73bf130	2620	/****************** Bit definition for ADC_DR register ******************/
vladvana	0:23d1f73bf130	2621	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
vladvana	0:23d1f73bf130	2622	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!< ADC2 data /
vladvana	0:23d1f73bf130	2623
vladvana	0:23d1f73bf130	2624
vladvana	0:23d1f73bf130	2625	/*****************************************************************************/
vladvana	0:23d1f73bf130	2626	/* */
vladvana	0:23d1f73bf130	2627	/* Timers (TIM) */
vladvana	0:23d1f73bf130	2628	/* */
vladvana	0:23d1f73bf130	2629	/*****************************************************************************/
vladvana	0:23d1f73bf130	2630	/***************** Bit definition for TIM_CR1 register *****************/
vladvana	0:23d1f73bf130	2631	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
vladvana	0:23d1f73bf130	2632	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
vladvana	0:23d1f73bf130	2633	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
vladvana	0:23d1f73bf130	2634	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
vladvana	0:23d1f73bf130	2635	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
vladvana	0:23d1f73bf130	2636
vladvana	0:23d1f73bf130	2637	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
vladvana	0:23d1f73bf130	2638	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
vladvana	0:23d1f73bf130	2639	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
vladvana	0:23d1f73bf130	2640
vladvana	0:23d1f73bf130	2641	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
vladvana	0:23d1f73bf130	2642
vladvana	0:23d1f73bf130	2643	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
vladvana	0:23d1f73bf130	2644	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
vladvana	0:23d1f73bf130	2645	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
vladvana	0:23d1f73bf130	2646
vladvana	0:23d1f73bf130	2647	/***************** Bit definition for TIM_CR2 register *****************/
vladvana	0:23d1f73bf130	2648	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
vladvana	0:23d1f73bf130	2649	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
vladvana	0:23d1f73bf130	2650	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
vladvana	0:23d1f73bf130	2651
vladvana	0:23d1f73bf130	2652	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
vladvana	0:23d1f73bf130	2653	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
vladvana	0:23d1f73bf130	2654	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
vladvana	0:23d1f73bf130	2655	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
vladvana	0:23d1f73bf130	2656
vladvana	0:23d1f73bf130	2657	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
vladvana	0:23d1f73bf130	2658	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
vladvana	0:23d1f73bf130	2659	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
vladvana	0:23d1f73bf130	2660	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
vladvana	0:23d1f73bf130	2661	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
vladvana	0:23d1f73bf130	2662	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
vladvana	0:23d1f73bf130	2663	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
vladvana	0:23d1f73bf130	2664	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
vladvana	0:23d1f73bf130	2665
vladvana	0:23d1f73bf130	2666	/***************** Bit definition for TIM_SMCR register ****************/
vladvana	0:23d1f73bf130	2667	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
vladvana	0:23d1f73bf130	2668	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
vladvana	0:23d1f73bf130	2669	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
vladvana	0:23d1f73bf130	2670	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
vladvana	0:23d1f73bf130	2671
vladvana	0:23d1f73bf130	2672	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
vladvana	0:23d1f73bf130	2673
vladvana	0:23d1f73bf130	2674	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
vladvana	0:23d1f73bf130	2675	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
vladvana	0:23d1f73bf130	2676	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
vladvana	0:23d1f73bf130	2677	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
vladvana	0:23d1f73bf130	2678
vladvana	0:23d1f73bf130	2679	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
vladvana	0:23d1f73bf130	2680
vladvana	0:23d1f73bf130	2681	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
vladvana	0:23d1f73bf130	2682	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
vladvana	0:23d1f73bf130	2683	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
vladvana	0:23d1f73bf130	2684	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
vladvana	0:23d1f73bf130	2685	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
vladvana	0:23d1f73bf130	2686
vladvana	0:23d1f73bf130	2687	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
vladvana	0:23d1f73bf130	2688	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
vladvana	0:23d1f73bf130	2689	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
vladvana	0:23d1f73bf130	2690
vladvana	0:23d1f73bf130	2691	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
vladvana	0:23d1f73bf130	2692	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
vladvana	0:23d1f73bf130	2693
vladvana	0:23d1f73bf130	2694	/***************** Bit definition for TIM_DIER register ****************/
vladvana	0:23d1f73bf130	2695	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
vladvana	0:23d1f73bf130	2696	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
vladvana	0:23d1f73bf130	2697	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
vladvana	0:23d1f73bf130	2698	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
vladvana	0:23d1f73bf130	2699	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
vladvana	0:23d1f73bf130	2700	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
vladvana	0:23d1f73bf130	2701	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
vladvana	0:23d1f73bf130	2702	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
vladvana	0:23d1f73bf130	2703	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
vladvana	0:23d1f73bf130	2704	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
vladvana	0:23d1f73bf130	2705	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
vladvana	0:23d1f73bf130	2706	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
vladvana	0:23d1f73bf130	2707	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
vladvana	0:23d1f73bf130	2708	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
vladvana	0:23d1f73bf130	2709	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
vladvana	0:23d1f73bf130	2710
vladvana	0:23d1f73bf130	2711	/****************** Bit definition for TIM_SR register *****************/
vladvana	0:23d1f73bf130	2712	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
vladvana	0:23d1f73bf130	2713	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
vladvana	0:23d1f73bf130	2714	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
vladvana	0:23d1f73bf130	2715	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
vladvana	0:23d1f73bf130	2716	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
vladvana	0:23d1f73bf130	2717	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
vladvana	0:23d1f73bf130	2718	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
vladvana	0:23d1f73bf130	2719	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
vladvana	0:23d1f73bf130	2720	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
vladvana	0:23d1f73bf130	2721	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
vladvana	0:23d1f73bf130	2722	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
vladvana	0:23d1f73bf130	2723	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
vladvana	0:23d1f73bf130	2724
vladvana	0:23d1f73bf130	2725	/***************** Bit definition for TIM_EGR register *****************/
vladvana	0:23d1f73bf130	2726	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
vladvana	0:23d1f73bf130	2727	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
vladvana	0:23d1f73bf130	2728	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
vladvana	0:23d1f73bf130	2729	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
vladvana	0:23d1f73bf130	2730	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
vladvana	0:23d1f73bf130	2731	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
vladvana	0:23d1f73bf130	2732	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
vladvana	0:23d1f73bf130	2733	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
vladvana	0:23d1f73bf130	2734
vladvana	0:23d1f73bf130	2735	/**************** Bit definition for TIM_CCMR1 register ****************/
vladvana	0:23d1f73bf130	2736	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
vladvana	0:23d1f73bf130	2737	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
vladvana	0:23d1f73bf130	2738	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
vladvana	0:23d1f73bf130	2739
vladvana	0:23d1f73bf130	2740	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
vladvana	0:23d1f73bf130	2741	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
vladvana	0:23d1f73bf130	2742
vladvana	0:23d1f73bf130	2743	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
vladvana	0:23d1f73bf130	2744	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
vladvana	0:23d1f73bf130	2745	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
vladvana	0:23d1f73bf130	2746	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
vladvana	0:23d1f73bf130	2747
vladvana	0:23d1f73bf130	2748	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
vladvana	0:23d1f73bf130	2749
vladvana	0:23d1f73bf130	2750	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
vladvana	0:23d1f73bf130	2751	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
vladvana	0:23d1f73bf130	2752	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
vladvana	0:23d1f73bf130	2753
vladvana	0:23d1f73bf130	2754	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
vladvana	0:23d1f73bf130	2755	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
vladvana	0:23d1f73bf130	2756
vladvana	0:23d1f73bf130	2757	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
vladvana	0:23d1f73bf130	2758	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
vladvana	0:23d1f73bf130	2759	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
vladvana	0:23d1f73bf130	2760	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
vladvana	0:23d1f73bf130	2761
vladvana	0:23d1f73bf130	2762	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
vladvana	0:23d1f73bf130	2763
vladvana	0:23d1f73bf130	2764	/---------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	2765
vladvana	0:23d1f73bf130	2766	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
vladvana	0:23d1f73bf130	2767	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
vladvana	0:23d1f73bf130	2768	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
vladvana	0:23d1f73bf130	2769
vladvana	0:23d1f73bf130	2770	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
vladvana	0:23d1f73bf130	2771	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
vladvana	0:23d1f73bf130	2772	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
vladvana	0:23d1f73bf130	2773	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
vladvana	0:23d1f73bf130	2774	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
vladvana	0:23d1f73bf130	2775
vladvana	0:23d1f73bf130	2776	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
vladvana	0:23d1f73bf130	2777	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
vladvana	0:23d1f73bf130	2778	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
vladvana	0:23d1f73bf130	2779
vladvana	0:23d1f73bf130	2780	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
vladvana	0:23d1f73bf130	2781	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
vladvana	0:23d1f73bf130	2782	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
vladvana	0:23d1f73bf130	2783	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
vladvana	0:23d1f73bf130	2784	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
vladvana	0:23d1f73bf130	2785
vladvana	0:23d1f73bf130	2786	/**************** Bit definition for TIM_CCMR2 register ****************/
vladvana	0:23d1f73bf130	2787	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
vladvana	0:23d1f73bf130	2788	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
vladvana	0:23d1f73bf130	2789	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
vladvana	0:23d1f73bf130	2790
vladvana	0:23d1f73bf130	2791	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
vladvana	0:23d1f73bf130	2792	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
vladvana	0:23d1f73bf130	2793
vladvana	0:23d1f73bf130	2794	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
vladvana	0:23d1f73bf130	2795	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
vladvana	0:23d1f73bf130	2796	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
vladvana	0:23d1f73bf130	2797	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
vladvana	0:23d1f73bf130	2798
vladvana	0:23d1f73bf130	2799	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
vladvana	0:23d1f73bf130	2800
vladvana	0:23d1f73bf130	2801	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
vladvana	0:23d1f73bf130	2802	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
vladvana	0:23d1f73bf130	2803	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
vladvana	0:23d1f73bf130	2804
vladvana	0:23d1f73bf130	2805	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
vladvana	0:23d1f73bf130	2806	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
vladvana	0:23d1f73bf130	2807
vladvana	0:23d1f73bf130	2808	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
vladvana	0:23d1f73bf130	2809	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
vladvana	0:23d1f73bf130	2810	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
vladvana	0:23d1f73bf130	2811	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
vladvana	0:23d1f73bf130	2812
vladvana	0:23d1f73bf130	2813	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
vladvana	0:23d1f73bf130	2814
vladvana	0:23d1f73bf130	2815	/---------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	2816
vladvana	0:23d1f73bf130	2817	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
vladvana	0:23d1f73bf130	2818	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
vladvana	0:23d1f73bf130	2819	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
vladvana	0:23d1f73bf130	2820
vladvana	0:23d1f73bf130	2821	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
vladvana	0:23d1f73bf130	2822	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
vladvana	0:23d1f73bf130	2823	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
vladvana	0:23d1f73bf130	2824	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
vladvana	0:23d1f73bf130	2825	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
vladvana	0:23d1f73bf130	2826
vladvana	0:23d1f73bf130	2827	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
vladvana	0:23d1f73bf130	2828	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
vladvana	0:23d1f73bf130	2829	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
vladvana	0:23d1f73bf130	2830
vladvana	0:23d1f73bf130	2831	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
vladvana	0:23d1f73bf130	2832	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
vladvana	0:23d1f73bf130	2833	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
vladvana	0:23d1f73bf130	2834	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
vladvana	0:23d1f73bf130	2835	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
vladvana	0:23d1f73bf130	2836
vladvana	0:23d1f73bf130	2837	/***************** Bit definition for TIM_CCER register ****************/
vladvana	0:23d1f73bf130	2838	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
vladvana	0:23d1f73bf130	2839	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
vladvana	0:23d1f73bf130	2840	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
vladvana	0:23d1f73bf130	2841	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
vladvana	0:23d1f73bf130	2842	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
vladvana	0:23d1f73bf130	2843	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
vladvana	0:23d1f73bf130	2844	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
vladvana	0:23d1f73bf130	2845	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
vladvana	0:23d1f73bf130	2846	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
vladvana	0:23d1f73bf130	2847	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
vladvana	0:23d1f73bf130	2848	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
vladvana	0:23d1f73bf130	2849	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
vladvana	0:23d1f73bf130	2850	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
vladvana	0:23d1f73bf130	2851	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
vladvana	0:23d1f73bf130	2852	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
vladvana	0:23d1f73bf130	2853
vladvana	0:23d1f73bf130	2854	/***************** Bit definition for TIM_CNT register *****************/
vladvana	0:23d1f73bf130	2855	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
vladvana	0:23d1f73bf130	2856
vladvana	0:23d1f73bf130	2857	/***************** Bit definition for TIM_PSC register *****************/
vladvana	0:23d1f73bf130	2858	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
vladvana	0:23d1f73bf130	2859
vladvana	0:23d1f73bf130	2860	/***************** Bit definition for TIM_ARR register *****************/
vladvana	0:23d1f73bf130	2861	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
vladvana	0:23d1f73bf130	2862
vladvana	0:23d1f73bf130	2863	/***************** Bit definition for TIM_RCR register *****************/
vladvana	0:23d1f73bf130	2864	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
vladvana	0:23d1f73bf130	2865
vladvana	0:23d1f73bf130	2866	/***************** Bit definition for TIM_CCR1 register ****************/
vladvana	0:23d1f73bf130	2867	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
vladvana	0:23d1f73bf130	2868
vladvana	0:23d1f73bf130	2869	/***************** Bit definition for TIM_CCR2 register ****************/
vladvana	0:23d1f73bf130	2870	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
vladvana	0:23d1f73bf130	2871
vladvana	0:23d1f73bf130	2872	/***************** Bit definition for TIM_CCR3 register ****************/
vladvana	0:23d1f73bf130	2873	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
vladvana	0:23d1f73bf130	2874
vladvana	0:23d1f73bf130	2875	/***************** Bit definition for TIM_CCR4 register ****************/
vladvana	0:23d1f73bf130	2876	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
vladvana	0:23d1f73bf130	2877
vladvana	0:23d1f73bf130	2878	/***************** Bit definition for TIM_BDTR register ****************/
vladvana	0:23d1f73bf130	2879	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
vladvana	0:23d1f73bf130	2880	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
vladvana	0:23d1f73bf130	2881	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
vladvana	0:23d1f73bf130	2882	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
vladvana	0:23d1f73bf130	2883	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
vladvana	0:23d1f73bf130	2884	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
vladvana	0:23d1f73bf130	2885	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
vladvana	0:23d1f73bf130	2886	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
vladvana	0:23d1f73bf130	2887	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
vladvana	0:23d1f73bf130	2888
vladvana	0:23d1f73bf130	2889	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
vladvana	0:23d1f73bf130	2890	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
vladvana	0:23d1f73bf130	2891	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
vladvana	0:23d1f73bf130	2892
vladvana	0:23d1f73bf130	2893	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
vladvana	0:23d1f73bf130	2894	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
vladvana	0:23d1f73bf130	2895	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
vladvana	0:23d1f73bf130	2896	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
vladvana	0:23d1f73bf130	2897	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
vladvana	0:23d1f73bf130	2898	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
vladvana	0:23d1f73bf130	2899
vladvana	0:23d1f73bf130	2900	/***************** Bit definition for TIM_DCR register *****************/
vladvana	0:23d1f73bf130	2901	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
vladvana	0:23d1f73bf130	2902	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
vladvana	0:23d1f73bf130	2903	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
vladvana	0:23d1f73bf130	2904	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
vladvana	0:23d1f73bf130	2905	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
vladvana	0:23d1f73bf130	2906	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
vladvana	0:23d1f73bf130	2907
vladvana	0:23d1f73bf130	2908	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
vladvana	0:23d1f73bf130	2909	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
vladvana	0:23d1f73bf130	2910	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
vladvana	0:23d1f73bf130	2911	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
vladvana	0:23d1f73bf130	2912	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
vladvana	0:23d1f73bf130	2913	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
vladvana	0:23d1f73bf130	2914
vladvana	0:23d1f73bf130	2915	/***************** Bit definition for TIM_DMAR register ****************/
vladvana	0:23d1f73bf130	2916	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
vladvana	0:23d1f73bf130	2917
vladvana	0:23d1f73bf130	2918	/***************** Bit definition for TIM_OR register ******************/
vladvana	0:23d1f73bf130	2919
vladvana	0:23d1f73bf130	2920	/******************************************************************************/
vladvana	0:23d1f73bf130	2921	/* */
vladvana	0:23d1f73bf130	2922	/* Real-Time Clock */
vladvana	0:23d1f73bf130	2923	/* */
vladvana	0:23d1f73bf130	2924	/******************************************************************************/
vladvana	0:23d1f73bf130	2925
vladvana	0:23d1f73bf130	2926	/***************** Bit definition for RTC_CRH register ******************/
vladvana	0:23d1f73bf130	2927	#define RTC_CRH_SECIE ((uint32_t)0x00000001) /!< Second Interrupt Enable /
vladvana	0:23d1f73bf130	2928	#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /!< Alarm Interrupt Enable /
vladvana	0:23d1f73bf130	2929	#define RTC_CRH_OWIE ((uint32_t)0x00000004) /!< OverfloW Interrupt Enable /
vladvana	0:23d1f73bf130	2930
vladvana	0:23d1f73bf130	2931	/***************** Bit definition for RTC_CRL register ******************/
vladvana	0:23d1f73bf130	2932	#define RTC_CRL_SECF ((uint32_t)0x00000001) /!< Second Flag /
vladvana	0:23d1f73bf130	2933	#define RTC_CRL_ALRF ((uint32_t)0x00000002) /!< Alarm Flag /
vladvana	0:23d1f73bf130	2934	#define RTC_CRL_OWF ((uint32_t)0x00000004) /!< OverfloW Flag /
vladvana	0:23d1f73bf130	2935	#define RTC_CRL_RSF ((uint32_t)0x00000008) /!< Registers Synchronized Flag /
vladvana	0:23d1f73bf130	2936	#define RTC_CRL_CNF ((uint32_t)0x00000010) /!< Configuration Flag /
vladvana	0:23d1f73bf130	2937	#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /!< RTC operation OFF /
vladvana	0:23d1f73bf130	2938
vladvana	0:23d1f73bf130	2939	/***************** Bit definition for RTC_PRLH register *****************/
vladvana	0:23d1f73bf130	2940	#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /!< RTC Prescaler Reload Value High /
vladvana	0:23d1f73bf130	2941
vladvana	0:23d1f73bf130	2942	/***************** Bit definition for RTC_PRLL register *****************/
vladvana	0:23d1f73bf130	2943	#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /!< RTC Prescaler Reload Value Low /
vladvana	0:23d1f73bf130	2944
vladvana	0:23d1f73bf130	2945	/***************** Bit definition for RTC_DIVH register *****************/
vladvana	0:23d1f73bf130	2946	#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /!< RTC Clock Divider High /
vladvana	0:23d1f73bf130	2947
vladvana	0:23d1f73bf130	2948	/***************** Bit definition for RTC_DIVL register *****************/
vladvana	0:23d1f73bf130	2949	#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /!< RTC Clock Divider Low /
vladvana	0:23d1f73bf130	2950
vladvana	0:23d1f73bf130	2951	/***************** Bit definition for RTC_CNTH register *****************/
vladvana	0:23d1f73bf130	2952	#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter High /
vladvana	0:23d1f73bf130	2953
vladvana	0:23d1f73bf130	2954	/***************** Bit definition for RTC_CNTL register *****************/
vladvana	0:23d1f73bf130	2955	#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter Low /
vladvana	0:23d1f73bf130	2956
vladvana	0:23d1f73bf130	2957	/***************** Bit definition for RTC_ALRH register *****************/
vladvana	0:23d1f73bf130	2958	#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm High /
vladvana	0:23d1f73bf130	2959
vladvana	0:23d1f73bf130	2960	/***************** Bit definition for RTC_ALRL register *****************/
vladvana	0:23d1f73bf130	2961	#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm Low /
vladvana	0:23d1f73bf130	2962
vladvana	0:23d1f73bf130	2963	/******************************************************************************/
vladvana	0:23d1f73bf130	2964	/* */
vladvana	0:23d1f73bf130	2965	/* Independent WATCHDOG (IWDG) */
vladvana	0:23d1f73bf130	2966	/* */
vladvana	0:23d1f73bf130	2967	/******************************************************************************/
vladvana	0:23d1f73bf130	2968
vladvana	0:23d1f73bf130	2969	/***************** Bit definition for IWDG_KR register ******************/
vladvana	0:23d1f73bf130	2970	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
vladvana	0:23d1f73bf130	2971
vladvana	0:23d1f73bf130	2972	/***************** Bit definition for IWDG_PR register ******************/
vladvana	0:23d1f73bf130	2973	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
vladvana	0:23d1f73bf130	2974	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2975	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2976	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2977
vladvana	0:23d1f73bf130	2978	/***************** Bit definition for IWDG_RLR register *****************/
vladvana	0:23d1f73bf130	2979	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
vladvana	0:23d1f73bf130	2980
vladvana	0:23d1f73bf130	2981	/***************** Bit definition for IWDG_SR register ******************/
vladvana	0:23d1f73bf130	2982	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
vladvana	0:23d1f73bf130	2983	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
vladvana	0:23d1f73bf130	2984
vladvana	0:23d1f73bf130	2985	/******************************************************************************/
vladvana	0:23d1f73bf130	2986	/* */
vladvana	0:23d1f73bf130	2987	/* Window WATCHDOG */
vladvana	0:23d1f73bf130	2988	/* */
vladvana	0:23d1f73bf130	2989	/******************************************************************************/
vladvana	0:23d1f73bf130	2990
vladvana	0:23d1f73bf130	2991	/***************** Bit definition for WWDG_CR register ******************/
vladvana	0:23d1f73bf130	2992	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
vladvana	0:23d1f73bf130	2993	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	2994	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	2995	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	2996	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	2997	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	2998	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
vladvana	0:23d1f73bf130	2999	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
vladvana	0:23d1f73bf130	3000
vladvana	0:23d1f73bf130	3001	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
vladvana	0:23d1f73bf130	3002
vladvana	0:23d1f73bf130	3003	/***************** Bit definition for WWDG_CFR register *****************/
vladvana	0:23d1f73bf130	3004	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
vladvana	0:23d1f73bf130	3005	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	3006	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	3007	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	3008	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	3009	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	3010	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
vladvana	0:23d1f73bf130	3011	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
vladvana	0:23d1f73bf130	3012
vladvana	0:23d1f73bf130	3013	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
vladvana	0:23d1f73bf130	3014	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
vladvana	0:23d1f73bf130	3015	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
vladvana	0:23d1f73bf130	3016
vladvana	0:23d1f73bf130	3017	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
vladvana	0:23d1f73bf130	3018
vladvana	0:23d1f73bf130	3019	/***************** Bit definition for WWDG_SR register ******************/
vladvana	0:23d1f73bf130	3020	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
vladvana	0:23d1f73bf130	3021
vladvana	0:23d1f73bf130	3022
vladvana	0:23d1f73bf130	3023	/******************************************************************************/
vladvana	0:23d1f73bf130	3024	/* */
vladvana	0:23d1f73bf130	3025	/* SD host Interface */
vladvana	0:23d1f73bf130	3026	/* */
vladvana	0:23d1f73bf130	3027	/******************************************************************************/
vladvana	0:23d1f73bf130	3028
vladvana	0:23d1f73bf130	3029	/**************** Bit definition for SDIO_POWER register ****************/
vladvana	0:23d1f73bf130	3030	#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
vladvana	0:23d1f73bf130	3031	#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /!< Bit 0 /
vladvana	0:23d1f73bf130	3032	#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /!< Bit 1 /
vladvana	0:23d1f73bf130	3033
vladvana	0:23d1f73bf130	3034	/**************** Bit definition for SDIO_CLKCR register ****************/
vladvana	0:23d1f73bf130	3035	#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /!< Clock divide factor /
vladvana	0:23d1f73bf130	3036	#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /!< Clock enable bit /
vladvana	0:23d1f73bf130	3037	#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /!< Power saving configuration bit /
vladvana	0:23d1f73bf130	3038	#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /!< Clock divider bypass enable bit /
vladvana	0:23d1f73bf130	3039
vladvana	0:23d1f73bf130	3040	#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
vladvana	0:23d1f73bf130	3041	#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!< Bit 0 /
vladvana	0:23d1f73bf130	3042	#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3043
vladvana	0:23d1f73bf130	3044	#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /!< SDIO_CK dephasing selection bit /
vladvana	0:23d1f73bf130	3045	#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /!< HW Flow Control enable /
vladvana	0:23d1f73bf130	3046
vladvana	0:23d1f73bf130	3047	/***************** Bit definition for SDIO_ARG register *****************/
vladvana	0:23d1f73bf130	3048	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
vladvana	0:23d1f73bf130	3049
vladvana	0:23d1f73bf130	3050	/***************** Bit definition for SDIO_CMD register *****************/
vladvana	0:23d1f73bf130	3051	#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /!< Command Index /
vladvana	0:23d1f73bf130	3052
vladvana	0:23d1f73bf130	3053	#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
vladvana	0:23d1f73bf130	3054	#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
vladvana	0:23d1f73bf130	3055	#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
vladvana	0:23d1f73bf130	3056
vladvana	0:23d1f73bf130	3057	#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /!< CPSM Waits for Interrupt Request /
vladvana	0:23d1f73bf130	3058	#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
vladvana	0:23d1f73bf130	3059	#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
vladvana	0:23d1f73bf130	3060	#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!< SD I/O suspend command /
vladvana	0:23d1f73bf130	3061	#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /!< Enable CMD completion /
vladvana	0:23d1f73bf130	3062	#define SDIO_CMD_NIEN ((uint32_t)0x2000) /!< Not Interrupt Enable /
vladvana	0:23d1f73bf130	3063	#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /!< CE-ATA command /
vladvana	0:23d1f73bf130	3064
vladvana	0:23d1f73bf130	3065	/*************** Bit definition for SDIO_RESPCMD register ***************/
vladvana	0:23d1f73bf130	3066	#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /!< Response command index /
vladvana	0:23d1f73bf130	3067
vladvana	0:23d1f73bf130	3068	/**************** Bit definition for SDIO_RESP0 register ****************/
vladvana	0:23d1f73bf130	3069	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
vladvana	0:23d1f73bf130	3070
vladvana	0:23d1f73bf130	3071	/**************** Bit definition for SDIO_RESP1 register ****************/
vladvana	0:23d1f73bf130	3072	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
vladvana	0:23d1f73bf130	3073
vladvana	0:23d1f73bf130	3074	/**************** Bit definition for SDIO_RESP2 register ****************/
vladvana	0:23d1f73bf130	3075	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
vladvana	0:23d1f73bf130	3076
vladvana	0:23d1f73bf130	3077	/**************** Bit definition for SDIO_RESP3 register ****************/
vladvana	0:23d1f73bf130	3078	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
vladvana	0:23d1f73bf130	3079
vladvana	0:23d1f73bf130	3080	/**************** Bit definition for SDIO_RESP4 register ****************/
vladvana	0:23d1f73bf130	3081	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
vladvana	0:23d1f73bf130	3082
vladvana	0:23d1f73bf130	3083	/**************** Bit definition for SDIO_DTIMER register ***************/
vladvana	0:23d1f73bf130	3084	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
vladvana	0:23d1f73bf130	3085
vladvana	0:23d1f73bf130	3086	/**************** Bit definition for SDIO_DLEN register *****************/
vladvana	0:23d1f73bf130	3087	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
vladvana	0:23d1f73bf130	3088
vladvana	0:23d1f73bf130	3089	/**************** Bit definition for SDIO_DCTRL register ****************/
vladvana	0:23d1f73bf130	3090	#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /!< Data transfer enabled bit /
vladvana	0:23d1f73bf130	3091	#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /!< Data transfer direction selection /
vladvana	0:23d1f73bf130	3092	#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /!< Data transfer mode selection /
vladvana	0:23d1f73bf130	3093	#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /!< DMA enabled bit /
vladvana	0:23d1f73bf130	3094
vladvana	0:23d1f73bf130	3095	#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
vladvana	0:23d1f73bf130	3096	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3097	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3098	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!< Bit 2 /
vladvana	0:23d1f73bf130	3099	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!< Bit 3 /
vladvana	0:23d1f73bf130	3100
vladvana	0:23d1f73bf130	3101	#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /!< Read wait start /
vladvana	0:23d1f73bf130	3102	#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /!< Read wait stop /
vladvana	0:23d1f73bf130	3103	#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /!< Read wait mode /
vladvana	0:23d1f73bf130	3104	#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /!< SD I/O enable functions /
vladvana	0:23d1f73bf130	3105
vladvana	0:23d1f73bf130	3106	/**************** Bit definition for SDIO_DCOUNT register ***************/
vladvana	0:23d1f73bf130	3107	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
vladvana	0:23d1f73bf130	3108
vladvana	0:23d1f73bf130	3109	/**************** Bit definition for SDIO_STA register ******************/
vladvana	0:23d1f73bf130	3110	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
vladvana	0:23d1f73bf130	3111	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
vladvana	0:23d1f73bf130	3112	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
vladvana	0:23d1f73bf130	3113	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
vladvana	0:23d1f73bf130	3114	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
vladvana	0:23d1f73bf130	3115	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
vladvana	0:23d1f73bf130	3116	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
vladvana	0:23d1f73bf130	3117	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
vladvana	0:23d1f73bf130	3118	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
vladvana	0:23d1f73bf130	3119	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
vladvana	0:23d1f73bf130	3120	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
vladvana	0:23d1f73bf130	3121	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
vladvana	0:23d1f73bf130	3122	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
vladvana	0:23d1f73bf130	3123	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
vladvana	0:23d1f73bf130	3124	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
vladvana	0:23d1f73bf130	3125	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
vladvana	0:23d1f73bf130	3126	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
vladvana	0:23d1f73bf130	3127	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
vladvana	0:23d1f73bf130	3128	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
vladvana	0:23d1f73bf130	3129	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
vladvana	0:23d1f73bf130	3130	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
vladvana	0:23d1f73bf130	3131	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
vladvana	0:23d1f73bf130	3132	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
vladvana	0:23d1f73bf130	3133	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
vladvana	0:23d1f73bf130	3134
vladvana	0:23d1f73bf130	3135	/***************** Bit definition for SDIO_ICR register *****************/
vladvana	0:23d1f73bf130	3136	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
vladvana	0:23d1f73bf130	3137	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
vladvana	0:23d1f73bf130	3138	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
vladvana	0:23d1f73bf130	3139	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
vladvana	0:23d1f73bf130	3140	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
vladvana	0:23d1f73bf130	3141	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
vladvana	0:23d1f73bf130	3142	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
vladvana	0:23d1f73bf130	3143	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
vladvana	0:23d1f73bf130	3144	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
vladvana	0:23d1f73bf130	3145	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
vladvana	0:23d1f73bf130	3146	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
vladvana	0:23d1f73bf130	3147	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
vladvana	0:23d1f73bf130	3148	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
vladvana	0:23d1f73bf130	3149
vladvana	0:23d1f73bf130	3150	/**************** Bit definition for SDIO_MASK register *****************/
vladvana	0:23d1f73bf130	3151	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
vladvana	0:23d1f73bf130	3152	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
vladvana	0:23d1f73bf130	3153	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
vladvana	0:23d1f73bf130	3154	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
vladvana	0:23d1f73bf130	3155	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
vladvana	0:23d1f73bf130	3156	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
vladvana	0:23d1f73bf130	3157	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
vladvana	0:23d1f73bf130	3158	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
vladvana	0:23d1f73bf130	3159	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
vladvana	0:23d1f73bf130	3160	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
vladvana	0:23d1f73bf130	3161	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
vladvana	0:23d1f73bf130	3162	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
vladvana	0:23d1f73bf130	3163	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
vladvana	0:23d1f73bf130	3164	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
vladvana	0:23d1f73bf130	3165	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
vladvana	0:23d1f73bf130	3166	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
vladvana	0:23d1f73bf130	3167	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
vladvana	0:23d1f73bf130	3168	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
vladvana	0:23d1f73bf130	3169	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
vladvana	0:23d1f73bf130	3170	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
vladvana	0:23d1f73bf130	3171	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
vladvana	0:23d1f73bf130	3172	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
vladvana	0:23d1f73bf130	3173	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
vladvana	0:23d1f73bf130	3174	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
vladvana	0:23d1f73bf130	3175
vladvana	0:23d1f73bf130	3176	/*************** Bit definition for SDIO_FIFOCNT register ***************/
vladvana	0:23d1f73bf130	3177	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
vladvana	0:23d1f73bf130	3178
vladvana	0:23d1f73bf130	3179	/**************** Bit definition for SDIO_FIFO register *****************/
vladvana	0:23d1f73bf130	3180	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
vladvana	0:23d1f73bf130	3181
vladvana	0:23d1f73bf130	3182	/******************************************************************************/
vladvana	0:23d1f73bf130	3183	/* */
vladvana	0:23d1f73bf130	3184	/* USB Device FS */
vladvana	0:23d1f73bf130	3185	/* */
vladvana	0:23d1f73bf130	3186	/******************************************************************************/
vladvana	0:23d1f73bf130	3187
vladvana	0:23d1f73bf130	3188	/!< Endpoint-specific registers /
vladvana	0:23d1f73bf130	3189	#define USB_EP0R USB_BASE /!< Endpoint 0 register address /
vladvana	0:23d1f73bf130	3190	#define USB_EP1R (USB_BASE + 0x00000004) /!< Endpoint 1 register address /
vladvana	0:23d1f73bf130	3191	#define USB_EP2R (USB_BASE + 0x00000008) /!< Endpoint 2 register address /
vladvana	0:23d1f73bf130	3192	#define USB_EP3R (USB_BASE + 0x0000000C) /!< Endpoint 3 register address /
vladvana	0:23d1f73bf130	3193	#define USB_EP4R (USB_BASE + 0x00000010) /!< Endpoint 4 register address /
vladvana	0:23d1f73bf130	3194	#define USB_EP5R (USB_BASE + 0x00000014) /!< Endpoint 5 register address /
vladvana	0:23d1f73bf130	3195	#define USB_EP6R (USB_BASE + 0x00000018) /!< Endpoint 6 register address /
vladvana	0:23d1f73bf130	3196	#define USB_EP7R (USB_BASE + 0x0000001C) /!< Endpoint 7 register address /
vladvana	0:23d1f73bf130	3197
vladvana	0:23d1f73bf130	3198	/* bit positions */
vladvana	0:23d1f73bf130	3199	#define USB_EP_CTR_RX ((uint32_t)0x00008000) /!< EndPoint Correct TRansfer RX /
vladvana	0:23d1f73bf130	3200	#define USB_EP_DTOG_RX ((uint32_t)0x00004000) /!< EndPoint Data TOGGLE RX /
vladvana	0:23d1f73bf130	3201	#define USB_EPRX_STAT ((uint32_t)0x00003000) /!< EndPoint RX STATus bit field /
vladvana	0:23d1f73bf130	3202	#define USB_EP_SETUP ((uint32_t)0x00000800) /!< EndPoint SETUP /
vladvana	0:23d1f73bf130	3203	#define USB_EP_T_FIELD ((uint32_t)0x00000600) /!< EndPoint TYPE /
vladvana	0:23d1f73bf130	3204	#define USB_EP_KIND ((uint32_t)0x00000100) /!< EndPoint KIND /
vladvana	0:23d1f73bf130	3205	#define USB_EP_CTR_TX ((uint32_t)0x00000080) /!< EndPoint Correct TRansfer TX /
vladvana	0:23d1f73bf130	3206	#define USB_EP_DTOG_TX ((uint32_t)0x00000040) /!< EndPoint Data TOGGLE TX /
vladvana	0:23d1f73bf130	3207	#define USB_EPTX_STAT ((uint32_t)0x00000030) /!< EndPoint TX STATus bit field /
vladvana	0:23d1f73bf130	3208	#define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /!< EndPoint ADDRess FIELD /
vladvana	0:23d1f73bf130	3209
vladvana	0:23d1f73bf130	3210	/* EndPoint REGister MASK (no toggle fields) */
vladvana	0:23d1f73bf130	3211	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
vladvana	0:23d1f73bf130	3212	/!< EP_TYPE[1:0] EndPoint TYPE /
vladvana	0:23d1f73bf130	3213	#define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /!< EndPoint TYPE Mask /
vladvana	0:23d1f73bf130	3214	#define USB_EP_BULK ((uint32_t)0x00000000) /!< EndPoint BULK /
vladvana	0:23d1f73bf130	3215	#define USB_EP_CONTROL ((uint32_t)0x00000200) /!< EndPoint CONTROL /
vladvana	0:23d1f73bf130	3216	#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /!< EndPoint ISOCHRONOUS /
vladvana	0:23d1f73bf130	3217	#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /!< EndPoint INTERRUPT /
vladvana	0:23d1f73bf130	3218	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
vladvana	0:23d1f73bf130	3219
vladvana	0:23d1f73bf130	3220	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
vladvana	0:23d1f73bf130	3221	/!< STAT_TX[1:0] STATus for TX transfer /
vladvana	0:23d1f73bf130	3222	#define USB_EP_TX_DIS ((uint32_t)0x00000000) /!< EndPoint TX DISabled /
vladvana	0:23d1f73bf130	3223	#define USB_EP_TX_STALL ((uint32_t)0x00000010) /!< EndPoint TX STALLed /
vladvana	0:23d1f73bf130	3224	#define USB_EP_TX_NAK ((uint32_t)0x00000020) /!< EndPoint TX NAKed /
vladvana	0:23d1f73bf130	3225	#define USB_EP_TX_VALID ((uint32_t)0x00000030) /!< EndPoint TX VALID /
vladvana	0:23d1f73bf130	3226	#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /!< EndPoint TX Data TOGgle bit1 /
vladvana	0:23d1f73bf130	3227	#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /!< EndPoint TX Data TOGgle bit2 /
vladvana	0:23d1f73bf130	3228	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
vladvana	0:23d1f73bf130	3229	/!< STAT_RX[1:0] STATus for RX transfer /
vladvana	0:23d1f73bf130	3230	#define USB_EP_RX_DIS ((uint32_t)0x00000000) /!< EndPoint RX DISabled /
vladvana	0:23d1f73bf130	3231	#define USB_EP_RX_STALL ((uint32_t)0x00001000) /!< EndPoint RX STALLed /
vladvana	0:23d1f73bf130	3232	#define USB_EP_RX_NAK ((uint32_t)0x00002000) /!< EndPoint RX NAKed /
vladvana	0:23d1f73bf130	3233	#define USB_EP_RX_VALID ((uint32_t)0x00003000) /!< EndPoint RX VALID /
vladvana	0:23d1f73bf130	3234	#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /!< EndPoint RX Data TOGgle bit1 /
vladvana	0:23d1f73bf130	3235	#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /!< EndPoint RX Data TOGgle bit1 /
vladvana	0:23d1f73bf130	3236	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
vladvana	0:23d1f73bf130	3237
vladvana	0:23d1f73bf130	3238	/***************** Bit definition for USB_EP0R register *****************/
vladvana	0:23d1f73bf130	3239	#define USB_EP0R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
vladvana	0:23d1f73bf130	3240
vladvana	0:23d1f73bf130	3241	#define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
vladvana	0:23d1f73bf130	3242	#define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3243	#define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3244
vladvana	0:23d1f73bf130	3245	#define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
vladvana	0:23d1f73bf130	3246	#define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
vladvana	0:23d1f73bf130	3247	#define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
vladvana	0:23d1f73bf130	3248
vladvana	0:23d1f73bf130	3249	#define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
vladvana	0:23d1f73bf130	3250	#define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	3251	#define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	3252
vladvana	0:23d1f73bf130	3253	#define USB_EP0R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
vladvana	0:23d1f73bf130	3254
vladvana	0:23d1f73bf130	3255	#define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
vladvana	0:23d1f73bf130	3256	#define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3257	#define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3258
vladvana	0:23d1f73bf130	3259	#define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
vladvana	0:23d1f73bf130	3260	#define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
vladvana	0:23d1f73bf130	3261
vladvana	0:23d1f73bf130	3262	/***************** Bit definition for USB_EP1R register *****************/
vladvana	0:23d1f73bf130	3263	#define USB_EP1R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
vladvana	0:23d1f73bf130	3264
vladvana	0:23d1f73bf130	3265	#define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
vladvana	0:23d1f73bf130	3266	#define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3267	#define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3268
vladvana	0:23d1f73bf130	3269	#define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
vladvana	0:23d1f73bf130	3270	#define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
vladvana	0:23d1f73bf130	3271	#define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
vladvana	0:23d1f73bf130	3272
vladvana	0:23d1f73bf130	3273	#define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
vladvana	0:23d1f73bf130	3274	#define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	3275	#define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	3276
vladvana	0:23d1f73bf130	3277	#define USB_EP1R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
vladvana	0:23d1f73bf130	3278
vladvana	0:23d1f73bf130	3279	#define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
vladvana	0:23d1f73bf130	3280	#define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3281	#define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3282
vladvana	0:23d1f73bf130	3283	#define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
vladvana	0:23d1f73bf130	3284	#define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
vladvana	0:23d1f73bf130	3285
vladvana	0:23d1f73bf130	3286	/***************** Bit definition for USB_EP2R register *****************/
vladvana	0:23d1f73bf130	3287	#define USB_EP2R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
vladvana	0:23d1f73bf130	3288
vladvana	0:23d1f73bf130	3289	#define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
vladvana	0:23d1f73bf130	3290	#define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3291	#define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3292
vladvana	0:23d1f73bf130	3293	#define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
vladvana	0:23d1f73bf130	3294	#define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
vladvana	0:23d1f73bf130	3295	#define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
vladvana	0:23d1f73bf130	3296
vladvana	0:23d1f73bf130	3297	#define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
vladvana	0:23d1f73bf130	3298	#define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	3299	#define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	3300
vladvana	0:23d1f73bf130	3301	#define USB_EP2R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
vladvana	0:23d1f73bf130	3302
vladvana	0:23d1f73bf130	3303	#define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
vladvana	0:23d1f73bf130	3304	#define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3305	#define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3306
vladvana	0:23d1f73bf130	3307	#define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
vladvana	0:23d1f73bf130	3308	#define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
vladvana	0:23d1f73bf130	3309
vladvana	0:23d1f73bf130	3310	/***************** Bit definition for USB_EP3R register *****************/
vladvana	0:23d1f73bf130	3311	#define USB_EP3R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
vladvana	0:23d1f73bf130	3312
vladvana	0:23d1f73bf130	3313	#define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
vladvana	0:23d1f73bf130	3314	#define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3315	#define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3316
vladvana	0:23d1f73bf130	3317	#define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
vladvana	0:23d1f73bf130	3318	#define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
vladvana	0:23d1f73bf130	3319	#define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
vladvana	0:23d1f73bf130	3320
vladvana	0:23d1f73bf130	3321	#define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
vladvana	0:23d1f73bf130	3322	#define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	3323	#define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	3324
vladvana	0:23d1f73bf130	3325	#define USB_EP3R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
vladvana	0:23d1f73bf130	3326
vladvana	0:23d1f73bf130	3327	#define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
vladvana	0:23d1f73bf130	3328	#define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3329	#define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3330
vladvana	0:23d1f73bf130	3331	#define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
vladvana	0:23d1f73bf130	3332	#define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
vladvana	0:23d1f73bf130	3333
vladvana	0:23d1f73bf130	3334	/***************** Bit definition for USB_EP4R register *****************/
vladvana	0:23d1f73bf130	3335	#define USB_EP4R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
vladvana	0:23d1f73bf130	3336
vladvana	0:23d1f73bf130	3337	#define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
vladvana	0:23d1f73bf130	3338	#define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3339	#define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3340
vladvana	0:23d1f73bf130	3341	#define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
vladvana	0:23d1f73bf130	3342	#define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
vladvana	0:23d1f73bf130	3343	#define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
vladvana	0:23d1f73bf130	3344
vladvana	0:23d1f73bf130	3345	#define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
vladvana	0:23d1f73bf130	3346	#define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	3347	#define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	3348
vladvana	0:23d1f73bf130	3349	#define USB_EP4R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
vladvana	0:23d1f73bf130	3350
vladvana	0:23d1f73bf130	3351	#define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
vladvana	0:23d1f73bf130	3352	#define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3353	#define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3354
vladvana	0:23d1f73bf130	3355	#define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
vladvana	0:23d1f73bf130	3356	#define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
vladvana	0:23d1f73bf130	3357
vladvana	0:23d1f73bf130	3358	/***************** Bit definition for USB_EP5R register *****************/
vladvana	0:23d1f73bf130	3359	#define USB_EP5R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
vladvana	0:23d1f73bf130	3360
vladvana	0:23d1f73bf130	3361	#define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
vladvana	0:23d1f73bf130	3362	#define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3363	#define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3364
vladvana	0:23d1f73bf130	3365	#define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
vladvana	0:23d1f73bf130	3366	#define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
vladvana	0:23d1f73bf130	3367	#define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
vladvana	0:23d1f73bf130	3368
vladvana	0:23d1f73bf130	3369	#define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
vladvana	0:23d1f73bf130	3370	#define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	3371	#define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	3372
vladvana	0:23d1f73bf130	3373	#define USB_EP5R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
vladvana	0:23d1f73bf130	3374
vladvana	0:23d1f73bf130	3375	#define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
vladvana	0:23d1f73bf130	3376	#define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3377	#define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3378
vladvana	0:23d1f73bf130	3379	#define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
vladvana	0:23d1f73bf130	3380	#define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
vladvana	0:23d1f73bf130	3381
vladvana	0:23d1f73bf130	3382	/***************** Bit definition for USB_EP6R register *****************/
vladvana	0:23d1f73bf130	3383	#define USB_EP6R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
vladvana	0:23d1f73bf130	3384
vladvana	0:23d1f73bf130	3385	#define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
vladvana	0:23d1f73bf130	3386	#define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3387	#define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3388
vladvana	0:23d1f73bf130	3389	#define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
vladvana	0:23d1f73bf130	3390	#define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
vladvana	0:23d1f73bf130	3391	#define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
vladvana	0:23d1f73bf130	3392
vladvana	0:23d1f73bf130	3393	#define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
vladvana	0:23d1f73bf130	3394	#define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	3395	#define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	3396
vladvana	0:23d1f73bf130	3397	#define USB_EP6R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
vladvana	0:23d1f73bf130	3398
vladvana	0:23d1f73bf130	3399	#define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
vladvana	0:23d1f73bf130	3400	#define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3401	#define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3402
vladvana	0:23d1f73bf130	3403	#define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
vladvana	0:23d1f73bf130	3404	#define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
vladvana	0:23d1f73bf130	3405
vladvana	0:23d1f73bf130	3406	/***************** Bit definition for USB_EP7R register *****************/
vladvana	0:23d1f73bf130	3407	#define USB_EP7R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
vladvana	0:23d1f73bf130	3408
vladvana	0:23d1f73bf130	3409	#define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
vladvana	0:23d1f73bf130	3410	#define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3411	#define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3412
vladvana	0:23d1f73bf130	3413	#define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
vladvana	0:23d1f73bf130	3414	#define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
vladvana	0:23d1f73bf130	3415	#define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
vladvana	0:23d1f73bf130	3416
vladvana	0:23d1f73bf130	3417	#define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
vladvana	0:23d1f73bf130	3418	#define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
vladvana	0:23d1f73bf130	3419	#define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
vladvana	0:23d1f73bf130	3420
vladvana	0:23d1f73bf130	3421	#define USB_EP7R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
vladvana	0:23d1f73bf130	3422
vladvana	0:23d1f73bf130	3423	#define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
vladvana	0:23d1f73bf130	3424	#define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3425	#define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3426
vladvana	0:23d1f73bf130	3427	#define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
vladvana	0:23d1f73bf130	3428	#define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
vladvana	0:23d1f73bf130	3429
vladvana	0:23d1f73bf130	3430	/!< Common registers /
vladvana	0:23d1f73bf130	3431	/***************** Bit definition for USB_CNTR register *****************/
vladvana	0:23d1f73bf130	3432	#define USB_CNTR_FRES ((uint32_t)0x00000001) /!< Force USB Reset /
vladvana	0:23d1f73bf130	3433	#define USB_CNTR_PDWN ((uint32_t)0x00000002) /!< Power down /
vladvana	0:23d1f73bf130	3434	#define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /!< Low-power mode /
vladvana	0:23d1f73bf130	3435	#define USB_CNTR_FSUSP ((uint32_t)0x00000008) /!< Force suspend /
vladvana	0:23d1f73bf130	3436	#define USB_CNTR_RESUME ((uint32_t)0x00000010) /!< Resume request /
vladvana	0:23d1f73bf130	3437	#define USB_CNTR_ESOFM ((uint32_t)0x00000100) /!< Expected Start Of Frame Interrupt Mask /
vladvana	0:23d1f73bf130	3438	#define USB_CNTR_SOFM ((uint32_t)0x00000200) /!< Start Of Frame Interrupt Mask /
vladvana	0:23d1f73bf130	3439	#define USB_CNTR_RESETM ((uint32_t)0x00000400) /!< RESET Interrupt Mask /
vladvana	0:23d1f73bf130	3440	#define USB_CNTR_SUSPM ((uint32_t)0x00000800) /!< Suspend mode Interrupt Mask /
vladvana	0:23d1f73bf130	3441	#define USB_CNTR_WKUPM ((uint32_t)0x00001000) /!< Wakeup Interrupt Mask /
vladvana	0:23d1f73bf130	3442	#define USB_CNTR_ERRM ((uint32_t)0x00002000) /!< Error Interrupt Mask /
vladvana	0:23d1f73bf130	3443	#define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /!< Packet Memory Area Over / Underrun Interrupt Mask /
vladvana	0:23d1f73bf130	3444	#define USB_CNTR_CTRM ((uint32_t)0x00008000) /!< Correct Transfer Interrupt Mask /
vladvana	0:23d1f73bf130	3445
vladvana	0:23d1f73bf130	3446	/***************** Bit definition for USB_ISTR register *****************/
vladvana	0:23d1f73bf130	3447	#define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /!< Endpoint Identifier /
vladvana	0:23d1f73bf130	3448	#define USB_ISTR_DIR ((uint32_t)0x00000010) /!< Direction of transaction /
vladvana	0:23d1f73bf130	3449	#define USB_ISTR_ESOF ((uint32_t)0x00000100) /!< Expected Start Of Frame /
vladvana	0:23d1f73bf130	3450	#define USB_ISTR_SOF ((uint32_t)0x00000200) /!< Start Of Frame /
vladvana	0:23d1f73bf130	3451	#define USB_ISTR_RESET ((uint32_t)0x00000400) /!< USB RESET request /
vladvana	0:23d1f73bf130	3452	#define USB_ISTR_SUSP ((uint32_t)0x00000800) /!< Suspend mode request /
vladvana	0:23d1f73bf130	3453	#define USB_ISTR_WKUP ((uint32_t)0x00001000) /!< Wake up /
vladvana	0:23d1f73bf130	3454	#define USB_ISTR_ERR ((uint32_t)0x00002000) /!< Error /
vladvana	0:23d1f73bf130	3455	#define USB_ISTR_PMAOVR ((uint32_t)0x00004000) /!< Packet Memory Area Over / Underrun /
vladvana	0:23d1f73bf130	3456	#define USB_ISTR_CTR ((uint32_t)0x00008000) /!< Correct Transfer /
vladvana	0:23d1f73bf130	3457
vladvana	0:23d1f73bf130	3458	/***************** Bit definition for USB_FNR register ******************/
vladvana	0:23d1f73bf130	3459	#define USB_FNR_FN ((uint32_t)0x000007FF) /!< Frame Number /
vladvana	0:23d1f73bf130	3460	#define USB_FNR_LSOF ((uint32_t)0x00001800) /!< Lost SOF /
vladvana	0:23d1f73bf130	3461	#define USB_FNR_LCK ((uint32_t)0x00002000) /!< Locked /
vladvana	0:23d1f73bf130	3462	#define USB_FNR_RXDM ((uint32_t)0x00004000) /!< Receive Data - Line Status /
vladvana	0:23d1f73bf130	3463	#define USB_FNR_RXDP ((uint32_t)0x00008000) /!< Receive Data + Line Status /
vladvana	0:23d1f73bf130	3464
vladvana	0:23d1f73bf130	3465	/**************** Bit definition for USB_DADDR register *****************/
vladvana	0:23d1f73bf130	3466	#define USB_DADDR_ADD ((uint32_t)0x0000007F) /!< ADD[6:0] bits (Device Address) /
vladvana	0:23d1f73bf130	3467	#define USB_DADDR_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	3468	#define USB_DADDR_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	3469	#define USB_DADDR_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	3470	#define USB_DADDR_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	3471	#define USB_DADDR_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	3472	#define USB_DADDR_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
vladvana	0:23d1f73bf130	3473	#define USB_DADDR_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
vladvana	0:23d1f73bf130	3474
vladvana	0:23d1f73bf130	3475	#define USB_DADDR_EF ((uint32_t)0x00000080) /!< Enable Function /
vladvana	0:23d1f73bf130	3476
vladvana	0:23d1f73bf130	3477	/**************** Bit definition for USB_BTABLE register ****************/
vladvana	0:23d1f73bf130	3478	#define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /!< Buffer Table /
vladvana	0:23d1f73bf130	3479
vladvana	0:23d1f73bf130	3480	/!< Buffer descriptor table /
vladvana	0:23d1f73bf130	3481	/*************** Bit definition for USB_ADDR0_TX register ***************/
vladvana	0:23d1f73bf130	3482	#define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 0 /
vladvana	0:23d1f73bf130	3483
vladvana	0:23d1f73bf130	3484	/*************** Bit definition for USB_ADDR1_TX register ***************/
vladvana	0:23d1f73bf130	3485	#define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 1 /
vladvana	0:23d1f73bf130	3486
vladvana	0:23d1f73bf130	3487	/*************** Bit definition for USB_ADDR2_TX register ***************/
vladvana	0:23d1f73bf130	3488	#define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 2 /
vladvana	0:23d1f73bf130	3489
vladvana	0:23d1f73bf130	3490	/*************** Bit definition for USB_ADDR3_TX register ***************/
vladvana	0:23d1f73bf130	3491	#define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 3 /
vladvana	0:23d1f73bf130	3492
vladvana	0:23d1f73bf130	3493	/*************** Bit definition for USB_ADDR4_TX register ***************/
vladvana	0:23d1f73bf130	3494	#define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 4 /
vladvana	0:23d1f73bf130	3495
vladvana	0:23d1f73bf130	3496	/*************** Bit definition for USB_ADDR5_TX register ***************/
vladvana	0:23d1f73bf130	3497	#define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 5 /
vladvana	0:23d1f73bf130	3498
vladvana	0:23d1f73bf130	3499	/*************** Bit definition for USB_ADDR6_TX register ***************/
vladvana	0:23d1f73bf130	3500	#define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 6 /
vladvana	0:23d1f73bf130	3501
vladvana	0:23d1f73bf130	3502	/*************** Bit definition for USB_ADDR7_TX register ***************/
vladvana	0:23d1f73bf130	3503	#define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 7 /
vladvana	0:23d1f73bf130	3504
vladvana	0:23d1f73bf130	3505	/----------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	3506
vladvana	0:23d1f73bf130	3507	/*************** Bit definition for USB_COUNT0_TX register **************/
vladvana	0:23d1f73bf130	3508	#define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 /
vladvana	0:23d1f73bf130	3509
vladvana	0:23d1f73bf130	3510	/*************** Bit definition for USB_COUNT1_TX register **************/
vladvana	0:23d1f73bf130	3511	#define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 /
vladvana	0:23d1f73bf130	3512
vladvana	0:23d1f73bf130	3513	/*************** Bit definition for USB_COUNT2_TX register **************/
vladvana	0:23d1f73bf130	3514	#define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 /
vladvana	0:23d1f73bf130	3515
vladvana	0:23d1f73bf130	3516	/*************** Bit definition for USB_COUNT3_TX register **************/
vladvana	0:23d1f73bf130	3517	#define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 /
vladvana	0:23d1f73bf130	3518
vladvana	0:23d1f73bf130	3519	/*************** Bit definition for USB_COUNT4_TX register **************/
vladvana	0:23d1f73bf130	3520	#define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 /
vladvana	0:23d1f73bf130	3521
vladvana	0:23d1f73bf130	3522	/*************** Bit definition for USB_COUNT5_TX register **************/
vladvana	0:23d1f73bf130	3523	#define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 /
vladvana	0:23d1f73bf130	3524
vladvana	0:23d1f73bf130	3525	/*************** Bit definition for USB_COUNT6_TX register **************/
vladvana	0:23d1f73bf130	3526	#define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 /
vladvana	0:23d1f73bf130	3527
vladvana	0:23d1f73bf130	3528	/*************** Bit definition for USB_COUNT7_TX register **************/
vladvana	0:23d1f73bf130	3529	#define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 /
vladvana	0:23d1f73bf130	3530
vladvana	0:23d1f73bf130	3531	/----------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	3532
vladvana	0:23d1f73bf130	3533	/************** Bit definition for USB_COUNT0_TX_0 register *************/
vladvana	0:23d1f73bf130	3534	#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 (low) /
vladvana	0:23d1f73bf130	3535
vladvana	0:23d1f73bf130	3536	/************** Bit definition for USB_COUNT0_TX_1 register *************/
vladvana	0:23d1f73bf130	3537	#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 0 (high) /
vladvana	0:23d1f73bf130	3538
vladvana	0:23d1f73bf130	3539	/************** Bit definition for USB_COUNT1_TX_0 register *************/
vladvana	0:23d1f73bf130	3540	#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 (low) /
vladvana	0:23d1f73bf130	3541
vladvana	0:23d1f73bf130	3542	/************** Bit definition for USB_COUNT1_TX_1 register *************/
vladvana	0:23d1f73bf130	3543	#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 1 (high) /
vladvana	0:23d1f73bf130	3544
vladvana	0:23d1f73bf130	3545	/************** Bit definition for USB_COUNT2_TX_0 register *************/
vladvana	0:23d1f73bf130	3546	#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 (low) /
vladvana	0:23d1f73bf130	3547
vladvana	0:23d1f73bf130	3548	/************** Bit definition for USB_COUNT2_TX_1 register *************/
vladvana	0:23d1f73bf130	3549	#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 2 (high) /
vladvana	0:23d1f73bf130	3550
vladvana	0:23d1f73bf130	3551	/************** Bit definition for USB_COUNT3_TX_0 register *************/
vladvana	0:23d1f73bf130	3552	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 (low) /
vladvana	0:23d1f73bf130	3553
vladvana	0:23d1f73bf130	3554	/************** Bit definition for USB_COUNT3_TX_1 register *************/
vladvana	0:23d1f73bf130	3555	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 3 (high) /
vladvana	0:23d1f73bf130	3556
vladvana	0:23d1f73bf130	3557	/************** Bit definition for USB_COUNT4_TX_0 register *************/
vladvana	0:23d1f73bf130	3558	#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 (low) /
vladvana	0:23d1f73bf130	3559
vladvana	0:23d1f73bf130	3560	/************** Bit definition for USB_COUNT4_TX_1 register *************/
vladvana	0:23d1f73bf130	3561	#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 4 (high) /
vladvana	0:23d1f73bf130	3562
vladvana	0:23d1f73bf130	3563	/************** Bit definition for USB_COUNT5_TX_0 register *************/
vladvana	0:23d1f73bf130	3564	#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 (low) /
vladvana	0:23d1f73bf130	3565
vladvana	0:23d1f73bf130	3566	/************** Bit definition for USB_COUNT5_TX_1 register *************/
vladvana	0:23d1f73bf130	3567	#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 5 (high) /
vladvana	0:23d1f73bf130	3568
vladvana	0:23d1f73bf130	3569	/************** Bit definition for USB_COUNT6_TX_0 register *************/
vladvana	0:23d1f73bf130	3570	#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 (low) /
vladvana	0:23d1f73bf130	3571
vladvana	0:23d1f73bf130	3572	/************** Bit definition for USB_COUNT6_TX_1 register *************/
vladvana	0:23d1f73bf130	3573	#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 6 (high) /
vladvana	0:23d1f73bf130	3574
vladvana	0:23d1f73bf130	3575	/************** Bit definition for USB_COUNT7_TX_0 register *************/
vladvana	0:23d1f73bf130	3576	#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 (low) /
vladvana	0:23d1f73bf130	3577
vladvana	0:23d1f73bf130	3578	/************** Bit definition for USB_COUNT7_TX_1 register *************/
vladvana	0:23d1f73bf130	3579	#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 7 (high) /
vladvana	0:23d1f73bf130	3580
vladvana	0:23d1f73bf130	3581	/----------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	3582
vladvana	0:23d1f73bf130	3583	/*************** Bit definition for USB_ADDR0_RX register ***************/
vladvana	0:23d1f73bf130	3584	#define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 0 /
vladvana	0:23d1f73bf130	3585
vladvana	0:23d1f73bf130	3586	/*************** Bit definition for USB_ADDR1_RX register ***************/
vladvana	0:23d1f73bf130	3587	#define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 1 /
vladvana	0:23d1f73bf130	3588
vladvana	0:23d1f73bf130	3589	/*************** Bit definition for USB_ADDR2_RX register ***************/
vladvana	0:23d1f73bf130	3590	#define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 2 /
vladvana	0:23d1f73bf130	3591
vladvana	0:23d1f73bf130	3592	/*************** Bit definition for USB_ADDR3_RX register ***************/
vladvana	0:23d1f73bf130	3593	#define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 3 /
vladvana	0:23d1f73bf130	3594
vladvana	0:23d1f73bf130	3595	/*************** Bit definition for USB_ADDR4_RX register ***************/
vladvana	0:23d1f73bf130	3596	#define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 4 /
vladvana	0:23d1f73bf130	3597
vladvana	0:23d1f73bf130	3598	/*************** Bit definition for USB_ADDR5_RX register ***************/
vladvana	0:23d1f73bf130	3599	#define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 5 /
vladvana	0:23d1f73bf130	3600
vladvana	0:23d1f73bf130	3601	/*************** Bit definition for USB_ADDR6_RX register ***************/
vladvana	0:23d1f73bf130	3602	#define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 6 /
vladvana	0:23d1f73bf130	3603
vladvana	0:23d1f73bf130	3604	/*************** Bit definition for USB_ADDR7_RX register ***************/
vladvana	0:23d1f73bf130	3605	#define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 7 /
vladvana	0:23d1f73bf130	3606
vladvana	0:23d1f73bf130	3607	/----------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	3608
vladvana	0:23d1f73bf130	3609	/*************** Bit definition for USB_COUNT0_RX register **************/
vladvana	0:23d1f73bf130	3610	#define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
vladvana	0:23d1f73bf130	3611
vladvana	0:23d1f73bf130	3612	#define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
vladvana	0:23d1f73bf130	3613	#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3614	#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3615	#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3616	#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3617	#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3618
vladvana	0:23d1f73bf130	3619	#define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
vladvana	0:23d1f73bf130	3620
vladvana	0:23d1f73bf130	3621	/*************** Bit definition for USB_COUNT1_RX register **************/
vladvana	0:23d1f73bf130	3622	#define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
vladvana	0:23d1f73bf130	3623
vladvana	0:23d1f73bf130	3624	#define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
vladvana	0:23d1f73bf130	3625	#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3626	#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3627	#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3628	#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3629	#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3630
vladvana	0:23d1f73bf130	3631	#define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
vladvana	0:23d1f73bf130	3632
vladvana	0:23d1f73bf130	3633	/*************** Bit definition for USB_COUNT2_RX register **************/
vladvana	0:23d1f73bf130	3634	#define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
vladvana	0:23d1f73bf130	3635
vladvana	0:23d1f73bf130	3636	#define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
vladvana	0:23d1f73bf130	3637	#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3638	#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3639	#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3640	#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3641	#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3642
vladvana	0:23d1f73bf130	3643	#define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
vladvana	0:23d1f73bf130	3644
vladvana	0:23d1f73bf130	3645	/*************** Bit definition for USB_COUNT3_RX register **************/
vladvana	0:23d1f73bf130	3646	#define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
vladvana	0:23d1f73bf130	3647
vladvana	0:23d1f73bf130	3648	#define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
vladvana	0:23d1f73bf130	3649	#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3650	#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3651	#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3652	#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3653	#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3654
vladvana	0:23d1f73bf130	3655	#define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
vladvana	0:23d1f73bf130	3656
vladvana	0:23d1f73bf130	3657	/*************** Bit definition for USB_COUNT4_RX register **************/
vladvana	0:23d1f73bf130	3658	#define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
vladvana	0:23d1f73bf130	3659
vladvana	0:23d1f73bf130	3660	#define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
vladvana	0:23d1f73bf130	3661	#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3662	#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3663	#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3664	#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3665	#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3666
vladvana	0:23d1f73bf130	3667	#define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
vladvana	0:23d1f73bf130	3668
vladvana	0:23d1f73bf130	3669	/*************** Bit definition for USB_COUNT5_RX register **************/
vladvana	0:23d1f73bf130	3670	#define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
vladvana	0:23d1f73bf130	3671
vladvana	0:23d1f73bf130	3672	#define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
vladvana	0:23d1f73bf130	3673	#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3674	#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3675	#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3676	#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3677	#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3678
vladvana	0:23d1f73bf130	3679	#define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
vladvana	0:23d1f73bf130	3680
vladvana	0:23d1f73bf130	3681	/*************** Bit definition for USB_COUNT6_RX register **************/
vladvana	0:23d1f73bf130	3682	#define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
vladvana	0:23d1f73bf130	3683
vladvana	0:23d1f73bf130	3684	#define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
vladvana	0:23d1f73bf130	3685	#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3686	#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3687	#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3688	#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3689	#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3690
vladvana	0:23d1f73bf130	3691	#define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
vladvana	0:23d1f73bf130	3692
vladvana	0:23d1f73bf130	3693	/*************** Bit definition for USB_COUNT7_RX register **************/
vladvana	0:23d1f73bf130	3694	#define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
vladvana	0:23d1f73bf130	3695
vladvana	0:23d1f73bf130	3696	#define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
vladvana	0:23d1f73bf130	3697	#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3698	#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3699	#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3700	#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3701	#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3702
vladvana	0:23d1f73bf130	3703	#define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
vladvana	0:23d1f73bf130	3704
vladvana	0:23d1f73bf130	3705	/----------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	3706
vladvana	0:23d1f73bf130	3707	/************** Bit definition for USB_COUNT0_RX_0 register *************/
vladvana	0:23d1f73bf130	3708	#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
vladvana	0:23d1f73bf130	3709
vladvana	0:23d1f73bf130	3710	#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
vladvana	0:23d1f73bf130	3711	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3712	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3713	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3714	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3715	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3716
vladvana	0:23d1f73bf130	3717	#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
vladvana	0:23d1f73bf130	3718
vladvana	0:23d1f73bf130	3719	/************** Bit definition for USB_COUNT0_RX_1 register *************/
vladvana	0:23d1f73bf130	3720	#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
vladvana	0:23d1f73bf130	3721
vladvana	0:23d1f73bf130	3722	#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
vladvana	0:23d1f73bf130	3723	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3724	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3725	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3726	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3727	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3728
vladvana	0:23d1f73bf130	3729	#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
vladvana	0:23d1f73bf130	3730
vladvana	0:23d1f73bf130	3731	/************** Bit definition for USB_COUNT1_RX_0 register *************/
vladvana	0:23d1f73bf130	3732	#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
vladvana	0:23d1f73bf130	3733
vladvana	0:23d1f73bf130	3734	#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
vladvana	0:23d1f73bf130	3735	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3736	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3737	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3738	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3739	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3740
vladvana	0:23d1f73bf130	3741	#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
vladvana	0:23d1f73bf130	3742
vladvana	0:23d1f73bf130	3743	/************** Bit definition for USB_COUNT1_RX_1 register *************/
vladvana	0:23d1f73bf130	3744	#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
vladvana	0:23d1f73bf130	3745
vladvana	0:23d1f73bf130	3746	#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
vladvana	0:23d1f73bf130	3747	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3748	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3749	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3750	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3751	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3752
vladvana	0:23d1f73bf130	3753	#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
vladvana	0:23d1f73bf130	3754
vladvana	0:23d1f73bf130	3755	/************** Bit definition for USB_COUNT2_RX_0 register *************/
vladvana	0:23d1f73bf130	3756	#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
vladvana	0:23d1f73bf130	3757
vladvana	0:23d1f73bf130	3758	#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
vladvana	0:23d1f73bf130	3759	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3760	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3761	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3762	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3763	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3764
vladvana	0:23d1f73bf130	3765	#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
vladvana	0:23d1f73bf130	3766
vladvana	0:23d1f73bf130	3767	/************** Bit definition for USB_COUNT2_RX_1 register *************/
vladvana	0:23d1f73bf130	3768	#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
vladvana	0:23d1f73bf130	3769
vladvana	0:23d1f73bf130	3770	#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
vladvana	0:23d1f73bf130	3771	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3772	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3773	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3774	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3775	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3776
vladvana	0:23d1f73bf130	3777	#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
vladvana	0:23d1f73bf130	3778
vladvana	0:23d1f73bf130	3779	/************** Bit definition for USB_COUNT3_RX_0 register *************/
vladvana	0:23d1f73bf130	3780	#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
vladvana	0:23d1f73bf130	3781
vladvana	0:23d1f73bf130	3782	#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
vladvana	0:23d1f73bf130	3783	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3784	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3785	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3786	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3787	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3788
vladvana	0:23d1f73bf130	3789	#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
vladvana	0:23d1f73bf130	3790
vladvana	0:23d1f73bf130	3791	/************** Bit definition for USB_COUNT3_RX_1 register *************/
vladvana	0:23d1f73bf130	3792	#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
vladvana	0:23d1f73bf130	3793
vladvana	0:23d1f73bf130	3794	#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
vladvana	0:23d1f73bf130	3795	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3796	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3797	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3798	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3799	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3800
vladvana	0:23d1f73bf130	3801	#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
vladvana	0:23d1f73bf130	3802
vladvana	0:23d1f73bf130	3803	/************** Bit definition for USB_COUNT4_RX_0 register *************/
vladvana	0:23d1f73bf130	3804	#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
vladvana	0:23d1f73bf130	3805
vladvana	0:23d1f73bf130	3806	#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
vladvana	0:23d1f73bf130	3807	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3808	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3809	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3810	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3811	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3812
vladvana	0:23d1f73bf130	3813	#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
vladvana	0:23d1f73bf130	3814
vladvana	0:23d1f73bf130	3815	/************** Bit definition for USB_COUNT4_RX_1 register *************/
vladvana	0:23d1f73bf130	3816	#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
vladvana	0:23d1f73bf130	3817
vladvana	0:23d1f73bf130	3818	#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
vladvana	0:23d1f73bf130	3819	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3820	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3821	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3822	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3823	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3824
vladvana	0:23d1f73bf130	3825	#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
vladvana	0:23d1f73bf130	3826
vladvana	0:23d1f73bf130	3827	/************** Bit definition for USB_COUNT5_RX_0 register *************/
vladvana	0:23d1f73bf130	3828	#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
vladvana	0:23d1f73bf130	3829
vladvana	0:23d1f73bf130	3830	#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
vladvana	0:23d1f73bf130	3831	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3832	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3833	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3834	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3835	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3836
vladvana	0:23d1f73bf130	3837	#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
vladvana	0:23d1f73bf130	3838
vladvana	0:23d1f73bf130	3839	/************** Bit definition for USB_COUNT5_RX_1 register *************/
vladvana	0:23d1f73bf130	3840	#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
vladvana	0:23d1f73bf130	3841
vladvana	0:23d1f73bf130	3842	#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
vladvana	0:23d1f73bf130	3843	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3844	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3845	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3846	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3847	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3848
vladvana	0:23d1f73bf130	3849	#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
vladvana	0:23d1f73bf130	3850
vladvana	0:23d1f73bf130	3851	/************* Bit definition for USB_COUNT6_RX_0 register *************/
vladvana	0:23d1f73bf130	3852	#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
vladvana	0:23d1f73bf130	3853
vladvana	0:23d1f73bf130	3854	#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
vladvana	0:23d1f73bf130	3855	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3856	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3857	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3858	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3859	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3860
vladvana	0:23d1f73bf130	3861	#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
vladvana	0:23d1f73bf130	3862
vladvana	0:23d1f73bf130	3863	/************** Bit definition for USB_COUNT6_RX_1 register *************/
vladvana	0:23d1f73bf130	3864	#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
vladvana	0:23d1f73bf130	3865
vladvana	0:23d1f73bf130	3866	#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
vladvana	0:23d1f73bf130	3867	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3868	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3869	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3870	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3871	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3872
vladvana	0:23d1f73bf130	3873	#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
vladvana	0:23d1f73bf130	3874
vladvana	0:23d1f73bf130	3875	/************* Bit definition for USB_COUNT7_RX_0 register **************/
vladvana	0:23d1f73bf130	3876	#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
vladvana	0:23d1f73bf130	3877
vladvana	0:23d1f73bf130	3878	#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
vladvana	0:23d1f73bf130	3879	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
vladvana	0:23d1f73bf130	3880	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
vladvana	0:23d1f73bf130	3881	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3882	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3883	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3884
vladvana	0:23d1f73bf130	3885	#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
vladvana	0:23d1f73bf130	3886
vladvana	0:23d1f73bf130	3887	/************* Bit definition for USB_COUNT7_RX_1 register **************/
vladvana	0:23d1f73bf130	3888	#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
vladvana	0:23d1f73bf130	3889
vladvana	0:23d1f73bf130	3890	#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
vladvana	0:23d1f73bf130	3891	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
vladvana	0:23d1f73bf130	3892	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
vladvana	0:23d1f73bf130	3893	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
vladvana	0:23d1f73bf130	3894	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
vladvana	0:23d1f73bf130	3895	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
vladvana	0:23d1f73bf130	3896
vladvana	0:23d1f73bf130	3897	#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
vladvana	0:23d1f73bf130	3898
vladvana	0:23d1f73bf130	3899	/******************************************************************************/
vladvana	0:23d1f73bf130	3900	/* */
vladvana	0:23d1f73bf130	3901	/* Controller Area Network */
vladvana	0:23d1f73bf130	3902	/* */
vladvana	0:23d1f73bf130	3903	/******************************************************************************/
vladvana	0:23d1f73bf130	3904
vladvana	0:23d1f73bf130	3905	/!< CAN control and status registers /
vladvana	0:23d1f73bf130	3906	/***************** Bit definition for CAN_MCR register ******************/
vladvana	0:23d1f73bf130	3907	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!< Initialization Request /
vladvana	0:23d1f73bf130	3908	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!< Sleep Mode Request /
vladvana	0:23d1f73bf130	3909	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!< Transmit FIFO Priority /
vladvana	0:23d1f73bf130	3910	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!< Receive FIFO Locked Mode /
vladvana	0:23d1f73bf130	3911	#define CAN_MCR_NART ((uint32_t)0x00000010) /!< No Automatic Retransmission /
vladvana	0:23d1f73bf130	3912	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!< Automatic Wakeup Mode /
vladvana	0:23d1f73bf130	3913	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!< Automatic Bus-Off Management /
vladvana	0:23d1f73bf130	3914	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!< Time Triggered Communication Mode /
vladvana	0:23d1f73bf130	3915	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!< CAN software master reset /
vladvana	0:23d1f73bf130	3916	#define CAN_MCR_DBF ((uint32_t)0x00010000) /!< CAN Debug freeze /
vladvana	0:23d1f73bf130	3917
vladvana	0:23d1f73bf130	3918	/***************** Bit definition for CAN_MSR register ******************/
vladvana	0:23d1f73bf130	3919	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!< Initialization Acknowledge /
vladvana	0:23d1f73bf130	3920	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!< Sleep Acknowledge /
vladvana	0:23d1f73bf130	3921	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!< Error Interrupt /
vladvana	0:23d1f73bf130	3922	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!< Wakeup Interrupt /
vladvana	0:23d1f73bf130	3923	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!< Sleep Acknowledge Interrupt /
vladvana	0:23d1f73bf130	3924	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!< Transmit Mode /
vladvana	0:23d1f73bf130	3925	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!< Receive Mode /
vladvana	0:23d1f73bf130	3926	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!< Last Sample Point /
vladvana	0:23d1f73bf130	3927	#define CAN_MSR_RX ((uint32_t)0x00000800) /!< CAN Rx Signal /
vladvana	0:23d1f73bf130	3928
vladvana	0:23d1f73bf130	3929	/***************** Bit definition for CAN_TSR register ******************/
vladvana	0:23d1f73bf130	3930	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!< Request Completed Mailbox0 /
vladvana	0:23d1f73bf130	3931	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!< Transmission OK of Mailbox0 /
vladvana	0:23d1f73bf130	3932	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!< Arbitration Lost for Mailbox0 /
vladvana	0:23d1f73bf130	3933	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!< Transmission Error of Mailbox0 /
vladvana	0:23d1f73bf130	3934	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!< Abort Request for Mailbox0 /
vladvana	0:23d1f73bf130	3935	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!< Request Completed Mailbox1 /
vladvana	0:23d1f73bf130	3936	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!< Transmission OK of Mailbox1 /
vladvana	0:23d1f73bf130	3937	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!< Arbitration Lost for Mailbox1 /
vladvana	0:23d1f73bf130	3938	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!< Transmission Error of Mailbox1 /
vladvana	0:23d1f73bf130	3939	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!< Abort Request for Mailbox 1 /
vladvana	0:23d1f73bf130	3940	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!< Request Completed Mailbox2 /
vladvana	0:23d1f73bf130	3941	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!< Transmission OK of Mailbox 2 /
vladvana	0:23d1f73bf130	3942	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!< Arbitration Lost for mailbox 2 /
vladvana	0:23d1f73bf130	3943	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!< Transmission Error of Mailbox 2 /
vladvana	0:23d1f73bf130	3944	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!< Abort Request for Mailbox 2 /
vladvana	0:23d1f73bf130	3945	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!< Mailbox Code /
vladvana	0:23d1f73bf130	3946
vladvana	0:23d1f73bf130	3947	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!< TME[2:0] bits /
vladvana	0:23d1f73bf130	3948	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!< Transmit Mailbox 0 Empty /
vladvana	0:23d1f73bf130	3949	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!< Transmit Mailbox 1 Empty /
vladvana	0:23d1f73bf130	3950	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!< Transmit Mailbox 2 Empty /
vladvana	0:23d1f73bf130	3951
vladvana	0:23d1f73bf130	3952	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!< LOW[2:0] bits /
vladvana	0:23d1f73bf130	3953	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!< Lowest Priority Flag for Mailbox 0 /
vladvana	0:23d1f73bf130	3954	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!< Lowest Priority Flag for Mailbox 1 /
vladvana	0:23d1f73bf130	3955	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!< Lowest Priority Flag for Mailbox 2 /
vladvana	0:23d1f73bf130	3956
vladvana	0:23d1f73bf130	3957	/***************** Bit definition for CAN_RF0R register *****************/
vladvana	0:23d1f73bf130	3958	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!< FIFO 0 Message Pending /
vladvana	0:23d1f73bf130	3959	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!< FIFO 0 Full /
vladvana	0:23d1f73bf130	3960	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!< FIFO 0 Overrun /
vladvana	0:23d1f73bf130	3961	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!< Release FIFO 0 Output Mailbox /
vladvana	0:23d1f73bf130	3962
vladvana	0:23d1f73bf130	3963	/***************** Bit definition for CAN_RF1R register *****************/
vladvana	0:23d1f73bf130	3964	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!< FIFO 1 Message Pending /
vladvana	0:23d1f73bf130	3965	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!< FIFO 1 Full /
vladvana	0:23d1f73bf130	3966	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!< FIFO 1 Overrun /
vladvana	0:23d1f73bf130	3967	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!< Release FIFO 1 Output Mailbox /
vladvana	0:23d1f73bf130	3968
vladvana	0:23d1f73bf130	3969	/****************** Bit definition for CAN_IER register *****************/
vladvana	0:23d1f73bf130	3970	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!< Transmit Mailbox Empty Interrupt Enable /
vladvana	0:23d1f73bf130	3971	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!< FIFO Message Pending Interrupt Enable /
vladvana	0:23d1f73bf130	3972	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!< FIFO Full Interrupt Enable /
vladvana	0:23d1f73bf130	3973	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!< FIFO Overrun Interrupt Enable /
vladvana	0:23d1f73bf130	3974	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!< FIFO Message Pending Interrupt Enable /
vladvana	0:23d1f73bf130	3975	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!< FIFO Full Interrupt Enable /
vladvana	0:23d1f73bf130	3976	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!< FIFO Overrun Interrupt Enable /
vladvana	0:23d1f73bf130	3977	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!< Error Warning Interrupt Enable /
vladvana	0:23d1f73bf130	3978	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!< Error Passive Interrupt Enable /
vladvana	0:23d1f73bf130	3979	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!< Bus-Off Interrupt Enable /
vladvana	0:23d1f73bf130	3980	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!< Last Error Code Interrupt Enable /
vladvana	0:23d1f73bf130	3981	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!< Error Interrupt Enable /
vladvana	0:23d1f73bf130	3982	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!< Wakeup Interrupt Enable /
vladvana	0:23d1f73bf130	3983	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!< Sleep Interrupt Enable /
vladvana	0:23d1f73bf130	3984
vladvana	0:23d1f73bf130	3985	/****************** Bit definition for CAN_ESR register *****************/
vladvana	0:23d1f73bf130	3986	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!< Error Warning Flag /
vladvana	0:23d1f73bf130	3987	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!< Error Passive Flag /
vladvana	0:23d1f73bf130	3988	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!< Bus-Off Flag /
vladvana	0:23d1f73bf130	3989
vladvana	0:23d1f73bf130	3990	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!< LEC[2:0] bits (Last Error Code) /
vladvana	0:23d1f73bf130	3991	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!< Bit 0 /
vladvana	0:23d1f73bf130	3992	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!< Bit 1 /
vladvana	0:23d1f73bf130	3993	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!< Bit 2 /
vladvana	0:23d1f73bf130	3994
vladvana	0:23d1f73bf130	3995	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!< Least significant byte of the 9-bit Transmit Error Counter /
vladvana	0:23d1f73bf130	3996	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!< Receive Error Counter /
vladvana	0:23d1f73bf130	3997
vladvana	0:23d1f73bf130	3998	/***************** Bit definition for CAN_BTR register ******************/
vladvana	0:23d1f73bf130	3999	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
vladvana	0:23d1f73bf130	4000	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
vladvana	0:23d1f73bf130	4001	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
vladvana	0:23d1f73bf130	4002	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
vladvana	0:23d1f73bf130	4003	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
vladvana	0:23d1f73bf130	4004	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
vladvana	0:23d1f73bf130	4005	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
vladvana	0:23d1f73bf130	4006	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
vladvana	0:23d1f73bf130	4007	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
vladvana	0:23d1f73bf130	4008	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
vladvana	0:23d1f73bf130	4009	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
vladvana	0:23d1f73bf130	4010	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
vladvana	0:23d1f73bf130	4011	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
vladvana	0:23d1f73bf130	4012	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
vladvana	0:23d1f73bf130	4013	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
vladvana	0:23d1f73bf130	4014
vladvana	0:23d1f73bf130	4015	/!< Mailbox registers /
vladvana	0:23d1f73bf130	4016	/**************** Bit definition for CAN_TI0R register ******************/
vladvana	0:23d1f73bf130	4017	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
vladvana	0:23d1f73bf130	4018	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
vladvana	0:23d1f73bf130	4019	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
vladvana	0:23d1f73bf130	4020	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
vladvana	0:23d1f73bf130	4021	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
vladvana	0:23d1f73bf130	4022
vladvana	0:23d1f73bf130	4023	/**************** Bit definition for CAN_TDT0R register *****************/
vladvana	0:23d1f73bf130	4024	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
vladvana	0:23d1f73bf130	4025	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
vladvana	0:23d1f73bf130	4026	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
vladvana	0:23d1f73bf130	4027
vladvana	0:23d1f73bf130	4028	/**************** Bit definition for CAN_TDL0R register *****************/
vladvana	0:23d1f73bf130	4029	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
vladvana	0:23d1f73bf130	4030	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
vladvana	0:23d1f73bf130	4031	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
vladvana	0:23d1f73bf130	4032	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
vladvana	0:23d1f73bf130	4033
vladvana	0:23d1f73bf130	4034	/**************** Bit definition for CAN_TDH0R register *****************/
vladvana	0:23d1f73bf130	4035	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
vladvana	0:23d1f73bf130	4036	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
vladvana	0:23d1f73bf130	4037	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
vladvana	0:23d1f73bf130	4038	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
vladvana	0:23d1f73bf130	4039
vladvana	0:23d1f73bf130	4040	/***************** Bit definition for CAN_TI1R register *****************/
vladvana	0:23d1f73bf130	4041	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
vladvana	0:23d1f73bf130	4042	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
vladvana	0:23d1f73bf130	4043	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
vladvana	0:23d1f73bf130	4044	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
vladvana	0:23d1f73bf130	4045	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
vladvana	0:23d1f73bf130	4046
vladvana	0:23d1f73bf130	4047	/***************** Bit definition for CAN_TDT1R register ****************/
vladvana	0:23d1f73bf130	4048	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
vladvana	0:23d1f73bf130	4049	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
vladvana	0:23d1f73bf130	4050	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
vladvana	0:23d1f73bf130	4051
vladvana	0:23d1f73bf130	4052	/***************** Bit definition for CAN_TDL1R register ****************/
vladvana	0:23d1f73bf130	4053	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
vladvana	0:23d1f73bf130	4054	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
vladvana	0:23d1f73bf130	4055	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
vladvana	0:23d1f73bf130	4056	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
vladvana	0:23d1f73bf130	4057
vladvana	0:23d1f73bf130	4058	/***************** Bit definition for CAN_TDH1R register ****************/
vladvana	0:23d1f73bf130	4059	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
vladvana	0:23d1f73bf130	4060	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
vladvana	0:23d1f73bf130	4061	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
vladvana	0:23d1f73bf130	4062	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
vladvana	0:23d1f73bf130	4063
vladvana	0:23d1f73bf130	4064	/***************** Bit definition for CAN_TI2R register *****************/
vladvana	0:23d1f73bf130	4065	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
vladvana	0:23d1f73bf130	4066	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
vladvana	0:23d1f73bf130	4067	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
vladvana	0:23d1f73bf130	4068	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
vladvana	0:23d1f73bf130	4069	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
vladvana	0:23d1f73bf130	4070
vladvana	0:23d1f73bf130	4071	/***************** Bit definition for CAN_TDT2R register ****************/
vladvana	0:23d1f73bf130	4072	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
vladvana	0:23d1f73bf130	4073	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
vladvana	0:23d1f73bf130	4074	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
vladvana	0:23d1f73bf130	4075
vladvana	0:23d1f73bf130	4076	/***************** Bit definition for CAN_TDL2R register ****************/
vladvana	0:23d1f73bf130	4077	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
vladvana	0:23d1f73bf130	4078	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
vladvana	0:23d1f73bf130	4079	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
vladvana	0:23d1f73bf130	4080	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
vladvana	0:23d1f73bf130	4081
vladvana	0:23d1f73bf130	4082	/***************** Bit definition for CAN_TDH2R register ****************/
vladvana	0:23d1f73bf130	4083	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
vladvana	0:23d1f73bf130	4084	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
vladvana	0:23d1f73bf130	4085	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
vladvana	0:23d1f73bf130	4086	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
vladvana	0:23d1f73bf130	4087
vladvana	0:23d1f73bf130	4088	/***************** Bit definition for CAN_RI0R register *****************/
vladvana	0:23d1f73bf130	4089	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
vladvana	0:23d1f73bf130	4090	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
vladvana	0:23d1f73bf130	4091	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
vladvana	0:23d1f73bf130	4092	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
vladvana	0:23d1f73bf130	4093
vladvana	0:23d1f73bf130	4094	/***************** Bit definition for CAN_RDT0R register ****************/
vladvana	0:23d1f73bf130	4095	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
vladvana	0:23d1f73bf130	4096	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
vladvana	0:23d1f73bf130	4097	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
vladvana	0:23d1f73bf130	4098
vladvana	0:23d1f73bf130	4099	/***************** Bit definition for CAN_RDL0R register ****************/
vladvana	0:23d1f73bf130	4100	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
vladvana	0:23d1f73bf130	4101	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
vladvana	0:23d1f73bf130	4102	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
vladvana	0:23d1f73bf130	4103	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
vladvana	0:23d1f73bf130	4104
vladvana	0:23d1f73bf130	4105	/***************** Bit definition for CAN_RDH0R register ****************/
vladvana	0:23d1f73bf130	4106	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
vladvana	0:23d1f73bf130	4107	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
vladvana	0:23d1f73bf130	4108	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
vladvana	0:23d1f73bf130	4109	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
vladvana	0:23d1f73bf130	4110
vladvana	0:23d1f73bf130	4111	/***************** Bit definition for CAN_RI1R register *****************/
vladvana	0:23d1f73bf130	4112	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
vladvana	0:23d1f73bf130	4113	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
vladvana	0:23d1f73bf130	4114	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
vladvana	0:23d1f73bf130	4115	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
vladvana	0:23d1f73bf130	4116
vladvana	0:23d1f73bf130	4117	/***************** Bit definition for CAN_RDT1R register ****************/
vladvana	0:23d1f73bf130	4118	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
vladvana	0:23d1f73bf130	4119	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
vladvana	0:23d1f73bf130	4120	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
vladvana	0:23d1f73bf130	4121
vladvana	0:23d1f73bf130	4122	/***************** Bit definition for CAN_RDL1R register ****************/
vladvana	0:23d1f73bf130	4123	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
vladvana	0:23d1f73bf130	4124	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
vladvana	0:23d1f73bf130	4125	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
vladvana	0:23d1f73bf130	4126	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
vladvana	0:23d1f73bf130	4127
vladvana	0:23d1f73bf130	4128	/***************** Bit definition for CAN_RDH1R register ****************/
vladvana	0:23d1f73bf130	4129	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
vladvana	0:23d1f73bf130	4130	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
vladvana	0:23d1f73bf130	4131	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
vladvana	0:23d1f73bf130	4132	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
vladvana	0:23d1f73bf130	4133
vladvana	0:23d1f73bf130	4134	/!< CAN filter registers /
vladvana	0:23d1f73bf130	4135	/***************** Bit definition for CAN_FMR register ******************/
vladvana	0:23d1f73bf130	4136	#define CAN_FMR_FINIT ((uint32_t)0x00000001) /!< Filter Init Mode /
vladvana	0:23d1f73bf130	4137	#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /!< CAN2 start bank /
vladvana	0:23d1f73bf130	4138
vladvana	0:23d1f73bf130	4139	/***************** Bit definition for CAN_FM1R register *****************/
vladvana	0:23d1f73bf130	4140	#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /!< Filter Mode /
vladvana	0:23d1f73bf130	4141	#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /!< Filter Init Mode for filter 0 /
vladvana	0:23d1f73bf130	4142	#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /!< Filter Init Mode for filter 1 /
vladvana	0:23d1f73bf130	4143	#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /!< Filter Init Mode for filter 2 /
vladvana	0:23d1f73bf130	4144	#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /!< Filter Init Mode for filter 3 /
vladvana	0:23d1f73bf130	4145	#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /!< Filter Init Mode for filter 4 /
vladvana	0:23d1f73bf130	4146	#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /!< Filter Init Mode for filter 5 /
vladvana	0:23d1f73bf130	4147	#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /!< Filter Init Mode for filter 6 /
vladvana	0:23d1f73bf130	4148	#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /!< Filter Init Mode for filter 7 /
vladvana	0:23d1f73bf130	4149	#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /!< Filter Init Mode for filter 8 /
vladvana	0:23d1f73bf130	4150	#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /!< Filter Init Mode for filter 9 /
vladvana	0:23d1f73bf130	4151	#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /!< Filter Init Mode for filter 10 /
vladvana	0:23d1f73bf130	4152	#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /!< Filter Init Mode for filter 11 /
vladvana	0:23d1f73bf130	4153	#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /!< Filter Init Mode for filter 12 /
vladvana	0:23d1f73bf130	4154	#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /!< Filter Init Mode for filter 13 /
vladvana	0:23d1f73bf130	4155
vladvana	0:23d1f73bf130	4156	/***************** Bit definition for CAN_FS1R register *****************/
vladvana	0:23d1f73bf130	4157	#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /!< Filter Scale Configuration /
vladvana	0:23d1f73bf130	4158	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!< Filter Scale Configuration for filter 0 /
vladvana	0:23d1f73bf130	4159	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!< Filter Scale Configuration for filter 1 /
vladvana	0:23d1f73bf130	4160	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!< Filter Scale Configuration for filter 2 /
vladvana	0:23d1f73bf130	4161	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!< Filter Scale Configuration for filter 3 /
vladvana	0:23d1f73bf130	4162	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!< Filter Scale Configuration for filter 4 /
vladvana	0:23d1f73bf130	4163	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!< Filter Scale Configuration for filter 5 /
vladvana	0:23d1f73bf130	4164	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!< Filter Scale Configuration for filter 6 /
vladvana	0:23d1f73bf130	4165	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!< Filter Scale Configuration for filter 7 /
vladvana	0:23d1f73bf130	4166	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!< Filter Scale Configuration for filter 8 /
vladvana	0:23d1f73bf130	4167	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!< Filter Scale Configuration for filter 9 /
vladvana	0:23d1f73bf130	4168	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!< Filter Scale Configuration for filter 10 /
vladvana	0:23d1f73bf130	4169	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!< Filter Scale Configuration for filter 11 /
vladvana	0:23d1f73bf130	4170	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!< Filter Scale Configuration for filter 12 /
vladvana	0:23d1f73bf130	4171	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!< Filter Scale Configuration for filter 13 /
vladvana	0:23d1f73bf130	4172
vladvana	0:23d1f73bf130	4173	/**************** Bit definition for CAN_FFA1R register *****************/
vladvana	0:23d1f73bf130	4174	#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /!< Filter FIFO Assignment /
vladvana	0:23d1f73bf130	4175	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!< Filter FIFO Assignment for filter 0 /
vladvana	0:23d1f73bf130	4176	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!< Filter FIFO Assignment for filter 1 /
vladvana	0:23d1f73bf130	4177	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!< Filter FIFO Assignment for filter 2 /
vladvana	0:23d1f73bf130	4178	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!< Filter FIFO Assignment for filter 3 /
vladvana	0:23d1f73bf130	4179	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!< Filter FIFO Assignment for filter 4 /
vladvana	0:23d1f73bf130	4180	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!< Filter FIFO Assignment for filter 5 /
vladvana	0:23d1f73bf130	4181	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!< Filter FIFO Assignment for filter 6 /
vladvana	0:23d1f73bf130	4182	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!< Filter FIFO Assignment for filter 7 /
vladvana	0:23d1f73bf130	4183	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!< Filter FIFO Assignment for filter 8 /
vladvana	0:23d1f73bf130	4184	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!< Filter FIFO Assignment for filter 9 /
vladvana	0:23d1f73bf130	4185	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!< Filter FIFO Assignment for filter 10 /
vladvana	0:23d1f73bf130	4186	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!< Filter FIFO Assignment for filter 11 /
vladvana	0:23d1f73bf130	4187	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!< Filter FIFO Assignment for filter 12 /
vladvana	0:23d1f73bf130	4188	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!< Filter FIFO Assignment for filter 13 /
vladvana	0:23d1f73bf130	4189
vladvana	0:23d1f73bf130	4190	/***************** Bit definition for CAN_FA1R register *****************/
vladvana	0:23d1f73bf130	4191	#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /!< Filter Active /
vladvana	0:23d1f73bf130	4192	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!< Filter 0 Active /
vladvana	0:23d1f73bf130	4193	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!< Filter 1 Active /
vladvana	0:23d1f73bf130	4194	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!< Filter 2 Active /
vladvana	0:23d1f73bf130	4195	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!< Filter 3 Active /
vladvana	0:23d1f73bf130	4196	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!< Filter 4 Active /
vladvana	0:23d1f73bf130	4197	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!< Filter 5 Active /
vladvana	0:23d1f73bf130	4198	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!< Filter 6 Active /
vladvana	0:23d1f73bf130	4199	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!< Filter 7 Active /
vladvana	0:23d1f73bf130	4200	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!< Filter 8 Active /
vladvana	0:23d1f73bf130	4201	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!< Filter 9 Active /
vladvana	0:23d1f73bf130	4202	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!< Filter 10 Active /
vladvana	0:23d1f73bf130	4203	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!< Filter 11 Active /
vladvana	0:23d1f73bf130	4204	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!< Filter 12 Active /
vladvana	0:23d1f73bf130	4205	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!< Filter 13 Active /
vladvana	0:23d1f73bf130	4206
vladvana	0:23d1f73bf130	4207	/***************** Bit definition for CAN_F0R1 register *****************/
vladvana	0:23d1f73bf130	4208	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4209	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4210	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4211	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4212	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4213	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4214	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4215	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4216	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4217	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4218	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4219	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4220	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4221	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4222	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4223	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4224	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4225	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4226	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4227	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4228	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4229	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4230	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4231	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4232	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4233	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4234	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4235	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4236	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4237	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4238	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4239	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4240
vladvana	0:23d1f73bf130	4241	/***************** Bit definition for CAN_F1R1 register *****************/
vladvana	0:23d1f73bf130	4242	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4243	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4244	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4245	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4246	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4247	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4248	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4249	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4250	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4251	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4252	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4253	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4254	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4255	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4256	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4257	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4258	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4259	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4260	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4261	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4262	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4263	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4264	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4265	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4266	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4267	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4268	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4269	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4270	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4271	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4272	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4273	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4274
vladvana	0:23d1f73bf130	4275	/***************** Bit definition for CAN_F2R1 register *****************/
vladvana	0:23d1f73bf130	4276	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4277	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4278	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4279	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4280	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4281	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4282	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4283	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4284	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4285	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4286	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4287	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4288	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4289	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4290	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4291	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4292	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4293	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4294	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4295	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4296	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4297	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4298	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4299	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4300	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4301	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4302	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4303	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4304	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4305	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4306	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4307	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4308
vladvana	0:23d1f73bf130	4309	/***************** Bit definition for CAN_F3R1 register *****************/
vladvana	0:23d1f73bf130	4310	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4311	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4312	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4313	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4314	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4315	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4316	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4317	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4318	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4319	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4320	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4321	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4322	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4323	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4324	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4325	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4326	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4327	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4328	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4329	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4330	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4331	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4332	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4333	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4334	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4335	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4336	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4337	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4338	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4339	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4340	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4341	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4342
vladvana	0:23d1f73bf130	4343	/***************** Bit definition for CAN_F4R1 register *****************/
vladvana	0:23d1f73bf130	4344	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4345	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4346	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4347	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4348	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4349	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4350	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4351	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4352	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4353	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4354	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4355	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4356	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4357	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4358	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4359	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4360	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4361	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4362	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4363	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4364	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4365	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4366	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4367	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4368	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4369	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4370	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4371	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4372	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4373	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4374	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4375	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4376
vladvana	0:23d1f73bf130	4377	/***************** Bit definition for CAN_F5R1 register *****************/
vladvana	0:23d1f73bf130	4378	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4379	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4380	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4381	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4382	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4383	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4384	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4385	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4386	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4387	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4388	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4389	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4390	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4391	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4392	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4393	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4394	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4395	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4396	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4397	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4398	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4399	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4400	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4401	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4402	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4403	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4404	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4405	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4406	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4407	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4408	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4409	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4410
vladvana	0:23d1f73bf130	4411	/***************** Bit definition for CAN_F6R1 register *****************/
vladvana	0:23d1f73bf130	4412	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4413	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4414	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4415	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4416	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4417	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4418	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4419	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4420	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4421	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4422	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4423	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4424	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4425	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4426	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4427	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4428	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4429	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4430	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4431	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4432	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4433	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4434	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4435	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4436	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4437	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4438	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4439	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4440	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4441	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4442	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4443	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4444
vladvana	0:23d1f73bf130	4445	/***************** Bit definition for CAN_F7R1 register *****************/
vladvana	0:23d1f73bf130	4446	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4447	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4448	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4449	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4450	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4451	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4452	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4453	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4454	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4455	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4456	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4457	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4458	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4459	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4460	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4461	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4462	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4463	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4464	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4465	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4466	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4467	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4468	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4469	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4470	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4471	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4472	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4473	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4474	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4475	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4476	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4477	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4478
vladvana	0:23d1f73bf130	4479	/***************** Bit definition for CAN_F8R1 register *****************/
vladvana	0:23d1f73bf130	4480	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4481	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4482	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4483	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4484	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4485	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4486	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4487	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4488	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4489	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4490	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4491	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4492	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4493	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4494	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4495	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4496	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4497	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4498	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4499	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4500	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4501	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4502	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4503	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4504	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4505	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4506	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4507	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4508	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4509	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4510	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4511	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4512
vladvana	0:23d1f73bf130	4513	/***************** Bit definition for CAN_F9R1 register *****************/
vladvana	0:23d1f73bf130	4514	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4515	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4516	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4517	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4518	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4519	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4520	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4521	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4522	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4523	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4524	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4525	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4526	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4527	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4528	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4529	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4530	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4531	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4532	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4533	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4534	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4535	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4536	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4537	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4538	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4539	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4540	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4541	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4542	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4543	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4544	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4545	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4546
vladvana	0:23d1f73bf130	4547	/***************** Bit definition for CAN_F10R1 register ****************/
vladvana	0:23d1f73bf130	4548	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4549	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4550	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4551	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4552	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4553	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4554	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4555	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4556	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4557	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4558	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4559	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4560	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4561	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4562	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4563	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4564	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4565	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4566	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4567	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4568	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4569	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4570	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4571	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4572	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4573	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4574	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4575	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4576	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4577	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4578	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4579	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4580
vladvana	0:23d1f73bf130	4581	/***************** Bit definition for CAN_F11R1 register ****************/
vladvana	0:23d1f73bf130	4582	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4583	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4584	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4585	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4586	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4587	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4588	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4589	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4590	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4591	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4592	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4593	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4594	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4595	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4596	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4597	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4598	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4599	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4600	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4601	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4602	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4603	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4604	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4605	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4606	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4607	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4608	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4609	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4610	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4611	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4612	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4613	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4614
vladvana	0:23d1f73bf130	4615	/***************** Bit definition for CAN_F12R1 register ****************/
vladvana	0:23d1f73bf130	4616	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4617	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4618	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4619	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4620	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4621	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4622	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4623	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4624	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4625	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4626	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4627	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4628	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4629	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4630	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4631	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4632	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4633	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4634	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4635	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4636	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4637	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4638	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4639	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4640	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4641	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4642	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4643	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4644	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4645	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4646	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4647	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4648
vladvana	0:23d1f73bf130	4649	/***************** Bit definition for CAN_F13R1 register ****************/
vladvana	0:23d1f73bf130	4650	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4651	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4652	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4653	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4654	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4655	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4656	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4657	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4658	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4659	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4660	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4661	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4662	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4663	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4664	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4665	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4666	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4667	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4668	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4669	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4670	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4671	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4672	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4673	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4674	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4675	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4676	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4677	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4678	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4679	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4680	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4681	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4682
vladvana	0:23d1f73bf130	4683	/***************** Bit definition for CAN_F0R2 register *****************/
vladvana	0:23d1f73bf130	4684	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4685	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4686	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4687	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4688	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4689	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4690	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4691	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4692	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4693	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4694	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4695	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4696	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4697	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4698	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4699	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4700	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4701	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4702	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4703	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4704	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4705	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4706	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4707	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4708	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4709	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4710	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4711	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4712	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4713	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4714	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4715	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4716
vladvana	0:23d1f73bf130	4717	/***************** Bit definition for CAN_F1R2 register *****************/
vladvana	0:23d1f73bf130	4718	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4719	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4720	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4721	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4722	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4723	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4724	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4725	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4726	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4727	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4728	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4729	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4730	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4731	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4732	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4733	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4734	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4735	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4736	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4737	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4738	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4739	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4740	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4741	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4742	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4743	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4744	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4745	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4746	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4747	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4748	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4749	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4750
vladvana	0:23d1f73bf130	4751	/***************** Bit definition for CAN_F2R2 register *****************/
vladvana	0:23d1f73bf130	4752	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4753	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4754	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4755	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4756	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4757	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4758	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4759	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4760	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4761	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4762	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4763	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4764	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4765	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4766	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4767	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4768	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4769	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4770	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4771	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4772	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4773	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4774	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4775	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4776	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4777	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4778	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4779	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4780	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4781	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4782	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4783	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4784
vladvana	0:23d1f73bf130	4785	/***************** Bit definition for CAN_F3R2 register *****************/
vladvana	0:23d1f73bf130	4786	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4787	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4788	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4789	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4790	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4791	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4792	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4793	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4794	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4795	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4796	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4797	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4798	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4799	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4800	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4801	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4802	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4803	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4804	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4805	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4806	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4807	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4808	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4809	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4810	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4811	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4812	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4813	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4814	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4815	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4816	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4817	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4818
vladvana	0:23d1f73bf130	4819	/***************** Bit definition for CAN_F4R2 register *****************/
vladvana	0:23d1f73bf130	4820	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4821	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4822	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4823	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4824	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4825	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4826	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4827	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4828	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4829	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4830	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4831	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4832	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4833	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4834	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4835	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4836	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4837	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4838	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4839	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4840	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4841	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4842	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4843	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4844	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4845	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4846	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4847	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4848	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4849	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4850	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4851	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4852
vladvana	0:23d1f73bf130	4853	/***************** Bit definition for CAN_F5R2 register *****************/
vladvana	0:23d1f73bf130	4854	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4855	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4856	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4857	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4858	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4859	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4860	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4861	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4862	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4863	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4864	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4865	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4866	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4867	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4868	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4869	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4870	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4871	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4872	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4873	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4874	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4875	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4876	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4877	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4878	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4879	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4880	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4881	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4882	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4883	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4884	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4885	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4886
vladvana	0:23d1f73bf130	4887	/***************** Bit definition for CAN_F6R2 register *****************/
vladvana	0:23d1f73bf130	4888	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4889	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4890	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4891	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4892	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4893	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4894	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4895	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4896	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4897	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4898	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4899	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4900	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4901	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4902	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4903	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4904	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4905	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4906	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4907	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4908	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4909	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4910	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4911	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4912	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4913	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4914	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4915	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4916	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4917	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4918	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4919	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4920
vladvana	0:23d1f73bf130	4921	/***************** Bit definition for CAN_F7R2 register *****************/
vladvana	0:23d1f73bf130	4922	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4923	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4924	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4925	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4926	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4927	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4928	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4929	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4930	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4931	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4932	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4933	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4934	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4935	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4936	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4937	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4938	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4939	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4940	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4941	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4942	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4943	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4944	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4945	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4946	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4947	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4948	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4949	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4950	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4951	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4952	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4953	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4954
vladvana	0:23d1f73bf130	4955	/***************** Bit definition for CAN_F8R2 register *****************/
vladvana	0:23d1f73bf130	4956	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4957	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4958	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4959	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4960	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4961	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4962	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4963	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4964	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4965	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	4966	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	4967	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	4968	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	4969	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	4970	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	4971	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	4972	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	4973	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	4974	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	4975	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	4976	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	4977	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	4978	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	4979	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	4980	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	4981	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	4982	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	4983	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	4984	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	4985	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	4986	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	4987	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	4988
vladvana	0:23d1f73bf130	4989	/***************** Bit definition for CAN_F9R2 register *****************/
vladvana	0:23d1f73bf130	4990	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	4991	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	4992	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	4993	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	4994	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	4995	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	4996	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	4997	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	4998	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	4999	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	5000	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	5001	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	5002	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	5003	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	5004	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	5005	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	5006	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	5007	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	5008	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	5009	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	5010	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	5011	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	5012	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	5013	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	5014	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	5015	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	5016	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	5017	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	5018	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	5019	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	5020	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	5021	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	5022
vladvana	0:23d1f73bf130	5023	/***************** Bit definition for CAN_F10R2 register ****************/
vladvana	0:23d1f73bf130	5024	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	5025	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	5026	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	5027	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	5028	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	5029	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	5030	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	5031	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	5032	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	5033	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	5034	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	5035	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	5036	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	5037	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	5038	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	5039	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	5040	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	5041	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	5042	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	5043	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	5044	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	5045	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	5046	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	5047	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	5048	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	5049	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	5050	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	5051	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	5052	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	5053	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	5054	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	5055	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	5056
vladvana	0:23d1f73bf130	5057	/***************** Bit definition for CAN_F11R2 register ****************/
vladvana	0:23d1f73bf130	5058	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	5059	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	5060	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	5061	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	5062	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	5063	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	5064	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	5065	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	5066	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	5067	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	5068	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	5069	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	5070	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	5071	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	5072	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	5073	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	5074	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	5075	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	5076	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	5077	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	5078	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	5079	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	5080	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	5081	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	5082	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	5083	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	5084	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	5085	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	5086	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	5087	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	5088	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	5089	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	5090
vladvana	0:23d1f73bf130	5091	/***************** Bit definition for CAN_F12R2 register ****************/
vladvana	0:23d1f73bf130	5092	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	5093	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	5094	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	5095	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	5096	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	5097	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	5098	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	5099	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	5100	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	5101	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	5102	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	5103	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	5104	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	5105	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	5106	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	5107	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	5108	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	5109	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	5110	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	5111	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	5112	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	5113	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	5114	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	5115	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	5116	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	5117	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	5118	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	5119	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	5120	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	5121	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	5122	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	5123	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	5124
vladvana	0:23d1f73bf130	5125	/***************** Bit definition for CAN_F13R2 register ****************/
vladvana	0:23d1f73bf130	5126	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
vladvana	0:23d1f73bf130	5127	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
vladvana	0:23d1f73bf130	5128	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
vladvana	0:23d1f73bf130	5129	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
vladvana	0:23d1f73bf130	5130	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
vladvana	0:23d1f73bf130	5131	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
vladvana	0:23d1f73bf130	5132	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
vladvana	0:23d1f73bf130	5133	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
vladvana	0:23d1f73bf130	5134	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
vladvana	0:23d1f73bf130	5135	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
vladvana	0:23d1f73bf130	5136	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
vladvana	0:23d1f73bf130	5137	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
vladvana	0:23d1f73bf130	5138	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
vladvana	0:23d1f73bf130	5139	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
vladvana	0:23d1f73bf130	5140	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
vladvana	0:23d1f73bf130	5141	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
vladvana	0:23d1f73bf130	5142	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
vladvana	0:23d1f73bf130	5143	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
vladvana	0:23d1f73bf130	5144	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
vladvana	0:23d1f73bf130	5145	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
vladvana	0:23d1f73bf130	5146	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
vladvana	0:23d1f73bf130	5147	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
vladvana	0:23d1f73bf130	5148	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
vladvana	0:23d1f73bf130	5149	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
vladvana	0:23d1f73bf130	5150	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
vladvana	0:23d1f73bf130	5151	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
vladvana	0:23d1f73bf130	5152	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
vladvana	0:23d1f73bf130	5153	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
vladvana	0:23d1f73bf130	5154	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
vladvana	0:23d1f73bf130	5155	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
vladvana	0:23d1f73bf130	5156	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
vladvana	0:23d1f73bf130	5157	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
vladvana	0:23d1f73bf130	5158
vladvana	0:23d1f73bf130	5159	/******************************************************************************/
vladvana	0:23d1f73bf130	5160	/* */
vladvana	0:23d1f73bf130	5161	/* Serial Peripheral Interface */
vladvana	0:23d1f73bf130	5162	/* */
vladvana	0:23d1f73bf130	5163	/******************************************************************************/
vladvana	0:23d1f73bf130	5164
vladvana	0:23d1f73bf130	5165	/***************** Bit definition for SPI_CR1 register ******************/
vladvana	0:23d1f73bf130	5166	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
vladvana	0:23d1f73bf130	5167	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
vladvana	0:23d1f73bf130	5168	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
vladvana	0:23d1f73bf130	5169
vladvana	0:23d1f73bf130	5170	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
vladvana	0:23d1f73bf130	5171	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
vladvana	0:23d1f73bf130	5172	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
vladvana	0:23d1f73bf130	5173	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
vladvana	0:23d1f73bf130	5174
vladvana	0:23d1f73bf130	5175	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
vladvana	0:23d1f73bf130	5176	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
vladvana	0:23d1f73bf130	5177	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
vladvana	0:23d1f73bf130	5178	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
vladvana	0:23d1f73bf130	5179	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
vladvana	0:23d1f73bf130	5180	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
vladvana	0:23d1f73bf130	5181	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
vladvana	0:23d1f73bf130	5182	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
vladvana	0:23d1f73bf130	5183	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
vladvana	0:23d1f73bf130	5184	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
vladvana	0:23d1f73bf130	5185
vladvana	0:23d1f73bf130	5186	/***************** Bit definition for SPI_CR2 register ******************/
vladvana	0:23d1f73bf130	5187	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
vladvana	0:23d1f73bf130	5188	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
vladvana	0:23d1f73bf130	5189	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
vladvana	0:23d1f73bf130	5190	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
vladvana	0:23d1f73bf130	5191	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
vladvana	0:23d1f73bf130	5192	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
vladvana	0:23d1f73bf130	5193
vladvana	0:23d1f73bf130	5194	/****************** Bit definition for SPI_SR register ******************/
vladvana	0:23d1f73bf130	5195	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
vladvana	0:23d1f73bf130	5196	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
vladvana	0:23d1f73bf130	5197	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
vladvana	0:23d1f73bf130	5198	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
vladvana	0:23d1f73bf130	5199	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
vladvana	0:23d1f73bf130	5200	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
vladvana	0:23d1f73bf130	5201	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
vladvana	0:23d1f73bf130	5202	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
vladvana	0:23d1f73bf130	5203
vladvana	0:23d1f73bf130	5204	/****************** Bit definition for SPI_DR register ******************/
vladvana	0:23d1f73bf130	5205	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
vladvana	0:23d1f73bf130	5206
vladvana	0:23d1f73bf130	5207	/***************** Bit definition for SPI_CRCPR register ****************/
vladvana	0:23d1f73bf130	5208	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
vladvana	0:23d1f73bf130	5209
vladvana	0:23d1f73bf130	5210	/**************** Bit definition for SPI_RXCRCR register ****************/
vladvana	0:23d1f73bf130	5211	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
vladvana	0:23d1f73bf130	5212
vladvana	0:23d1f73bf130	5213	/**************** Bit definition for SPI_TXCRCR register ****************/
vladvana	0:23d1f73bf130	5214	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
vladvana	0:23d1f73bf130	5215
vladvana	0:23d1f73bf130	5216	/**************** Bit definition for SPI_I2SCFGR register ***************/
vladvana	0:23d1f73bf130	5217	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!< I2S mode selection /
vladvana	0:23d1f73bf130	5218
vladvana	0:23d1f73bf130	5219
vladvana	0:23d1f73bf130	5220	/******************************************************************************/
vladvana	0:23d1f73bf130	5221	/* */
vladvana	0:23d1f73bf130	5222	/* Inter-integrated Circuit Interface */
vladvana	0:23d1f73bf130	5223	/* */
vladvana	0:23d1f73bf130	5224	/******************************************************************************/
vladvana	0:23d1f73bf130	5225
vladvana	0:23d1f73bf130	5226	/***************** Bit definition for I2C_CR1 register ******************/
vladvana	0:23d1f73bf130	5227	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
vladvana	0:23d1f73bf130	5228	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
vladvana	0:23d1f73bf130	5229	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
vladvana	0:23d1f73bf130	5230	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
vladvana	0:23d1f73bf130	5231	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
vladvana	0:23d1f73bf130	5232	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
vladvana	0:23d1f73bf130	5233	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
vladvana	0:23d1f73bf130	5234	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
vladvana	0:23d1f73bf130	5235	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
vladvana	0:23d1f73bf130	5236	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
vladvana	0:23d1f73bf130	5237	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
vladvana	0:23d1f73bf130	5238	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
vladvana	0:23d1f73bf130	5239	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
vladvana	0:23d1f73bf130	5240	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
vladvana	0:23d1f73bf130	5241
vladvana	0:23d1f73bf130	5242	/***************** Bit definition for I2C_CR2 register ******************/
vladvana	0:23d1f73bf130	5243	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
vladvana	0:23d1f73bf130	5244	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	5245	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	5246	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	5247	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	5248	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	5249	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
vladvana	0:23d1f73bf130	5250
vladvana	0:23d1f73bf130	5251	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
vladvana	0:23d1f73bf130	5252	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
vladvana	0:23d1f73bf130	5253	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
vladvana	0:23d1f73bf130	5254	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
vladvana	0:23d1f73bf130	5255	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
vladvana	0:23d1f73bf130	5256
vladvana	0:23d1f73bf130	5257	/***************** Bit definition for I2C_OAR1 register *****************/
vladvana	0:23d1f73bf130	5258	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
vladvana	0:23d1f73bf130	5259	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
vladvana	0:23d1f73bf130	5260
vladvana	0:23d1f73bf130	5261	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	5262	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	5263	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	5264	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	5265	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	5266	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
vladvana	0:23d1f73bf130	5267	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
vladvana	0:23d1f73bf130	5268	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
vladvana	0:23d1f73bf130	5269	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
vladvana	0:23d1f73bf130	5270	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
vladvana	0:23d1f73bf130	5271
vladvana	0:23d1f73bf130	5272	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
vladvana	0:23d1f73bf130	5273
vladvana	0:23d1f73bf130	5274	/***************** Bit definition for I2C_OAR2 register *****************/
vladvana	0:23d1f73bf130	5275	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
vladvana	0:23d1f73bf130	5276	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
vladvana	0:23d1f73bf130	5277
vladvana	0:23d1f73bf130	5278	/***************** Bit definition for I2C_SR1 register ******************/
vladvana	0:23d1f73bf130	5279	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
vladvana	0:23d1f73bf130	5280	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
vladvana	0:23d1f73bf130	5281	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
vladvana	0:23d1f73bf130	5282	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
vladvana	0:23d1f73bf130	5283	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
vladvana	0:23d1f73bf130	5284	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
vladvana	0:23d1f73bf130	5285	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
vladvana	0:23d1f73bf130	5286	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
vladvana	0:23d1f73bf130	5287	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
vladvana	0:23d1f73bf130	5288	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
vladvana	0:23d1f73bf130	5289	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
vladvana	0:23d1f73bf130	5290	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
vladvana	0:23d1f73bf130	5291	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
vladvana	0:23d1f73bf130	5292	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
vladvana	0:23d1f73bf130	5293
vladvana	0:23d1f73bf130	5294	/***************** Bit definition for I2C_SR2 register ******************/
vladvana	0:23d1f73bf130	5295	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
vladvana	0:23d1f73bf130	5296	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
vladvana	0:23d1f73bf130	5297	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
vladvana	0:23d1f73bf130	5298	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
vladvana	0:23d1f73bf130	5299	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
vladvana	0:23d1f73bf130	5300	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
vladvana	0:23d1f73bf130	5301	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
vladvana	0:23d1f73bf130	5302	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
vladvana	0:23d1f73bf130	5303
vladvana	0:23d1f73bf130	5304	/***************** Bit definition for I2C_CCR register ******************/
vladvana	0:23d1f73bf130	5305	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
vladvana	0:23d1f73bf130	5306	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
vladvana	0:23d1f73bf130	5307	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
vladvana	0:23d1f73bf130	5308
vladvana	0:23d1f73bf130	5309	/**************** Bit definition for I2C_TRISE register *****************/
vladvana	0:23d1f73bf130	5310	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
vladvana	0:23d1f73bf130	5311
vladvana	0:23d1f73bf130	5312	/******************************************************************************/
vladvana	0:23d1f73bf130	5313	/* */
vladvana	0:23d1f73bf130	5314	/* Universal Synchronous Asynchronous Receiver Transmitter */
vladvana	0:23d1f73bf130	5315	/* */
vladvana	0:23d1f73bf130	5316	/******************************************************************************/
vladvana	0:23d1f73bf130	5317
vladvana	0:23d1f73bf130	5318	/***************** Bit definition for USART_SR register *****************/
vladvana	0:23d1f73bf130	5319	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
vladvana	0:23d1f73bf130	5320	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
vladvana	0:23d1f73bf130	5321	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
vladvana	0:23d1f73bf130	5322	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
vladvana	0:23d1f73bf130	5323	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
vladvana	0:23d1f73bf130	5324	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
vladvana	0:23d1f73bf130	5325	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
vladvana	0:23d1f73bf130	5326	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
vladvana	0:23d1f73bf130	5327	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
vladvana	0:23d1f73bf130	5328	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
vladvana	0:23d1f73bf130	5329
vladvana	0:23d1f73bf130	5330	/***************** Bit definition for USART_DR register *****************/
vladvana	0:23d1f73bf130	5331	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
vladvana	0:23d1f73bf130	5332
vladvana	0:23d1f73bf130	5333	/**************** Bit definition for USART_BRR register *****************/
vladvana	0:23d1f73bf130	5334	#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
vladvana	0:23d1f73bf130	5335	#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
vladvana	0:23d1f73bf130	5336
vladvana	0:23d1f73bf130	5337	/**************** Bit definition for USART_CR1 register *****************/
vladvana	0:23d1f73bf130	5338	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
vladvana	0:23d1f73bf130	5339	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
vladvana	0:23d1f73bf130	5340	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
vladvana	0:23d1f73bf130	5341	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
vladvana	0:23d1f73bf130	5342	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
vladvana	0:23d1f73bf130	5343	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
vladvana	0:23d1f73bf130	5344	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
vladvana	0:23d1f73bf130	5345	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
vladvana	0:23d1f73bf130	5346	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
vladvana	0:23d1f73bf130	5347	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
vladvana	0:23d1f73bf130	5348	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
vladvana	0:23d1f73bf130	5349	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
vladvana	0:23d1f73bf130	5350	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
vladvana	0:23d1f73bf130	5351	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
vladvana	0:23d1f73bf130	5352
vladvana	0:23d1f73bf130	5353	/**************** Bit definition for USART_CR2 register *****************/
vladvana	0:23d1f73bf130	5354	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
vladvana	0:23d1f73bf130	5355	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
vladvana	0:23d1f73bf130	5356	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
vladvana	0:23d1f73bf130	5357	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
vladvana	0:23d1f73bf130	5358	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
vladvana	0:23d1f73bf130	5359	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
vladvana	0:23d1f73bf130	5360	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
vladvana	0:23d1f73bf130	5361
vladvana	0:23d1f73bf130	5362	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
vladvana	0:23d1f73bf130	5363	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
vladvana	0:23d1f73bf130	5364	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
vladvana	0:23d1f73bf130	5365
vladvana	0:23d1f73bf130	5366	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
vladvana	0:23d1f73bf130	5367
vladvana	0:23d1f73bf130	5368	/**************** Bit definition for USART_CR3 register *****************/
vladvana	0:23d1f73bf130	5369	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
vladvana	0:23d1f73bf130	5370	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
vladvana	0:23d1f73bf130	5371	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
vladvana	0:23d1f73bf130	5372	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
vladvana	0:23d1f73bf130	5373	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
vladvana	0:23d1f73bf130	5374	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
vladvana	0:23d1f73bf130	5375	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
vladvana	0:23d1f73bf130	5376	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
vladvana	0:23d1f73bf130	5377	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
vladvana	0:23d1f73bf130	5378	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
vladvana	0:23d1f73bf130	5379	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
vladvana	0:23d1f73bf130	5380
vladvana	0:23d1f73bf130	5381	/**************** Bit definition for USART_GTPR register ****************/
vladvana	0:23d1f73bf130	5382	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
vladvana	0:23d1f73bf130	5383	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	5384	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	5385	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	5386	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
vladvana	0:23d1f73bf130	5387	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
vladvana	0:23d1f73bf130	5388	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
vladvana	0:23d1f73bf130	5389	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
vladvana	0:23d1f73bf130	5390	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
vladvana	0:23d1f73bf130	5391
vladvana	0:23d1f73bf130	5392	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
vladvana	0:23d1f73bf130	5393
vladvana	0:23d1f73bf130	5394	/******************************************************************************/
vladvana	0:23d1f73bf130	5395	/* */
vladvana	0:23d1f73bf130	5396	/* Debug MCU */
vladvana	0:23d1f73bf130	5397	/* */
vladvana	0:23d1f73bf130	5398	/******************************************************************************/
vladvana	0:23d1f73bf130	5399
vladvana	0:23d1f73bf130	5400	/************** Bit definition for DBGMCU_IDCODE register ***************/
vladvana	0:23d1f73bf130	5401	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
vladvana	0:23d1f73bf130	5402
vladvana	0:23d1f73bf130	5403	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
vladvana	0:23d1f73bf130	5404	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
vladvana	0:23d1f73bf130	5405	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
vladvana	0:23d1f73bf130	5406	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
vladvana	0:23d1f73bf130	5407	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
vladvana	0:23d1f73bf130	5408	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
vladvana	0:23d1f73bf130	5409	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
vladvana	0:23d1f73bf130	5410	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
vladvana	0:23d1f73bf130	5411	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
vladvana	0:23d1f73bf130	5412	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
vladvana	0:23d1f73bf130	5413	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
vladvana	0:23d1f73bf130	5414	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
vladvana	0:23d1f73bf130	5415	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
vladvana	0:23d1f73bf130	5416	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
vladvana	0:23d1f73bf130	5417	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
vladvana	0:23d1f73bf130	5418	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
vladvana	0:23d1f73bf130	5419	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
vladvana	0:23d1f73bf130	5420
vladvana	0:23d1f73bf130	5421	/**************** Bit definition for DBGMCU_CR register *****************/
vladvana	0:23d1f73bf130	5422	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
vladvana	0:23d1f73bf130	5423	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
vladvana	0:23d1f73bf130	5424	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
vladvana	0:23d1f73bf130	5425	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
vladvana	0:23d1f73bf130	5426
vladvana	0:23d1f73bf130	5427	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
vladvana	0:23d1f73bf130	5428	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
vladvana	0:23d1f73bf130	5429	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
vladvana	0:23d1f73bf130	5430
vladvana	0:23d1f73bf130	5431	#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /!< Debug Independent Watchdog stopped when Core is halted /
vladvana	0:23d1f73bf130	5432	#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /!< Debug Window Watchdog stopped when Core is halted /
vladvana	0:23d1f73bf130	5433	#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /!< TIM1 counter stopped when core is halted /
vladvana	0:23d1f73bf130	5434	#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /!< TIM2 counter stopped when core is halted /
vladvana	0:23d1f73bf130	5435	#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /!< TIM3 counter stopped when core is halted /
vladvana	0:23d1f73bf130	5436	#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /!< TIM4 counter stopped when core is halted /
vladvana	0:23d1f73bf130	5437	#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /!< Debug CAN1 stopped when Core is halted /
vladvana	0:23d1f73bf130	5438	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /!< SMBUS timeout mode stopped when Core is halted /
vladvana	0:23d1f73bf130	5439	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /!< SMBUS timeout mode stopped when Core is halted /
vladvana	0:23d1f73bf130	5440
vladvana	0:23d1f73bf130	5441	/******************************************************************************/
vladvana	0:23d1f73bf130	5442	/* */
vladvana	0:23d1f73bf130	5443	/* FLASH and Option Bytes Registers */
vladvana	0:23d1f73bf130	5444	/* */
vladvana	0:23d1f73bf130	5445	/******************************************************************************/
vladvana	0:23d1f73bf130	5446	/***************** Bit definition for FLASH_ACR register ****************/
vladvana	0:23d1f73bf130	5447	#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /!< LATENCY[2:0] bits (Latency) /
vladvana	0:23d1f73bf130	5448	#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /!< Bit 0 /
vladvana	0:23d1f73bf130	5449	#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /!< Bit 1 /
vladvana	0:23d1f73bf130	5450	#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /!< Bit 2 /
vladvana	0:23d1f73bf130	5451
vladvana	0:23d1f73bf130	5452	#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /!< Flash Half Cycle Access Enable /
vladvana	0:23d1f73bf130	5453	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
vladvana	0:23d1f73bf130	5454	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
vladvana	0:23d1f73bf130	5455
vladvana	0:23d1f73bf130	5456	/**************** Bit definition for FLASH_KEYR register ****************/
vladvana	0:23d1f73bf130	5457	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
vladvana	0:23d1f73bf130	5458
vladvana	0:23d1f73bf130	5459	#define RDP_KEY ((uint32_t)0x000000A5) /!< RDP Key /
vladvana	0:23d1f73bf130	5460	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
vladvana	0:23d1f73bf130	5461	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
vladvana	0:23d1f73bf130	5462
vladvana	0:23d1f73bf130	5463	/*************** Bit definition for FLASH_OPTKEYR register **************/
vladvana	0:23d1f73bf130	5464	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
vladvana	0:23d1f73bf130	5465
vladvana	0:23d1f73bf130	5466	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
vladvana	0:23d1f73bf130	5467	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
vladvana	0:23d1f73bf130	5468
vladvana	0:23d1f73bf130	5469	/**************** Bit definition for FLASH_SR register ******************/
vladvana	0:23d1f73bf130	5470	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
vladvana	0:23d1f73bf130	5471	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
vladvana	0:23d1f73bf130	5472	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
vladvana	0:23d1f73bf130	5473	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
vladvana	0:23d1f73bf130	5474
vladvana	0:23d1f73bf130	5475	/***************** Bit definition for FLASH_CR register *****************/
vladvana	0:23d1f73bf130	5476	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
vladvana	0:23d1f73bf130	5477	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
vladvana	0:23d1f73bf130	5478	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
vladvana	0:23d1f73bf130	5479	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
vladvana	0:23d1f73bf130	5480	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
vladvana	0:23d1f73bf130	5481	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
vladvana	0:23d1f73bf130	5482	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
vladvana	0:23d1f73bf130	5483	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
vladvana	0:23d1f73bf130	5484	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
vladvana	0:23d1f73bf130	5485	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
vladvana	0:23d1f73bf130	5486
vladvana	0:23d1f73bf130	5487	/***************** Bit definition for FLASH_AR register *****************/
vladvana	0:23d1f73bf130	5488	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
vladvana	0:23d1f73bf130	5489
vladvana	0:23d1f73bf130	5490	/**************** Bit definition for FLASH_OBR register *****************/
vladvana	0:23d1f73bf130	5491	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
vladvana	0:23d1f73bf130	5492	#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /!< Read protection /
vladvana	0:23d1f73bf130	5493
vladvana	0:23d1f73bf130	5494	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /!< IWDG SW /
vladvana	0:23d1f73bf130	5495	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /!< nRST_STOP /
vladvana	0:23d1f73bf130	5496	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /!< nRST_STDBY /
vladvana	0:23d1f73bf130	5497	#define FLASH_OBR_USER ((uint32_t)0x0000001C) /!< User Option Bytes /
vladvana	0:23d1f73bf130	5498
vladvana	0:23d1f73bf130	5499	/**************** Bit definition for FLASH_WRPR register ****************/
vladvana	0:23d1f73bf130	5500	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
vladvana	0:23d1f73bf130	5501
vladvana	0:23d1f73bf130	5502	/----------------------------------------------------------------------------/
vladvana	0:23d1f73bf130	5503
vladvana	0:23d1f73bf130	5504	/**************** Bit definition for FLASH_RDP register *****************/
vladvana	0:23d1f73bf130	5505	#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
vladvana	0:23d1f73bf130	5506	#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
vladvana	0:23d1f73bf130	5507
vladvana	0:23d1f73bf130	5508	/**************** Bit definition for FLASH_USER register ****************/
vladvana	0:23d1f73bf130	5509	#define FLASH_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
vladvana	0:23d1f73bf130	5510	#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
vladvana	0:23d1f73bf130	5511
vladvana	0:23d1f73bf130	5512	/**************** Bit definition for FLASH_Data0 register ***************/
vladvana	0:23d1f73bf130	5513	#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /!< User data storage option byte /
vladvana	0:23d1f73bf130	5514	#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /!< User data storage complemented option byte /
vladvana	0:23d1f73bf130	5515
vladvana	0:23d1f73bf130	5516	/**************** Bit definition for FLASH_Data1 register ***************/
vladvana	0:23d1f73bf130	5517	#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /!< User data storage option byte /
vladvana	0:23d1f73bf130	5518	#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /!< User data storage complemented option byte /
vladvana	0:23d1f73bf130	5519
vladvana	0:23d1f73bf130	5520	/**************** Bit definition for FLASH_WRP0 register ****************/
vladvana	0:23d1f73bf130	5521	#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
vladvana	0:23d1f73bf130	5522	#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
vladvana	0:23d1f73bf130	5523
vladvana	0:23d1f73bf130	5524	/**************** Bit definition for FLASH_WRP1 register ****************/
vladvana	0:23d1f73bf130	5525	#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
vladvana	0:23d1f73bf130	5526	#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
vladvana	0:23d1f73bf130	5527
vladvana	0:23d1f73bf130	5528	/**************** Bit definition for FLASH_WRP2 register ****************/
vladvana	0:23d1f73bf130	5529	#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
vladvana	0:23d1f73bf130	5530	#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
vladvana	0:23d1f73bf130	5531
vladvana	0:23d1f73bf130	5532	/**************** Bit definition for FLASH_WRP3 register ****************/
vladvana	0:23d1f73bf130	5533	#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
vladvana	0:23d1f73bf130	5534	#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
vladvana	0:23d1f73bf130	5535
vladvana	0:23d1f73bf130	5536
vladvana	0:23d1f73bf130	5537
vladvana	0:23d1f73bf130	5538	/**
vladvana	0:23d1f73bf130	5539	* @}
vladvana	0:23d1f73bf130	5540	*/
vladvana	0:23d1f73bf130	5541
vladvana	0:23d1f73bf130	5542	/**
vladvana	0:23d1f73bf130	5543	* @}
vladvana	0:23d1f73bf130	5544	*/
vladvana	0:23d1f73bf130	5545
vladvana	0:23d1f73bf130	5546	/** @addtogroup Exported_macro
vladvana	0:23d1f73bf130	5547	* @{
vladvana	0:23d1f73bf130	5548	*/
vladvana	0:23d1f73bf130	5549
vladvana	0:23d1f73bf130	5550	/**************************** ADC Instances *******************************/
vladvana	0:23d1f73bf130	5551	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
vladvana	0:23d1f73bf130	5552	((INSTANCE) == ADC2))
vladvana	0:23d1f73bf130	5553
vladvana	0:23d1f73bf130	5554	#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
vladvana	0:23d1f73bf130	5555
vladvana	0:23d1f73bf130	5556	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
vladvana	0:23d1f73bf130	5557
vladvana	0:23d1f73bf130	5558
vladvana	0:23d1f73bf130	5559	/**************************** CAN Instances *******************************/
vladvana	0:23d1f73bf130	5560	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
vladvana	0:23d1f73bf130	5561
vladvana	0:23d1f73bf130	5562	/**************************** CRC Instances *******************************/
vladvana	0:23d1f73bf130	5563	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
vladvana	0:23d1f73bf130	5564
vladvana	0:23d1f73bf130	5565	/**************************** DAC Instances *******************************/
vladvana	0:23d1f73bf130	5566
vladvana	0:23d1f73bf130	5567	/**************************** DMA Instances *******************************/
vladvana	0:23d1f73bf130	5568	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
vladvana	0:23d1f73bf130	5569	((INSTANCE) == DMA1_Channel2) \|\| \
vladvana	0:23d1f73bf130	5570	((INSTANCE) == DMA1_Channel3) \|\| \
vladvana	0:23d1f73bf130	5571	((INSTANCE) == DMA1_Channel4) \|\| \
vladvana	0:23d1f73bf130	5572	((INSTANCE) == DMA1_Channel5) \|\| \
vladvana	0:23d1f73bf130	5573	((INSTANCE) == DMA1_Channel6) \|\| \
vladvana	0:23d1f73bf130	5574	((INSTANCE) == DMA1_Channel7))
vladvana	0:23d1f73bf130	5575
vladvana	0:23d1f73bf130	5576	/***************************** GPIO Instances *****************************/
vladvana	0:23d1f73bf130	5577	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
vladvana	0:23d1f73bf130	5578	((INSTANCE) == GPIOB) \|\| \
vladvana	0:23d1f73bf130	5579	((INSTANCE) == GPIOC) \|\| \
vladvana	0:23d1f73bf130	5580	((INSTANCE) == GPIOD) \|\| \
vladvana	0:23d1f73bf130	5581	((INSTANCE) == GPIOE))
vladvana	0:23d1f73bf130	5582
vladvana	0:23d1f73bf130	5583	/************************** GPIO Alternate Function Instances *************/
vladvana	0:23d1f73bf130	5584	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
vladvana	0:23d1f73bf130	5585
vladvana	0:23d1f73bf130	5586	/************************** GPIO Lock Instances ***************************/
vladvana	0:23d1f73bf130	5587	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
vladvana	0:23d1f73bf130	5588
vladvana	0:23d1f73bf130	5589	/****************************** I2C Instances *****************************/
vladvana	0:23d1f73bf130	5590	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
vladvana	0:23d1f73bf130	5591	((INSTANCE) == I2C2))
vladvana	0:23d1f73bf130	5592
vladvana	0:23d1f73bf130	5593	/**************************** IWDG Instances ******************************/
vladvana	0:23d1f73bf130	5594	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
vladvana	0:23d1f73bf130	5595
vladvana	0:23d1f73bf130	5596	/****************************** SPI Instances *****************************/
vladvana	0:23d1f73bf130	5597	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
vladvana	0:23d1f73bf130	5598	((INSTANCE) == SPI2))
vladvana	0:23d1f73bf130	5599
vladvana	0:23d1f73bf130	5600	/**************************** START TIM Instances *************************/
vladvana	0:23d1f73bf130	5601	/**************************** TIM Instances *******************************/
vladvana	0:23d1f73bf130	5602	#define IS_TIM_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5603	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5604	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5605	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5606	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5607
vladvana	0:23d1f73bf130	5608	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5609	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5610	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5611	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5612	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5613
vladvana	0:23d1f73bf130	5614	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5615	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5616	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5617	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5618	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5619
vladvana	0:23d1f73bf130	5620	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5621	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5622	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5623	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5624	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5625
vladvana	0:23d1f73bf130	5626	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5627	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5628	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5629	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5630	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5631
vladvana	0:23d1f73bf130	5632	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5633	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5634	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5635	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5636	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5637
vladvana	0:23d1f73bf130	5638	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5639	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5640	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5641	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5642	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5643
vladvana	0:23d1f73bf130	5644	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5645	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5646	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5647	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5648	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5649
vladvana	0:23d1f73bf130	5650	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5651	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5652	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5653	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5654	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5655
vladvana	0:23d1f73bf130	5656	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5657	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5658	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5659	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5660	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5661
vladvana	0:23d1f73bf130	5662	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5663	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5664	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5665	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5666	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5667
vladvana	0:23d1f73bf130	5668	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5669	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5670	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5671	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5672	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5673
vladvana	0:23d1f73bf130	5674	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5675	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5676	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5677	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5678	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5679
vladvana	0:23d1f73bf130	5680	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5681	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5682	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5683	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5684	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5685
vladvana	0:23d1f73bf130	5686	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5687	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5688	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5689	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5690	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5691
vladvana	0:23d1f73bf130	5692	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5693	((INSTANCE) == TIM1)
vladvana	0:23d1f73bf130	5694
vladvana	0:23d1f73bf130	5695	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
vladvana	0:23d1f73bf130	5696	((((INSTANCE) == TIM1) && \
vladvana	0:23d1f73bf130	5697	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	5698	((CHANNEL) == TIM_CHANNEL_2) \|\| \
vladvana	0:23d1f73bf130	5699	((CHANNEL) == TIM_CHANNEL_3) \|\| \
vladvana	0:23d1f73bf130	5700	((CHANNEL) == TIM_CHANNEL_4))) \
vladvana	0:23d1f73bf130	5701	\|\| \
vladvana	0:23d1f73bf130	5702	(((INSTANCE) == TIM2) && \
vladvana	0:23d1f73bf130	5703	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	5704	((CHANNEL) == TIM_CHANNEL_2) \|\| \
vladvana	0:23d1f73bf130	5705	((CHANNEL) == TIM_CHANNEL_3) \|\| \
vladvana	0:23d1f73bf130	5706	((CHANNEL) == TIM_CHANNEL_4))) \
vladvana	0:23d1f73bf130	5707	\|\| \
vladvana	0:23d1f73bf130	5708	(((INSTANCE) == TIM3) && \
vladvana	0:23d1f73bf130	5709	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	5710	((CHANNEL) == TIM_CHANNEL_2) \|\| \
vladvana	0:23d1f73bf130	5711	((CHANNEL) == TIM_CHANNEL_3) \|\| \
vladvana	0:23d1f73bf130	5712	((CHANNEL) == TIM_CHANNEL_4))) \
vladvana	0:23d1f73bf130	5713	\|\| \
vladvana	0:23d1f73bf130	5714	(((INSTANCE) == TIM4) && \
vladvana	0:23d1f73bf130	5715	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	5716	((CHANNEL) == TIM_CHANNEL_2) \|\| \
vladvana	0:23d1f73bf130	5717	((CHANNEL) == TIM_CHANNEL_3) \|\| \
vladvana	0:23d1f73bf130	5718	((CHANNEL) == TIM_CHANNEL_4))))
vladvana	0:23d1f73bf130	5719
vladvana	0:23d1f73bf130	5720	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
vladvana	0:23d1f73bf130	5721	(((INSTANCE) == TIM1) && \
vladvana	0:23d1f73bf130	5722	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
vladvana	0:23d1f73bf130	5723	((CHANNEL) == TIM_CHANNEL_2) \|\| \
vladvana	0:23d1f73bf130	5724	((CHANNEL) == TIM_CHANNEL_3)))
vladvana	0:23d1f73bf130	5725
vladvana	0:23d1f73bf130	5726	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5727	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5728	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5729	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5730	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5731
vladvana	0:23d1f73bf130	5732	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5733	((INSTANCE) == TIM1)
vladvana	0:23d1f73bf130	5734
vladvana	0:23d1f73bf130	5735	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5736	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5737	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5738	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5739	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5740
vladvana	0:23d1f73bf130	5741	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5742	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5743	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5744	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5745	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5746
vladvana	0:23d1f73bf130	5747	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5748	(((INSTANCE) == TIM1) \|\| \
vladvana	0:23d1f73bf130	5749	((INSTANCE) == TIM2) \|\| \
vladvana	0:23d1f73bf130	5750	((INSTANCE) == TIM3) \|\| \
vladvana	0:23d1f73bf130	5751	((INSTANCE) == TIM4))
vladvana	0:23d1f73bf130	5752
vladvana	0:23d1f73bf130	5753	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
vladvana	0:23d1f73bf130	5754	((INSTANCE) == TIM1)
vladvana	0:23d1f73bf130	5755
vladvana	0:23d1f73bf130	5756	/**************************** END TIM Instances ***************************/
vladvana	0:23d1f73bf130	5757
vladvana	0:23d1f73bf130	5758
vladvana	0:23d1f73bf130	5759	/****************** USART Instances : Synchronous mode ********************/
vladvana	0:23d1f73bf130	5760	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5761	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5762	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5763
vladvana	0:23d1f73bf130	5764	/****************** UART Instances : Asynchronous mode ********************/
vladvana	0:23d1f73bf130	5765	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5766	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5767	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5768
vladvana	0:23d1f73bf130	5769	/****************** UART Instances : Half-Duplex mode ********************/
vladvana	0:23d1f73bf130	5770	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5771	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5772	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5773
vladvana	0:23d1f73bf130	5774	/****************** UART Instances : LIN mode ********************/
vladvana	0:23d1f73bf130	5775	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5776	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5777	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5778
vladvana	0:23d1f73bf130	5779	/**************** UART Instances : Hardware Flow control ******************/
vladvana	0:23d1f73bf130	5780	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5781	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5782	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5783
vladvana	0:23d1f73bf130	5784	/******************* UART Instances : Smard card mode *********************/
vladvana	0:23d1f73bf130	5785	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5786	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5787	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5788
vladvana	0:23d1f73bf130	5789	/********************* UART Instances : IRDA mode *************************/
vladvana	0:23d1f73bf130	5790	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5791	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5792	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5793
vladvana	0:23d1f73bf130	5794	/*************** UART Instances : Multi-Processor mode ********************/
vladvana	0:23d1f73bf130	5795	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5796	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5797	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5798
vladvana	0:23d1f73bf130	5799	/*************** UART Instances : DMA mode available ********************/
vladvana	0:23d1f73bf130	5800	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
vladvana	0:23d1f73bf130	5801	((INSTANCE) == USART2) \|\| \
vladvana	0:23d1f73bf130	5802	((INSTANCE) == USART3))
vladvana	0:23d1f73bf130	5803
vladvana	0:23d1f73bf130	5804	/**************************** RTC Instances *******************************/
vladvana	0:23d1f73bf130	5805	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
vladvana	0:23d1f73bf130	5806
vladvana	0:23d1f73bf130	5807	/************************** WWDG Instances ***************************/
vladvana	0:23d1f73bf130	5808	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
vladvana	0:23d1f73bf130	5809
vladvana	0:23d1f73bf130	5810	/**************************** USB Instances ******************************/
vladvana	0:23d1f73bf130	5811	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
vladvana	0:23d1f73bf130	5812
vladvana	0:23d1f73bf130	5813
vladvana	0:23d1f73bf130	5814
vladvana	0:23d1f73bf130	5815
vladvana	0:23d1f73bf130	5816	/**
vladvana	0:23d1f73bf130	5817	* @}
vladvana	0:23d1f73bf130	5818	*/
vladvana	0:23d1f73bf130	5819	/******************************************************************************/
vladvana	0:23d1f73bf130	5820	/* For a painless codes migration between the STM32F1xx device product */
vladvana	0:23d1f73bf130	5821	/* lines, the aliases defined below are put in place to overcome the */
vladvana	0:23d1f73bf130	5822	/* differences in the interrupt handlers and IRQn definitions. */
vladvana	0:23d1f73bf130	5823	/* No need to update developed interrupt code when moving across */
vladvana	0:23d1f73bf130	5824	/* product lines within the same STM32F1 Family */
vladvana	0:23d1f73bf130	5825	/******************************************************************************/
vladvana	0:23d1f73bf130	5826
vladvana	0:23d1f73bf130	5827	/* Aliases for __IRQn */
vladvana	0:23d1f73bf130	5828	#define ADC1_IRQn ADC1_2_IRQn
vladvana	0:23d1f73bf130	5829
vladvana	0:23d1f73bf130	5830
vladvana	0:23d1f73bf130	5831
vladvana	0:23d1f73bf130	5832	#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
vladvana	0:23d1f73bf130	5833	#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
vladvana	0:23d1f73bf130	5834
vladvana	0:23d1f73bf130	5835	#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
vladvana	0:23d1f73bf130	5836	#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
vladvana	0:23d1f73bf130	5837
vladvana	0:23d1f73bf130	5838
vladvana	0:23d1f73bf130	5839
vladvana	0:23d1f73bf130	5840	#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
vladvana	0:23d1f73bf130	5841	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
vladvana	0:23d1f73bf130	5842	#define TIM9_IRQn TIM1_BRK_IRQn
vladvana	0:23d1f73bf130	5843
vladvana	0:23d1f73bf130	5844	#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
vladvana	0:23d1f73bf130	5845	#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
vladvana	0:23d1f73bf130	5846	#define TIM10_IRQn TIM1_UP_IRQn
vladvana	0:23d1f73bf130	5847
vladvana	0:23d1f73bf130	5848	#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
vladvana	0:23d1f73bf130	5849	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
vladvana	0:23d1f73bf130	5850	#define TIM11_IRQn TIM1_TRG_COM_IRQn
vladvana	0:23d1f73bf130	5851
vladvana	0:23d1f73bf130	5852	#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
vladvana	0:23d1f73bf130	5853	#define CEC_IRQn USBWakeUp_IRQn
vladvana	0:23d1f73bf130	5854
vladvana	0:23d1f73bf130	5855
vladvana	0:23d1f73bf130	5856
vladvana	0:23d1f73bf130	5857
vladvana	0:23d1f73bf130	5858	/* Aliases for __IRQHandler */
vladvana	0:23d1f73bf130	5859	#define ADC1_IRQHandler ADC1_2_IRQHandler
vladvana	0:23d1f73bf130	5860
vladvana	0:23d1f73bf130	5861
vladvana	0:23d1f73bf130	5862
vladvana	0:23d1f73bf130	5863	#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
vladvana	0:23d1f73bf130	5864	#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
vladvana	0:23d1f73bf130	5865
vladvana	0:23d1f73bf130	5866	#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
vladvana	0:23d1f73bf130	5867	#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
vladvana	0:23d1f73bf130	5868
vladvana	0:23d1f73bf130	5869
vladvana	0:23d1f73bf130	5870
vladvana	0:23d1f73bf130	5871	#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
vladvana	0:23d1f73bf130	5872	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
vladvana	0:23d1f73bf130	5873	#define TIM9_IRQHandler TIM1_BRK_IRQHandler
vladvana	0:23d1f73bf130	5874
vladvana	0:23d1f73bf130	5875	#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
vladvana	0:23d1f73bf130	5876	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
vladvana	0:23d1f73bf130	5877	#define TIM10_IRQHandler TIM1_UP_IRQHandler
vladvana	0:23d1f73bf130	5878
vladvana	0:23d1f73bf130	5879	#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
vladvana	0:23d1f73bf130	5880	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
vladvana	0:23d1f73bf130	5881	#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
vladvana	0:23d1f73bf130	5882
vladvana	0:23d1f73bf130	5883	#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
vladvana	0:23d1f73bf130	5884	#define CEC_IRQHandler USBWakeUp_IRQHandler
vladvana	0:23d1f73bf130	5885
vladvana	0:23d1f73bf130	5886
vladvana	0:23d1f73bf130	5887
vladvana	0:23d1f73bf130	5888
vladvana	0:23d1f73bf130	5889	/**
vladvana	0:23d1f73bf130	5890	* @}
vladvana	0:23d1f73bf130	5891	*/
vladvana	0:23d1f73bf130	5892
vladvana	0:23d1f73bf130	5893	/**
vladvana	0:23d1f73bf130	5894	* @}
vladvana	0:23d1f73bf130	5895	*/
vladvana	0:23d1f73bf130	5896
vladvana	0:23d1f73bf130	5897
vladvana	0:23d1f73bf130	5898	#ifdef __cplusplus
vladvana	0:23d1f73bf130	5899	}
vladvana	0:23d1f73bf130	5900	#endif /* __cplusplus */
vladvana	0:23d1f73bf130	5901
vladvana	0:23d1f73bf130	5902	#endif /* __STM32F103xB_H */
vladvana	0:23d1f73bf130	5903
vladvana	0:23d1f73bf130	5904
vladvana	0:23d1f73bf130	5905
vladvana	0:23d1f73bf130	5906	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	24 Sep 2017
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F103RB/stm32f103xb.h@0:23d1f73bf130, 2017-09-24 (annotated)

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