Vladimir Vana / mbed

pro vyuku PSS v Jecne

TARGET_NUCLEO_F103RB/core_cmFunc.h@0:23d1f73bf130, 2017-09-24 (annotated)

Committer:
vladvana
Date:
Sun Sep 24 12:31:52 2017 +0000
Revision:
0:23d1f73bf130
podklady pro cviceni z PSS

Who changed what in which revision?

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vladvana 0:23d1f73bf130 1 /**************************************************************************//**
vladvana 0:23d1f73bf130 2 * @file core_cmFunc.h
vladvana 0:23d1f73bf130 3 * @brief CMSIS Cortex-M Core Function Access Header File
vladvana 0:23d1f73bf130 4 * @version V4.10
vladvana 0:23d1f73bf130 5 * @date 18. March 2015
vladvana 0:23d1f73bf130 6 *
vladvana 0:23d1f73bf130 7 * @note
vladvana 0:23d1f73bf130 8 *
vladvana 0:23d1f73bf130 9 ******************************************************************************/
vladvana 0:23d1f73bf130 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
vladvana 0:23d1f73bf130 11
vladvana 0:23d1f73bf130 12 All rights reserved.
vladvana 0:23d1f73bf130 13 Redistribution and use in source and binary forms, with or without
vladvana 0:23d1f73bf130 14 modification, are permitted provided that the following conditions are met:
vladvana 0:23d1f73bf130 15 - Redistributions of source code must retain the above copyright
vladvana 0:23d1f73bf130 16 notice, this list of conditions and the following disclaimer.
vladvana 0:23d1f73bf130 17 - Redistributions in binary form must reproduce the above copyright
vladvana 0:23d1f73bf130 18 notice, this list of conditions and the following disclaimer in the
vladvana 0:23d1f73bf130 19 documentation and/or other materials provided with the distribution.
vladvana 0:23d1f73bf130 20 - Neither the name of ARM nor the names of its contributors may be used
vladvana 0:23d1f73bf130 21 to endorse or promote products derived from this software without
vladvana 0:23d1f73bf130 22 specific prior written permission.
vladvana 0:23d1f73bf130 23 *
vladvana 0:23d1f73bf130 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vladvana 0:23d1f73bf130 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vladvana 0:23d1f73bf130 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vladvana 0:23d1f73bf130 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vladvana 0:23d1f73bf130 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vladvana 0:23d1f73bf130 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vladvana 0:23d1f73bf130 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vladvana 0:23d1f73bf130 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vladvana 0:23d1f73bf130 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vladvana 0:23d1f73bf130 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vladvana 0:23d1f73bf130 34 POSSIBILITY OF SUCH DAMAGE.
vladvana 0:23d1f73bf130 35 ---------------------------------------------------------------------------*/
vladvana 0:23d1f73bf130 36
vladvana 0:23d1f73bf130 37
vladvana 0:23d1f73bf130 38 #ifndef __CORE_CMFUNC_H
vladvana 0:23d1f73bf130 39 #define __CORE_CMFUNC_H
vladvana 0:23d1f73bf130 40
vladvana 0:23d1f73bf130 41
vladvana 0:23d1f73bf130 42 /* ########################### Core Function Access ########################### */
vladvana 0:23d1f73bf130 43 /** \ingroup CMSIS_Core_FunctionInterface
vladvana 0:23d1f73bf130 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
vladvana 0:23d1f73bf130 45 @{
vladvana 0:23d1f73bf130 46 */
vladvana 0:23d1f73bf130 47
vladvana 0:23d1f73bf130 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
vladvana 0:23d1f73bf130 49 /* ARM armcc specific functions */
vladvana 0:23d1f73bf130 50
vladvana 0:23d1f73bf130 51 #if (__ARMCC_VERSION < 400677)
vladvana 0:23d1f73bf130 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
vladvana 0:23d1f73bf130 53 #endif
vladvana 0:23d1f73bf130 54
vladvana 0:23d1f73bf130 55 /* intrinsic void __enable_irq(); */
vladvana 0:23d1f73bf130 56 /* intrinsic void __disable_irq(); */
vladvana 0:23d1f73bf130 57
vladvana 0:23d1f73bf130 58 /** \brief Get Control Register
vladvana 0:23d1f73bf130 59
vladvana 0:23d1f73bf130 60 This function returns the content of the Control Register.
vladvana 0:23d1f73bf130 61
vladvana 0:23d1f73bf130 62 \return Control Register value
vladvana 0:23d1f73bf130 63 */
vladvana 0:23d1f73bf130 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
vladvana 0:23d1f73bf130 65 {
vladvana 0:23d1f73bf130 66 register uint32_t __regControl __ASM("control");
vladvana 0:23d1f73bf130 67 return(__regControl);
vladvana 0:23d1f73bf130 68 }
vladvana 0:23d1f73bf130 69
vladvana 0:23d1f73bf130 70
vladvana 0:23d1f73bf130 71 /** \brief Set Control Register
vladvana 0:23d1f73bf130 72
vladvana 0:23d1f73bf130 73 This function writes the given value to the Control Register.
vladvana 0:23d1f73bf130 74
vladvana 0:23d1f73bf130 75 \param [in] control Control Register value to set
vladvana 0:23d1f73bf130 76 */
vladvana 0:23d1f73bf130 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
vladvana 0:23d1f73bf130 78 {
vladvana 0:23d1f73bf130 79 register uint32_t __regControl __ASM("control");
vladvana 0:23d1f73bf130 80 __regControl = control;
vladvana 0:23d1f73bf130 81 }
vladvana 0:23d1f73bf130 82
vladvana 0:23d1f73bf130 83
vladvana 0:23d1f73bf130 84 /** \brief Get IPSR Register
vladvana 0:23d1f73bf130 85
vladvana 0:23d1f73bf130 86 This function returns the content of the IPSR Register.
vladvana 0:23d1f73bf130 87
vladvana 0:23d1f73bf130 88 \return IPSR Register value
vladvana 0:23d1f73bf130 89 */
vladvana 0:23d1f73bf130 90 __STATIC_INLINE uint32_t __get_IPSR(void)
vladvana 0:23d1f73bf130 91 {
vladvana 0:23d1f73bf130 92 register uint32_t __regIPSR __ASM("ipsr");
vladvana 0:23d1f73bf130 93 return(__regIPSR);
vladvana 0:23d1f73bf130 94 }
vladvana 0:23d1f73bf130 95
vladvana 0:23d1f73bf130 96
vladvana 0:23d1f73bf130 97 /** \brief Get APSR Register
vladvana 0:23d1f73bf130 98
vladvana 0:23d1f73bf130 99 This function returns the content of the APSR Register.
vladvana 0:23d1f73bf130 100
vladvana 0:23d1f73bf130 101 \return APSR Register value
vladvana 0:23d1f73bf130 102 */
vladvana 0:23d1f73bf130 103 __STATIC_INLINE uint32_t __get_APSR(void)
vladvana 0:23d1f73bf130 104 {
vladvana 0:23d1f73bf130 105 register uint32_t __regAPSR __ASM("apsr");
vladvana 0:23d1f73bf130 106 return(__regAPSR);
vladvana 0:23d1f73bf130 107 }
vladvana 0:23d1f73bf130 108
vladvana 0:23d1f73bf130 109
vladvana 0:23d1f73bf130 110 /** \brief Get xPSR Register
vladvana 0:23d1f73bf130 111
vladvana 0:23d1f73bf130 112 This function returns the content of the xPSR Register.
vladvana 0:23d1f73bf130 113
vladvana 0:23d1f73bf130 114 \return xPSR Register value
vladvana 0:23d1f73bf130 115 */
vladvana 0:23d1f73bf130 116 __STATIC_INLINE uint32_t __get_xPSR(void)
vladvana 0:23d1f73bf130 117 {
vladvana 0:23d1f73bf130 118 register uint32_t __regXPSR __ASM("xpsr");
vladvana 0:23d1f73bf130 119 return(__regXPSR);
vladvana 0:23d1f73bf130 120 }
vladvana 0:23d1f73bf130 121
vladvana 0:23d1f73bf130 122
vladvana 0:23d1f73bf130 123 /** \brief Get Process Stack Pointer
vladvana 0:23d1f73bf130 124
vladvana 0:23d1f73bf130 125 This function returns the current value of the Process Stack Pointer (PSP).
vladvana 0:23d1f73bf130 126
vladvana 0:23d1f73bf130 127 \return PSP Register value
vladvana 0:23d1f73bf130 128 */
vladvana 0:23d1f73bf130 129 __STATIC_INLINE uint32_t __get_PSP(void)
vladvana 0:23d1f73bf130 130 {
vladvana 0:23d1f73bf130 131 register uint32_t __regProcessStackPointer __ASM("psp");
vladvana 0:23d1f73bf130 132 return(__regProcessStackPointer);
vladvana 0:23d1f73bf130 133 }
vladvana 0:23d1f73bf130 134
vladvana 0:23d1f73bf130 135
vladvana 0:23d1f73bf130 136 /** \brief Set Process Stack Pointer
vladvana 0:23d1f73bf130 137
vladvana 0:23d1f73bf130 138 This function assigns the given value to the Process Stack Pointer (PSP).
vladvana 0:23d1f73bf130 139
vladvana 0:23d1f73bf130 140 \param [in] topOfProcStack Process Stack Pointer value to set
vladvana 0:23d1f73bf130 141 */
vladvana 0:23d1f73bf130 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
vladvana 0:23d1f73bf130 143 {
vladvana 0:23d1f73bf130 144 register uint32_t __regProcessStackPointer __ASM("psp");
vladvana 0:23d1f73bf130 145 __regProcessStackPointer = topOfProcStack;
vladvana 0:23d1f73bf130 146 }
vladvana 0:23d1f73bf130 147
vladvana 0:23d1f73bf130 148
vladvana 0:23d1f73bf130 149 /** \brief Get Main Stack Pointer
vladvana 0:23d1f73bf130 150
vladvana 0:23d1f73bf130 151 This function returns the current value of the Main Stack Pointer (MSP).
vladvana 0:23d1f73bf130 152
vladvana 0:23d1f73bf130 153 \return MSP Register value
vladvana 0:23d1f73bf130 154 */
vladvana 0:23d1f73bf130 155 __STATIC_INLINE uint32_t __get_MSP(void)
vladvana 0:23d1f73bf130 156 {
vladvana 0:23d1f73bf130 157 register uint32_t __regMainStackPointer __ASM("msp");
vladvana 0:23d1f73bf130 158 return(__regMainStackPointer);
vladvana 0:23d1f73bf130 159 }
vladvana 0:23d1f73bf130 160
vladvana 0:23d1f73bf130 161
vladvana 0:23d1f73bf130 162 /** \brief Set Main Stack Pointer
vladvana 0:23d1f73bf130 163
vladvana 0:23d1f73bf130 164 This function assigns the given value to the Main Stack Pointer (MSP).
vladvana 0:23d1f73bf130 165
vladvana 0:23d1f73bf130 166 \param [in] topOfMainStack Main Stack Pointer value to set
vladvana 0:23d1f73bf130 167 */
vladvana 0:23d1f73bf130 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
vladvana 0:23d1f73bf130 169 {
vladvana 0:23d1f73bf130 170 register uint32_t __regMainStackPointer __ASM("msp");
vladvana 0:23d1f73bf130 171 __regMainStackPointer = topOfMainStack;
vladvana 0:23d1f73bf130 172 }
vladvana 0:23d1f73bf130 173
vladvana 0:23d1f73bf130 174
vladvana 0:23d1f73bf130 175 /** \brief Get Priority Mask
vladvana 0:23d1f73bf130 176
vladvana 0:23d1f73bf130 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
vladvana 0:23d1f73bf130 178
vladvana 0:23d1f73bf130 179 \return Priority Mask value
vladvana 0:23d1f73bf130 180 */
vladvana 0:23d1f73bf130 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
vladvana 0:23d1f73bf130 182 {
vladvana 0:23d1f73bf130 183 register uint32_t __regPriMask __ASM("primask");
vladvana 0:23d1f73bf130 184 return(__regPriMask);
vladvana 0:23d1f73bf130 185 }
vladvana 0:23d1f73bf130 186
vladvana 0:23d1f73bf130 187
vladvana 0:23d1f73bf130 188 /** \brief Set Priority Mask
vladvana 0:23d1f73bf130 189
vladvana 0:23d1f73bf130 190 This function assigns the given value to the Priority Mask Register.
vladvana 0:23d1f73bf130 191
vladvana 0:23d1f73bf130 192 \param [in] priMask Priority Mask
vladvana 0:23d1f73bf130 193 */
vladvana 0:23d1f73bf130 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
vladvana 0:23d1f73bf130 195 {
vladvana 0:23d1f73bf130 196 register uint32_t __regPriMask __ASM("primask");
vladvana 0:23d1f73bf130 197 __regPriMask = (priMask);
vladvana 0:23d1f73bf130 198 }
vladvana 0:23d1f73bf130 199
vladvana 0:23d1f73bf130 200
vladvana 0:23d1f73bf130 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
vladvana 0:23d1f73bf130 202
vladvana 0:23d1f73bf130 203 /** \brief Enable FIQ
vladvana 0:23d1f73bf130 204
vladvana 0:23d1f73bf130 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
vladvana 0:23d1f73bf130 206 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 207 */
vladvana 0:23d1f73bf130 208 #define __enable_fault_irq __enable_fiq
vladvana 0:23d1f73bf130 209
vladvana 0:23d1f73bf130 210
vladvana 0:23d1f73bf130 211 /** \brief Disable FIQ
vladvana 0:23d1f73bf130 212
vladvana 0:23d1f73bf130 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
vladvana 0:23d1f73bf130 214 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 215 */
vladvana 0:23d1f73bf130 216 #define __disable_fault_irq __disable_fiq
vladvana 0:23d1f73bf130 217
vladvana 0:23d1f73bf130 218
vladvana 0:23d1f73bf130 219 /** \brief Get Base Priority
vladvana 0:23d1f73bf130 220
vladvana 0:23d1f73bf130 221 This function returns the current value of the Base Priority register.
vladvana 0:23d1f73bf130 222
vladvana 0:23d1f73bf130 223 \return Base Priority register value
vladvana 0:23d1f73bf130 224 */
vladvana 0:23d1f73bf130 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
vladvana 0:23d1f73bf130 226 {
vladvana 0:23d1f73bf130 227 register uint32_t __regBasePri __ASM("basepri");
vladvana 0:23d1f73bf130 228 return(__regBasePri);
vladvana 0:23d1f73bf130 229 }
vladvana 0:23d1f73bf130 230
vladvana 0:23d1f73bf130 231
vladvana 0:23d1f73bf130 232 /** \brief Set Base Priority
vladvana 0:23d1f73bf130 233
vladvana 0:23d1f73bf130 234 This function assigns the given value to the Base Priority register.
vladvana 0:23d1f73bf130 235
vladvana 0:23d1f73bf130 236 \param [in] basePri Base Priority value to set
vladvana 0:23d1f73bf130 237 */
vladvana 0:23d1f73bf130 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
vladvana 0:23d1f73bf130 239 {
vladvana 0:23d1f73bf130 240 register uint32_t __regBasePri __ASM("basepri");
vladvana 0:23d1f73bf130 241 __regBasePri = (basePri & 0xff);
vladvana 0:23d1f73bf130 242 }
vladvana 0:23d1f73bf130 243
vladvana 0:23d1f73bf130 244
vladvana 0:23d1f73bf130 245 /** \brief Set Base Priority with condition
vladvana 0:23d1f73bf130 246
vladvana 0:23d1f73bf130 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
vladvana 0:23d1f73bf130 248 or the new value increases the BASEPRI priority level.
vladvana 0:23d1f73bf130 249
vladvana 0:23d1f73bf130 250 \param [in] basePri Base Priority value to set
vladvana 0:23d1f73bf130 251 */
vladvana 0:23d1f73bf130 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
vladvana 0:23d1f73bf130 253 {
vladvana 0:23d1f73bf130 254 register uint32_t __regBasePriMax __ASM("basepri_max");
vladvana 0:23d1f73bf130 255 __regBasePriMax = (basePri & 0xff);
vladvana 0:23d1f73bf130 256 }
vladvana 0:23d1f73bf130 257
vladvana 0:23d1f73bf130 258
vladvana 0:23d1f73bf130 259 /** \brief Get Fault Mask
vladvana 0:23d1f73bf130 260
vladvana 0:23d1f73bf130 261 This function returns the current value of the Fault Mask register.
vladvana 0:23d1f73bf130 262
vladvana 0:23d1f73bf130 263 \return Fault Mask register value
vladvana 0:23d1f73bf130 264 */
vladvana 0:23d1f73bf130 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
vladvana 0:23d1f73bf130 266 {
vladvana 0:23d1f73bf130 267 register uint32_t __regFaultMask __ASM("faultmask");
vladvana 0:23d1f73bf130 268 return(__regFaultMask);
vladvana 0:23d1f73bf130 269 }
vladvana 0:23d1f73bf130 270
vladvana 0:23d1f73bf130 271
vladvana 0:23d1f73bf130 272 /** \brief Set Fault Mask
vladvana 0:23d1f73bf130 273
vladvana 0:23d1f73bf130 274 This function assigns the given value to the Fault Mask register.
vladvana 0:23d1f73bf130 275
vladvana 0:23d1f73bf130 276 \param [in] faultMask Fault Mask value to set
vladvana 0:23d1f73bf130 277 */
vladvana 0:23d1f73bf130 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
vladvana 0:23d1f73bf130 279 {
vladvana 0:23d1f73bf130 280 register uint32_t __regFaultMask __ASM("faultmask");
vladvana 0:23d1f73bf130 281 __regFaultMask = (faultMask & (uint32_t)1);
vladvana 0:23d1f73bf130 282 }
vladvana 0:23d1f73bf130 283
vladvana 0:23d1f73bf130 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
vladvana 0:23d1f73bf130 285
vladvana 0:23d1f73bf130 286
vladvana 0:23d1f73bf130 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
vladvana 0:23d1f73bf130 288
vladvana 0:23d1f73bf130 289 /** \brief Get FPSCR
vladvana 0:23d1f73bf130 290
vladvana 0:23d1f73bf130 291 This function returns the current value of the Floating Point Status/Control register.
vladvana 0:23d1f73bf130 292
vladvana 0:23d1f73bf130 293 \return Floating Point Status/Control register value
vladvana 0:23d1f73bf130 294 */
vladvana 0:23d1f73bf130 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
vladvana 0:23d1f73bf130 296 {
vladvana 0:23d1f73bf130 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vladvana 0:23d1f73bf130 298 register uint32_t __regfpscr __ASM("fpscr");
vladvana 0:23d1f73bf130 299 return(__regfpscr);
vladvana 0:23d1f73bf130 300 #else
vladvana 0:23d1f73bf130 301 return(0);
vladvana 0:23d1f73bf130 302 #endif
vladvana 0:23d1f73bf130 303 }
vladvana 0:23d1f73bf130 304
vladvana 0:23d1f73bf130 305
vladvana 0:23d1f73bf130 306 /** \brief Set FPSCR
vladvana 0:23d1f73bf130 307
vladvana 0:23d1f73bf130 308 This function assigns the given value to the Floating Point Status/Control register.
vladvana 0:23d1f73bf130 309
vladvana 0:23d1f73bf130 310 \param [in] fpscr Floating Point Status/Control value to set
vladvana 0:23d1f73bf130 311 */
vladvana 0:23d1f73bf130 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
vladvana 0:23d1f73bf130 313 {
vladvana 0:23d1f73bf130 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vladvana 0:23d1f73bf130 315 register uint32_t __regfpscr __ASM("fpscr");
vladvana 0:23d1f73bf130 316 __regfpscr = (fpscr);
vladvana 0:23d1f73bf130 317 #endif
vladvana 0:23d1f73bf130 318 }
vladvana 0:23d1f73bf130 319
vladvana 0:23d1f73bf130 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
vladvana 0:23d1f73bf130 321
vladvana 0:23d1f73bf130 322
vladvana 0:23d1f73bf130 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
vladvana 0:23d1f73bf130 324 /* GNU gcc specific functions */
vladvana 0:23d1f73bf130 325
vladvana 0:23d1f73bf130 326 /** \brief Enable IRQ Interrupts
vladvana 0:23d1f73bf130 327
vladvana 0:23d1f73bf130 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
vladvana 0:23d1f73bf130 329 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 330 */
vladvana 0:23d1f73bf130 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
vladvana 0:23d1f73bf130 332 {
vladvana 0:23d1f73bf130 333 __ASM volatile ("cpsie i" : : : "memory");
vladvana 0:23d1f73bf130 334 }
vladvana 0:23d1f73bf130 335
vladvana 0:23d1f73bf130 336
vladvana 0:23d1f73bf130 337 /** \brief Disable IRQ Interrupts
vladvana 0:23d1f73bf130 338
vladvana 0:23d1f73bf130 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
vladvana 0:23d1f73bf130 340 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 341 */
vladvana 0:23d1f73bf130 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
vladvana 0:23d1f73bf130 343 {
vladvana 0:23d1f73bf130 344 __ASM volatile ("cpsid i" : : : "memory");
vladvana 0:23d1f73bf130 345 }
vladvana 0:23d1f73bf130 346
vladvana 0:23d1f73bf130 347
vladvana 0:23d1f73bf130 348 /** \brief Get Control Register
vladvana 0:23d1f73bf130 349
vladvana 0:23d1f73bf130 350 This function returns the content of the Control Register.
vladvana 0:23d1f73bf130 351
vladvana 0:23d1f73bf130 352 \return Control Register value
vladvana 0:23d1f73bf130 353 */
vladvana 0:23d1f73bf130 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
vladvana 0:23d1f73bf130 355 {
vladvana 0:23d1f73bf130 356 uint32_t result;
vladvana 0:23d1f73bf130 357
vladvana 0:23d1f73bf130 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
vladvana 0:23d1f73bf130 359 return(result);
vladvana 0:23d1f73bf130 360 }
vladvana 0:23d1f73bf130 361
vladvana 0:23d1f73bf130 362
vladvana 0:23d1f73bf130 363 /** \brief Set Control Register
vladvana 0:23d1f73bf130 364
vladvana 0:23d1f73bf130 365 This function writes the given value to the Control Register.
vladvana 0:23d1f73bf130 366
vladvana 0:23d1f73bf130 367 \param [in] control Control Register value to set
vladvana 0:23d1f73bf130 368 */
vladvana 0:23d1f73bf130 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
vladvana 0:23d1f73bf130 370 {
vladvana 0:23d1f73bf130 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
vladvana 0:23d1f73bf130 372 }
vladvana 0:23d1f73bf130 373
vladvana 0:23d1f73bf130 374
vladvana 0:23d1f73bf130 375 /** \brief Get IPSR Register
vladvana 0:23d1f73bf130 376
vladvana 0:23d1f73bf130 377 This function returns the content of the IPSR Register.
vladvana 0:23d1f73bf130 378
vladvana 0:23d1f73bf130 379 \return IPSR Register value
vladvana 0:23d1f73bf130 380 */
vladvana 0:23d1f73bf130 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
vladvana 0:23d1f73bf130 382 {
vladvana 0:23d1f73bf130 383 uint32_t result;
vladvana 0:23d1f73bf130 384
vladvana 0:23d1f73bf130 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
vladvana 0:23d1f73bf130 386 return(result);
vladvana 0:23d1f73bf130 387 }
vladvana 0:23d1f73bf130 388
vladvana 0:23d1f73bf130 389
vladvana 0:23d1f73bf130 390 /** \brief Get APSR Register
vladvana 0:23d1f73bf130 391
vladvana 0:23d1f73bf130 392 This function returns the content of the APSR Register.
vladvana 0:23d1f73bf130 393
vladvana 0:23d1f73bf130 394 \return APSR Register value
vladvana 0:23d1f73bf130 395 */
vladvana 0:23d1f73bf130 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
vladvana 0:23d1f73bf130 397 {
vladvana 0:23d1f73bf130 398 uint32_t result;
vladvana 0:23d1f73bf130 399
vladvana 0:23d1f73bf130 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
vladvana 0:23d1f73bf130 401 return(result);
vladvana 0:23d1f73bf130 402 }
vladvana 0:23d1f73bf130 403
vladvana 0:23d1f73bf130 404
vladvana 0:23d1f73bf130 405 /** \brief Get xPSR Register
vladvana 0:23d1f73bf130 406
vladvana 0:23d1f73bf130 407 This function returns the content of the xPSR Register.
vladvana 0:23d1f73bf130 408
vladvana 0:23d1f73bf130 409 \return xPSR Register value
vladvana 0:23d1f73bf130 410 */
vladvana 0:23d1f73bf130 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
vladvana 0:23d1f73bf130 412 {
vladvana 0:23d1f73bf130 413 uint32_t result;
vladvana 0:23d1f73bf130 414
vladvana 0:23d1f73bf130 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
vladvana 0:23d1f73bf130 416 return(result);
vladvana 0:23d1f73bf130 417 }
vladvana 0:23d1f73bf130 418
vladvana 0:23d1f73bf130 419
vladvana 0:23d1f73bf130 420 /** \brief Get Process Stack Pointer
vladvana 0:23d1f73bf130 421
vladvana 0:23d1f73bf130 422 This function returns the current value of the Process Stack Pointer (PSP).
vladvana 0:23d1f73bf130 423
vladvana 0:23d1f73bf130 424 \return PSP Register value
vladvana 0:23d1f73bf130 425 */
vladvana 0:23d1f73bf130 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
vladvana 0:23d1f73bf130 427 {
vladvana 0:23d1f73bf130 428 register uint32_t result;
vladvana 0:23d1f73bf130 429
vladvana 0:23d1f73bf130 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
vladvana 0:23d1f73bf130 431 return(result);
vladvana 0:23d1f73bf130 432 }
vladvana 0:23d1f73bf130 433
vladvana 0:23d1f73bf130 434
vladvana 0:23d1f73bf130 435 /** \brief Set Process Stack Pointer
vladvana 0:23d1f73bf130 436
vladvana 0:23d1f73bf130 437 This function assigns the given value to the Process Stack Pointer (PSP).
vladvana 0:23d1f73bf130 438
vladvana 0:23d1f73bf130 439 \param [in] topOfProcStack Process Stack Pointer value to set
vladvana 0:23d1f73bf130 440 */
vladvana 0:23d1f73bf130 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
vladvana 0:23d1f73bf130 442 {
vladvana 0:23d1f73bf130 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
vladvana 0:23d1f73bf130 444 }
vladvana 0:23d1f73bf130 445
vladvana 0:23d1f73bf130 446
vladvana 0:23d1f73bf130 447 /** \brief Get Main Stack Pointer
vladvana 0:23d1f73bf130 448
vladvana 0:23d1f73bf130 449 This function returns the current value of the Main Stack Pointer (MSP).
vladvana 0:23d1f73bf130 450
vladvana 0:23d1f73bf130 451 \return MSP Register value
vladvana 0:23d1f73bf130 452 */
vladvana 0:23d1f73bf130 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
vladvana 0:23d1f73bf130 454 {
vladvana 0:23d1f73bf130 455 register uint32_t result;
vladvana 0:23d1f73bf130 456
vladvana 0:23d1f73bf130 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
vladvana 0:23d1f73bf130 458 return(result);
vladvana 0:23d1f73bf130 459 }
vladvana 0:23d1f73bf130 460
vladvana 0:23d1f73bf130 461
vladvana 0:23d1f73bf130 462 /** \brief Set Main Stack Pointer
vladvana 0:23d1f73bf130 463
vladvana 0:23d1f73bf130 464 This function assigns the given value to the Main Stack Pointer (MSP).
vladvana 0:23d1f73bf130 465
vladvana 0:23d1f73bf130 466 \param [in] topOfMainStack Main Stack Pointer value to set
vladvana 0:23d1f73bf130 467 */
vladvana 0:23d1f73bf130 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
vladvana 0:23d1f73bf130 469 {
vladvana 0:23d1f73bf130 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
vladvana 0:23d1f73bf130 471 }
vladvana 0:23d1f73bf130 472
vladvana 0:23d1f73bf130 473
vladvana 0:23d1f73bf130 474 /** \brief Get Priority Mask
vladvana 0:23d1f73bf130 475
vladvana 0:23d1f73bf130 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
vladvana 0:23d1f73bf130 477
vladvana 0:23d1f73bf130 478 \return Priority Mask value
vladvana 0:23d1f73bf130 479 */
vladvana 0:23d1f73bf130 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
vladvana 0:23d1f73bf130 481 {
vladvana 0:23d1f73bf130 482 uint32_t result;
vladvana 0:23d1f73bf130 483
vladvana 0:23d1f73bf130 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
vladvana 0:23d1f73bf130 485 return(result);
vladvana 0:23d1f73bf130 486 }
vladvana 0:23d1f73bf130 487
vladvana 0:23d1f73bf130 488
vladvana 0:23d1f73bf130 489 /** \brief Set Priority Mask
vladvana 0:23d1f73bf130 490
vladvana 0:23d1f73bf130 491 This function assigns the given value to the Priority Mask Register.
vladvana 0:23d1f73bf130 492
vladvana 0:23d1f73bf130 493 \param [in] priMask Priority Mask
vladvana 0:23d1f73bf130 494 */
vladvana 0:23d1f73bf130 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
vladvana 0:23d1f73bf130 496 {
vladvana 0:23d1f73bf130 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
vladvana 0:23d1f73bf130 498 }
vladvana 0:23d1f73bf130 499
vladvana 0:23d1f73bf130 500
vladvana 0:23d1f73bf130 501 #if (__CORTEX_M >= 0x03)
vladvana 0:23d1f73bf130 502
vladvana 0:23d1f73bf130 503 /** \brief Enable FIQ
vladvana 0:23d1f73bf130 504
vladvana 0:23d1f73bf130 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
vladvana 0:23d1f73bf130 506 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 507 */
vladvana 0:23d1f73bf130 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
vladvana 0:23d1f73bf130 509 {
vladvana 0:23d1f73bf130 510 __ASM volatile ("cpsie f" : : : "memory");
vladvana 0:23d1f73bf130 511 }
vladvana 0:23d1f73bf130 512
vladvana 0:23d1f73bf130 513
vladvana 0:23d1f73bf130 514 /** \brief Disable FIQ
vladvana 0:23d1f73bf130 515
vladvana 0:23d1f73bf130 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
vladvana 0:23d1f73bf130 517 Can only be executed in Privileged modes.
vladvana 0:23d1f73bf130 518 */
vladvana 0:23d1f73bf130 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
vladvana 0:23d1f73bf130 520 {
vladvana 0:23d1f73bf130 521 __ASM volatile ("cpsid f" : : : "memory");
vladvana 0:23d1f73bf130 522 }
vladvana 0:23d1f73bf130 523
vladvana 0:23d1f73bf130 524
vladvana 0:23d1f73bf130 525 /** \brief Get Base Priority
vladvana 0:23d1f73bf130 526
vladvana 0:23d1f73bf130 527 This function returns the current value of the Base Priority register.
vladvana 0:23d1f73bf130 528
vladvana 0:23d1f73bf130 529 \return Base Priority register value
vladvana 0:23d1f73bf130 530 */
vladvana 0:23d1f73bf130 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
vladvana 0:23d1f73bf130 532 {
vladvana 0:23d1f73bf130 533 uint32_t result;
vladvana 0:23d1f73bf130 534
vladvana 0:23d1f73bf130 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
vladvana 0:23d1f73bf130 536 return(result);
vladvana 0:23d1f73bf130 537 }
vladvana 0:23d1f73bf130 538
vladvana 0:23d1f73bf130 539
vladvana 0:23d1f73bf130 540 /** \brief Set Base Priority
vladvana 0:23d1f73bf130 541
vladvana 0:23d1f73bf130 542 This function assigns the given value to the Base Priority register.
vladvana 0:23d1f73bf130 543
vladvana 0:23d1f73bf130 544 \param [in] basePri Base Priority value to set
vladvana 0:23d1f73bf130 545 */
vladvana 0:23d1f73bf130 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
vladvana 0:23d1f73bf130 547 {
vladvana 0:23d1f73bf130 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
vladvana 0:23d1f73bf130 549 }
vladvana 0:23d1f73bf130 550
vladvana 0:23d1f73bf130 551
vladvana 0:23d1f73bf130 552 /** \brief Set Base Priority with condition
vladvana 0:23d1f73bf130 553
vladvana 0:23d1f73bf130 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
vladvana 0:23d1f73bf130 555 or the new value increases the BASEPRI priority level.
vladvana 0:23d1f73bf130 556
vladvana 0:23d1f73bf130 557 \param [in] basePri Base Priority value to set
vladvana 0:23d1f73bf130 558 */
vladvana 0:23d1f73bf130 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
vladvana 0:23d1f73bf130 560 {
vladvana 0:23d1f73bf130 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
vladvana 0:23d1f73bf130 562 }
vladvana 0:23d1f73bf130 563
vladvana 0:23d1f73bf130 564
vladvana 0:23d1f73bf130 565 /** \brief Get Fault Mask
vladvana 0:23d1f73bf130 566
vladvana 0:23d1f73bf130 567 This function returns the current value of the Fault Mask register.
vladvana 0:23d1f73bf130 568
vladvana 0:23d1f73bf130 569 \return Fault Mask register value
vladvana 0:23d1f73bf130 570 */
vladvana 0:23d1f73bf130 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
vladvana 0:23d1f73bf130 572 {
vladvana 0:23d1f73bf130 573 uint32_t result;
vladvana 0:23d1f73bf130 574
vladvana 0:23d1f73bf130 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
vladvana 0:23d1f73bf130 576 return(result);
vladvana 0:23d1f73bf130 577 }
vladvana 0:23d1f73bf130 578
vladvana 0:23d1f73bf130 579
vladvana 0:23d1f73bf130 580 /** \brief Set Fault Mask
vladvana 0:23d1f73bf130 581
vladvana 0:23d1f73bf130 582 This function assigns the given value to the Fault Mask register.
vladvana 0:23d1f73bf130 583
vladvana 0:23d1f73bf130 584 \param [in] faultMask Fault Mask value to set
vladvana 0:23d1f73bf130 585 */
vladvana 0:23d1f73bf130 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
vladvana 0:23d1f73bf130 587 {
vladvana 0:23d1f73bf130 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
vladvana 0:23d1f73bf130 589 }
vladvana 0:23d1f73bf130 590
vladvana 0:23d1f73bf130 591 #endif /* (__CORTEX_M >= 0x03) */
vladvana 0:23d1f73bf130 592
vladvana 0:23d1f73bf130 593
vladvana 0:23d1f73bf130 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
vladvana 0:23d1f73bf130 595
vladvana 0:23d1f73bf130 596 /** \brief Get FPSCR
vladvana 0:23d1f73bf130 597
vladvana 0:23d1f73bf130 598 This function returns the current value of the Floating Point Status/Control register.
vladvana 0:23d1f73bf130 599
vladvana 0:23d1f73bf130 600 \return Floating Point Status/Control register value
vladvana 0:23d1f73bf130 601 */
vladvana 0:23d1f73bf130 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
vladvana 0:23d1f73bf130 603 {
vladvana 0:23d1f73bf130 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vladvana 0:23d1f73bf130 605 uint32_t result;
vladvana 0:23d1f73bf130 606
vladvana 0:23d1f73bf130 607 /* Empty asm statement works as a scheduling barrier */
vladvana 0:23d1f73bf130 608 __ASM volatile ("");
vladvana 0:23d1f73bf130 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
vladvana 0:23d1f73bf130 610 __ASM volatile ("");
vladvana 0:23d1f73bf130 611 return(result);
vladvana 0:23d1f73bf130 612 #else
vladvana 0:23d1f73bf130 613 return(0);
vladvana 0:23d1f73bf130 614 #endif
vladvana 0:23d1f73bf130 615 }
vladvana 0:23d1f73bf130 616
vladvana 0:23d1f73bf130 617
vladvana 0:23d1f73bf130 618 /** \brief Set FPSCR
vladvana 0:23d1f73bf130 619
vladvana 0:23d1f73bf130 620 This function assigns the given value to the Floating Point Status/Control register.
vladvana 0:23d1f73bf130 621
vladvana 0:23d1f73bf130 622 \param [in] fpscr Floating Point Status/Control value to set
vladvana 0:23d1f73bf130 623 */
vladvana 0:23d1f73bf130 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
vladvana 0:23d1f73bf130 625 {
vladvana 0:23d1f73bf130 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vladvana 0:23d1f73bf130 627 /* Empty asm statement works as a scheduling barrier */
vladvana 0:23d1f73bf130 628 __ASM volatile ("");
vladvana 0:23d1f73bf130 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
vladvana 0:23d1f73bf130 630 __ASM volatile ("");
vladvana 0:23d1f73bf130 631 #endif
vladvana 0:23d1f73bf130 632 }
vladvana 0:23d1f73bf130 633
vladvana 0:23d1f73bf130 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
vladvana 0:23d1f73bf130 635
vladvana 0:23d1f73bf130 636
vladvana 0:23d1f73bf130 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
vladvana 0:23d1f73bf130 638 /* IAR iccarm specific functions */
vladvana 0:23d1f73bf130 639 #include <cmsis_iar.h>
vladvana 0:23d1f73bf130 640
vladvana 0:23d1f73bf130 641
vladvana 0:23d1f73bf130 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
vladvana 0:23d1f73bf130 643 /* TI CCS specific functions */
vladvana 0:23d1f73bf130 644 #include <cmsis_ccs.h>
vladvana 0:23d1f73bf130 645
vladvana 0:23d1f73bf130 646
vladvana 0:23d1f73bf130 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
vladvana 0:23d1f73bf130 648 /* TASKING carm specific functions */
vladvana 0:23d1f73bf130 649 /*
vladvana 0:23d1f73bf130 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
vladvana 0:23d1f73bf130 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
vladvana 0:23d1f73bf130 652 * Including the CMSIS ones.
vladvana 0:23d1f73bf130 653 */
vladvana 0:23d1f73bf130 654
vladvana 0:23d1f73bf130 655
vladvana 0:23d1f73bf130 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
vladvana 0:23d1f73bf130 657 /* Cosmic specific functions */
vladvana 0:23d1f73bf130 658 #include <cmsis_csm.h>
vladvana 0:23d1f73bf130 659
vladvana 0:23d1f73bf130 660 #endif
vladvana 0:23d1f73bf130 661
vladvana 0:23d1f73bf130 662 /*@} end of CMSIS_Core_RegAccFunctions */
vladvana 0:23d1f73bf130 663
vladvana 0:23d1f73bf130 664 #endif /* __CORE_CMFUNC_H */