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PGA280.h@1:533ce2102fcc, 2020-06-22 (annotated)

Committer:
vitlog
Date:
Mon Jun 22 09:51:45 2020 +0000
Revision:
1:533ce2102fcc
Parent:
0:f9ba28ab9f4c 
ne pomnyu chto pomenyal

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vitlog 0:f9ba28ab9f4c 1 #ifndef _PGA280_ARDUINO_H /* Guard against multiple inclusion */
vitlog 0:f9ba28ab9f4c 2 #define _PGA280_ARDUINO_H
vitlog 0:f9ba28ab9f4c 3 #include <stdint.h>
vitlog 0:f9ba28ab9f4c 4 #include "PerifConfig.h"
vitlog 0:f9ba28ab9f4c 5 //#include <stdbool.h>
vitlog 0:f9ba28ab9f4c 6 //#include <stddef.h>
vitlog 0:f9ba28ab9f4c 7 //#include <stdlib.h>
vitlog 0:f9ba28ab9f4c 8
vitlog 0:f9ba28ab9f4c 9 /* Provide C++ Compatibility */
vitlog 0:f9ba28ab9f4c 10 #ifdef __cplusplus
vitlog 0:f9ba28ab9f4c 11 extern "C" {
vitlog 0:f9ba28ab9f4c 12 #endif
vitlog 0:f9ba28ab9f4c 13
vitlog 0:f9ba28ab9f4c 14 // commands
vitlog 0:f9ba28ab9f4c 15 #define WRITE_BUF_PGA280 0x60
vitlog 0:f9ba28ab9f4c 16 #define WRITE_PGA280 0x40
vitlog 0:f9ba28ab9f4c 17 #define READ_PGA280 0x80
vitlog 0:f9ba28ab9f4c 18 #define CS_DIRECT_BUF_PGA280 0xE0
vitlog 0:f9ba28ab9f4c 19 #define CS_DIRECT_PGA280 0xC0
vitlog 0:f9ba28ab9f4c 20
vitlog 0:f9ba28ab9f4c 21 // registers адреса регистров
vitlog 0:f9ba28ab9f4c 22 #define PGA280_MUX_GAIN_ADR 0x00
vitlog 0:f9ba28ab9f4c 23 #define PGA280_RESET_ADR 0x01
vitlog 0:f9ba28ab9f4c 24 #define PGA280_SPI_MODE_ADR 0x02
vitlog 0:f9ba28ab9f4c 25 #define PGA280_BUF_TIMEOUT_ADR 0x03
vitlog 0:f9ba28ab9f4c 26 #define PGA280_ERROR_ADR 0x04
vitlog 0:f9ba28ab9f4c 27 #define PGA280_GPIO_DATA_ADR 0x05
vitlog 0:f9ba28ab9f4c 28 #define PGA280_INPUT_SWITCH0_ADR 0x06
vitlog 0:f9ba28ab9f4c 29 #define PGA280_INPUT_SWITCH1_ADR 0x07
vitlog 0:f9ba28ab9f4c 30 #define PGA280_GPIO_DIR_ADR 0x08
vitlog 0:f9ba28ab9f4c 31 #define PGA280_CS_MODE_ADR 0x09
vitlog 0:f9ba28ab9f4c 32 #define PGA280_CONFIG0_ADR 0x0A
vitlog 0:f9ba28ab9f4c 33 #define PGA280_CONFIG1_ADR 0x0B
vitlog 0:f9ba28ab9f4c 34 #define PGA280_SP_FUNCTION_ADR 0x0C
vitlog 0:f9ba28ab9f4c 35
vitlog 0:f9ba28ab9f4c 36 // Gain
vitlog 0:f9ba28ab9f4c 37 #define GAIN_1_8_PGA280 0x00
vitlog 0:f9ba28ab9f4c 38 #define GAIN_1_4_PGA280 0x01
vitlog 0:f9ba28ab9f4c 39 #define GAIN_1_2_PGA280 0x02
vitlog 0:f9ba28ab9f4c 40 #define GAIN_1_PGA280 0x03
vitlog 0:f9ba28ab9f4c 41 #define GAIN_2_PGA280 0x04
vitlog 0:f9ba28ab9f4c 42 #define GAIN_4_PGA280 0x05
vitlog 0:f9ba28ab9f4c 43 #define GAIN_8_PGA280 0x06
vitlog 0:f9ba28ab9f4c 44 #define GAIN_16_PGA280 0x07
vitlog 0:f9ba28ab9f4c 45 #define GAIN_32_PGA280 0x08
vitlog 0:f9ba28ab9f4c 46 #define GAIN_64_PGA280 0x09
vitlog 0:f9ba28ab9f4c 47 #define GAIN_128_PGA280 0x0A
vitlog 0:f9ba28ab9f4c 48
vitlog 0:f9ba28ab9f4c 49 namespace pga280{};
vitlog 0:f9ba28ab9f4c 50 using namespace pga280;
vitlog 0:f9ba28ab9f4c 51
vitlog 0:f9ba28ab9f4c 52 /*Удобное обращение к регистрам если не требуется высокая скорость*/
vitlog 0:f9ba28ab9f4c 53
vitlog 0:f9ba28ab9f4c 54 //Register 0 - Gain and Optional MUX Register (название из даташита)
vitlog 0:f9ba28ab9f4c 55 typedef union {
vitlog 0:f9ba28ab9f4c 56 struct {
vitlog 0:f9ba28ab9f4c 57 uint8_t
vitlog 0:f9ba28ab9f4c 58 MUX0:1,
vitlog 0:f9ba28ab9f4c 59 MUX1:1,
vitlog 0:f9ba28ab9f4c 60 MUX2:1,
vitlog 0:f9ba28ab9f4c 61 G0:1,
vitlog 0:f9ba28ab9f4c 62 G1:1,
vitlog 0:f9ba28ab9f4c 63 G2:1,
vitlog 0:f9ba28ab9f4c 64 G3:1,
vitlog 0:f9ba28ab9f4c 65 G4:1;
vitlog 0:f9ba28ab9f4c 66 };
vitlog 0:f9ba28ab9f4c 67 struct {
vitlog 0:f9ba28ab9f4c 68 uint8_t MUX:3;
vitlog 0:f9ba28ab9f4c 69 uint8_t GAIN:4;
vitlog 0:f9ba28ab9f4c 70 uint8_t :1;
vitlog 1:533ce2102fcc 71 };
vitlog 1:533ce2102fcc 72 uint8_t w;
vitlog 1:533ce2102fcc 73
vitlog 0:f9ba28ab9f4c 74 }__PGA280_MUX_GAIN_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 75 extern __PGA280_MUX_GAIN_t PGA280_MUX_GAIN; //объявление переменной
vitlog 0:f9ba28ab9f4c 76
vitlog 0:f9ba28ab9f4c 77 //Register 2 - SPI: MODE Selection to GPIO-Pin (название из даташита)
vitlog 0:f9ba28ab9f4c 78 typedef union {
vitlog 0:f9ba28ab9f4c 79 struct {
vitlog 0:f9ba28ab9f4c 80 uint8_t
vitlog 0:f9ba28ab9f4c 81 CP0:1,
vitlog 0:f9ba28ab9f4c 82 CP1:1,
vitlog 0:f9ba28ab9f4c 83 CP2:1,
vitlog 0:f9ba28ab9f4c 84 CP3:1,
vitlog 0:f9ba28ab9f4c 85 CP4:1,
vitlog 0:f9ba28ab9f4c 86 CP5:1,
vitlog 0:f9ba28ab9f4c 87 CP6:1,
vitlog 0:f9ba28ab9f4c 88 :1;
vitlog 0:f9ba28ab9f4c 89 };
vitlog 0:f9ba28ab9f4c 90 struct {
vitlog 0:f9ba28ab9f4c 91 uint8_t CP:7;
vitlog 0:f9ba28ab9f4c 92 uint8_t :1;
vitlog 0:f9ba28ab9f4c 93 };
vitlog 0:f9ba28ab9f4c 94 struct {
vitlog 0:f9ba28ab9f4c 95 uint8_t w:8;
vitlog 0:f9ba28ab9f4c 96 };
vitlog 0:f9ba28ab9f4c 97 }__PGA280_SPI_MODE_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 98 extern __PGA280_SPI_MODE_t PGA280_SPI_MODE; //объявление переменной
vitlog 0:f9ba28ab9f4c 99
vitlog 0:f9ba28ab9f4c 100 //Register 3 - BUF Timeout Register (название из даташита)
vitlog 0:f9ba28ab9f4c 101 typedef union {
vitlog 0:f9ba28ab9f4c 102 struct {
vitlog 0:f9ba28ab9f4c 103 uint8_t
vitlog 0:f9ba28ab9f4c 104 BUFTIM0:1,
vitlog 0:f9ba28ab9f4c 105 BUFTIM1:1,
vitlog 0:f9ba28ab9f4c 106 BUFTIM2:1,
vitlog 0:f9ba28ab9f4c 107 BUFTIM3:1,
vitlog 0:f9ba28ab9f4c 108 BUFTIM4:1,
vitlog 0:f9ba28ab9f4c 109 BUFTIM5:1,
vitlog 0:f9ba28ab9f4c 110 :2;
vitlog 0:f9ba28ab9f4c 111 };
vitlog 0:f9ba28ab9f4c 112 struct {
vitlog 0:f9ba28ab9f4c 113 uint8_t BUFTIM:6;
vitlog 0:f9ba28ab9f4c 114 uint8_t :2;
vitlog 0:f9ba28ab9f4c 115 };
vitlog 0:f9ba28ab9f4c 116 struct {
vitlog 0:f9ba28ab9f4c 117 uint8_t w:8;
vitlog 0:f9ba28ab9f4c 118 };
vitlog 0:f9ba28ab9f4c 119 }__PGA280_BUF_TIMEOUT_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 120 extern __PGA280_BUF_TIMEOUT_t PGA280_BUF_TIMEOUT; //объявление переменной
vitlog 0:f9ba28ab9f4c 121
vitlog 0:f9ba28ab9f4c 122 //Register 4 - Error Register (название из даташита)
vitlog 0:f9ba28ab9f4c 123 typedef union {
vitlog 0:f9ba28ab9f4c 124 struct {
vitlog 0:f9ba28ab9f4c 125 uint8_t
vitlog 0:f9ba28ab9f4c 126 IOVerr:1, //Input Overvoltage
vitlog 0:f9ba28ab9f4c 127 GAINerr:1, //Gain Network Overload
vitlog 0:f9ba28ab9f4c 128 OUTerr:1, //Output Stage Error (allow approximately 6µs activation delay).
vitlog 0:f9ba28ab9f4c 129 EF:1, //Error Flag. Logic OR combination of error bits of Register 10. This bit can be connected to GPIO3 pin if the bit is configured for output (Register 8) and as a special function (Register 12).
vitlog 0:f9ba28ab9f4c 130 ICAerr:1, //Input Clamp Active
vitlog 0:f9ba28ab9f4c 131 BUFA:1, // Buffer Active
vitlog 0:f9ba28ab9f4c 132 IARerr:1, //Input Amplifier Saturation
vitlog 0:f9ba28ab9f4c 133 CHKerr:1; //Checksum error in SPI. This bit is only active if checksum is enabled.
vitlog 0:f9ba28ab9f4c 134 //This bit is set to 1 when the checksum byte is incorrect.
vitlog 0:f9ba28ab9f4c 135 };
vitlog 0:f9ba28ab9f4c 136 struct {
vitlog 0:f9ba28ab9f4c 137 uint8_t ERR:8;
vitlog 0:f9ba28ab9f4c 138 };
vitlog 0:f9ba28ab9f4c 139 }__PGA280_ERROR_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 140 extern __PGA280_ERROR_t PGA280_ERROR; //объявление переменной
vitlog 0:f9ba28ab9f4c 141
vitlog 0:f9ba28ab9f4c 142 //Register 5 - GPIO Register (название из даташита)
vitlog 0:f9ba28ab9f4c 143 typedef union {
vitlog 0:f9ba28ab9f4c 144 struct {
vitlog 0:f9ba28ab9f4c 145 uint8_t
vitlog 0:f9ba28ab9f4c 146 GPIO0:1,
vitlog 0:f9ba28ab9f4c 147 GPIO1:1,
vitlog 0:f9ba28ab9f4c 148 GPIO2:1,
vitlog 0:f9ba28ab9f4c 149 GPIO3:1,
vitlog 0:f9ba28ab9f4c 150 GPIO4:1,
vitlog 0:f9ba28ab9f4c 151 GPIO5:1,
vitlog 0:f9ba28ab9f4c 152 GPIO6:1,
vitlog 0:f9ba28ab9f4c 153 :1;
vitlog 0:f9ba28ab9f4c 154 };
vitlog 0:f9ba28ab9f4c 155 struct {
vitlog 0:f9ba28ab9f4c 156 uint8_t GPIO:7;
vitlog 0:f9ba28ab9f4c 157 uint8_t :1;
vitlog 0:f9ba28ab9f4c 158 };
vitlog 0:f9ba28ab9f4c 159 struct {
vitlog 0:f9ba28ab9f4c 160 uint8_t w:8;
vitlog 0:f9ba28ab9f4c 161 };
vitlog 0:f9ba28ab9f4c 162 }__PGA280_GPIO_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 163 extern __PGA280_GPIO_t PGA280_GPIO; //объявление переменной
vitlog 0:f9ba28ab9f4c 164
vitlog 0:f9ba28ab9f4c 165 //Register 6 - Input Switch Control Register 1 (название из даташита)
vitlog 0:f9ba28ab9f4c 166 typedef union {
vitlog 0:f9ba28ab9f4c 167 struct {
vitlog 0:f9ba28ab9f4c 168 uint8_t
vitlog 0:f9ba28ab9f4c 169 SW_D12:1,
vitlog 0:f9ba28ab9f4c 170 SW_C2:1,
vitlog 0:f9ba28ab9f4c 171 SW_C1:1,
vitlog 0:f9ba28ab9f4c 172 SW_B2:1,
vitlog 0:f9ba28ab9f4c 173 SW_B1:1,
vitlog 0:f9ba28ab9f4c 174 SW_A2:1,
vitlog 0:f9ba28ab9f4c 175 SW_A1:1,
vitlog 0:f9ba28ab9f4c 176 :1;
vitlog 0:f9ba28ab9f4c 177 };
vitlog 0:f9ba28ab9f4c 178 struct {
vitlog 0:f9ba28ab9f4c 179 uint8_t SWCR0:7;
vitlog 0:f9ba28ab9f4c 180 uint8_t :1;
vitlog 0:f9ba28ab9f4c 181 };
vitlog 0:f9ba28ab9f4c 182 struct {
vitlog 0:f9ba28ab9f4c 183 uint8_t w:8;
vitlog 0:f9ba28ab9f4c 184 };
vitlog 0:f9ba28ab9f4c 185 }__PGA280_INPUT_SWITCH0_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 186 extern __PGA280_INPUT_SWITCH0_t PGA280_INPUT_SWITCH0; //объявление переменной
vitlog 0:f9ba28ab9f4c 187
vitlog 0:f9ba28ab9f4c 188 //Register 7 - Input Switch Control Register 2 (название из даташита)
vitlog 0:f9ba28ab9f4c 189 typedef union {
vitlog 0:f9ba28ab9f4c 190 struct {
vitlog 0:f9ba28ab9f4c 191 uint8_t
vitlog 0:f9ba28ab9f4c 192 SW_G2:1,
vitlog 0:f9ba28ab9f4c 193 SW_G1:1,
vitlog 0:f9ba28ab9f4c 194 SW_F2:1,
vitlog 0:f9ba28ab9f4c 195 SW_F1:1,
vitlog 0:f9ba28ab9f4c 196 :4;
vitlog 0:f9ba28ab9f4c 197 };
vitlog 0:f9ba28ab9f4c 198 struct {
vitlog 0:f9ba28ab9f4c 199 uint8_t SWCR1:4;
vitlog 0:f9ba28ab9f4c 200 uint8_t :4;
vitlog 0:f9ba28ab9f4c 201 };
vitlog 0:f9ba28ab9f4c 202 struct {
vitlog 0:f9ba28ab9f4c 203 uint8_t w:8;
vitlog 0:f9ba28ab9f4c 204 };
vitlog 0:f9ba28ab9f4c 205 }__PGA280_INPUT_SWITCH1_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 206 extern __PGA280_INPUT_SWITCH1_t PGA280_INPUT_SWITCH1; //объявление переменной
vitlog 0:f9ba28ab9f4c 207
vitlog 0:f9ba28ab9f4c 208 //Register 8 - GPIO Configuration Register (название из даташита)
vitlog 0:f9ba28ab9f4c 209 typedef union {
vitlog 0:f9ba28ab9f4c 210 struct {
vitlog 0:f9ba28ab9f4c 211 uint8_t
vitlog 0:f9ba28ab9f4c 212 DIR0:1,
vitlog 0:f9ba28ab9f4c 213 DIR1:1,
vitlog 0:f9ba28ab9f4c 214 DIR2:1,
vitlog 0:f9ba28ab9f4c 215 DIR3:1,
vitlog 0:f9ba28ab9f4c 216 DIR4:1,
vitlog 0:f9ba28ab9f4c 217 DIR5:1,
vitlog 0:f9ba28ab9f4c 218 DIR6:1,
vitlog 0:f9ba28ab9f4c 219 :1;
vitlog 0:f9ba28ab9f4c 220 };
vitlog 0:f9ba28ab9f4c 221 struct {
vitlog 0:f9ba28ab9f4c 222 uint8_t DIR:7;
vitlog 0:f9ba28ab9f4c 223 uint8_t :1;
vitlog 0:f9ba28ab9f4c 224 };
vitlog 0:f9ba28ab9f4c 225 struct {
vitlog 0:f9ba28ab9f4c 226 uint8_t w:8;
vitlog 0:f9ba28ab9f4c 227 };
vitlog 0:f9ba28ab9f4c 228 }__PGA280_GPIO_DIR_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 229 extern __PGA280_GPIO_DIR_t PGA280_GPIO_DIR; //объявление переменной
vitlog 0:f9ba28ab9f4c 230
vitlog 0:f9ba28ab9f4c 231 //Register 9 - CS Configuration Mode Register (название из даташита)
vitlog 0:f9ba28ab9f4c 232 typedef union {
vitlog 0:f9ba28ab9f4c 233 struct {
vitlog 0:f9ba28ab9f4c 234 uint8_t
vitlog 0:f9ba28ab9f4c 235 ECS0:1,
vitlog 0:f9ba28ab9f4c 236 ECS1:1,
vitlog 0:f9ba28ab9f4c 237 ECS2:1,
vitlog 0:f9ba28ab9f4c 238 ECS3:1,
vitlog 0:f9ba28ab9f4c 239 ECS4:1,
vitlog 0:f9ba28ab9f4c 240 ECS5:1,
vitlog 0:f9ba28ab9f4c 241 ECS6:1,
vitlog 0:f9ba28ab9f4c 242 :1;
vitlog 0:f9ba28ab9f4c 243 };
vitlog 0:f9ba28ab9f4c 244 struct {
vitlog 0:f9ba28ab9f4c 245 uint8_t ECS:7;
vitlog 0:f9ba28ab9f4c 246 uint8_t :1;
vitlog 0:f9ba28ab9f4c 247 };
vitlog 0:f9ba28ab9f4c 248 struct {
vitlog 0:f9ba28ab9f4c 249 uint8_t w:8;
vitlog 0:f9ba28ab9f4c 250 };
vitlog 0:f9ba28ab9f4c 251 }__PGA280_CS_MODE_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 252 extern __PGA280_CS_MODE_t PGA280_CS_MODE; //объявление переменной
vitlog 0:f9ba28ab9f4c 253
vitlog 0:f9ba28ab9f4c 254 //Register 10 - Configuration Register 1 (название из даташита)
vitlog 0:f9ba28ab9f4c 255 typedef union {
vitlog 0:f9ba28ab9f4c 256 struct {
vitlog 0:f9ba28ab9f4c 257 uint8_t
vitlog 0:f9ba28ab9f4c 258 IOVerr:1, //Input Overvoltage
vitlog 0:f9ba28ab9f4c 259 GAINerr:1, //Gain Network Overload
vitlog 0:f9ba28ab9f4c 260 OUTerr:1, //Output Stage Error (allow approximately 6µs activation delay).
vitlog 0:f9ba28ab9f4c 261 EDBUFA:1,
vitlog 0:f9ba28ab9f4c 262 ICAerr:1, //Input Clamp Active
vitlog 0:f9ba28ab9f4c 263 BUFAPOL:1,
vitlog 0:f9ba28ab9f4c 264 IARerr:1, //Input Amplifier Saturation
vitlog 0:f9ba28ab9f4c 265 MUX_D:1;
vitlog 0:f9ba28ab9f4c 266 };
vitlog 0:f9ba28ab9f4c 267 struct {
vitlog 0:f9ba28ab9f4c 268 uint8_t CFG0:8;
vitlog 0:f9ba28ab9f4c 269 };
vitlog 0:f9ba28ab9f4c 270 }__PGA280_CONFIG0_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 271 extern __PGA280_CONFIG0_t PGA280_CONFIG0; //объявление переменной
vitlog 0:f9ba28ab9f4c 272
vitlog 0:f9ba28ab9f4c 273 //Register 11 - Configuration Register 1 (название из даташита)
vitlog 0:f9ba28ab9f4c 274 typedef union {
vitlog 0:f9ba28ab9f4c 275 struct {
vitlog 0:f9ba28ab9f4c 276 uint8_t
vitlog 0:f9ba28ab9f4c 277 CHKsumE:1,
vitlog 0:f9ba28ab9f4c 278 :1,
vitlog 0:f9ba28ab9f4c 279 FLGTIM0:1,
vitlog 0:f9ba28ab9f4c 280 FLGTIM1:1,
vitlog 0:f9ba28ab9f4c 281 FLGTIM2:1,
vitlog 0:f9ba28ab9f4c 282 FLGTIM3:1,
vitlog 0:f9ba28ab9f4c 283 :1,
vitlog 0:f9ba28ab9f4c 284 LTD:1;
vitlog 0:f9ba28ab9f4c 285
vitlog 0:f9ba28ab9f4c 286 };
vitlog 0:f9ba28ab9f4c 287 struct {
vitlog 0:f9ba28ab9f4c 288 uint8_t
vitlog 0:f9ba28ab9f4c 289 :2,
vitlog 0:f9ba28ab9f4c 290 FLGTIM:4,
vitlog 0:f9ba28ab9f4c 291 :2;
vitlog 0:f9ba28ab9f4c 292 };
vitlog 0:f9ba28ab9f4c 293 struct {
vitlog 0:f9ba28ab9f4c 294 uint8_t CFG1:8;
vitlog 0:f9ba28ab9f4c 295 };
vitlog 0:f9ba28ab9f4c 296 }__PGA280_CONFIG1_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 297 extern __PGA280_CONFIG1_t PGA280_CONFIG1; //объявление переменной
vitlog 0:f9ba28ab9f4c 298
vitlog 0:f9ba28ab9f4c 299 //Register 12 - Special Functions Register (название из даташита)
vitlog 0:f9ba28ab9f4c 300 typedef union {
vitlog 0:f9ba28ab9f4c 301 struct {
vitlog 0:f9ba28ab9f4c 302 uint8_t
vitlog 0:f9ba28ab9f4c 303 /*If the GPIO pins are configured as outputs and these bits are set to 1, the GPIO pins are
vitlog 0:f9ba28ab9f4c 304 *controlled from Register 0 (if MUX-D = 0).*/
vitlog 0:f9ba28ab9f4c 305 MUX0:1,
vitlog 0:f9ba28ab9f4c 306 MUX1:1,
vitlog 0:f9ba28ab9f4c 307 MUX2:1,
vitlog 0:f9ba28ab9f4c 308
vitlog 0:f9ba28ab9f4c 309 /*A logic OR combination of error bits; see Register 10. This flag can control GPIO3 if this pin is
vitlog 0:f9ba28ab9f4c 310 *configured as an output and EFout = 1.*/
vitlog 0:f9ba28ab9f4c 311 EFout:1,
vitlog 0:f9ba28ab9f4c 312
vitlog 0:f9ba28ab9f4c 313 /*The current buffer can be triggered externally by pin GPIO4, if configured as an input. The low-to-
vitlog 0:f9ba28ab9f4c 314 *high edge of a pulse starts the buffer with a delay of three to four clock cycles. If held high, the buffer [BUFA]
vitlog 0:f9ba28ab9f4c 315 *remains active. The active time is extended by a minimum of three to four clock cycles plus the time set with FLAGTIM.*/
vitlog 0:f9ba28ab9f4c 316 BUFTin:1,
vitlog 0:f9ba28ab9f4c 317
vitlog 0:f9ba28ab9f4c 318 /*Pin GPIO5 indicates a buffer active condition (if configured as an output). The BUFA output signal
vitlog 0:f9ba28ab9f4c 319 * is active high by default, but can be inverted to active low by BUFA Pol.*/
vitlog 0:f9ba28ab9f4c 320 BUFAout:1,
vitlog 0:f9ba28ab9f4c 321
vitlog 0:f9ba28ab9f4c 322 //External connection for external oscillator input to pin GPIO6 (GPIO6 configured as an input).
vitlog 0:f9ba28ab9f4c 323 SYNCin:1,
vitlog 0:f9ba28ab9f4c 324
vitlog 0:f9ba28ab9f4c 325 //Internal oscillator connected to pin GPIO6 for output (GPIO6 configured as an output).
vitlog 0:f9ba28ab9f4c 326 OSCout:1;
vitlog 0:f9ba28ab9f4c 327 };
vitlog 0:f9ba28ab9f4c 328 struct {
vitlog 0:f9ba28ab9f4c 329 uint8_t MUX:3;
vitlog 0:f9ba28ab9f4c 330 uint8_t :5;
vitlog 0:f9ba28ab9f4c 331 };
vitlog 0:f9ba28ab9f4c 332 struct {
vitlog 0:f9ba28ab9f4c 333 uint8_t w:8;
vitlog 0:f9ba28ab9f4c 334 };
vitlog 0:f9ba28ab9f4c 335 }__PGA280_SP_FUNCTION_t; //это объявление типа.
vitlog 0:f9ba28ab9f4c 336 extern __PGA280_SP_FUNCTION_t PGA280_SP_FUNCTION; //объявление переменной
vitlog 0:f9ba28ab9f4c 337
vitlog 0:f9ba28ab9f4c 338 void pga280_setAdress ( unsigned char adr );
vitlog 0:f9ba28ab9f4c 339 void pga280_resetAdress ( void );
vitlog 0:f9ba28ab9f4c 340 char pga280_sendCommandDevice ( unsigned char command, unsigned char adr );
vitlog 0:f9ba28ab9f4c 341 unsigned char pga280_readOneRegisterDevice ( unsigned char reg, unsigned char adr );
vitlog 0:f9ba28ab9f4c 342 void pga280_writeOneRegisterDevice ( unsigned char reg, unsigned char data, unsigned char adr );
vitlog 0:f9ba28ab9f4c 343 void pga280_writeBufOneRegisterDevice ( unsigned char reg, unsigned char data, unsigned char adr );
vitlog 0:f9ba28ab9f4c 344 void pga280_directCS ( unsigned char ex_cs, unsigned char adr );
vitlog 0:f9ba28ab9f4c 345 void pga280_resetDevice ( unsigned char adr );
vitlog 0:f9ba28ab9f4c 346 void pga280_setMUX (unsigned char mux, unsigned char adr );
vitlog 0:f9ba28ab9f4c 347 void pga280_setGAIN ( unsigned char gain, unsigned char adr );
vitlog 0:f9ba28ab9f4c 348 void pga280_directCsBegin ( unsigned char exCS, unsigned char adr );
vitlog 0:f9ba28ab9f4c 349 void pga280_directCsEnd ( void );
vitlog 0:f9ba28ab9f4c 350 void pga280_setGPIO ( unsigned char num, unsigned char adr );
vitlog 0:f9ba28ab9f4c 351 void pga280_resetGPIO ( unsigned char num, unsigned char adr );
vitlog 0:f9ba28ab9f4c 352
vitlog 0:f9ba28ab9f4c 353
vitlog 0:f9ba28ab9f4c 354 /* Provide C++ Compatibility */
vitlog 0:f9ba28ab9f4c 355 #ifdef __cplusplus
vitlog 0:f9ba28ab9f4c 356 }
vitlog 0:f9ba28ab9f4c 357 #endif
vitlog 0:f9ba28ab9f4c 358
vitlog 0:f9ba28ab9f4c 359 #endif /* _EXAMPLE_FILE_NAME_H */
vitlog 0:f9ba28ab9f4c 360
vitlog 0:f9ba28ab9f4c 361 /* *****************************************************************************
vitlog 0:f9ba28ab9f4c 362 End of File
vitlog 0:f9ba28ab9f4c 363 */