Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /*******************************************************************************
vipinranka 12:9a20164dcc47 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
vipinranka 12:9a20164dcc47 3 *
vipinranka 12:9a20164dcc47 4 * Permission is hereby granted, free of charge, to any person obtaining a
vipinranka 12:9a20164dcc47 5 * copy of this software and associated documentation files (the "Software"),
vipinranka 12:9a20164dcc47 6 * to deal in the Software without restriction, including without limitation
vipinranka 12:9a20164dcc47 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
vipinranka 12:9a20164dcc47 8 * and/or sell copies of the Software, and to permit persons to whom the
vipinranka 12:9a20164dcc47 9 * Software is furnished to do so, subject to the following conditions:
vipinranka 12:9a20164dcc47 10 *
vipinranka 12:9a20164dcc47 11 * The above copyright notice and this permission notice shall be included
vipinranka 12:9a20164dcc47 12 * in all copies or substantial portions of the Software.
vipinranka 12:9a20164dcc47 13 *
vipinranka 12:9a20164dcc47 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
vipinranka 12:9a20164dcc47 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
vipinranka 12:9a20164dcc47 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
vipinranka 12:9a20164dcc47 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
vipinranka 12:9a20164dcc47 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
vipinranka 12:9a20164dcc47 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
vipinranka 12:9a20164dcc47 20 * OTHER DEALINGS IN THE SOFTWARE.
vipinranka 12:9a20164dcc47 21 *
vipinranka 12:9a20164dcc47 22 * Except as contained in this notice, the name of Maxim Integrated
vipinranka 12:9a20164dcc47 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
vipinranka 12:9a20164dcc47 24 * Products, Inc. Branding Policy.
vipinranka 12:9a20164dcc47 25 *
vipinranka 12:9a20164dcc47 26 * The mere transfer of this software does not imply any licenses
vipinranka 12:9a20164dcc47 27 * of trade secrets, proprietary technology, copyrights, patents,
vipinranka 12:9a20164dcc47 28 * trademarks, maskwork rights, or any other form of intellectual
vipinranka 12:9a20164dcc47 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
vipinranka 12:9a20164dcc47 30 * ownership rights.
vipinranka 12:9a20164dcc47 31 *******************************************************************************
vipinranka 12:9a20164dcc47 32 */
vipinranka 12:9a20164dcc47 33
vipinranka 12:9a20164dcc47 34 #include "sleep_api.h"
vipinranka 12:9a20164dcc47 35 #include "pwrman_regs.h"
vipinranka 12:9a20164dcc47 36 #include "pwrseq_regs.h"
vipinranka 12:9a20164dcc47 37 #include "clkman_regs.h"
vipinranka 12:9a20164dcc47 38 #include "ioman_regs.h"
vipinranka 12:9a20164dcc47 39 #include "rtc_regs.h"
vipinranka 12:9a20164dcc47 40 #include "usb_regs.h"
vipinranka 12:9a20164dcc47 41
vipinranka 12:9a20164dcc47 42 #define REVISION_A3 2
vipinranka 12:9a20164dcc47 43 #define REVISION_A4 3
vipinranka 12:9a20164dcc47 44
vipinranka 12:9a20164dcc47 45 // USB state to be restored upon wakeup
vipinranka 12:9a20164dcc47 46 typedef struct {
vipinranka 12:9a20164dcc47 47 uint32_t dev_cn;
vipinranka 12:9a20164dcc47 48 uint32_t dev_inten;
vipinranka 12:9a20164dcc47 49 uint32_t ep_base;
vipinranka 12:9a20164dcc47 50 uint32_t ep[MXC_USB_NUM_EP];
vipinranka 12:9a20164dcc47 51 } usb_state_t;
vipinranka 12:9a20164dcc47 52
vipinranka 12:9a20164dcc47 53 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
vipinranka 12:9a20164dcc47 54 static int restore_usb;
vipinranka 12:9a20164dcc47 55 static usb_state_t usb_state;
vipinranka 12:9a20164dcc47 56
vipinranka 12:9a20164dcc47 57 void sleep(void)
vipinranka 12:9a20164dcc47 58 {
vipinranka 12:9a20164dcc47 59 // Normal sleep mode for ARM core
vipinranka 12:9a20164dcc47 60 SCB->SCR = 0;
vipinranka 12:9a20164dcc47 61
vipinranka 12:9a20164dcc47 62 __DSB();
vipinranka 12:9a20164dcc47 63 __WFI();
vipinranka 12:9a20164dcc47 64 }
vipinranka 12:9a20164dcc47 65
vipinranka 12:9a20164dcc47 66 static void usb_sleep(void)
vipinranka 12:9a20164dcc47 67 {
vipinranka 12:9a20164dcc47 68 int i;
vipinranka 12:9a20164dcc47 69
vipinranka 12:9a20164dcc47 70 if (MXC_USB->cn & MXC_F_USB_CN_USB_EN) {
vipinranka 12:9a20164dcc47 71 // The USB module will not survive Deep Sleep.
vipinranka 12:9a20164dcc47 72
vipinranka 12:9a20164dcc47 73 // Save the USB state to restore it upon wakeup
vipinranka 12:9a20164dcc47 74 usb_state.dev_cn = MXC_USB->dev_cn;
vipinranka 12:9a20164dcc47 75 usb_state.dev_inten = MXC_USB->dev_inten;
vipinranka 12:9a20164dcc47 76 usb_state.ep_base = MXC_USB->ep_base;
vipinranka 12:9a20164dcc47 77 for (i = 0; i < MXC_USB_NUM_EP; i++) {
vipinranka 12:9a20164dcc47 78 usb_state.ep[i] = MXC_USB->ep[i] & (MXC_F_USB_EP_DIR | MXC_F_USB_EP_BUF2 | MXC_F_USB_EP_INT_EN | MXC_F_USB_EP_NAK_EN);
vipinranka 12:9a20164dcc47 79 }
vipinranka 12:9a20164dcc47 80 restore_usb = 1;
vipinranka 12:9a20164dcc47 81
vipinranka 12:9a20164dcc47 82 // Shut down the USB module.
vipinranka 12:9a20164dcc47 83 MXC_USB->dev_inten = 0;
vipinranka 12:9a20164dcc47 84 MXC_USB->dev_cn = 0;
vipinranka 12:9a20164dcc47 85 MXC_USB->cn = 0;
vipinranka 12:9a20164dcc47 86 restore_usb = 1; // USB should be restored upon wakeup
vipinranka 12:9a20164dcc47 87 } else {
vipinranka 12:9a20164dcc47 88 restore_usb = 0;
vipinranka 12:9a20164dcc47 89 }
vipinranka 12:9a20164dcc47 90 }
vipinranka 12:9a20164dcc47 91
vipinranka 12:9a20164dcc47 92 // Restore the USB module state.
vipinranka 12:9a20164dcc47 93 static void usb_wakeup(void)
vipinranka 12:9a20164dcc47 94 {
vipinranka 12:9a20164dcc47 95 int i;
vipinranka 12:9a20164dcc47 96
vipinranka 12:9a20164dcc47 97 if (restore_usb) {
vipinranka 12:9a20164dcc47 98 MXC_USB->cn = MXC_F_USB_CN_USB_EN;
vipinranka 12:9a20164dcc47 99 MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
vipinranka 12:9a20164dcc47 100 MXC_USB->dev_cn = 0;
vipinranka 12:9a20164dcc47 101 for (i = 0; i < MXC_USB_NUM_EP; i++) {
vipinranka 12:9a20164dcc47 102 MXC_USB->ep[i] = usb_state.ep[i];
vipinranka 12:9a20164dcc47 103 }
vipinranka 12:9a20164dcc47 104 MXC_USB->ep_base = usb_state.ep_base;
vipinranka 12:9a20164dcc47 105 MXC_USB->dev_cn = usb_state.dev_cn;
vipinranka 12:9a20164dcc47 106 MXC_USB->dev_inten = usb_state.dev_inten;
vipinranka 12:9a20164dcc47 107 restore_usb = 0;
vipinranka 12:9a20164dcc47 108 }
vipinranka 12:9a20164dcc47 109 }
vipinranka 12:9a20164dcc47 110
vipinranka 12:9a20164dcc47 111 // Low-power stop mode
vipinranka 12:9a20164dcc47 112 void deepsleep(void)
vipinranka 12:9a20164dcc47 113 {
vipinranka 12:9a20164dcc47 114 unsigned int part_rev = MXC_PWRMAN->mask_id0 & MXC_F_PWRMAN_MASK_ID0_REVISION_ID;
vipinranka 12:9a20164dcc47 115
vipinranka 12:9a20164dcc47 116 // Deep Sleep is not working properly on Revisions A3 and earlier
vipinranka 12:9a20164dcc47 117 if (part_rev <= REVISION_A3) {
vipinranka 12:9a20164dcc47 118 sleep();
vipinranka 12:9a20164dcc47 119 return;
vipinranka 12:9a20164dcc47 120 }
vipinranka 12:9a20164dcc47 121
vipinranka 12:9a20164dcc47 122 // Wait for all STDIO characters to be sent. The UART clock will stop.
vipinranka 12:9a20164dcc47 123 while ((stdio_uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ||
vipinranka 12:9a20164dcc47 124 !(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE));
vipinranka 12:9a20164dcc47 125
vipinranka 12:9a20164dcc47 126 __disable_irq();
vipinranka 12:9a20164dcc47 127
vipinranka 12:9a20164dcc47 128 // Do not enter Deep Sleep if connected to VBUS
vipinranka 12:9a20164dcc47 129 if (MXC_USB->dev_intfl & MXC_F_USB_DEV_INTFL_VBUS_ST) {
vipinranka 12:9a20164dcc47 130 __enable_irq();
vipinranka 12:9a20164dcc47 131 sleep();
vipinranka 12:9a20164dcc47 132 return;
vipinranka 12:9a20164dcc47 133 }
vipinranka 12:9a20164dcc47 134
vipinranka 12:9a20164dcc47 135 // The USB module will not survive Deep Sleep. Shut it down.
vipinranka 12:9a20164dcc47 136 usb_sleep();
vipinranka 12:9a20164dcc47 137
vipinranka 12:9a20164dcc47 138 // Make sure RTC is not pending before sleeping, if its still synchronizing
vipinranka 12:9a20164dcc47 139 // we might not wake up.
vipinranka 12:9a20164dcc47 140 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
vipinranka 12:9a20164dcc47 141
vipinranka 12:9a20164dcc47 142 // Clear any active GPIO Wake Up Events
vipinranka 12:9a20164dcc47 143 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP) {
vipinranka 12:9a20164dcc47 144 // NOTE: These must be cleared before clearing IOWAKEUP
vipinranka 12:9a20164dcc47 145 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH;
vipinranka 12:9a20164dcc47 146 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH;
vipinranka 12:9a20164dcc47 147
vipinranka 12:9a20164dcc47 148 MXC_PWRSEQ->flags |= MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP;
vipinranka 12:9a20164dcc47 149 }
vipinranka 12:9a20164dcc47 150
vipinranka 12:9a20164dcc47 151 // Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP
vipinranka 12:9a20164dcc47 152 if (part_rev == REVISION_A4) {
vipinranka 12:9a20164dcc47 153 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_LP1; // A4 requires part to go to pseudo LP0
vipinranka 12:9a20164dcc47 154 } else {
vipinranka 12:9a20164dcc47 155 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;
vipinranka 12:9a20164dcc47 156 }
vipinranka 12:9a20164dcc47 157
vipinranka 12:9a20164dcc47 158 // The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state)
vipinranka 12:9a20164dcc47 159 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
vipinranka 12:9a20164dcc47 160
vipinranka 12:9a20164dcc47 161 if (part_rev == REVISION_A4) {
vipinranka 12:9a20164dcc47 162 // WORKAROUND: Toggle SVM bits, which send extra clocks to the power sequencer to fix retention controller
vipinranka 12:9a20164dcc47 163 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD;
vipinranka 12:9a20164dcc47 164 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN);
vipinranka 12:9a20164dcc47 165 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN;
vipinranka 12:9a20164dcc47 166 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD;
vipinranka 12:9a20164dcc47 167 }
vipinranka 12:9a20164dcc47 168
vipinranka 12:9a20164dcc47 169 // Enable Retention controller
vipinranka 12:9a20164dcc47 170 MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN;
vipinranka 12:9a20164dcc47 171
vipinranka 12:9a20164dcc47 172 // Clear the firstboot bit, which is generated by a POR event and locks out LPx modes
vipinranka 12:9a20164dcc47 173 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT;
vipinranka 12:9a20164dcc47 174
vipinranka 12:9a20164dcc47 175 // Freeze GPIO using MBUS so that it doesn't flail while digital core is asleep
vipinranka 12:9a20164dcc47 176 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
vipinranka 12:9a20164dcc47 177
vipinranka 12:9a20164dcc47 178 // Dummy read to make sure SSB writes are complete
vipinranka 12:9a20164dcc47 179 MXC_PWRSEQ->reg0 = MXC_PWRSEQ->reg0;
vipinranka 12:9a20164dcc47 180
vipinranka 12:9a20164dcc47 181 if (part_rev == REVISION_A4) {
vipinranka 12:9a20164dcc47 182 // Note: ARM deep-sleep requires a specific sequence to clear event latches,
vipinranka 12:9a20164dcc47 183 // otherwise the CPU will not enter sleep.
vipinranka 12:9a20164dcc47 184 __SEV();
vipinranka 12:9a20164dcc47 185 __WFE();
vipinranka 12:9a20164dcc47 186 __WFI();
vipinranka 12:9a20164dcc47 187 } else {
vipinranka 12:9a20164dcc47 188 // Note: ARM deep-sleep requires a specific sequence to clear event latches,
vipinranka 12:9a20164dcc47 189 // otherwise the CPU will not enter sleep.
vipinranka 12:9a20164dcc47 190 __SEV();
vipinranka 12:9a20164dcc47 191 __WFE();
vipinranka 12:9a20164dcc47 192 __WFE();
vipinranka 12:9a20164dcc47 193 }
vipinranka 12:9a20164dcc47 194
vipinranka 12:9a20164dcc47 195 // We'll wakeup here ...
vipinranka 12:9a20164dcc47 196
vipinranka 12:9a20164dcc47 197 // Unfreeze the GPIO by clearing MBUS_GATE
vipinranka 12:9a20164dcc47 198 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
vipinranka 12:9a20164dcc47 199
vipinranka 12:9a20164dcc47 200 usb_wakeup();
vipinranka 12:9a20164dcc47 201
vipinranka 12:9a20164dcc47 202 // Clear power sequencer event flags (write-1-to-clear)
vipinranka 12:9a20164dcc47 203 // RTC and GPIO flags are cleared in their interrupts handlers
vipinranka 12:9a20164dcc47 204 // NOTE: We are ignoring all of these potential wake up types
vipinranka 12:9a20164dcc47 205 MXC_PWRSEQ->flags = (MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL |
vipinranka 12:9a20164dcc47 206 MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL |
vipinranka 12:9a20164dcc47 207 MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE |
vipinranka 12:9a20164dcc47 208 MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD |
vipinranka 12:9a20164dcc47 209 MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD |
vipinranka 12:9a20164dcc47 210 MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD |
vipinranka 12:9a20164dcc47 211 MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD |
vipinranka 12:9a20164dcc47 212 MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD |
vipinranka 12:9a20164dcc47 213 MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH |
vipinranka 12:9a20164dcc47 214 MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP |
vipinranka 12:9a20164dcc47 215 MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP |
vipinranka 12:9a20164dcc47 216 MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD);
vipinranka 12:9a20164dcc47 217
vipinranka 12:9a20164dcc47 218 __enable_irq();
vipinranka 12:9a20164dcc47 219 }