Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /*******************************************************************************
vipinranka 12:9a20164dcc47 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
vipinranka 12:9a20164dcc47 3 *
vipinranka 12:9a20164dcc47 4 * Permission is hereby granted, free of charge, to any person obtaining a
vipinranka 12:9a20164dcc47 5 * copy of this software and associated documentation files (the "Software"),
vipinranka 12:9a20164dcc47 6 * to deal in the Software without restriction, including without limitation
vipinranka 12:9a20164dcc47 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
vipinranka 12:9a20164dcc47 8 * and/or sell copies of the Software, and to permit persons to whom the
vipinranka 12:9a20164dcc47 9 * Software is furnished to do so, subject to the following conditions:
vipinranka 12:9a20164dcc47 10 *
vipinranka 12:9a20164dcc47 11 * The above copyright notice and this permission notice shall be included
vipinranka 12:9a20164dcc47 12 * in all copies or substantial portions of the Software.
vipinranka 12:9a20164dcc47 13 *
vipinranka 12:9a20164dcc47 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
vipinranka 12:9a20164dcc47 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
vipinranka 12:9a20164dcc47 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
vipinranka 12:9a20164dcc47 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
vipinranka 12:9a20164dcc47 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
vipinranka 12:9a20164dcc47 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
vipinranka 12:9a20164dcc47 20 * OTHER DEALINGS IN THE SOFTWARE.
vipinranka 12:9a20164dcc47 21 *
vipinranka 12:9a20164dcc47 22 * Except as contained in this notice, the name of Maxim Integrated
vipinranka 12:9a20164dcc47 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
vipinranka 12:9a20164dcc47 24 * Products, Inc. Branding Policy.
vipinranka 12:9a20164dcc47 25 *
vipinranka 12:9a20164dcc47 26 * The mere transfer of this software does not imply any licenses
vipinranka 12:9a20164dcc47 27 * of trade secrets, proprietary technology, copyrights, patents,
vipinranka 12:9a20164dcc47 28 * trademarks, maskwork rights, or any other form of intellectual
vipinranka 12:9a20164dcc47 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
vipinranka 12:9a20164dcc47 30 * ownership rights.
vipinranka 12:9a20164dcc47 31 *******************************************************************************
vipinranka 12:9a20164dcc47 32 */
vipinranka 12:9a20164dcc47 33
vipinranka 12:9a20164dcc47 34 #include <string.h>
vipinranka 12:9a20164dcc47 35 #include "mbed_assert.h"
vipinranka 12:9a20164dcc47 36 #include "cmsis.h"
vipinranka 12:9a20164dcc47 37 #include "serial_api.h"
vipinranka 12:9a20164dcc47 38 #include "uart_regs.h"
vipinranka 12:9a20164dcc47 39 #include "ioman_regs.h"
vipinranka 12:9a20164dcc47 40 #include "gpio_api.h"
vipinranka 12:9a20164dcc47 41 #include "clkman_regs.h"
vipinranka 12:9a20164dcc47 42 #include "PeripheralPins.h"
vipinranka 12:9a20164dcc47 43
vipinranka 12:9a20164dcc47 44 #define DEFAULT_BAUD 9600
vipinranka 12:9a20164dcc47 45 #define DEFAULT_STOP 1
vipinranka 12:9a20164dcc47 46 #define DEFAULT_PARITY ParityNone
vipinranka 12:9a20164dcc47 47
vipinranka 12:9a20164dcc47 48 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
vipinranka 12:9a20164dcc47 49 MXC_F_UART_INTFL_RX_PARITY_ERR | \
vipinranka 12:9a20164dcc47 50 MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
vipinranka 12:9a20164dcc47 51
vipinranka 12:9a20164dcc47 52 // Variables for managing the stdio UART
vipinranka 12:9a20164dcc47 53 int stdio_uart_inited;
vipinranka 12:9a20164dcc47 54 serial_t stdio_uart;
vipinranka 12:9a20164dcc47 55
vipinranka 12:9a20164dcc47 56 // Variables for interrupt driven
vipinranka 12:9a20164dcc47 57 static uart_irq_handler irq_handler;
vipinranka 12:9a20164dcc47 58 static uint32_t serial_irq_ids[MXC_CFG_UART_INSTANCES];
vipinranka 12:9a20164dcc47 59
vipinranka 12:9a20164dcc47 60 //******************************************************************************
vipinranka 12:9a20164dcc47 61 void serial_init(serial_t *obj, PinName tx, PinName rx)
vipinranka 12:9a20164dcc47 62 {
vipinranka 12:9a20164dcc47 63 // Determine which uart is associated with each pin
vipinranka 12:9a20164dcc47 64 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
vipinranka 12:9a20164dcc47 65 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
vipinranka 12:9a20164dcc47 66 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
vipinranka 12:9a20164dcc47 67
vipinranka 12:9a20164dcc47 68 // Make sure that both pins are pointing to the same uart
vipinranka 12:9a20164dcc47 69 MBED_ASSERT(uart != (UARTName)NC);
vipinranka 12:9a20164dcc47 70
vipinranka 12:9a20164dcc47 71 // Ensure that the UART clock is enabled
vipinranka 12:9a20164dcc47 72 switch (uart) {
vipinranka 12:9a20164dcc47 73 case UART_0:
vipinranka 12:9a20164dcc47 74 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER;
vipinranka 12:9a20164dcc47 75 break;
vipinranka 12:9a20164dcc47 76 case UART_1:
vipinranka 12:9a20164dcc47 77 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER;
vipinranka 12:9a20164dcc47 78 break;
vipinranka 12:9a20164dcc47 79 case UART_2:
vipinranka 12:9a20164dcc47 80 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER;
vipinranka 12:9a20164dcc47 81 break;
vipinranka 12:9a20164dcc47 82 case UART_3:
vipinranka 12:9a20164dcc47 83 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER;
vipinranka 12:9a20164dcc47 84 break;
vipinranka 12:9a20164dcc47 85 default:
vipinranka 12:9a20164dcc47 86 break;
vipinranka 12:9a20164dcc47 87 }
vipinranka 12:9a20164dcc47 88
vipinranka 12:9a20164dcc47 89 // Ensure that the UART clock is enabled
vipinranka 12:9a20164dcc47 90 // But don't override the scaler
vipinranka 12:9a20164dcc47 91 //
vipinranka 12:9a20164dcc47 92 // To support the most common baud rates, 9600 and 115200, we need to
vipinranka 12:9a20164dcc47 93 // scale down the uart input clock.
vipinranka 12:9a20164dcc47 94 if (!(MXC_CLKMAN->sys_clk_ctrl_8_uart & MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE)) {
vipinranka 12:9a20164dcc47 95
vipinranka 12:9a20164dcc47 96 switch (SystemCoreClock) {
vipinranka 12:9a20164dcc47 97 case RO_FREQ:
vipinranka 12:9a20164dcc47 98 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
vipinranka 12:9a20164dcc47 99 break;
vipinranka 12:9a20164dcc47 100 case (RO_FREQ / 2):
vipinranka 12:9a20164dcc47 101 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_2;
vipinranka 12:9a20164dcc47 102 break;
vipinranka 12:9a20164dcc47 103 default:
vipinranka 12:9a20164dcc47 104 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
vipinranka 12:9a20164dcc47 105 break;
vipinranka 12:9a20164dcc47 106 }
vipinranka 12:9a20164dcc47 107 }
vipinranka 12:9a20164dcc47 108
vipinranka 12:9a20164dcc47 109 // Set the obj pointer to the proper uart
vipinranka 12:9a20164dcc47 110 obj->uart = (mxc_uart_regs_t*)uart;
vipinranka 12:9a20164dcc47 111
vipinranka 12:9a20164dcc47 112 // Set the uart index
vipinranka 12:9a20164dcc47 113 obj->index = MXC_UART_GET_IDX(obj->uart);
vipinranka 12:9a20164dcc47 114 obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index);
vipinranka 12:9a20164dcc47 115
vipinranka 12:9a20164dcc47 116 // Configure the pins
vipinranka 12:9a20164dcc47 117 pinmap_pinout(tx, PinMap_UART_TX);
vipinranka 12:9a20164dcc47 118 pinmap_pinout(rx, PinMap_UART_RX);
vipinranka 12:9a20164dcc47 119
vipinranka 12:9a20164dcc47 120 // Flush the RX and TX FIFOs, clear the settings
vipinranka 12:9a20164dcc47 121 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
vipinranka 12:9a20164dcc47 122 obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
vipinranka 12:9a20164dcc47 123
vipinranka 12:9a20164dcc47 124 // Disable interrupts
vipinranka 12:9a20164dcc47 125 obj->uart->inten = 0;
vipinranka 12:9a20164dcc47 126 obj->uart->intfl = obj->uart->intfl;
vipinranka 12:9a20164dcc47 127
vipinranka 12:9a20164dcc47 128 // Configure to default settings
vipinranka 12:9a20164dcc47 129 serial_baud(obj, DEFAULT_BAUD);
vipinranka 12:9a20164dcc47 130 serial_format(obj, 8, ParityNone, 1);
vipinranka 12:9a20164dcc47 131
vipinranka 12:9a20164dcc47 132 // Manage stdio UART
vipinranka 12:9a20164dcc47 133 if (uart == STDIO_UART) {
vipinranka 12:9a20164dcc47 134 stdio_uart_inited = 1;
vipinranka 12:9a20164dcc47 135 memcpy(&stdio_uart, obj, sizeof(serial_t));
vipinranka 12:9a20164dcc47 136 }
vipinranka 12:9a20164dcc47 137
vipinranka 12:9a20164dcc47 138 // Enable UART
vipinranka 12:9a20164dcc47 139 obj->uart->ctrl |= MXC_F_UART_CTRL_UART_EN;
vipinranka 12:9a20164dcc47 140 }
vipinranka 12:9a20164dcc47 141
vipinranka 12:9a20164dcc47 142 //******************************************************************************
vipinranka 12:9a20164dcc47 143 void serial_baud(serial_t *obj, int baudrate)
vipinranka 12:9a20164dcc47 144 {
vipinranka 12:9a20164dcc47 145 uint32_t baud_setting = 0;
vipinranka 12:9a20164dcc47 146
vipinranka 12:9a20164dcc47 147 MBED_ASSERT(MXC_CLKMAN->sys_clk_ctrl_8_uart > MXC_S_CLKMAN_CLK_SCALE_DISABLED);
vipinranka 12:9a20164dcc47 148
vipinranka 12:9a20164dcc47 149 // Calculate the integer and decimal portions
vipinranka 12:9a20164dcc47 150 baud_setting = SystemCoreClock / (1<<(MXC_CLKMAN->sys_clk_ctrl_8_uart-1));
vipinranka 12:9a20164dcc47 151 baud_setting = baud_setting / (baudrate * 16);
vipinranka 12:9a20164dcc47 152
vipinranka 12:9a20164dcc47 153 // If the result doesn't fit in the register
vipinranka 12:9a20164dcc47 154 MBED_ASSERT(baud_setting <= UINT8_MAX);
vipinranka 12:9a20164dcc47 155
vipinranka 12:9a20164dcc47 156 obj->uart->baud = baud_setting;
vipinranka 12:9a20164dcc47 157 }
vipinranka 12:9a20164dcc47 158
vipinranka 12:9a20164dcc47 159 //******************************************************************************
vipinranka 12:9a20164dcc47 160 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
vipinranka 12:9a20164dcc47 161 {
vipinranka 12:9a20164dcc47 162 // Check the validity of the inputs
vipinranka 12:9a20164dcc47 163 MBED_ASSERT((data_bits > 4) && (data_bits < 9));
vipinranka 12:9a20164dcc47 164 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
vipinranka 12:9a20164dcc47 165 (parity == ParityEven) || (parity == ParityForced1) ||
vipinranka 12:9a20164dcc47 166 (parity == ParityForced0));
vipinranka 12:9a20164dcc47 167 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
vipinranka 12:9a20164dcc47 168
vipinranka 12:9a20164dcc47 169 // Adjust the stop and data bits
vipinranka 12:9a20164dcc47 170 stop_bits -= 1;
vipinranka 12:9a20164dcc47 171 data_bits -= 5;
vipinranka 12:9a20164dcc47 172
vipinranka 12:9a20164dcc47 173 // Adjust the parity setting
vipinranka 12:9a20164dcc47 174 int mode = 0;
vipinranka 12:9a20164dcc47 175 switch (parity) {
vipinranka 12:9a20164dcc47 176 case ParityNone:
vipinranka 12:9a20164dcc47 177 mode = 0;
vipinranka 12:9a20164dcc47 178 break;
vipinranka 12:9a20164dcc47 179 case ParityOdd :
vipinranka 12:9a20164dcc47 180 mode = 1;
vipinranka 12:9a20164dcc47 181 break;
vipinranka 12:9a20164dcc47 182 case ParityEven:
vipinranka 12:9a20164dcc47 183 mode = 2;
vipinranka 12:9a20164dcc47 184 break;
vipinranka 12:9a20164dcc47 185 case ParityForced1:
vipinranka 12:9a20164dcc47 186 // Hardware does not support forced parity
vipinranka 12:9a20164dcc47 187 MBED_ASSERT(0);
vipinranka 12:9a20164dcc47 188 break;
vipinranka 12:9a20164dcc47 189 case ParityForced0:
vipinranka 12:9a20164dcc47 190 // Hardware does not support forced parity
vipinranka 12:9a20164dcc47 191 MBED_ASSERT(0);
vipinranka 12:9a20164dcc47 192 break;
vipinranka 12:9a20164dcc47 193 default:
vipinranka 12:9a20164dcc47 194 mode = 0;
vipinranka 12:9a20164dcc47 195 break;
vipinranka 12:9a20164dcc47 196 }
vipinranka 12:9a20164dcc47 197
vipinranka 12:9a20164dcc47 198 int temp = obj->uart->ctrl;
vipinranka 12:9a20164dcc47 199 temp &= ~(MXC_F_UART_CTRL_DATA_SIZE | MXC_F_UART_CTRL_EXTRA_STOP | MXC_F_UART_CTRL_PARITY);
vipinranka 12:9a20164dcc47 200 temp |= (data_bits << MXC_F_UART_CTRL_DATA_SIZE_POS);
vipinranka 12:9a20164dcc47 201 temp |= (stop_bits << MXC_F_UART_CTRL_EXTRA_STOP_POS);
vipinranka 12:9a20164dcc47 202 temp |= (mode << MXC_F_UART_CTRL_PARITY_POS);
vipinranka 12:9a20164dcc47 203 obj->uart->ctrl = temp;
vipinranka 12:9a20164dcc47 204 }
vipinranka 12:9a20164dcc47 205
vipinranka 12:9a20164dcc47 206 //******************************************************************************
vipinranka 12:9a20164dcc47 207 void uart_handler(mxc_uart_regs_t* uart, int id)
vipinranka 12:9a20164dcc47 208 {
vipinranka 12:9a20164dcc47 209 // Check for errors or RX Threshold
vipinranka 12:9a20164dcc47 210 if (uart->intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
vipinranka 12:9a20164dcc47 211 if (serial_irq_ids[id]) {
vipinranka 12:9a20164dcc47 212 irq_handler(serial_irq_ids[id], RxIrq);
vipinranka 12:9a20164dcc47 213 }
vipinranka 12:9a20164dcc47 214 uart->intfl = (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
vipinranka 12:9a20164dcc47 215 }
vipinranka 12:9a20164dcc47 216
vipinranka 12:9a20164dcc47 217 // Check for TX Threshold
vipinranka 12:9a20164dcc47 218 if (uart->intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
vipinranka 12:9a20164dcc47 219 if (serial_irq_ids[id]) {
vipinranka 12:9a20164dcc47 220 irq_handler(serial_irq_ids[id], TxIrq);
vipinranka 12:9a20164dcc47 221 }
vipinranka 12:9a20164dcc47 222 uart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
vipinranka 12:9a20164dcc47 223 }
vipinranka 12:9a20164dcc47 224 }
vipinranka 12:9a20164dcc47 225
vipinranka 12:9a20164dcc47 226 void uart0_handler(void) { uart_handler(MXC_UART0, 0); }
vipinranka 12:9a20164dcc47 227 void uart1_handler(void) { uart_handler(MXC_UART1, 1); }
vipinranka 12:9a20164dcc47 228 void uart2_handler(void) { uart_handler(MXC_UART2, 2); }
vipinranka 12:9a20164dcc47 229 void uart3_handler(void) { uart_handler(MXC_UART3, 3); }
vipinranka 12:9a20164dcc47 230
vipinranka 12:9a20164dcc47 231 //******************************************************************************
vipinranka 12:9a20164dcc47 232 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
vipinranka 12:9a20164dcc47 233 {
vipinranka 12:9a20164dcc47 234 irq_handler = handler;
vipinranka 12:9a20164dcc47 235 serial_irq_ids[obj->index] = id;
vipinranka 12:9a20164dcc47 236 }
vipinranka 12:9a20164dcc47 237
vipinranka 12:9a20164dcc47 238 //******************************************************************************
vipinranka 12:9a20164dcc47 239 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
vipinranka 12:9a20164dcc47 240 {
vipinranka 12:9a20164dcc47 241 switch (obj->index) {
vipinranka 12:9a20164dcc47 242 case 0:
vipinranka 12:9a20164dcc47 243 NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
vipinranka 12:9a20164dcc47 244 NVIC_EnableIRQ(UART0_IRQn);
vipinranka 12:9a20164dcc47 245 break;
vipinranka 12:9a20164dcc47 246 case 1:
vipinranka 12:9a20164dcc47 247 NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
vipinranka 12:9a20164dcc47 248 NVIC_EnableIRQ(UART1_IRQn);
vipinranka 12:9a20164dcc47 249 break;
vipinranka 12:9a20164dcc47 250 case 2:
vipinranka 12:9a20164dcc47 251 NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler);
vipinranka 12:9a20164dcc47 252 NVIC_EnableIRQ(UART2_IRQn);
vipinranka 12:9a20164dcc47 253 break;
vipinranka 12:9a20164dcc47 254 case 3:
vipinranka 12:9a20164dcc47 255 NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler);
vipinranka 12:9a20164dcc47 256 NVIC_EnableIRQ(UART3_IRQn);
vipinranka 12:9a20164dcc47 257 break;
vipinranka 12:9a20164dcc47 258 default:
vipinranka 12:9a20164dcc47 259 MBED_ASSERT(0);
vipinranka 12:9a20164dcc47 260 }
vipinranka 12:9a20164dcc47 261
vipinranka 12:9a20164dcc47 262 if (irq == RxIrq) {
vipinranka 12:9a20164dcc47 263 // Enable RX FIFO Threshold Interrupt
vipinranka 12:9a20164dcc47 264 if (enable) {
vipinranka 12:9a20164dcc47 265 // Clear pending interrupts
vipinranka 12:9a20164dcc47 266 obj->uart->intfl = obj->uart->intfl;
vipinranka 12:9a20164dcc47 267 obj->uart->inten |= (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
vipinranka 12:9a20164dcc47 268 } else {
vipinranka 12:9a20164dcc47 269 // Clear pending interrupts
vipinranka 12:9a20164dcc47 270 obj->uart->intfl = obj->uart->intfl;
vipinranka 12:9a20164dcc47 271 obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
vipinranka 12:9a20164dcc47 272 }
vipinranka 12:9a20164dcc47 273
vipinranka 12:9a20164dcc47 274 } else if (irq == TxIrq) {
vipinranka 12:9a20164dcc47 275 // Set TX Almost Empty level to interrupt when empty
vipinranka 12:9a20164dcc47 276 MXC_SET_FIELD(&obj->uart->tx_fifo_ctrl, MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL,
vipinranka 12:9a20164dcc47 277 (MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS);
vipinranka 12:9a20164dcc47 278
vipinranka 12:9a20164dcc47 279 // Enable TX Almost Empty Interrupt
vipinranka 12:9a20164dcc47 280 if (enable) {
vipinranka 12:9a20164dcc47 281 // Clear pending interrupts
vipinranka 12:9a20164dcc47 282 obj->uart->intfl = obj->uart->intfl;
vipinranka 12:9a20164dcc47 283 obj->uart->inten |= MXC_F_UART_INTFL_TX_FIFO_AE;
vipinranka 12:9a20164dcc47 284 } else {
vipinranka 12:9a20164dcc47 285 // Clear pending interrupts
vipinranka 12:9a20164dcc47 286 obj->uart->intfl = obj->uart->intfl;
vipinranka 12:9a20164dcc47 287 obj->uart->inten &= ~MXC_F_UART_INTFL_TX_FIFO_AE;
vipinranka 12:9a20164dcc47 288 }
vipinranka 12:9a20164dcc47 289
vipinranka 12:9a20164dcc47 290 } else {
vipinranka 12:9a20164dcc47 291 MBED_ASSERT(0);
vipinranka 12:9a20164dcc47 292 }
vipinranka 12:9a20164dcc47 293 }
vipinranka 12:9a20164dcc47 294
vipinranka 12:9a20164dcc47 295
vipinranka 12:9a20164dcc47 296 //******************************************************************************
vipinranka 12:9a20164dcc47 297 int serial_getc(serial_t *obj)
vipinranka 12:9a20164dcc47 298 {
vipinranka 12:9a20164dcc47 299 int c;
vipinranka 12:9a20164dcc47 300
vipinranka 12:9a20164dcc47 301 // Wait for data to be available
vipinranka 12:9a20164dcc47 302 while ((obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) == 0);
vipinranka 12:9a20164dcc47 303
vipinranka 12:9a20164dcc47 304 c = *obj->fifo->rx_8;
vipinranka 12:9a20164dcc47 305
vipinranka 12:9a20164dcc47 306 return c;
vipinranka 12:9a20164dcc47 307 }
vipinranka 12:9a20164dcc47 308
vipinranka 12:9a20164dcc47 309 //******************************************************************************
vipinranka 12:9a20164dcc47 310 void serial_putc(serial_t *obj, int c)
vipinranka 12:9a20164dcc47 311 {
vipinranka 12:9a20164dcc47 312 // Wait for TXFIFO to not be full
vipinranka 12:9a20164dcc47 313 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
vipinranka 12:9a20164dcc47 314 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
vipinranka 12:9a20164dcc47 315 >= MXC_UART_FIFO_DEPTH );
vipinranka 12:9a20164dcc47 316
vipinranka 12:9a20164dcc47 317 // Must clear before every write to the buffer to know that the fifo
vipinranka 12:9a20164dcc47 318 // is empty when the TX DONE bit is set
vipinranka 12:9a20164dcc47 319 obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE;
vipinranka 12:9a20164dcc47 320 *obj->fifo->tx_8 = (uint8_t)c;
vipinranka 12:9a20164dcc47 321 }
vipinranka 12:9a20164dcc47 322
vipinranka 12:9a20164dcc47 323 //******************************************************************************
vipinranka 12:9a20164dcc47 324 int serial_readable(serial_t *obj)
vipinranka 12:9a20164dcc47 325 {
vipinranka 12:9a20164dcc47 326 return (obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY);
vipinranka 12:9a20164dcc47 327 }
vipinranka 12:9a20164dcc47 328
vipinranka 12:9a20164dcc47 329 //******************************************************************************
vipinranka 12:9a20164dcc47 330 int serial_writable(serial_t *obj)
vipinranka 12:9a20164dcc47 331 {
vipinranka 12:9a20164dcc47 332 return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
vipinranka 12:9a20164dcc47 333 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
vipinranka 12:9a20164dcc47 334 < MXC_UART_FIFO_DEPTH );
vipinranka 12:9a20164dcc47 335 }
vipinranka 12:9a20164dcc47 336
vipinranka 12:9a20164dcc47 337 //******************************************************************************
vipinranka 12:9a20164dcc47 338 void serial_clear(serial_t *obj)
vipinranka 12:9a20164dcc47 339 {
vipinranka 12:9a20164dcc47 340 // Clear the rx and tx fifos
vipinranka 12:9a20164dcc47 341 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
vipinranka 12:9a20164dcc47 342 obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
vipinranka 12:9a20164dcc47 343 }
vipinranka 12:9a20164dcc47 344
vipinranka 12:9a20164dcc47 345
vipinranka 12:9a20164dcc47 346 //******************************************************************************
vipinranka 12:9a20164dcc47 347 void serial_break_set(serial_t *obj)
vipinranka 12:9a20164dcc47 348 {
vipinranka 12:9a20164dcc47 349 // Make sure that nothing is being sent
vipinranka 12:9a20164dcc47 350 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
vipinranka 12:9a20164dcc47 351 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
vipinranka 12:9a20164dcc47 352 while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE));
vipinranka 12:9a20164dcc47 353
vipinranka 12:9a20164dcc47 354 // Configure the GPIO to output 0
vipinranka 12:9a20164dcc47 355 gpio_t tx_gpio;
vipinranka 12:9a20164dcc47 356 switch (((UARTName)(obj->uart))) {
vipinranka 12:9a20164dcc47 357 case UART_0:
vipinranka 12:9a20164dcc47 358 gpio_init_out(&tx_gpio, UART0_TX);
vipinranka 12:9a20164dcc47 359 break;
vipinranka 12:9a20164dcc47 360 case UART_1:
vipinranka 12:9a20164dcc47 361 gpio_init_out(&tx_gpio, UART1_TX);
vipinranka 12:9a20164dcc47 362 break;
vipinranka 12:9a20164dcc47 363 case UART_2:
vipinranka 12:9a20164dcc47 364 gpio_init_out(&tx_gpio, UART2_TX);
vipinranka 12:9a20164dcc47 365 break;
vipinranka 12:9a20164dcc47 366 case UART_3:
vipinranka 12:9a20164dcc47 367 gpio_init_out(&tx_gpio, UART3_TX);
vipinranka 12:9a20164dcc47 368 break;
vipinranka 12:9a20164dcc47 369 default:
vipinranka 12:9a20164dcc47 370 gpio_init_out(&tx_gpio, (PinName)NC);
vipinranka 12:9a20164dcc47 371 break;
vipinranka 12:9a20164dcc47 372 }
vipinranka 12:9a20164dcc47 373
vipinranka 12:9a20164dcc47 374 gpio_write(&tx_gpio, 0);
vipinranka 12:9a20164dcc47 375
vipinranka 12:9a20164dcc47 376 // GPIO is setup now, but we need to map GPIO to the pin
vipinranka 12:9a20164dcc47 377 switch (((UARTName)(obj->uart))) {
vipinranka 12:9a20164dcc47 378 case UART_0:
vipinranka 12:9a20164dcc47 379 MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
vipinranka 12:9a20164dcc47 380 MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
vipinranka 12:9a20164dcc47 381 break;
vipinranka 12:9a20164dcc47 382 case UART_1:
vipinranka 12:9a20164dcc47 383 MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
vipinranka 12:9a20164dcc47 384 MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
vipinranka 12:9a20164dcc47 385 break;
vipinranka 12:9a20164dcc47 386 case UART_2:
vipinranka 12:9a20164dcc47 387 MXC_IOMAN->uart2_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
vipinranka 12:9a20164dcc47 388 MBED_ASSERT((MXC_IOMAN->uart2_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
vipinranka 12:9a20164dcc47 389 break;
vipinranka 12:9a20164dcc47 390 case UART_3:
vipinranka 12:9a20164dcc47 391 MXC_IOMAN->uart3_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
vipinranka 12:9a20164dcc47 392 MBED_ASSERT((MXC_IOMAN->uart3_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
vipinranka 12:9a20164dcc47 393 break;
vipinranka 12:9a20164dcc47 394 default:
vipinranka 12:9a20164dcc47 395 break;
vipinranka 12:9a20164dcc47 396 }
vipinranka 12:9a20164dcc47 397 }
vipinranka 12:9a20164dcc47 398
vipinranka 12:9a20164dcc47 399 //******************************************************************************
vipinranka 12:9a20164dcc47 400 void serial_break_clear(serial_t *obj)
vipinranka 12:9a20164dcc47 401 {
vipinranka 12:9a20164dcc47 402 // Configure the GPIO to output 1
vipinranka 12:9a20164dcc47 403 gpio_t tx_gpio;
vipinranka 12:9a20164dcc47 404 switch (((UARTName)(obj->uart))) {
vipinranka 12:9a20164dcc47 405 case UART_0:
vipinranka 12:9a20164dcc47 406 gpio_init_out(&tx_gpio, UART0_TX);
vipinranka 12:9a20164dcc47 407 break;
vipinranka 12:9a20164dcc47 408 case UART_1:
vipinranka 12:9a20164dcc47 409 gpio_init_out(&tx_gpio, UART1_TX);
vipinranka 12:9a20164dcc47 410 break;
vipinranka 12:9a20164dcc47 411 case UART_2:
vipinranka 12:9a20164dcc47 412 gpio_init_out(&tx_gpio, UART2_TX);
vipinranka 12:9a20164dcc47 413 break;
vipinranka 12:9a20164dcc47 414 case UART_3:
vipinranka 12:9a20164dcc47 415 gpio_init_out(&tx_gpio, UART3_TX);
vipinranka 12:9a20164dcc47 416 break;
vipinranka 12:9a20164dcc47 417 default:
vipinranka 12:9a20164dcc47 418 gpio_init_out(&tx_gpio, (PinName)NC);
vipinranka 12:9a20164dcc47 419 break;
vipinranka 12:9a20164dcc47 420 }
vipinranka 12:9a20164dcc47 421
vipinranka 12:9a20164dcc47 422 gpio_write(&tx_gpio, 1);
vipinranka 12:9a20164dcc47 423
vipinranka 12:9a20164dcc47 424 // Renable UART
vipinranka 12:9a20164dcc47 425 switch (((UARTName)(obj->uart))) {
vipinranka 12:9a20164dcc47 426 case UART_0:
vipinranka 12:9a20164dcc47 427 serial_pinout_tx(UART0_TX);
vipinranka 12:9a20164dcc47 428 break;
vipinranka 12:9a20164dcc47 429 case UART_1:
vipinranka 12:9a20164dcc47 430 serial_pinout_tx(UART1_TX);
vipinranka 12:9a20164dcc47 431 break;
vipinranka 12:9a20164dcc47 432 case UART_2:
vipinranka 12:9a20164dcc47 433 serial_pinout_tx(UART2_TX);
vipinranka 12:9a20164dcc47 434 break;
vipinranka 12:9a20164dcc47 435 case UART_3:
vipinranka 12:9a20164dcc47 436 serial_pinout_tx(UART3_TX);
vipinranka 12:9a20164dcc47 437 break;
vipinranka 12:9a20164dcc47 438 default:
vipinranka 12:9a20164dcc47 439 serial_pinout_tx((PinName)NC);
vipinranka 12:9a20164dcc47 440 break;
vipinranka 12:9a20164dcc47 441 }
vipinranka 12:9a20164dcc47 442 }
vipinranka 12:9a20164dcc47 443
vipinranka 12:9a20164dcc47 444 //******************************************************************************
vipinranka 12:9a20164dcc47 445 void serial_pinout_tx(PinName tx)
vipinranka 12:9a20164dcc47 446 {
vipinranka 12:9a20164dcc47 447 pinmap_pinout(tx, PinMap_UART_TX);
vipinranka 12:9a20164dcc47 448 }
vipinranka 12:9a20164dcc47 449
vipinranka 12:9a20164dcc47 450 //******************************************************************************
vipinranka 12:9a20164dcc47 451 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
vipinranka 12:9a20164dcc47 452 {
vipinranka 12:9a20164dcc47 453 uint32_t ctrl = obj->uart->ctrl;
vipinranka 12:9a20164dcc47 454
vipinranka 12:9a20164dcc47 455 // Disable hardware flow control
vipinranka 12:9a20164dcc47 456 ctrl &= ~(MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_CTS_EN);
vipinranka 12:9a20164dcc47 457
vipinranka 12:9a20164dcc47 458 if (FlowControlNone != type) {
vipinranka 12:9a20164dcc47 459 // Check to see if we can use HW flow control
vipinranka 12:9a20164dcc47 460 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
vipinranka 12:9a20164dcc47 461 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
vipinranka 12:9a20164dcc47 462 UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
vipinranka 12:9a20164dcc47 463
vipinranka 12:9a20164dcc47 464 // Make sure that the pins are pointing to the same UART
vipinranka 12:9a20164dcc47 465 MBED_ASSERT(uart != (UARTName)NC);
vipinranka 12:9a20164dcc47 466
vipinranka 12:9a20164dcc47 467 if ((FlowControlCTS == type) || (FlowControlRTSCTS == type)) {
vipinranka 12:9a20164dcc47 468 // Make sure pin is in the PinMap
vipinranka 12:9a20164dcc47 469 MBED_ASSERT(uart_cts != (UARTName)NC);
vipinranka 12:9a20164dcc47 470
vipinranka 12:9a20164dcc47 471 // Enable the pin for CTS function
vipinranka 12:9a20164dcc47 472 pinmap_pinout(txflow, PinMap_UART_CTS);
vipinranka 12:9a20164dcc47 473
vipinranka 12:9a20164dcc47 474 // Enable active-low hardware flow control
vipinranka 12:9a20164dcc47 475 ctrl |= (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_CTS_POLARITY);
vipinranka 12:9a20164dcc47 476 }
vipinranka 12:9a20164dcc47 477
vipinranka 12:9a20164dcc47 478 if ((FlowControlRTS == type) || (FlowControlRTSCTS == type)) {
vipinranka 12:9a20164dcc47 479 // Make sure pin is in the PinMap
vipinranka 12:9a20164dcc47 480 MBED_ASSERT(uart_rts != (UARTName)NC);
vipinranka 12:9a20164dcc47 481
vipinranka 12:9a20164dcc47 482 // Enable the pin for RTS function
vipinranka 12:9a20164dcc47 483 pinmap_pinout(rxflow, PinMap_UART_RTS);
vipinranka 12:9a20164dcc47 484
vipinranka 12:9a20164dcc47 485 // Enable active-low hardware flow control
vipinranka 12:9a20164dcc47 486 ctrl |= (MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_RTS_POLARITY);
vipinranka 12:9a20164dcc47 487 }
vipinranka 12:9a20164dcc47 488 }
vipinranka 12:9a20164dcc47 489
vipinranka 12:9a20164dcc47 490 obj->uart->ctrl = ctrl;
vipinranka 12:9a20164dcc47 491 }