Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /*******************************************************************************
vipinranka 12:9a20164dcc47 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
vipinranka 12:9a20164dcc47 3 *
vipinranka 12:9a20164dcc47 4 * Permission is hereby granted, free of charge, to any person obtaining a
vipinranka 12:9a20164dcc47 5 * copy of this software and associated documentation files (the "Software"),
vipinranka 12:9a20164dcc47 6 * to deal in the Software without restriction, including without limitation
vipinranka 12:9a20164dcc47 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
vipinranka 12:9a20164dcc47 8 * and/or sell copies of the Software, and to permit persons to whom the
vipinranka 12:9a20164dcc47 9 * Software is furnished to do so, subject to the following conditions:
vipinranka 12:9a20164dcc47 10 *
vipinranka 12:9a20164dcc47 11 * The above copyright notice and this permission notice shall be included
vipinranka 12:9a20164dcc47 12 * in all copies or substantial portions of the Software.
vipinranka 12:9a20164dcc47 13 *
vipinranka 12:9a20164dcc47 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
vipinranka 12:9a20164dcc47 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
vipinranka 12:9a20164dcc47 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
vipinranka 12:9a20164dcc47 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
vipinranka 12:9a20164dcc47 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
vipinranka 12:9a20164dcc47 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
vipinranka 12:9a20164dcc47 20 * OTHER DEALINGS IN THE SOFTWARE.
vipinranka 12:9a20164dcc47 21 *
vipinranka 12:9a20164dcc47 22 * Except as contained in this notice, the name of Maxim Integrated
vipinranka 12:9a20164dcc47 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
vipinranka 12:9a20164dcc47 24 * Products, Inc. Branding Policy.
vipinranka 12:9a20164dcc47 25 *
vipinranka 12:9a20164dcc47 26 * The mere transfer of this software does not imply any licenses
vipinranka 12:9a20164dcc47 27 * of trade secrets, proprietary technology, copyrights, patents,
vipinranka 12:9a20164dcc47 28 * trademarks, maskwork rights, or any other form of intellectual
vipinranka 12:9a20164dcc47 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
vipinranka 12:9a20164dcc47 30 * ownership rights.
vipinranka 12:9a20164dcc47 31 *******************************************************************************
vipinranka 12:9a20164dcc47 32 */
vipinranka 12:9a20164dcc47 33
vipinranka 12:9a20164dcc47 34 #include "rtc_api.h"
vipinranka 12:9a20164dcc47 35 #include "lp_ticker_api.h"
vipinranka 12:9a20164dcc47 36 #include "cmsis.h"
vipinranka 12:9a20164dcc47 37 #include "rtc_regs.h"
vipinranka 12:9a20164dcc47 38 #include "pwrseq_regs.h"
vipinranka 12:9a20164dcc47 39 #include "clkman_regs.h"
vipinranka 12:9a20164dcc47 40
vipinranka 12:9a20164dcc47 41 /**
vipinranka 12:9a20164dcc47 42 * Defines clock divider for 4096Hz input clock.
vipinranka 12:9a20164dcc47 43 */
vipinranka 12:9a20164dcc47 44 typedef enum {
vipinranka 12:9a20164dcc47 45 /** (4kHz) divide input clock by 2^0 = 1 */
vipinranka 12:9a20164dcc47 46 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
vipinranka 12:9a20164dcc47 47 /** (2kHz) divide input clock by 2^1 = 2 */
vipinranka 12:9a20164dcc47 48 MXC_E_RTC_PRESCALE_DIV_2_1,
vipinranka 12:9a20164dcc47 49 /** (1kHz) divide input clock by 2^2 = 4 */
vipinranka 12:9a20164dcc47 50 MXC_E_RTC_PRESCALE_DIV_2_2,
vipinranka 12:9a20164dcc47 51 /** (512Hz) divide input clock by 2^3 = 8 */
vipinranka 12:9a20164dcc47 52 MXC_E_RTC_PRESCALE_DIV_2_3,
vipinranka 12:9a20164dcc47 53 /** (256Hz) divide input clock by 2^4 = 16 */
vipinranka 12:9a20164dcc47 54 MXC_E_RTC_PRESCALE_DIV_2_4,
vipinranka 12:9a20164dcc47 55 /** (128Hz) divide input clock by 2^5 = 32 */
vipinranka 12:9a20164dcc47 56 MXC_E_RTC_PRESCALE_DIV_2_5,
vipinranka 12:9a20164dcc47 57 /** (64Hz) divide input clock by 2^6 = 64 */
vipinranka 12:9a20164dcc47 58 MXC_E_RTC_PRESCALE_DIV_2_6,
vipinranka 12:9a20164dcc47 59 /** (32Hz) divide input clock by 2^7 = 128 */
vipinranka 12:9a20164dcc47 60 MXC_E_RTC_PRESCALE_DIV_2_7,
vipinranka 12:9a20164dcc47 61 /** (16Hz) divide input clock by 2^8 = 256 */
vipinranka 12:9a20164dcc47 62 MXC_E_RTC_PRESCALE_DIV_2_8,
vipinranka 12:9a20164dcc47 63 /** (8Hz) divide input clock by 2^9 = 512 */
vipinranka 12:9a20164dcc47 64 MXC_E_RTC_PRESCALE_DIV_2_9,
vipinranka 12:9a20164dcc47 65 /** (4Hz) divide input clock by 2^10 = 1024 */
vipinranka 12:9a20164dcc47 66 MXC_E_RTC_PRESCALE_DIV_2_10,
vipinranka 12:9a20164dcc47 67 /** (2Hz) divide input clock by 2^11 = 2048 */
vipinranka 12:9a20164dcc47 68 MXC_E_RTC_PRESCALE_DIV_2_11,
vipinranka 12:9a20164dcc47 69 /** (1Hz) divide input clock by 2^12 = 4096 */
vipinranka 12:9a20164dcc47 70 MXC_E_RTC_PRESCALE_DIV_2_12,
vipinranka 12:9a20164dcc47 71 } mxc_rtc_prescale_t;
vipinranka 12:9a20164dcc47 72
vipinranka 12:9a20164dcc47 73 #define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
vipinranka 12:9a20164dcc47 74 #define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
vipinranka 12:9a20164dcc47 75
vipinranka 12:9a20164dcc47 76 #define WINDOW 1000
vipinranka 12:9a20164dcc47 77
vipinranka 12:9a20164dcc47 78 static int rtc_inited = 0;
vipinranka 12:9a20164dcc47 79 static volatile uint32_t overflow_cnt = 0;
vipinranka 12:9a20164dcc47 80
vipinranka 12:9a20164dcc47 81 static uint64_t rtc_read64(void);
vipinranka 12:9a20164dcc47 82
vipinranka 12:9a20164dcc47 83 //******************************************************************************
vipinranka 12:9a20164dcc47 84 static void overflow_handler(void)
vipinranka 12:9a20164dcc47 85 {
vipinranka 12:9a20164dcc47 86 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
vipinranka 12:9a20164dcc47 87 overflow_cnt++;
vipinranka 12:9a20164dcc47 88
vipinranka 12:9a20164dcc47 89 // Wait for pending transactions
vipinranka 12:9a20164dcc47 90 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
vipinranka 12:9a20164dcc47 91 }
vipinranka 12:9a20164dcc47 92
vipinranka 12:9a20164dcc47 93 //******************************************************************************
vipinranka 12:9a20164dcc47 94 void rtc_init(void)
vipinranka 12:9a20164dcc47 95 {
vipinranka 12:9a20164dcc47 96 if (rtc_inited) {
vipinranka 12:9a20164dcc47 97 return;
vipinranka 12:9a20164dcc47 98 }
vipinranka 12:9a20164dcc47 99 rtc_inited = 1;
vipinranka 12:9a20164dcc47 100
vipinranka 12:9a20164dcc47 101 overflow_cnt = 0;
vipinranka 12:9a20164dcc47 102
vipinranka 12:9a20164dcc47 103 // Enable the clock to the synchronizer
vipinranka 12:9a20164dcc47 104 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
vipinranka 12:9a20164dcc47 105
vipinranka 12:9a20164dcc47 106 // Enable the clock to the RTC
vipinranka 12:9a20164dcc47 107 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
vipinranka 12:9a20164dcc47 108
vipinranka 12:9a20164dcc47 109 // Prepare interrupt handlers
vipinranka 12:9a20164dcc47 110 NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
vipinranka 12:9a20164dcc47 111 NVIC_EnableIRQ(RTC0_IRQn);
vipinranka 12:9a20164dcc47 112 NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
vipinranka 12:9a20164dcc47 113 NVIC_EnableIRQ(RTC3_IRQn);
vipinranka 12:9a20164dcc47 114
vipinranka 12:9a20164dcc47 115 // Enable wakeup on RTC rollover
vipinranka 12:9a20164dcc47 116 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
vipinranka 12:9a20164dcc47 117
vipinranka 12:9a20164dcc47 118 /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
vipinranka 12:9a20164dcc47 119 * if it is already running.
vipinranka 12:9a20164dcc47 120 */
vipinranka 12:9a20164dcc47 121 if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) {
vipinranka 12:9a20164dcc47 122 // Set the clock divider
vipinranka 12:9a20164dcc47 123 MXC_RTCTMR->prescale = PRESCALE_VAL;
vipinranka 12:9a20164dcc47 124
vipinranka 12:9a20164dcc47 125 // Enable the overflow interrupt
vipinranka 12:9a20164dcc47 126 MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
vipinranka 12:9a20164dcc47 127
vipinranka 12:9a20164dcc47 128 // Restart the timer from 0
vipinranka 12:9a20164dcc47 129 MXC_RTCTMR->timer = 0;
vipinranka 12:9a20164dcc47 130
vipinranka 12:9a20164dcc47 131 // Enable the RTC
vipinranka 12:9a20164dcc47 132 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
vipinranka 12:9a20164dcc47 133 }
vipinranka 12:9a20164dcc47 134 }
vipinranka 12:9a20164dcc47 135
vipinranka 12:9a20164dcc47 136 //******************************************************************************
vipinranka 12:9a20164dcc47 137 void lp_ticker_init(void)
vipinranka 12:9a20164dcc47 138 {
vipinranka 12:9a20164dcc47 139 rtc_init();
vipinranka 12:9a20164dcc47 140 }
vipinranka 12:9a20164dcc47 141
vipinranka 12:9a20164dcc47 142 //******************************************************************************
vipinranka 12:9a20164dcc47 143 void rtc_free(void)
vipinranka 12:9a20164dcc47 144 {
vipinranka 12:9a20164dcc47 145 if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
vipinranka 12:9a20164dcc47 146 // Clear and disable RTC
vipinranka 12:9a20164dcc47 147 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
vipinranka 12:9a20164dcc47 148 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
vipinranka 12:9a20164dcc47 149
vipinranka 12:9a20164dcc47 150 // Wait for pending transactions
vipinranka 12:9a20164dcc47 151 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
vipinranka 12:9a20164dcc47 152 }
vipinranka 12:9a20164dcc47 153
vipinranka 12:9a20164dcc47 154 // Disable the clock to the RTC
vipinranka 12:9a20164dcc47 155 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
vipinranka 12:9a20164dcc47 156
vipinranka 12:9a20164dcc47 157 // Disable the clock to the synchronizer
vipinranka 12:9a20164dcc47 158 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DISABLED;
vipinranka 12:9a20164dcc47 159 }
vipinranka 12:9a20164dcc47 160
vipinranka 12:9a20164dcc47 161 //******************************************************************************
vipinranka 12:9a20164dcc47 162 int rtc_isenabled(void)
vipinranka 12:9a20164dcc47 163 {
vipinranka 12:9a20164dcc47 164 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
vipinranka 12:9a20164dcc47 165 }
vipinranka 12:9a20164dcc47 166
vipinranka 12:9a20164dcc47 167 //******************************************************************************
vipinranka 12:9a20164dcc47 168 time_t rtc_read(void)
vipinranka 12:9a20164dcc47 169 {
vipinranka 12:9a20164dcc47 170 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
vipinranka 12:9a20164dcc47 171 uint32_t ovf1, ovf2;
vipinranka 12:9a20164dcc47 172
vipinranka 12:9a20164dcc47 173 // Make sure RTC is setup before trying to read
vipinranka 12:9a20164dcc47 174 if (!rtc_inited) {
vipinranka 12:9a20164dcc47 175 rtc_init();
vipinranka 12:9a20164dcc47 176 }
vipinranka 12:9a20164dcc47 177
vipinranka 12:9a20164dcc47 178 // Ensure coherency between overflow_cnt and timer
vipinranka 12:9a20164dcc47 179 do {
vipinranka 12:9a20164dcc47 180 ovf_cnt_1 = overflow_cnt;
vipinranka 12:9a20164dcc47 181 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
vipinranka 12:9a20164dcc47 182 timer_cnt = MXC_RTCTMR->timer;
vipinranka 12:9a20164dcc47 183 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
vipinranka 12:9a20164dcc47 184 ovf_cnt_2 = overflow_cnt;
vipinranka 12:9a20164dcc47 185 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
vipinranka 12:9a20164dcc47 186
vipinranka 12:9a20164dcc47 187 // Account for an unserviced interrupt
vipinranka 12:9a20164dcc47 188 if (ovf1) {
vipinranka 12:9a20164dcc47 189 ovf_cnt_1++;
vipinranka 12:9a20164dcc47 190 }
vipinranka 12:9a20164dcc47 191
vipinranka 12:9a20164dcc47 192 return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
vipinranka 12:9a20164dcc47 193 }
vipinranka 12:9a20164dcc47 194
vipinranka 12:9a20164dcc47 195 //******************************************************************************
vipinranka 12:9a20164dcc47 196 static uint64_t rtc_read64(void)
vipinranka 12:9a20164dcc47 197 {
vipinranka 12:9a20164dcc47 198 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
vipinranka 12:9a20164dcc47 199 uint32_t ovf1, ovf2;
vipinranka 12:9a20164dcc47 200 uint64_t current_us;
vipinranka 12:9a20164dcc47 201
vipinranka 12:9a20164dcc47 202 // Make sure RTC is setup before trying to read
vipinranka 12:9a20164dcc47 203 if (!rtc_inited) {
vipinranka 12:9a20164dcc47 204 rtc_init();
vipinranka 12:9a20164dcc47 205 }
vipinranka 12:9a20164dcc47 206
vipinranka 12:9a20164dcc47 207 // Ensure coherency between overflow_cnt and timer
vipinranka 12:9a20164dcc47 208 do {
vipinranka 12:9a20164dcc47 209 ovf_cnt_1 = overflow_cnt;
vipinranka 12:9a20164dcc47 210 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
vipinranka 12:9a20164dcc47 211 timer_cnt = MXC_RTCTMR->timer;
vipinranka 12:9a20164dcc47 212 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
vipinranka 12:9a20164dcc47 213 ovf_cnt_2 = overflow_cnt;
vipinranka 12:9a20164dcc47 214 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
vipinranka 12:9a20164dcc47 215
vipinranka 12:9a20164dcc47 216 // Account for an unserviced interrupt
vipinranka 12:9a20164dcc47 217 if (ovf1) {
vipinranka 12:9a20164dcc47 218 ovf_cnt_1++;
vipinranka 12:9a20164dcc47 219 }
vipinranka 12:9a20164dcc47 220
vipinranka 12:9a20164dcc47 221 current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
vipinranka 12:9a20164dcc47 222
vipinranka 12:9a20164dcc47 223 return current_us;
vipinranka 12:9a20164dcc47 224 }
vipinranka 12:9a20164dcc47 225
vipinranka 12:9a20164dcc47 226 //******************************************************************************
vipinranka 12:9a20164dcc47 227 void rtc_write(time_t t)
vipinranka 12:9a20164dcc47 228 {
vipinranka 12:9a20164dcc47 229 // Make sure RTC is setup before accessing
vipinranka 12:9a20164dcc47 230 if (!rtc_inited) {
vipinranka 12:9a20164dcc47 231 rtc_init();
vipinranka 12:9a20164dcc47 232 }
vipinranka 12:9a20164dcc47 233
vipinranka 12:9a20164dcc47 234 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
vipinranka 12:9a20164dcc47 235 MXC_RTCTMR->timer = t << SHIFT_AMT;
vipinranka 12:9a20164dcc47 236 overflow_cnt = t >> (32 - SHIFT_AMT);
vipinranka 12:9a20164dcc47 237 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating
vipinranka 12:9a20164dcc47 238 }
vipinranka 12:9a20164dcc47 239
vipinranka 12:9a20164dcc47 240 //******************************************************************************
vipinranka 12:9a20164dcc47 241 void lp_ticker_set_interrupt(timestamp_t timestamp)
vipinranka 12:9a20164dcc47 242 {
vipinranka 12:9a20164dcc47 243 uint32_t comp_value;
vipinranka 12:9a20164dcc47 244 uint64_t curr_ts64;
vipinranka 12:9a20164dcc47 245 uint64_t ts64;
vipinranka 12:9a20164dcc47 246
vipinranka 12:9a20164dcc47 247 // Note: interrupts are disabled before this function is called.
vipinranka 12:9a20164dcc47 248
vipinranka 12:9a20164dcc47 249 // Disable the alarm while it is prepared
vipinranka 12:9a20164dcc47 250 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
vipinranka 12:9a20164dcc47 251
vipinranka 12:9a20164dcc47 252 curr_ts64 = rtc_read64();
vipinranka 12:9a20164dcc47 253 ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
vipinranka 12:9a20164dcc47 254
vipinranka 12:9a20164dcc47 255 // If this event is older than a recent window, it must be in the future
vipinranka 12:9a20164dcc47 256 if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
vipinranka 12:9a20164dcc47 257 ts64 += 0x100000000ULL;
vipinranka 12:9a20164dcc47 258 }
vipinranka 12:9a20164dcc47 259
vipinranka 12:9a20164dcc47 260 uint32_t timer = MXC_RTCTMR->timer;
vipinranka 12:9a20164dcc47 261 if (ts64 <= curr_ts64) {
vipinranka 12:9a20164dcc47 262 // This event has already occurred. Set the alarm to expire immediately.
vipinranka 12:9a20164dcc47 263 comp_value = timer + 1;
vipinranka 12:9a20164dcc47 264 } else {
vipinranka 12:9a20164dcc47 265 comp_value = (ts64 << SHIFT_AMT) / 1000000;
vipinranka 12:9a20164dcc47 266 }
vipinranka 12:9a20164dcc47 267
vipinranka 12:9a20164dcc47 268 // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
vipinranka 12:9a20164dcc47 269 if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
vipinranka 12:9a20164dcc47 270 comp_value = timer + 2;
vipinranka 12:9a20164dcc47 271 }
vipinranka 12:9a20164dcc47 272
vipinranka 12:9a20164dcc47 273 MXC_RTCTMR->comp[0] = comp_value;
vipinranka 12:9a20164dcc47 274 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
vipinranka 12:9a20164dcc47 275 MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
vipinranka 12:9a20164dcc47 276
vipinranka 12:9a20164dcc47 277 // Enable wakeup from RTC
vipinranka 12:9a20164dcc47 278 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
vipinranka 12:9a20164dcc47 279
vipinranka 12:9a20164dcc47 280 // Wait for pending transactions
vipinranka 12:9a20164dcc47 281 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
vipinranka 12:9a20164dcc47 282 }
vipinranka 12:9a20164dcc47 283
vipinranka 12:9a20164dcc47 284 //******************************************************************************
vipinranka 12:9a20164dcc47 285 inline void lp_ticker_disable_interrupt(void)
vipinranka 12:9a20164dcc47 286 {
vipinranka 12:9a20164dcc47 287 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
vipinranka 12:9a20164dcc47 288 }
vipinranka 12:9a20164dcc47 289
vipinranka 12:9a20164dcc47 290 //******************************************************************************
vipinranka 12:9a20164dcc47 291 inline void lp_ticker_clear_interrupt(void)
vipinranka 12:9a20164dcc47 292 {
vipinranka 12:9a20164dcc47 293 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
vipinranka 12:9a20164dcc47 294
vipinranka 12:9a20164dcc47 295 // Wait for pending transactions
vipinranka 12:9a20164dcc47 296 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
vipinranka 12:9a20164dcc47 297 }
vipinranka 12:9a20164dcc47 298
vipinranka 12:9a20164dcc47 299 //******************************************************************************
vipinranka 12:9a20164dcc47 300 inline uint32_t lp_ticker_read(void)
vipinranka 12:9a20164dcc47 301 {
vipinranka 12:9a20164dcc47 302 return rtc_read64();
vipinranka 12:9a20164dcc47 303 }