Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /*******************************************************************************
vipinranka 12:9a20164dcc47 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
vipinranka 12:9a20164dcc47 3 *
vipinranka 12:9a20164dcc47 4 * Permission is hereby granted, free of charge, to any person obtaining a
vipinranka 12:9a20164dcc47 5 * copy of this software and associated documentation files (the "Software"),
vipinranka 12:9a20164dcc47 6 * to deal in the Software without restriction, including without limitation
vipinranka 12:9a20164dcc47 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
vipinranka 12:9a20164dcc47 8 * and/or sell copies of the Software, and to permit persons to whom the
vipinranka 12:9a20164dcc47 9 * Software is furnished to do so, subject to the following conditions:
vipinranka 12:9a20164dcc47 10 *
vipinranka 12:9a20164dcc47 11 * The above copyright notice and this permission notice shall be included
vipinranka 12:9a20164dcc47 12 * in all copies or substantial portions of the Software.
vipinranka 12:9a20164dcc47 13 *
vipinranka 12:9a20164dcc47 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
vipinranka 12:9a20164dcc47 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
vipinranka 12:9a20164dcc47 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
vipinranka 12:9a20164dcc47 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
vipinranka 12:9a20164dcc47 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
vipinranka 12:9a20164dcc47 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
vipinranka 12:9a20164dcc47 20 * OTHER DEALINGS IN THE SOFTWARE.
vipinranka 12:9a20164dcc47 21 *
vipinranka 12:9a20164dcc47 22 * Except as contained in this notice, the name of Maxim Integrated
vipinranka 12:9a20164dcc47 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
vipinranka 12:9a20164dcc47 24 * Products, Inc. Branding Policy.
vipinranka 12:9a20164dcc47 25 *
vipinranka 12:9a20164dcc47 26 * The mere transfer of this software does not imply any licenses
vipinranka 12:9a20164dcc47 27 * of trade secrets, proprietary technology, copyrights, patents,
vipinranka 12:9a20164dcc47 28 * trademarks, maskwork rights, or any other form of intellectual
vipinranka 12:9a20164dcc47 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
vipinranka 12:9a20164dcc47 30 * ownership rights.
vipinranka 12:9a20164dcc47 31 *******************************************************************************
vipinranka 12:9a20164dcc47 32 */
vipinranka 12:9a20164dcc47 33
vipinranka 12:9a20164dcc47 34 #include <stddef.h>
vipinranka 12:9a20164dcc47 35 #include "cmsis.h"
vipinranka 12:9a20164dcc47 36 #include "gpio_irq_api.h"
vipinranka 12:9a20164dcc47 37 #include "mbed_error.h"
vipinranka 12:9a20164dcc47 38 #include "ioman_regs.h"
vipinranka 12:9a20164dcc47 39 #include "pwrman_regs.h"
vipinranka 12:9a20164dcc47 40 #include "pwrseq_regs.h"
vipinranka 12:9a20164dcc47 41
vipinranka 12:9a20164dcc47 42 static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}};
vipinranka 12:9a20164dcc47 43 static gpio_irq_handler irq_handler;
vipinranka 12:9a20164dcc47 44
vipinranka 12:9a20164dcc47 45 static void gpio_irq_wud_req(gpio_irq_t *obj)
vipinranka 12:9a20164dcc47 46 {
vipinranka 12:9a20164dcc47 47 unsigned int port = obj->port;
vipinranka 12:9a20164dcc47 48 unsigned int pin = obj->pin;
vipinranka 12:9a20164dcc47 49 uint32_t pin_mask = 1 << pin;
vipinranka 12:9a20164dcc47 50
vipinranka 12:9a20164dcc47 51 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1 */
vipinranka 12:9a20164dcc47 52 /* During the time the WUD IOMAN requests are asserted (1), the GPIO Pad */
vipinranka 12:9a20164dcc47 53 /* is in HIGH Z mode, regardless of GPIO setting. This may cause bogus interrupts. */
vipinranka 12:9a20164dcc47 54 if (port < 4) {
vipinranka 12:9a20164dcc47 55 uint32_t mask = pin_mask << (port << 3);
vipinranka 12:9a20164dcc47 56 if (!(MXC_IOMAN->wud_ack0 & mask)) {
vipinranka 12:9a20164dcc47 57 MXC_IOMAN->wud_req0 |= mask;
vipinranka 12:9a20164dcc47 58 while(!(MXC_IOMAN->wud_ack0 & mask));
vipinranka 12:9a20164dcc47 59 }
vipinranka 12:9a20164dcc47 60 } else if (port < 8) {
vipinranka 12:9a20164dcc47 61 uint32_t mask = pin_mask << ((port-4) << 3);
vipinranka 12:9a20164dcc47 62 if (!(MXC_IOMAN->wud_ack1 & mask)) {
vipinranka 12:9a20164dcc47 63 MXC_IOMAN->wud_req1 |= mask;
vipinranka 12:9a20164dcc47 64 while(!(MXC_IOMAN->wud_ack1 & mask));
vipinranka 12:9a20164dcc47 65 }
vipinranka 12:9a20164dcc47 66 }
vipinranka 12:9a20164dcc47 67 }
vipinranka 12:9a20164dcc47 68
vipinranka 12:9a20164dcc47 69 /* Clear the selected pin from wake-up detect */
vipinranka 12:9a20164dcc47 70 static void gpio_irq_wud_clear(gpio_irq_t *obj)
vipinranka 12:9a20164dcc47 71 {
vipinranka 12:9a20164dcc47 72 unsigned int port = obj->port;
vipinranka 12:9a20164dcc47 73 unsigned int pin = obj->pin;
vipinranka 12:9a20164dcc47 74
vipinranka 12:9a20164dcc47 75 /* Enable modifications to WUD configuration */
vipinranka 12:9a20164dcc47 76 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
vipinranka 12:9a20164dcc47 77
vipinranka 12:9a20164dcc47 78 /* Select pad in WUD control */
vipinranka 12:9a20164dcc47 79 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
vipinranka 12:9a20164dcc47 80 MXC_PWRMAN->wud_ctrl |= (port * 8) + pin;
vipinranka 12:9a20164dcc47 81
vipinranka 12:9a20164dcc47 82 /* Clear any existing WUD configuration for this pad */
vipinranka 12:9a20164dcc47 83 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
vipinranka 12:9a20164dcc47 84 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
vipinranka 12:9a20164dcc47 85 /* Clear with PULSE0; PULSE1 enables WUD */
vipinranka 12:9a20164dcc47 86 MXC_PWRMAN->wud_pulse0 = 1;
vipinranka 12:9a20164dcc47 87
vipinranka 12:9a20164dcc47 88 /* Disable configuration */
vipinranka 12:9a20164dcc47 89 MXC_PWRMAN->wud_ctrl = 0;
vipinranka 12:9a20164dcc47 90 MXC_IOMAN->wud_req0 = 0;
vipinranka 12:9a20164dcc47 91 MXC_IOMAN->wud_req1 = 0;
vipinranka 12:9a20164dcc47 92 }
vipinranka 12:9a20164dcc47 93
vipinranka 12:9a20164dcc47 94 /* Configure the selected pin for wake-up detect */
vipinranka 12:9a20164dcc47 95 static void gpio_irq_wud_config(gpio_irq_t *obj)
vipinranka 12:9a20164dcc47 96 {
vipinranka 12:9a20164dcc47 97 unsigned int port = obj->port;
vipinranka 12:9a20164dcc47 98 unsigned int pin = obj->pin;
vipinranka 12:9a20164dcc47 99 uint32_t pin_mask = 1 << pin;
vipinranka 12:9a20164dcc47 100
vipinranka 12:9a20164dcc47 101 /* Enable modifications to WUD configuration */
vipinranka 12:9a20164dcc47 102 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
vipinranka 12:9a20164dcc47 103
vipinranka 12:9a20164dcc47 104 /* Select pad in WUD control */
vipinranka 12:9a20164dcc47 105 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
vipinranka 12:9a20164dcc47 106 MXC_PWRMAN->wud_ctrl |= (port * 8) + pin;
vipinranka 12:9a20164dcc47 107
vipinranka 12:9a20164dcc47 108 /* First clear any existing WUD configuration for this pad */
vipinranka 12:9a20164dcc47 109 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
vipinranka 12:9a20164dcc47 110 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
vipinranka 12:9a20164dcc47 111 /* Clear with PULSE0; PULSE1 enables WUD */
vipinranka 12:9a20164dcc47 112 MXC_PWRMAN->wud_pulse0 = 1;
vipinranka 12:9a20164dcc47 113
vipinranka 12:9a20164dcc47 114 if (obj->fall_en || obj->rise_en) {
vipinranka 12:9a20164dcc47 115 /* Configure sense level on this pad */
vipinranka 12:9a20164dcc47 116 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
vipinranka 12:9a20164dcc47 117 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
vipinranka 12:9a20164dcc47 118
vipinranka 12:9a20164dcc47 119 uint32_t in_val = MXC_GPIO->in_val[port] & pin_mask;
vipinranka 12:9a20164dcc47 120 do {
vipinranka 12:9a20164dcc47 121 if (in_val) {
vipinranka 12:9a20164dcc47 122 /* Select active low with PULSE1 (backwards from what you'd expect) */
vipinranka 12:9a20164dcc47 123 MXC_PWRMAN->wud_pulse1 = 1;
vipinranka 12:9a20164dcc47 124 } else {
vipinranka 12:9a20164dcc47 125 /* Select active high with PULSE0 (backwards from what you'd expect) */
vipinranka 12:9a20164dcc47 126 MXC_PWRMAN->wud_pulse0 = 1;
vipinranka 12:9a20164dcc47 127 }
vipinranka 12:9a20164dcc47 128 } while ((MXC_GPIO->in_val[port] & pin_mask) != in_val);
vipinranka 12:9a20164dcc47 129
vipinranka 12:9a20164dcc47 130 /* Select this pad to have the wake-up function enabled */
vipinranka 12:9a20164dcc47 131 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
vipinranka 12:9a20164dcc47 132 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
vipinranka 12:9a20164dcc47 133 /* Activate with PULSE1 */
vipinranka 12:9a20164dcc47 134 MXC_PWRMAN->wud_pulse1 = 1;
vipinranka 12:9a20164dcc47 135
vipinranka 12:9a20164dcc47 136 // NOTE: Low Power Pullup/down is not normally needed in addition to
vipinranka 12:9a20164dcc47 137 // standard GPIO Pullup/downs.
vipinranka 12:9a20164dcc47 138
vipinranka 12:9a20164dcc47 139 /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
vipinranka 12:9a20164dcc47 140 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
vipinranka 12:9a20164dcc47 141 }
vipinranka 12:9a20164dcc47 142
vipinranka 12:9a20164dcc47 143 /* Disable configuration */
vipinranka 12:9a20164dcc47 144 MXC_PWRMAN->wud_ctrl = 0;
vipinranka 12:9a20164dcc47 145 MXC_IOMAN->wud_req0 = 0;
vipinranka 12:9a20164dcc47 146 MXC_IOMAN->wud_req1 = 0;
vipinranka 12:9a20164dcc47 147 }
vipinranka 12:9a20164dcc47 148
vipinranka 12:9a20164dcc47 149 static void handle_irq(unsigned int port)
vipinranka 12:9a20164dcc47 150 {
vipinranka 12:9a20164dcc47 151 uint32_t intfl, in_val;
vipinranka 12:9a20164dcc47 152 uint32_t mask;
vipinranka 12:9a20164dcc47 153 unsigned int pin;
vipinranka 12:9a20164dcc47 154
vipinranka 12:9a20164dcc47 155 /* Read pin state */
vipinranka 12:9a20164dcc47 156 in_val = MXC_GPIO->in_val[port];
vipinranka 12:9a20164dcc47 157
vipinranka 12:9a20164dcc47 158 /* Read interrupts */
vipinranka 12:9a20164dcc47 159 intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
vipinranka 12:9a20164dcc47 160
vipinranka 12:9a20164dcc47 161 mask = 1;
vipinranka 12:9a20164dcc47 162
vipinranka 12:9a20164dcc47 163 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
vipinranka 12:9a20164dcc47 164 if (intfl & mask) {
vipinranka 12:9a20164dcc47 165 MXC_GPIO->intfl[port] = mask; /* clear interrupt */
vipinranka 12:9a20164dcc47 166 gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL;
vipinranka 12:9a20164dcc47 167 gpio_irq_t *obj = objs[port][pin];
vipinranka 12:9a20164dcc47 168 if (obj && obj->id) {
vipinranka 12:9a20164dcc47 169 if ((event == IRQ_RISE) && obj->rise_en) {
vipinranka 12:9a20164dcc47 170 irq_handler(obj->id, IRQ_RISE);
vipinranka 12:9a20164dcc47 171 } else if ((event == IRQ_FALL) && obj->fall_en) {
vipinranka 12:9a20164dcc47 172 irq_handler(obj->id, IRQ_FALL);
vipinranka 12:9a20164dcc47 173 }
vipinranka 12:9a20164dcc47 174 }
vipinranka 12:9a20164dcc47 175
vipinranka 12:9a20164dcc47 176 gpio_irq_wud_config(obj);
vipinranka 12:9a20164dcc47 177 }
vipinranka 12:9a20164dcc47 178 mask <<= 1;
vipinranka 12:9a20164dcc47 179 }
vipinranka 12:9a20164dcc47 180 }
vipinranka 12:9a20164dcc47 181
vipinranka 12:9a20164dcc47 182 void gpio_irq_0(void) { handle_irq(0); }
vipinranka 12:9a20164dcc47 183 void gpio_irq_1(void) { handle_irq(1); }
vipinranka 12:9a20164dcc47 184 void gpio_irq_2(void) { handle_irq(2); }
vipinranka 12:9a20164dcc47 185 void gpio_irq_3(void) { handle_irq(3); }
vipinranka 12:9a20164dcc47 186 void gpio_irq_4(void) { handle_irq(4); }
vipinranka 12:9a20164dcc47 187 void gpio_irq_5(void) { handle_irq(5); }
vipinranka 12:9a20164dcc47 188 void gpio_irq_6(void) { handle_irq(6); }
vipinranka 12:9a20164dcc47 189
vipinranka 12:9a20164dcc47 190 int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
vipinranka 12:9a20164dcc47 191 {
vipinranka 12:9a20164dcc47 192 if (name == NC) {
vipinranka 12:9a20164dcc47 193 return -1;
vipinranka 12:9a20164dcc47 194 }
vipinranka 12:9a20164dcc47 195
vipinranka 12:9a20164dcc47 196 uint8_t port = PINNAME_TO_PORT(name);
vipinranka 12:9a20164dcc47 197 uint8_t pin = PINNAME_TO_PIN(name);
vipinranka 12:9a20164dcc47 198
vipinranka 12:9a20164dcc47 199 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
vipinranka 12:9a20164dcc47 200 return 1;
vipinranka 12:9a20164dcc47 201 }
vipinranka 12:9a20164dcc47 202
vipinranka 12:9a20164dcc47 203 obj->port = port;
vipinranka 12:9a20164dcc47 204 obj->pin = pin;
vipinranka 12:9a20164dcc47 205 obj->id = id;
vipinranka 12:9a20164dcc47 206 objs[port][pin] = obj;
vipinranka 12:9a20164dcc47 207
vipinranka 12:9a20164dcc47 208 /* register handlers */
vipinranka 12:9a20164dcc47 209 irq_handler = handler;
vipinranka 12:9a20164dcc47 210 NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0);
vipinranka 12:9a20164dcc47 211 NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1);
vipinranka 12:9a20164dcc47 212 NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2);
vipinranka 12:9a20164dcc47 213 NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3);
vipinranka 12:9a20164dcc47 214 NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4);
vipinranka 12:9a20164dcc47 215 NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5);
vipinranka 12:9a20164dcc47 216 NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6);
vipinranka 12:9a20164dcc47 217
vipinranka 12:9a20164dcc47 218 /* request WUD in case the application is going to sleep */
vipinranka 12:9a20164dcc47 219 gpio_irq_wud_req(obj);
vipinranka 12:9a20164dcc47 220
vipinranka 12:9a20164dcc47 221 /* disable the interrupt locally */
vipinranka 12:9a20164dcc47 222 MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
vipinranka 12:9a20164dcc47 223
vipinranka 12:9a20164dcc47 224 /* clear a pending request */
vipinranka 12:9a20164dcc47 225 MXC_GPIO->intfl[port] = 1 << pin;
vipinranka 12:9a20164dcc47 226
vipinranka 12:9a20164dcc47 227 /* enable the requested interrupt */
vipinranka 12:9a20164dcc47 228 MXC_GPIO->inten[port] |= (1 << pin);
vipinranka 12:9a20164dcc47 229 NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
vipinranka 12:9a20164dcc47 230
vipinranka 12:9a20164dcc47 231 return 0;
vipinranka 12:9a20164dcc47 232 }
vipinranka 12:9a20164dcc47 233
vipinranka 12:9a20164dcc47 234 void gpio_irq_free(gpio_irq_t *obj)
vipinranka 12:9a20164dcc47 235 {
vipinranka 12:9a20164dcc47 236 /* disable interrupt */
vipinranka 12:9a20164dcc47 237 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
vipinranka 12:9a20164dcc47 238 MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
vipinranka 12:9a20164dcc47 239 objs[obj->port][obj->pin] = NULL;
vipinranka 12:9a20164dcc47 240 gpio_irq_wud_clear(obj);
vipinranka 12:9a20164dcc47 241 }
vipinranka 12:9a20164dcc47 242
vipinranka 12:9a20164dcc47 243 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
vipinranka 12:9a20164dcc47 244 {
vipinranka 12:9a20164dcc47 245 if (event == IRQ_FALL) {
vipinranka 12:9a20164dcc47 246 obj->fall_en = enable;
vipinranka 12:9a20164dcc47 247 } else if (event == IRQ_RISE) {
vipinranka 12:9a20164dcc47 248 obj->rise_en = enable;
vipinranka 12:9a20164dcc47 249 }
vipinranka 12:9a20164dcc47 250
vipinranka 12:9a20164dcc47 251 if (obj->fall_en || obj->rise_en) {
vipinranka 12:9a20164dcc47 252 MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
vipinranka 12:9a20164dcc47 253 gpio_irq_wud_config(obj); /* enable WUD for this pin so we may wake from deepsleep as well */
vipinranka 12:9a20164dcc47 254 } else {
vipinranka 12:9a20164dcc47 255 MXC_GPIO->int_mode[obj->port] &= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
vipinranka 12:9a20164dcc47 256 gpio_irq_wud_clear(obj);
vipinranka 12:9a20164dcc47 257 }
vipinranka 12:9a20164dcc47 258 }
vipinranka 12:9a20164dcc47 259
vipinranka 12:9a20164dcc47 260 void gpio_irq_enable(gpio_irq_t *obj)
vipinranka 12:9a20164dcc47 261 {
vipinranka 12:9a20164dcc47 262 MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
vipinranka 12:9a20164dcc47 263 gpio_irq_wud_config(obj);
vipinranka 12:9a20164dcc47 264 }
vipinranka 12:9a20164dcc47 265
vipinranka 12:9a20164dcc47 266 void gpio_irq_disable(gpio_irq_t *obj)
vipinranka 12:9a20164dcc47 267 {
vipinranka 12:9a20164dcc47 268 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
vipinranka 12:9a20164dcc47 269 gpio_irq_wud_clear(obj);
vipinranka 12:9a20164dcc47 270 }
vipinranka 12:9a20164dcc47 271
vipinranka 12:9a20164dcc47 272 gpio_irq_t *gpio_irq_get_obj(PinName name)
vipinranka 12:9a20164dcc47 273 {
vipinranka 12:9a20164dcc47 274 if (name == NC) {
vipinranka 12:9a20164dcc47 275 return NULL;
vipinranka 12:9a20164dcc47 276 }
vipinranka 12:9a20164dcc47 277
vipinranka 12:9a20164dcc47 278 unsigned int port = PINNAME_TO_PORT(name);
vipinranka 12:9a20164dcc47 279 unsigned int pin = PINNAME_TO_PIN(name);
vipinranka 12:9a20164dcc47 280
vipinranka 12:9a20164dcc47 281 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
vipinranka 12:9a20164dcc47 282 return NULL;
vipinranka 12:9a20164dcc47 283 }
vipinranka 12:9a20164dcc47 284
vipinranka 12:9a20164dcc47 285 return objs[port][pin];
vipinranka 12:9a20164dcc47 286 }