Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/hal/spi_api.h@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1
vipinranka 12:9a20164dcc47 2 /** \addtogroup hal */
vipinranka 12:9a20164dcc47 3 /** @{*/
vipinranka 12:9a20164dcc47 4 /* mbed Microcontroller Library
vipinranka 12:9a20164dcc47 5 * Copyright (c) 2006-2013 ARM Limited
vipinranka 12:9a20164dcc47 6 *
vipinranka 12:9a20164dcc47 7 * Licensed under the Apache License, Version 2.0 (the "License");
vipinranka 12:9a20164dcc47 8 * you may not use this file except in compliance with the License.
vipinranka 12:9a20164dcc47 9 * You may obtain a copy of the License at
vipinranka 12:9a20164dcc47 10 *
vipinranka 12:9a20164dcc47 11 * http://www.apache.org/licenses/LICENSE-2.0
vipinranka 12:9a20164dcc47 12 *
vipinranka 12:9a20164dcc47 13 * Unless required by applicable law or agreed to in writing, software
vipinranka 12:9a20164dcc47 14 * distributed under the License is distributed on an "AS IS" BASIS,
vipinranka 12:9a20164dcc47 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
vipinranka 12:9a20164dcc47 16 * See the License for the specific language governing permissions and
vipinranka 12:9a20164dcc47 17 * limitations under the License.
vipinranka 12:9a20164dcc47 18 */
vipinranka 12:9a20164dcc47 19 #ifndef MBED_SPI_API_H
vipinranka 12:9a20164dcc47 20 #define MBED_SPI_API_H
vipinranka 12:9a20164dcc47 21
vipinranka 12:9a20164dcc47 22 #include "device.h"
vipinranka 12:9a20164dcc47 23 #include "hal/dma_api.h"
vipinranka 12:9a20164dcc47 24 #include "hal/buffer.h"
vipinranka 12:9a20164dcc47 25
vipinranka 12:9a20164dcc47 26 #if DEVICE_SPI
vipinranka 12:9a20164dcc47 27
vipinranka 12:9a20164dcc47 28 #define SPI_EVENT_ERROR (1 << 1)
vipinranka 12:9a20164dcc47 29 #define SPI_EVENT_COMPLETE (1 << 2)
vipinranka 12:9a20164dcc47 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
vipinranka 12:9a20164dcc47 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
vipinranka 12:9a20164dcc47 32
vipinranka 12:9a20164dcc47 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
vipinranka 12:9a20164dcc47 34
vipinranka 12:9a20164dcc47 35 #define SPI_FILL_WORD (0xFFFF)
vipinranka 12:9a20164dcc47 36
vipinranka 12:9a20164dcc47 37 #if DEVICE_SPI_ASYNCH
vipinranka 12:9a20164dcc47 38 /** Asynch SPI HAL structure
vipinranka 12:9a20164dcc47 39 */
vipinranka 12:9a20164dcc47 40 typedef struct {
vipinranka 12:9a20164dcc47 41 struct spi_s spi; /**< Target specific SPI structure */
vipinranka 12:9a20164dcc47 42 struct buffer_s tx_buff; /**< Tx buffer */
vipinranka 12:9a20164dcc47 43 struct buffer_s rx_buff; /**< Rx buffer */
vipinranka 12:9a20164dcc47 44 } spi_t;
vipinranka 12:9a20164dcc47 45
vipinranka 12:9a20164dcc47 46 #else
vipinranka 12:9a20164dcc47 47 /** Non-asynch SPI HAL structure
vipinranka 12:9a20164dcc47 48 */
vipinranka 12:9a20164dcc47 49 typedef struct spi_s spi_t;
vipinranka 12:9a20164dcc47 50
vipinranka 12:9a20164dcc47 51 #endif
vipinranka 12:9a20164dcc47 52
vipinranka 12:9a20164dcc47 53 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 54 extern "C" {
vipinranka 12:9a20164dcc47 55 #endif
vipinranka 12:9a20164dcc47 56
vipinranka 12:9a20164dcc47 57 /**
vipinranka 12:9a20164dcc47 58 * \defgroup hal_GeneralSPI SPI Configuration Functions
vipinranka 12:9a20164dcc47 59 * @{
vipinranka 12:9a20164dcc47 60 */
vipinranka 12:9a20164dcc47 61
vipinranka 12:9a20164dcc47 62 /** Initialize the SPI peripheral
vipinranka 12:9a20164dcc47 63 *
vipinranka 12:9a20164dcc47 64 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
vipinranka 12:9a20164dcc47 65 * @param[out] obj The SPI object to initialize
vipinranka 12:9a20164dcc47 66 * @param[in] mosi The pin to use for MOSI
vipinranka 12:9a20164dcc47 67 * @param[in] miso The pin to use for MISO
vipinranka 12:9a20164dcc47 68 * @param[in] sclk The pin to use for SCLK
vipinranka 12:9a20164dcc47 69 * @param[in] ssel The pin to use for SSEL
vipinranka 12:9a20164dcc47 70 */
vipinranka 12:9a20164dcc47 71 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
vipinranka 12:9a20164dcc47 72
vipinranka 12:9a20164dcc47 73 /** Release a SPI object
vipinranka 12:9a20164dcc47 74 *
vipinranka 12:9a20164dcc47 75 * TODO: spi_free is currently unimplemented
vipinranka 12:9a20164dcc47 76 * This will require reference counting at the C++ level to be safe
vipinranka 12:9a20164dcc47 77 *
vipinranka 12:9a20164dcc47 78 * Return the pins owned by the SPI object to their reset state
vipinranka 12:9a20164dcc47 79 * Disable the SPI peripheral
vipinranka 12:9a20164dcc47 80 * Disable the SPI clock
vipinranka 12:9a20164dcc47 81 * @param[in] obj The SPI object to deinitialize
vipinranka 12:9a20164dcc47 82 */
vipinranka 12:9a20164dcc47 83 void spi_free(spi_t *obj);
vipinranka 12:9a20164dcc47 84
vipinranka 12:9a20164dcc47 85 /** Configure the SPI format
vipinranka 12:9a20164dcc47 86 *
vipinranka 12:9a20164dcc47 87 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
vipinranka 12:9a20164dcc47 88 * The default bit order is MSB.
vipinranka 12:9a20164dcc47 89 * @param[in,out] obj The SPI object to configure
vipinranka 12:9a20164dcc47 90 * @param[in] bits The number of bits per frame
vipinranka 12:9a20164dcc47 91 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
vipinranka 12:9a20164dcc47 92 * @param[in] slave Zero for master mode or non-zero for slave mode
vipinranka 12:9a20164dcc47 93 */
vipinranka 12:9a20164dcc47 94 void spi_format(spi_t *obj, int bits, int mode, int slave);
vipinranka 12:9a20164dcc47 95
vipinranka 12:9a20164dcc47 96 /** Set the SPI baud rate
vipinranka 12:9a20164dcc47 97 *
vipinranka 12:9a20164dcc47 98 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
vipinranka 12:9a20164dcc47 99 * Configures the SPI peripheral's baud rate
vipinranka 12:9a20164dcc47 100 * @param[in,out] obj The SPI object to configure
vipinranka 12:9a20164dcc47 101 * @param[in] hz The baud rate in Hz
vipinranka 12:9a20164dcc47 102 */
vipinranka 12:9a20164dcc47 103 void spi_frequency(spi_t *obj, int hz);
vipinranka 12:9a20164dcc47 104
vipinranka 12:9a20164dcc47 105 /**@}*/
vipinranka 12:9a20164dcc47 106 /**
vipinranka 12:9a20164dcc47 107 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
vipinranka 12:9a20164dcc47 108 * @{
vipinranka 12:9a20164dcc47 109 */
vipinranka 12:9a20164dcc47 110
vipinranka 12:9a20164dcc47 111 /** Write a byte out in master mode and receive a value
vipinranka 12:9a20164dcc47 112 *
vipinranka 12:9a20164dcc47 113 * @param[in] obj The SPI peripheral to use for sending
vipinranka 12:9a20164dcc47 114 * @param[in] value The value to send
vipinranka 12:9a20164dcc47 115 * @return Returns the value received during send
vipinranka 12:9a20164dcc47 116 */
vipinranka 12:9a20164dcc47 117 int spi_master_write(spi_t *obj, int value);
vipinranka 12:9a20164dcc47 118
vipinranka 12:9a20164dcc47 119 /** Check if a value is available to read
vipinranka 12:9a20164dcc47 120 *
vipinranka 12:9a20164dcc47 121 * @param[in] obj The SPI peripheral to check
vipinranka 12:9a20164dcc47 122 * @return non-zero if a value is available
vipinranka 12:9a20164dcc47 123 */
vipinranka 12:9a20164dcc47 124 int spi_slave_receive(spi_t *obj);
vipinranka 12:9a20164dcc47 125
vipinranka 12:9a20164dcc47 126 /** Get a received value out of the SPI receive buffer in slave mode
vipinranka 12:9a20164dcc47 127 *
vipinranka 12:9a20164dcc47 128 * Blocks until a value is available
vipinranka 12:9a20164dcc47 129 * @param[in] obj The SPI peripheral to read
vipinranka 12:9a20164dcc47 130 * @return The value received
vipinranka 12:9a20164dcc47 131 */
vipinranka 12:9a20164dcc47 132 int spi_slave_read(spi_t *obj);
vipinranka 12:9a20164dcc47 133
vipinranka 12:9a20164dcc47 134 /** Write a value to the SPI peripheral in slave mode
vipinranka 12:9a20164dcc47 135 *
vipinranka 12:9a20164dcc47 136 * Blocks until the SPI peripheral can be written to
vipinranka 12:9a20164dcc47 137 * @param[in] obj The SPI peripheral to write
vipinranka 12:9a20164dcc47 138 * @param[in] value The value to write
vipinranka 12:9a20164dcc47 139 */
vipinranka 12:9a20164dcc47 140 void spi_slave_write(spi_t *obj, int value);
vipinranka 12:9a20164dcc47 141
vipinranka 12:9a20164dcc47 142 /** Checks if the specified SPI peripheral is in use
vipinranka 12:9a20164dcc47 143 *
vipinranka 12:9a20164dcc47 144 * @param[in] obj The SPI peripheral to check
vipinranka 12:9a20164dcc47 145 * @return non-zero if the peripheral is currently transmitting
vipinranka 12:9a20164dcc47 146 */
vipinranka 12:9a20164dcc47 147 int spi_busy(spi_t *obj);
vipinranka 12:9a20164dcc47 148
vipinranka 12:9a20164dcc47 149 /** Get the module number
vipinranka 12:9a20164dcc47 150 *
vipinranka 12:9a20164dcc47 151 * @param[in] obj The SPI peripheral to check
vipinranka 12:9a20164dcc47 152 * @return The module number
vipinranka 12:9a20164dcc47 153 */
vipinranka 12:9a20164dcc47 154 uint8_t spi_get_module(spi_t *obj);
vipinranka 12:9a20164dcc47 155
vipinranka 12:9a20164dcc47 156 /**@}*/
vipinranka 12:9a20164dcc47 157
vipinranka 12:9a20164dcc47 158 #if DEVICE_SPI_ASYNCH
vipinranka 12:9a20164dcc47 159 /**
vipinranka 12:9a20164dcc47 160 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
vipinranka 12:9a20164dcc47 161 * @{
vipinranka 12:9a20164dcc47 162 */
vipinranka 12:9a20164dcc47 163
vipinranka 12:9a20164dcc47 164 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
vipinranka 12:9a20164dcc47 165 *
vipinranka 12:9a20164dcc47 166 * @param[in] obj The SPI object that holds the transfer information
vipinranka 12:9a20164dcc47 167 * @param[in] tx The transmit buffer
vipinranka 12:9a20164dcc47 168 * @param[in] tx_length The number of bytes to transmit
vipinranka 12:9a20164dcc47 169 * @param[in] rx The receive buffer
vipinranka 12:9a20164dcc47 170 * @param[in] rx_length The number of bytes to receive
vipinranka 12:9a20164dcc47 171 * @param[in] bit_width The bit width of buffer words
vipinranka 12:9a20164dcc47 172 * @param[in] event The logical OR of events to be registered
vipinranka 12:9a20164dcc47 173 * @param[in] handler SPI interrupt handler
vipinranka 12:9a20164dcc47 174 * @param[in] hint A suggestion for how to use DMA with this transfer
vipinranka 12:9a20164dcc47 175 */
vipinranka 12:9a20164dcc47 176 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
vipinranka 12:9a20164dcc47 177
vipinranka 12:9a20164dcc47 178 /** The asynchronous IRQ handler
vipinranka 12:9a20164dcc47 179 *
vipinranka 12:9a20164dcc47 180 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
vipinranka 12:9a20164dcc47 181 * conditions, such as buffer overflows or transfer complete.
vipinranka 12:9a20164dcc47 182 * @param[in] obj The SPI object that holds the transfer information
vipinranka 12:9a20164dcc47 183 * @return Event flags if a transfer termination condition was met; otherwise 0.
vipinranka 12:9a20164dcc47 184 */
vipinranka 12:9a20164dcc47 185 uint32_t spi_irq_handler_asynch(spi_t *obj);
vipinranka 12:9a20164dcc47 186
vipinranka 12:9a20164dcc47 187 /** Attempts to determine if the SPI peripheral is already in use
vipinranka 12:9a20164dcc47 188 *
vipinranka 12:9a20164dcc47 189 * If a temporary DMA channel has been allocated, peripheral is in use.
vipinranka 12:9a20164dcc47 190 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
vipinranka 12:9a20164dcc47 191 * channel were allocated.
vipinranka 12:9a20164dcc47 192 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
vipinranka 12:9a20164dcc47 193 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
vipinranka 12:9a20164dcc47 194 * there are any bytes in the FIFOs.
vipinranka 12:9a20164dcc47 195 * @param[in] obj The SPI object to check for activity
vipinranka 12:9a20164dcc47 196 * @return Non-zero if the SPI port is active or zero if it is not.
vipinranka 12:9a20164dcc47 197 */
vipinranka 12:9a20164dcc47 198 uint8_t spi_active(spi_t *obj);
vipinranka 12:9a20164dcc47 199
vipinranka 12:9a20164dcc47 200 /** Abort an SPI transfer
vipinranka 12:9a20164dcc47 201 *
vipinranka 12:9a20164dcc47 202 * @param obj The SPI peripheral to stop
vipinranka 12:9a20164dcc47 203 */
vipinranka 12:9a20164dcc47 204 void spi_abort_asynch(spi_t *obj);
vipinranka 12:9a20164dcc47 205
vipinranka 12:9a20164dcc47 206
vipinranka 12:9a20164dcc47 207 #endif
vipinranka 12:9a20164dcc47 208
vipinranka 12:9a20164dcc47 209 /**@}*/
vipinranka 12:9a20164dcc47 210
vipinranka 12:9a20164dcc47 211 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 212 }
vipinranka 12:9a20164dcc47 213 #endif // __cplusplus
vipinranka 12:9a20164dcc47 214
vipinranka 12:9a20164dcc47 215 #endif // SPI_DEVICE
vipinranka 12:9a20164dcc47 216
vipinranka 12:9a20164dcc47 217 #endif // MBED_SPI_API_H
vipinranka 12:9a20164dcc47 218
vipinranka 12:9a20164dcc47 219 /** @}*/