Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/drivers/SPI.h@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /* mbed Microcontroller Library
vipinranka 12:9a20164dcc47 2 * Copyright (c) 2006-2015 ARM Limited
vipinranka 12:9a20164dcc47 3 *
vipinranka 12:9a20164dcc47 4 * Licensed under the Apache License, Version 2.0 (the "License");
vipinranka 12:9a20164dcc47 5 * you may not use this file except in compliance with the License.
vipinranka 12:9a20164dcc47 6 * You may obtain a copy of the License at
vipinranka 12:9a20164dcc47 7 *
vipinranka 12:9a20164dcc47 8 * http://www.apache.org/licenses/LICENSE-2.0
vipinranka 12:9a20164dcc47 9 *
vipinranka 12:9a20164dcc47 10 * Unless required by applicable law or agreed to in writing, software
vipinranka 12:9a20164dcc47 11 * distributed under the License is distributed on an "AS IS" BASIS,
vipinranka 12:9a20164dcc47 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
vipinranka 12:9a20164dcc47 13 * See the License for the specific language governing permissions and
vipinranka 12:9a20164dcc47 14 * limitations under the License.
vipinranka 12:9a20164dcc47 15 */
vipinranka 12:9a20164dcc47 16 #ifndef MBED_SPI_H
vipinranka 12:9a20164dcc47 17 #define MBED_SPI_H
vipinranka 12:9a20164dcc47 18
vipinranka 12:9a20164dcc47 19 #include "platform/platform.h"
vipinranka 12:9a20164dcc47 20
vipinranka 12:9a20164dcc47 21 #if DEVICE_SPI
vipinranka 12:9a20164dcc47 22
vipinranka 12:9a20164dcc47 23 #include "platform/PlatformMutex.h"
vipinranka 12:9a20164dcc47 24 #include "hal/spi_api.h"
vipinranka 12:9a20164dcc47 25 #include "platform/SingletonPtr.h"
vipinranka 12:9a20164dcc47 26
vipinranka 12:9a20164dcc47 27 #if DEVICE_SPI_ASYNCH
vipinranka 12:9a20164dcc47 28 #include "platform/CThunk.h"
vipinranka 12:9a20164dcc47 29 #include "hal/dma_api.h"
vipinranka 12:9a20164dcc47 30 #include "platform/CircularBuffer.h"
vipinranka 12:9a20164dcc47 31 #include "platform/FunctionPointer.h"
vipinranka 12:9a20164dcc47 32 #include "platform/Transaction.h"
vipinranka 12:9a20164dcc47 33 #endif
vipinranka 12:9a20164dcc47 34
vipinranka 12:9a20164dcc47 35 namespace mbed {
vipinranka 12:9a20164dcc47 36 /** \addtogroup drivers */
vipinranka 12:9a20164dcc47 37 /** @{*/
vipinranka 12:9a20164dcc47 38
vipinranka 12:9a20164dcc47 39 /** A SPI Master, used for communicating with SPI slave devices
vipinranka 12:9a20164dcc47 40 *
vipinranka 12:9a20164dcc47 41 * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
vipinranka 12:9a20164dcc47 42 *
vipinranka 12:9a20164dcc47 43 * Most SPI devices will also require Chip Select and Reset signals. These
vipinranka 12:9a20164dcc47 44 * can be controlled using <DigitalOut> pins
vipinranka 12:9a20164dcc47 45 *
vipinranka 12:9a20164dcc47 46 * @Note Synchronization level: Thread safe
vipinranka 12:9a20164dcc47 47 *
vipinranka 12:9a20164dcc47 48 * Example:
vipinranka 12:9a20164dcc47 49 * @code
vipinranka 12:9a20164dcc47 50 * // Send a byte to a SPI slave, and record the response
vipinranka 12:9a20164dcc47 51 *
vipinranka 12:9a20164dcc47 52 * #include "mbed.h"
vipinranka 12:9a20164dcc47 53 *
vipinranka 12:9a20164dcc47 54 * // hardware ssel (where applicable)
vipinranka 12:9a20164dcc47 55 * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
vipinranka 12:9a20164dcc47 56 *
vipinranka 12:9a20164dcc47 57 * // software ssel
vipinranka 12:9a20164dcc47 58 * SPI device(p5, p6, p7); // mosi, miso, sclk
vipinranka 12:9a20164dcc47 59 * DigitalOut cs(p8); // ssel
vipinranka 12:9a20164dcc47 60 *
vipinranka 12:9a20164dcc47 61 * int main() {
vipinranka 12:9a20164dcc47 62 * // hardware ssel (where applicable)
vipinranka 12:9a20164dcc47 63 * //int response = device.write(0xFF);
vipinranka 12:9a20164dcc47 64 *
vipinranka 12:9a20164dcc47 65 * device.lock();
vipinranka 12:9a20164dcc47 66 * // software ssel
vipinranka 12:9a20164dcc47 67 * cs = 0;
vipinranka 12:9a20164dcc47 68 * int response = device.write(0xFF);
vipinranka 12:9a20164dcc47 69 * cs = 1;
vipinranka 12:9a20164dcc47 70 * device.unlock();
vipinranka 12:9a20164dcc47 71 *
vipinranka 12:9a20164dcc47 72 * }
vipinranka 12:9a20164dcc47 73 * @endcode
vipinranka 12:9a20164dcc47 74 */
vipinranka 12:9a20164dcc47 75 class SPI {
vipinranka 12:9a20164dcc47 76
vipinranka 12:9a20164dcc47 77 public:
vipinranka 12:9a20164dcc47 78
vipinranka 12:9a20164dcc47 79 /** Create a SPI master connected to the specified pins
vipinranka 12:9a20164dcc47 80 *
vipinranka 12:9a20164dcc47 81 * mosi or miso can be specfied as NC if not used
vipinranka 12:9a20164dcc47 82 *
vipinranka 12:9a20164dcc47 83 * @param mosi SPI Master Out, Slave In pin
vipinranka 12:9a20164dcc47 84 * @param miso SPI Master In, Slave Out pin
vipinranka 12:9a20164dcc47 85 * @param sclk SPI Clock pin
vipinranka 12:9a20164dcc47 86 * @param ssel SPI chip select pin
vipinranka 12:9a20164dcc47 87 */
vipinranka 12:9a20164dcc47 88 SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
vipinranka 12:9a20164dcc47 89
vipinranka 12:9a20164dcc47 90 /** Configure the data transmission format
vipinranka 12:9a20164dcc47 91 *
vipinranka 12:9a20164dcc47 92 * @param bits Number of bits per SPI frame (4 - 16)
vipinranka 12:9a20164dcc47 93 * @param mode Clock polarity and phase mode (0 - 3)
vipinranka 12:9a20164dcc47 94 *
vipinranka 12:9a20164dcc47 95 * @code
vipinranka 12:9a20164dcc47 96 * mode | POL PHA
vipinranka 12:9a20164dcc47 97 * -----+--------
vipinranka 12:9a20164dcc47 98 * 0 | 0 0
vipinranka 12:9a20164dcc47 99 * 1 | 0 1
vipinranka 12:9a20164dcc47 100 * 2 | 1 0
vipinranka 12:9a20164dcc47 101 * 3 | 1 1
vipinranka 12:9a20164dcc47 102 * @endcode
vipinranka 12:9a20164dcc47 103 */
vipinranka 12:9a20164dcc47 104 void format(int bits, int mode = 0);
vipinranka 12:9a20164dcc47 105
vipinranka 12:9a20164dcc47 106 /** Set the spi bus clock frequency
vipinranka 12:9a20164dcc47 107 *
vipinranka 12:9a20164dcc47 108 * @param hz SCLK frequency in hz (default = 1MHz)
vipinranka 12:9a20164dcc47 109 */
vipinranka 12:9a20164dcc47 110 void frequency(int hz = 1000000);
vipinranka 12:9a20164dcc47 111
vipinranka 12:9a20164dcc47 112 /** Write to the SPI Slave and return the response
vipinranka 12:9a20164dcc47 113 *
vipinranka 12:9a20164dcc47 114 * @param value Data to be sent to the SPI slave
vipinranka 12:9a20164dcc47 115 *
vipinranka 12:9a20164dcc47 116 * @returns
vipinranka 12:9a20164dcc47 117 * Response from the SPI slave
vipinranka 12:9a20164dcc47 118 */
vipinranka 12:9a20164dcc47 119 virtual int write(int value);
vipinranka 12:9a20164dcc47 120
vipinranka 12:9a20164dcc47 121 /** Acquire exclusive access to this SPI bus
vipinranka 12:9a20164dcc47 122 */
vipinranka 12:9a20164dcc47 123 virtual void lock(void);
vipinranka 12:9a20164dcc47 124
vipinranka 12:9a20164dcc47 125 /** Release exclusive access to this SPI bus
vipinranka 12:9a20164dcc47 126 */
vipinranka 12:9a20164dcc47 127 virtual void unlock(void);
vipinranka 12:9a20164dcc47 128
vipinranka 12:9a20164dcc47 129 #if DEVICE_SPI_ASYNCH
vipinranka 12:9a20164dcc47 130
vipinranka 12:9a20164dcc47 131 /** Start non-blocking SPI transfer using 8bit buffers.
vipinranka 12:9a20164dcc47 132 *
vipinranka 12:9a20164dcc47 133 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
vipinranka 12:9a20164dcc47 134 * the default SPI value is sent
vipinranka 12:9a20164dcc47 135 * @param tx_length The length of TX buffer in bytes
vipinranka 12:9a20164dcc47 136 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
vipinranka 12:9a20164dcc47 137 * received data are ignored
vipinranka 12:9a20164dcc47 138 * @param rx_length The length of RX buffer in bytes
vipinranka 12:9a20164dcc47 139 * @param callback The event callback function
vipinranka 12:9a20164dcc47 140 * @param event The logical OR of events to modify. Look at spi hal header file for SPI events.
vipinranka 12:9a20164dcc47 141 * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
vipinranka 12:9a20164dcc47 142 */
vipinranka 12:9a20164dcc47 143 template<typename Type>
vipinranka 12:9a20164dcc47 144 int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
vipinranka 12:9a20164dcc47 145 if (spi_active(&_spi)) {
vipinranka 12:9a20164dcc47 146 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
vipinranka 12:9a20164dcc47 147 }
vipinranka 12:9a20164dcc47 148 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
vipinranka 12:9a20164dcc47 149 return 0;
vipinranka 12:9a20164dcc47 150 }
vipinranka 12:9a20164dcc47 151
vipinranka 12:9a20164dcc47 152 /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
vipinranka 12:9a20164dcc47 153 */
vipinranka 12:9a20164dcc47 154 void abort_transfer();
vipinranka 12:9a20164dcc47 155
vipinranka 12:9a20164dcc47 156 /** Clear the transaction buffer
vipinranka 12:9a20164dcc47 157 */
vipinranka 12:9a20164dcc47 158 void clear_transfer_buffer();
vipinranka 12:9a20164dcc47 159
vipinranka 12:9a20164dcc47 160 /** Clear the transaction buffer and abort on-going transfer.
vipinranka 12:9a20164dcc47 161 */
vipinranka 12:9a20164dcc47 162 void abort_all_transfers();
vipinranka 12:9a20164dcc47 163
vipinranka 12:9a20164dcc47 164 /** Configure DMA usage suggestion for non-blocking transfers
vipinranka 12:9a20164dcc47 165 *
vipinranka 12:9a20164dcc47 166 * @param usage The usage DMA hint for peripheral
vipinranka 12:9a20164dcc47 167 * @return Zero if the usage was set, -1 if a transaction is on-going
vipinranka 12:9a20164dcc47 168 */
vipinranka 12:9a20164dcc47 169 int set_dma_usage(DMAUsage usage);
vipinranka 12:9a20164dcc47 170
vipinranka 12:9a20164dcc47 171 protected:
vipinranka 12:9a20164dcc47 172 /** SPI IRQ handler
vipinranka 12:9a20164dcc47 173 *
vipinranka 12:9a20164dcc47 174 */
vipinranka 12:9a20164dcc47 175 void irq_handler_asynch(void);
vipinranka 12:9a20164dcc47 176
vipinranka 12:9a20164dcc47 177 /** Common transfer method
vipinranka 12:9a20164dcc47 178 *
vipinranka 12:9a20164dcc47 179 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
vipinranka 12:9a20164dcc47 180 * the default SPI value is sent
vipinranka 12:9a20164dcc47 181 * @param tx_length The length of TX buffer in bytes
vipinranka 12:9a20164dcc47 182 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
vipinranka 12:9a20164dcc47 183 * received data are ignored
vipinranka 12:9a20164dcc47 184 * @param rx_length The length of RX buffer in bytes
vipinranka 12:9a20164dcc47 185 * @param bit_width The buffers element width
vipinranka 12:9a20164dcc47 186 * @param callback The event callback function
vipinranka 12:9a20164dcc47 187 * @param event The logical OR of events to modify
vipinranka 12:9a20164dcc47 188 * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
vipinranka 12:9a20164dcc47 189 */
vipinranka 12:9a20164dcc47 190 int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
vipinranka 12:9a20164dcc47 191
vipinranka 12:9a20164dcc47 192 /**
vipinranka 12:9a20164dcc47 193 *
vipinranka 12:9a20164dcc47 194 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
vipinranka 12:9a20164dcc47 195 * the default SPI value is sent
vipinranka 12:9a20164dcc47 196 * @param tx_length The length of TX buffer in bytes
vipinranka 12:9a20164dcc47 197 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
vipinranka 12:9a20164dcc47 198 * received data are ignored
vipinranka 12:9a20164dcc47 199 * @param rx_length The length of RX buffer in bytes
vipinranka 12:9a20164dcc47 200 * @param bit_width The buffers element width
vipinranka 12:9a20164dcc47 201 * @param callback The event callback function
vipinranka 12:9a20164dcc47 202 * @param event The logical OR of events to modify
vipinranka 12:9a20164dcc47 203 * @return Zero if a transfer was added to the queue, or -1 if the queue is full
vipinranka 12:9a20164dcc47 204 */
vipinranka 12:9a20164dcc47 205 int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
vipinranka 12:9a20164dcc47 206
vipinranka 12:9a20164dcc47 207 /** Configures a callback, spi peripheral and initiate a new transfer
vipinranka 12:9a20164dcc47 208 *
vipinranka 12:9a20164dcc47 209 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
vipinranka 12:9a20164dcc47 210 * the default SPI value is sent
vipinranka 12:9a20164dcc47 211 * @param tx_length The length of TX buffer in bytes
vipinranka 12:9a20164dcc47 212 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
vipinranka 12:9a20164dcc47 213 * received data are ignored
vipinranka 12:9a20164dcc47 214 * @param rx_length The length of RX buffer in bytes
vipinranka 12:9a20164dcc47 215 * @param bit_width The buffers element width
vipinranka 12:9a20164dcc47 216 * @param callback The event callback function
vipinranka 12:9a20164dcc47 217 * @param event The logical OR of events to modify
vipinranka 12:9a20164dcc47 218 */
vipinranka 12:9a20164dcc47 219 void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
vipinranka 12:9a20164dcc47 220
vipinranka 12:9a20164dcc47 221 #if TRANSACTION_QUEUE_SIZE_SPI
vipinranka 12:9a20164dcc47 222
vipinranka 12:9a20164dcc47 223 /** Start a new transaction
vipinranka 12:9a20164dcc47 224 *
vipinranka 12:9a20164dcc47 225 * @param data Transaction data
vipinranka 12:9a20164dcc47 226 */
vipinranka 12:9a20164dcc47 227 void start_transaction(transaction_t *data);
vipinranka 12:9a20164dcc47 228
vipinranka 12:9a20164dcc47 229 /** Dequeue a transaction
vipinranka 12:9a20164dcc47 230 *
vipinranka 12:9a20164dcc47 231 */
vipinranka 12:9a20164dcc47 232 void dequeue_transaction();
vipinranka 12:9a20164dcc47 233 static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
vipinranka 12:9a20164dcc47 234 #endif
vipinranka 12:9a20164dcc47 235
vipinranka 12:9a20164dcc47 236 #endif
vipinranka 12:9a20164dcc47 237
vipinranka 12:9a20164dcc47 238 public:
vipinranka 12:9a20164dcc47 239 virtual ~SPI() {
vipinranka 12:9a20164dcc47 240 }
vipinranka 12:9a20164dcc47 241
vipinranka 12:9a20164dcc47 242 protected:
vipinranka 12:9a20164dcc47 243 spi_t _spi;
vipinranka 12:9a20164dcc47 244
vipinranka 12:9a20164dcc47 245 #if DEVICE_SPI_ASYNCH
vipinranka 12:9a20164dcc47 246 CThunk<SPI> _irq;
vipinranka 12:9a20164dcc47 247 event_callback_t _callback;
vipinranka 12:9a20164dcc47 248 DMAUsage _usage;
vipinranka 12:9a20164dcc47 249 #endif
vipinranka 12:9a20164dcc47 250
vipinranka 12:9a20164dcc47 251 void aquire(void);
vipinranka 12:9a20164dcc47 252 static SPI *_owner;
vipinranka 12:9a20164dcc47 253 static SingletonPtr<PlatformMutex> _mutex;
vipinranka 12:9a20164dcc47 254 int _bits;
vipinranka 12:9a20164dcc47 255 int _mode;
vipinranka 12:9a20164dcc47 256 int _hz;
vipinranka 12:9a20164dcc47 257 };
vipinranka 12:9a20164dcc47 258
vipinranka 12:9a20164dcc47 259 } // namespace mbed
vipinranka 12:9a20164dcc47 260
vipinranka 12:9a20164dcc47 261 #endif
vipinranka 12:9a20164dcc47 262
vipinranka 12:9a20164dcc47 263 #endif
vipinranka 12:9a20164dcc47 264
vipinranka 12:9a20164dcc47 265 /** @}*/