Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/cmsis/core_sc300.h@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /**************************************************************************//**
vipinranka 12:9a20164dcc47 2 * @file core_sc300.h
vipinranka 12:9a20164dcc47 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
vipinranka 12:9a20164dcc47 4 * @version V4.10
vipinranka 12:9a20164dcc47 5 * @date 18. March 2015
vipinranka 12:9a20164dcc47 6 *
vipinranka 12:9a20164dcc47 7 * @note
vipinranka 12:9a20164dcc47 8 *
vipinranka 12:9a20164dcc47 9 ******************************************************************************/
vipinranka 12:9a20164dcc47 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
vipinranka 12:9a20164dcc47 11
vipinranka 12:9a20164dcc47 12 All rights reserved.
vipinranka 12:9a20164dcc47 13 Redistribution and use in source and binary forms, with or without
vipinranka 12:9a20164dcc47 14 modification, are permitted provided that the following conditions are met:
vipinranka 12:9a20164dcc47 15 - Redistributions of source code must retain the above copyright
vipinranka 12:9a20164dcc47 16 notice, this list of conditions and the following disclaimer.
vipinranka 12:9a20164dcc47 17 - Redistributions in binary form must reproduce the above copyright
vipinranka 12:9a20164dcc47 18 notice, this list of conditions and the following disclaimer in the
vipinranka 12:9a20164dcc47 19 documentation and/or other materials provided with the distribution.
vipinranka 12:9a20164dcc47 20 - Neither the name of ARM nor the names of its contributors may be used
vipinranka 12:9a20164dcc47 21 to endorse or promote products derived from this software without
vipinranka 12:9a20164dcc47 22 specific prior written permission.
vipinranka 12:9a20164dcc47 23 *
vipinranka 12:9a20164dcc47 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vipinranka 12:9a20164dcc47 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vipinranka 12:9a20164dcc47 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vipinranka 12:9a20164dcc47 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vipinranka 12:9a20164dcc47 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vipinranka 12:9a20164dcc47 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vipinranka 12:9a20164dcc47 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vipinranka 12:9a20164dcc47 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vipinranka 12:9a20164dcc47 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vipinranka 12:9a20164dcc47 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vipinranka 12:9a20164dcc47 34 POSSIBILITY OF SUCH DAMAGE.
vipinranka 12:9a20164dcc47 35 ---------------------------------------------------------------------------*/
vipinranka 12:9a20164dcc47 36
vipinranka 12:9a20164dcc47 37
vipinranka 12:9a20164dcc47 38 #if defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 39 #pragma system_include /* treat file as system include file for MISRA check */
vipinranka 12:9a20164dcc47 40 #endif
vipinranka 12:9a20164dcc47 41
vipinranka 12:9a20164dcc47 42 #ifndef __CORE_SC300_H_GENERIC
vipinranka 12:9a20164dcc47 43 #define __CORE_SC300_H_GENERIC
vipinranka 12:9a20164dcc47 44
vipinranka 12:9a20164dcc47 45 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 46 extern "C" {
vipinranka 12:9a20164dcc47 47 #endif
vipinranka 12:9a20164dcc47 48
vipinranka 12:9a20164dcc47 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
vipinranka 12:9a20164dcc47 50 CMSIS violates the following MISRA-C:2004 rules:
vipinranka 12:9a20164dcc47 51
vipinranka 12:9a20164dcc47 52 \li Required Rule 8.5, object/function definition in header file.<br>
vipinranka 12:9a20164dcc47 53 Function definitions in header files are used to allow 'inlining'.
vipinranka 12:9a20164dcc47 54
vipinranka 12:9a20164dcc47 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
vipinranka 12:9a20164dcc47 56 Unions are used for effective representation of core registers.
vipinranka 12:9a20164dcc47 57
vipinranka 12:9a20164dcc47 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
vipinranka 12:9a20164dcc47 59 Function-like macros are used to allow more efficient code.
vipinranka 12:9a20164dcc47 60 */
vipinranka 12:9a20164dcc47 61
vipinranka 12:9a20164dcc47 62
vipinranka 12:9a20164dcc47 63 /*******************************************************************************
vipinranka 12:9a20164dcc47 64 * CMSIS definitions
vipinranka 12:9a20164dcc47 65 ******************************************************************************/
vipinranka 12:9a20164dcc47 66 /** \ingroup SC3000
vipinranka 12:9a20164dcc47 67 @{
vipinranka 12:9a20164dcc47 68 */
vipinranka 12:9a20164dcc47 69
vipinranka 12:9a20164dcc47 70 /* CMSIS SC300 definitions */
vipinranka 12:9a20164dcc47 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
vipinranka 12:9a20164dcc47 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
vipinranka 12:9a20164dcc47 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
vipinranka 12:9a20164dcc47 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
vipinranka 12:9a20164dcc47 75
vipinranka 12:9a20164dcc47 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
vipinranka 12:9a20164dcc47 77
vipinranka 12:9a20164dcc47 78
vipinranka 12:9a20164dcc47 79 #if defined ( __CC_ARM )
vipinranka 12:9a20164dcc47 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
vipinranka 12:9a20164dcc47 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
vipinranka 12:9a20164dcc47 82 #define __STATIC_INLINE static __inline
vipinranka 12:9a20164dcc47 83
vipinranka 12:9a20164dcc47 84 #elif defined ( __GNUC__ )
vipinranka 12:9a20164dcc47 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
vipinranka 12:9a20164dcc47 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
vipinranka 12:9a20164dcc47 87 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 88
vipinranka 12:9a20164dcc47 89 #elif defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
vipinranka 12:9a20164dcc47 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
vipinranka 12:9a20164dcc47 92 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 93
vipinranka 12:9a20164dcc47 94 #elif defined ( __TMS470__ )
vipinranka 12:9a20164dcc47 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
vipinranka 12:9a20164dcc47 96 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 97
vipinranka 12:9a20164dcc47 98 #elif defined ( __TASKING__ )
vipinranka 12:9a20164dcc47 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
vipinranka 12:9a20164dcc47 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
vipinranka 12:9a20164dcc47 101 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 102
vipinranka 12:9a20164dcc47 103 #elif defined ( __CSMC__ )
vipinranka 12:9a20164dcc47 104 #define __packed
vipinranka 12:9a20164dcc47 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
vipinranka 12:9a20164dcc47 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
vipinranka 12:9a20164dcc47 107 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 108
vipinranka 12:9a20164dcc47 109 #endif
vipinranka 12:9a20164dcc47 110
vipinranka 12:9a20164dcc47 111 /** __FPU_USED indicates whether an FPU is used or not.
vipinranka 12:9a20164dcc47 112 This core does not support an FPU at all
vipinranka 12:9a20164dcc47 113 */
vipinranka 12:9a20164dcc47 114 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 115
vipinranka 12:9a20164dcc47 116 #if defined ( __CC_ARM )
vipinranka 12:9a20164dcc47 117 #if defined __TARGET_FPU_VFP
vipinranka 12:9a20164dcc47 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 119 #endif
vipinranka 12:9a20164dcc47 120
vipinranka 12:9a20164dcc47 121 #elif defined ( __GNUC__ )
vipinranka 12:9a20164dcc47 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
vipinranka 12:9a20164dcc47 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 124 #endif
vipinranka 12:9a20164dcc47 125
vipinranka 12:9a20164dcc47 126 #elif defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 127 #if defined __ARMVFP__
vipinranka 12:9a20164dcc47 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 129 #endif
vipinranka 12:9a20164dcc47 130
vipinranka 12:9a20164dcc47 131 #elif defined ( __TMS470__ )
vipinranka 12:9a20164dcc47 132 #if defined __TI__VFP_SUPPORT____
vipinranka 12:9a20164dcc47 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 134 #endif
vipinranka 12:9a20164dcc47 135
vipinranka 12:9a20164dcc47 136 #elif defined ( __TASKING__ )
vipinranka 12:9a20164dcc47 137 #if defined __FPU_VFP__
vipinranka 12:9a20164dcc47 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 139 #endif
vipinranka 12:9a20164dcc47 140
vipinranka 12:9a20164dcc47 141 #elif defined ( __CSMC__ ) /* Cosmic */
vipinranka 12:9a20164dcc47 142 #if ( __CSMC__ & 0x400) // FPU present for parser
vipinranka 12:9a20164dcc47 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 144 #endif
vipinranka 12:9a20164dcc47 145 #endif
vipinranka 12:9a20164dcc47 146
vipinranka 12:9a20164dcc47 147 #include <stdint.h> /* standard types definitions */
vipinranka 12:9a20164dcc47 148 #include <core_cmInstr.h> /* Core Instruction Access */
vipinranka 12:9a20164dcc47 149 #include <core_cmFunc.h> /* Core Function Access */
vipinranka 12:9a20164dcc47 150
vipinranka 12:9a20164dcc47 151 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 152 }
vipinranka 12:9a20164dcc47 153 #endif
vipinranka 12:9a20164dcc47 154
vipinranka 12:9a20164dcc47 155 #endif /* __CORE_SC300_H_GENERIC */
vipinranka 12:9a20164dcc47 156
vipinranka 12:9a20164dcc47 157 #ifndef __CMSIS_GENERIC
vipinranka 12:9a20164dcc47 158
vipinranka 12:9a20164dcc47 159 #ifndef __CORE_SC300_H_DEPENDANT
vipinranka 12:9a20164dcc47 160 #define __CORE_SC300_H_DEPENDANT
vipinranka 12:9a20164dcc47 161
vipinranka 12:9a20164dcc47 162 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 163 extern "C" {
vipinranka 12:9a20164dcc47 164 #endif
vipinranka 12:9a20164dcc47 165
vipinranka 12:9a20164dcc47 166 /* check device defines and use defaults */
vipinranka 12:9a20164dcc47 167 #if defined __CHECK_DEVICE_DEFINES
vipinranka 12:9a20164dcc47 168 #ifndef __SC300_REV
vipinranka 12:9a20164dcc47 169 #define __SC300_REV 0x0000
vipinranka 12:9a20164dcc47 170 #warning "__SC300_REV not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 171 #endif
vipinranka 12:9a20164dcc47 172
vipinranka 12:9a20164dcc47 173 #ifndef __MPU_PRESENT
vipinranka 12:9a20164dcc47 174 #define __MPU_PRESENT 0
vipinranka 12:9a20164dcc47 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 176 #endif
vipinranka 12:9a20164dcc47 177
vipinranka 12:9a20164dcc47 178 #ifndef __NVIC_PRIO_BITS
vipinranka 12:9a20164dcc47 179 #define __NVIC_PRIO_BITS 4
vipinranka 12:9a20164dcc47 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 181 #endif
vipinranka 12:9a20164dcc47 182
vipinranka 12:9a20164dcc47 183 #ifndef __Vendor_SysTickConfig
vipinranka 12:9a20164dcc47 184 #define __Vendor_SysTickConfig 0
vipinranka 12:9a20164dcc47 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 186 #endif
vipinranka 12:9a20164dcc47 187 #endif
vipinranka 12:9a20164dcc47 188
vipinranka 12:9a20164dcc47 189 /* IO definitions (access restrictions to peripheral registers) */
vipinranka 12:9a20164dcc47 190 /**
vipinranka 12:9a20164dcc47 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
vipinranka 12:9a20164dcc47 192
vipinranka 12:9a20164dcc47 193 <strong>IO Type Qualifiers</strong> are used
vipinranka 12:9a20164dcc47 194 \li to specify the access to peripheral variables.
vipinranka 12:9a20164dcc47 195 \li for automatic generation of peripheral register debug information.
vipinranka 12:9a20164dcc47 196 */
vipinranka 12:9a20164dcc47 197 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 198 #define __I volatile /*!< Defines 'read only' permissions */
vipinranka 12:9a20164dcc47 199 #else
vipinranka 12:9a20164dcc47 200 #define __I volatile const /*!< Defines 'read only' permissions */
vipinranka 12:9a20164dcc47 201 #endif
vipinranka 12:9a20164dcc47 202 #define __O volatile /*!< Defines 'write only' permissions */
vipinranka 12:9a20164dcc47 203 #define __IO volatile /*!< Defines 'read / write' permissions */
vipinranka 12:9a20164dcc47 204
vipinranka 12:9a20164dcc47 205 /*@} end of group SC300 */
vipinranka 12:9a20164dcc47 206
vipinranka 12:9a20164dcc47 207
vipinranka 12:9a20164dcc47 208
vipinranka 12:9a20164dcc47 209 /*******************************************************************************
vipinranka 12:9a20164dcc47 210 * Register Abstraction
vipinranka 12:9a20164dcc47 211 Core Register contain:
vipinranka 12:9a20164dcc47 212 - Core Register
vipinranka 12:9a20164dcc47 213 - Core NVIC Register
vipinranka 12:9a20164dcc47 214 - Core SCB Register
vipinranka 12:9a20164dcc47 215 - Core SysTick Register
vipinranka 12:9a20164dcc47 216 - Core Debug Register
vipinranka 12:9a20164dcc47 217 - Core MPU Register
vipinranka 12:9a20164dcc47 218 ******************************************************************************/
vipinranka 12:9a20164dcc47 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
vipinranka 12:9a20164dcc47 220 \brief Type definitions and defines for Cortex-M processor based devices.
vipinranka 12:9a20164dcc47 221 */
vipinranka 12:9a20164dcc47 222
vipinranka 12:9a20164dcc47 223 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 224 \defgroup CMSIS_CORE Status and Control Registers
vipinranka 12:9a20164dcc47 225 \brief Core Register type definitions.
vipinranka 12:9a20164dcc47 226 @{
vipinranka 12:9a20164dcc47 227 */
vipinranka 12:9a20164dcc47 228
vipinranka 12:9a20164dcc47 229 /** \brief Union type to access the Application Program Status Register (APSR).
vipinranka 12:9a20164dcc47 230 */
vipinranka 12:9a20164dcc47 231 typedef union
vipinranka 12:9a20164dcc47 232 {
vipinranka 12:9a20164dcc47 233 struct
vipinranka 12:9a20164dcc47 234 {
vipinranka 12:9a20164dcc47 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
vipinranka 12:9a20164dcc47 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
vipinranka 12:9a20164dcc47 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vipinranka 12:9a20164dcc47 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vipinranka 12:9a20164dcc47 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vipinranka 12:9a20164dcc47 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vipinranka 12:9a20164dcc47 241 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 242 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 243 } APSR_Type;
vipinranka 12:9a20164dcc47 244
vipinranka 12:9a20164dcc47 245 /* APSR Register Definitions */
vipinranka 12:9a20164dcc47 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
vipinranka 12:9a20164dcc47 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
vipinranka 12:9a20164dcc47 248
vipinranka 12:9a20164dcc47 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
vipinranka 12:9a20164dcc47 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
vipinranka 12:9a20164dcc47 251
vipinranka 12:9a20164dcc47 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
vipinranka 12:9a20164dcc47 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
vipinranka 12:9a20164dcc47 254
vipinranka 12:9a20164dcc47 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
vipinranka 12:9a20164dcc47 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
vipinranka 12:9a20164dcc47 257
vipinranka 12:9a20164dcc47 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
vipinranka 12:9a20164dcc47 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
vipinranka 12:9a20164dcc47 260
vipinranka 12:9a20164dcc47 261
vipinranka 12:9a20164dcc47 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
vipinranka 12:9a20164dcc47 263 */
vipinranka 12:9a20164dcc47 264 typedef union
vipinranka 12:9a20164dcc47 265 {
vipinranka 12:9a20164dcc47 266 struct
vipinranka 12:9a20164dcc47 267 {
vipinranka 12:9a20164dcc47 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vipinranka 12:9a20164dcc47 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
vipinranka 12:9a20164dcc47 270 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 271 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 272 } IPSR_Type;
vipinranka 12:9a20164dcc47 273
vipinranka 12:9a20164dcc47 274 /* IPSR Register Definitions */
vipinranka 12:9a20164dcc47 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
vipinranka 12:9a20164dcc47 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
vipinranka 12:9a20164dcc47 277
vipinranka 12:9a20164dcc47 278
vipinranka 12:9a20164dcc47 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
vipinranka 12:9a20164dcc47 280 */
vipinranka 12:9a20164dcc47 281 typedef union
vipinranka 12:9a20164dcc47 282 {
vipinranka 12:9a20164dcc47 283 struct
vipinranka 12:9a20164dcc47 284 {
vipinranka 12:9a20164dcc47 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vipinranka 12:9a20164dcc47 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
vipinranka 12:9a20164dcc47 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
vipinranka 12:9a20164dcc47 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
vipinranka 12:9a20164dcc47 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
vipinranka 12:9a20164dcc47 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vipinranka 12:9a20164dcc47 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vipinranka 12:9a20164dcc47 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vipinranka 12:9a20164dcc47 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vipinranka 12:9a20164dcc47 294 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 295 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 296 } xPSR_Type;
vipinranka 12:9a20164dcc47 297
vipinranka 12:9a20164dcc47 298 /* xPSR Register Definitions */
vipinranka 12:9a20164dcc47 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
vipinranka 12:9a20164dcc47 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
vipinranka 12:9a20164dcc47 301
vipinranka 12:9a20164dcc47 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
vipinranka 12:9a20164dcc47 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
vipinranka 12:9a20164dcc47 304
vipinranka 12:9a20164dcc47 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
vipinranka 12:9a20164dcc47 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
vipinranka 12:9a20164dcc47 307
vipinranka 12:9a20164dcc47 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
vipinranka 12:9a20164dcc47 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
vipinranka 12:9a20164dcc47 310
vipinranka 12:9a20164dcc47 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
vipinranka 12:9a20164dcc47 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
vipinranka 12:9a20164dcc47 313
vipinranka 12:9a20164dcc47 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
vipinranka 12:9a20164dcc47 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
vipinranka 12:9a20164dcc47 316
vipinranka 12:9a20164dcc47 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
vipinranka 12:9a20164dcc47 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
vipinranka 12:9a20164dcc47 319
vipinranka 12:9a20164dcc47 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
vipinranka 12:9a20164dcc47 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
vipinranka 12:9a20164dcc47 322
vipinranka 12:9a20164dcc47 323
vipinranka 12:9a20164dcc47 324 /** \brief Union type to access the Control Registers (CONTROL).
vipinranka 12:9a20164dcc47 325 */
vipinranka 12:9a20164dcc47 326 typedef union
vipinranka 12:9a20164dcc47 327 {
vipinranka 12:9a20164dcc47 328 struct
vipinranka 12:9a20164dcc47 329 {
vipinranka 12:9a20164dcc47 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
vipinranka 12:9a20164dcc47 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
vipinranka 12:9a20164dcc47 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
vipinranka 12:9a20164dcc47 333 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 334 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 335 } CONTROL_Type;
vipinranka 12:9a20164dcc47 336
vipinranka 12:9a20164dcc47 337 /* CONTROL Register Definitions */
vipinranka 12:9a20164dcc47 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
vipinranka 12:9a20164dcc47 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
vipinranka 12:9a20164dcc47 340
vipinranka 12:9a20164dcc47 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
vipinranka 12:9a20164dcc47 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
vipinranka 12:9a20164dcc47 343
vipinranka 12:9a20164dcc47 344 /*@} end of group CMSIS_CORE */
vipinranka 12:9a20164dcc47 345
vipinranka 12:9a20164dcc47 346
vipinranka 12:9a20164dcc47 347 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
vipinranka 12:9a20164dcc47 349 \brief Type definitions for the NVIC Registers
vipinranka 12:9a20164dcc47 350 @{
vipinranka 12:9a20164dcc47 351 */
vipinranka 12:9a20164dcc47 352
vipinranka 12:9a20164dcc47 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
vipinranka 12:9a20164dcc47 354 */
vipinranka 12:9a20164dcc47 355 typedef struct
vipinranka 12:9a20164dcc47 356 {
vipinranka 12:9a20164dcc47 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
vipinranka 12:9a20164dcc47 358 uint32_t RESERVED0[24];
vipinranka 12:9a20164dcc47 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
vipinranka 12:9a20164dcc47 360 uint32_t RSERVED1[24];
vipinranka 12:9a20164dcc47 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
vipinranka 12:9a20164dcc47 362 uint32_t RESERVED2[24];
vipinranka 12:9a20164dcc47 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
vipinranka 12:9a20164dcc47 364 uint32_t RESERVED3[24];
vipinranka 12:9a20164dcc47 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
vipinranka 12:9a20164dcc47 366 uint32_t RESERVED4[56];
vipinranka 12:9a20164dcc47 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
vipinranka 12:9a20164dcc47 368 uint32_t RESERVED5[644];
vipinranka 12:9a20164dcc47 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
vipinranka 12:9a20164dcc47 370 } NVIC_Type;
vipinranka 12:9a20164dcc47 371
vipinranka 12:9a20164dcc47 372 /* Software Triggered Interrupt Register Definitions */
vipinranka 12:9a20164dcc47 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
vipinranka 12:9a20164dcc47 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
vipinranka 12:9a20164dcc47 375
vipinranka 12:9a20164dcc47 376 /*@} end of group CMSIS_NVIC */
vipinranka 12:9a20164dcc47 377
vipinranka 12:9a20164dcc47 378
vipinranka 12:9a20164dcc47 379 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 380 \defgroup CMSIS_SCB System Control Block (SCB)
vipinranka 12:9a20164dcc47 381 \brief Type definitions for the System Control Block Registers
vipinranka 12:9a20164dcc47 382 @{
vipinranka 12:9a20164dcc47 383 */
vipinranka 12:9a20164dcc47 384
vipinranka 12:9a20164dcc47 385 /** \brief Structure type to access the System Control Block (SCB).
vipinranka 12:9a20164dcc47 386 */
vipinranka 12:9a20164dcc47 387 typedef struct
vipinranka 12:9a20164dcc47 388 {
vipinranka 12:9a20164dcc47 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
vipinranka 12:9a20164dcc47 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
vipinranka 12:9a20164dcc47 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
vipinranka 12:9a20164dcc47 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
vipinranka 12:9a20164dcc47 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
vipinranka 12:9a20164dcc47 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
vipinranka 12:9a20164dcc47 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
vipinranka 12:9a20164dcc47 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
vipinranka 12:9a20164dcc47 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
vipinranka 12:9a20164dcc47 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
vipinranka 12:9a20164dcc47 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
vipinranka 12:9a20164dcc47 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
vipinranka 12:9a20164dcc47 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
vipinranka 12:9a20164dcc47 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
vipinranka 12:9a20164dcc47 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
vipinranka 12:9a20164dcc47 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
vipinranka 12:9a20164dcc47 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
vipinranka 12:9a20164dcc47 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
vipinranka 12:9a20164dcc47 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
vipinranka 12:9a20164dcc47 408 uint32_t RESERVED0[5];
vipinranka 12:9a20164dcc47 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
vipinranka 12:9a20164dcc47 410 uint32_t RESERVED1[129];
vipinranka 12:9a20164dcc47 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
vipinranka 12:9a20164dcc47 412 } SCB_Type;
vipinranka 12:9a20164dcc47 413
vipinranka 12:9a20164dcc47 414 /* SCB CPUID Register Definitions */
vipinranka 12:9a20164dcc47 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
vipinranka 12:9a20164dcc47 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
vipinranka 12:9a20164dcc47 417
vipinranka 12:9a20164dcc47 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
vipinranka 12:9a20164dcc47 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
vipinranka 12:9a20164dcc47 420
vipinranka 12:9a20164dcc47 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
vipinranka 12:9a20164dcc47 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
vipinranka 12:9a20164dcc47 423
vipinranka 12:9a20164dcc47 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
vipinranka 12:9a20164dcc47 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
vipinranka 12:9a20164dcc47 426
vipinranka 12:9a20164dcc47 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
vipinranka 12:9a20164dcc47 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
vipinranka 12:9a20164dcc47 429
vipinranka 12:9a20164dcc47 430 /* SCB Interrupt Control State Register Definitions */
vipinranka 12:9a20164dcc47 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
vipinranka 12:9a20164dcc47 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
vipinranka 12:9a20164dcc47 433
vipinranka 12:9a20164dcc47 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
vipinranka 12:9a20164dcc47 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
vipinranka 12:9a20164dcc47 436
vipinranka 12:9a20164dcc47 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
vipinranka 12:9a20164dcc47 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
vipinranka 12:9a20164dcc47 439
vipinranka 12:9a20164dcc47 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
vipinranka 12:9a20164dcc47 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
vipinranka 12:9a20164dcc47 442
vipinranka 12:9a20164dcc47 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
vipinranka 12:9a20164dcc47 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
vipinranka 12:9a20164dcc47 445
vipinranka 12:9a20164dcc47 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
vipinranka 12:9a20164dcc47 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
vipinranka 12:9a20164dcc47 448
vipinranka 12:9a20164dcc47 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
vipinranka 12:9a20164dcc47 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
vipinranka 12:9a20164dcc47 451
vipinranka 12:9a20164dcc47 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
vipinranka 12:9a20164dcc47 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
vipinranka 12:9a20164dcc47 454
vipinranka 12:9a20164dcc47 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
vipinranka 12:9a20164dcc47 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
vipinranka 12:9a20164dcc47 457
vipinranka 12:9a20164dcc47 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
vipinranka 12:9a20164dcc47 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
vipinranka 12:9a20164dcc47 460
vipinranka 12:9a20164dcc47 461 /* SCB Vector Table Offset Register Definitions */
vipinranka 12:9a20164dcc47 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
vipinranka 12:9a20164dcc47 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
vipinranka 12:9a20164dcc47 464
vipinranka 12:9a20164dcc47 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
vipinranka 12:9a20164dcc47 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
vipinranka 12:9a20164dcc47 467
vipinranka 12:9a20164dcc47 468 /* SCB Application Interrupt and Reset Control Register Definitions */
vipinranka 12:9a20164dcc47 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
vipinranka 12:9a20164dcc47 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
vipinranka 12:9a20164dcc47 471
vipinranka 12:9a20164dcc47 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
vipinranka 12:9a20164dcc47 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
vipinranka 12:9a20164dcc47 474
vipinranka 12:9a20164dcc47 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
vipinranka 12:9a20164dcc47 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
vipinranka 12:9a20164dcc47 477
vipinranka 12:9a20164dcc47 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
vipinranka 12:9a20164dcc47 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
vipinranka 12:9a20164dcc47 480
vipinranka 12:9a20164dcc47 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
vipinranka 12:9a20164dcc47 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
vipinranka 12:9a20164dcc47 483
vipinranka 12:9a20164dcc47 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
vipinranka 12:9a20164dcc47 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
vipinranka 12:9a20164dcc47 486
vipinranka 12:9a20164dcc47 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
vipinranka 12:9a20164dcc47 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
vipinranka 12:9a20164dcc47 489
vipinranka 12:9a20164dcc47 490 /* SCB System Control Register Definitions */
vipinranka 12:9a20164dcc47 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
vipinranka 12:9a20164dcc47 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
vipinranka 12:9a20164dcc47 493
vipinranka 12:9a20164dcc47 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
vipinranka 12:9a20164dcc47 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
vipinranka 12:9a20164dcc47 496
vipinranka 12:9a20164dcc47 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
vipinranka 12:9a20164dcc47 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
vipinranka 12:9a20164dcc47 499
vipinranka 12:9a20164dcc47 500 /* SCB Configuration Control Register Definitions */
vipinranka 12:9a20164dcc47 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
vipinranka 12:9a20164dcc47 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
vipinranka 12:9a20164dcc47 503
vipinranka 12:9a20164dcc47 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
vipinranka 12:9a20164dcc47 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
vipinranka 12:9a20164dcc47 506
vipinranka 12:9a20164dcc47 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
vipinranka 12:9a20164dcc47 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
vipinranka 12:9a20164dcc47 509
vipinranka 12:9a20164dcc47 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
vipinranka 12:9a20164dcc47 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
vipinranka 12:9a20164dcc47 512
vipinranka 12:9a20164dcc47 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
vipinranka 12:9a20164dcc47 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
vipinranka 12:9a20164dcc47 515
vipinranka 12:9a20164dcc47 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
vipinranka 12:9a20164dcc47 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
vipinranka 12:9a20164dcc47 518
vipinranka 12:9a20164dcc47 519 /* SCB System Handler Control and State Register Definitions */
vipinranka 12:9a20164dcc47 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
vipinranka 12:9a20164dcc47 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
vipinranka 12:9a20164dcc47 522
vipinranka 12:9a20164dcc47 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
vipinranka 12:9a20164dcc47 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
vipinranka 12:9a20164dcc47 525
vipinranka 12:9a20164dcc47 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
vipinranka 12:9a20164dcc47 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
vipinranka 12:9a20164dcc47 528
vipinranka 12:9a20164dcc47 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
vipinranka 12:9a20164dcc47 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
vipinranka 12:9a20164dcc47 531
vipinranka 12:9a20164dcc47 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
vipinranka 12:9a20164dcc47 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
vipinranka 12:9a20164dcc47 534
vipinranka 12:9a20164dcc47 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
vipinranka 12:9a20164dcc47 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
vipinranka 12:9a20164dcc47 537
vipinranka 12:9a20164dcc47 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
vipinranka 12:9a20164dcc47 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
vipinranka 12:9a20164dcc47 540
vipinranka 12:9a20164dcc47 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
vipinranka 12:9a20164dcc47 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
vipinranka 12:9a20164dcc47 543
vipinranka 12:9a20164dcc47 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
vipinranka 12:9a20164dcc47 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
vipinranka 12:9a20164dcc47 546
vipinranka 12:9a20164dcc47 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
vipinranka 12:9a20164dcc47 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
vipinranka 12:9a20164dcc47 549
vipinranka 12:9a20164dcc47 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
vipinranka 12:9a20164dcc47 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
vipinranka 12:9a20164dcc47 552
vipinranka 12:9a20164dcc47 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
vipinranka 12:9a20164dcc47 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
vipinranka 12:9a20164dcc47 555
vipinranka 12:9a20164dcc47 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
vipinranka 12:9a20164dcc47 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
vipinranka 12:9a20164dcc47 558
vipinranka 12:9a20164dcc47 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
vipinranka 12:9a20164dcc47 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
vipinranka 12:9a20164dcc47 561
vipinranka 12:9a20164dcc47 562 /* SCB Configurable Fault Status Registers Definitions */
vipinranka 12:9a20164dcc47 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
vipinranka 12:9a20164dcc47 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
vipinranka 12:9a20164dcc47 565
vipinranka 12:9a20164dcc47 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
vipinranka 12:9a20164dcc47 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
vipinranka 12:9a20164dcc47 568
vipinranka 12:9a20164dcc47 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
vipinranka 12:9a20164dcc47 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
vipinranka 12:9a20164dcc47 571
vipinranka 12:9a20164dcc47 572 /* SCB Hard Fault Status Registers Definitions */
vipinranka 12:9a20164dcc47 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
vipinranka 12:9a20164dcc47 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
vipinranka 12:9a20164dcc47 575
vipinranka 12:9a20164dcc47 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
vipinranka 12:9a20164dcc47 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
vipinranka 12:9a20164dcc47 578
vipinranka 12:9a20164dcc47 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
vipinranka 12:9a20164dcc47 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
vipinranka 12:9a20164dcc47 581
vipinranka 12:9a20164dcc47 582 /* SCB Debug Fault Status Register Definitions */
vipinranka 12:9a20164dcc47 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
vipinranka 12:9a20164dcc47 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
vipinranka 12:9a20164dcc47 585
vipinranka 12:9a20164dcc47 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
vipinranka 12:9a20164dcc47 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
vipinranka 12:9a20164dcc47 588
vipinranka 12:9a20164dcc47 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
vipinranka 12:9a20164dcc47 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
vipinranka 12:9a20164dcc47 591
vipinranka 12:9a20164dcc47 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
vipinranka 12:9a20164dcc47 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
vipinranka 12:9a20164dcc47 594
vipinranka 12:9a20164dcc47 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
vipinranka 12:9a20164dcc47 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
vipinranka 12:9a20164dcc47 597
vipinranka 12:9a20164dcc47 598 /*@} end of group CMSIS_SCB */
vipinranka 12:9a20164dcc47 599
vipinranka 12:9a20164dcc47 600
vipinranka 12:9a20164dcc47 601 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
vipinranka 12:9a20164dcc47 603 \brief Type definitions for the System Control and ID Register not in the SCB
vipinranka 12:9a20164dcc47 604 @{
vipinranka 12:9a20164dcc47 605 */
vipinranka 12:9a20164dcc47 606
vipinranka 12:9a20164dcc47 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
vipinranka 12:9a20164dcc47 608 */
vipinranka 12:9a20164dcc47 609 typedef struct
vipinranka 12:9a20164dcc47 610 {
vipinranka 12:9a20164dcc47 611 uint32_t RESERVED0[1];
vipinranka 12:9a20164dcc47 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
vipinranka 12:9a20164dcc47 613 uint32_t RESERVED1[1];
vipinranka 12:9a20164dcc47 614 } SCnSCB_Type;
vipinranka 12:9a20164dcc47 615
vipinranka 12:9a20164dcc47 616 /* Interrupt Controller Type Register Definitions */
vipinranka 12:9a20164dcc47 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
vipinranka 12:9a20164dcc47 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
vipinranka 12:9a20164dcc47 619
vipinranka 12:9a20164dcc47 620 /*@} end of group CMSIS_SCnotSCB */
vipinranka 12:9a20164dcc47 621
vipinranka 12:9a20164dcc47 622
vipinranka 12:9a20164dcc47 623 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
vipinranka 12:9a20164dcc47 625 \brief Type definitions for the System Timer Registers.
vipinranka 12:9a20164dcc47 626 @{
vipinranka 12:9a20164dcc47 627 */
vipinranka 12:9a20164dcc47 628
vipinranka 12:9a20164dcc47 629 /** \brief Structure type to access the System Timer (SysTick).
vipinranka 12:9a20164dcc47 630 */
vipinranka 12:9a20164dcc47 631 typedef struct
vipinranka 12:9a20164dcc47 632 {
vipinranka 12:9a20164dcc47 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
vipinranka 12:9a20164dcc47 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
vipinranka 12:9a20164dcc47 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
vipinranka 12:9a20164dcc47 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
vipinranka 12:9a20164dcc47 637 } SysTick_Type;
vipinranka 12:9a20164dcc47 638
vipinranka 12:9a20164dcc47 639 /* SysTick Control / Status Register Definitions */
vipinranka 12:9a20164dcc47 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
vipinranka 12:9a20164dcc47 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
vipinranka 12:9a20164dcc47 642
vipinranka 12:9a20164dcc47 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
vipinranka 12:9a20164dcc47 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
vipinranka 12:9a20164dcc47 645
vipinranka 12:9a20164dcc47 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
vipinranka 12:9a20164dcc47 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
vipinranka 12:9a20164dcc47 648
vipinranka 12:9a20164dcc47 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
vipinranka 12:9a20164dcc47 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
vipinranka 12:9a20164dcc47 651
vipinranka 12:9a20164dcc47 652 /* SysTick Reload Register Definitions */
vipinranka 12:9a20164dcc47 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
vipinranka 12:9a20164dcc47 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
vipinranka 12:9a20164dcc47 655
vipinranka 12:9a20164dcc47 656 /* SysTick Current Register Definitions */
vipinranka 12:9a20164dcc47 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
vipinranka 12:9a20164dcc47 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
vipinranka 12:9a20164dcc47 659
vipinranka 12:9a20164dcc47 660 /* SysTick Calibration Register Definitions */
vipinranka 12:9a20164dcc47 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
vipinranka 12:9a20164dcc47 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
vipinranka 12:9a20164dcc47 663
vipinranka 12:9a20164dcc47 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
vipinranka 12:9a20164dcc47 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
vipinranka 12:9a20164dcc47 666
vipinranka 12:9a20164dcc47 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
vipinranka 12:9a20164dcc47 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
vipinranka 12:9a20164dcc47 669
vipinranka 12:9a20164dcc47 670 /*@} end of group CMSIS_SysTick */
vipinranka 12:9a20164dcc47 671
vipinranka 12:9a20164dcc47 672
vipinranka 12:9a20164dcc47 673 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
vipinranka 12:9a20164dcc47 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
vipinranka 12:9a20164dcc47 676 @{
vipinranka 12:9a20164dcc47 677 */
vipinranka 12:9a20164dcc47 678
vipinranka 12:9a20164dcc47 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
vipinranka 12:9a20164dcc47 680 */
vipinranka 12:9a20164dcc47 681 typedef struct
vipinranka 12:9a20164dcc47 682 {
vipinranka 12:9a20164dcc47 683 __O union
vipinranka 12:9a20164dcc47 684 {
vipinranka 12:9a20164dcc47 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
vipinranka 12:9a20164dcc47 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
vipinranka 12:9a20164dcc47 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
vipinranka 12:9a20164dcc47 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
vipinranka 12:9a20164dcc47 689 uint32_t RESERVED0[864];
vipinranka 12:9a20164dcc47 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
vipinranka 12:9a20164dcc47 691 uint32_t RESERVED1[15];
vipinranka 12:9a20164dcc47 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
vipinranka 12:9a20164dcc47 693 uint32_t RESERVED2[15];
vipinranka 12:9a20164dcc47 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
vipinranka 12:9a20164dcc47 695 uint32_t RESERVED3[29];
vipinranka 12:9a20164dcc47 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
vipinranka 12:9a20164dcc47 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
vipinranka 12:9a20164dcc47 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
vipinranka 12:9a20164dcc47 699 uint32_t RESERVED4[43];
vipinranka 12:9a20164dcc47 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
vipinranka 12:9a20164dcc47 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
vipinranka 12:9a20164dcc47 702 uint32_t RESERVED5[6];
vipinranka 12:9a20164dcc47 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
vipinranka 12:9a20164dcc47 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
vipinranka 12:9a20164dcc47 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
vipinranka 12:9a20164dcc47 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
vipinranka 12:9a20164dcc47 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
vipinranka 12:9a20164dcc47 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
vipinranka 12:9a20164dcc47 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
vipinranka 12:9a20164dcc47 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
vipinranka 12:9a20164dcc47 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
vipinranka 12:9a20164dcc47 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
vipinranka 12:9a20164dcc47 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
vipinranka 12:9a20164dcc47 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
vipinranka 12:9a20164dcc47 715 } ITM_Type;
vipinranka 12:9a20164dcc47 716
vipinranka 12:9a20164dcc47 717 /* ITM Trace Privilege Register Definitions */
vipinranka 12:9a20164dcc47 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
vipinranka 12:9a20164dcc47 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
vipinranka 12:9a20164dcc47 720
vipinranka 12:9a20164dcc47 721 /* ITM Trace Control Register Definitions */
vipinranka 12:9a20164dcc47 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
vipinranka 12:9a20164dcc47 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
vipinranka 12:9a20164dcc47 724
vipinranka 12:9a20164dcc47 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
vipinranka 12:9a20164dcc47 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
vipinranka 12:9a20164dcc47 727
vipinranka 12:9a20164dcc47 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
vipinranka 12:9a20164dcc47 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
vipinranka 12:9a20164dcc47 730
vipinranka 12:9a20164dcc47 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
vipinranka 12:9a20164dcc47 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
vipinranka 12:9a20164dcc47 733
vipinranka 12:9a20164dcc47 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
vipinranka 12:9a20164dcc47 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
vipinranka 12:9a20164dcc47 736
vipinranka 12:9a20164dcc47 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
vipinranka 12:9a20164dcc47 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
vipinranka 12:9a20164dcc47 739
vipinranka 12:9a20164dcc47 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
vipinranka 12:9a20164dcc47 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
vipinranka 12:9a20164dcc47 742
vipinranka 12:9a20164dcc47 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
vipinranka 12:9a20164dcc47 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
vipinranka 12:9a20164dcc47 745
vipinranka 12:9a20164dcc47 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
vipinranka 12:9a20164dcc47 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
vipinranka 12:9a20164dcc47 748
vipinranka 12:9a20164dcc47 749 /* ITM Integration Write Register Definitions */
vipinranka 12:9a20164dcc47 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
vipinranka 12:9a20164dcc47 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
vipinranka 12:9a20164dcc47 752
vipinranka 12:9a20164dcc47 753 /* ITM Integration Read Register Definitions */
vipinranka 12:9a20164dcc47 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
vipinranka 12:9a20164dcc47 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
vipinranka 12:9a20164dcc47 756
vipinranka 12:9a20164dcc47 757 /* ITM Integration Mode Control Register Definitions */
vipinranka 12:9a20164dcc47 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
vipinranka 12:9a20164dcc47 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
vipinranka 12:9a20164dcc47 760
vipinranka 12:9a20164dcc47 761 /* ITM Lock Status Register Definitions */
vipinranka 12:9a20164dcc47 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
vipinranka 12:9a20164dcc47 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
vipinranka 12:9a20164dcc47 764
vipinranka 12:9a20164dcc47 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
vipinranka 12:9a20164dcc47 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
vipinranka 12:9a20164dcc47 767
vipinranka 12:9a20164dcc47 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
vipinranka 12:9a20164dcc47 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
vipinranka 12:9a20164dcc47 770
vipinranka 12:9a20164dcc47 771 /*@}*/ /* end of group CMSIS_ITM */
vipinranka 12:9a20164dcc47 772
vipinranka 12:9a20164dcc47 773
vipinranka 12:9a20164dcc47 774 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
vipinranka 12:9a20164dcc47 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
vipinranka 12:9a20164dcc47 777 @{
vipinranka 12:9a20164dcc47 778 */
vipinranka 12:9a20164dcc47 779
vipinranka 12:9a20164dcc47 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
vipinranka 12:9a20164dcc47 781 */
vipinranka 12:9a20164dcc47 782 typedef struct
vipinranka 12:9a20164dcc47 783 {
vipinranka 12:9a20164dcc47 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
vipinranka 12:9a20164dcc47 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
vipinranka 12:9a20164dcc47 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
vipinranka 12:9a20164dcc47 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
vipinranka 12:9a20164dcc47 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
vipinranka 12:9a20164dcc47 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
vipinranka 12:9a20164dcc47 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
vipinranka 12:9a20164dcc47 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
vipinranka 12:9a20164dcc47 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
vipinranka 12:9a20164dcc47 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
vipinranka 12:9a20164dcc47 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
vipinranka 12:9a20164dcc47 795 uint32_t RESERVED0[1];
vipinranka 12:9a20164dcc47 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
vipinranka 12:9a20164dcc47 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
vipinranka 12:9a20164dcc47 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
vipinranka 12:9a20164dcc47 799 uint32_t RESERVED1[1];
vipinranka 12:9a20164dcc47 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
vipinranka 12:9a20164dcc47 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
vipinranka 12:9a20164dcc47 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
vipinranka 12:9a20164dcc47 803 uint32_t RESERVED2[1];
vipinranka 12:9a20164dcc47 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
vipinranka 12:9a20164dcc47 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
vipinranka 12:9a20164dcc47 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
vipinranka 12:9a20164dcc47 807 } DWT_Type;
vipinranka 12:9a20164dcc47 808
vipinranka 12:9a20164dcc47 809 /* DWT Control Register Definitions */
vipinranka 12:9a20164dcc47 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
vipinranka 12:9a20164dcc47 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
vipinranka 12:9a20164dcc47 812
vipinranka 12:9a20164dcc47 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
vipinranka 12:9a20164dcc47 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
vipinranka 12:9a20164dcc47 815
vipinranka 12:9a20164dcc47 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
vipinranka 12:9a20164dcc47 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
vipinranka 12:9a20164dcc47 818
vipinranka 12:9a20164dcc47 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
vipinranka 12:9a20164dcc47 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
vipinranka 12:9a20164dcc47 821
vipinranka 12:9a20164dcc47 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
vipinranka 12:9a20164dcc47 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
vipinranka 12:9a20164dcc47 824
vipinranka 12:9a20164dcc47 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
vipinranka 12:9a20164dcc47 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
vipinranka 12:9a20164dcc47 827
vipinranka 12:9a20164dcc47 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
vipinranka 12:9a20164dcc47 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
vipinranka 12:9a20164dcc47 830
vipinranka 12:9a20164dcc47 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
vipinranka 12:9a20164dcc47 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
vipinranka 12:9a20164dcc47 833
vipinranka 12:9a20164dcc47 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
vipinranka 12:9a20164dcc47 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
vipinranka 12:9a20164dcc47 836
vipinranka 12:9a20164dcc47 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
vipinranka 12:9a20164dcc47 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
vipinranka 12:9a20164dcc47 839
vipinranka 12:9a20164dcc47 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
vipinranka 12:9a20164dcc47 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
vipinranka 12:9a20164dcc47 842
vipinranka 12:9a20164dcc47 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
vipinranka 12:9a20164dcc47 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
vipinranka 12:9a20164dcc47 845
vipinranka 12:9a20164dcc47 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
vipinranka 12:9a20164dcc47 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
vipinranka 12:9a20164dcc47 848
vipinranka 12:9a20164dcc47 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
vipinranka 12:9a20164dcc47 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
vipinranka 12:9a20164dcc47 851
vipinranka 12:9a20164dcc47 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
vipinranka 12:9a20164dcc47 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
vipinranka 12:9a20164dcc47 854
vipinranka 12:9a20164dcc47 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
vipinranka 12:9a20164dcc47 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
vipinranka 12:9a20164dcc47 857
vipinranka 12:9a20164dcc47 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
vipinranka 12:9a20164dcc47 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
vipinranka 12:9a20164dcc47 860
vipinranka 12:9a20164dcc47 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
vipinranka 12:9a20164dcc47 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
vipinranka 12:9a20164dcc47 863
vipinranka 12:9a20164dcc47 864 /* DWT CPI Count Register Definitions */
vipinranka 12:9a20164dcc47 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
vipinranka 12:9a20164dcc47 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
vipinranka 12:9a20164dcc47 867
vipinranka 12:9a20164dcc47 868 /* DWT Exception Overhead Count Register Definitions */
vipinranka 12:9a20164dcc47 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
vipinranka 12:9a20164dcc47 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
vipinranka 12:9a20164dcc47 871
vipinranka 12:9a20164dcc47 872 /* DWT Sleep Count Register Definitions */
vipinranka 12:9a20164dcc47 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
vipinranka 12:9a20164dcc47 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
vipinranka 12:9a20164dcc47 875
vipinranka 12:9a20164dcc47 876 /* DWT LSU Count Register Definitions */
vipinranka 12:9a20164dcc47 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
vipinranka 12:9a20164dcc47 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
vipinranka 12:9a20164dcc47 879
vipinranka 12:9a20164dcc47 880 /* DWT Folded-instruction Count Register Definitions */
vipinranka 12:9a20164dcc47 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
vipinranka 12:9a20164dcc47 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
vipinranka 12:9a20164dcc47 883
vipinranka 12:9a20164dcc47 884 /* DWT Comparator Mask Register Definitions */
vipinranka 12:9a20164dcc47 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
vipinranka 12:9a20164dcc47 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
vipinranka 12:9a20164dcc47 887
vipinranka 12:9a20164dcc47 888 /* DWT Comparator Function Register Definitions */
vipinranka 12:9a20164dcc47 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
vipinranka 12:9a20164dcc47 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
vipinranka 12:9a20164dcc47 891
vipinranka 12:9a20164dcc47 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
vipinranka 12:9a20164dcc47 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
vipinranka 12:9a20164dcc47 894
vipinranka 12:9a20164dcc47 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
vipinranka 12:9a20164dcc47 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
vipinranka 12:9a20164dcc47 897
vipinranka 12:9a20164dcc47 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
vipinranka 12:9a20164dcc47 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
vipinranka 12:9a20164dcc47 900
vipinranka 12:9a20164dcc47 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
vipinranka 12:9a20164dcc47 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
vipinranka 12:9a20164dcc47 903
vipinranka 12:9a20164dcc47 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
vipinranka 12:9a20164dcc47 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
vipinranka 12:9a20164dcc47 906
vipinranka 12:9a20164dcc47 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
vipinranka 12:9a20164dcc47 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
vipinranka 12:9a20164dcc47 909
vipinranka 12:9a20164dcc47 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
vipinranka 12:9a20164dcc47 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
vipinranka 12:9a20164dcc47 912
vipinranka 12:9a20164dcc47 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
vipinranka 12:9a20164dcc47 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
vipinranka 12:9a20164dcc47 915
vipinranka 12:9a20164dcc47 916 /*@}*/ /* end of group CMSIS_DWT */
vipinranka 12:9a20164dcc47 917
vipinranka 12:9a20164dcc47 918
vipinranka 12:9a20164dcc47 919 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
vipinranka 12:9a20164dcc47 921 \brief Type definitions for the Trace Port Interface (TPI)
vipinranka 12:9a20164dcc47 922 @{
vipinranka 12:9a20164dcc47 923 */
vipinranka 12:9a20164dcc47 924
vipinranka 12:9a20164dcc47 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
vipinranka 12:9a20164dcc47 926 */
vipinranka 12:9a20164dcc47 927 typedef struct
vipinranka 12:9a20164dcc47 928 {
vipinranka 12:9a20164dcc47 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
vipinranka 12:9a20164dcc47 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
vipinranka 12:9a20164dcc47 931 uint32_t RESERVED0[2];
vipinranka 12:9a20164dcc47 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
vipinranka 12:9a20164dcc47 933 uint32_t RESERVED1[55];
vipinranka 12:9a20164dcc47 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
vipinranka 12:9a20164dcc47 935 uint32_t RESERVED2[131];
vipinranka 12:9a20164dcc47 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
vipinranka 12:9a20164dcc47 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
vipinranka 12:9a20164dcc47 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
vipinranka 12:9a20164dcc47 939 uint32_t RESERVED3[759];
vipinranka 12:9a20164dcc47 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
vipinranka 12:9a20164dcc47 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
vipinranka 12:9a20164dcc47 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
vipinranka 12:9a20164dcc47 943 uint32_t RESERVED4[1];
vipinranka 12:9a20164dcc47 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
vipinranka 12:9a20164dcc47 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
vipinranka 12:9a20164dcc47 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
vipinranka 12:9a20164dcc47 947 uint32_t RESERVED5[39];
vipinranka 12:9a20164dcc47 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
vipinranka 12:9a20164dcc47 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
vipinranka 12:9a20164dcc47 950 uint32_t RESERVED7[8];
vipinranka 12:9a20164dcc47 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
vipinranka 12:9a20164dcc47 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
vipinranka 12:9a20164dcc47 953 } TPI_Type;
vipinranka 12:9a20164dcc47 954
vipinranka 12:9a20164dcc47 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
vipinranka 12:9a20164dcc47 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
vipinranka 12:9a20164dcc47 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
vipinranka 12:9a20164dcc47 958
vipinranka 12:9a20164dcc47 959 /* TPI Selected Pin Protocol Register Definitions */
vipinranka 12:9a20164dcc47 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
vipinranka 12:9a20164dcc47 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
vipinranka 12:9a20164dcc47 962
vipinranka 12:9a20164dcc47 963 /* TPI Formatter and Flush Status Register Definitions */
vipinranka 12:9a20164dcc47 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
vipinranka 12:9a20164dcc47 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
vipinranka 12:9a20164dcc47 966
vipinranka 12:9a20164dcc47 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
vipinranka 12:9a20164dcc47 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
vipinranka 12:9a20164dcc47 969
vipinranka 12:9a20164dcc47 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
vipinranka 12:9a20164dcc47 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
vipinranka 12:9a20164dcc47 972
vipinranka 12:9a20164dcc47 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
vipinranka 12:9a20164dcc47 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
vipinranka 12:9a20164dcc47 975
vipinranka 12:9a20164dcc47 976 /* TPI Formatter and Flush Control Register Definitions */
vipinranka 12:9a20164dcc47 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
vipinranka 12:9a20164dcc47 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
vipinranka 12:9a20164dcc47 979
vipinranka 12:9a20164dcc47 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
vipinranka 12:9a20164dcc47 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
vipinranka 12:9a20164dcc47 982
vipinranka 12:9a20164dcc47 983 /* TPI TRIGGER Register Definitions */
vipinranka 12:9a20164dcc47 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
vipinranka 12:9a20164dcc47 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
vipinranka 12:9a20164dcc47 986
vipinranka 12:9a20164dcc47 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
vipinranka 12:9a20164dcc47 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
vipinranka 12:9a20164dcc47 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
vipinranka 12:9a20164dcc47 990
vipinranka 12:9a20164dcc47 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
vipinranka 12:9a20164dcc47 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
vipinranka 12:9a20164dcc47 993
vipinranka 12:9a20164dcc47 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
vipinranka 12:9a20164dcc47 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
vipinranka 12:9a20164dcc47 996
vipinranka 12:9a20164dcc47 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
vipinranka 12:9a20164dcc47 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
vipinranka 12:9a20164dcc47 999
vipinranka 12:9a20164dcc47 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
vipinranka 12:9a20164dcc47 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
vipinranka 12:9a20164dcc47 1002
vipinranka 12:9a20164dcc47 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
vipinranka 12:9a20164dcc47 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
vipinranka 12:9a20164dcc47 1005
vipinranka 12:9a20164dcc47 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
vipinranka 12:9a20164dcc47 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
vipinranka 12:9a20164dcc47 1008
vipinranka 12:9a20164dcc47 1009 /* TPI ITATBCTR2 Register Definitions */
vipinranka 12:9a20164dcc47 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
vipinranka 12:9a20164dcc47 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
vipinranka 12:9a20164dcc47 1012
vipinranka 12:9a20164dcc47 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
vipinranka 12:9a20164dcc47 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
vipinranka 12:9a20164dcc47 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
vipinranka 12:9a20164dcc47 1016
vipinranka 12:9a20164dcc47 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
vipinranka 12:9a20164dcc47 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
vipinranka 12:9a20164dcc47 1019
vipinranka 12:9a20164dcc47 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
vipinranka 12:9a20164dcc47 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
vipinranka 12:9a20164dcc47 1022
vipinranka 12:9a20164dcc47 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
vipinranka 12:9a20164dcc47 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
vipinranka 12:9a20164dcc47 1025
vipinranka 12:9a20164dcc47 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
vipinranka 12:9a20164dcc47 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
vipinranka 12:9a20164dcc47 1028
vipinranka 12:9a20164dcc47 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
vipinranka 12:9a20164dcc47 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
vipinranka 12:9a20164dcc47 1031
vipinranka 12:9a20164dcc47 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
vipinranka 12:9a20164dcc47 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
vipinranka 12:9a20164dcc47 1034
vipinranka 12:9a20164dcc47 1035 /* TPI ITATBCTR0 Register Definitions */
vipinranka 12:9a20164dcc47 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
vipinranka 12:9a20164dcc47 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
vipinranka 12:9a20164dcc47 1038
vipinranka 12:9a20164dcc47 1039 /* TPI Integration Mode Control Register Definitions */
vipinranka 12:9a20164dcc47 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
vipinranka 12:9a20164dcc47 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
vipinranka 12:9a20164dcc47 1042
vipinranka 12:9a20164dcc47 1043 /* TPI DEVID Register Definitions */
vipinranka 12:9a20164dcc47 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
vipinranka 12:9a20164dcc47 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
vipinranka 12:9a20164dcc47 1046
vipinranka 12:9a20164dcc47 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
vipinranka 12:9a20164dcc47 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
vipinranka 12:9a20164dcc47 1049
vipinranka 12:9a20164dcc47 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
vipinranka 12:9a20164dcc47 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
vipinranka 12:9a20164dcc47 1052
vipinranka 12:9a20164dcc47 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
vipinranka 12:9a20164dcc47 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
vipinranka 12:9a20164dcc47 1055
vipinranka 12:9a20164dcc47 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
vipinranka 12:9a20164dcc47 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
vipinranka 12:9a20164dcc47 1058
vipinranka 12:9a20164dcc47 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
vipinranka 12:9a20164dcc47 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
vipinranka 12:9a20164dcc47 1061
vipinranka 12:9a20164dcc47 1062 /* TPI DEVTYPE Register Definitions */
vipinranka 12:9a20164dcc47 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
vipinranka 12:9a20164dcc47 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
vipinranka 12:9a20164dcc47 1065
vipinranka 12:9a20164dcc47 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
vipinranka 12:9a20164dcc47 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
vipinranka 12:9a20164dcc47 1068
vipinranka 12:9a20164dcc47 1069 /*@}*/ /* end of group CMSIS_TPI */
vipinranka 12:9a20164dcc47 1070
vipinranka 12:9a20164dcc47 1071
vipinranka 12:9a20164dcc47 1072 #if (__MPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 1073 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
vipinranka 12:9a20164dcc47 1075 \brief Type definitions for the Memory Protection Unit (MPU)
vipinranka 12:9a20164dcc47 1076 @{
vipinranka 12:9a20164dcc47 1077 */
vipinranka 12:9a20164dcc47 1078
vipinranka 12:9a20164dcc47 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
vipinranka 12:9a20164dcc47 1080 */
vipinranka 12:9a20164dcc47 1081 typedef struct
vipinranka 12:9a20164dcc47 1082 {
vipinranka 12:9a20164dcc47 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
vipinranka 12:9a20164dcc47 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
vipinranka 12:9a20164dcc47 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
vipinranka 12:9a20164dcc47 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
vipinranka 12:9a20164dcc47 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
vipinranka 12:9a20164dcc47 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
vipinranka 12:9a20164dcc47 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
vipinranka 12:9a20164dcc47 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
vipinranka 12:9a20164dcc47 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
vipinranka 12:9a20164dcc47 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
vipinranka 12:9a20164dcc47 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
vipinranka 12:9a20164dcc47 1094 } MPU_Type;
vipinranka 12:9a20164dcc47 1095
vipinranka 12:9a20164dcc47 1096 /* MPU Type Register */
vipinranka 12:9a20164dcc47 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
vipinranka 12:9a20164dcc47 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
vipinranka 12:9a20164dcc47 1099
vipinranka 12:9a20164dcc47 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
vipinranka 12:9a20164dcc47 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
vipinranka 12:9a20164dcc47 1102
vipinranka 12:9a20164dcc47 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
vipinranka 12:9a20164dcc47 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
vipinranka 12:9a20164dcc47 1105
vipinranka 12:9a20164dcc47 1106 /* MPU Control Register */
vipinranka 12:9a20164dcc47 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
vipinranka 12:9a20164dcc47 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
vipinranka 12:9a20164dcc47 1109
vipinranka 12:9a20164dcc47 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
vipinranka 12:9a20164dcc47 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
vipinranka 12:9a20164dcc47 1112
vipinranka 12:9a20164dcc47 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
vipinranka 12:9a20164dcc47 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
vipinranka 12:9a20164dcc47 1115
vipinranka 12:9a20164dcc47 1116 /* MPU Region Number Register */
vipinranka 12:9a20164dcc47 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
vipinranka 12:9a20164dcc47 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
vipinranka 12:9a20164dcc47 1119
vipinranka 12:9a20164dcc47 1120 /* MPU Region Base Address Register */
vipinranka 12:9a20164dcc47 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
vipinranka 12:9a20164dcc47 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
vipinranka 12:9a20164dcc47 1123
vipinranka 12:9a20164dcc47 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
vipinranka 12:9a20164dcc47 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
vipinranka 12:9a20164dcc47 1126
vipinranka 12:9a20164dcc47 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
vipinranka 12:9a20164dcc47 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
vipinranka 12:9a20164dcc47 1129
vipinranka 12:9a20164dcc47 1130 /* MPU Region Attribute and Size Register */
vipinranka 12:9a20164dcc47 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
vipinranka 12:9a20164dcc47 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
vipinranka 12:9a20164dcc47 1133
vipinranka 12:9a20164dcc47 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
vipinranka 12:9a20164dcc47 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
vipinranka 12:9a20164dcc47 1136
vipinranka 12:9a20164dcc47 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
vipinranka 12:9a20164dcc47 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
vipinranka 12:9a20164dcc47 1139
vipinranka 12:9a20164dcc47 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
vipinranka 12:9a20164dcc47 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
vipinranka 12:9a20164dcc47 1142
vipinranka 12:9a20164dcc47 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
vipinranka 12:9a20164dcc47 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
vipinranka 12:9a20164dcc47 1145
vipinranka 12:9a20164dcc47 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
vipinranka 12:9a20164dcc47 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
vipinranka 12:9a20164dcc47 1148
vipinranka 12:9a20164dcc47 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
vipinranka 12:9a20164dcc47 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
vipinranka 12:9a20164dcc47 1151
vipinranka 12:9a20164dcc47 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
vipinranka 12:9a20164dcc47 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
vipinranka 12:9a20164dcc47 1154
vipinranka 12:9a20164dcc47 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
vipinranka 12:9a20164dcc47 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
vipinranka 12:9a20164dcc47 1157
vipinranka 12:9a20164dcc47 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
vipinranka 12:9a20164dcc47 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
vipinranka 12:9a20164dcc47 1160
vipinranka 12:9a20164dcc47 1161 /*@} end of group CMSIS_MPU */
vipinranka 12:9a20164dcc47 1162 #endif
vipinranka 12:9a20164dcc47 1163
vipinranka 12:9a20164dcc47 1164
vipinranka 12:9a20164dcc47 1165 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
vipinranka 12:9a20164dcc47 1167 \brief Type definitions for the Core Debug Registers
vipinranka 12:9a20164dcc47 1168 @{
vipinranka 12:9a20164dcc47 1169 */
vipinranka 12:9a20164dcc47 1170
vipinranka 12:9a20164dcc47 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
vipinranka 12:9a20164dcc47 1172 */
vipinranka 12:9a20164dcc47 1173 typedef struct
vipinranka 12:9a20164dcc47 1174 {
vipinranka 12:9a20164dcc47 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
vipinranka 12:9a20164dcc47 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
vipinranka 12:9a20164dcc47 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
vipinranka 12:9a20164dcc47 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
vipinranka 12:9a20164dcc47 1179 } CoreDebug_Type;
vipinranka 12:9a20164dcc47 1180
vipinranka 12:9a20164dcc47 1181 /* Debug Halting Control and Status Register */
vipinranka 12:9a20164dcc47 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
vipinranka 12:9a20164dcc47 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
vipinranka 12:9a20164dcc47 1184
vipinranka 12:9a20164dcc47 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
vipinranka 12:9a20164dcc47 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
vipinranka 12:9a20164dcc47 1187
vipinranka 12:9a20164dcc47 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
vipinranka 12:9a20164dcc47 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
vipinranka 12:9a20164dcc47 1190
vipinranka 12:9a20164dcc47 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
vipinranka 12:9a20164dcc47 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
vipinranka 12:9a20164dcc47 1193
vipinranka 12:9a20164dcc47 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
vipinranka 12:9a20164dcc47 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
vipinranka 12:9a20164dcc47 1196
vipinranka 12:9a20164dcc47 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
vipinranka 12:9a20164dcc47 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
vipinranka 12:9a20164dcc47 1199
vipinranka 12:9a20164dcc47 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
vipinranka 12:9a20164dcc47 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
vipinranka 12:9a20164dcc47 1202
vipinranka 12:9a20164dcc47 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
vipinranka 12:9a20164dcc47 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
vipinranka 12:9a20164dcc47 1205
vipinranka 12:9a20164dcc47 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
vipinranka 12:9a20164dcc47 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
vipinranka 12:9a20164dcc47 1208
vipinranka 12:9a20164dcc47 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
vipinranka 12:9a20164dcc47 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
vipinranka 12:9a20164dcc47 1211
vipinranka 12:9a20164dcc47 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
vipinranka 12:9a20164dcc47 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
vipinranka 12:9a20164dcc47 1214
vipinranka 12:9a20164dcc47 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
vipinranka 12:9a20164dcc47 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
vipinranka 12:9a20164dcc47 1217
vipinranka 12:9a20164dcc47 1218 /* Debug Core Register Selector Register */
vipinranka 12:9a20164dcc47 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
vipinranka 12:9a20164dcc47 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
vipinranka 12:9a20164dcc47 1221
vipinranka 12:9a20164dcc47 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
vipinranka 12:9a20164dcc47 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
vipinranka 12:9a20164dcc47 1224
vipinranka 12:9a20164dcc47 1225 /* Debug Exception and Monitor Control Register */
vipinranka 12:9a20164dcc47 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
vipinranka 12:9a20164dcc47 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
vipinranka 12:9a20164dcc47 1228
vipinranka 12:9a20164dcc47 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
vipinranka 12:9a20164dcc47 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
vipinranka 12:9a20164dcc47 1231
vipinranka 12:9a20164dcc47 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
vipinranka 12:9a20164dcc47 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
vipinranka 12:9a20164dcc47 1234
vipinranka 12:9a20164dcc47 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
vipinranka 12:9a20164dcc47 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
vipinranka 12:9a20164dcc47 1237
vipinranka 12:9a20164dcc47 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
vipinranka 12:9a20164dcc47 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
vipinranka 12:9a20164dcc47 1240
vipinranka 12:9a20164dcc47 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
vipinranka 12:9a20164dcc47 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
vipinranka 12:9a20164dcc47 1243
vipinranka 12:9a20164dcc47 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
vipinranka 12:9a20164dcc47 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
vipinranka 12:9a20164dcc47 1246
vipinranka 12:9a20164dcc47 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
vipinranka 12:9a20164dcc47 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
vipinranka 12:9a20164dcc47 1249
vipinranka 12:9a20164dcc47 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
vipinranka 12:9a20164dcc47 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
vipinranka 12:9a20164dcc47 1252
vipinranka 12:9a20164dcc47 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
vipinranka 12:9a20164dcc47 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
vipinranka 12:9a20164dcc47 1255
vipinranka 12:9a20164dcc47 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
vipinranka 12:9a20164dcc47 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
vipinranka 12:9a20164dcc47 1258
vipinranka 12:9a20164dcc47 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
vipinranka 12:9a20164dcc47 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
vipinranka 12:9a20164dcc47 1261
vipinranka 12:9a20164dcc47 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
vipinranka 12:9a20164dcc47 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
vipinranka 12:9a20164dcc47 1264
vipinranka 12:9a20164dcc47 1265 /*@} end of group CMSIS_CoreDebug */
vipinranka 12:9a20164dcc47 1266
vipinranka 12:9a20164dcc47 1267
vipinranka 12:9a20164dcc47 1268 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 1269 \defgroup CMSIS_core_base Core Definitions
vipinranka 12:9a20164dcc47 1270 \brief Definitions for base addresses, unions, and structures.
vipinranka 12:9a20164dcc47 1271 @{
vipinranka 12:9a20164dcc47 1272 */
vipinranka 12:9a20164dcc47 1273
vipinranka 12:9a20164dcc47 1274 /* Memory mapping of Cortex-M3 Hardware */
vipinranka 12:9a20164dcc47 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
vipinranka 12:9a20164dcc47 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
vipinranka 12:9a20164dcc47 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
vipinranka 12:9a20164dcc47 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
vipinranka 12:9a20164dcc47 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
vipinranka 12:9a20164dcc47 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
vipinranka 12:9a20164dcc47 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
vipinranka 12:9a20164dcc47 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
vipinranka 12:9a20164dcc47 1283
vipinranka 12:9a20164dcc47 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
vipinranka 12:9a20164dcc47 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
vipinranka 12:9a20164dcc47 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
vipinranka 12:9a20164dcc47 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
vipinranka 12:9a20164dcc47 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
vipinranka 12:9a20164dcc47 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
vipinranka 12:9a20164dcc47 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
vipinranka 12:9a20164dcc47 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
vipinranka 12:9a20164dcc47 1292
vipinranka 12:9a20164dcc47 1293 #if (__MPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
vipinranka 12:9a20164dcc47 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
vipinranka 12:9a20164dcc47 1296 #endif
vipinranka 12:9a20164dcc47 1297
vipinranka 12:9a20164dcc47 1298 /*@} */
vipinranka 12:9a20164dcc47 1299
vipinranka 12:9a20164dcc47 1300
vipinranka 12:9a20164dcc47 1301
vipinranka 12:9a20164dcc47 1302 /*******************************************************************************
vipinranka 12:9a20164dcc47 1303 * Hardware Abstraction Layer
vipinranka 12:9a20164dcc47 1304 Core Function Interface contains:
vipinranka 12:9a20164dcc47 1305 - Core NVIC Functions
vipinranka 12:9a20164dcc47 1306 - Core SysTick Functions
vipinranka 12:9a20164dcc47 1307 - Core Debug Functions
vipinranka 12:9a20164dcc47 1308 - Core Register Access Functions
vipinranka 12:9a20164dcc47 1309 ******************************************************************************/
vipinranka 12:9a20164dcc47 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
vipinranka 12:9a20164dcc47 1311 */
vipinranka 12:9a20164dcc47 1312
vipinranka 12:9a20164dcc47 1313
vipinranka 12:9a20164dcc47 1314
vipinranka 12:9a20164dcc47 1315 /* ########################## NVIC functions #################################### */
vipinranka 12:9a20164dcc47 1316 /** \ingroup CMSIS_Core_FunctionInterface
vipinranka 12:9a20164dcc47 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
vipinranka 12:9a20164dcc47 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
vipinranka 12:9a20164dcc47 1319 @{
vipinranka 12:9a20164dcc47 1320 */
vipinranka 12:9a20164dcc47 1321
vipinranka 12:9a20164dcc47 1322 /** \brief Set Priority Grouping
vipinranka 12:9a20164dcc47 1323
vipinranka 12:9a20164dcc47 1324 The function sets the priority grouping field using the required unlock sequence.
vipinranka 12:9a20164dcc47 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
vipinranka 12:9a20164dcc47 1326 Only values from 0..7 are used.
vipinranka 12:9a20164dcc47 1327 In case of a conflict between priority grouping and available
vipinranka 12:9a20164dcc47 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
vipinranka 12:9a20164dcc47 1329
vipinranka 12:9a20164dcc47 1330 \param [in] PriorityGroup Priority grouping field.
vipinranka 12:9a20164dcc47 1331 */
vipinranka 12:9a20164dcc47 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
vipinranka 12:9a20164dcc47 1333 {
vipinranka 12:9a20164dcc47 1334 uint32_t reg_value;
vipinranka 12:9a20164dcc47 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vipinranka 12:9a20164dcc47 1336
vipinranka 12:9a20164dcc47 1337 reg_value = SCB->AIRCR; /* read old register configuration */
vipinranka 12:9a20164dcc47 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
vipinranka 12:9a20164dcc47 1339 reg_value = (reg_value |
vipinranka 12:9a20164dcc47 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
vipinranka 12:9a20164dcc47 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
vipinranka 12:9a20164dcc47 1342 SCB->AIRCR = reg_value;
vipinranka 12:9a20164dcc47 1343 }
vipinranka 12:9a20164dcc47 1344
vipinranka 12:9a20164dcc47 1345
vipinranka 12:9a20164dcc47 1346 /** \brief Get Priority Grouping
vipinranka 12:9a20164dcc47 1347
vipinranka 12:9a20164dcc47 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
vipinranka 12:9a20164dcc47 1349
vipinranka 12:9a20164dcc47 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
vipinranka 12:9a20164dcc47 1351 */
vipinranka 12:9a20164dcc47 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
vipinranka 12:9a20164dcc47 1353 {
vipinranka 12:9a20164dcc47 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
vipinranka 12:9a20164dcc47 1355 }
vipinranka 12:9a20164dcc47 1356
vipinranka 12:9a20164dcc47 1357
vipinranka 12:9a20164dcc47 1358 /** \brief Enable External Interrupt
vipinranka 12:9a20164dcc47 1359
vipinranka 12:9a20164dcc47 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
vipinranka 12:9a20164dcc47 1361
vipinranka 12:9a20164dcc47 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka 12:9a20164dcc47 1363 */
vipinranka 12:9a20164dcc47 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 1365 {
vipinranka 12:9a20164dcc47 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka 12:9a20164dcc47 1367 }
vipinranka 12:9a20164dcc47 1368
vipinranka 12:9a20164dcc47 1369
vipinranka 12:9a20164dcc47 1370 /** \brief Disable External Interrupt
vipinranka 12:9a20164dcc47 1371
vipinranka 12:9a20164dcc47 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
vipinranka 12:9a20164dcc47 1373
vipinranka 12:9a20164dcc47 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka 12:9a20164dcc47 1375 */
vipinranka 12:9a20164dcc47 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 1377 {
vipinranka 12:9a20164dcc47 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka 12:9a20164dcc47 1379 __DSB();
vipinranka 12:9a20164dcc47 1380 __ISB();
vipinranka 12:9a20164dcc47 1381 }
vipinranka 12:9a20164dcc47 1382
vipinranka 12:9a20164dcc47 1383
vipinranka 12:9a20164dcc47 1384 /** \brief Get Pending Interrupt
vipinranka 12:9a20164dcc47 1385
vipinranka 12:9a20164dcc47 1386 The function reads the pending register in the NVIC and returns the pending bit
vipinranka 12:9a20164dcc47 1387 for the specified interrupt.
vipinranka 12:9a20164dcc47 1388
vipinranka 12:9a20164dcc47 1389 \param [in] IRQn Interrupt number.
vipinranka 12:9a20164dcc47 1390
vipinranka 12:9a20164dcc47 1391 \return 0 Interrupt status is not pending.
vipinranka 12:9a20164dcc47 1392 \return 1 Interrupt status is pending.
vipinranka 12:9a20164dcc47 1393 */
vipinranka 12:9a20164dcc47 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 1395 {
vipinranka 12:9a20164dcc47 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vipinranka 12:9a20164dcc47 1397 }
vipinranka 12:9a20164dcc47 1398
vipinranka 12:9a20164dcc47 1399
vipinranka 12:9a20164dcc47 1400 /** \brief Set Pending Interrupt
vipinranka 12:9a20164dcc47 1401
vipinranka 12:9a20164dcc47 1402 The function sets the pending bit of an external interrupt.
vipinranka 12:9a20164dcc47 1403
vipinranka 12:9a20164dcc47 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
vipinranka 12:9a20164dcc47 1405 */
vipinranka 12:9a20164dcc47 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 1407 {
vipinranka 12:9a20164dcc47 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka 12:9a20164dcc47 1409 }
vipinranka 12:9a20164dcc47 1410
vipinranka 12:9a20164dcc47 1411
vipinranka 12:9a20164dcc47 1412 /** \brief Clear Pending Interrupt
vipinranka 12:9a20164dcc47 1413
vipinranka 12:9a20164dcc47 1414 The function clears the pending bit of an external interrupt.
vipinranka 12:9a20164dcc47 1415
vipinranka 12:9a20164dcc47 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka 12:9a20164dcc47 1417 */
vipinranka 12:9a20164dcc47 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 1419 {
vipinranka 12:9a20164dcc47 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka 12:9a20164dcc47 1421 }
vipinranka 12:9a20164dcc47 1422
vipinranka 12:9a20164dcc47 1423
vipinranka 12:9a20164dcc47 1424 /** \brief Get Active Interrupt
vipinranka 12:9a20164dcc47 1425
vipinranka 12:9a20164dcc47 1426 The function reads the active register in NVIC and returns the active bit.
vipinranka 12:9a20164dcc47 1427
vipinranka 12:9a20164dcc47 1428 \param [in] IRQn Interrupt number.
vipinranka 12:9a20164dcc47 1429
vipinranka 12:9a20164dcc47 1430 \return 0 Interrupt status is not active.
vipinranka 12:9a20164dcc47 1431 \return 1 Interrupt status is active.
vipinranka 12:9a20164dcc47 1432 */
vipinranka 12:9a20164dcc47 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 1434 {
vipinranka 12:9a20164dcc47 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vipinranka 12:9a20164dcc47 1436 }
vipinranka 12:9a20164dcc47 1437
vipinranka 12:9a20164dcc47 1438
vipinranka 12:9a20164dcc47 1439 /** \brief Set Interrupt Priority
vipinranka 12:9a20164dcc47 1440
vipinranka 12:9a20164dcc47 1441 The function sets the priority of an interrupt.
vipinranka 12:9a20164dcc47 1442
vipinranka 12:9a20164dcc47 1443 \note The priority cannot be set for every core interrupt.
vipinranka 12:9a20164dcc47 1444
vipinranka 12:9a20164dcc47 1445 \param [in] IRQn Interrupt number.
vipinranka 12:9a20164dcc47 1446 \param [in] priority Priority to set.
vipinranka 12:9a20164dcc47 1447 */
vipinranka 12:9a20164dcc47 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
vipinranka 12:9a20164dcc47 1449 {
vipinranka 12:9a20164dcc47 1450 if((int32_t)IRQn < 0) {
vipinranka 12:9a20164dcc47 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
vipinranka 12:9a20164dcc47 1452 }
vipinranka 12:9a20164dcc47 1453 else {
vipinranka 12:9a20164dcc47 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
vipinranka 12:9a20164dcc47 1455 }
vipinranka 12:9a20164dcc47 1456 }
vipinranka 12:9a20164dcc47 1457
vipinranka 12:9a20164dcc47 1458
vipinranka 12:9a20164dcc47 1459 /** \brief Get Interrupt Priority
vipinranka 12:9a20164dcc47 1460
vipinranka 12:9a20164dcc47 1461 The function reads the priority of an interrupt. The interrupt
vipinranka 12:9a20164dcc47 1462 number can be positive to specify an external (device specific)
vipinranka 12:9a20164dcc47 1463 interrupt, or negative to specify an internal (core) interrupt.
vipinranka 12:9a20164dcc47 1464
vipinranka 12:9a20164dcc47 1465
vipinranka 12:9a20164dcc47 1466 \param [in] IRQn Interrupt number.
vipinranka 12:9a20164dcc47 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
vipinranka 12:9a20164dcc47 1468 priority bits of the microcontroller.
vipinranka 12:9a20164dcc47 1469 */
vipinranka 12:9a20164dcc47 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 1471 {
vipinranka 12:9a20164dcc47 1472
vipinranka 12:9a20164dcc47 1473 if((int32_t)IRQn < 0) {
vipinranka 12:9a20164dcc47 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
vipinranka 12:9a20164dcc47 1475 }
vipinranka 12:9a20164dcc47 1476 else {
vipinranka 12:9a20164dcc47 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
vipinranka 12:9a20164dcc47 1478 }
vipinranka 12:9a20164dcc47 1479 }
vipinranka 12:9a20164dcc47 1480
vipinranka 12:9a20164dcc47 1481
vipinranka 12:9a20164dcc47 1482 /** \brief Encode Priority
vipinranka 12:9a20164dcc47 1483
vipinranka 12:9a20164dcc47 1484 The function encodes the priority for an interrupt with the given priority group,
vipinranka 12:9a20164dcc47 1485 preemptive priority value, and subpriority value.
vipinranka 12:9a20164dcc47 1486 In case of a conflict between priority grouping and available
vipinranka 12:9a20164dcc47 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
vipinranka 12:9a20164dcc47 1488
vipinranka 12:9a20164dcc47 1489 \param [in] PriorityGroup Used priority group.
vipinranka 12:9a20164dcc47 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
vipinranka 12:9a20164dcc47 1491 \param [in] SubPriority Subpriority value (starting from 0).
vipinranka 12:9a20164dcc47 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
vipinranka 12:9a20164dcc47 1493 */
vipinranka 12:9a20164dcc47 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
vipinranka 12:9a20164dcc47 1495 {
vipinranka 12:9a20164dcc47 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vipinranka 12:9a20164dcc47 1497 uint32_t PreemptPriorityBits;
vipinranka 12:9a20164dcc47 1498 uint32_t SubPriorityBits;
vipinranka 12:9a20164dcc47 1499
vipinranka 12:9a20164dcc47 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
vipinranka 12:9a20164dcc47 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
vipinranka 12:9a20164dcc47 1502
vipinranka 12:9a20164dcc47 1503 return (
vipinranka 12:9a20164dcc47 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
vipinranka 12:9a20164dcc47 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
vipinranka 12:9a20164dcc47 1506 );
vipinranka 12:9a20164dcc47 1507 }
vipinranka 12:9a20164dcc47 1508
vipinranka 12:9a20164dcc47 1509
vipinranka 12:9a20164dcc47 1510 /** \brief Decode Priority
vipinranka 12:9a20164dcc47 1511
vipinranka 12:9a20164dcc47 1512 The function decodes an interrupt priority value with a given priority group to
vipinranka 12:9a20164dcc47 1513 preemptive priority value and subpriority value.
vipinranka 12:9a20164dcc47 1514 In case of a conflict between priority grouping and available
vipinranka 12:9a20164dcc47 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
vipinranka 12:9a20164dcc47 1516
vipinranka 12:9a20164dcc47 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
vipinranka 12:9a20164dcc47 1518 \param [in] PriorityGroup Used priority group.
vipinranka 12:9a20164dcc47 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
vipinranka 12:9a20164dcc47 1520 \param [out] pSubPriority Subpriority value (starting from 0).
vipinranka 12:9a20164dcc47 1521 */
vipinranka 12:9a20164dcc47 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
vipinranka 12:9a20164dcc47 1523 {
vipinranka 12:9a20164dcc47 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vipinranka 12:9a20164dcc47 1525 uint32_t PreemptPriorityBits;
vipinranka 12:9a20164dcc47 1526 uint32_t SubPriorityBits;
vipinranka 12:9a20164dcc47 1527
vipinranka 12:9a20164dcc47 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
vipinranka 12:9a20164dcc47 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
vipinranka 12:9a20164dcc47 1530
vipinranka 12:9a20164dcc47 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
vipinranka 12:9a20164dcc47 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
vipinranka 12:9a20164dcc47 1533 }
vipinranka 12:9a20164dcc47 1534
vipinranka 12:9a20164dcc47 1535
vipinranka 12:9a20164dcc47 1536 /** \brief System Reset
vipinranka 12:9a20164dcc47 1537
vipinranka 12:9a20164dcc47 1538 The function initiates a system reset request to reset the MCU.
vipinranka 12:9a20164dcc47 1539 */
vipinranka 12:9a20164dcc47 1540 __STATIC_INLINE void NVIC_SystemReset(void)
vipinranka 12:9a20164dcc47 1541 {
vipinranka 12:9a20164dcc47 1542 __DSB(); /* Ensure all outstanding memory accesses included
vipinranka 12:9a20164dcc47 1543 buffered write are completed before reset */
vipinranka 12:9a20164dcc47 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
vipinranka 12:9a20164dcc47 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
vipinranka 12:9a20164dcc47 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
vipinranka 12:9a20164dcc47 1547 __DSB(); /* Ensure completion of memory access */
vipinranka 12:9a20164dcc47 1548 while(1) { __NOP(); } /* wait until reset */
vipinranka 12:9a20164dcc47 1549 }
vipinranka 12:9a20164dcc47 1550
vipinranka 12:9a20164dcc47 1551 /*@} end of CMSIS_Core_NVICFunctions */
vipinranka 12:9a20164dcc47 1552
vipinranka 12:9a20164dcc47 1553
vipinranka 12:9a20164dcc47 1554
vipinranka 12:9a20164dcc47 1555 /* ################################## SysTick function ############################################ */
vipinranka 12:9a20164dcc47 1556 /** \ingroup CMSIS_Core_FunctionInterface
vipinranka 12:9a20164dcc47 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
vipinranka 12:9a20164dcc47 1558 \brief Functions that configure the System.
vipinranka 12:9a20164dcc47 1559 @{
vipinranka 12:9a20164dcc47 1560 */
vipinranka 12:9a20164dcc47 1561
vipinranka 12:9a20164dcc47 1562 #if (__Vendor_SysTickConfig == 0)
vipinranka 12:9a20164dcc47 1563
vipinranka 12:9a20164dcc47 1564 /** \brief System Tick Configuration
vipinranka 12:9a20164dcc47 1565
vipinranka 12:9a20164dcc47 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
vipinranka 12:9a20164dcc47 1567 Counter is in free running mode to generate periodic interrupts.
vipinranka 12:9a20164dcc47 1568
vipinranka 12:9a20164dcc47 1569 \param [in] ticks Number of ticks between two interrupts.
vipinranka 12:9a20164dcc47 1570
vipinranka 12:9a20164dcc47 1571 \return 0 Function succeeded.
vipinranka 12:9a20164dcc47 1572 \return 1 Function failed.
vipinranka 12:9a20164dcc47 1573
vipinranka 12:9a20164dcc47 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
vipinranka 12:9a20164dcc47 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
vipinranka 12:9a20164dcc47 1576 must contain a vendor-specific implementation of this function.
vipinranka 12:9a20164dcc47 1577
vipinranka 12:9a20164dcc47 1578 */
vipinranka 12:9a20164dcc47 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
vipinranka 12:9a20164dcc47 1580 {
vipinranka 12:9a20164dcc47 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
vipinranka 12:9a20164dcc47 1582
vipinranka 12:9a20164dcc47 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
vipinranka 12:9a20164dcc47 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
vipinranka 12:9a20164dcc47 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
vipinranka 12:9a20164dcc47 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
vipinranka 12:9a20164dcc47 1587 SysTick_CTRL_TICKINT_Msk |
vipinranka 12:9a20164dcc47 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
vipinranka 12:9a20164dcc47 1589 return (0UL); /* Function successful */
vipinranka 12:9a20164dcc47 1590 }
vipinranka 12:9a20164dcc47 1591
vipinranka 12:9a20164dcc47 1592 #endif
vipinranka 12:9a20164dcc47 1593
vipinranka 12:9a20164dcc47 1594 /*@} end of CMSIS_Core_SysTickFunctions */
vipinranka 12:9a20164dcc47 1595
vipinranka 12:9a20164dcc47 1596
vipinranka 12:9a20164dcc47 1597
vipinranka 12:9a20164dcc47 1598 /* ##################################### Debug In/Output function ########################################### */
vipinranka 12:9a20164dcc47 1599 /** \ingroup CMSIS_Core_FunctionInterface
vipinranka 12:9a20164dcc47 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
vipinranka 12:9a20164dcc47 1601 \brief Functions that access the ITM debug interface.
vipinranka 12:9a20164dcc47 1602 @{
vipinranka 12:9a20164dcc47 1603 */
vipinranka 12:9a20164dcc47 1604
vipinranka 12:9a20164dcc47 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
vipinranka 12:9a20164dcc47 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
vipinranka 12:9a20164dcc47 1607
vipinranka 12:9a20164dcc47 1608
vipinranka 12:9a20164dcc47 1609 /** \brief ITM Send Character
vipinranka 12:9a20164dcc47 1610
vipinranka 12:9a20164dcc47 1611 The function transmits a character via the ITM channel 0, and
vipinranka 12:9a20164dcc47 1612 \li Just returns when no debugger is connected that has booked the output.
vipinranka 12:9a20164dcc47 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
vipinranka 12:9a20164dcc47 1614
vipinranka 12:9a20164dcc47 1615 \param [in] ch Character to transmit.
vipinranka 12:9a20164dcc47 1616
vipinranka 12:9a20164dcc47 1617 \returns Character to transmit.
vipinranka 12:9a20164dcc47 1618 */
vipinranka 12:9a20164dcc47 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
vipinranka 12:9a20164dcc47 1620 {
vipinranka 12:9a20164dcc47 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
vipinranka 12:9a20164dcc47 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
vipinranka 12:9a20164dcc47 1623 {
vipinranka 12:9a20164dcc47 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
vipinranka 12:9a20164dcc47 1625 ITM->PORT[0].u8 = (uint8_t)ch;
vipinranka 12:9a20164dcc47 1626 }
vipinranka 12:9a20164dcc47 1627 return (ch);
vipinranka 12:9a20164dcc47 1628 }
vipinranka 12:9a20164dcc47 1629
vipinranka 12:9a20164dcc47 1630
vipinranka 12:9a20164dcc47 1631 /** \brief ITM Receive Character
vipinranka 12:9a20164dcc47 1632
vipinranka 12:9a20164dcc47 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
vipinranka 12:9a20164dcc47 1634
vipinranka 12:9a20164dcc47 1635 \return Received character.
vipinranka 12:9a20164dcc47 1636 \return -1 No character pending.
vipinranka 12:9a20164dcc47 1637 */
vipinranka 12:9a20164dcc47 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
vipinranka 12:9a20164dcc47 1639 int32_t ch = -1; /* no character available */
vipinranka 12:9a20164dcc47 1640
vipinranka 12:9a20164dcc47 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
vipinranka 12:9a20164dcc47 1642 ch = ITM_RxBuffer;
vipinranka 12:9a20164dcc47 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
vipinranka 12:9a20164dcc47 1644 }
vipinranka 12:9a20164dcc47 1645
vipinranka 12:9a20164dcc47 1646 return (ch);
vipinranka 12:9a20164dcc47 1647 }
vipinranka 12:9a20164dcc47 1648
vipinranka 12:9a20164dcc47 1649
vipinranka 12:9a20164dcc47 1650 /** \brief ITM Check Character
vipinranka 12:9a20164dcc47 1651
vipinranka 12:9a20164dcc47 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
vipinranka 12:9a20164dcc47 1653
vipinranka 12:9a20164dcc47 1654 \return 0 No character available.
vipinranka 12:9a20164dcc47 1655 \return 1 Character available.
vipinranka 12:9a20164dcc47 1656 */
vipinranka 12:9a20164dcc47 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
vipinranka 12:9a20164dcc47 1658
vipinranka 12:9a20164dcc47 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
vipinranka 12:9a20164dcc47 1660 return (0); /* no character available */
vipinranka 12:9a20164dcc47 1661 } else {
vipinranka 12:9a20164dcc47 1662 return (1); /* character available */
vipinranka 12:9a20164dcc47 1663 }
vipinranka 12:9a20164dcc47 1664 }
vipinranka 12:9a20164dcc47 1665
vipinranka 12:9a20164dcc47 1666 /*@} end of CMSIS_core_DebugFunctions */
vipinranka 12:9a20164dcc47 1667
vipinranka 12:9a20164dcc47 1668
vipinranka 12:9a20164dcc47 1669
vipinranka 12:9a20164dcc47 1670
vipinranka 12:9a20164dcc47 1671 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 1672 }
vipinranka 12:9a20164dcc47 1673 #endif
vipinranka 12:9a20164dcc47 1674
vipinranka 12:9a20164dcc47 1675 #endif /* __CORE_SC300_H_DEPENDANT */
vipinranka 12:9a20164dcc47 1676
vipinranka 12:9a20164dcc47 1677 #endif /* __CMSIS_GENERIC */