Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/cmsis/core_cmInstr.h@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /**************************************************************************//**
vipinranka 12:9a20164dcc47 2 * @file core_cmInstr.h
vipinranka 12:9a20164dcc47 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
vipinranka 12:9a20164dcc47 4 * @version V4.10
vipinranka 12:9a20164dcc47 5 * @date 18. March 2015
vipinranka 12:9a20164dcc47 6 *
vipinranka 12:9a20164dcc47 7 * @note
vipinranka 12:9a20164dcc47 8 *
vipinranka 12:9a20164dcc47 9 ******************************************************************************/
vipinranka 12:9a20164dcc47 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
vipinranka 12:9a20164dcc47 11
vipinranka 12:9a20164dcc47 12 All rights reserved.
vipinranka 12:9a20164dcc47 13 Redistribution and use in source and binary forms, with or without
vipinranka 12:9a20164dcc47 14 modification, are permitted provided that the following conditions are met:
vipinranka 12:9a20164dcc47 15 - Redistributions of source code must retain the above copyright
vipinranka 12:9a20164dcc47 16 notice, this list of conditions and the following disclaimer.
vipinranka 12:9a20164dcc47 17 - Redistributions in binary form must reproduce the above copyright
vipinranka 12:9a20164dcc47 18 notice, this list of conditions and the following disclaimer in the
vipinranka 12:9a20164dcc47 19 documentation and/or other materials provided with the distribution.
vipinranka 12:9a20164dcc47 20 - Neither the name of ARM nor the names of its contributors may be used
vipinranka 12:9a20164dcc47 21 to endorse or promote products derived from this software without
vipinranka 12:9a20164dcc47 22 specific prior written permission.
vipinranka 12:9a20164dcc47 23 *
vipinranka 12:9a20164dcc47 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vipinranka 12:9a20164dcc47 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vipinranka 12:9a20164dcc47 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vipinranka 12:9a20164dcc47 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vipinranka 12:9a20164dcc47 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vipinranka 12:9a20164dcc47 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vipinranka 12:9a20164dcc47 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vipinranka 12:9a20164dcc47 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vipinranka 12:9a20164dcc47 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vipinranka 12:9a20164dcc47 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vipinranka 12:9a20164dcc47 34 POSSIBILITY OF SUCH DAMAGE.
vipinranka 12:9a20164dcc47 35 ---------------------------------------------------------------------------*/
vipinranka 12:9a20164dcc47 36
vipinranka 12:9a20164dcc47 37
vipinranka 12:9a20164dcc47 38 #ifndef __CORE_CMINSTR_H
vipinranka 12:9a20164dcc47 39 #define __CORE_CMINSTR_H
vipinranka 12:9a20164dcc47 40
vipinranka 12:9a20164dcc47 41
vipinranka 12:9a20164dcc47 42 /* ########################## Core Instruction Access ######################### */
vipinranka 12:9a20164dcc47 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
vipinranka 12:9a20164dcc47 44 Access to dedicated instructions
vipinranka 12:9a20164dcc47 45 @{
vipinranka 12:9a20164dcc47 46 */
vipinranka 12:9a20164dcc47 47
vipinranka 12:9a20164dcc47 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
vipinranka 12:9a20164dcc47 49 /* ARM armcc specific functions */
vipinranka 12:9a20164dcc47 50
vipinranka 12:9a20164dcc47 51 #if (__ARMCC_VERSION < 400677)
vipinranka 12:9a20164dcc47 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
vipinranka 12:9a20164dcc47 53 #endif
vipinranka 12:9a20164dcc47 54
vipinranka 12:9a20164dcc47 55
vipinranka 12:9a20164dcc47 56 /** \brief No Operation
vipinranka 12:9a20164dcc47 57
vipinranka 12:9a20164dcc47 58 No Operation does nothing. This instruction can be used for code alignment purposes.
vipinranka 12:9a20164dcc47 59 */
vipinranka 12:9a20164dcc47 60 #define __NOP __nop
vipinranka 12:9a20164dcc47 61
vipinranka 12:9a20164dcc47 62
vipinranka 12:9a20164dcc47 63 /** \brief Wait For Interrupt
vipinranka 12:9a20164dcc47 64
vipinranka 12:9a20164dcc47 65 Wait For Interrupt is a hint instruction that suspends execution
vipinranka 12:9a20164dcc47 66 until one of a number of events occurs.
vipinranka 12:9a20164dcc47 67 */
vipinranka 12:9a20164dcc47 68 #define __WFI __wfi
vipinranka 12:9a20164dcc47 69
vipinranka 12:9a20164dcc47 70
vipinranka 12:9a20164dcc47 71 /** \brief Wait For Event
vipinranka 12:9a20164dcc47 72
vipinranka 12:9a20164dcc47 73 Wait For Event is a hint instruction that permits the processor to enter
vipinranka 12:9a20164dcc47 74 a low-power state until one of a number of events occurs.
vipinranka 12:9a20164dcc47 75 */
vipinranka 12:9a20164dcc47 76 #define __WFE __wfe
vipinranka 12:9a20164dcc47 77
vipinranka 12:9a20164dcc47 78
vipinranka 12:9a20164dcc47 79 /** \brief Send Event
vipinranka 12:9a20164dcc47 80
vipinranka 12:9a20164dcc47 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
vipinranka 12:9a20164dcc47 82 */
vipinranka 12:9a20164dcc47 83 #define __SEV __sev
vipinranka 12:9a20164dcc47 84
vipinranka 12:9a20164dcc47 85
vipinranka 12:9a20164dcc47 86 /** \brief Instruction Synchronization Barrier
vipinranka 12:9a20164dcc47 87
vipinranka 12:9a20164dcc47 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
vipinranka 12:9a20164dcc47 89 so that all instructions following the ISB are fetched from cache or
vipinranka 12:9a20164dcc47 90 memory, after the instruction has been completed.
vipinranka 12:9a20164dcc47 91 */
vipinranka 12:9a20164dcc47 92 #define __ISB() do {\
vipinranka 12:9a20164dcc47 93 __schedule_barrier();\
vipinranka 12:9a20164dcc47 94 __isb(0xF);\
vipinranka 12:9a20164dcc47 95 __schedule_barrier();\
vipinranka 12:9a20164dcc47 96 } while (0)
vipinranka 12:9a20164dcc47 97
vipinranka 12:9a20164dcc47 98 /** \brief Data Synchronization Barrier
vipinranka 12:9a20164dcc47 99
vipinranka 12:9a20164dcc47 100 This function acts as a special kind of Data Memory Barrier.
vipinranka 12:9a20164dcc47 101 It completes when all explicit memory accesses before this instruction complete.
vipinranka 12:9a20164dcc47 102 */
vipinranka 12:9a20164dcc47 103 #define __DSB() do {\
vipinranka 12:9a20164dcc47 104 __schedule_barrier();\
vipinranka 12:9a20164dcc47 105 __dsb(0xF);\
vipinranka 12:9a20164dcc47 106 __schedule_barrier();\
vipinranka 12:9a20164dcc47 107 } while (0)
vipinranka 12:9a20164dcc47 108
vipinranka 12:9a20164dcc47 109 /** \brief Data Memory Barrier
vipinranka 12:9a20164dcc47 110
vipinranka 12:9a20164dcc47 111 This function ensures the apparent order of the explicit memory operations before
vipinranka 12:9a20164dcc47 112 and after the instruction, without ensuring their completion.
vipinranka 12:9a20164dcc47 113 */
vipinranka 12:9a20164dcc47 114 #define __DMB() do {\
vipinranka 12:9a20164dcc47 115 __schedule_barrier();\
vipinranka 12:9a20164dcc47 116 __dmb(0xF);\
vipinranka 12:9a20164dcc47 117 __schedule_barrier();\
vipinranka 12:9a20164dcc47 118 } while (0)
vipinranka 12:9a20164dcc47 119
vipinranka 12:9a20164dcc47 120 /** \brief Reverse byte order (32 bit)
vipinranka 12:9a20164dcc47 121
vipinranka 12:9a20164dcc47 122 This function reverses the byte order in integer value.
vipinranka 12:9a20164dcc47 123
vipinranka 12:9a20164dcc47 124 \param [in] value Value to reverse
vipinranka 12:9a20164dcc47 125 \return Reversed value
vipinranka 12:9a20164dcc47 126 */
vipinranka 12:9a20164dcc47 127 #define __REV __rev
vipinranka 12:9a20164dcc47 128
vipinranka 12:9a20164dcc47 129
vipinranka 12:9a20164dcc47 130 /** \brief Reverse byte order (16 bit)
vipinranka 12:9a20164dcc47 131
vipinranka 12:9a20164dcc47 132 This function reverses the byte order in two unsigned short values.
vipinranka 12:9a20164dcc47 133
vipinranka 12:9a20164dcc47 134 \param [in] value Value to reverse
vipinranka 12:9a20164dcc47 135 \return Reversed value
vipinranka 12:9a20164dcc47 136 */
vipinranka 12:9a20164dcc47 137 #ifndef __NO_EMBEDDED_ASM
vipinranka 12:9a20164dcc47 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
vipinranka 12:9a20164dcc47 139 {
vipinranka 12:9a20164dcc47 140 rev16 r0, r0
vipinranka 12:9a20164dcc47 141 bx lr
vipinranka 12:9a20164dcc47 142 }
vipinranka 12:9a20164dcc47 143 #endif
vipinranka 12:9a20164dcc47 144
vipinranka 12:9a20164dcc47 145 /** \brief Reverse byte order in signed short value
vipinranka 12:9a20164dcc47 146
vipinranka 12:9a20164dcc47 147 This function reverses the byte order in a signed short value with sign extension to integer.
vipinranka 12:9a20164dcc47 148
vipinranka 12:9a20164dcc47 149 \param [in] value Value to reverse
vipinranka 12:9a20164dcc47 150 \return Reversed value
vipinranka 12:9a20164dcc47 151 */
vipinranka 12:9a20164dcc47 152 #ifndef __NO_EMBEDDED_ASM
vipinranka 12:9a20164dcc47 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
vipinranka 12:9a20164dcc47 154 {
vipinranka 12:9a20164dcc47 155 revsh r0, r0
vipinranka 12:9a20164dcc47 156 bx lr
vipinranka 12:9a20164dcc47 157 }
vipinranka 12:9a20164dcc47 158 #endif
vipinranka 12:9a20164dcc47 159
vipinranka 12:9a20164dcc47 160
vipinranka 12:9a20164dcc47 161 /** \brief Rotate Right in unsigned value (32 bit)
vipinranka 12:9a20164dcc47 162
vipinranka 12:9a20164dcc47 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
vipinranka 12:9a20164dcc47 164
vipinranka 12:9a20164dcc47 165 \param [in] value Value to rotate
vipinranka 12:9a20164dcc47 166 \param [in] value Number of Bits to rotate
vipinranka 12:9a20164dcc47 167 \return Rotated value
vipinranka 12:9a20164dcc47 168 */
vipinranka 12:9a20164dcc47 169 #define __ROR __ror
vipinranka 12:9a20164dcc47 170
vipinranka 12:9a20164dcc47 171
vipinranka 12:9a20164dcc47 172 /** \brief Breakpoint
vipinranka 12:9a20164dcc47 173
vipinranka 12:9a20164dcc47 174 This function causes the processor to enter Debug state.
vipinranka 12:9a20164dcc47 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
vipinranka 12:9a20164dcc47 176
vipinranka 12:9a20164dcc47 177 \param [in] value is ignored by the processor.
vipinranka 12:9a20164dcc47 178 If required, a debugger can use it to store additional information about the breakpoint.
vipinranka 12:9a20164dcc47 179 */
vipinranka 12:9a20164dcc47 180 #define __BKPT(value) __breakpoint(value)
vipinranka 12:9a20164dcc47 181
vipinranka 12:9a20164dcc47 182
vipinranka 12:9a20164dcc47 183 /** \brief Reverse bit order of value
vipinranka 12:9a20164dcc47 184
vipinranka 12:9a20164dcc47 185 This function reverses the bit order of the given value.
vipinranka 12:9a20164dcc47 186
vipinranka 12:9a20164dcc47 187 \param [in] value Value to reverse
vipinranka 12:9a20164dcc47 188 \return Reversed value
vipinranka 12:9a20164dcc47 189 */
vipinranka 12:9a20164dcc47 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
vipinranka 12:9a20164dcc47 191 #define __RBIT __rbit
vipinranka 12:9a20164dcc47 192 #else
vipinranka 12:9a20164dcc47 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
vipinranka 12:9a20164dcc47 194 {
vipinranka 12:9a20164dcc47 195 uint32_t result;
vipinranka 12:9a20164dcc47 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
vipinranka 12:9a20164dcc47 197
vipinranka 12:9a20164dcc47 198 result = value; // r will be reversed bits of v; first get LSB of v
vipinranka 12:9a20164dcc47 199 for (value >>= 1; value; value >>= 1)
vipinranka 12:9a20164dcc47 200 {
vipinranka 12:9a20164dcc47 201 result <<= 1;
vipinranka 12:9a20164dcc47 202 result |= value & 1;
vipinranka 12:9a20164dcc47 203 s--;
vipinranka 12:9a20164dcc47 204 }
vipinranka 12:9a20164dcc47 205 result <<= s; // shift when v's highest bits are zero
vipinranka 12:9a20164dcc47 206 return(result);
vipinranka 12:9a20164dcc47 207 }
vipinranka 12:9a20164dcc47 208 #endif
vipinranka 12:9a20164dcc47 209
vipinranka 12:9a20164dcc47 210
vipinranka 12:9a20164dcc47 211 /** \brief Count leading zeros
vipinranka 12:9a20164dcc47 212
vipinranka 12:9a20164dcc47 213 This function counts the number of leading zeros of a data value.
vipinranka 12:9a20164dcc47 214
vipinranka 12:9a20164dcc47 215 \param [in] value Value to count the leading zeros
vipinranka 12:9a20164dcc47 216 \return number of leading zeros in value
vipinranka 12:9a20164dcc47 217 */
vipinranka 12:9a20164dcc47 218 #define __CLZ __clz
vipinranka 12:9a20164dcc47 219
vipinranka 12:9a20164dcc47 220
vipinranka 12:9a20164dcc47 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
vipinranka 12:9a20164dcc47 222
vipinranka 12:9a20164dcc47 223 /** \brief LDR Exclusive (8 bit)
vipinranka 12:9a20164dcc47 224
vipinranka 12:9a20164dcc47 225 This function executes a exclusive LDR instruction for 8 bit value.
vipinranka 12:9a20164dcc47 226
vipinranka 12:9a20164dcc47 227 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 228 \return value of type uint8_t at (*ptr)
vipinranka 12:9a20164dcc47 229 */
vipinranka 12:9a20164dcc47 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
vipinranka 12:9a20164dcc47 231
vipinranka 12:9a20164dcc47 232
vipinranka 12:9a20164dcc47 233 /** \brief LDR Exclusive (16 bit)
vipinranka 12:9a20164dcc47 234
vipinranka 12:9a20164dcc47 235 This function executes a exclusive LDR instruction for 16 bit values.
vipinranka 12:9a20164dcc47 236
vipinranka 12:9a20164dcc47 237 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 238 \return value of type uint16_t at (*ptr)
vipinranka 12:9a20164dcc47 239 */
vipinranka 12:9a20164dcc47 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
vipinranka 12:9a20164dcc47 241
vipinranka 12:9a20164dcc47 242
vipinranka 12:9a20164dcc47 243 /** \brief LDR Exclusive (32 bit)
vipinranka 12:9a20164dcc47 244
vipinranka 12:9a20164dcc47 245 This function executes a exclusive LDR instruction for 32 bit values.
vipinranka 12:9a20164dcc47 246
vipinranka 12:9a20164dcc47 247 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 248 \return value of type uint32_t at (*ptr)
vipinranka 12:9a20164dcc47 249 */
vipinranka 12:9a20164dcc47 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
vipinranka 12:9a20164dcc47 251
vipinranka 12:9a20164dcc47 252
vipinranka 12:9a20164dcc47 253 /** \brief STR Exclusive (8 bit)
vipinranka 12:9a20164dcc47 254
vipinranka 12:9a20164dcc47 255 This function executes a exclusive STR instruction for 8 bit values.
vipinranka 12:9a20164dcc47 256
vipinranka 12:9a20164dcc47 257 \param [in] value Value to store
vipinranka 12:9a20164dcc47 258 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 259 \return 0 Function succeeded
vipinranka 12:9a20164dcc47 260 \return 1 Function failed
vipinranka 12:9a20164dcc47 261 */
vipinranka 12:9a20164dcc47 262 #define __STREXB(value, ptr) __strex(value, ptr)
vipinranka 12:9a20164dcc47 263
vipinranka 12:9a20164dcc47 264
vipinranka 12:9a20164dcc47 265 /** \brief STR Exclusive (16 bit)
vipinranka 12:9a20164dcc47 266
vipinranka 12:9a20164dcc47 267 This function executes a exclusive STR instruction for 16 bit values.
vipinranka 12:9a20164dcc47 268
vipinranka 12:9a20164dcc47 269 \param [in] value Value to store
vipinranka 12:9a20164dcc47 270 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 271 \return 0 Function succeeded
vipinranka 12:9a20164dcc47 272 \return 1 Function failed
vipinranka 12:9a20164dcc47 273 */
vipinranka 12:9a20164dcc47 274 #define __STREXH(value, ptr) __strex(value, ptr)
vipinranka 12:9a20164dcc47 275
vipinranka 12:9a20164dcc47 276
vipinranka 12:9a20164dcc47 277 /** \brief STR Exclusive (32 bit)
vipinranka 12:9a20164dcc47 278
vipinranka 12:9a20164dcc47 279 This function executes a exclusive STR instruction for 32 bit values.
vipinranka 12:9a20164dcc47 280
vipinranka 12:9a20164dcc47 281 \param [in] value Value to store
vipinranka 12:9a20164dcc47 282 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 283 \return 0 Function succeeded
vipinranka 12:9a20164dcc47 284 \return 1 Function failed
vipinranka 12:9a20164dcc47 285 */
vipinranka 12:9a20164dcc47 286 #define __STREXW(value, ptr) __strex(value, ptr)
vipinranka 12:9a20164dcc47 287
vipinranka 12:9a20164dcc47 288
vipinranka 12:9a20164dcc47 289 /** \brief Remove the exclusive lock
vipinranka 12:9a20164dcc47 290
vipinranka 12:9a20164dcc47 291 This function removes the exclusive lock which is created by LDREX.
vipinranka 12:9a20164dcc47 292
vipinranka 12:9a20164dcc47 293 */
vipinranka 12:9a20164dcc47 294 #define __CLREX __clrex
vipinranka 12:9a20164dcc47 295
vipinranka 12:9a20164dcc47 296
vipinranka 12:9a20164dcc47 297 /** \brief Signed Saturate
vipinranka 12:9a20164dcc47 298
vipinranka 12:9a20164dcc47 299 This function saturates a signed value.
vipinranka 12:9a20164dcc47 300
vipinranka 12:9a20164dcc47 301 \param [in] value Value to be saturated
vipinranka 12:9a20164dcc47 302 \param [in] sat Bit position to saturate to (1..32)
vipinranka 12:9a20164dcc47 303 \return Saturated value
vipinranka 12:9a20164dcc47 304 */
vipinranka 12:9a20164dcc47 305 #define __SSAT __ssat
vipinranka 12:9a20164dcc47 306
vipinranka 12:9a20164dcc47 307
vipinranka 12:9a20164dcc47 308 /** \brief Unsigned Saturate
vipinranka 12:9a20164dcc47 309
vipinranka 12:9a20164dcc47 310 This function saturates an unsigned value.
vipinranka 12:9a20164dcc47 311
vipinranka 12:9a20164dcc47 312 \param [in] value Value to be saturated
vipinranka 12:9a20164dcc47 313 \param [in] sat Bit position to saturate to (0..31)
vipinranka 12:9a20164dcc47 314 \return Saturated value
vipinranka 12:9a20164dcc47 315 */
vipinranka 12:9a20164dcc47 316 #define __USAT __usat
vipinranka 12:9a20164dcc47 317
vipinranka 12:9a20164dcc47 318
vipinranka 12:9a20164dcc47 319 /** \brief Rotate Right with Extend (32 bit)
vipinranka 12:9a20164dcc47 320
vipinranka 12:9a20164dcc47 321 This function moves each bit of a bitstring right by one bit.
vipinranka 12:9a20164dcc47 322 The carry input is shifted in at the left end of the bitstring.
vipinranka 12:9a20164dcc47 323
vipinranka 12:9a20164dcc47 324 \param [in] value Value to rotate
vipinranka 12:9a20164dcc47 325 \return Rotated value
vipinranka 12:9a20164dcc47 326 */
vipinranka 12:9a20164dcc47 327 #ifndef __NO_EMBEDDED_ASM
vipinranka 12:9a20164dcc47 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
vipinranka 12:9a20164dcc47 329 {
vipinranka 12:9a20164dcc47 330 rrx r0, r0
vipinranka 12:9a20164dcc47 331 bx lr
vipinranka 12:9a20164dcc47 332 }
vipinranka 12:9a20164dcc47 333 #endif
vipinranka 12:9a20164dcc47 334
vipinranka 12:9a20164dcc47 335
vipinranka 12:9a20164dcc47 336 /** \brief LDRT Unprivileged (8 bit)
vipinranka 12:9a20164dcc47 337
vipinranka 12:9a20164dcc47 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
vipinranka 12:9a20164dcc47 339
vipinranka 12:9a20164dcc47 340 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 341 \return value of type uint8_t at (*ptr)
vipinranka 12:9a20164dcc47 342 */
vipinranka 12:9a20164dcc47 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
vipinranka 12:9a20164dcc47 344
vipinranka 12:9a20164dcc47 345
vipinranka 12:9a20164dcc47 346 /** \brief LDRT Unprivileged (16 bit)
vipinranka 12:9a20164dcc47 347
vipinranka 12:9a20164dcc47 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
vipinranka 12:9a20164dcc47 349
vipinranka 12:9a20164dcc47 350 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 351 \return value of type uint16_t at (*ptr)
vipinranka 12:9a20164dcc47 352 */
vipinranka 12:9a20164dcc47 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
vipinranka 12:9a20164dcc47 354
vipinranka 12:9a20164dcc47 355
vipinranka 12:9a20164dcc47 356 /** \brief LDRT Unprivileged (32 bit)
vipinranka 12:9a20164dcc47 357
vipinranka 12:9a20164dcc47 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
vipinranka 12:9a20164dcc47 359
vipinranka 12:9a20164dcc47 360 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 361 \return value of type uint32_t at (*ptr)
vipinranka 12:9a20164dcc47 362 */
vipinranka 12:9a20164dcc47 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
vipinranka 12:9a20164dcc47 364
vipinranka 12:9a20164dcc47 365
vipinranka 12:9a20164dcc47 366 /** \brief STRT Unprivileged (8 bit)
vipinranka 12:9a20164dcc47 367
vipinranka 12:9a20164dcc47 368 This function executes a Unprivileged STRT instruction for 8 bit values.
vipinranka 12:9a20164dcc47 369
vipinranka 12:9a20164dcc47 370 \param [in] value Value to store
vipinranka 12:9a20164dcc47 371 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 372 */
vipinranka 12:9a20164dcc47 373 #define __STRBT(value, ptr) __strt(value, ptr)
vipinranka 12:9a20164dcc47 374
vipinranka 12:9a20164dcc47 375
vipinranka 12:9a20164dcc47 376 /** \brief STRT Unprivileged (16 bit)
vipinranka 12:9a20164dcc47 377
vipinranka 12:9a20164dcc47 378 This function executes a Unprivileged STRT instruction for 16 bit values.
vipinranka 12:9a20164dcc47 379
vipinranka 12:9a20164dcc47 380 \param [in] value Value to store
vipinranka 12:9a20164dcc47 381 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 382 */
vipinranka 12:9a20164dcc47 383 #define __STRHT(value, ptr) __strt(value, ptr)
vipinranka 12:9a20164dcc47 384
vipinranka 12:9a20164dcc47 385
vipinranka 12:9a20164dcc47 386 /** \brief STRT Unprivileged (32 bit)
vipinranka 12:9a20164dcc47 387
vipinranka 12:9a20164dcc47 388 This function executes a Unprivileged STRT instruction for 32 bit values.
vipinranka 12:9a20164dcc47 389
vipinranka 12:9a20164dcc47 390 \param [in] value Value to store
vipinranka 12:9a20164dcc47 391 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 392 */
vipinranka 12:9a20164dcc47 393 #define __STRT(value, ptr) __strt(value, ptr)
vipinranka 12:9a20164dcc47 394
vipinranka 12:9a20164dcc47 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
vipinranka 12:9a20164dcc47 396
vipinranka 12:9a20164dcc47 397
vipinranka 12:9a20164dcc47 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
vipinranka 12:9a20164dcc47 399 /* GNU gcc specific functions */
vipinranka 12:9a20164dcc47 400
vipinranka 12:9a20164dcc47 401 /* Define macros for porting to both thumb1 and thumb2.
vipinranka 12:9a20164dcc47 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
vipinranka 12:9a20164dcc47 403 * Otherwise, use general registers, specified by constrant "r" */
vipinranka 12:9a20164dcc47 404 #if defined (__thumb__) && !defined (__thumb2__)
vipinranka 12:9a20164dcc47 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
vipinranka 12:9a20164dcc47 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
vipinranka 12:9a20164dcc47 407 #else
vipinranka 12:9a20164dcc47 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
vipinranka 12:9a20164dcc47 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
vipinranka 12:9a20164dcc47 410 #endif
vipinranka 12:9a20164dcc47 411
vipinranka 12:9a20164dcc47 412 /** \brief No Operation
vipinranka 12:9a20164dcc47 413
vipinranka 12:9a20164dcc47 414 No Operation does nothing. This instruction can be used for code alignment purposes.
vipinranka 12:9a20164dcc47 415 */
vipinranka 12:9a20164dcc47 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
vipinranka 12:9a20164dcc47 417 {
vipinranka 12:9a20164dcc47 418 __ASM volatile ("nop");
vipinranka 12:9a20164dcc47 419 }
vipinranka 12:9a20164dcc47 420
vipinranka 12:9a20164dcc47 421
vipinranka 12:9a20164dcc47 422 /** \brief Wait For Interrupt
vipinranka 12:9a20164dcc47 423
vipinranka 12:9a20164dcc47 424 Wait For Interrupt is a hint instruction that suspends execution
vipinranka 12:9a20164dcc47 425 until one of a number of events occurs.
vipinranka 12:9a20164dcc47 426 */
vipinranka 12:9a20164dcc47 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
vipinranka 12:9a20164dcc47 428 {
vipinranka 12:9a20164dcc47 429 __ASM volatile ("wfi");
vipinranka 12:9a20164dcc47 430 }
vipinranka 12:9a20164dcc47 431
vipinranka 12:9a20164dcc47 432
vipinranka 12:9a20164dcc47 433 /** \brief Wait For Event
vipinranka 12:9a20164dcc47 434
vipinranka 12:9a20164dcc47 435 Wait For Event is a hint instruction that permits the processor to enter
vipinranka 12:9a20164dcc47 436 a low-power state until one of a number of events occurs.
vipinranka 12:9a20164dcc47 437 */
vipinranka 12:9a20164dcc47 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
vipinranka 12:9a20164dcc47 439 {
vipinranka 12:9a20164dcc47 440 __ASM volatile ("wfe");
vipinranka 12:9a20164dcc47 441 }
vipinranka 12:9a20164dcc47 442
vipinranka 12:9a20164dcc47 443
vipinranka 12:9a20164dcc47 444 /** \brief Send Event
vipinranka 12:9a20164dcc47 445
vipinranka 12:9a20164dcc47 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
vipinranka 12:9a20164dcc47 447 */
vipinranka 12:9a20164dcc47 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
vipinranka 12:9a20164dcc47 449 {
vipinranka 12:9a20164dcc47 450 __ASM volatile ("sev");
vipinranka 12:9a20164dcc47 451 }
vipinranka 12:9a20164dcc47 452
vipinranka 12:9a20164dcc47 453
vipinranka 12:9a20164dcc47 454 /** \brief Instruction Synchronization Barrier
vipinranka 12:9a20164dcc47 455
vipinranka 12:9a20164dcc47 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
vipinranka 12:9a20164dcc47 457 so that all instructions following the ISB are fetched from cache or
vipinranka 12:9a20164dcc47 458 memory, after the instruction has been completed.
vipinranka 12:9a20164dcc47 459 */
vipinranka 12:9a20164dcc47 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
vipinranka 12:9a20164dcc47 461 {
vipinranka 12:9a20164dcc47 462 __ASM volatile ("isb 0xF":::"memory");
vipinranka 12:9a20164dcc47 463 }
vipinranka 12:9a20164dcc47 464
vipinranka 12:9a20164dcc47 465
vipinranka 12:9a20164dcc47 466 /** \brief Data Synchronization Barrier
vipinranka 12:9a20164dcc47 467
vipinranka 12:9a20164dcc47 468 This function acts as a special kind of Data Memory Barrier.
vipinranka 12:9a20164dcc47 469 It completes when all explicit memory accesses before this instruction complete.
vipinranka 12:9a20164dcc47 470 */
vipinranka 12:9a20164dcc47 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
vipinranka 12:9a20164dcc47 472 {
vipinranka 12:9a20164dcc47 473 __ASM volatile ("dsb 0xF":::"memory");
vipinranka 12:9a20164dcc47 474 }
vipinranka 12:9a20164dcc47 475
vipinranka 12:9a20164dcc47 476
vipinranka 12:9a20164dcc47 477 /** \brief Data Memory Barrier
vipinranka 12:9a20164dcc47 478
vipinranka 12:9a20164dcc47 479 This function ensures the apparent order of the explicit memory operations before
vipinranka 12:9a20164dcc47 480 and after the instruction, without ensuring their completion.
vipinranka 12:9a20164dcc47 481 */
vipinranka 12:9a20164dcc47 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
vipinranka 12:9a20164dcc47 483 {
vipinranka 12:9a20164dcc47 484 __ASM volatile ("dmb 0xF":::"memory");
vipinranka 12:9a20164dcc47 485 }
vipinranka 12:9a20164dcc47 486
vipinranka 12:9a20164dcc47 487
vipinranka 12:9a20164dcc47 488 /** \brief Reverse byte order (32 bit)
vipinranka 12:9a20164dcc47 489
vipinranka 12:9a20164dcc47 490 This function reverses the byte order in integer value.
vipinranka 12:9a20164dcc47 491
vipinranka 12:9a20164dcc47 492 \param [in] value Value to reverse
vipinranka 12:9a20164dcc47 493 \return Reversed value
vipinranka 12:9a20164dcc47 494 */
vipinranka 12:9a20164dcc47 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
vipinranka 12:9a20164dcc47 496 {
vipinranka 12:9a20164dcc47 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
vipinranka 12:9a20164dcc47 498 return __builtin_bswap32(value);
vipinranka 12:9a20164dcc47 499 #else
vipinranka 12:9a20164dcc47 500 uint32_t result;
vipinranka 12:9a20164dcc47 501
vipinranka 12:9a20164dcc47 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
vipinranka 12:9a20164dcc47 503 return(result);
vipinranka 12:9a20164dcc47 504 #endif
vipinranka 12:9a20164dcc47 505 }
vipinranka 12:9a20164dcc47 506
vipinranka 12:9a20164dcc47 507
vipinranka 12:9a20164dcc47 508 /** \brief Reverse byte order (16 bit)
vipinranka 12:9a20164dcc47 509
vipinranka 12:9a20164dcc47 510 This function reverses the byte order in two unsigned short values.
vipinranka 12:9a20164dcc47 511
vipinranka 12:9a20164dcc47 512 \param [in] value Value to reverse
vipinranka 12:9a20164dcc47 513 \return Reversed value
vipinranka 12:9a20164dcc47 514 */
vipinranka 12:9a20164dcc47 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
vipinranka 12:9a20164dcc47 516 {
vipinranka 12:9a20164dcc47 517 uint32_t result;
vipinranka 12:9a20164dcc47 518
vipinranka 12:9a20164dcc47 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
vipinranka 12:9a20164dcc47 520 return(result);
vipinranka 12:9a20164dcc47 521 }
vipinranka 12:9a20164dcc47 522
vipinranka 12:9a20164dcc47 523
vipinranka 12:9a20164dcc47 524 /** \brief Reverse byte order in signed short value
vipinranka 12:9a20164dcc47 525
vipinranka 12:9a20164dcc47 526 This function reverses the byte order in a signed short value with sign extension to integer.
vipinranka 12:9a20164dcc47 527
vipinranka 12:9a20164dcc47 528 \param [in] value Value to reverse
vipinranka 12:9a20164dcc47 529 \return Reversed value
vipinranka 12:9a20164dcc47 530 */
vipinranka 12:9a20164dcc47 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
vipinranka 12:9a20164dcc47 532 {
vipinranka 12:9a20164dcc47 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
vipinranka 12:9a20164dcc47 534 return (short)__builtin_bswap16(value);
vipinranka 12:9a20164dcc47 535 #else
vipinranka 12:9a20164dcc47 536 uint32_t result;
vipinranka 12:9a20164dcc47 537
vipinranka 12:9a20164dcc47 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
vipinranka 12:9a20164dcc47 539 return(result);
vipinranka 12:9a20164dcc47 540 #endif
vipinranka 12:9a20164dcc47 541 }
vipinranka 12:9a20164dcc47 542
vipinranka 12:9a20164dcc47 543
vipinranka 12:9a20164dcc47 544 /** \brief Rotate Right in unsigned value (32 bit)
vipinranka 12:9a20164dcc47 545
vipinranka 12:9a20164dcc47 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
vipinranka 12:9a20164dcc47 547
vipinranka 12:9a20164dcc47 548 \param [in] value Value to rotate
vipinranka 12:9a20164dcc47 549 \param [in] value Number of Bits to rotate
vipinranka 12:9a20164dcc47 550 \return Rotated value
vipinranka 12:9a20164dcc47 551 */
vipinranka 12:9a20164dcc47 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
vipinranka 12:9a20164dcc47 553 {
vipinranka 12:9a20164dcc47 554 return (op1 >> op2) | (op1 << (32 - op2));
vipinranka 12:9a20164dcc47 555 }
vipinranka 12:9a20164dcc47 556
vipinranka 12:9a20164dcc47 557
vipinranka 12:9a20164dcc47 558 /** \brief Breakpoint
vipinranka 12:9a20164dcc47 559
vipinranka 12:9a20164dcc47 560 This function causes the processor to enter Debug state.
vipinranka 12:9a20164dcc47 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
vipinranka 12:9a20164dcc47 562
vipinranka 12:9a20164dcc47 563 \param [in] value is ignored by the processor.
vipinranka 12:9a20164dcc47 564 If required, a debugger can use it to store additional information about the breakpoint.
vipinranka 12:9a20164dcc47 565 */
vipinranka 12:9a20164dcc47 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
vipinranka 12:9a20164dcc47 567
vipinranka 12:9a20164dcc47 568
vipinranka 12:9a20164dcc47 569 /** \brief Reverse bit order of value
vipinranka 12:9a20164dcc47 570
vipinranka 12:9a20164dcc47 571 This function reverses the bit order of the given value.
vipinranka 12:9a20164dcc47 572
vipinranka 12:9a20164dcc47 573 \param [in] value Value to reverse
vipinranka 12:9a20164dcc47 574 \return Reversed value
vipinranka 12:9a20164dcc47 575 */
vipinranka 12:9a20164dcc47 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
vipinranka 12:9a20164dcc47 577 {
vipinranka 12:9a20164dcc47 578 uint32_t result;
vipinranka 12:9a20164dcc47 579
vipinranka 12:9a20164dcc47 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
vipinranka 12:9a20164dcc47 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
vipinranka 12:9a20164dcc47 582 #else
vipinranka 12:9a20164dcc47 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
vipinranka 12:9a20164dcc47 584
vipinranka 12:9a20164dcc47 585 result = value; // r will be reversed bits of v; first get LSB of v
vipinranka 12:9a20164dcc47 586 for (value >>= 1; value; value >>= 1)
vipinranka 12:9a20164dcc47 587 {
vipinranka 12:9a20164dcc47 588 result <<= 1;
vipinranka 12:9a20164dcc47 589 result |= value & 1;
vipinranka 12:9a20164dcc47 590 s--;
vipinranka 12:9a20164dcc47 591 }
vipinranka 12:9a20164dcc47 592 result <<= s; // shift when v's highest bits are zero
vipinranka 12:9a20164dcc47 593 #endif
vipinranka 12:9a20164dcc47 594 return(result);
vipinranka 12:9a20164dcc47 595 }
vipinranka 12:9a20164dcc47 596
vipinranka 12:9a20164dcc47 597
vipinranka 12:9a20164dcc47 598 /** \brief Count leading zeros
vipinranka 12:9a20164dcc47 599
vipinranka 12:9a20164dcc47 600 This function counts the number of leading zeros of a data value.
vipinranka 12:9a20164dcc47 601
vipinranka 12:9a20164dcc47 602 \param [in] value Value to count the leading zeros
vipinranka 12:9a20164dcc47 603 \return number of leading zeros in value
vipinranka 12:9a20164dcc47 604 */
vipinranka 12:9a20164dcc47 605 #define __CLZ __builtin_clz
vipinranka 12:9a20164dcc47 606
vipinranka 12:9a20164dcc47 607
vipinranka 12:9a20164dcc47 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
vipinranka 12:9a20164dcc47 609
vipinranka 12:9a20164dcc47 610 /** \brief LDR Exclusive (8 bit)
vipinranka 12:9a20164dcc47 611
vipinranka 12:9a20164dcc47 612 This function executes a exclusive LDR instruction for 8 bit value.
vipinranka 12:9a20164dcc47 613
vipinranka 12:9a20164dcc47 614 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 615 \return value of type uint8_t at (*ptr)
vipinranka 12:9a20164dcc47 616 */
vipinranka 12:9a20164dcc47 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
vipinranka 12:9a20164dcc47 618 {
vipinranka 12:9a20164dcc47 619 uint32_t result;
vipinranka 12:9a20164dcc47 620
vipinranka 12:9a20164dcc47 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
vipinranka 12:9a20164dcc47 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
vipinranka 12:9a20164dcc47 623 #else
vipinranka 12:9a20164dcc47 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
vipinranka 12:9a20164dcc47 625 accepted by assembler. So has to use following less efficient pattern.
vipinranka 12:9a20164dcc47 626 */
vipinranka 12:9a20164dcc47 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
vipinranka 12:9a20164dcc47 628 #endif
vipinranka 12:9a20164dcc47 629 return ((uint8_t) result); /* Add explicit type cast here */
vipinranka 12:9a20164dcc47 630 }
vipinranka 12:9a20164dcc47 631
vipinranka 12:9a20164dcc47 632
vipinranka 12:9a20164dcc47 633 /** \brief LDR Exclusive (16 bit)
vipinranka 12:9a20164dcc47 634
vipinranka 12:9a20164dcc47 635 This function executes a exclusive LDR instruction for 16 bit values.
vipinranka 12:9a20164dcc47 636
vipinranka 12:9a20164dcc47 637 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 638 \return value of type uint16_t at (*ptr)
vipinranka 12:9a20164dcc47 639 */
vipinranka 12:9a20164dcc47 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
vipinranka 12:9a20164dcc47 641 {
vipinranka 12:9a20164dcc47 642 uint32_t result;
vipinranka 12:9a20164dcc47 643
vipinranka 12:9a20164dcc47 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
vipinranka 12:9a20164dcc47 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
vipinranka 12:9a20164dcc47 646 #else
vipinranka 12:9a20164dcc47 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
vipinranka 12:9a20164dcc47 648 accepted by assembler. So has to use following less efficient pattern.
vipinranka 12:9a20164dcc47 649 */
vipinranka 12:9a20164dcc47 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
vipinranka 12:9a20164dcc47 651 #endif
vipinranka 12:9a20164dcc47 652 return ((uint16_t) result); /* Add explicit type cast here */
vipinranka 12:9a20164dcc47 653 }
vipinranka 12:9a20164dcc47 654
vipinranka 12:9a20164dcc47 655
vipinranka 12:9a20164dcc47 656 /** \brief LDR Exclusive (32 bit)
vipinranka 12:9a20164dcc47 657
vipinranka 12:9a20164dcc47 658 This function executes a exclusive LDR instruction for 32 bit values.
vipinranka 12:9a20164dcc47 659
vipinranka 12:9a20164dcc47 660 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 661 \return value of type uint32_t at (*ptr)
vipinranka 12:9a20164dcc47 662 */
vipinranka 12:9a20164dcc47 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
vipinranka 12:9a20164dcc47 664 {
vipinranka 12:9a20164dcc47 665 uint32_t result;
vipinranka 12:9a20164dcc47 666
vipinranka 12:9a20164dcc47 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
vipinranka 12:9a20164dcc47 668 return(result);
vipinranka 12:9a20164dcc47 669 }
vipinranka 12:9a20164dcc47 670
vipinranka 12:9a20164dcc47 671
vipinranka 12:9a20164dcc47 672 /** \brief STR Exclusive (8 bit)
vipinranka 12:9a20164dcc47 673
vipinranka 12:9a20164dcc47 674 This function executes a exclusive STR instruction for 8 bit values.
vipinranka 12:9a20164dcc47 675
vipinranka 12:9a20164dcc47 676 \param [in] value Value to store
vipinranka 12:9a20164dcc47 677 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 678 \return 0 Function succeeded
vipinranka 12:9a20164dcc47 679 \return 1 Function failed
vipinranka 12:9a20164dcc47 680 */
vipinranka 12:9a20164dcc47 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
vipinranka 12:9a20164dcc47 682 {
vipinranka 12:9a20164dcc47 683 uint32_t result;
vipinranka 12:9a20164dcc47 684
vipinranka 12:9a20164dcc47 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
vipinranka 12:9a20164dcc47 686 return(result);
vipinranka 12:9a20164dcc47 687 }
vipinranka 12:9a20164dcc47 688
vipinranka 12:9a20164dcc47 689
vipinranka 12:9a20164dcc47 690 /** \brief STR Exclusive (16 bit)
vipinranka 12:9a20164dcc47 691
vipinranka 12:9a20164dcc47 692 This function executes a exclusive STR instruction for 16 bit values.
vipinranka 12:9a20164dcc47 693
vipinranka 12:9a20164dcc47 694 \param [in] value Value to store
vipinranka 12:9a20164dcc47 695 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 696 \return 0 Function succeeded
vipinranka 12:9a20164dcc47 697 \return 1 Function failed
vipinranka 12:9a20164dcc47 698 */
vipinranka 12:9a20164dcc47 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
vipinranka 12:9a20164dcc47 700 {
vipinranka 12:9a20164dcc47 701 uint32_t result;
vipinranka 12:9a20164dcc47 702
vipinranka 12:9a20164dcc47 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
vipinranka 12:9a20164dcc47 704 return(result);
vipinranka 12:9a20164dcc47 705 }
vipinranka 12:9a20164dcc47 706
vipinranka 12:9a20164dcc47 707
vipinranka 12:9a20164dcc47 708 /** \brief STR Exclusive (32 bit)
vipinranka 12:9a20164dcc47 709
vipinranka 12:9a20164dcc47 710 This function executes a exclusive STR instruction for 32 bit values.
vipinranka 12:9a20164dcc47 711
vipinranka 12:9a20164dcc47 712 \param [in] value Value to store
vipinranka 12:9a20164dcc47 713 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 714 \return 0 Function succeeded
vipinranka 12:9a20164dcc47 715 \return 1 Function failed
vipinranka 12:9a20164dcc47 716 */
vipinranka 12:9a20164dcc47 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
vipinranka 12:9a20164dcc47 718 {
vipinranka 12:9a20164dcc47 719 uint32_t result;
vipinranka 12:9a20164dcc47 720
vipinranka 12:9a20164dcc47 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
vipinranka 12:9a20164dcc47 722 return(result);
vipinranka 12:9a20164dcc47 723 }
vipinranka 12:9a20164dcc47 724
vipinranka 12:9a20164dcc47 725
vipinranka 12:9a20164dcc47 726 /** \brief Remove the exclusive lock
vipinranka 12:9a20164dcc47 727
vipinranka 12:9a20164dcc47 728 This function removes the exclusive lock which is created by LDREX.
vipinranka 12:9a20164dcc47 729
vipinranka 12:9a20164dcc47 730 */
vipinranka 12:9a20164dcc47 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
vipinranka 12:9a20164dcc47 732 {
vipinranka 12:9a20164dcc47 733 __ASM volatile ("clrex" ::: "memory");
vipinranka 12:9a20164dcc47 734 }
vipinranka 12:9a20164dcc47 735
vipinranka 12:9a20164dcc47 736
vipinranka 12:9a20164dcc47 737 /** \brief Signed Saturate
vipinranka 12:9a20164dcc47 738
vipinranka 12:9a20164dcc47 739 This function saturates a signed value.
vipinranka 12:9a20164dcc47 740
vipinranka 12:9a20164dcc47 741 \param [in] value Value to be saturated
vipinranka 12:9a20164dcc47 742 \param [in] sat Bit position to saturate to (1..32)
vipinranka 12:9a20164dcc47 743 \return Saturated value
vipinranka 12:9a20164dcc47 744 */
vipinranka 12:9a20164dcc47 745 #define __SSAT(ARG1,ARG2) \
vipinranka 12:9a20164dcc47 746 ({ \
vipinranka 12:9a20164dcc47 747 uint32_t __RES, __ARG1 = (ARG1); \
vipinranka 12:9a20164dcc47 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
vipinranka 12:9a20164dcc47 749 __RES; \
vipinranka 12:9a20164dcc47 750 })
vipinranka 12:9a20164dcc47 751
vipinranka 12:9a20164dcc47 752
vipinranka 12:9a20164dcc47 753 /** \brief Unsigned Saturate
vipinranka 12:9a20164dcc47 754
vipinranka 12:9a20164dcc47 755 This function saturates an unsigned value.
vipinranka 12:9a20164dcc47 756
vipinranka 12:9a20164dcc47 757 \param [in] value Value to be saturated
vipinranka 12:9a20164dcc47 758 \param [in] sat Bit position to saturate to (0..31)
vipinranka 12:9a20164dcc47 759 \return Saturated value
vipinranka 12:9a20164dcc47 760 */
vipinranka 12:9a20164dcc47 761 #define __USAT(ARG1,ARG2) \
vipinranka 12:9a20164dcc47 762 ({ \
vipinranka 12:9a20164dcc47 763 uint32_t __RES, __ARG1 = (ARG1); \
vipinranka 12:9a20164dcc47 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
vipinranka 12:9a20164dcc47 765 __RES; \
vipinranka 12:9a20164dcc47 766 })
vipinranka 12:9a20164dcc47 767
vipinranka 12:9a20164dcc47 768
vipinranka 12:9a20164dcc47 769 /** \brief Rotate Right with Extend (32 bit)
vipinranka 12:9a20164dcc47 770
vipinranka 12:9a20164dcc47 771 This function moves each bit of a bitstring right by one bit.
vipinranka 12:9a20164dcc47 772 The carry input is shifted in at the left end of the bitstring.
vipinranka 12:9a20164dcc47 773
vipinranka 12:9a20164dcc47 774 \param [in] value Value to rotate
vipinranka 12:9a20164dcc47 775 \return Rotated value
vipinranka 12:9a20164dcc47 776 */
vipinranka 12:9a20164dcc47 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
vipinranka 12:9a20164dcc47 778 {
vipinranka 12:9a20164dcc47 779 uint32_t result;
vipinranka 12:9a20164dcc47 780
vipinranka 12:9a20164dcc47 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
vipinranka 12:9a20164dcc47 782 return(result);
vipinranka 12:9a20164dcc47 783 }
vipinranka 12:9a20164dcc47 784
vipinranka 12:9a20164dcc47 785
vipinranka 12:9a20164dcc47 786 /** \brief LDRT Unprivileged (8 bit)
vipinranka 12:9a20164dcc47 787
vipinranka 12:9a20164dcc47 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
vipinranka 12:9a20164dcc47 789
vipinranka 12:9a20164dcc47 790 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 791 \return value of type uint8_t at (*ptr)
vipinranka 12:9a20164dcc47 792 */
vipinranka 12:9a20164dcc47 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
vipinranka 12:9a20164dcc47 794 {
vipinranka 12:9a20164dcc47 795 uint32_t result;
vipinranka 12:9a20164dcc47 796
vipinranka 12:9a20164dcc47 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
vipinranka 12:9a20164dcc47 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
vipinranka 12:9a20164dcc47 799 #else
vipinranka 12:9a20164dcc47 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
vipinranka 12:9a20164dcc47 801 accepted by assembler. So has to use following less efficient pattern.
vipinranka 12:9a20164dcc47 802 */
vipinranka 12:9a20164dcc47 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
vipinranka 12:9a20164dcc47 804 #endif
vipinranka 12:9a20164dcc47 805 return ((uint8_t) result); /* Add explicit type cast here */
vipinranka 12:9a20164dcc47 806 }
vipinranka 12:9a20164dcc47 807
vipinranka 12:9a20164dcc47 808
vipinranka 12:9a20164dcc47 809 /** \brief LDRT Unprivileged (16 bit)
vipinranka 12:9a20164dcc47 810
vipinranka 12:9a20164dcc47 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
vipinranka 12:9a20164dcc47 812
vipinranka 12:9a20164dcc47 813 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 814 \return value of type uint16_t at (*ptr)
vipinranka 12:9a20164dcc47 815 */
vipinranka 12:9a20164dcc47 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
vipinranka 12:9a20164dcc47 817 {
vipinranka 12:9a20164dcc47 818 uint32_t result;
vipinranka 12:9a20164dcc47 819
vipinranka 12:9a20164dcc47 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
vipinranka 12:9a20164dcc47 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
vipinranka 12:9a20164dcc47 822 #else
vipinranka 12:9a20164dcc47 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
vipinranka 12:9a20164dcc47 824 accepted by assembler. So has to use following less efficient pattern.
vipinranka 12:9a20164dcc47 825 */
vipinranka 12:9a20164dcc47 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
vipinranka 12:9a20164dcc47 827 #endif
vipinranka 12:9a20164dcc47 828 return ((uint16_t) result); /* Add explicit type cast here */
vipinranka 12:9a20164dcc47 829 }
vipinranka 12:9a20164dcc47 830
vipinranka 12:9a20164dcc47 831
vipinranka 12:9a20164dcc47 832 /** \brief LDRT Unprivileged (32 bit)
vipinranka 12:9a20164dcc47 833
vipinranka 12:9a20164dcc47 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
vipinranka 12:9a20164dcc47 835
vipinranka 12:9a20164dcc47 836 \param [in] ptr Pointer to data
vipinranka 12:9a20164dcc47 837 \return value of type uint32_t at (*ptr)
vipinranka 12:9a20164dcc47 838 */
vipinranka 12:9a20164dcc47 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
vipinranka 12:9a20164dcc47 840 {
vipinranka 12:9a20164dcc47 841 uint32_t result;
vipinranka 12:9a20164dcc47 842
vipinranka 12:9a20164dcc47 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
vipinranka 12:9a20164dcc47 844 return(result);
vipinranka 12:9a20164dcc47 845 }
vipinranka 12:9a20164dcc47 846
vipinranka 12:9a20164dcc47 847
vipinranka 12:9a20164dcc47 848 /** \brief STRT Unprivileged (8 bit)
vipinranka 12:9a20164dcc47 849
vipinranka 12:9a20164dcc47 850 This function executes a Unprivileged STRT instruction for 8 bit values.
vipinranka 12:9a20164dcc47 851
vipinranka 12:9a20164dcc47 852 \param [in] value Value to store
vipinranka 12:9a20164dcc47 853 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 854 */
vipinranka 12:9a20164dcc47 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
vipinranka 12:9a20164dcc47 856 {
vipinranka 12:9a20164dcc47 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
vipinranka 12:9a20164dcc47 858 }
vipinranka 12:9a20164dcc47 859
vipinranka 12:9a20164dcc47 860
vipinranka 12:9a20164dcc47 861 /** \brief STRT Unprivileged (16 bit)
vipinranka 12:9a20164dcc47 862
vipinranka 12:9a20164dcc47 863 This function executes a Unprivileged STRT instruction for 16 bit values.
vipinranka 12:9a20164dcc47 864
vipinranka 12:9a20164dcc47 865 \param [in] value Value to store
vipinranka 12:9a20164dcc47 866 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 867 */
vipinranka 12:9a20164dcc47 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
vipinranka 12:9a20164dcc47 869 {
vipinranka 12:9a20164dcc47 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
vipinranka 12:9a20164dcc47 871 }
vipinranka 12:9a20164dcc47 872
vipinranka 12:9a20164dcc47 873
vipinranka 12:9a20164dcc47 874 /** \brief STRT Unprivileged (32 bit)
vipinranka 12:9a20164dcc47 875
vipinranka 12:9a20164dcc47 876 This function executes a Unprivileged STRT instruction for 32 bit values.
vipinranka 12:9a20164dcc47 877
vipinranka 12:9a20164dcc47 878 \param [in] value Value to store
vipinranka 12:9a20164dcc47 879 \param [in] ptr Pointer to location
vipinranka 12:9a20164dcc47 880 */
vipinranka 12:9a20164dcc47 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
vipinranka 12:9a20164dcc47 882 {
vipinranka 12:9a20164dcc47 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
vipinranka 12:9a20164dcc47 884 }
vipinranka 12:9a20164dcc47 885
vipinranka 12:9a20164dcc47 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
vipinranka 12:9a20164dcc47 887
vipinranka 12:9a20164dcc47 888
vipinranka 12:9a20164dcc47 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
vipinranka 12:9a20164dcc47 890 /* IAR iccarm specific functions */
vipinranka 12:9a20164dcc47 891 #include <cmsis_iar.h>
vipinranka 12:9a20164dcc47 892
vipinranka 12:9a20164dcc47 893
vipinranka 12:9a20164dcc47 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
vipinranka 12:9a20164dcc47 895 /* TI CCS specific functions */
vipinranka 12:9a20164dcc47 896 #include <cmsis_ccs.h>
vipinranka 12:9a20164dcc47 897
vipinranka 12:9a20164dcc47 898
vipinranka 12:9a20164dcc47 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
vipinranka 12:9a20164dcc47 900 /* TASKING carm specific functions */
vipinranka 12:9a20164dcc47 901 /*
vipinranka 12:9a20164dcc47 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
vipinranka 12:9a20164dcc47 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
vipinranka 12:9a20164dcc47 904 * Including the CMSIS ones.
vipinranka 12:9a20164dcc47 905 */
vipinranka 12:9a20164dcc47 906
vipinranka 12:9a20164dcc47 907
vipinranka 12:9a20164dcc47 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
vipinranka 12:9a20164dcc47 909 /* Cosmic specific functions */
vipinranka 12:9a20164dcc47 910 #include <cmsis_csm.h>
vipinranka 12:9a20164dcc47 911
vipinranka 12:9a20164dcc47 912 #endif
vipinranka 12:9a20164dcc47 913
vipinranka 12:9a20164dcc47 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
vipinranka 12:9a20164dcc47 915
vipinranka 12:9a20164dcc47 916 #endif /* __CORE_CMINSTR_H */