MGAS_GR_Peach - This is the final version of Mini Gateway for Aut…

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This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies: GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/cmsis/core_cm7.h@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:: vipinranka
Date:: Wed Jan 11 11:41:30 2017 +0000
Revision:: 12:9a20164dcc47

This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

User	Revision	Line number	New contents of line
vipinranka	12:9a20164dcc47	1	/************************************************************************//
vipinranka	12:9a20164dcc47	2	* @file core_cm7.h
vipinranka	12:9a20164dcc47	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
vipinranka	12:9a20164dcc47	4	* @version V4.10
vipinranka	12:9a20164dcc47	5	* @date 18. March 2015
vipinranka	12:9a20164dcc47	6	*
vipinranka	12:9a20164dcc47	7	* @note
vipinranka	12:9a20164dcc47	8	*
vipinranka	12:9a20164dcc47	9	******************************************************************************/
vipinranka	12:9a20164dcc47	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
vipinranka	12:9a20164dcc47	11
vipinranka	12:9a20164dcc47	12	All rights reserved.
vipinranka	12:9a20164dcc47	13	Redistribution and use in source and binary forms, with or without
vipinranka	12:9a20164dcc47	14	modification, are permitted provided that the following conditions are met:
vipinranka	12:9a20164dcc47	15	- Redistributions of source code must retain the above copyright
vipinranka	12:9a20164dcc47	16	notice, this list of conditions and the following disclaimer.
vipinranka	12:9a20164dcc47	17	- Redistributions in binary form must reproduce the above copyright
vipinranka	12:9a20164dcc47	18	notice, this list of conditions and the following disclaimer in the
vipinranka	12:9a20164dcc47	19	documentation and/or other materials provided with the distribution.
vipinranka	12:9a20164dcc47	20	- Neither the name of ARM nor the names of its contributors may be used
vipinranka	12:9a20164dcc47	21	to endorse or promote products derived from this software without
vipinranka	12:9a20164dcc47	22	specific prior written permission.
vipinranka	12:9a20164dcc47	23	*
vipinranka	12:9a20164dcc47	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vipinranka	12:9a20164dcc47	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vipinranka	12:9a20164dcc47	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vipinranka	12:9a20164dcc47	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vipinranka	12:9a20164dcc47	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vipinranka	12:9a20164dcc47	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vipinranka	12:9a20164dcc47	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vipinranka	12:9a20164dcc47	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vipinranka	12:9a20164dcc47	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vipinranka	12:9a20164dcc47	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vipinranka	12:9a20164dcc47	34	POSSIBILITY OF SUCH DAMAGE.
vipinranka	12:9a20164dcc47	35	---------------------------------------------------------------------------*/
vipinranka	12:9a20164dcc47	36
vipinranka	12:9a20164dcc47	37
vipinranka	12:9a20164dcc47	38	#if defined ( __ICCARM__ )
vipinranka	12:9a20164dcc47	39	#pragma system_include /* treat file as system include file for MISRA check */
vipinranka	12:9a20164dcc47	40	#endif
vipinranka	12:9a20164dcc47	41
vipinranka	12:9a20164dcc47	42	#ifndef __CORE_CM7_H_GENERIC
vipinranka	12:9a20164dcc47	43	#define __CORE_CM7_H_GENERIC
vipinranka	12:9a20164dcc47	44
vipinranka	12:9a20164dcc47	45	#ifdef __cplusplus
vipinranka	12:9a20164dcc47	46	extern "C" {
vipinranka	12:9a20164dcc47	47	#endif
vipinranka	12:9a20164dcc47	48
vipinranka	12:9a20164dcc47	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
vipinranka	12:9a20164dcc47	50	CMSIS violates the following MISRA-C:2004 rules:
vipinranka	12:9a20164dcc47	51
vipinranka	12:9a20164dcc47	52	\li Required Rule 8.5, object/function definition in header file.<br>
vipinranka	12:9a20164dcc47	53	Function definitions in header files are used to allow 'inlining'.
vipinranka	12:9a20164dcc47	54
vipinranka	12:9a20164dcc47	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
vipinranka	12:9a20164dcc47	56	Unions are used for effective representation of core registers.
vipinranka	12:9a20164dcc47	57
vipinranka	12:9a20164dcc47	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
vipinranka	12:9a20164dcc47	59	Function-like macros are used to allow more efficient code.
vipinranka	12:9a20164dcc47	60	*/
vipinranka	12:9a20164dcc47	61
vipinranka	12:9a20164dcc47	62
vipinranka	12:9a20164dcc47	63	/*******************************************************************************
vipinranka	12:9a20164dcc47	64	* CMSIS definitions
vipinranka	12:9a20164dcc47	65	******************************************************************************/
vipinranka	12:9a20164dcc47	66	/** \ingroup Cortex_M7
vipinranka	12:9a20164dcc47	67	@{
vipinranka	12:9a20164dcc47	68	*/
vipinranka	12:9a20164dcc47	69
vipinranka	12:9a20164dcc47	70	/* CMSIS CM7 definitions */
vipinranka	12:9a20164dcc47	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
vipinranka	12:9a20164dcc47	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
vipinranka	12:9a20164dcc47	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
vipinranka	12:9a20164dcc47	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
vipinranka	12:9a20164dcc47	75
vipinranka	12:9a20164dcc47	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
vipinranka	12:9a20164dcc47	77
vipinranka	12:9a20164dcc47	78
vipinranka	12:9a20164dcc47	79	#if defined ( __CC_ARM )
vipinranka	12:9a20164dcc47	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
vipinranka	12:9a20164dcc47	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
vipinranka	12:9a20164dcc47	82	#define __STATIC_INLINE static __inline
vipinranka	12:9a20164dcc47	83
vipinranka	12:9a20164dcc47	84	#elif defined ( __GNUC__ )
vipinranka	12:9a20164dcc47	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
vipinranka	12:9a20164dcc47	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
vipinranka	12:9a20164dcc47	87	#define __STATIC_INLINE static inline
vipinranka	12:9a20164dcc47	88
vipinranka	12:9a20164dcc47	89	#elif defined ( __ICCARM__ )
vipinranka	12:9a20164dcc47	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
vipinranka	12:9a20164dcc47	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
vipinranka	12:9a20164dcc47	92	#define __STATIC_INLINE static inline
vipinranka	12:9a20164dcc47	93
vipinranka	12:9a20164dcc47	94	#elif defined ( __TMS470__ )
vipinranka	12:9a20164dcc47	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
vipinranka	12:9a20164dcc47	96	#define __STATIC_INLINE static inline
vipinranka	12:9a20164dcc47	97
vipinranka	12:9a20164dcc47	98	#elif defined ( __TASKING__ )
vipinranka	12:9a20164dcc47	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
vipinranka	12:9a20164dcc47	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
vipinranka	12:9a20164dcc47	101	#define __STATIC_INLINE static inline
vipinranka	12:9a20164dcc47	102
vipinranka	12:9a20164dcc47	103	#elif defined ( __CSMC__ )
vipinranka	12:9a20164dcc47	104	#define __packed
vipinranka	12:9a20164dcc47	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
vipinranka	12:9a20164dcc47	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
vipinranka	12:9a20164dcc47	107	#define __STATIC_INLINE static inline
vipinranka	12:9a20164dcc47	108
vipinranka	12:9a20164dcc47	109	#endif
vipinranka	12:9a20164dcc47	110
vipinranka	12:9a20164dcc47	111	/** __FPU_USED indicates whether an FPU is used or not.
vipinranka	12:9a20164dcc47	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
vipinranka	12:9a20164dcc47	113	*/
vipinranka	12:9a20164dcc47	114	#if defined ( __CC_ARM )
vipinranka	12:9a20164dcc47	115	#if defined __TARGET_FPU_VFP
vipinranka	12:9a20164dcc47	116	#if (__FPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	117	#define __FPU_USED 1
vipinranka	12:9a20164dcc47	118	#else
vipinranka	12:9a20164dcc47	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka	12:9a20164dcc47	120	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	121	#endif
vipinranka	12:9a20164dcc47	122	#else
vipinranka	12:9a20164dcc47	123	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	124	#endif
vipinranka	12:9a20164dcc47	125
vipinranka	12:9a20164dcc47	126	#elif defined ( __GNUC__ )
vipinranka	12:9a20164dcc47	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
vipinranka	12:9a20164dcc47	128	#if (__FPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	129	#define __FPU_USED 1
vipinranka	12:9a20164dcc47	130	#else
vipinranka	12:9a20164dcc47	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka	12:9a20164dcc47	132	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	133	#endif
vipinranka	12:9a20164dcc47	134	#else
vipinranka	12:9a20164dcc47	135	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	136	#endif
vipinranka	12:9a20164dcc47	137
vipinranka	12:9a20164dcc47	138	#elif defined ( __ICCARM__ )
vipinranka	12:9a20164dcc47	139	#if defined __ARMVFP__
vipinranka	12:9a20164dcc47	140	#if (__FPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	141	#define __FPU_USED 1
vipinranka	12:9a20164dcc47	142	#else
vipinranka	12:9a20164dcc47	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka	12:9a20164dcc47	144	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	145	#endif
vipinranka	12:9a20164dcc47	146	#else
vipinranka	12:9a20164dcc47	147	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	148	#endif
vipinranka	12:9a20164dcc47	149
vipinranka	12:9a20164dcc47	150	#elif defined ( __TMS470__ )
vipinranka	12:9a20164dcc47	151	#if defined __TI_VFP_SUPPORT__
vipinranka	12:9a20164dcc47	152	#if (__FPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	153	#define __FPU_USED 1
vipinranka	12:9a20164dcc47	154	#else
vipinranka	12:9a20164dcc47	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka	12:9a20164dcc47	156	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	157	#endif
vipinranka	12:9a20164dcc47	158	#else
vipinranka	12:9a20164dcc47	159	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	160	#endif
vipinranka	12:9a20164dcc47	161
vipinranka	12:9a20164dcc47	162	#elif defined ( __TASKING__ )
vipinranka	12:9a20164dcc47	163	#if defined __FPU_VFP__
vipinranka	12:9a20164dcc47	164	#if (__FPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	165	#define __FPU_USED 1
vipinranka	12:9a20164dcc47	166	#else
vipinranka	12:9a20164dcc47	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka	12:9a20164dcc47	168	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	169	#endif
vipinranka	12:9a20164dcc47	170	#else
vipinranka	12:9a20164dcc47	171	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	172	#endif
vipinranka	12:9a20164dcc47	173
vipinranka	12:9a20164dcc47	174	#elif defined ( __CSMC__ ) /* Cosmic */
vipinranka	12:9a20164dcc47	175	#if ( __CSMC__ & 0x400) // FPU present for parser
vipinranka	12:9a20164dcc47	176	#if (__FPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	177	#define __FPU_USED 1
vipinranka	12:9a20164dcc47	178	#else
vipinranka	12:9a20164dcc47	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka	12:9a20164dcc47	180	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	181	#endif
vipinranka	12:9a20164dcc47	182	#else
vipinranka	12:9a20164dcc47	183	#define __FPU_USED 0
vipinranka	12:9a20164dcc47	184	#endif
vipinranka	12:9a20164dcc47	185	#endif
vipinranka	12:9a20164dcc47	186
vipinranka	12:9a20164dcc47	187	#include <stdint.h> /* standard types definitions */
vipinranka	12:9a20164dcc47	188	#include <core_cmInstr.h> /* Core Instruction Access */
vipinranka	12:9a20164dcc47	189	#include <core_cmFunc.h> /* Core Function Access */
vipinranka	12:9a20164dcc47	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
vipinranka	12:9a20164dcc47	191
vipinranka	12:9a20164dcc47	192	#ifdef __cplusplus
vipinranka	12:9a20164dcc47	193	}
vipinranka	12:9a20164dcc47	194	#endif
vipinranka	12:9a20164dcc47	195
vipinranka	12:9a20164dcc47	196	#endif /* __CORE_CM7_H_GENERIC */
vipinranka	12:9a20164dcc47	197
vipinranka	12:9a20164dcc47	198	#ifndef __CMSIS_GENERIC
vipinranka	12:9a20164dcc47	199
vipinranka	12:9a20164dcc47	200	#ifndef __CORE_CM7_H_DEPENDANT
vipinranka	12:9a20164dcc47	201	#define __CORE_CM7_H_DEPENDANT
vipinranka	12:9a20164dcc47	202
vipinranka	12:9a20164dcc47	203	#ifdef __cplusplus
vipinranka	12:9a20164dcc47	204	extern "C" {
vipinranka	12:9a20164dcc47	205	#endif
vipinranka	12:9a20164dcc47	206
vipinranka	12:9a20164dcc47	207	/* check device defines and use defaults */
vipinranka	12:9a20164dcc47	208	#if defined __CHECK_DEVICE_DEFINES
vipinranka	12:9a20164dcc47	209	#ifndef __CM7_REV
vipinranka	12:9a20164dcc47	210	#define __CM7_REV 0x0000
vipinranka	12:9a20164dcc47	211	#warning "__CM7_REV not defined in device header file; using default!"
vipinranka	12:9a20164dcc47	212	#endif
vipinranka	12:9a20164dcc47	213
vipinranka	12:9a20164dcc47	214	#ifndef __FPU_PRESENT
vipinranka	12:9a20164dcc47	215	#define __FPU_PRESENT 0
vipinranka	12:9a20164dcc47	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
vipinranka	12:9a20164dcc47	217	#endif
vipinranka	12:9a20164dcc47	218
vipinranka	12:9a20164dcc47	219	#ifndef __MPU_PRESENT
vipinranka	12:9a20164dcc47	220	#define __MPU_PRESENT 0
vipinranka	12:9a20164dcc47	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
vipinranka	12:9a20164dcc47	222	#endif
vipinranka	12:9a20164dcc47	223
vipinranka	12:9a20164dcc47	224	#ifndef __ICACHE_PRESENT
vipinranka	12:9a20164dcc47	225	#define __ICACHE_PRESENT 0
vipinranka	12:9a20164dcc47	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
vipinranka	12:9a20164dcc47	227	#endif
vipinranka	12:9a20164dcc47	228
vipinranka	12:9a20164dcc47	229	#ifndef __DCACHE_PRESENT
vipinranka	12:9a20164dcc47	230	#define __DCACHE_PRESENT 0
vipinranka	12:9a20164dcc47	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
vipinranka	12:9a20164dcc47	232	#endif
vipinranka	12:9a20164dcc47	233
vipinranka	12:9a20164dcc47	234	#ifndef __DTCM_PRESENT
vipinranka	12:9a20164dcc47	235	#define __DTCM_PRESENT 0
vipinranka	12:9a20164dcc47	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
vipinranka	12:9a20164dcc47	237	#endif
vipinranka	12:9a20164dcc47	238
vipinranka	12:9a20164dcc47	239	#ifndef __NVIC_PRIO_BITS
vipinranka	12:9a20164dcc47	240	#define __NVIC_PRIO_BITS 3
vipinranka	12:9a20164dcc47	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
vipinranka	12:9a20164dcc47	242	#endif
vipinranka	12:9a20164dcc47	243
vipinranka	12:9a20164dcc47	244	#ifndef __Vendor_SysTickConfig
vipinranka	12:9a20164dcc47	245	#define __Vendor_SysTickConfig 0
vipinranka	12:9a20164dcc47	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
vipinranka	12:9a20164dcc47	247	#endif
vipinranka	12:9a20164dcc47	248	#endif
vipinranka	12:9a20164dcc47	249
vipinranka	12:9a20164dcc47	250	/* IO definitions (access restrictions to peripheral registers) */
vipinranka	12:9a20164dcc47	251	/**
vipinranka	12:9a20164dcc47	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
vipinranka	12:9a20164dcc47	253
vipinranka	12:9a20164dcc47	254	<strong>IO Type Qualifiers</strong> are used
vipinranka	12:9a20164dcc47	255	\li to specify the access to peripheral variables.
vipinranka	12:9a20164dcc47	256	\li for automatic generation of peripheral register debug information.
vipinranka	12:9a20164dcc47	257	*/
vipinranka	12:9a20164dcc47	258	#ifdef __cplusplus
vipinranka	12:9a20164dcc47	259	#define __I volatile /!< Defines 'read only' permissions /
vipinranka	12:9a20164dcc47	260	#else
vipinranka	12:9a20164dcc47	261	#define __I volatile const /!< Defines 'read only' permissions /
vipinranka	12:9a20164dcc47	262	#endif
vipinranka	12:9a20164dcc47	263	#define __O volatile /!< Defines 'write only' permissions /
vipinranka	12:9a20164dcc47	264	#define __IO volatile /!< Defines 'read / write' permissions /
vipinranka	12:9a20164dcc47	265
vipinranka	12:9a20164dcc47	266	#ifdef __cplusplus
vipinranka	12:9a20164dcc47	267	#define __IM volatile /!< Defines 'read only' permissions /
vipinranka	12:9a20164dcc47	268	#else
vipinranka	12:9a20164dcc47	269	#define __IM volatile const /!< Defines 'read only' permissions /
vipinranka	12:9a20164dcc47	270	#endif
vipinranka	12:9a20164dcc47	271	#define __OM volatile /!< Defines 'write only' permissions /
vipinranka	12:9a20164dcc47	272	#define __IOM volatile /!< Defines 'read / write' permissions /
vipinranka	12:9a20164dcc47	273
vipinranka	12:9a20164dcc47	274	/@} end of group Cortex_M7 /
vipinranka	12:9a20164dcc47	275
vipinranka	12:9a20164dcc47	276
vipinranka	12:9a20164dcc47	277
vipinranka	12:9a20164dcc47	278	/*******************************************************************************
vipinranka	12:9a20164dcc47	279	* Register Abstraction
vipinranka	12:9a20164dcc47	280	Core Register contain:
vipinranka	12:9a20164dcc47	281	- Core Register
vipinranka	12:9a20164dcc47	282	- Core NVIC Register
vipinranka	12:9a20164dcc47	283	- Core SCB Register
vipinranka	12:9a20164dcc47	284	- Core SysTick Register
vipinranka	12:9a20164dcc47	285	- Core Debug Register
vipinranka	12:9a20164dcc47	286	- Core MPU Register
vipinranka	12:9a20164dcc47	287	- Core FPU Register
vipinranka	12:9a20164dcc47	288	******************************************************************************/
vipinranka	12:9a20164dcc47	289	/** \defgroup CMSIS_core_register Defines and Type Definitions
vipinranka	12:9a20164dcc47	290	\brief Type definitions and defines for Cortex-M processor based devices.
vipinranka	12:9a20164dcc47	291	*/
vipinranka	12:9a20164dcc47	292
vipinranka	12:9a20164dcc47	293	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	294	\defgroup CMSIS_CORE Status and Control Registers
vipinranka	12:9a20164dcc47	295	\brief Core Register type definitions.
vipinranka	12:9a20164dcc47	296	@{
vipinranka	12:9a20164dcc47	297	*/
vipinranka	12:9a20164dcc47	298
vipinranka	12:9a20164dcc47	299	/** \brief Union type to access the Application Program Status Register (APSR).
vipinranka	12:9a20164dcc47	300	*/
vipinranka	12:9a20164dcc47	301	typedef union
vipinranka	12:9a20164dcc47	302	{
vipinranka	12:9a20164dcc47	303	struct
vipinranka	12:9a20164dcc47	304	{
vipinranka	12:9a20164dcc47	305	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
vipinranka	12:9a20164dcc47	306	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
vipinranka	12:9a20164dcc47	307	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
vipinranka	12:9a20164dcc47	308	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
vipinranka	12:9a20164dcc47	309	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
vipinranka	12:9a20164dcc47	310	uint32_t C:1; /!< bit: 29 Carry condition code flag /
vipinranka	12:9a20164dcc47	311	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
vipinranka	12:9a20164dcc47	312	uint32_t N:1; /!< bit: 31 Negative condition code flag /
vipinranka	12:9a20164dcc47	313	} b; /!< Structure used for bit access /
vipinranka	12:9a20164dcc47	314	uint32_t w; /!< Type used for word access /
vipinranka	12:9a20164dcc47	315	} APSR_Type;
vipinranka	12:9a20164dcc47	316
vipinranka	12:9a20164dcc47	317	/* APSR Register Definitions */
vipinranka	12:9a20164dcc47	318	#define APSR_N_Pos 31 /!< APSR: N Position /
vipinranka	12:9a20164dcc47	319	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
vipinranka	12:9a20164dcc47	320
vipinranka	12:9a20164dcc47	321	#define APSR_Z_Pos 30 /!< APSR: Z Position /
vipinranka	12:9a20164dcc47	322	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
vipinranka	12:9a20164dcc47	323
vipinranka	12:9a20164dcc47	324	#define APSR_C_Pos 29 /!< APSR: C Position /
vipinranka	12:9a20164dcc47	325	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
vipinranka	12:9a20164dcc47	326
vipinranka	12:9a20164dcc47	327	#define APSR_V_Pos 28 /!< APSR: V Position /
vipinranka	12:9a20164dcc47	328	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
vipinranka	12:9a20164dcc47	329
vipinranka	12:9a20164dcc47	330	#define APSR_Q_Pos 27 /!< APSR: Q Position /
vipinranka	12:9a20164dcc47	331	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
vipinranka	12:9a20164dcc47	332
vipinranka	12:9a20164dcc47	333	#define APSR_GE_Pos 16 /!< APSR: GE Position /
vipinranka	12:9a20164dcc47	334	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
vipinranka	12:9a20164dcc47	335
vipinranka	12:9a20164dcc47	336
vipinranka	12:9a20164dcc47	337	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
vipinranka	12:9a20164dcc47	338	*/
vipinranka	12:9a20164dcc47	339	typedef union
vipinranka	12:9a20164dcc47	340	{
vipinranka	12:9a20164dcc47	341	struct
vipinranka	12:9a20164dcc47	342	{
vipinranka	12:9a20164dcc47	343	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
vipinranka	12:9a20164dcc47	344	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
vipinranka	12:9a20164dcc47	345	} b; /!< Structure used for bit access /
vipinranka	12:9a20164dcc47	346	uint32_t w; /!< Type used for word access /
vipinranka	12:9a20164dcc47	347	} IPSR_Type;
vipinranka	12:9a20164dcc47	348
vipinranka	12:9a20164dcc47	349	/* IPSR Register Definitions */
vipinranka	12:9a20164dcc47	350	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
vipinranka	12:9a20164dcc47	351	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
vipinranka	12:9a20164dcc47	352
vipinranka	12:9a20164dcc47	353
vipinranka	12:9a20164dcc47	354	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
vipinranka	12:9a20164dcc47	355	*/
vipinranka	12:9a20164dcc47	356	typedef union
vipinranka	12:9a20164dcc47	357	{
vipinranka	12:9a20164dcc47	358	struct
vipinranka	12:9a20164dcc47	359	{
vipinranka	12:9a20164dcc47	360	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
vipinranka	12:9a20164dcc47	361	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
vipinranka	12:9a20164dcc47	362	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
vipinranka	12:9a20164dcc47	363	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
vipinranka	12:9a20164dcc47	364	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
vipinranka	12:9a20164dcc47	365	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
vipinranka	12:9a20164dcc47	366	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
vipinranka	12:9a20164dcc47	367	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
vipinranka	12:9a20164dcc47	368	uint32_t C:1; /!< bit: 29 Carry condition code flag /
vipinranka	12:9a20164dcc47	369	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
vipinranka	12:9a20164dcc47	370	uint32_t N:1; /!< bit: 31 Negative condition code flag /
vipinranka	12:9a20164dcc47	371	} b; /!< Structure used for bit access /
vipinranka	12:9a20164dcc47	372	uint32_t w; /!< Type used for word access /
vipinranka	12:9a20164dcc47	373	} xPSR_Type;
vipinranka	12:9a20164dcc47	374
vipinranka	12:9a20164dcc47	375	/* xPSR Register Definitions */
vipinranka	12:9a20164dcc47	376	#define xPSR_N_Pos 31 /!< xPSR: N Position /
vipinranka	12:9a20164dcc47	377	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
vipinranka	12:9a20164dcc47	378
vipinranka	12:9a20164dcc47	379	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
vipinranka	12:9a20164dcc47	380	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
vipinranka	12:9a20164dcc47	381
vipinranka	12:9a20164dcc47	382	#define xPSR_C_Pos 29 /!< xPSR: C Position /
vipinranka	12:9a20164dcc47	383	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
vipinranka	12:9a20164dcc47	384
vipinranka	12:9a20164dcc47	385	#define xPSR_V_Pos 28 /!< xPSR: V Position /
vipinranka	12:9a20164dcc47	386	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
vipinranka	12:9a20164dcc47	387
vipinranka	12:9a20164dcc47	388	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
vipinranka	12:9a20164dcc47	389	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
vipinranka	12:9a20164dcc47	390
vipinranka	12:9a20164dcc47	391	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
vipinranka	12:9a20164dcc47	392	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
vipinranka	12:9a20164dcc47	393
vipinranka	12:9a20164dcc47	394	#define xPSR_T_Pos 24 /!< xPSR: T Position /
vipinranka	12:9a20164dcc47	395	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
vipinranka	12:9a20164dcc47	396
vipinranka	12:9a20164dcc47	397	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
vipinranka	12:9a20164dcc47	398	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
vipinranka	12:9a20164dcc47	399
vipinranka	12:9a20164dcc47	400	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
vipinranka	12:9a20164dcc47	401	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
vipinranka	12:9a20164dcc47	402
vipinranka	12:9a20164dcc47	403
vipinranka	12:9a20164dcc47	404	/** \brief Union type to access the Control Registers (CONTROL).
vipinranka	12:9a20164dcc47	405	*/
vipinranka	12:9a20164dcc47	406	typedef union
vipinranka	12:9a20164dcc47	407	{
vipinranka	12:9a20164dcc47	408	struct
vipinranka	12:9a20164dcc47	409	{
vipinranka	12:9a20164dcc47	410	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
vipinranka	12:9a20164dcc47	411	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
vipinranka	12:9a20164dcc47	412	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
vipinranka	12:9a20164dcc47	413	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
vipinranka	12:9a20164dcc47	414	} b; /!< Structure used for bit access /
vipinranka	12:9a20164dcc47	415	uint32_t w; /!< Type used for word access /
vipinranka	12:9a20164dcc47	416	} CONTROL_Type;
vipinranka	12:9a20164dcc47	417
vipinranka	12:9a20164dcc47	418	/* CONTROL Register Definitions */
vipinranka	12:9a20164dcc47	419	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
vipinranka	12:9a20164dcc47	420	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
vipinranka	12:9a20164dcc47	421
vipinranka	12:9a20164dcc47	422	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
vipinranka	12:9a20164dcc47	423	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
vipinranka	12:9a20164dcc47	424
vipinranka	12:9a20164dcc47	425	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
vipinranka	12:9a20164dcc47	426	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
vipinranka	12:9a20164dcc47	427
vipinranka	12:9a20164dcc47	428	/@} end of group CMSIS_CORE /
vipinranka	12:9a20164dcc47	429
vipinranka	12:9a20164dcc47	430
vipinranka	12:9a20164dcc47	431	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	432	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
vipinranka	12:9a20164dcc47	433	\brief Type definitions for the NVIC Registers
vipinranka	12:9a20164dcc47	434	@{
vipinranka	12:9a20164dcc47	435	*/
vipinranka	12:9a20164dcc47	436
vipinranka	12:9a20164dcc47	437	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
vipinranka	12:9a20164dcc47	438	*/
vipinranka	12:9a20164dcc47	439	typedef struct
vipinranka	12:9a20164dcc47	440	{
vipinranka	12:9a20164dcc47	441	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
vipinranka	12:9a20164dcc47	442	uint32_t RESERVED0[24];
vipinranka	12:9a20164dcc47	443	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
vipinranka	12:9a20164dcc47	444	uint32_t RSERVED1[24];
vipinranka	12:9a20164dcc47	445	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
vipinranka	12:9a20164dcc47	446	uint32_t RESERVED2[24];
vipinranka	12:9a20164dcc47	447	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
vipinranka	12:9a20164dcc47	448	uint32_t RESERVED3[24];
vipinranka	12:9a20164dcc47	449	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
vipinranka	12:9a20164dcc47	450	uint32_t RESERVED4[56];
vipinranka	12:9a20164dcc47	451	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
vipinranka	12:9a20164dcc47	452	uint32_t RESERVED5[644];
vipinranka	12:9a20164dcc47	453	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
vipinranka	12:9a20164dcc47	454	} NVIC_Type;
vipinranka	12:9a20164dcc47	455
vipinranka	12:9a20164dcc47	456	/* Software Triggered Interrupt Register Definitions */
vipinranka	12:9a20164dcc47	457	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
vipinranka	12:9a20164dcc47	458	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
vipinranka	12:9a20164dcc47	459
vipinranka	12:9a20164dcc47	460	/@} end of group CMSIS_NVIC /
vipinranka	12:9a20164dcc47	461
vipinranka	12:9a20164dcc47	462
vipinranka	12:9a20164dcc47	463	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	464	\defgroup CMSIS_SCB System Control Block (SCB)
vipinranka	12:9a20164dcc47	465	\brief Type definitions for the System Control Block Registers
vipinranka	12:9a20164dcc47	466	@{
vipinranka	12:9a20164dcc47	467	*/
vipinranka	12:9a20164dcc47	468
vipinranka	12:9a20164dcc47	469	/** \brief Structure type to access the System Control Block (SCB).
vipinranka	12:9a20164dcc47	470	*/
vipinranka	12:9a20164dcc47	471	typedef struct
vipinranka	12:9a20164dcc47	472	{
vipinranka	12:9a20164dcc47	473	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
vipinranka	12:9a20164dcc47	474	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
vipinranka	12:9a20164dcc47	475	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
vipinranka	12:9a20164dcc47	476	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
vipinranka	12:9a20164dcc47	477	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
vipinranka	12:9a20164dcc47	478	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
vipinranka	12:9a20164dcc47	479	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
vipinranka	12:9a20164dcc47	480	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
vipinranka	12:9a20164dcc47	481	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
vipinranka	12:9a20164dcc47	482	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
vipinranka	12:9a20164dcc47	483	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
vipinranka	12:9a20164dcc47	484	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
vipinranka	12:9a20164dcc47	485	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
vipinranka	12:9a20164dcc47	486	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
vipinranka	12:9a20164dcc47	487	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
vipinranka	12:9a20164dcc47	488	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
vipinranka	12:9a20164dcc47	489	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
vipinranka	12:9a20164dcc47	490	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
vipinranka	12:9a20164dcc47	491	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
vipinranka	12:9a20164dcc47	492	uint32_t RESERVED0[1];
vipinranka	12:9a20164dcc47	493	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
vipinranka	12:9a20164dcc47	494	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
vipinranka	12:9a20164dcc47	495	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
vipinranka	12:9a20164dcc47	496	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
vipinranka	12:9a20164dcc47	497	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
vipinranka	12:9a20164dcc47	498	uint32_t RESERVED3[93];
vipinranka	12:9a20164dcc47	499	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
vipinranka	12:9a20164dcc47	500	uint32_t RESERVED4[15];
vipinranka	12:9a20164dcc47	501	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
vipinranka	12:9a20164dcc47	502	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
vipinranka	12:9a20164dcc47	503	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
vipinranka	12:9a20164dcc47	504	uint32_t RESERVED5[1];
vipinranka	12:9a20164dcc47	505	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
vipinranka	12:9a20164dcc47	506	uint32_t RESERVED6[1];
vipinranka	12:9a20164dcc47	507	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
vipinranka	12:9a20164dcc47	508	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
vipinranka	12:9a20164dcc47	509	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
vipinranka	12:9a20164dcc47	510	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
vipinranka	12:9a20164dcc47	511	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
vipinranka	12:9a20164dcc47	512	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
vipinranka	12:9a20164dcc47	513	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
vipinranka	12:9a20164dcc47	514	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
vipinranka	12:9a20164dcc47	515	uint32_t RESERVED7[6];
vipinranka	12:9a20164dcc47	516	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
vipinranka	12:9a20164dcc47	517	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
vipinranka	12:9a20164dcc47	518	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
vipinranka	12:9a20164dcc47	519	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
vipinranka	12:9a20164dcc47	520	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
vipinranka	12:9a20164dcc47	521	uint32_t RESERVED8[1];
vipinranka	12:9a20164dcc47	522	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
vipinranka	12:9a20164dcc47	523	} SCB_Type;
vipinranka	12:9a20164dcc47	524
vipinranka	12:9a20164dcc47	525	/* SCB CPUID Register Definitions */
vipinranka	12:9a20164dcc47	526	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
vipinranka	12:9a20164dcc47	527	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
vipinranka	12:9a20164dcc47	528
vipinranka	12:9a20164dcc47	529	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
vipinranka	12:9a20164dcc47	530	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
vipinranka	12:9a20164dcc47	531
vipinranka	12:9a20164dcc47	532	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
vipinranka	12:9a20164dcc47	533	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
vipinranka	12:9a20164dcc47	534
vipinranka	12:9a20164dcc47	535	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
vipinranka	12:9a20164dcc47	536	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
vipinranka	12:9a20164dcc47	537
vipinranka	12:9a20164dcc47	538	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
vipinranka	12:9a20164dcc47	539	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
vipinranka	12:9a20164dcc47	540
vipinranka	12:9a20164dcc47	541	/* SCB Interrupt Control State Register Definitions */
vipinranka	12:9a20164dcc47	542	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
vipinranka	12:9a20164dcc47	543	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
vipinranka	12:9a20164dcc47	544
vipinranka	12:9a20164dcc47	545	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
vipinranka	12:9a20164dcc47	546	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
vipinranka	12:9a20164dcc47	547
vipinranka	12:9a20164dcc47	548	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
vipinranka	12:9a20164dcc47	549	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
vipinranka	12:9a20164dcc47	550
vipinranka	12:9a20164dcc47	551	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
vipinranka	12:9a20164dcc47	552	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
vipinranka	12:9a20164dcc47	553
vipinranka	12:9a20164dcc47	554	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
vipinranka	12:9a20164dcc47	555	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
vipinranka	12:9a20164dcc47	556
vipinranka	12:9a20164dcc47	557	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
vipinranka	12:9a20164dcc47	558	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
vipinranka	12:9a20164dcc47	559
vipinranka	12:9a20164dcc47	560	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
vipinranka	12:9a20164dcc47	561	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
vipinranka	12:9a20164dcc47	562
vipinranka	12:9a20164dcc47	563	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
vipinranka	12:9a20164dcc47	564	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
vipinranka	12:9a20164dcc47	565
vipinranka	12:9a20164dcc47	566	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
vipinranka	12:9a20164dcc47	567	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
vipinranka	12:9a20164dcc47	568
vipinranka	12:9a20164dcc47	569	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
vipinranka	12:9a20164dcc47	570	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
vipinranka	12:9a20164dcc47	571
vipinranka	12:9a20164dcc47	572	/* SCB Vector Table Offset Register Definitions */
vipinranka	12:9a20164dcc47	573	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
vipinranka	12:9a20164dcc47	574	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
vipinranka	12:9a20164dcc47	575
vipinranka	12:9a20164dcc47	576	/* SCB Application Interrupt and Reset Control Register Definitions */
vipinranka	12:9a20164dcc47	577	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
vipinranka	12:9a20164dcc47	578	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
vipinranka	12:9a20164dcc47	579
vipinranka	12:9a20164dcc47	580	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
vipinranka	12:9a20164dcc47	581	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
vipinranka	12:9a20164dcc47	582
vipinranka	12:9a20164dcc47	583	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
vipinranka	12:9a20164dcc47	584	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
vipinranka	12:9a20164dcc47	585
vipinranka	12:9a20164dcc47	586	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
vipinranka	12:9a20164dcc47	587	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
vipinranka	12:9a20164dcc47	588
vipinranka	12:9a20164dcc47	589	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
vipinranka	12:9a20164dcc47	590	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
vipinranka	12:9a20164dcc47	591
vipinranka	12:9a20164dcc47	592	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
vipinranka	12:9a20164dcc47	593	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
vipinranka	12:9a20164dcc47	594
vipinranka	12:9a20164dcc47	595	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
vipinranka	12:9a20164dcc47	596	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
vipinranka	12:9a20164dcc47	597
vipinranka	12:9a20164dcc47	598	/* SCB System Control Register Definitions */
vipinranka	12:9a20164dcc47	599	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
vipinranka	12:9a20164dcc47	600	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
vipinranka	12:9a20164dcc47	601
vipinranka	12:9a20164dcc47	602	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
vipinranka	12:9a20164dcc47	603	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
vipinranka	12:9a20164dcc47	604
vipinranka	12:9a20164dcc47	605	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
vipinranka	12:9a20164dcc47	606	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
vipinranka	12:9a20164dcc47	607
vipinranka	12:9a20164dcc47	608	/* SCB Configuration Control Register Definitions */
vipinranka	12:9a20164dcc47	609	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
vipinranka	12:9a20164dcc47	610	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
vipinranka	12:9a20164dcc47	611
vipinranka	12:9a20164dcc47	612	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
vipinranka	12:9a20164dcc47	613	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
vipinranka	12:9a20164dcc47	614
vipinranka	12:9a20164dcc47	615	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
vipinranka	12:9a20164dcc47	616	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
vipinranka	12:9a20164dcc47	617
vipinranka	12:9a20164dcc47	618	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
vipinranka	12:9a20164dcc47	619	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
vipinranka	12:9a20164dcc47	620
vipinranka	12:9a20164dcc47	621	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
vipinranka	12:9a20164dcc47	622	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
vipinranka	12:9a20164dcc47	623
vipinranka	12:9a20164dcc47	624	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
vipinranka	12:9a20164dcc47	625	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
vipinranka	12:9a20164dcc47	626
vipinranka	12:9a20164dcc47	627	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
vipinranka	12:9a20164dcc47	628	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
vipinranka	12:9a20164dcc47	629
vipinranka	12:9a20164dcc47	630	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
vipinranka	12:9a20164dcc47	631	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
vipinranka	12:9a20164dcc47	632
vipinranka	12:9a20164dcc47	633	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
vipinranka	12:9a20164dcc47	634	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
vipinranka	12:9a20164dcc47	635
vipinranka	12:9a20164dcc47	636	/* SCB System Handler Control and State Register Definitions */
vipinranka	12:9a20164dcc47	637	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
vipinranka	12:9a20164dcc47	638	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
vipinranka	12:9a20164dcc47	639
vipinranka	12:9a20164dcc47	640	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
vipinranka	12:9a20164dcc47	641	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
vipinranka	12:9a20164dcc47	642
vipinranka	12:9a20164dcc47	643	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
vipinranka	12:9a20164dcc47	644	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
vipinranka	12:9a20164dcc47	645
vipinranka	12:9a20164dcc47	646	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
vipinranka	12:9a20164dcc47	647	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
vipinranka	12:9a20164dcc47	648
vipinranka	12:9a20164dcc47	649	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
vipinranka	12:9a20164dcc47	650	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
vipinranka	12:9a20164dcc47	651
vipinranka	12:9a20164dcc47	652	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
vipinranka	12:9a20164dcc47	653	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
vipinranka	12:9a20164dcc47	654
vipinranka	12:9a20164dcc47	655	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
vipinranka	12:9a20164dcc47	656	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
vipinranka	12:9a20164dcc47	657
vipinranka	12:9a20164dcc47	658	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
vipinranka	12:9a20164dcc47	659	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
vipinranka	12:9a20164dcc47	660
vipinranka	12:9a20164dcc47	661	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
vipinranka	12:9a20164dcc47	662	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
vipinranka	12:9a20164dcc47	663
vipinranka	12:9a20164dcc47	664	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
vipinranka	12:9a20164dcc47	665	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
vipinranka	12:9a20164dcc47	666
vipinranka	12:9a20164dcc47	667	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
vipinranka	12:9a20164dcc47	668	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
vipinranka	12:9a20164dcc47	669
vipinranka	12:9a20164dcc47	670	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
vipinranka	12:9a20164dcc47	671	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
vipinranka	12:9a20164dcc47	672
vipinranka	12:9a20164dcc47	673	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
vipinranka	12:9a20164dcc47	674	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
vipinranka	12:9a20164dcc47	675
vipinranka	12:9a20164dcc47	676	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
vipinranka	12:9a20164dcc47	677	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
vipinranka	12:9a20164dcc47	678
vipinranka	12:9a20164dcc47	679	/* SCB Configurable Fault Status Registers Definitions */
vipinranka	12:9a20164dcc47	680	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
vipinranka	12:9a20164dcc47	681	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
vipinranka	12:9a20164dcc47	682
vipinranka	12:9a20164dcc47	683	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
vipinranka	12:9a20164dcc47	684	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
vipinranka	12:9a20164dcc47	685
vipinranka	12:9a20164dcc47	686	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
vipinranka	12:9a20164dcc47	687	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
vipinranka	12:9a20164dcc47	688
vipinranka	12:9a20164dcc47	689	/* SCB Hard Fault Status Registers Definitions */
vipinranka	12:9a20164dcc47	690	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
vipinranka	12:9a20164dcc47	691	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
vipinranka	12:9a20164dcc47	692
vipinranka	12:9a20164dcc47	693	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
vipinranka	12:9a20164dcc47	694	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
vipinranka	12:9a20164dcc47	695
vipinranka	12:9a20164dcc47	696	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
vipinranka	12:9a20164dcc47	697	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
vipinranka	12:9a20164dcc47	698
vipinranka	12:9a20164dcc47	699	/* SCB Debug Fault Status Register Definitions */
vipinranka	12:9a20164dcc47	700	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
vipinranka	12:9a20164dcc47	701	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
vipinranka	12:9a20164dcc47	702
vipinranka	12:9a20164dcc47	703	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
vipinranka	12:9a20164dcc47	704	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
vipinranka	12:9a20164dcc47	705
vipinranka	12:9a20164dcc47	706	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
vipinranka	12:9a20164dcc47	707	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
vipinranka	12:9a20164dcc47	708
vipinranka	12:9a20164dcc47	709	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
vipinranka	12:9a20164dcc47	710	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
vipinranka	12:9a20164dcc47	711
vipinranka	12:9a20164dcc47	712	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
vipinranka	12:9a20164dcc47	713	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
vipinranka	12:9a20164dcc47	714
vipinranka	12:9a20164dcc47	715	/* Cache Level ID register */
vipinranka	12:9a20164dcc47	716	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
vipinranka	12:9a20164dcc47	717	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
vipinranka	12:9a20164dcc47	718
vipinranka	12:9a20164dcc47	719	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
vipinranka	12:9a20164dcc47	720	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
vipinranka	12:9a20164dcc47	721
vipinranka	12:9a20164dcc47	722	/* Cache Type register */
vipinranka	12:9a20164dcc47	723	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
vipinranka	12:9a20164dcc47	724	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
vipinranka	12:9a20164dcc47	725
vipinranka	12:9a20164dcc47	726	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
vipinranka	12:9a20164dcc47	727	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
vipinranka	12:9a20164dcc47	728
vipinranka	12:9a20164dcc47	729	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
vipinranka	12:9a20164dcc47	730	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
vipinranka	12:9a20164dcc47	731
vipinranka	12:9a20164dcc47	732	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
vipinranka	12:9a20164dcc47	733	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
vipinranka	12:9a20164dcc47	734
vipinranka	12:9a20164dcc47	735	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
vipinranka	12:9a20164dcc47	736	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
vipinranka	12:9a20164dcc47	737
vipinranka	12:9a20164dcc47	738	/* Cache Size ID Register */
vipinranka	12:9a20164dcc47	739	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
vipinranka	12:9a20164dcc47	740	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
vipinranka	12:9a20164dcc47	741
vipinranka	12:9a20164dcc47	742	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
vipinranka	12:9a20164dcc47	743	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
vipinranka	12:9a20164dcc47	744
vipinranka	12:9a20164dcc47	745	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
vipinranka	12:9a20164dcc47	746	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
vipinranka	12:9a20164dcc47	747
vipinranka	12:9a20164dcc47	748	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
vipinranka	12:9a20164dcc47	749	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
vipinranka	12:9a20164dcc47	750
vipinranka	12:9a20164dcc47	751	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
vipinranka	12:9a20164dcc47	752	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
vipinranka	12:9a20164dcc47	753
vipinranka	12:9a20164dcc47	754	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
vipinranka	12:9a20164dcc47	755	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
vipinranka	12:9a20164dcc47	756
vipinranka	12:9a20164dcc47	757	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
vipinranka	12:9a20164dcc47	758	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
vipinranka	12:9a20164dcc47	759
vipinranka	12:9a20164dcc47	760	/* Cache Size Selection Register */
vipinranka	12:9a20164dcc47	761	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
vipinranka	12:9a20164dcc47	762	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
vipinranka	12:9a20164dcc47	763
vipinranka	12:9a20164dcc47	764	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
vipinranka	12:9a20164dcc47	765	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
vipinranka	12:9a20164dcc47	766
vipinranka	12:9a20164dcc47	767	/* SCB Software Triggered Interrupt Register */
vipinranka	12:9a20164dcc47	768	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
vipinranka	12:9a20164dcc47	769	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
vipinranka	12:9a20164dcc47	770
vipinranka	12:9a20164dcc47	771	/* Instruction Tightly-Coupled Memory Control Register*/
vipinranka	12:9a20164dcc47	772	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
vipinranka	12:9a20164dcc47	773	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
vipinranka	12:9a20164dcc47	774
vipinranka	12:9a20164dcc47	775	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
vipinranka	12:9a20164dcc47	776	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
vipinranka	12:9a20164dcc47	777
vipinranka	12:9a20164dcc47	778	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
vipinranka	12:9a20164dcc47	779	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
vipinranka	12:9a20164dcc47	780
vipinranka	12:9a20164dcc47	781	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
vipinranka	12:9a20164dcc47	782	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
vipinranka	12:9a20164dcc47	783
vipinranka	12:9a20164dcc47	784	/* Data Tightly-Coupled Memory Control Registers */
vipinranka	12:9a20164dcc47	785	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
vipinranka	12:9a20164dcc47	786	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
vipinranka	12:9a20164dcc47	787
vipinranka	12:9a20164dcc47	788	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
vipinranka	12:9a20164dcc47	789	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
vipinranka	12:9a20164dcc47	790
vipinranka	12:9a20164dcc47	791	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
vipinranka	12:9a20164dcc47	792	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
vipinranka	12:9a20164dcc47	793
vipinranka	12:9a20164dcc47	794	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
vipinranka	12:9a20164dcc47	795	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
vipinranka	12:9a20164dcc47	796
vipinranka	12:9a20164dcc47	797	/* AHBP Control Register */
vipinranka	12:9a20164dcc47	798	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
vipinranka	12:9a20164dcc47	799	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
vipinranka	12:9a20164dcc47	800
vipinranka	12:9a20164dcc47	801	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
vipinranka	12:9a20164dcc47	802	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
vipinranka	12:9a20164dcc47	803
vipinranka	12:9a20164dcc47	804	/* L1 Cache Control Register */
vipinranka	12:9a20164dcc47	805	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
vipinranka	12:9a20164dcc47	806	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
vipinranka	12:9a20164dcc47	807
vipinranka	12:9a20164dcc47	808	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
vipinranka	12:9a20164dcc47	809	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
vipinranka	12:9a20164dcc47	810
vipinranka	12:9a20164dcc47	811	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
vipinranka	12:9a20164dcc47	812	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
vipinranka	12:9a20164dcc47	813
vipinranka	12:9a20164dcc47	814	/* AHBS control register */
vipinranka	12:9a20164dcc47	815	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
vipinranka	12:9a20164dcc47	816	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
vipinranka	12:9a20164dcc47	817
vipinranka	12:9a20164dcc47	818	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
vipinranka	12:9a20164dcc47	819	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
vipinranka	12:9a20164dcc47	820
vipinranka	12:9a20164dcc47	821	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
vipinranka	12:9a20164dcc47	822	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
vipinranka	12:9a20164dcc47	823
vipinranka	12:9a20164dcc47	824	/* Auxiliary Bus Fault Status Register */
vipinranka	12:9a20164dcc47	825	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
vipinranka	12:9a20164dcc47	826	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
vipinranka	12:9a20164dcc47	827
vipinranka	12:9a20164dcc47	828	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
vipinranka	12:9a20164dcc47	829	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
vipinranka	12:9a20164dcc47	830
vipinranka	12:9a20164dcc47	831	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
vipinranka	12:9a20164dcc47	832	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
vipinranka	12:9a20164dcc47	833
vipinranka	12:9a20164dcc47	834	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
vipinranka	12:9a20164dcc47	835	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
vipinranka	12:9a20164dcc47	836
vipinranka	12:9a20164dcc47	837	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
vipinranka	12:9a20164dcc47	838	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
vipinranka	12:9a20164dcc47	839
vipinranka	12:9a20164dcc47	840	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
vipinranka	12:9a20164dcc47	841	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
vipinranka	12:9a20164dcc47	842
vipinranka	12:9a20164dcc47	843	/@} end of group CMSIS_SCB /
vipinranka	12:9a20164dcc47	844
vipinranka	12:9a20164dcc47	845
vipinranka	12:9a20164dcc47	846	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	847	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
vipinranka	12:9a20164dcc47	848	\brief Type definitions for the System Control and ID Register not in the SCB
vipinranka	12:9a20164dcc47	849	@{
vipinranka	12:9a20164dcc47	850	*/
vipinranka	12:9a20164dcc47	851
vipinranka	12:9a20164dcc47	852	/** \brief Structure type to access the System Control and ID Register not in the SCB.
vipinranka	12:9a20164dcc47	853	*/
vipinranka	12:9a20164dcc47	854	typedef struct
vipinranka	12:9a20164dcc47	855	{
vipinranka	12:9a20164dcc47	856	uint32_t RESERVED0[1];
vipinranka	12:9a20164dcc47	857	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
vipinranka	12:9a20164dcc47	858	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
vipinranka	12:9a20164dcc47	859	} SCnSCB_Type;
vipinranka	12:9a20164dcc47	860
vipinranka	12:9a20164dcc47	861	/* Interrupt Controller Type Register Definitions */
vipinranka	12:9a20164dcc47	862	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
vipinranka	12:9a20164dcc47	863	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
vipinranka	12:9a20164dcc47	864
vipinranka	12:9a20164dcc47	865	/* Auxiliary Control Register Definitions */
vipinranka	12:9a20164dcc47	866	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
vipinranka	12:9a20164dcc47	867	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
vipinranka	12:9a20164dcc47	868
vipinranka	12:9a20164dcc47	869	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
vipinranka	12:9a20164dcc47	870	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
vipinranka	12:9a20164dcc47	871
vipinranka	12:9a20164dcc47	872	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
vipinranka	12:9a20164dcc47	873	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
vipinranka	12:9a20164dcc47	874
vipinranka	12:9a20164dcc47	875	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
vipinranka	12:9a20164dcc47	876	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
vipinranka	12:9a20164dcc47	877
vipinranka	12:9a20164dcc47	878	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
vipinranka	12:9a20164dcc47	879	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
vipinranka	12:9a20164dcc47	880
vipinranka	12:9a20164dcc47	881	/@} end of group CMSIS_SCnotSCB /
vipinranka	12:9a20164dcc47	882
vipinranka	12:9a20164dcc47	883
vipinranka	12:9a20164dcc47	884	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	885	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
vipinranka	12:9a20164dcc47	886	\brief Type definitions for the System Timer Registers.
vipinranka	12:9a20164dcc47	887	@{
vipinranka	12:9a20164dcc47	888	*/
vipinranka	12:9a20164dcc47	889
vipinranka	12:9a20164dcc47	890	/** \brief Structure type to access the System Timer (SysTick).
vipinranka	12:9a20164dcc47	891	*/
vipinranka	12:9a20164dcc47	892	typedef struct
vipinranka	12:9a20164dcc47	893	{
vipinranka	12:9a20164dcc47	894	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
vipinranka	12:9a20164dcc47	895	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
vipinranka	12:9a20164dcc47	896	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
vipinranka	12:9a20164dcc47	897	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
vipinranka	12:9a20164dcc47	898	} SysTick_Type;
vipinranka	12:9a20164dcc47	899
vipinranka	12:9a20164dcc47	900	/* SysTick Control / Status Register Definitions */
vipinranka	12:9a20164dcc47	901	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
vipinranka	12:9a20164dcc47	902	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
vipinranka	12:9a20164dcc47	903
vipinranka	12:9a20164dcc47	904	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
vipinranka	12:9a20164dcc47	905	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
vipinranka	12:9a20164dcc47	906
vipinranka	12:9a20164dcc47	907	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
vipinranka	12:9a20164dcc47	908	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
vipinranka	12:9a20164dcc47	909
vipinranka	12:9a20164dcc47	910	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
vipinranka	12:9a20164dcc47	911	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
vipinranka	12:9a20164dcc47	912
vipinranka	12:9a20164dcc47	913	/* SysTick Reload Register Definitions */
vipinranka	12:9a20164dcc47	914	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
vipinranka	12:9a20164dcc47	915	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
vipinranka	12:9a20164dcc47	916
vipinranka	12:9a20164dcc47	917	/* SysTick Current Register Definitions */
vipinranka	12:9a20164dcc47	918	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
vipinranka	12:9a20164dcc47	919	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
vipinranka	12:9a20164dcc47	920
vipinranka	12:9a20164dcc47	921	/* SysTick Calibration Register Definitions */
vipinranka	12:9a20164dcc47	922	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
vipinranka	12:9a20164dcc47	923	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
vipinranka	12:9a20164dcc47	924
vipinranka	12:9a20164dcc47	925	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
vipinranka	12:9a20164dcc47	926	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
vipinranka	12:9a20164dcc47	927
vipinranka	12:9a20164dcc47	928	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
vipinranka	12:9a20164dcc47	929	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
vipinranka	12:9a20164dcc47	930
vipinranka	12:9a20164dcc47	931	/@} end of group CMSIS_SysTick /
vipinranka	12:9a20164dcc47	932
vipinranka	12:9a20164dcc47	933
vipinranka	12:9a20164dcc47	934	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	935	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
vipinranka	12:9a20164dcc47	936	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
vipinranka	12:9a20164dcc47	937	@{
vipinranka	12:9a20164dcc47	938	*/
vipinranka	12:9a20164dcc47	939
vipinranka	12:9a20164dcc47	940	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
vipinranka	12:9a20164dcc47	941	*/
vipinranka	12:9a20164dcc47	942	typedef struct
vipinranka	12:9a20164dcc47	943	{
vipinranka	12:9a20164dcc47	944	__O union
vipinranka	12:9a20164dcc47	945	{
vipinranka	12:9a20164dcc47	946	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
vipinranka	12:9a20164dcc47	947	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
vipinranka	12:9a20164dcc47	948	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
vipinranka	12:9a20164dcc47	949	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
vipinranka	12:9a20164dcc47	950	uint32_t RESERVED0[864];
vipinranka	12:9a20164dcc47	951	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
vipinranka	12:9a20164dcc47	952	uint32_t RESERVED1[15];
vipinranka	12:9a20164dcc47	953	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
vipinranka	12:9a20164dcc47	954	uint32_t RESERVED2[15];
vipinranka	12:9a20164dcc47	955	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
vipinranka	12:9a20164dcc47	956	uint32_t RESERVED3[29];
vipinranka	12:9a20164dcc47	957	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
vipinranka	12:9a20164dcc47	958	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
vipinranka	12:9a20164dcc47	959	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
vipinranka	12:9a20164dcc47	960	uint32_t RESERVED4[43];
vipinranka	12:9a20164dcc47	961	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
vipinranka	12:9a20164dcc47	962	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
vipinranka	12:9a20164dcc47	963	uint32_t RESERVED5[6];
vipinranka	12:9a20164dcc47	964	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
vipinranka	12:9a20164dcc47	965	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
vipinranka	12:9a20164dcc47	966	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
vipinranka	12:9a20164dcc47	967	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
vipinranka	12:9a20164dcc47	968	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
vipinranka	12:9a20164dcc47	969	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
vipinranka	12:9a20164dcc47	970	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
vipinranka	12:9a20164dcc47	971	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
vipinranka	12:9a20164dcc47	972	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
vipinranka	12:9a20164dcc47	973	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
vipinranka	12:9a20164dcc47	974	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
vipinranka	12:9a20164dcc47	975	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
vipinranka	12:9a20164dcc47	976	} ITM_Type;
vipinranka	12:9a20164dcc47	977
vipinranka	12:9a20164dcc47	978	/* ITM Trace Privilege Register Definitions */
vipinranka	12:9a20164dcc47	979	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
vipinranka	12:9a20164dcc47	980	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
vipinranka	12:9a20164dcc47	981
vipinranka	12:9a20164dcc47	982	/* ITM Trace Control Register Definitions */
vipinranka	12:9a20164dcc47	983	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
vipinranka	12:9a20164dcc47	984	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
vipinranka	12:9a20164dcc47	985
vipinranka	12:9a20164dcc47	986	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
vipinranka	12:9a20164dcc47	987	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
vipinranka	12:9a20164dcc47	988
vipinranka	12:9a20164dcc47	989	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
vipinranka	12:9a20164dcc47	990	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
vipinranka	12:9a20164dcc47	991
vipinranka	12:9a20164dcc47	992	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
vipinranka	12:9a20164dcc47	993	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
vipinranka	12:9a20164dcc47	994
vipinranka	12:9a20164dcc47	995	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
vipinranka	12:9a20164dcc47	996	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
vipinranka	12:9a20164dcc47	997
vipinranka	12:9a20164dcc47	998	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
vipinranka	12:9a20164dcc47	999	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
vipinranka	12:9a20164dcc47	1000
vipinranka	12:9a20164dcc47	1001	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
vipinranka	12:9a20164dcc47	1002	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
vipinranka	12:9a20164dcc47	1003
vipinranka	12:9a20164dcc47	1004	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
vipinranka	12:9a20164dcc47	1005	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
vipinranka	12:9a20164dcc47	1006
vipinranka	12:9a20164dcc47	1007	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
vipinranka	12:9a20164dcc47	1008	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
vipinranka	12:9a20164dcc47	1009
vipinranka	12:9a20164dcc47	1010	/* ITM Integration Write Register Definitions */
vipinranka	12:9a20164dcc47	1011	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
vipinranka	12:9a20164dcc47	1012	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
vipinranka	12:9a20164dcc47	1013
vipinranka	12:9a20164dcc47	1014	/* ITM Integration Read Register Definitions */
vipinranka	12:9a20164dcc47	1015	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
vipinranka	12:9a20164dcc47	1016	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
vipinranka	12:9a20164dcc47	1017
vipinranka	12:9a20164dcc47	1018	/* ITM Integration Mode Control Register Definitions */
vipinranka	12:9a20164dcc47	1019	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
vipinranka	12:9a20164dcc47	1020	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
vipinranka	12:9a20164dcc47	1021
vipinranka	12:9a20164dcc47	1022	/* ITM Lock Status Register Definitions */
vipinranka	12:9a20164dcc47	1023	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
vipinranka	12:9a20164dcc47	1024	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
vipinranka	12:9a20164dcc47	1025
vipinranka	12:9a20164dcc47	1026	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
vipinranka	12:9a20164dcc47	1027	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
vipinranka	12:9a20164dcc47	1028
vipinranka	12:9a20164dcc47	1029	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
vipinranka	12:9a20164dcc47	1030	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
vipinranka	12:9a20164dcc47	1031
vipinranka	12:9a20164dcc47	1032	/@}/ /* end of group CMSIS_ITM */
vipinranka	12:9a20164dcc47	1033
vipinranka	12:9a20164dcc47	1034
vipinranka	12:9a20164dcc47	1035	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	1036	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
vipinranka	12:9a20164dcc47	1037	\brief Type definitions for the Data Watchpoint and Trace (DWT)
vipinranka	12:9a20164dcc47	1038	@{
vipinranka	12:9a20164dcc47	1039	*/
vipinranka	12:9a20164dcc47	1040
vipinranka	12:9a20164dcc47	1041	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
vipinranka	12:9a20164dcc47	1042	*/
vipinranka	12:9a20164dcc47	1043	typedef struct
vipinranka	12:9a20164dcc47	1044	{
vipinranka	12:9a20164dcc47	1045	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
vipinranka	12:9a20164dcc47	1046	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
vipinranka	12:9a20164dcc47	1047	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
vipinranka	12:9a20164dcc47	1048	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
vipinranka	12:9a20164dcc47	1049	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
vipinranka	12:9a20164dcc47	1050	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
vipinranka	12:9a20164dcc47	1051	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
vipinranka	12:9a20164dcc47	1052	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
vipinranka	12:9a20164dcc47	1053	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
vipinranka	12:9a20164dcc47	1054	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
vipinranka	12:9a20164dcc47	1055	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
vipinranka	12:9a20164dcc47	1056	uint32_t RESERVED0[1];
vipinranka	12:9a20164dcc47	1057	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
vipinranka	12:9a20164dcc47	1058	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
vipinranka	12:9a20164dcc47	1059	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
vipinranka	12:9a20164dcc47	1060	uint32_t RESERVED1[1];
vipinranka	12:9a20164dcc47	1061	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
vipinranka	12:9a20164dcc47	1062	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
vipinranka	12:9a20164dcc47	1063	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
vipinranka	12:9a20164dcc47	1064	uint32_t RESERVED2[1];
vipinranka	12:9a20164dcc47	1065	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
vipinranka	12:9a20164dcc47	1066	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
vipinranka	12:9a20164dcc47	1067	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
vipinranka	12:9a20164dcc47	1068	uint32_t RESERVED3[981];
vipinranka	12:9a20164dcc47	1069	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
vipinranka	12:9a20164dcc47	1070	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
vipinranka	12:9a20164dcc47	1071	} DWT_Type;
vipinranka	12:9a20164dcc47	1072
vipinranka	12:9a20164dcc47	1073	/* DWT Control Register Definitions */
vipinranka	12:9a20164dcc47	1074	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
vipinranka	12:9a20164dcc47	1075	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
vipinranka	12:9a20164dcc47	1076
vipinranka	12:9a20164dcc47	1077	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
vipinranka	12:9a20164dcc47	1078	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
vipinranka	12:9a20164dcc47	1079
vipinranka	12:9a20164dcc47	1080	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
vipinranka	12:9a20164dcc47	1081	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
vipinranka	12:9a20164dcc47	1082
vipinranka	12:9a20164dcc47	1083	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
vipinranka	12:9a20164dcc47	1084	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
vipinranka	12:9a20164dcc47	1085
vipinranka	12:9a20164dcc47	1086	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
vipinranka	12:9a20164dcc47	1087	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
vipinranka	12:9a20164dcc47	1088
vipinranka	12:9a20164dcc47	1089	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
vipinranka	12:9a20164dcc47	1090	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
vipinranka	12:9a20164dcc47	1091
vipinranka	12:9a20164dcc47	1092	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
vipinranka	12:9a20164dcc47	1093	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
vipinranka	12:9a20164dcc47	1094
vipinranka	12:9a20164dcc47	1095	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
vipinranka	12:9a20164dcc47	1096	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
vipinranka	12:9a20164dcc47	1097
vipinranka	12:9a20164dcc47	1098	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
vipinranka	12:9a20164dcc47	1099	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
vipinranka	12:9a20164dcc47	1100
vipinranka	12:9a20164dcc47	1101	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
vipinranka	12:9a20164dcc47	1102	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
vipinranka	12:9a20164dcc47	1103
vipinranka	12:9a20164dcc47	1104	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
vipinranka	12:9a20164dcc47	1105	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
vipinranka	12:9a20164dcc47	1106
vipinranka	12:9a20164dcc47	1107	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
vipinranka	12:9a20164dcc47	1108	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
vipinranka	12:9a20164dcc47	1109
vipinranka	12:9a20164dcc47	1110	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
vipinranka	12:9a20164dcc47	1111	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
vipinranka	12:9a20164dcc47	1112
vipinranka	12:9a20164dcc47	1113	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
vipinranka	12:9a20164dcc47	1114	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
vipinranka	12:9a20164dcc47	1115
vipinranka	12:9a20164dcc47	1116	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
vipinranka	12:9a20164dcc47	1117	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
vipinranka	12:9a20164dcc47	1118
vipinranka	12:9a20164dcc47	1119	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
vipinranka	12:9a20164dcc47	1120	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
vipinranka	12:9a20164dcc47	1121
vipinranka	12:9a20164dcc47	1122	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
vipinranka	12:9a20164dcc47	1123	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
vipinranka	12:9a20164dcc47	1124
vipinranka	12:9a20164dcc47	1125	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
vipinranka	12:9a20164dcc47	1126	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
vipinranka	12:9a20164dcc47	1127
vipinranka	12:9a20164dcc47	1128	/* DWT CPI Count Register Definitions */
vipinranka	12:9a20164dcc47	1129	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
vipinranka	12:9a20164dcc47	1130	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
vipinranka	12:9a20164dcc47	1131
vipinranka	12:9a20164dcc47	1132	/* DWT Exception Overhead Count Register Definitions */
vipinranka	12:9a20164dcc47	1133	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
vipinranka	12:9a20164dcc47	1134	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
vipinranka	12:9a20164dcc47	1135
vipinranka	12:9a20164dcc47	1136	/* DWT Sleep Count Register Definitions */
vipinranka	12:9a20164dcc47	1137	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
vipinranka	12:9a20164dcc47	1138	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
vipinranka	12:9a20164dcc47	1139
vipinranka	12:9a20164dcc47	1140	/* DWT LSU Count Register Definitions */
vipinranka	12:9a20164dcc47	1141	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
vipinranka	12:9a20164dcc47	1142	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
vipinranka	12:9a20164dcc47	1143
vipinranka	12:9a20164dcc47	1144	/* DWT Folded-instruction Count Register Definitions */
vipinranka	12:9a20164dcc47	1145	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
vipinranka	12:9a20164dcc47	1146	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
vipinranka	12:9a20164dcc47	1147
vipinranka	12:9a20164dcc47	1148	/* DWT Comparator Mask Register Definitions */
vipinranka	12:9a20164dcc47	1149	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
vipinranka	12:9a20164dcc47	1150	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
vipinranka	12:9a20164dcc47	1151
vipinranka	12:9a20164dcc47	1152	/* DWT Comparator Function Register Definitions */
vipinranka	12:9a20164dcc47	1153	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
vipinranka	12:9a20164dcc47	1154	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
vipinranka	12:9a20164dcc47	1155
vipinranka	12:9a20164dcc47	1156	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
vipinranka	12:9a20164dcc47	1157	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
vipinranka	12:9a20164dcc47	1158
vipinranka	12:9a20164dcc47	1159	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
vipinranka	12:9a20164dcc47	1160	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
vipinranka	12:9a20164dcc47	1161
vipinranka	12:9a20164dcc47	1162	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
vipinranka	12:9a20164dcc47	1163	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
vipinranka	12:9a20164dcc47	1164
vipinranka	12:9a20164dcc47	1165	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
vipinranka	12:9a20164dcc47	1166	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
vipinranka	12:9a20164dcc47	1167
vipinranka	12:9a20164dcc47	1168	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
vipinranka	12:9a20164dcc47	1169	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
vipinranka	12:9a20164dcc47	1170
vipinranka	12:9a20164dcc47	1171	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
vipinranka	12:9a20164dcc47	1172	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
vipinranka	12:9a20164dcc47	1173
vipinranka	12:9a20164dcc47	1174	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
vipinranka	12:9a20164dcc47	1175	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
vipinranka	12:9a20164dcc47	1176
vipinranka	12:9a20164dcc47	1177	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
vipinranka	12:9a20164dcc47	1178	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
vipinranka	12:9a20164dcc47	1179
vipinranka	12:9a20164dcc47	1180	/@}/ /* end of group CMSIS_DWT */
vipinranka	12:9a20164dcc47	1181
vipinranka	12:9a20164dcc47	1182
vipinranka	12:9a20164dcc47	1183	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	1184	\defgroup CMSIS_TPI Trace Port Interface (TPI)
vipinranka	12:9a20164dcc47	1185	\brief Type definitions for the Trace Port Interface (TPI)
vipinranka	12:9a20164dcc47	1186	@{
vipinranka	12:9a20164dcc47	1187	*/
vipinranka	12:9a20164dcc47	1188
vipinranka	12:9a20164dcc47	1189	/** \brief Structure type to access the Trace Port Interface Register (TPI).
vipinranka	12:9a20164dcc47	1190	*/
vipinranka	12:9a20164dcc47	1191	typedef struct
vipinranka	12:9a20164dcc47	1192	{
vipinranka	12:9a20164dcc47	1193	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
vipinranka	12:9a20164dcc47	1194	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
vipinranka	12:9a20164dcc47	1195	uint32_t RESERVED0[2];
vipinranka	12:9a20164dcc47	1196	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
vipinranka	12:9a20164dcc47	1197	uint32_t RESERVED1[55];
vipinranka	12:9a20164dcc47	1198	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
vipinranka	12:9a20164dcc47	1199	uint32_t RESERVED2[131];
vipinranka	12:9a20164dcc47	1200	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
vipinranka	12:9a20164dcc47	1201	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
vipinranka	12:9a20164dcc47	1202	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
vipinranka	12:9a20164dcc47	1203	uint32_t RESERVED3[759];
vipinranka	12:9a20164dcc47	1204	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
vipinranka	12:9a20164dcc47	1205	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
vipinranka	12:9a20164dcc47	1206	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
vipinranka	12:9a20164dcc47	1207	uint32_t RESERVED4[1];
vipinranka	12:9a20164dcc47	1208	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
vipinranka	12:9a20164dcc47	1209	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
vipinranka	12:9a20164dcc47	1210	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
vipinranka	12:9a20164dcc47	1211	uint32_t RESERVED5[39];
vipinranka	12:9a20164dcc47	1212	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
vipinranka	12:9a20164dcc47	1213	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
vipinranka	12:9a20164dcc47	1214	uint32_t RESERVED7[8];
vipinranka	12:9a20164dcc47	1215	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
vipinranka	12:9a20164dcc47	1216	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
vipinranka	12:9a20164dcc47	1217	} TPI_Type;
vipinranka	12:9a20164dcc47	1218
vipinranka	12:9a20164dcc47	1219	/* TPI Asynchronous Clock Prescaler Register Definitions */
vipinranka	12:9a20164dcc47	1220	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
vipinranka	12:9a20164dcc47	1221	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
vipinranka	12:9a20164dcc47	1222
vipinranka	12:9a20164dcc47	1223	/* TPI Selected Pin Protocol Register Definitions */
vipinranka	12:9a20164dcc47	1224	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
vipinranka	12:9a20164dcc47	1225	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
vipinranka	12:9a20164dcc47	1226
vipinranka	12:9a20164dcc47	1227	/* TPI Formatter and Flush Status Register Definitions */
vipinranka	12:9a20164dcc47	1228	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
vipinranka	12:9a20164dcc47	1229	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
vipinranka	12:9a20164dcc47	1230
vipinranka	12:9a20164dcc47	1231	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
vipinranka	12:9a20164dcc47	1232	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
vipinranka	12:9a20164dcc47	1233
vipinranka	12:9a20164dcc47	1234	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
vipinranka	12:9a20164dcc47	1235	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
vipinranka	12:9a20164dcc47	1236
vipinranka	12:9a20164dcc47	1237	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
vipinranka	12:9a20164dcc47	1238	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
vipinranka	12:9a20164dcc47	1239
vipinranka	12:9a20164dcc47	1240	/* TPI Formatter and Flush Control Register Definitions */
vipinranka	12:9a20164dcc47	1241	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
vipinranka	12:9a20164dcc47	1242	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
vipinranka	12:9a20164dcc47	1243
vipinranka	12:9a20164dcc47	1244	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
vipinranka	12:9a20164dcc47	1245	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
vipinranka	12:9a20164dcc47	1246
vipinranka	12:9a20164dcc47	1247	/* TPI TRIGGER Register Definitions */
vipinranka	12:9a20164dcc47	1248	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
vipinranka	12:9a20164dcc47	1249	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
vipinranka	12:9a20164dcc47	1250
vipinranka	12:9a20164dcc47	1251	/* TPI Integration ETM Data Register Definitions (FIFO0) */
vipinranka	12:9a20164dcc47	1252	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
vipinranka	12:9a20164dcc47	1253	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
vipinranka	12:9a20164dcc47	1254
vipinranka	12:9a20164dcc47	1255	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
vipinranka	12:9a20164dcc47	1256	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
vipinranka	12:9a20164dcc47	1257
vipinranka	12:9a20164dcc47	1258	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
vipinranka	12:9a20164dcc47	1259	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
vipinranka	12:9a20164dcc47	1260
vipinranka	12:9a20164dcc47	1261	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
vipinranka	12:9a20164dcc47	1262	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
vipinranka	12:9a20164dcc47	1263
vipinranka	12:9a20164dcc47	1264	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
vipinranka	12:9a20164dcc47	1265	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
vipinranka	12:9a20164dcc47	1266
vipinranka	12:9a20164dcc47	1267	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
vipinranka	12:9a20164dcc47	1268	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
vipinranka	12:9a20164dcc47	1269
vipinranka	12:9a20164dcc47	1270	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
vipinranka	12:9a20164dcc47	1271	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
vipinranka	12:9a20164dcc47	1272
vipinranka	12:9a20164dcc47	1273	/* TPI ITATBCTR2 Register Definitions */
vipinranka	12:9a20164dcc47	1274	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
vipinranka	12:9a20164dcc47	1275	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
vipinranka	12:9a20164dcc47	1276
vipinranka	12:9a20164dcc47	1277	/* TPI Integration ITM Data Register Definitions (FIFO1) */
vipinranka	12:9a20164dcc47	1278	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
vipinranka	12:9a20164dcc47	1279	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
vipinranka	12:9a20164dcc47	1280
vipinranka	12:9a20164dcc47	1281	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
vipinranka	12:9a20164dcc47	1282	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
vipinranka	12:9a20164dcc47	1283
vipinranka	12:9a20164dcc47	1284	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
vipinranka	12:9a20164dcc47	1285	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
vipinranka	12:9a20164dcc47	1286
vipinranka	12:9a20164dcc47	1287	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
vipinranka	12:9a20164dcc47	1288	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
vipinranka	12:9a20164dcc47	1289
vipinranka	12:9a20164dcc47	1290	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
vipinranka	12:9a20164dcc47	1291	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
vipinranka	12:9a20164dcc47	1292
vipinranka	12:9a20164dcc47	1293	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
vipinranka	12:9a20164dcc47	1294	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
vipinranka	12:9a20164dcc47	1295
vipinranka	12:9a20164dcc47	1296	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
vipinranka	12:9a20164dcc47	1297	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
vipinranka	12:9a20164dcc47	1298
vipinranka	12:9a20164dcc47	1299	/* TPI ITATBCTR0 Register Definitions */
vipinranka	12:9a20164dcc47	1300	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
vipinranka	12:9a20164dcc47	1301	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
vipinranka	12:9a20164dcc47	1302
vipinranka	12:9a20164dcc47	1303	/* TPI Integration Mode Control Register Definitions */
vipinranka	12:9a20164dcc47	1304	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
vipinranka	12:9a20164dcc47	1305	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
vipinranka	12:9a20164dcc47	1306
vipinranka	12:9a20164dcc47	1307	/* TPI DEVID Register Definitions */
vipinranka	12:9a20164dcc47	1308	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
vipinranka	12:9a20164dcc47	1309	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
vipinranka	12:9a20164dcc47	1310
vipinranka	12:9a20164dcc47	1311	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
vipinranka	12:9a20164dcc47	1312	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
vipinranka	12:9a20164dcc47	1313
vipinranka	12:9a20164dcc47	1314	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
vipinranka	12:9a20164dcc47	1315	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
vipinranka	12:9a20164dcc47	1316
vipinranka	12:9a20164dcc47	1317	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
vipinranka	12:9a20164dcc47	1318	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
vipinranka	12:9a20164dcc47	1319
vipinranka	12:9a20164dcc47	1320	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
vipinranka	12:9a20164dcc47	1321	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
vipinranka	12:9a20164dcc47	1322
vipinranka	12:9a20164dcc47	1323	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
vipinranka	12:9a20164dcc47	1324	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
vipinranka	12:9a20164dcc47	1325
vipinranka	12:9a20164dcc47	1326	/* TPI DEVTYPE Register Definitions */
vipinranka	12:9a20164dcc47	1327	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
vipinranka	12:9a20164dcc47	1328	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
vipinranka	12:9a20164dcc47	1329
vipinranka	12:9a20164dcc47	1330	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
vipinranka	12:9a20164dcc47	1331	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
vipinranka	12:9a20164dcc47	1332
vipinranka	12:9a20164dcc47	1333	/@}/ /* end of group CMSIS_TPI */
vipinranka	12:9a20164dcc47	1334
vipinranka	12:9a20164dcc47	1335
vipinranka	12:9a20164dcc47	1336	#if (__MPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	1337	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	1338	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
vipinranka	12:9a20164dcc47	1339	\brief Type definitions for the Memory Protection Unit (MPU)
vipinranka	12:9a20164dcc47	1340	@{
vipinranka	12:9a20164dcc47	1341	*/
vipinranka	12:9a20164dcc47	1342
vipinranka	12:9a20164dcc47	1343	/** \brief Structure type to access the Memory Protection Unit (MPU).
vipinranka	12:9a20164dcc47	1344	*/
vipinranka	12:9a20164dcc47	1345	typedef struct
vipinranka	12:9a20164dcc47	1346	{
vipinranka	12:9a20164dcc47	1347	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
vipinranka	12:9a20164dcc47	1348	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
vipinranka	12:9a20164dcc47	1349	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
vipinranka	12:9a20164dcc47	1350	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
vipinranka	12:9a20164dcc47	1351	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
vipinranka	12:9a20164dcc47	1352	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
vipinranka	12:9a20164dcc47	1353	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
vipinranka	12:9a20164dcc47	1354	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
vipinranka	12:9a20164dcc47	1355	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
vipinranka	12:9a20164dcc47	1356	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
vipinranka	12:9a20164dcc47	1357	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
vipinranka	12:9a20164dcc47	1358	} MPU_Type;
vipinranka	12:9a20164dcc47	1359
vipinranka	12:9a20164dcc47	1360	/* MPU Type Register */
vipinranka	12:9a20164dcc47	1361	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
vipinranka	12:9a20164dcc47	1362	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
vipinranka	12:9a20164dcc47	1363
vipinranka	12:9a20164dcc47	1364	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
vipinranka	12:9a20164dcc47	1365	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
vipinranka	12:9a20164dcc47	1366
vipinranka	12:9a20164dcc47	1367	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
vipinranka	12:9a20164dcc47	1368	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
vipinranka	12:9a20164dcc47	1369
vipinranka	12:9a20164dcc47	1370	/* MPU Control Register */
vipinranka	12:9a20164dcc47	1371	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
vipinranka	12:9a20164dcc47	1372	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
vipinranka	12:9a20164dcc47	1373
vipinranka	12:9a20164dcc47	1374	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
vipinranka	12:9a20164dcc47	1375	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
vipinranka	12:9a20164dcc47	1376
vipinranka	12:9a20164dcc47	1377	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
vipinranka	12:9a20164dcc47	1378	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
vipinranka	12:9a20164dcc47	1379
vipinranka	12:9a20164dcc47	1380	/* MPU Region Number Register */
vipinranka	12:9a20164dcc47	1381	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
vipinranka	12:9a20164dcc47	1382	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
vipinranka	12:9a20164dcc47	1383
vipinranka	12:9a20164dcc47	1384	/* MPU Region Base Address Register */
vipinranka	12:9a20164dcc47	1385	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
vipinranka	12:9a20164dcc47	1386	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
vipinranka	12:9a20164dcc47	1387
vipinranka	12:9a20164dcc47	1388	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
vipinranka	12:9a20164dcc47	1389	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
vipinranka	12:9a20164dcc47	1390
vipinranka	12:9a20164dcc47	1391	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
vipinranka	12:9a20164dcc47	1392	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
vipinranka	12:9a20164dcc47	1393
vipinranka	12:9a20164dcc47	1394	/* MPU Region Attribute and Size Register */
vipinranka	12:9a20164dcc47	1395	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
vipinranka	12:9a20164dcc47	1396	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
vipinranka	12:9a20164dcc47	1397
vipinranka	12:9a20164dcc47	1398	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
vipinranka	12:9a20164dcc47	1399	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
vipinranka	12:9a20164dcc47	1400
vipinranka	12:9a20164dcc47	1401	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
vipinranka	12:9a20164dcc47	1402	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
vipinranka	12:9a20164dcc47	1403
vipinranka	12:9a20164dcc47	1404	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
vipinranka	12:9a20164dcc47	1405	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
vipinranka	12:9a20164dcc47	1406
vipinranka	12:9a20164dcc47	1407	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
vipinranka	12:9a20164dcc47	1408	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
vipinranka	12:9a20164dcc47	1409
vipinranka	12:9a20164dcc47	1410	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
vipinranka	12:9a20164dcc47	1411	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
vipinranka	12:9a20164dcc47	1412
vipinranka	12:9a20164dcc47	1413	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
vipinranka	12:9a20164dcc47	1414	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
vipinranka	12:9a20164dcc47	1415
vipinranka	12:9a20164dcc47	1416	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
vipinranka	12:9a20164dcc47	1417	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
vipinranka	12:9a20164dcc47	1418
vipinranka	12:9a20164dcc47	1419	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
vipinranka	12:9a20164dcc47	1420	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
vipinranka	12:9a20164dcc47	1421
vipinranka	12:9a20164dcc47	1422	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
vipinranka	12:9a20164dcc47	1423	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
vipinranka	12:9a20164dcc47	1424
vipinranka	12:9a20164dcc47	1425	/@} end of group CMSIS_MPU /
vipinranka	12:9a20164dcc47	1426	#endif
vipinranka	12:9a20164dcc47	1427
vipinranka	12:9a20164dcc47	1428
vipinranka	12:9a20164dcc47	1429	#if (__FPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	1430	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	1431	\defgroup CMSIS_FPU Floating Point Unit (FPU)
vipinranka	12:9a20164dcc47	1432	\brief Type definitions for the Floating Point Unit (FPU)
vipinranka	12:9a20164dcc47	1433	@{
vipinranka	12:9a20164dcc47	1434	*/
vipinranka	12:9a20164dcc47	1435
vipinranka	12:9a20164dcc47	1436	/** \brief Structure type to access the Floating Point Unit (FPU).
vipinranka	12:9a20164dcc47	1437	*/
vipinranka	12:9a20164dcc47	1438	typedef struct
vipinranka	12:9a20164dcc47	1439	{
vipinranka	12:9a20164dcc47	1440	uint32_t RESERVED0[1];
vipinranka	12:9a20164dcc47	1441	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
vipinranka	12:9a20164dcc47	1442	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
vipinranka	12:9a20164dcc47	1443	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
vipinranka	12:9a20164dcc47	1444	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
vipinranka	12:9a20164dcc47	1445	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
vipinranka	12:9a20164dcc47	1446	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
vipinranka	12:9a20164dcc47	1447	} FPU_Type;
vipinranka	12:9a20164dcc47	1448
vipinranka	12:9a20164dcc47	1449	/* Floating-Point Context Control Register */
vipinranka	12:9a20164dcc47	1450	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
vipinranka	12:9a20164dcc47	1451	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
vipinranka	12:9a20164dcc47	1452
vipinranka	12:9a20164dcc47	1453	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
vipinranka	12:9a20164dcc47	1454	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
vipinranka	12:9a20164dcc47	1455
vipinranka	12:9a20164dcc47	1456	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
vipinranka	12:9a20164dcc47	1457	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
vipinranka	12:9a20164dcc47	1458
vipinranka	12:9a20164dcc47	1459	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
vipinranka	12:9a20164dcc47	1460	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
vipinranka	12:9a20164dcc47	1461
vipinranka	12:9a20164dcc47	1462	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
vipinranka	12:9a20164dcc47	1463	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
vipinranka	12:9a20164dcc47	1464
vipinranka	12:9a20164dcc47	1465	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
vipinranka	12:9a20164dcc47	1466	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
vipinranka	12:9a20164dcc47	1467
vipinranka	12:9a20164dcc47	1468	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
vipinranka	12:9a20164dcc47	1469	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
vipinranka	12:9a20164dcc47	1470
vipinranka	12:9a20164dcc47	1471	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
vipinranka	12:9a20164dcc47	1472	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
vipinranka	12:9a20164dcc47	1473
vipinranka	12:9a20164dcc47	1474	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
vipinranka	12:9a20164dcc47	1475	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
vipinranka	12:9a20164dcc47	1476
vipinranka	12:9a20164dcc47	1477	/* Floating-Point Context Address Register */
vipinranka	12:9a20164dcc47	1478	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
vipinranka	12:9a20164dcc47	1479	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
vipinranka	12:9a20164dcc47	1480
vipinranka	12:9a20164dcc47	1481	/* Floating-Point Default Status Control Register */
vipinranka	12:9a20164dcc47	1482	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
vipinranka	12:9a20164dcc47	1483	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
vipinranka	12:9a20164dcc47	1484
vipinranka	12:9a20164dcc47	1485	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
vipinranka	12:9a20164dcc47	1486	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
vipinranka	12:9a20164dcc47	1487
vipinranka	12:9a20164dcc47	1488	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
vipinranka	12:9a20164dcc47	1489	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
vipinranka	12:9a20164dcc47	1490
vipinranka	12:9a20164dcc47	1491	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
vipinranka	12:9a20164dcc47	1492	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
vipinranka	12:9a20164dcc47	1493
vipinranka	12:9a20164dcc47	1494	/* Media and FP Feature Register 0 */
vipinranka	12:9a20164dcc47	1495	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
vipinranka	12:9a20164dcc47	1496	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
vipinranka	12:9a20164dcc47	1497
vipinranka	12:9a20164dcc47	1498	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
vipinranka	12:9a20164dcc47	1499	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
vipinranka	12:9a20164dcc47	1500
vipinranka	12:9a20164dcc47	1501	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
vipinranka	12:9a20164dcc47	1502	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
vipinranka	12:9a20164dcc47	1503
vipinranka	12:9a20164dcc47	1504	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
vipinranka	12:9a20164dcc47	1505	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
vipinranka	12:9a20164dcc47	1506
vipinranka	12:9a20164dcc47	1507	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
vipinranka	12:9a20164dcc47	1508	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
vipinranka	12:9a20164dcc47	1509
vipinranka	12:9a20164dcc47	1510	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
vipinranka	12:9a20164dcc47	1511	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
vipinranka	12:9a20164dcc47	1512
vipinranka	12:9a20164dcc47	1513	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
vipinranka	12:9a20164dcc47	1514	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
vipinranka	12:9a20164dcc47	1515
vipinranka	12:9a20164dcc47	1516	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
vipinranka	12:9a20164dcc47	1517	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
vipinranka	12:9a20164dcc47	1518
vipinranka	12:9a20164dcc47	1519	/* Media and FP Feature Register 1 */
vipinranka	12:9a20164dcc47	1520	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
vipinranka	12:9a20164dcc47	1521	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
vipinranka	12:9a20164dcc47	1522
vipinranka	12:9a20164dcc47	1523	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
vipinranka	12:9a20164dcc47	1524	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
vipinranka	12:9a20164dcc47	1525
vipinranka	12:9a20164dcc47	1526	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
vipinranka	12:9a20164dcc47	1527	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
vipinranka	12:9a20164dcc47	1528
vipinranka	12:9a20164dcc47	1529	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
vipinranka	12:9a20164dcc47	1530	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
vipinranka	12:9a20164dcc47	1531
vipinranka	12:9a20164dcc47	1532	/* Media and FP Feature Register 2 */
vipinranka	12:9a20164dcc47	1533
vipinranka	12:9a20164dcc47	1534	/@} end of group CMSIS_FPU /
vipinranka	12:9a20164dcc47	1535	#endif
vipinranka	12:9a20164dcc47	1536
vipinranka	12:9a20164dcc47	1537
vipinranka	12:9a20164dcc47	1538	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	1539	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
vipinranka	12:9a20164dcc47	1540	\brief Type definitions for the Core Debug Registers
vipinranka	12:9a20164dcc47	1541	@{
vipinranka	12:9a20164dcc47	1542	*/
vipinranka	12:9a20164dcc47	1543
vipinranka	12:9a20164dcc47	1544	/** \brief Structure type to access the Core Debug Register (CoreDebug).
vipinranka	12:9a20164dcc47	1545	*/
vipinranka	12:9a20164dcc47	1546	typedef struct
vipinranka	12:9a20164dcc47	1547	{
vipinranka	12:9a20164dcc47	1548	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
vipinranka	12:9a20164dcc47	1549	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
vipinranka	12:9a20164dcc47	1550	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
vipinranka	12:9a20164dcc47	1551	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
vipinranka	12:9a20164dcc47	1552	} CoreDebug_Type;
vipinranka	12:9a20164dcc47	1553
vipinranka	12:9a20164dcc47	1554	/* Debug Halting Control and Status Register */
vipinranka	12:9a20164dcc47	1555	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
vipinranka	12:9a20164dcc47	1556	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
vipinranka	12:9a20164dcc47	1557
vipinranka	12:9a20164dcc47	1558	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
vipinranka	12:9a20164dcc47	1559	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
vipinranka	12:9a20164dcc47	1560
vipinranka	12:9a20164dcc47	1561	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
vipinranka	12:9a20164dcc47	1562	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
vipinranka	12:9a20164dcc47	1563
vipinranka	12:9a20164dcc47	1564	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
vipinranka	12:9a20164dcc47	1565	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
vipinranka	12:9a20164dcc47	1566
vipinranka	12:9a20164dcc47	1567	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
vipinranka	12:9a20164dcc47	1568	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
vipinranka	12:9a20164dcc47	1569
vipinranka	12:9a20164dcc47	1570	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
vipinranka	12:9a20164dcc47	1571	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
vipinranka	12:9a20164dcc47	1572
vipinranka	12:9a20164dcc47	1573	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
vipinranka	12:9a20164dcc47	1574	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
vipinranka	12:9a20164dcc47	1575
vipinranka	12:9a20164dcc47	1576	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
vipinranka	12:9a20164dcc47	1577	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
vipinranka	12:9a20164dcc47	1578
vipinranka	12:9a20164dcc47	1579	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
vipinranka	12:9a20164dcc47	1580	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
vipinranka	12:9a20164dcc47	1581
vipinranka	12:9a20164dcc47	1582	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
vipinranka	12:9a20164dcc47	1583	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
vipinranka	12:9a20164dcc47	1584
vipinranka	12:9a20164dcc47	1585	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
vipinranka	12:9a20164dcc47	1586	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
vipinranka	12:9a20164dcc47	1587
vipinranka	12:9a20164dcc47	1588	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
vipinranka	12:9a20164dcc47	1589	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
vipinranka	12:9a20164dcc47	1590
vipinranka	12:9a20164dcc47	1591	/* Debug Core Register Selector Register */
vipinranka	12:9a20164dcc47	1592	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
vipinranka	12:9a20164dcc47	1593	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
vipinranka	12:9a20164dcc47	1594
vipinranka	12:9a20164dcc47	1595	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
vipinranka	12:9a20164dcc47	1596	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
vipinranka	12:9a20164dcc47	1597
vipinranka	12:9a20164dcc47	1598	/* Debug Exception and Monitor Control Register */
vipinranka	12:9a20164dcc47	1599	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
vipinranka	12:9a20164dcc47	1600	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
vipinranka	12:9a20164dcc47	1601
vipinranka	12:9a20164dcc47	1602	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
vipinranka	12:9a20164dcc47	1603	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
vipinranka	12:9a20164dcc47	1604
vipinranka	12:9a20164dcc47	1605	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
vipinranka	12:9a20164dcc47	1606	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
vipinranka	12:9a20164dcc47	1607
vipinranka	12:9a20164dcc47	1608	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
vipinranka	12:9a20164dcc47	1609	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
vipinranka	12:9a20164dcc47	1610
vipinranka	12:9a20164dcc47	1611	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
vipinranka	12:9a20164dcc47	1612	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
vipinranka	12:9a20164dcc47	1613
vipinranka	12:9a20164dcc47	1614	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
vipinranka	12:9a20164dcc47	1615	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
vipinranka	12:9a20164dcc47	1616
vipinranka	12:9a20164dcc47	1617	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
vipinranka	12:9a20164dcc47	1618	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
vipinranka	12:9a20164dcc47	1619
vipinranka	12:9a20164dcc47	1620	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
vipinranka	12:9a20164dcc47	1621	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
vipinranka	12:9a20164dcc47	1622
vipinranka	12:9a20164dcc47	1623	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
vipinranka	12:9a20164dcc47	1624	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
vipinranka	12:9a20164dcc47	1625
vipinranka	12:9a20164dcc47	1626	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
vipinranka	12:9a20164dcc47	1627	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
vipinranka	12:9a20164dcc47	1628
vipinranka	12:9a20164dcc47	1629	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
vipinranka	12:9a20164dcc47	1630	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
vipinranka	12:9a20164dcc47	1631
vipinranka	12:9a20164dcc47	1632	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
vipinranka	12:9a20164dcc47	1633	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
vipinranka	12:9a20164dcc47	1634
vipinranka	12:9a20164dcc47	1635	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
vipinranka	12:9a20164dcc47	1636	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
vipinranka	12:9a20164dcc47	1637
vipinranka	12:9a20164dcc47	1638	/@} end of group CMSIS_CoreDebug /
vipinranka	12:9a20164dcc47	1639
vipinranka	12:9a20164dcc47	1640
vipinranka	12:9a20164dcc47	1641	/** \ingroup CMSIS_core_register
vipinranka	12:9a20164dcc47	1642	\defgroup CMSIS_core_base Core Definitions
vipinranka	12:9a20164dcc47	1643	\brief Definitions for base addresses, unions, and structures.
vipinranka	12:9a20164dcc47	1644	@{
vipinranka	12:9a20164dcc47	1645	*/
vipinranka	12:9a20164dcc47	1646
vipinranka	12:9a20164dcc47	1647	/* Memory mapping of Cortex-M4 Hardware */
vipinranka	12:9a20164dcc47	1648	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
vipinranka	12:9a20164dcc47	1649	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
vipinranka	12:9a20164dcc47	1650	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
vipinranka	12:9a20164dcc47	1651	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
vipinranka	12:9a20164dcc47	1652	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
vipinranka	12:9a20164dcc47	1653	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
vipinranka	12:9a20164dcc47	1654	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
vipinranka	12:9a20164dcc47	1655	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
vipinranka	12:9a20164dcc47	1656
vipinranka	12:9a20164dcc47	1657	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
vipinranka	12:9a20164dcc47	1658	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
vipinranka	12:9a20164dcc47	1659	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
vipinranka	12:9a20164dcc47	1660	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
vipinranka	12:9a20164dcc47	1661	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
vipinranka	12:9a20164dcc47	1662	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
vipinranka	12:9a20164dcc47	1663	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
vipinranka	12:9a20164dcc47	1664	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
vipinranka	12:9a20164dcc47	1665
vipinranka	12:9a20164dcc47	1666	#if (__MPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	1667	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
vipinranka	12:9a20164dcc47	1668	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
vipinranka	12:9a20164dcc47	1669	#endif
vipinranka	12:9a20164dcc47	1670
vipinranka	12:9a20164dcc47	1671	#if (__FPU_PRESENT == 1)
vipinranka	12:9a20164dcc47	1672	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
vipinranka	12:9a20164dcc47	1673	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
vipinranka	12:9a20164dcc47	1674	#endif
vipinranka	12:9a20164dcc47	1675
vipinranka	12:9a20164dcc47	1676	/@} /
vipinranka	12:9a20164dcc47	1677
vipinranka	12:9a20164dcc47	1678
vipinranka	12:9a20164dcc47	1679
vipinranka	12:9a20164dcc47	1680	/*******************************************************************************
vipinranka	12:9a20164dcc47	1681	* Hardware Abstraction Layer
vipinranka	12:9a20164dcc47	1682	Core Function Interface contains:
vipinranka	12:9a20164dcc47	1683	- Core NVIC Functions
vipinranka	12:9a20164dcc47	1684	- Core SysTick Functions
vipinranka	12:9a20164dcc47	1685	- Core Debug Functions
vipinranka	12:9a20164dcc47	1686	- Core Register Access Functions
vipinranka	12:9a20164dcc47	1687	******************************************************************************/
vipinranka	12:9a20164dcc47	1688	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
vipinranka	12:9a20164dcc47	1689	*/
vipinranka	12:9a20164dcc47	1690
vipinranka	12:9a20164dcc47	1691
vipinranka	12:9a20164dcc47	1692
vipinranka	12:9a20164dcc47	1693	/* ########################## NVIC functions #################################### */
vipinranka	12:9a20164dcc47	1694	/** \ingroup CMSIS_Core_FunctionInterface
vipinranka	12:9a20164dcc47	1695	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
vipinranka	12:9a20164dcc47	1696	\brief Functions that manage interrupts and exceptions via the NVIC.
vipinranka	12:9a20164dcc47	1697	@{
vipinranka	12:9a20164dcc47	1698	*/
vipinranka	12:9a20164dcc47	1699
vipinranka	12:9a20164dcc47	1700	/** \brief Set Priority Grouping
vipinranka	12:9a20164dcc47	1701
vipinranka	12:9a20164dcc47	1702	The function sets the priority grouping field using the required unlock sequence.
vipinranka	12:9a20164dcc47	1703	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
vipinranka	12:9a20164dcc47	1704	Only values from 0..7 are used.
vipinranka	12:9a20164dcc47	1705	In case of a conflict between priority grouping and available
vipinranka	12:9a20164dcc47	1706	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
vipinranka	12:9a20164dcc47	1707
vipinranka	12:9a20164dcc47	1708	\param [in] PriorityGroup Priority grouping field.
vipinranka	12:9a20164dcc47	1709	*/
vipinranka	12:9a20164dcc47	1710	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
vipinranka	12:9a20164dcc47	1711	{
vipinranka	12:9a20164dcc47	1712	uint32_t reg_value;
vipinranka	12:9a20164dcc47	1713	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vipinranka	12:9a20164dcc47	1714
vipinranka	12:9a20164dcc47	1715	reg_value = SCB->AIRCR; /* read old register configuration */
vipinranka	12:9a20164dcc47	1716	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
vipinranka	12:9a20164dcc47	1717	reg_value = (reg_value \|
vipinranka	12:9a20164dcc47	1718	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
vipinranka	12:9a20164dcc47	1719	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
vipinranka	12:9a20164dcc47	1720	SCB->AIRCR = reg_value;
vipinranka	12:9a20164dcc47	1721	}
vipinranka	12:9a20164dcc47	1722
vipinranka	12:9a20164dcc47	1723
vipinranka	12:9a20164dcc47	1724	/** \brief Get Priority Grouping
vipinranka	12:9a20164dcc47	1725
vipinranka	12:9a20164dcc47	1726	The function reads the priority grouping field from the NVIC Interrupt Controller.
vipinranka	12:9a20164dcc47	1727
vipinranka	12:9a20164dcc47	1728	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
vipinranka	12:9a20164dcc47	1729	*/
vipinranka	12:9a20164dcc47	1730	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
vipinranka	12:9a20164dcc47	1731	{
vipinranka	12:9a20164dcc47	1732	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
vipinranka	12:9a20164dcc47	1733	}
vipinranka	12:9a20164dcc47	1734
vipinranka	12:9a20164dcc47	1735
vipinranka	12:9a20164dcc47	1736	/** \brief Enable External Interrupt
vipinranka	12:9a20164dcc47	1737
vipinranka	12:9a20164dcc47	1738	The function enables a device-specific interrupt in the NVIC interrupt controller.
vipinranka	12:9a20164dcc47	1739
vipinranka	12:9a20164dcc47	1740	\param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka	12:9a20164dcc47	1741	*/
vipinranka	12:9a20164dcc47	1742	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
vipinranka	12:9a20164dcc47	1743	{
vipinranka	12:9a20164dcc47	1744	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka	12:9a20164dcc47	1745	}
vipinranka	12:9a20164dcc47	1746
vipinranka	12:9a20164dcc47	1747
vipinranka	12:9a20164dcc47	1748	/** \brief Disable External Interrupt
vipinranka	12:9a20164dcc47	1749
vipinranka	12:9a20164dcc47	1750	The function disables a device-specific interrupt in the NVIC interrupt controller.
vipinranka	12:9a20164dcc47	1751
vipinranka	12:9a20164dcc47	1752	\param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka	12:9a20164dcc47	1753	*/
vipinranka	12:9a20164dcc47	1754	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
vipinranka	12:9a20164dcc47	1755	{
vipinranka	12:9a20164dcc47	1756	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka	12:9a20164dcc47	1757	__DSB();
vipinranka	12:9a20164dcc47	1758	__ISB();
vipinranka	12:9a20164dcc47	1759	}
vipinranka	12:9a20164dcc47	1760
vipinranka	12:9a20164dcc47	1761
vipinranka	12:9a20164dcc47	1762	/** \brief Get Pending Interrupt
vipinranka	12:9a20164dcc47	1763
vipinranka	12:9a20164dcc47	1764	The function reads the pending register in the NVIC and returns the pending bit
vipinranka	12:9a20164dcc47	1765	for the specified interrupt.
vipinranka	12:9a20164dcc47	1766
vipinranka	12:9a20164dcc47	1767	\param [in] IRQn Interrupt number.
vipinranka	12:9a20164dcc47	1768
vipinranka	12:9a20164dcc47	1769	\return 0 Interrupt status is not pending.
vipinranka	12:9a20164dcc47	1770	\return 1 Interrupt status is pending.
vipinranka	12:9a20164dcc47	1771	*/
vipinranka	12:9a20164dcc47	1772	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
vipinranka	12:9a20164dcc47	1773	{
vipinranka	12:9a20164dcc47	1774	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vipinranka	12:9a20164dcc47	1775	}
vipinranka	12:9a20164dcc47	1776
vipinranka	12:9a20164dcc47	1777
vipinranka	12:9a20164dcc47	1778	/** \brief Set Pending Interrupt
vipinranka	12:9a20164dcc47	1779
vipinranka	12:9a20164dcc47	1780	The function sets the pending bit of an external interrupt.
vipinranka	12:9a20164dcc47	1781
vipinranka	12:9a20164dcc47	1782	\param [in] IRQn Interrupt number. Value cannot be negative.
vipinranka	12:9a20164dcc47	1783	*/
vipinranka	12:9a20164dcc47	1784	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
vipinranka	12:9a20164dcc47	1785	{
vipinranka	12:9a20164dcc47	1786	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka	12:9a20164dcc47	1787	}
vipinranka	12:9a20164dcc47	1788
vipinranka	12:9a20164dcc47	1789
vipinranka	12:9a20164dcc47	1790	/** \brief Clear Pending Interrupt
vipinranka	12:9a20164dcc47	1791
vipinranka	12:9a20164dcc47	1792	The function clears the pending bit of an external interrupt.
vipinranka	12:9a20164dcc47	1793
vipinranka	12:9a20164dcc47	1794	\param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka	12:9a20164dcc47	1795	*/
vipinranka	12:9a20164dcc47	1796	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
vipinranka	12:9a20164dcc47	1797	{
vipinranka	12:9a20164dcc47	1798	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka	12:9a20164dcc47	1799	}
vipinranka	12:9a20164dcc47	1800
vipinranka	12:9a20164dcc47	1801
vipinranka	12:9a20164dcc47	1802	/** \brief Get Active Interrupt
vipinranka	12:9a20164dcc47	1803
vipinranka	12:9a20164dcc47	1804	The function reads the active register in NVIC and returns the active bit.
vipinranka	12:9a20164dcc47	1805
vipinranka	12:9a20164dcc47	1806	\param [in] IRQn Interrupt number.
vipinranka	12:9a20164dcc47	1807
vipinranka	12:9a20164dcc47	1808	\return 0 Interrupt status is not active.
vipinranka	12:9a20164dcc47	1809	\return 1 Interrupt status is active.
vipinranka	12:9a20164dcc47	1810	*/
vipinranka	12:9a20164dcc47	1811	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
vipinranka	12:9a20164dcc47	1812	{
vipinranka	12:9a20164dcc47	1813	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vipinranka	12:9a20164dcc47	1814	}
vipinranka	12:9a20164dcc47	1815
vipinranka	12:9a20164dcc47	1816
vipinranka	12:9a20164dcc47	1817	/** \brief Set Interrupt Priority
vipinranka	12:9a20164dcc47	1818
vipinranka	12:9a20164dcc47	1819	The function sets the priority of an interrupt.
vipinranka	12:9a20164dcc47	1820
vipinranka	12:9a20164dcc47	1821	\note The priority cannot be set for every core interrupt.
vipinranka	12:9a20164dcc47	1822
vipinranka	12:9a20164dcc47	1823	\param [in] IRQn Interrupt number.
vipinranka	12:9a20164dcc47	1824	\param [in] priority Priority to set.
vipinranka	12:9a20164dcc47	1825	*/
vipinranka	12:9a20164dcc47	1826	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
vipinranka	12:9a20164dcc47	1827	{
vipinranka	12:9a20164dcc47	1828	if((int32_t)IRQn < 0) {
vipinranka	12:9a20164dcc47	1829	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
vipinranka	12:9a20164dcc47	1830	}
vipinranka	12:9a20164dcc47	1831	else {
vipinranka	12:9a20164dcc47	1832	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
vipinranka	12:9a20164dcc47	1833	}
vipinranka	12:9a20164dcc47	1834	}
vipinranka	12:9a20164dcc47	1835
vipinranka	12:9a20164dcc47	1836
vipinranka	12:9a20164dcc47	1837	/** \brief Get Interrupt Priority
vipinranka	12:9a20164dcc47	1838
vipinranka	12:9a20164dcc47	1839	The function reads the priority of an interrupt. The interrupt
vipinranka	12:9a20164dcc47	1840	number can be positive to specify an external (device specific)
vipinranka	12:9a20164dcc47	1841	interrupt, or negative to specify an internal (core) interrupt.
vipinranka	12:9a20164dcc47	1842
vipinranka	12:9a20164dcc47	1843
vipinranka	12:9a20164dcc47	1844	\param [in] IRQn Interrupt number.
vipinranka	12:9a20164dcc47	1845	\return Interrupt Priority. Value is aligned automatically to the implemented
vipinranka	12:9a20164dcc47	1846	priority bits of the microcontroller.
vipinranka	12:9a20164dcc47	1847	*/
vipinranka	12:9a20164dcc47	1848	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
vipinranka	12:9a20164dcc47	1849	{
vipinranka	12:9a20164dcc47	1850
vipinranka	12:9a20164dcc47	1851	if((int32_t)IRQn < 0) {
vipinranka	12:9a20164dcc47	1852	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
vipinranka	12:9a20164dcc47	1853	}
vipinranka	12:9a20164dcc47	1854	else {
vipinranka	12:9a20164dcc47	1855	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
vipinranka	12:9a20164dcc47	1856	}
vipinranka	12:9a20164dcc47	1857	}
vipinranka	12:9a20164dcc47	1858
vipinranka	12:9a20164dcc47	1859
vipinranka	12:9a20164dcc47	1860	/** \brief Encode Priority
vipinranka	12:9a20164dcc47	1861
vipinranka	12:9a20164dcc47	1862	The function encodes the priority for an interrupt with the given priority group,
vipinranka	12:9a20164dcc47	1863	preemptive priority value, and subpriority value.
vipinranka	12:9a20164dcc47	1864	In case of a conflict between priority grouping and available
vipinranka	12:9a20164dcc47	1865	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
vipinranka	12:9a20164dcc47	1866
vipinranka	12:9a20164dcc47	1867	\param [in] PriorityGroup Used priority group.
vipinranka	12:9a20164dcc47	1868	\param [in] PreemptPriority Preemptive priority value (starting from 0).
vipinranka	12:9a20164dcc47	1869	\param [in] SubPriority Subpriority value (starting from 0).
vipinranka	12:9a20164dcc47	1870	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
vipinranka	12:9a20164dcc47	1871	*/
vipinranka	12:9a20164dcc47	1872	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
vipinranka	12:9a20164dcc47	1873	{
vipinranka	12:9a20164dcc47	1874	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vipinranka	12:9a20164dcc47	1875	uint32_t PreemptPriorityBits;
vipinranka	12:9a20164dcc47	1876	uint32_t SubPriorityBits;
vipinranka	12:9a20164dcc47	1877
vipinranka	12:9a20164dcc47	1878	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
vipinranka	12:9a20164dcc47	1879	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
vipinranka	12:9a20164dcc47	1880
vipinranka	12:9a20164dcc47	1881	return (
vipinranka	12:9a20164dcc47	1882	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
vipinranka	12:9a20164dcc47	1883	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
vipinranka	12:9a20164dcc47	1884	);
vipinranka	12:9a20164dcc47	1885	}
vipinranka	12:9a20164dcc47	1886
vipinranka	12:9a20164dcc47	1887
vipinranka	12:9a20164dcc47	1888	/** \brief Decode Priority
vipinranka	12:9a20164dcc47	1889
vipinranka	12:9a20164dcc47	1890	The function decodes an interrupt priority value with a given priority group to
vipinranka	12:9a20164dcc47	1891	preemptive priority value and subpriority value.
vipinranka	12:9a20164dcc47	1892	In case of a conflict between priority grouping and available
vipinranka	12:9a20164dcc47	1893	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
vipinranka	12:9a20164dcc47	1894
vipinranka	12:9a20164dcc47	1895	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
vipinranka	12:9a20164dcc47	1896	\param [in] PriorityGroup Used priority group.
vipinranka	12:9a20164dcc47	1897	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
vipinranka	12:9a20164dcc47	1898	\param [out] pSubPriority Subpriority value (starting from 0).
vipinranka	12:9a20164dcc47	1899	*/
vipinranka	12:9a20164dcc47	1900	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
vipinranka	12:9a20164dcc47	1901	{
vipinranka	12:9a20164dcc47	1902	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
vipinranka	12:9a20164dcc47	1903	uint32_t PreemptPriorityBits;
vipinranka	12:9a20164dcc47	1904	uint32_t SubPriorityBits;
vipinranka	12:9a20164dcc47	1905
vipinranka	12:9a20164dcc47	1906	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
vipinranka	12:9a20164dcc47	1907	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
vipinranka	12:9a20164dcc47	1908
vipinranka	12:9a20164dcc47	1909	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
vipinranka	12:9a20164dcc47	1910	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
vipinranka	12:9a20164dcc47	1911	}
vipinranka	12:9a20164dcc47	1912
vipinranka	12:9a20164dcc47	1913
vipinranka	12:9a20164dcc47	1914	/** \brief System Reset
vipinranka	12:9a20164dcc47	1915
vipinranka	12:9a20164dcc47	1916	The function initiates a system reset request to reset the MCU.
vipinranka	12:9a20164dcc47	1917	*/
vipinranka	12:9a20164dcc47	1918	__STATIC_INLINE void NVIC_SystemReset(void)
vipinranka	12:9a20164dcc47	1919	{
vipinranka	12:9a20164dcc47	1920	__DSB(); /* Ensure all outstanding memory accesses included
vipinranka	12:9a20164dcc47	1921	buffered write are completed before reset */
vipinranka	12:9a20164dcc47	1922	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
vipinranka	12:9a20164dcc47	1923	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
vipinranka	12:9a20164dcc47	1924	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
vipinranka	12:9a20164dcc47	1925	__DSB(); /* Ensure completion of memory access */
vipinranka	12:9a20164dcc47	1926	while(1) { __NOP(); } /* wait until reset */
vipinranka	12:9a20164dcc47	1927	}
vipinranka	12:9a20164dcc47	1928
vipinranka	12:9a20164dcc47	1929	/@} end of CMSIS_Core_NVICFunctions /
vipinranka	12:9a20164dcc47	1930
vipinranka	12:9a20164dcc47	1931
vipinranka	12:9a20164dcc47	1932	/* ########################## FPU functions #################################### */
vipinranka	12:9a20164dcc47	1933	/** \ingroup CMSIS_Core_FunctionInterface
vipinranka	12:9a20164dcc47	1934	\defgroup CMSIS_Core_FpuFunctions FPU Functions
vipinranka	12:9a20164dcc47	1935	\brief Function that provides FPU type.
vipinranka	12:9a20164dcc47	1936	@{
vipinranka	12:9a20164dcc47	1937	*/
vipinranka	12:9a20164dcc47	1938
vipinranka	12:9a20164dcc47	1939	/**
vipinranka	12:9a20164dcc47	1940	\fn uint32_t SCB_GetFPUType(void)
vipinranka	12:9a20164dcc47	1941	\brief get FPU type
vipinranka	12:9a20164dcc47	1942	\returns
vipinranka	12:9a20164dcc47	1943	- \b 0: No FPU
vipinranka	12:9a20164dcc47	1944	- \b 1: Single precision FPU
vipinranka	12:9a20164dcc47	1945	- \b 2: Double + Single precision FPU
vipinranka	12:9a20164dcc47	1946	*/
vipinranka	12:9a20164dcc47	1947	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
vipinranka	12:9a20164dcc47	1948	{
vipinranka	12:9a20164dcc47	1949	uint32_t mvfr0;
vipinranka	12:9a20164dcc47	1950
vipinranka	12:9a20164dcc47	1951	mvfr0 = SCB->MVFR0;
vipinranka	12:9a20164dcc47	1952	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
vipinranka	12:9a20164dcc47	1953	return 2UL; // Double + Single precision FPU
vipinranka	12:9a20164dcc47	1954	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
vipinranka	12:9a20164dcc47	1955	return 1UL; // Single precision FPU
vipinranka	12:9a20164dcc47	1956	} else {
vipinranka	12:9a20164dcc47	1957	return 0UL; // No FPU
vipinranka	12:9a20164dcc47	1958	}
vipinranka	12:9a20164dcc47	1959	}
vipinranka	12:9a20164dcc47	1960
vipinranka	12:9a20164dcc47	1961
vipinranka	12:9a20164dcc47	1962	/@} end of CMSIS_Core_FpuFunctions /
vipinranka	12:9a20164dcc47	1963
vipinranka	12:9a20164dcc47	1964
vipinranka	12:9a20164dcc47	1965
vipinranka	12:9a20164dcc47	1966	/* ########################## Cache functions #################################### */
vipinranka	12:9a20164dcc47	1967	/** \ingroup CMSIS_Core_FunctionInterface
vipinranka	12:9a20164dcc47	1968	\defgroup CMSIS_Core_CacheFunctions Cache Functions
vipinranka	12:9a20164dcc47	1969	\brief Functions that configure Instruction and Data cache.
vipinranka	12:9a20164dcc47	1970	@{
vipinranka	12:9a20164dcc47	1971	*/
vipinranka	12:9a20164dcc47	1972
vipinranka	12:9a20164dcc47	1973	/* Cache Size ID Register Macros */
vipinranka	12:9a20164dcc47	1974	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
vipinranka	12:9a20164dcc47	1975	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
vipinranka	12:9a20164dcc47	1976	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
vipinranka	12:9a20164dcc47	1977
vipinranka	12:9a20164dcc47	1978
vipinranka	12:9a20164dcc47	1979	/** \brief Enable I-Cache
vipinranka	12:9a20164dcc47	1980
vipinranka	12:9a20164dcc47	1981	The function turns on I-Cache
vipinranka	12:9a20164dcc47	1982	*/
vipinranka	12:9a20164dcc47	1983	__STATIC_INLINE void SCB_EnableICache (void)
vipinranka	12:9a20164dcc47	1984	{
vipinranka	12:9a20164dcc47	1985	#if (__ICACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	1986	__DSB();
vipinranka	12:9a20164dcc47	1987	__ISB();
vipinranka	12:9a20164dcc47	1988	SCB->ICIALLU = 0UL; // invalidate I-Cache
vipinranka	12:9a20164dcc47	1989	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
vipinranka	12:9a20164dcc47	1990	__DSB();
vipinranka	12:9a20164dcc47	1991	__ISB();
vipinranka	12:9a20164dcc47	1992	#endif
vipinranka	12:9a20164dcc47	1993	}
vipinranka	12:9a20164dcc47	1994
vipinranka	12:9a20164dcc47	1995
vipinranka	12:9a20164dcc47	1996	/** \brief Disable I-Cache
vipinranka	12:9a20164dcc47	1997
vipinranka	12:9a20164dcc47	1998	The function turns off I-Cache
vipinranka	12:9a20164dcc47	1999	*/
vipinranka	12:9a20164dcc47	2000	__STATIC_INLINE void SCB_DisableICache (void)
vipinranka	12:9a20164dcc47	2001	{
vipinranka	12:9a20164dcc47	2002	#if (__ICACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2003	__DSB();
vipinranka	12:9a20164dcc47	2004	__ISB();
vipinranka	12:9a20164dcc47	2005	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
vipinranka	12:9a20164dcc47	2006	SCB->ICIALLU = 0UL; // invalidate I-Cache
vipinranka	12:9a20164dcc47	2007	__DSB();
vipinranka	12:9a20164dcc47	2008	__ISB();
vipinranka	12:9a20164dcc47	2009	#endif
vipinranka	12:9a20164dcc47	2010	}
vipinranka	12:9a20164dcc47	2011
vipinranka	12:9a20164dcc47	2012
vipinranka	12:9a20164dcc47	2013	/** \brief Invalidate I-Cache
vipinranka	12:9a20164dcc47	2014
vipinranka	12:9a20164dcc47	2015	The function invalidates I-Cache
vipinranka	12:9a20164dcc47	2016	*/
vipinranka	12:9a20164dcc47	2017	__STATIC_INLINE void SCB_InvalidateICache (void)
vipinranka	12:9a20164dcc47	2018	{
vipinranka	12:9a20164dcc47	2019	#if (__ICACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2020	__DSB();
vipinranka	12:9a20164dcc47	2021	__ISB();
vipinranka	12:9a20164dcc47	2022	SCB->ICIALLU = 0UL;
vipinranka	12:9a20164dcc47	2023	__DSB();
vipinranka	12:9a20164dcc47	2024	__ISB();
vipinranka	12:9a20164dcc47	2025	#endif
vipinranka	12:9a20164dcc47	2026	}
vipinranka	12:9a20164dcc47	2027
vipinranka	12:9a20164dcc47	2028
vipinranka	12:9a20164dcc47	2029	/** \brief Enable D-Cache
vipinranka	12:9a20164dcc47	2030
vipinranka	12:9a20164dcc47	2031	The function turns on D-Cache
vipinranka	12:9a20164dcc47	2032	*/
vipinranka	12:9a20164dcc47	2033	__STATIC_INLINE void SCB_EnableDCache (void)
vipinranka	12:9a20164dcc47	2034	{
vipinranka	12:9a20164dcc47	2035	#if (__DCACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2036	uint32_t ccsidr, sshift, wshift, sw;
vipinranka	12:9a20164dcc47	2037	uint32_t sets, ways;
vipinranka	12:9a20164dcc47	2038
vipinranka	12:9a20164dcc47	2039	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
vipinranka	12:9a20164dcc47	2040	ccsidr = SCB->CCSIDR;
vipinranka	12:9a20164dcc47	2041	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vipinranka	12:9a20164dcc47	2042	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vipinranka	12:9a20164dcc47	2043	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vipinranka	12:9a20164dcc47	2044	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vipinranka	12:9a20164dcc47	2045
vipinranka	12:9a20164dcc47	2046	__DSB();
vipinranka	12:9a20164dcc47	2047
vipinranka	12:9a20164dcc47	2048	do { // invalidate D-Cache
vipinranka	12:9a20164dcc47	2049	uint32_t tmpways = ways;
vipinranka	12:9a20164dcc47	2050	do {
vipinranka	12:9a20164dcc47	2051	sw = ((tmpways << wshift) \| (sets << sshift));
vipinranka	12:9a20164dcc47	2052	SCB->DCISW = sw;
vipinranka	12:9a20164dcc47	2053	} while(tmpways--);
vipinranka	12:9a20164dcc47	2054	} while(sets--);
vipinranka	12:9a20164dcc47	2055	__DSB();
vipinranka	12:9a20164dcc47	2056
vipinranka	12:9a20164dcc47	2057	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
vipinranka	12:9a20164dcc47	2058
vipinranka	12:9a20164dcc47	2059	__DSB();
vipinranka	12:9a20164dcc47	2060	__ISB();
vipinranka	12:9a20164dcc47	2061	#endif
vipinranka	12:9a20164dcc47	2062	}
vipinranka	12:9a20164dcc47	2063
vipinranka	12:9a20164dcc47	2064
vipinranka	12:9a20164dcc47	2065	/** \brief Disable D-Cache
vipinranka	12:9a20164dcc47	2066
vipinranka	12:9a20164dcc47	2067	The function turns off D-Cache
vipinranka	12:9a20164dcc47	2068	*/
vipinranka	12:9a20164dcc47	2069	__STATIC_INLINE void SCB_DisableDCache (void)
vipinranka	12:9a20164dcc47	2070	{
vipinranka	12:9a20164dcc47	2071	#if (__DCACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2072	uint32_t ccsidr, sshift, wshift, sw;
vipinranka	12:9a20164dcc47	2073	uint32_t sets, ways;
vipinranka	12:9a20164dcc47	2074
vipinranka	12:9a20164dcc47	2075	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
vipinranka	12:9a20164dcc47	2076	ccsidr = SCB->CCSIDR;
vipinranka	12:9a20164dcc47	2077	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vipinranka	12:9a20164dcc47	2078	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vipinranka	12:9a20164dcc47	2079	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vipinranka	12:9a20164dcc47	2080	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vipinranka	12:9a20164dcc47	2081
vipinranka	12:9a20164dcc47	2082	__DSB();
vipinranka	12:9a20164dcc47	2083
vipinranka	12:9a20164dcc47	2084	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
vipinranka	12:9a20164dcc47	2085
vipinranka	12:9a20164dcc47	2086	do { // clean & invalidate D-Cache
vipinranka	12:9a20164dcc47	2087	uint32_t tmpways = ways;
vipinranka	12:9a20164dcc47	2088	do {
vipinranka	12:9a20164dcc47	2089	sw = ((tmpways << wshift) \| (sets << sshift));
vipinranka	12:9a20164dcc47	2090	SCB->DCCISW = sw;
vipinranka	12:9a20164dcc47	2091	} while(tmpways--);
vipinranka	12:9a20164dcc47	2092	} while(sets--);
vipinranka	12:9a20164dcc47	2093
vipinranka	12:9a20164dcc47	2094
vipinranka	12:9a20164dcc47	2095	__DSB();
vipinranka	12:9a20164dcc47	2096	__ISB();
vipinranka	12:9a20164dcc47	2097	#endif
vipinranka	12:9a20164dcc47	2098	}
vipinranka	12:9a20164dcc47	2099
vipinranka	12:9a20164dcc47	2100
vipinranka	12:9a20164dcc47	2101	/** \brief Invalidate D-Cache
vipinranka	12:9a20164dcc47	2102
vipinranka	12:9a20164dcc47	2103	The function invalidates D-Cache
vipinranka	12:9a20164dcc47	2104	*/
vipinranka	12:9a20164dcc47	2105	__STATIC_INLINE void SCB_InvalidateDCache (void)
vipinranka	12:9a20164dcc47	2106	{
vipinranka	12:9a20164dcc47	2107	#if (__DCACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2108	uint32_t ccsidr, sshift, wshift, sw;
vipinranka	12:9a20164dcc47	2109	uint32_t sets, ways;
vipinranka	12:9a20164dcc47	2110
vipinranka	12:9a20164dcc47	2111	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
vipinranka	12:9a20164dcc47	2112	ccsidr = SCB->CCSIDR;
vipinranka	12:9a20164dcc47	2113	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vipinranka	12:9a20164dcc47	2114	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vipinranka	12:9a20164dcc47	2115	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vipinranka	12:9a20164dcc47	2116	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vipinranka	12:9a20164dcc47	2117
vipinranka	12:9a20164dcc47	2118	__DSB();
vipinranka	12:9a20164dcc47	2119
vipinranka	12:9a20164dcc47	2120	do { // invalidate D-Cache
vipinranka	12:9a20164dcc47	2121	uint32_t tmpways = ways;
vipinranka	12:9a20164dcc47	2122	do {
vipinranka	12:9a20164dcc47	2123	sw = ((tmpways << wshift) \| (sets << sshift));
vipinranka	12:9a20164dcc47	2124	SCB->DCISW = sw;
vipinranka	12:9a20164dcc47	2125	} while(tmpways--);
vipinranka	12:9a20164dcc47	2126	} while(sets--);
vipinranka	12:9a20164dcc47	2127
vipinranka	12:9a20164dcc47	2128	__DSB();
vipinranka	12:9a20164dcc47	2129	__ISB();
vipinranka	12:9a20164dcc47	2130	#endif
vipinranka	12:9a20164dcc47	2131	}
vipinranka	12:9a20164dcc47	2132
vipinranka	12:9a20164dcc47	2133
vipinranka	12:9a20164dcc47	2134	/** \brief Clean D-Cache
vipinranka	12:9a20164dcc47	2135
vipinranka	12:9a20164dcc47	2136	The function cleans D-Cache
vipinranka	12:9a20164dcc47	2137	*/
vipinranka	12:9a20164dcc47	2138	__STATIC_INLINE void SCB_CleanDCache (void)
vipinranka	12:9a20164dcc47	2139	{
vipinranka	12:9a20164dcc47	2140	#if (__DCACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2141	uint32_t ccsidr, sshift, wshift, sw;
vipinranka	12:9a20164dcc47	2142	uint32_t sets, ways;
vipinranka	12:9a20164dcc47	2143
vipinranka	12:9a20164dcc47	2144	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
vipinranka	12:9a20164dcc47	2145	ccsidr = SCB->CCSIDR;
vipinranka	12:9a20164dcc47	2146	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vipinranka	12:9a20164dcc47	2147	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vipinranka	12:9a20164dcc47	2148	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vipinranka	12:9a20164dcc47	2149	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vipinranka	12:9a20164dcc47	2150
vipinranka	12:9a20164dcc47	2151	__DSB();
vipinranka	12:9a20164dcc47	2152
vipinranka	12:9a20164dcc47	2153	do { // clean D-Cache
vipinranka	12:9a20164dcc47	2154	uint32_t tmpways = ways;
vipinranka	12:9a20164dcc47	2155	do {
vipinranka	12:9a20164dcc47	2156	sw = ((tmpways << wshift) \| (sets << sshift));
vipinranka	12:9a20164dcc47	2157	SCB->DCCSW = sw;
vipinranka	12:9a20164dcc47	2158	} while(tmpways--);
vipinranka	12:9a20164dcc47	2159	} while(sets--);
vipinranka	12:9a20164dcc47	2160
vipinranka	12:9a20164dcc47	2161	__DSB();
vipinranka	12:9a20164dcc47	2162	__ISB();
vipinranka	12:9a20164dcc47	2163	#endif
vipinranka	12:9a20164dcc47	2164	}
vipinranka	12:9a20164dcc47	2165
vipinranka	12:9a20164dcc47	2166
vipinranka	12:9a20164dcc47	2167	/** \brief Clean & Invalidate D-Cache
vipinranka	12:9a20164dcc47	2168
vipinranka	12:9a20164dcc47	2169	The function cleans and Invalidates D-Cache
vipinranka	12:9a20164dcc47	2170	*/
vipinranka	12:9a20164dcc47	2171	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
vipinranka	12:9a20164dcc47	2172	{
vipinranka	12:9a20164dcc47	2173	#if (__DCACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2174	uint32_t ccsidr, sshift, wshift, sw;
vipinranka	12:9a20164dcc47	2175	uint32_t sets, ways;
vipinranka	12:9a20164dcc47	2176
vipinranka	12:9a20164dcc47	2177	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
vipinranka	12:9a20164dcc47	2178	ccsidr = SCB->CCSIDR;
vipinranka	12:9a20164dcc47	2179	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
vipinranka	12:9a20164dcc47	2180	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
vipinranka	12:9a20164dcc47	2181	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
vipinranka	12:9a20164dcc47	2182	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
vipinranka	12:9a20164dcc47	2183
vipinranka	12:9a20164dcc47	2184	__DSB();
vipinranka	12:9a20164dcc47	2185
vipinranka	12:9a20164dcc47	2186	do { // clean & invalidate D-Cache
vipinranka	12:9a20164dcc47	2187	uint32_t tmpways = ways;
vipinranka	12:9a20164dcc47	2188	do {
vipinranka	12:9a20164dcc47	2189	sw = ((tmpways << wshift) \| (sets << sshift));
vipinranka	12:9a20164dcc47	2190	SCB->DCCISW = sw;
vipinranka	12:9a20164dcc47	2191	} while(tmpways--);
vipinranka	12:9a20164dcc47	2192	} while(sets--);
vipinranka	12:9a20164dcc47	2193
vipinranka	12:9a20164dcc47	2194	__DSB();
vipinranka	12:9a20164dcc47	2195	__ISB();
vipinranka	12:9a20164dcc47	2196	#endif
vipinranka	12:9a20164dcc47	2197	}
vipinranka	12:9a20164dcc47	2198
vipinranka	12:9a20164dcc47	2199
vipinranka	12:9a20164dcc47	2200	/**
vipinranka	12:9a20164dcc47	2201	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
vipinranka	12:9a20164dcc47	2202	\brief D-Cache Invalidate by address
vipinranka	12:9a20164dcc47	2203	\param[in] addr address (aligned to 32-byte boundary)
vipinranka	12:9a20164dcc47	2204	\param[in] dsize size of memory block (in number of bytes)
vipinranka	12:9a20164dcc47	2205	*/
vipinranka	12:9a20164dcc47	2206	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
vipinranka	12:9a20164dcc47	2207	{
vipinranka	12:9a20164dcc47	2208	#if (__DCACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2209	int32_t op_size = dsize;
vipinranka	12:9a20164dcc47	2210	uint32_t op_addr = (uint32_t)addr;
vipinranka	12:9a20164dcc47	2211	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
vipinranka	12:9a20164dcc47	2212
vipinranka	12:9a20164dcc47	2213	__DSB();
vipinranka	12:9a20164dcc47	2214
vipinranka	12:9a20164dcc47	2215	while (op_size > 0) {
vipinranka	12:9a20164dcc47	2216	SCB->DCIMVAC = op_addr;
vipinranka	12:9a20164dcc47	2217	op_addr += linesize;
vipinranka	12:9a20164dcc47	2218	op_size -= (int32_t)linesize;
vipinranka	12:9a20164dcc47	2219	}
vipinranka	12:9a20164dcc47	2220
vipinranka	12:9a20164dcc47	2221	__DSB();
vipinranka	12:9a20164dcc47	2222	__ISB();
vipinranka	12:9a20164dcc47	2223	#endif
vipinranka	12:9a20164dcc47	2224	}
vipinranka	12:9a20164dcc47	2225
vipinranka	12:9a20164dcc47	2226
vipinranka	12:9a20164dcc47	2227	/**
vipinranka	12:9a20164dcc47	2228	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
vipinranka	12:9a20164dcc47	2229	\brief D-Cache Clean by address
vipinranka	12:9a20164dcc47	2230	\param[in] addr address (aligned to 32-byte boundary)
vipinranka	12:9a20164dcc47	2231	\param[in] dsize size of memory block (in number of bytes)
vipinranka	12:9a20164dcc47	2232	*/
vipinranka	12:9a20164dcc47	2233	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
vipinranka	12:9a20164dcc47	2234	{
vipinranka	12:9a20164dcc47	2235	#if (__DCACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2236	int32_t op_size = dsize;
vipinranka	12:9a20164dcc47	2237	uint32_t op_addr = (uint32_t) addr;
vipinranka	12:9a20164dcc47	2238	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
vipinranka	12:9a20164dcc47	2239
vipinranka	12:9a20164dcc47	2240	__DSB();
vipinranka	12:9a20164dcc47	2241
vipinranka	12:9a20164dcc47	2242	while (op_size > 0) {
vipinranka	12:9a20164dcc47	2243	SCB->DCCMVAC = op_addr;
vipinranka	12:9a20164dcc47	2244	op_addr += linesize;
vipinranka	12:9a20164dcc47	2245	op_size -= (int32_t)linesize;
vipinranka	12:9a20164dcc47	2246	}
vipinranka	12:9a20164dcc47	2247
vipinranka	12:9a20164dcc47	2248	__DSB();
vipinranka	12:9a20164dcc47	2249	__ISB();
vipinranka	12:9a20164dcc47	2250	#endif
vipinranka	12:9a20164dcc47	2251	}
vipinranka	12:9a20164dcc47	2252
vipinranka	12:9a20164dcc47	2253
vipinranka	12:9a20164dcc47	2254	/**
vipinranka	12:9a20164dcc47	2255	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
vipinranka	12:9a20164dcc47	2256	\brief D-Cache Clean and Invalidate by address
vipinranka	12:9a20164dcc47	2257	\param[in] addr address (aligned to 32-byte boundary)
vipinranka	12:9a20164dcc47	2258	\param[in] dsize size of memory block (in number of bytes)
vipinranka	12:9a20164dcc47	2259	*/
vipinranka	12:9a20164dcc47	2260	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
vipinranka	12:9a20164dcc47	2261	{
vipinranka	12:9a20164dcc47	2262	#if (__DCACHE_PRESENT == 1)
vipinranka	12:9a20164dcc47	2263	int32_t op_size = dsize;
vipinranka	12:9a20164dcc47	2264	uint32_t op_addr = (uint32_t) addr;
vipinranka	12:9a20164dcc47	2265	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
vipinranka	12:9a20164dcc47	2266
vipinranka	12:9a20164dcc47	2267	__DSB();
vipinranka	12:9a20164dcc47	2268
vipinranka	12:9a20164dcc47	2269	while (op_size > 0) {
vipinranka	12:9a20164dcc47	2270	SCB->DCCIMVAC = op_addr;
vipinranka	12:9a20164dcc47	2271	op_addr += linesize;
vipinranka	12:9a20164dcc47	2272	op_size -= (int32_t)linesize;
vipinranka	12:9a20164dcc47	2273	}
vipinranka	12:9a20164dcc47	2274
vipinranka	12:9a20164dcc47	2275	__DSB();
vipinranka	12:9a20164dcc47	2276	__ISB();
vipinranka	12:9a20164dcc47	2277	#endif
vipinranka	12:9a20164dcc47	2278	}
vipinranka	12:9a20164dcc47	2279
vipinranka	12:9a20164dcc47	2280
vipinranka	12:9a20164dcc47	2281	/@} end of CMSIS_Core_CacheFunctions /
vipinranka	12:9a20164dcc47	2282
vipinranka	12:9a20164dcc47	2283
vipinranka	12:9a20164dcc47	2284
vipinranka	12:9a20164dcc47	2285	/* ################################## SysTick function ############################################ */
vipinranka	12:9a20164dcc47	2286	/** \ingroup CMSIS_Core_FunctionInterface
vipinranka	12:9a20164dcc47	2287	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
vipinranka	12:9a20164dcc47	2288	\brief Functions that configure the System.
vipinranka	12:9a20164dcc47	2289	@{
vipinranka	12:9a20164dcc47	2290	*/
vipinranka	12:9a20164dcc47	2291
vipinranka	12:9a20164dcc47	2292	#if (__Vendor_SysTickConfig == 0)
vipinranka	12:9a20164dcc47	2293
vipinranka	12:9a20164dcc47	2294	/** \brief System Tick Configuration
vipinranka	12:9a20164dcc47	2295
vipinranka	12:9a20164dcc47	2296	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
vipinranka	12:9a20164dcc47	2297	Counter is in free running mode to generate periodic interrupts.
vipinranka	12:9a20164dcc47	2298
vipinranka	12:9a20164dcc47	2299	\param [in] ticks Number of ticks between two interrupts.
vipinranka	12:9a20164dcc47	2300
vipinranka	12:9a20164dcc47	2301	\return 0 Function succeeded.
vipinranka	12:9a20164dcc47	2302	\return 1 Function failed.
vipinranka	12:9a20164dcc47	2303
vipinranka	12:9a20164dcc47	2304	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
vipinranka	12:9a20164dcc47	2305	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
vipinranka	12:9a20164dcc47	2306	must contain a vendor-specific implementation of this function.
vipinranka	12:9a20164dcc47	2307
vipinranka	12:9a20164dcc47	2308	*/
vipinranka	12:9a20164dcc47	2309	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
vipinranka	12:9a20164dcc47	2310	{
vipinranka	12:9a20164dcc47	2311	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
vipinranka	12:9a20164dcc47	2312
vipinranka	12:9a20164dcc47	2313	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
vipinranka	12:9a20164dcc47	2314	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
vipinranka	12:9a20164dcc47	2315	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
vipinranka	12:9a20164dcc47	2316	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
vipinranka	12:9a20164dcc47	2317	SysTick_CTRL_TICKINT_Msk \|
vipinranka	12:9a20164dcc47	2318	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
vipinranka	12:9a20164dcc47	2319	return (0UL); /* Function successful */
vipinranka	12:9a20164dcc47	2320	}
vipinranka	12:9a20164dcc47	2321
vipinranka	12:9a20164dcc47	2322	#endif
vipinranka	12:9a20164dcc47	2323
vipinranka	12:9a20164dcc47	2324	/@} end of CMSIS_Core_SysTickFunctions /
vipinranka	12:9a20164dcc47	2325
vipinranka	12:9a20164dcc47	2326
vipinranka	12:9a20164dcc47	2327
vipinranka	12:9a20164dcc47	2328	/* ##################################### Debug In/Output function ########################################### */
vipinranka	12:9a20164dcc47	2329	/** \ingroup CMSIS_Core_FunctionInterface
vipinranka	12:9a20164dcc47	2330	\defgroup CMSIS_core_DebugFunctions ITM Functions
vipinranka	12:9a20164dcc47	2331	\brief Functions that access the ITM debug interface.
vipinranka	12:9a20164dcc47	2332	@{
vipinranka	12:9a20164dcc47	2333	*/
vipinranka	12:9a20164dcc47	2334
vipinranka	12:9a20164dcc47	2335	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
vipinranka	12:9a20164dcc47	2336	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
vipinranka	12:9a20164dcc47	2337
vipinranka	12:9a20164dcc47	2338
vipinranka	12:9a20164dcc47	2339	/** \brief ITM Send Character
vipinranka	12:9a20164dcc47	2340
vipinranka	12:9a20164dcc47	2341	The function transmits a character via the ITM channel 0, and
vipinranka	12:9a20164dcc47	2342	\li Just returns when no debugger is connected that has booked the output.
vipinranka	12:9a20164dcc47	2343	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
vipinranka	12:9a20164dcc47	2344
vipinranka	12:9a20164dcc47	2345	\param [in] ch Character to transmit.
vipinranka	12:9a20164dcc47	2346
vipinranka	12:9a20164dcc47	2347	\returns Character to transmit.
vipinranka	12:9a20164dcc47	2348	*/
vipinranka	12:9a20164dcc47	2349	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
vipinranka	12:9a20164dcc47	2350	{
vipinranka	12:9a20164dcc47	2351	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
vipinranka	12:9a20164dcc47	2352	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
vipinranka	12:9a20164dcc47	2353	{
vipinranka	12:9a20164dcc47	2354	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
vipinranka	12:9a20164dcc47	2355	ITM->PORT[0].u8 = (uint8_t)ch;
vipinranka	12:9a20164dcc47	2356	}
vipinranka	12:9a20164dcc47	2357	return (ch);
vipinranka	12:9a20164dcc47	2358	}
vipinranka	12:9a20164dcc47	2359
vipinranka	12:9a20164dcc47	2360
vipinranka	12:9a20164dcc47	2361	/** \brief ITM Receive Character
vipinranka	12:9a20164dcc47	2362
vipinranka	12:9a20164dcc47	2363	The function inputs a character via the external variable \ref ITM_RxBuffer.
vipinranka	12:9a20164dcc47	2364
vipinranka	12:9a20164dcc47	2365	\return Received character.
vipinranka	12:9a20164dcc47	2366	\return -1 No character pending.
vipinranka	12:9a20164dcc47	2367	*/
vipinranka	12:9a20164dcc47	2368	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
vipinranka	12:9a20164dcc47	2369	int32_t ch = -1; /* no character available */
vipinranka	12:9a20164dcc47	2370
vipinranka	12:9a20164dcc47	2371	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
vipinranka	12:9a20164dcc47	2372	ch = ITM_RxBuffer;
vipinranka	12:9a20164dcc47	2373	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
vipinranka	12:9a20164dcc47	2374	}
vipinranka	12:9a20164dcc47	2375
vipinranka	12:9a20164dcc47	2376	return (ch);
vipinranka	12:9a20164dcc47	2377	}
vipinranka	12:9a20164dcc47	2378
vipinranka	12:9a20164dcc47	2379
vipinranka	12:9a20164dcc47	2380	/** \brief ITM Check Character
vipinranka	12:9a20164dcc47	2381
vipinranka	12:9a20164dcc47	2382	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
vipinranka	12:9a20164dcc47	2383
vipinranka	12:9a20164dcc47	2384	\return 0 No character available.
vipinranka	12:9a20164dcc47	2385	\return 1 Character available.
vipinranka	12:9a20164dcc47	2386	*/
vipinranka	12:9a20164dcc47	2387	__STATIC_INLINE int32_t ITM_CheckChar (void) {
vipinranka	12:9a20164dcc47	2388
vipinranka	12:9a20164dcc47	2389	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
vipinranka	12:9a20164dcc47	2390	return (0); /* no character available */
vipinranka	12:9a20164dcc47	2391	} else {
vipinranka	12:9a20164dcc47	2392	return (1); /* character available */
vipinranka	12:9a20164dcc47	2393	}
vipinranka	12:9a20164dcc47	2394	}
vipinranka	12:9a20164dcc47	2395
vipinranka	12:9a20164dcc47	2396	/@} end of CMSIS_core_DebugFunctions /
vipinranka	12:9a20164dcc47	2397
vipinranka	12:9a20164dcc47	2398
vipinranka	12:9a20164dcc47	2399
vipinranka	12:9a20164dcc47	2400
vipinranka	12:9a20164dcc47	2401	#ifdef __cplusplus
vipinranka	12:9a20164dcc47	2402	}
vipinranka	12:9a20164dcc47	2403	#endif
vipinranka	12:9a20164dcc47	2404
vipinranka	12:9a20164dcc47	2405	#endif /* __CORE_CM7_H_DEPENDANT */
vipinranka	12:9a20164dcc47	2406
vipinranka	12:9a20164dcc47	2407	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	11 Jan 2017
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Commits:	13
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mbed-dev/cmsis/core_cm7.h@12:9a20164dcc47, 2017-01-11 (annotated)

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