Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/cmsis/core_cm0plus.h@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /**************************************************************************//**
vipinranka 12:9a20164dcc47 2 * @file core_cm0plus.h
vipinranka 12:9a20164dcc47 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
vipinranka 12:9a20164dcc47 4 * @version V4.10
vipinranka 12:9a20164dcc47 5 * @date 18. March 2015
vipinranka 12:9a20164dcc47 6 *
vipinranka 12:9a20164dcc47 7 * @note
vipinranka 12:9a20164dcc47 8 *
vipinranka 12:9a20164dcc47 9 ******************************************************************************/
vipinranka 12:9a20164dcc47 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
vipinranka 12:9a20164dcc47 11
vipinranka 12:9a20164dcc47 12 All rights reserved.
vipinranka 12:9a20164dcc47 13 Redistribution and use in source and binary forms, with or without
vipinranka 12:9a20164dcc47 14 modification, are permitted provided that the following conditions are met:
vipinranka 12:9a20164dcc47 15 - Redistributions of source code must retain the above copyright
vipinranka 12:9a20164dcc47 16 notice, this list of conditions and the following disclaimer.
vipinranka 12:9a20164dcc47 17 - Redistributions in binary form must reproduce the above copyright
vipinranka 12:9a20164dcc47 18 notice, this list of conditions and the following disclaimer in the
vipinranka 12:9a20164dcc47 19 documentation and/or other materials provided with the distribution.
vipinranka 12:9a20164dcc47 20 - Neither the name of ARM nor the names of its contributors may be used
vipinranka 12:9a20164dcc47 21 to endorse or promote products derived from this software without
vipinranka 12:9a20164dcc47 22 specific prior written permission.
vipinranka 12:9a20164dcc47 23 *
vipinranka 12:9a20164dcc47 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vipinranka 12:9a20164dcc47 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vipinranka 12:9a20164dcc47 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vipinranka 12:9a20164dcc47 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vipinranka 12:9a20164dcc47 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vipinranka 12:9a20164dcc47 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vipinranka 12:9a20164dcc47 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vipinranka 12:9a20164dcc47 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vipinranka 12:9a20164dcc47 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vipinranka 12:9a20164dcc47 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vipinranka 12:9a20164dcc47 34 POSSIBILITY OF SUCH DAMAGE.
vipinranka 12:9a20164dcc47 35 ---------------------------------------------------------------------------*/
vipinranka 12:9a20164dcc47 36
vipinranka 12:9a20164dcc47 37
vipinranka 12:9a20164dcc47 38 #if defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 39 #pragma system_include /* treat file as system include file for MISRA check */
vipinranka 12:9a20164dcc47 40 #endif
vipinranka 12:9a20164dcc47 41
vipinranka 12:9a20164dcc47 42 #ifndef __CORE_CM0PLUS_H_GENERIC
vipinranka 12:9a20164dcc47 43 #define __CORE_CM0PLUS_H_GENERIC
vipinranka 12:9a20164dcc47 44
vipinranka 12:9a20164dcc47 45 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 46 extern "C" {
vipinranka 12:9a20164dcc47 47 #endif
vipinranka 12:9a20164dcc47 48
vipinranka 12:9a20164dcc47 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
vipinranka 12:9a20164dcc47 50 CMSIS violates the following MISRA-C:2004 rules:
vipinranka 12:9a20164dcc47 51
vipinranka 12:9a20164dcc47 52 \li Required Rule 8.5, object/function definition in header file.<br>
vipinranka 12:9a20164dcc47 53 Function definitions in header files are used to allow 'inlining'.
vipinranka 12:9a20164dcc47 54
vipinranka 12:9a20164dcc47 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
vipinranka 12:9a20164dcc47 56 Unions are used for effective representation of core registers.
vipinranka 12:9a20164dcc47 57
vipinranka 12:9a20164dcc47 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
vipinranka 12:9a20164dcc47 59 Function-like macros are used to allow more efficient code.
vipinranka 12:9a20164dcc47 60 */
vipinranka 12:9a20164dcc47 61
vipinranka 12:9a20164dcc47 62
vipinranka 12:9a20164dcc47 63 /*******************************************************************************
vipinranka 12:9a20164dcc47 64 * CMSIS definitions
vipinranka 12:9a20164dcc47 65 ******************************************************************************/
vipinranka 12:9a20164dcc47 66 /** \ingroup Cortex-M0+
vipinranka 12:9a20164dcc47 67 @{
vipinranka 12:9a20164dcc47 68 */
vipinranka 12:9a20164dcc47 69
vipinranka 12:9a20164dcc47 70 /* CMSIS CM0P definitions */
vipinranka 12:9a20164dcc47 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
vipinranka 12:9a20164dcc47 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
vipinranka 12:9a20164dcc47 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
vipinranka 12:9a20164dcc47 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
vipinranka 12:9a20164dcc47 75
vipinranka 12:9a20164dcc47 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
vipinranka 12:9a20164dcc47 77
vipinranka 12:9a20164dcc47 78
vipinranka 12:9a20164dcc47 79 #if defined ( __CC_ARM )
vipinranka 12:9a20164dcc47 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
vipinranka 12:9a20164dcc47 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
vipinranka 12:9a20164dcc47 82 #define __STATIC_INLINE static __inline
vipinranka 12:9a20164dcc47 83
vipinranka 12:9a20164dcc47 84 #elif defined ( __GNUC__ )
vipinranka 12:9a20164dcc47 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
vipinranka 12:9a20164dcc47 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
vipinranka 12:9a20164dcc47 87 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 88
vipinranka 12:9a20164dcc47 89 #elif defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
vipinranka 12:9a20164dcc47 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
vipinranka 12:9a20164dcc47 92 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 93
vipinranka 12:9a20164dcc47 94 #elif defined ( __TMS470__ )
vipinranka 12:9a20164dcc47 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
vipinranka 12:9a20164dcc47 96 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 97
vipinranka 12:9a20164dcc47 98 #elif defined ( __TASKING__ )
vipinranka 12:9a20164dcc47 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
vipinranka 12:9a20164dcc47 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
vipinranka 12:9a20164dcc47 101 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 102
vipinranka 12:9a20164dcc47 103 #elif defined ( __CSMC__ )
vipinranka 12:9a20164dcc47 104 #define __packed
vipinranka 12:9a20164dcc47 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
vipinranka 12:9a20164dcc47 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
vipinranka 12:9a20164dcc47 107 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 108
vipinranka 12:9a20164dcc47 109 #endif
vipinranka 12:9a20164dcc47 110
vipinranka 12:9a20164dcc47 111 /** __FPU_USED indicates whether an FPU is used or not.
vipinranka 12:9a20164dcc47 112 This core does not support an FPU at all
vipinranka 12:9a20164dcc47 113 */
vipinranka 12:9a20164dcc47 114 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 115
vipinranka 12:9a20164dcc47 116 #if defined ( __CC_ARM )
vipinranka 12:9a20164dcc47 117 #if defined __TARGET_FPU_VFP
vipinranka 12:9a20164dcc47 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 119 #endif
vipinranka 12:9a20164dcc47 120
vipinranka 12:9a20164dcc47 121 #elif defined ( __GNUC__ )
vipinranka 12:9a20164dcc47 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
vipinranka 12:9a20164dcc47 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 124 #endif
vipinranka 12:9a20164dcc47 125
vipinranka 12:9a20164dcc47 126 #elif defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 127 #if defined __ARMVFP__
vipinranka 12:9a20164dcc47 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 129 #endif
vipinranka 12:9a20164dcc47 130
vipinranka 12:9a20164dcc47 131 #elif defined ( __TMS470__ )
vipinranka 12:9a20164dcc47 132 #if defined __TI__VFP_SUPPORT____
vipinranka 12:9a20164dcc47 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 134 #endif
vipinranka 12:9a20164dcc47 135
vipinranka 12:9a20164dcc47 136 #elif defined ( __TASKING__ )
vipinranka 12:9a20164dcc47 137 #if defined __FPU_VFP__
vipinranka 12:9a20164dcc47 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 139 #endif
vipinranka 12:9a20164dcc47 140
vipinranka 12:9a20164dcc47 141 #elif defined ( __CSMC__ ) /* Cosmic */
vipinranka 12:9a20164dcc47 142 #if ( __CSMC__ & 0x400) // FPU present for parser
vipinranka 12:9a20164dcc47 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 144 #endif
vipinranka 12:9a20164dcc47 145 #endif
vipinranka 12:9a20164dcc47 146
vipinranka 12:9a20164dcc47 147 #include <stdint.h> /* standard types definitions */
vipinranka 12:9a20164dcc47 148 #include <core_cmInstr.h> /* Core Instruction Access */
vipinranka 12:9a20164dcc47 149 #include <core_cmFunc.h> /* Core Function Access */
vipinranka 12:9a20164dcc47 150
vipinranka 12:9a20164dcc47 151 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 152 }
vipinranka 12:9a20164dcc47 153 #endif
vipinranka 12:9a20164dcc47 154
vipinranka 12:9a20164dcc47 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
vipinranka 12:9a20164dcc47 156
vipinranka 12:9a20164dcc47 157 #ifndef __CMSIS_GENERIC
vipinranka 12:9a20164dcc47 158
vipinranka 12:9a20164dcc47 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
vipinranka 12:9a20164dcc47 160 #define __CORE_CM0PLUS_H_DEPENDANT
vipinranka 12:9a20164dcc47 161
vipinranka 12:9a20164dcc47 162 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 163 extern "C" {
vipinranka 12:9a20164dcc47 164 #endif
vipinranka 12:9a20164dcc47 165
vipinranka 12:9a20164dcc47 166 /* check device defines and use defaults */
vipinranka 12:9a20164dcc47 167 #if defined __CHECK_DEVICE_DEFINES
vipinranka 12:9a20164dcc47 168 #ifndef __CM0PLUS_REV
vipinranka 12:9a20164dcc47 169 #define __CM0PLUS_REV 0x0000
vipinranka 12:9a20164dcc47 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 171 #endif
vipinranka 12:9a20164dcc47 172
vipinranka 12:9a20164dcc47 173 #ifndef __MPU_PRESENT
vipinranka 12:9a20164dcc47 174 #define __MPU_PRESENT 0
vipinranka 12:9a20164dcc47 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 176 #endif
vipinranka 12:9a20164dcc47 177
vipinranka 12:9a20164dcc47 178 #ifndef __VTOR_PRESENT
vipinranka 12:9a20164dcc47 179 #define __VTOR_PRESENT 0
vipinranka 12:9a20164dcc47 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 181 #endif
vipinranka 12:9a20164dcc47 182
vipinranka 12:9a20164dcc47 183 #ifndef __NVIC_PRIO_BITS
vipinranka 12:9a20164dcc47 184 #define __NVIC_PRIO_BITS 2
vipinranka 12:9a20164dcc47 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 186 #endif
vipinranka 12:9a20164dcc47 187
vipinranka 12:9a20164dcc47 188 #ifndef __Vendor_SysTickConfig
vipinranka 12:9a20164dcc47 189 #define __Vendor_SysTickConfig 0
vipinranka 12:9a20164dcc47 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 191 #endif
vipinranka 12:9a20164dcc47 192 #endif
vipinranka 12:9a20164dcc47 193
vipinranka 12:9a20164dcc47 194 /* IO definitions (access restrictions to peripheral registers) */
vipinranka 12:9a20164dcc47 195 /**
vipinranka 12:9a20164dcc47 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
vipinranka 12:9a20164dcc47 197
vipinranka 12:9a20164dcc47 198 <strong>IO Type Qualifiers</strong> are used
vipinranka 12:9a20164dcc47 199 \li to specify the access to peripheral variables.
vipinranka 12:9a20164dcc47 200 \li for automatic generation of peripheral register debug information.
vipinranka 12:9a20164dcc47 201 */
vipinranka 12:9a20164dcc47 202 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 203 #define __I volatile /*!< Defines 'read only' permissions */
vipinranka 12:9a20164dcc47 204 #else
vipinranka 12:9a20164dcc47 205 #define __I volatile const /*!< Defines 'read only' permissions */
vipinranka 12:9a20164dcc47 206 #endif
vipinranka 12:9a20164dcc47 207 #define __O volatile /*!< Defines 'write only' permissions */
vipinranka 12:9a20164dcc47 208 #define __IO volatile /*!< Defines 'read / write' permissions */
vipinranka 12:9a20164dcc47 209
vipinranka 12:9a20164dcc47 210 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 211 #define __IM volatile /*!< Defines 'read only' permissions */
vipinranka 12:9a20164dcc47 212 #else
vipinranka 12:9a20164dcc47 213 #define __IM volatile const /*!< Defines 'read only' permissions */
vipinranka 12:9a20164dcc47 214 #endif
vipinranka 12:9a20164dcc47 215 #define __OM volatile /*!< Defines 'write only' permissions */
vipinranka 12:9a20164dcc47 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
vipinranka 12:9a20164dcc47 217
vipinranka 12:9a20164dcc47 218 /*@} end of group Cortex-M0+ */
vipinranka 12:9a20164dcc47 219
vipinranka 12:9a20164dcc47 220
vipinranka 12:9a20164dcc47 221
vipinranka 12:9a20164dcc47 222 /*******************************************************************************
vipinranka 12:9a20164dcc47 223 * Register Abstraction
vipinranka 12:9a20164dcc47 224 Core Register contain:
vipinranka 12:9a20164dcc47 225 - Core Register
vipinranka 12:9a20164dcc47 226 - Core NVIC Register
vipinranka 12:9a20164dcc47 227 - Core SCB Register
vipinranka 12:9a20164dcc47 228 - Core SysTick Register
vipinranka 12:9a20164dcc47 229 - Core MPU Register
vipinranka 12:9a20164dcc47 230 ******************************************************************************/
vipinranka 12:9a20164dcc47 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
vipinranka 12:9a20164dcc47 232 \brief Type definitions and defines for Cortex-M processor based devices.
vipinranka 12:9a20164dcc47 233 */
vipinranka 12:9a20164dcc47 234
vipinranka 12:9a20164dcc47 235 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 236 \defgroup CMSIS_CORE Status and Control Registers
vipinranka 12:9a20164dcc47 237 \brief Core Register type definitions.
vipinranka 12:9a20164dcc47 238 @{
vipinranka 12:9a20164dcc47 239 */
vipinranka 12:9a20164dcc47 240
vipinranka 12:9a20164dcc47 241 /** \brief Union type to access the Application Program Status Register (APSR).
vipinranka 12:9a20164dcc47 242 */
vipinranka 12:9a20164dcc47 243 typedef union
vipinranka 12:9a20164dcc47 244 {
vipinranka 12:9a20164dcc47 245 struct
vipinranka 12:9a20164dcc47 246 {
vipinranka 12:9a20164dcc47 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
vipinranka 12:9a20164dcc47 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vipinranka 12:9a20164dcc47 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vipinranka 12:9a20164dcc47 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vipinranka 12:9a20164dcc47 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vipinranka 12:9a20164dcc47 252 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 253 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 254 } APSR_Type;
vipinranka 12:9a20164dcc47 255
vipinranka 12:9a20164dcc47 256 /* APSR Register Definitions */
vipinranka 12:9a20164dcc47 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
vipinranka 12:9a20164dcc47 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
vipinranka 12:9a20164dcc47 259
vipinranka 12:9a20164dcc47 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
vipinranka 12:9a20164dcc47 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
vipinranka 12:9a20164dcc47 262
vipinranka 12:9a20164dcc47 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
vipinranka 12:9a20164dcc47 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
vipinranka 12:9a20164dcc47 265
vipinranka 12:9a20164dcc47 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
vipinranka 12:9a20164dcc47 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
vipinranka 12:9a20164dcc47 268
vipinranka 12:9a20164dcc47 269
vipinranka 12:9a20164dcc47 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
vipinranka 12:9a20164dcc47 271 */
vipinranka 12:9a20164dcc47 272 typedef union
vipinranka 12:9a20164dcc47 273 {
vipinranka 12:9a20164dcc47 274 struct
vipinranka 12:9a20164dcc47 275 {
vipinranka 12:9a20164dcc47 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vipinranka 12:9a20164dcc47 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
vipinranka 12:9a20164dcc47 278 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 279 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 280 } IPSR_Type;
vipinranka 12:9a20164dcc47 281
vipinranka 12:9a20164dcc47 282 /* IPSR Register Definitions */
vipinranka 12:9a20164dcc47 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
vipinranka 12:9a20164dcc47 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
vipinranka 12:9a20164dcc47 285
vipinranka 12:9a20164dcc47 286
vipinranka 12:9a20164dcc47 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
vipinranka 12:9a20164dcc47 288 */
vipinranka 12:9a20164dcc47 289 typedef union
vipinranka 12:9a20164dcc47 290 {
vipinranka 12:9a20164dcc47 291 struct
vipinranka 12:9a20164dcc47 292 {
vipinranka 12:9a20164dcc47 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
vipinranka 12:9a20164dcc47 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
vipinranka 12:9a20164dcc47 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
vipinranka 12:9a20164dcc47 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
vipinranka 12:9a20164dcc47 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vipinranka 12:9a20164dcc47 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vipinranka 12:9a20164dcc47 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vipinranka 12:9a20164dcc47 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vipinranka 12:9a20164dcc47 301 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 302 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 303 } xPSR_Type;
vipinranka 12:9a20164dcc47 304
vipinranka 12:9a20164dcc47 305 /* xPSR Register Definitions */
vipinranka 12:9a20164dcc47 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
vipinranka 12:9a20164dcc47 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
vipinranka 12:9a20164dcc47 308
vipinranka 12:9a20164dcc47 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
vipinranka 12:9a20164dcc47 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
vipinranka 12:9a20164dcc47 311
vipinranka 12:9a20164dcc47 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
vipinranka 12:9a20164dcc47 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
vipinranka 12:9a20164dcc47 314
vipinranka 12:9a20164dcc47 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
vipinranka 12:9a20164dcc47 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
vipinranka 12:9a20164dcc47 317
vipinranka 12:9a20164dcc47 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
vipinranka 12:9a20164dcc47 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
vipinranka 12:9a20164dcc47 320
vipinranka 12:9a20164dcc47 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
vipinranka 12:9a20164dcc47 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
vipinranka 12:9a20164dcc47 323
vipinranka 12:9a20164dcc47 324
vipinranka 12:9a20164dcc47 325 /** \brief Union type to access the Control Registers (CONTROL).
vipinranka 12:9a20164dcc47 326 */
vipinranka 12:9a20164dcc47 327 typedef union
vipinranka 12:9a20164dcc47 328 {
vipinranka 12:9a20164dcc47 329 struct
vipinranka 12:9a20164dcc47 330 {
vipinranka 12:9a20164dcc47 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
vipinranka 12:9a20164dcc47 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
vipinranka 12:9a20164dcc47 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
vipinranka 12:9a20164dcc47 334 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 335 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 336 } CONTROL_Type;
vipinranka 12:9a20164dcc47 337
vipinranka 12:9a20164dcc47 338 /* CONTROL Register Definitions */
vipinranka 12:9a20164dcc47 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
vipinranka 12:9a20164dcc47 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
vipinranka 12:9a20164dcc47 341
vipinranka 12:9a20164dcc47 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
vipinranka 12:9a20164dcc47 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
vipinranka 12:9a20164dcc47 344
vipinranka 12:9a20164dcc47 345 /*@} end of group CMSIS_CORE */
vipinranka 12:9a20164dcc47 346
vipinranka 12:9a20164dcc47 347
vipinranka 12:9a20164dcc47 348 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
vipinranka 12:9a20164dcc47 350 \brief Type definitions for the NVIC Registers
vipinranka 12:9a20164dcc47 351 @{
vipinranka 12:9a20164dcc47 352 */
vipinranka 12:9a20164dcc47 353
vipinranka 12:9a20164dcc47 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
vipinranka 12:9a20164dcc47 355 */
vipinranka 12:9a20164dcc47 356 typedef struct
vipinranka 12:9a20164dcc47 357 {
vipinranka 12:9a20164dcc47 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
vipinranka 12:9a20164dcc47 359 uint32_t RESERVED0[31];
vipinranka 12:9a20164dcc47 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
vipinranka 12:9a20164dcc47 361 uint32_t RSERVED1[31];
vipinranka 12:9a20164dcc47 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
vipinranka 12:9a20164dcc47 363 uint32_t RESERVED2[31];
vipinranka 12:9a20164dcc47 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
vipinranka 12:9a20164dcc47 365 uint32_t RESERVED3[31];
vipinranka 12:9a20164dcc47 366 uint32_t RESERVED4[64];
vipinranka 12:9a20164dcc47 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
vipinranka 12:9a20164dcc47 368 } NVIC_Type;
vipinranka 12:9a20164dcc47 369
vipinranka 12:9a20164dcc47 370 /*@} end of group CMSIS_NVIC */
vipinranka 12:9a20164dcc47 371
vipinranka 12:9a20164dcc47 372
vipinranka 12:9a20164dcc47 373 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 374 \defgroup CMSIS_SCB System Control Block (SCB)
vipinranka 12:9a20164dcc47 375 \brief Type definitions for the System Control Block Registers
vipinranka 12:9a20164dcc47 376 @{
vipinranka 12:9a20164dcc47 377 */
vipinranka 12:9a20164dcc47 378
vipinranka 12:9a20164dcc47 379 /** \brief Structure type to access the System Control Block (SCB).
vipinranka 12:9a20164dcc47 380 */
vipinranka 12:9a20164dcc47 381 typedef struct
vipinranka 12:9a20164dcc47 382 {
vipinranka 12:9a20164dcc47 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
vipinranka 12:9a20164dcc47 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
vipinranka 12:9a20164dcc47 385 #if (__VTOR_PRESENT == 1)
vipinranka 12:9a20164dcc47 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
vipinranka 12:9a20164dcc47 387 #else
vipinranka 12:9a20164dcc47 388 uint32_t RESERVED0;
vipinranka 12:9a20164dcc47 389 #endif
vipinranka 12:9a20164dcc47 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
vipinranka 12:9a20164dcc47 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
vipinranka 12:9a20164dcc47 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
vipinranka 12:9a20164dcc47 393 uint32_t RESERVED1;
vipinranka 12:9a20164dcc47 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
vipinranka 12:9a20164dcc47 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
vipinranka 12:9a20164dcc47 396 } SCB_Type;
vipinranka 12:9a20164dcc47 397
vipinranka 12:9a20164dcc47 398 /* SCB CPUID Register Definitions */
vipinranka 12:9a20164dcc47 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
vipinranka 12:9a20164dcc47 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
vipinranka 12:9a20164dcc47 401
vipinranka 12:9a20164dcc47 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
vipinranka 12:9a20164dcc47 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
vipinranka 12:9a20164dcc47 404
vipinranka 12:9a20164dcc47 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
vipinranka 12:9a20164dcc47 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
vipinranka 12:9a20164dcc47 407
vipinranka 12:9a20164dcc47 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
vipinranka 12:9a20164dcc47 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
vipinranka 12:9a20164dcc47 410
vipinranka 12:9a20164dcc47 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
vipinranka 12:9a20164dcc47 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
vipinranka 12:9a20164dcc47 413
vipinranka 12:9a20164dcc47 414 /* SCB Interrupt Control State Register Definitions */
vipinranka 12:9a20164dcc47 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
vipinranka 12:9a20164dcc47 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
vipinranka 12:9a20164dcc47 417
vipinranka 12:9a20164dcc47 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
vipinranka 12:9a20164dcc47 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
vipinranka 12:9a20164dcc47 420
vipinranka 12:9a20164dcc47 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
vipinranka 12:9a20164dcc47 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
vipinranka 12:9a20164dcc47 423
vipinranka 12:9a20164dcc47 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
vipinranka 12:9a20164dcc47 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
vipinranka 12:9a20164dcc47 426
vipinranka 12:9a20164dcc47 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
vipinranka 12:9a20164dcc47 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
vipinranka 12:9a20164dcc47 429
vipinranka 12:9a20164dcc47 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
vipinranka 12:9a20164dcc47 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
vipinranka 12:9a20164dcc47 432
vipinranka 12:9a20164dcc47 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
vipinranka 12:9a20164dcc47 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
vipinranka 12:9a20164dcc47 435
vipinranka 12:9a20164dcc47 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
vipinranka 12:9a20164dcc47 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
vipinranka 12:9a20164dcc47 438
vipinranka 12:9a20164dcc47 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
vipinranka 12:9a20164dcc47 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
vipinranka 12:9a20164dcc47 441
vipinranka 12:9a20164dcc47 442 #if (__VTOR_PRESENT == 1)
vipinranka 12:9a20164dcc47 443 /* SCB Interrupt Control State Register Definitions */
vipinranka 12:9a20164dcc47 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
vipinranka 12:9a20164dcc47 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
vipinranka 12:9a20164dcc47 446 #endif
vipinranka 12:9a20164dcc47 447
vipinranka 12:9a20164dcc47 448 /* SCB Application Interrupt and Reset Control Register Definitions */
vipinranka 12:9a20164dcc47 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
vipinranka 12:9a20164dcc47 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
vipinranka 12:9a20164dcc47 451
vipinranka 12:9a20164dcc47 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
vipinranka 12:9a20164dcc47 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
vipinranka 12:9a20164dcc47 454
vipinranka 12:9a20164dcc47 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
vipinranka 12:9a20164dcc47 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
vipinranka 12:9a20164dcc47 457
vipinranka 12:9a20164dcc47 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
vipinranka 12:9a20164dcc47 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
vipinranka 12:9a20164dcc47 460
vipinranka 12:9a20164dcc47 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
vipinranka 12:9a20164dcc47 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
vipinranka 12:9a20164dcc47 463
vipinranka 12:9a20164dcc47 464 /* SCB System Control Register Definitions */
vipinranka 12:9a20164dcc47 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
vipinranka 12:9a20164dcc47 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
vipinranka 12:9a20164dcc47 467
vipinranka 12:9a20164dcc47 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
vipinranka 12:9a20164dcc47 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
vipinranka 12:9a20164dcc47 470
vipinranka 12:9a20164dcc47 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
vipinranka 12:9a20164dcc47 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
vipinranka 12:9a20164dcc47 473
vipinranka 12:9a20164dcc47 474 /* SCB Configuration Control Register Definitions */
vipinranka 12:9a20164dcc47 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
vipinranka 12:9a20164dcc47 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
vipinranka 12:9a20164dcc47 477
vipinranka 12:9a20164dcc47 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
vipinranka 12:9a20164dcc47 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
vipinranka 12:9a20164dcc47 480
vipinranka 12:9a20164dcc47 481 /* SCB System Handler Control and State Register Definitions */
vipinranka 12:9a20164dcc47 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
vipinranka 12:9a20164dcc47 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
vipinranka 12:9a20164dcc47 484
vipinranka 12:9a20164dcc47 485 /*@} end of group CMSIS_SCB */
vipinranka 12:9a20164dcc47 486
vipinranka 12:9a20164dcc47 487
vipinranka 12:9a20164dcc47 488 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
vipinranka 12:9a20164dcc47 490 \brief Type definitions for the System Timer Registers.
vipinranka 12:9a20164dcc47 491 @{
vipinranka 12:9a20164dcc47 492 */
vipinranka 12:9a20164dcc47 493
vipinranka 12:9a20164dcc47 494 /** \brief Structure type to access the System Timer (SysTick).
vipinranka 12:9a20164dcc47 495 */
vipinranka 12:9a20164dcc47 496 typedef struct
vipinranka 12:9a20164dcc47 497 {
vipinranka 12:9a20164dcc47 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
vipinranka 12:9a20164dcc47 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
vipinranka 12:9a20164dcc47 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
vipinranka 12:9a20164dcc47 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
vipinranka 12:9a20164dcc47 502 } SysTick_Type;
vipinranka 12:9a20164dcc47 503
vipinranka 12:9a20164dcc47 504 /* SysTick Control / Status Register Definitions */
vipinranka 12:9a20164dcc47 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
vipinranka 12:9a20164dcc47 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
vipinranka 12:9a20164dcc47 507
vipinranka 12:9a20164dcc47 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
vipinranka 12:9a20164dcc47 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
vipinranka 12:9a20164dcc47 510
vipinranka 12:9a20164dcc47 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
vipinranka 12:9a20164dcc47 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
vipinranka 12:9a20164dcc47 513
vipinranka 12:9a20164dcc47 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
vipinranka 12:9a20164dcc47 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
vipinranka 12:9a20164dcc47 516
vipinranka 12:9a20164dcc47 517 /* SysTick Reload Register Definitions */
vipinranka 12:9a20164dcc47 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
vipinranka 12:9a20164dcc47 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
vipinranka 12:9a20164dcc47 520
vipinranka 12:9a20164dcc47 521 /* SysTick Current Register Definitions */
vipinranka 12:9a20164dcc47 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
vipinranka 12:9a20164dcc47 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
vipinranka 12:9a20164dcc47 524
vipinranka 12:9a20164dcc47 525 /* SysTick Calibration Register Definitions */
vipinranka 12:9a20164dcc47 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
vipinranka 12:9a20164dcc47 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
vipinranka 12:9a20164dcc47 528
vipinranka 12:9a20164dcc47 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
vipinranka 12:9a20164dcc47 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
vipinranka 12:9a20164dcc47 531
vipinranka 12:9a20164dcc47 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
vipinranka 12:9a20164dcc47 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
vipinranka 12:9a20164dcc47 534
vipinranka 12:9a20164dcc47 535 /*@} end of group CMSIS_SysTick */
vipinranka 12:9a20164dcc47 536
vipinranka 12:9a20164dcc47 537 #if (__MPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 538 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
vipinranka 12:9a20164dcc47 540 \brief Type definitions for the Memory Protection Unit (MPU)
vipinranka 12:9a20164dcc47 541 @{
vipinranka 12:9a20164dcc47 542 */
vipinranka 12:9a20164dcc47 543
vipinranka 12:9a20164dcc47 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
vipinranka 12:9a20164dcc47 545 */
vipinranka 12:9a20164dcc47 546 typedef struct
vipinranka 12:9a20164dcc47 547 {
vipinranka 12:9a20164dcc47 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
vipinranka 12:9a20164dcc47 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
vipinranka 12:9a20164dcc47 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
vipinranka 12:9a20164dcc47 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
vipinranka 12:9a20164dcc47 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
vipinranka 12:9a20164dcc47 553 } MPU_Type;
vipinranka 12:9a20164dcc47 554
vipinranka 12:9a20164dcc47 555 /* MPU Type Register */
vipinranka 12:9a20164dcc47 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
vipinranka 12:9a20164dcc47 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
vipinranka 12:9a20164dcc47 558
vipinranka 12:9a20164dcc47 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
vipinranka 12:9a20164dcc47 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
vipinranka 12:9a20164dcc47 561
vipinranka 12:9a20164dcc47 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
vipinranka 12:9a20164dcc47 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
vipinranka 12:9a20164dcc47 564
vipinranka 12:9a20164dcc47 565 /* MPU Control Register */
vipinranka 12:9a20164dcc47 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
vipinranka 12:9a20164dcc47 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
vipinranka 12:9a20164dcc47 568
vipinranka 12:9a20164dcc47 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
vipinranka 12:9a20164dcc47 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
vipinranka 12:9a20164dcc47 571
vipinranka 12:9a20164dcc47 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
vipinranka 12:9a20164dcc47 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
vipinranka 12:9a20164dcc47 574
vipinranka 12:9a20164dcc47 575 /* MPU Region Number Register */
vipinranka 12:9a20164dcc47 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
vipinranka 12:9a20164dcc47 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
vipinranka 12:9a20164dcc47 578
vipinranka 12:9a20164dcc47 579 /* MPU Region Base Address Register */
vipinranka 12:9a20164dcc47 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
vipinranka 12:9a20164dcc47 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
vipinranka 12:9a20164dcc47 582
vipinranka 12:9a20164dcc47 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
vipinranka 12:9a20164dcc47 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
vipinranka 12:9a20164dcc47 585
vipinranka 12:9a20164dcc47 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
vipinranka 12:9a20164dcc47 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
vipinranka 12:9a20164dcc47 588
vipinranka 12:9a20164dcc47 589 /* MPU Region Attribute and Size Register */
vipinranka 12:9a20164dcc47 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
vipinranka 12:9a20164dcc47 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
vipinranka 12:9a20164dcc47 592
vipinranka 12:9a20164dcc47 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
vipinranka 12:9a20164dcc47 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
vipinranka 12:9a20164dcc47 595
vipinranka 12:9a20164dcc47 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
vipinranka 12:9a20164dcc47 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
vipinranka 12:9a20164dcc47 598
vipinranka 12:9a20164dcc47 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
vipinranka 12:9a20164dcc47 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
vipinranka 12:9a20164dcc47 601
vipinranka 12:9a20164dcc47 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
vipinranka 12:9a20164dcc47 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
vipinranka 12:9a20164dcc47 604
vipinranka 12:9a20164dcc47 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
vipinranka 12:9a20164dcc47 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
vipinranka 12:9a20164dcc47 607
vipinranka 12:9a20164dcc47 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
vipinranka 12:9a20164dcc47 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
vipinranka 12:9a20164dcc47 610
vipinranka 12:9a20164dcc47 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
vipinranka 12:9a20164dcc47 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
vipinranka 12:9a20164dcc47 613
vipinranka 12:9a20164dcc47 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
vipinranka 12:9a20164dcc47 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
vipinranka 12:9a20164dcc47 616
vipinranka 12:9a20164dcc47 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
vipinranka 12:9a20164dcc47 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
vipinranka 12:9a20164dcc47 619
vipinranka 12:9a20164dcc47 620 /*@} end of group CMSIS_MPU */
vipinranka 12:9a20164dcc47 621 #endif
vipinranka 12:9a20164dcc47 622
vipinranka 12:9a20164dcc47 623
vipinranka 12:9a20164dcc47 624 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
vipinranka 12:9a20164dcc47 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
vipinranka 12:9a20164dcc47 627 are only accessible over DAP and not via processor. Therefore
vipinranka 12:9a20164dcc47 628 they are not covered by the Cortex-M0 header file.
vipinranka 12:9a20164dcc47 629 @{
vipinranka 12:9a20164dcc47 630 */
vipinranka 12:9a20164dcc47 631 /*@} end of group CMSIS_CoreDebug */
vipinranka 12:9a20164dcc47 632
vipinranka 12:9a20164dcc47 633
vipinranka 12:9a20164dcc47 634 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 635 \defgroup CMSIS_core_base Core Definitions
vipinranka 12:9a20164dcc47 636 \brief Definitions for base addresses, unions, and structures.
vipinranka 12:9a20164dcc47 637 @{
vipinranka 12:9a20164dcc47 638 */
vipinranka 12:9a20164dcc47 639
vipinranka 12:9a20164dcc47 640 /* Memory mapping of Cortex-M0+ Hardware */
vipinranka 12:9a20164dcc47 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
vipinranka 12:9a20164dcc47 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
vipinranka 12:9a20164dcc47 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
vipinranka 12:9a20164dcc47 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
vipinranka 12:9a20164dcc47 645
vipinranka 12:9a20164dcc47 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
vipinranka 12:9a20164dcc47 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
vipinranka 12:9a20164dcc47 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
vipinranka 12:9a20164dcc47 649
vipinranka 12:9a20164dcc47 650 #if (__MPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
vipinranka 12:9a20164dcc47 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
vipinranka 12:9a20164dcc47 653 #endif
vipinranka 12:9a20164dcc47 654
vipinranka 12:9a20164dcc47 655 /*@} */
vipinranka 12:9a20164dcc47 656
vipinranka 12:9a20164dcc47 657
vipinranka 12:9a20164dcc47 658
vipinranka 12:9a20164dcc47 659 /*******************************************************************************
vipinranka 12:9a20164dcc47 660 * Hardware Abstraction Layer
vipinranka 12:9a20164dcc47 661 Core Function Interface contains:
vipinranka 12:9a20164dcc47 662 - Core NVIC Functions
vipinranka 12:9a20164dcc47 663 - Core SysTick Functions
vipinranka 12:9a20164dcc47 664 - Core Register Access Functions
vipinranka 12:9a20164dcc47 665 ******************************************************************************/
vipinranka 12:9a20164dcc47 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
vipinranka 12:9a20164dcc47 667 */
vipinranka 12:9a20164dcc47 668
vipinranka 12:9a20164dcc47 669
vipinranka 12:9a20164dcc47 670
vipinranka 12:9a20164dcc47 671 /* ########################## NVIC functions #################################### */
vipinranka 12:9a20164dcc47 672 /** \ingroup CMSIS_Core_FunctionInterface
vipinranka 12:9a20164dcc47 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
vipinranka 12:9a20164dcc47 674 \brief Functions that manage interrupts and exceptions via the NVIC.
vipinranka 12:9a20164dcc47 675 @{
vipinranka 12:9a20164dcc47 676 */
vipinranka 12:9a20164dcc47 677
vipinranka 12:9a20164dcc47 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
vipinranka 12:9a20164dcc47 679 /* The following MACROS handle generation of the register offset and byte masks */
vipinranka 12:9a20164dcc47 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
vipinranka 12:9a20164dcc47 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
vipinranka 12:9a20164dcc47 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
vipinranka 12:9a20164dcc47 683
vipinranka 12:9a20164dcc47 684
vipinranka 12:9a20164dcc47 685 /** \brief Enable External Interrupt
vipinranka 12:9a20164dcc47 686
vipinranka 12:9a20164dcc47 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
vipinranka 12:9a20164dcc47 688
vipinranka 12:9a20164dcc47 689 \param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka 12:9a20164dcc47 690 */
vipinranka 12:9a20164dcc47 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 692 {
vipinranka 12:9a20164dcc47 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka 12:9a20164dcc47 694 }
vipinranka 12:9a20164dcc47 695
vipinranka 12:9a20164dcc47 696
vipinranka 12:9a20164dcc47 697 /** \brief Disable External Interrupt
vipinranka 12:9a20164dcc47 698
vipinranka 12:9a20164dcc47 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
vipinranka 12:9a20164dcc47 700
vipinranka 12:9a20164dcc47 701 \param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka 12:9a20164dcc47 702 */
vipinranka 12:9a20164dcc47 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 704 {
vipinranka 12:9a20164dcc47 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka 12:9a20164dcc47 706 __DSB();
vipinranka 12:9a20164dcc47 707 __ISB();
vipinranka 12:9a20164dcc47 708 }
vipinranka 12:9a20164dcc47 709
vipinranka 12:9a20164dcc47 710
vipinranka 12:9a20164dcc47 711 /** \brief Get Pending Interrupt
vipinranka 12:9a20164dcc47 712
vipinranka 12:9a20164dcc47 713 The function reads the pending register in the NVIC and returns the pending bit
vipinranka 12:9a20164dcc47 714 for the specified interrupt.
vipinranka 12:9a20164dcc47 715
vipinranka 12:9a20164dcc47 716 \param [in] IRQn Interrupt number.
vipinranka 12:9a20164dcc47 717
vipinranka 12:9a20164dcc47 718 \return 0 Interrupt status is not pending.
vipinranka 12:9a20164dcc47 719 \return 1 Interrupt status is pending.
vipinranka 12:9a20164dcc47 720 */
vipinranka 12:9a20164dcc47 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 722 {
vipinranka 12:9a20164dcc47 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
vipinranka 12:9a20164dcc47 724 }
vipinranka 12:9a20164dcc47 725
vipinranka 12:9a20164dcc47 726
vipinranka 12:9a20164dcc47 727 /** \brief Set Pending Interrupt
vipinranka 12:9a20164dcc47 728
vipinranka 12:9a20164dcc47 729 The function sets the pending bit of an external interrupt.
vipinranka 12:9a20164dcc47 730
vipinranka 12:9a20164dcc47 731 \param [in] IRQn Interrupt number. Value cannot be negative.
vipinranka 12:9a20164dcc47 732 */
vipinranka 12:9a20164dcc47 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 734 {
vipinranka 12:9a20164dcc47 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka 12:9a20164dcc47 736 }
vipinranka 12:9a20164dcc47 737
vipinranka 12:9a20164dcc47 738
vipinranka 12:9a20164dcc47 739 /** \brief Clear Pending Interrupt
vipinranka 12:9a20164dcc47 740
vipinranka 12:9a20164dcc47 741 The function clears the pending bit of an external interrupt.
vipinranka 12:9a20164dcc47 742
vipinranka 12:9a20164dcc47 743 \param [in] IRQn External interrupt number. Value cannot be negative.
vipinranka 12:9a20164dcc47 744 */
vipinranka 12:9a20164dcc47 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 746 {
vipinranka 12:9a20164dcc47 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
vipinranka 12:9a20164dcc47 748 }
vipinranka 12:9a20164dcc47 749
vipinranka 12:9a20164dcc47 750
vipinranka 12:9a20164dcc47 751 /** \brief Set Interrupt Priority
vipinranka 12:9a20164dcc47 752
vipinranka 12:9a20164dcc47 753 The function sets the priority of an interrupt.
vipinranka 12:9a20164dcc47 754
vipinranka 12:9a20164dcc47 755 \note The priority cannot be set for every core interrupt.
vipinranka 12:9a20164dcc47 756
vipinranka 12:9a20164dcc47 757 \param [in] IRQn Interrupt number.
vipinranka 12:9a20164dcc47 758 \param [in] priority Priority to set.
vipinranka 12:9a20164dcc47 759 */
vipinranka 12:9a20164dcc47 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
vipinranka 12:9a20164dcc47 761 {
vipinranka 12:9a20164dcc47 762 if((int32_t)(IRQn) < 0) {
vipinranka 12:9a20164dcc47 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
vipinranka 12:9a20164dcc47 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
vipinranka 12:9a20164dcc47 765 }
vipinranka 12:9a20164dcc47 766 else {
vipinranka 12:9a20164dcc47 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
vipinranka 12:9a20164dcc47 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
vipinranka 12:9a20164dcc47 769 }
vipinranka 12:9a20164dcc47 770 }
vipinranka 12:9a20164dcc47 771
vipinranka 12:9a20164dcc47 772
vipinranka 12:9a20164dcc47 773 /** \brief Get Interrupt Priority
vipinranka 12:9a20164dcc47 774
vipinranka 12:9a20164dcc47 775 The function reads the priority of an interrupt. The interrupt
vipinranka 12:9a20164dcc47 776 number can be positive to specify an external (device specific)
vipinranka 12:9a20164dcc47 777 interrupt, or negative to specify an internal (core) interrupt.
vipinranka 12:9a20164dcc47 778
vipinranka 12:9a20164dcc47 779
vipinranka 12:9a20164dcc47 780 \param [in] IRQn Interrupt number.
vipinranka 12:9a20164dcc47 781 \return Interrupt Priority. Value is aligned automatically to the implemented
vipinranka 12:9a20164dcc47 782 priority bits of the microcontroller.
vipinranka 12:9a20164dcc47 783 */
vipinranka 12:9a20164dcc47 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
vipinranka 12:9a20164dcc47 785 {
vipinranka 12:9a20164dcc47 786
vipinranka 12:9a20164dcc47 787 if((int32_t)(IRQn) < 0) {
vipinranka 12:9a20164dcc47 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
vipinranka 12:9a20164dcc47 789 }
vipinranka 12:9a20164dcc47 790 else {
vipinranka 12:9a20164dcc47 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
vipinranka 12:9a20164dcc47 792 }
vipinranka 12:9a20164dcc47 793 }
vipinranka 12:9a20164dcc47 794
vipinranka 12:9a20164dcc47 795
vipinranka 12:9a20164dcc47 796 /** \brief System Reset
vipinranka 12:9a20164dcc47 797
vipinranka 12:9a20164dcc47 798 The function initiates a system reset request to reset the MCU.
vipinranka 12:9a20164dcc47 799 */
vipinranka 12:9a20164dcc47 800 __STATIC_INLINE void NVIC_SystemReset(void)
vipinranka 12:9a20164dcc47 801 {
vipinranka 12:9a20164dcc47 802 __DSB(); /* Ensure all outstanding memory accesses included
vipinranka 12:9a20164dcc47 803 buffered write are completed before reset */
vipinranka 12:9a20164dcc47 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
vipinranka 12:9a20164dcc47 805 SCB_AIRCR_SYSRESETREQ_Msk);
vipinranka 12:9a20164dcc47 806 __DSB(); /* Ensure completion of memory access */
vipinranka 12:9a20164dcc47 807 while(1) { __NOP(); } /* wait until reset */
vipinranka 12:9a20164dcc47 808 }
vipinranka 12:9a20164dcc47 809
vipinranka 12:9a20164dcc47 810 /*@} end of CMSIS_Core_NVICFunctions */
vipinranka 12:9a20164dcc47 811
vipinranka 12:9a20164dcc47 812
vipinranka 12:9a20164dcc47 813
vipinranka 12:9a20164dcc47 814 /* ################################## SysTick function ############################################ */
vipinranka 12:9a20164dcc47 815 /** \ingroup CMSIS_Core_FunctionInterface
vipinranka 12:9a20164dcc47 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
vipinranka 12:9a20164dcc47 817 \brief Functions that configure the System.
vipinranka 12:9a20164dcc47 818 @{
vipinranka 12:9a20164dcc47 819 */
vipinranka 12:9a20164dcc47 820
vipinranka 12:9a20164dcc47 821 #if (__Vendor_SysTickConfig == 0)
vipinranka 12:9a20164dcc47 822
vipinranka 12:9a20164dcc47 823 /** \brief System Tick Configuration
vipinranka 12:9a20164dcc47 824
vipinranka 12:9a20164dcc47 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
vipinranka 12:9a20164dcc47 826 Counter is in free running mode to generate periodic interrupts.
vipinranka 12:9a20164dcc47 827
vipinranka 12:9a20164dcc47 828 \param [in] ticks Number of ticks between two interrupts.
vipinranka 12:9a20164dcc47 829
vipinranka 12:9a20164dcc47 830 \return 0 Function succeeded.
vipinranka 12:9a20164dcc47 831 \return 1 Function failed.
vipinranka 12:9a20164dcc47 832
vipinranka 12:9a20164dcc47 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
vipinranka 12:9a20164dcc47 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
vipinranka 12:9a20164dcc47 835 must contain a vendor-specific implementation of this function.
vipinranka 12:9a20164dcc47 836
vipinranka 12:9a20164dcc47 837 */
vipinranka 12:9a20164dcc47 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
vipinranka 12:9a20164dcc47 839 {
vipinranka 12:9a20164dcc47 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
vipinranka 12:9a20164dcc47 841
vipinranka 12:9a20164dcc47 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
vipinranka 12:9a20164dcc47 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
vipinranka 12:9a20164dcc47 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
vipinranka 12:9a20164dcc47 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
vipinranka 12:9a20164dcc47 846 SysTick_CTRL_TICKINT_Msk |
vipinranka 12:9a20164dcc47 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
vipinranka 12:9a20164dcc47 848 return (0UL); /* Function successful */
vipinranka 12:9a20164dcc47 849 }
vipinranka 12:9a20164dcc47 850
vipinranka 12:9a20164dcc47 851 #endif
vipinranka 12:9a20164dcc47 852
vipinranka 12:9a20164dcc47 853 /*@} end of CMSIS_Core_SysTickFunctions */
vipinranka 12:9a20164dcc47 854
vipinranka 12:9a20164dcc47 855
vipinranka 12:9a20164dcc47 856
vipinranka 12:9a20164dcc47 857
vipinranka 12:9a20164dcc47 858 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 859 }
vipinranka 12:9a20164dcc47 860 #endif
vipinranka 12:9a20164dcc47 861
vipinranka 12:9a20164dcc47 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
vipinranka 12:9a20164dcc47 863
vipinranka 12:9a20164dcc47 864 #endif /* __CMSIS_GENERIC */