Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/cmsis/core_caFunc.h@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /**************************************************************************//**
vipinranka 12:9a20164dcc47 2 * @file core_caFunc.h
vipinranka 12:9a20164dcc47 3 * @brief CMSIS Cortex-A Core Function Access Header File
vipinranka 12:9a20164dcc47 4 * @version V3.10
vipinranka 12:9a20164dcc47 5 * @date 30 Oct 2013
vipinranka 12:9a20164dcc47 6 *
vipinranka 12:9a20164dcc47 7 * @note
vipinranka 12:9a20164dcc47 8 *
vipinranka 12:9a20164dcc47 9 ******************************************************************************/
vipinranka 12:9a20164dcc47 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
vipinranka 12:9a20164dcc47 11
vipinranka 12:9a20164dcc47 12 All rights reserved.
vipinranka 12:9a20164dcc47 13 Redistribution and use in source and binary forms, with or without
vipinranka 12:9a20164dcc47 14 modification, are permitted provided that the following conditions are met:
vipinranka 12:9a20164dcc47 15 - Redistributions of source code must retain the above copyright
vipinranka 12:9a20164dcc47 16 notice, this list of conditions and the following disclaimer.
vipinranka 12:9a20164dcc47 17 - Redistributions in binary form must reproduce the above copyright
vipinranka 12:9a20164dcc47 18 notice, this list of conditions and the following disclaimer in the
vipinranka 12:9a20164dcc47 19 documentation and/or other materials provided with the distribution.
vipinranka 12:9a20164dcc47 20 - Neither the name of ARM nor the names of its contributors may be used
vipinranka 12:9a20164dcc47 21 to endorse or promote products derived from this software without
vipinranka 12:9a20164dcc47 22 specific prior written permission.
vipinranka 12:9a20164dcc47 23 *
vipinranka 12:9a20164dcc47 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vipinranka 12:9a20164dcc47 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vipinranka 12:9a20164dcc47 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vipinranka 12:9a20164dcc47 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vipinranka 12:9a20164dcc47 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vipinranka 12:9a20164dcc47 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vipinranka 12:9a20164dcc47 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vipinranka 12:9a20164dcc47 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vipinranka 12:9a20164dcc47 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vipinranka 12:9a20164dcc47 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vipinranka 12:9a20164dcc47 34 POSSIBILITY OF SUCH DAMAGE.
vipinranka 12:9a20164dcc47 35 ---------------------------------------------------------------------------*/
vipinranka 12:9a20164dcc47 36
vipinranka 12:9a20164dcc47 37
vipinranka 12:9a20164dcc47 38 #ifndef __CORE_CAFUNC_H__
vipinranka 12:9a20164dcc47 39 #define __CORE_CAFUNC_H__
vipinranka 12:9a20164dcc47 40
vipinranka 12:9a20164dcc47 41
vipinranka 12:9a20164dcc47 42 /* ########################### Core Function Access ########################### */
vipinranka 12:9a20164dcc47 43 /** \ingroup CMSIS_Core_FunctionInterface
vipinranka 12:9a20164dcc47 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
vipinranka 12:9a20164dcc47 45 @{
vipinranka 12:9a20164dcc47 46 */
vipinranka 12:9a20164dcc47 47
vipinranka 12:9a20164dcc47 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
vipinranka 12:9a20164dcc47 49 /* ARM armcc specific functions */
vipinranka 12:9a20164dcc47 50
vipinranka 12:9a20164dcc47 51 #if (__ARMCC_VERSION < 400677)
vipinranka 12:9a20164dcc47 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
vipinranka 12:9a20164dcc47 53 #endif
vipinranka 12:9a20164dcc47 54
vipinranka 12:9a20164dcc47 55 #define MODE_USR 0x10
vipinranka 12:9a20164dcc47 56 #define MODE_FIQ 0x11
vipinranka 12:9a20164dcc47 57 #define MODE_IRQ 0x12
vipinranka 12:9a20164dcc47 58 #define MODE_SVC 0x13
vipinranka 12:9a20164dcc47 59 #define MODE_MON 0x16
vipinranka 12:9a20164dcc47 60 #define MODE_ABT 0x17
vipinranka 12:9a20164dcc47 61 #define MODE_HYP 0x1A
vipinranka 12:9a20164dcc47 62 #define MODE_UND 0x1B
vipinranka 12:9a20164dcc47 63 #define MODE_SYS 0x1F
vipinranka 12:9a20164dcc47 64
vipinranka 12:9a20164dcc47 65 /** \brief Get APSR Register
vipinranka 12:9a20164dcc47 66
vipinranka 12:9a20164dcc47 67 This function returns the content of the APSR Register.
vipinranka 12:9a20164dcc47 68
vipinranka 12:9a20164dcc47 69 \return APSR Register value
vipinranka 12:9a20164dcc47 70 */
vipinranka 12:9a20164dcc47 71 __STATIC_INLINE uint32_t __get_APSR(void)
vipinranka 12:9a20164dcc47 72 {
vipinranka 12:9a20164dcc47 73 register uint32_t __regAPSR __ASM("apsr");
vipinranka 12:9a20164dcc47 74 return(__regAPSR);
vipinranka 12:9a20164dcc47 75 }
vipinranka 12:9a20164dcc47 76
vipinranka 12:9a20164dcc47 77
vipinranka 12:9a20164dcc47 78 /** \brief Get CPSR Register
vipinranka 12:9a20164dcc47 79
vipinranka 12:9a20164dcc47 80 This function returns the content of the CPSR Register.
vipinranka 12:9a20164dcc47 81
vipinranka 12:9a20164dcc47 82 \return CPSR Register value
vipinranka 12:9a20164dcc47 83 */
vipinranka 12:9a20164dcc47 84 __STATIC_INLINE uint32_t __get_CPSR(void)
vipinranka 12:9a20164dcc47 85 {
vipinranka 12:9a20164dcc47 86 register uint32_t __regCPSR __ASM("cpsr");
vipinranka 12:9a20164dcc47 87 return(__regCPSR);
vipinranka 12:9a20164dcc47 88 }
vipinranka 12:9a20164dcc47 89
vipinranka 12:9a20164dcc47 90 /** \brief Set Stack Pointer
vipinranka 12:9a20164dcc47 91
vipinranka 12:9a20164dcc47 92 This function assigns the given value to the current stack pointer.
vipinranka 12:9a20164dcc47 93
vipinranka 12:9a20164dcc47 94 \param [in] topOfStack Stack Pointer value to set
vipinranka 12:9a20164dcc47 95 */
vipinranka 12:9a20164dcc47 96 register uint32_t __regSP __ASM("sp");
vipinranka 12:9a20164dcc47 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
vipinranka 12:9a20164dcc47 98 {
vipinranka 12:9a20164dcc47 99 __regSP = topOfStack;
vipinranka 12:9a20164dcc47 100 }
vipinranka 12:9a20164dcc47 101
vipinranka 12:9a20164dcc47 102
vipinranka 12:9a20164dcc47 103 /** \brief Get link register
vipinranka 12:9a20164dcc47 104
vipinranka 12:9a20164dcc47 105 This function returns the value of the link register
vipinranka 12:9a20164dcc47 106
vipinranka 12:9a20164dcc47 107 \return Value of link register
vipinranka 12:9a20164dcc47 108 */
vipinranka 12:9a20164dcc47 109 register uint32_t __reglr __ASM("lr");
vipinranka 12:9a20164dcc47 110 __STATIC_INLINE uint32_t __get_LR(void)
vipinranka 12:9a20164dcc47 111 {
vipinranka 12:9a20164dcc47 112 return(__reglr);
vipinranka 12:9a20164dcc47 113 }
vipinranka 12:9a20164dcc47 114
vipinranka 12:9a20164dcc47 115 /** \brief Set link register
vipinranka 12:9a20164dcc47 116
vipinranka 12:9a20164dcc47 117 This function sets the value of the link register
vipinranka 12:9a20164dcc47 118
vipinranka 12:9a20164dcc47 119 \param [in] lr LR value to set
vipinranka 12:9a20164dcc47 120 */
vipinranka 12:9a20164dcc47 121 __STATIC_INLINE void __set_LR(uint32_t lr)
vipinranka 12:9a20164dcc47 122 {
vipinranka 12:9a20164dcc47 123 __reglr = lr;
vipinranka 12:9a20164dcc47 124 }
vipinranka 12:9a20164dcc47 125
vipinranka 12:9a20164dcc47 126 /** \brief Set Process Stack Pointer
vipinranka 12:9a20164dcc47 127
vipinranka 12:9a20164dcc47 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
vipinranka 12:9a20164dcc47 129
vipinranka 12:9a20164dcc47 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
vipinranka 12:9a20164dcc47 131 */
vipinranka 12:9a20164dcc47 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
vipinranka 12:9a20164dcc47 133 {
vipinranka 12:9a20164dcc47 134 ARM
vipinranka 12:9a20164dcc47 135 PRESERVE8
vipinranka 12:9a20164dcc47 136
vipinranka 12:9a20164dcc47 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
vipinranka 12:9a20164dcc47 138 MRS R1, CPSR
vipinranka 12:9a20164dcc47 139 CPS #MODE_SYS ;no effect in USR mode
vipinranka 12:9a20164dcc47 140 MOV SP, R0
vipinranka 12:9a20164dcc47 141 MSR CPSR_c, R1 ;no effect in USR mode
vipinranka 12:9a20164dcc47 142 ISB
vipinranka 12:9a20164dcc47 143 BX LR
vipinranka 12:9a20164dcc47 144
vipinranka 12:9a20164dcc47 145 }
vipinranka 12:9a20164dcc47 146
vipinranka 12:9a20164dcc47 147 /** \brief Set User Mode
vipinranka 12:9a20164dcc47 148
vipinranka 12:9a20164dcc47 149 This function changes the processor state to User Mode
vipinranka 12:9a20164dcc47 150 */
vipinranka 12:9a20164dcc47 151 __STATIC_ASM void __set_CPS_USR(void)
vipinranka 12:9a20164dcc47 152 {
vipinranka 12:9a20164dcc47 153 ARM
vipinranka 12:9a20164dcc47 154
vipinranka 12:9a20164dcc47 155 CPS #MODE_USR
vipinranka 12:9a20164dcc47 156 BX LR
vipinranka 12:9a20164dcc47 157 }
vipinranka 12:9a20164dcc47 158
vipinranka 12:9a20164dcc47 159
vipinranka 12:9a20164dcc47 160 /** \brief Enable FIQ
vipinranka 12:9a20164dcc47 161
vipinranka 12:9a20164dcc47 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
vipinranka 12:9a20164dcc47 163 Can only be executed in Privileged modes.
vipinranka 12:9a20164dcc47 164 */
vipinranka 12:9a20164dcc47 165 #define __enable_fault_irq __enable_fiq
vipinranka 12:9a20164dcc47 166
vipinranka 12:9a20164dcc47 167
vipinranka 12:9a20164dcc47 168 /** \brief Disable FIQ
vipinranka 12:9a20164dcc47 169
vipinranka 12:9a20164dcc47 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
vipinranka 12:9a20164dcc47 171 Can only be executed in Privileged modes.
vipinranka 12:9a20164dcc47 172 */
vipinranka 12:9a20164dcc47 173 #define __disable_fault_irq __disable_fiq
vipinranka 12:9a20164dcc47 174
vipinranka 12:9a20164dcc47 175
vipinranka 12:9a20164dcc47 176 /** \brief Get FPSCR
vipinranka 12:9a20164dcc47 177
vipinranka 12:9a20164dcc47 178 This function returns the current value of the Floating Point Status/Control register.
vipinranka 12:9a20164dcc47 179
vipinranka 12:9a20164dcc47 180 \return Floating Point Status/Control register value
vipinranka 12:9a20164dcc47 181 */
vipinranka 12:9a20164dcc47 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
vipinranka 12:9a20164dcc47 183 {
vipinranka 12:9a20164dcc47 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vipinranka 12:9a20164dcc47 185 register uint32_t __regfpscr __ASM("fpscr");
vipinranka 12:9a20164dcc47 186 return(__regfpscr);
vipinranka 12:9a20164dcc47 187 #else
vipinranka 12:9a20164dcc47 188 return(0);
vipinranka 12:9a20164dcc47 189 #endif
vipinranka 12:9a20164dcc47 190 }
vipinranka 12:9a20164dcc47 191
vipinranka 12:9a20164dcc47 192
vipinranka 12:9a20164dcc47 193 /** \brief Set FPSCR
vipinranka 12:9a20164dcc47 194
vipinranka 12:9a20164dcc47 195 This function assigns the given value to the Floating Point Status/Control register.
vipinranka 12:9a20164dcc47 196
vipinranka 12:9a20164dcc47 197 \param [in] fpscr Floating Point Status/Control value to set
vipinranka 12:9a20164dcc47 198 */
vipinranka 12:9a20164dcc47 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
vipinranka 12:9a20164dcc47 200 {
vipinranka 12:9a20164dcc47 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vipinranka 12:9a20164dcc47 202 register uint32_t __regfpscr __ASM("fpscr");
vipinranka 12:9a20164dcc47 203 __regfpscr = (fpscr);
vipinranka 12:9a20164dcc47 204 #endif
vipinranka 12:9a20164dcc47 205 }
vipinranka 12:9a20164dcc47 206
vipinranka 12:9a20164dcc47 207 /** \brief Get FPEXC
vipinranka 12:9a20164dcc47 208
vipinranka 12:9a20164dcc47 209 This function returns the current value of the Floating Point Exception Control register.
vipinranka 12:9a20164dcc47 210
vipinranka 12:9a20164dcc47 211 \return Floating Point Exception Control register value
vipinranka 12:9a20164dcc47 212 */
vipinranka 12:9a20164dcc47 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
vipinranka 12:9a20164dcc47 214 {
vipinranka 12:9a20164dcc47 215 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 216 register uint32_t __regfpexc __ASM("fpexc");
vipinranka 12:9a20164dcc47 217 return(__regfpexc);
vipinranka 12:9a20164dcc47 218 #else
vipinranka 12:9a20164dcc47 219 return(0);
vipinranka 12:9a20164dcc47 220 #endif
vipinranka 12:9a20164dcc47 221 }
vipinranka 12:9a20164dcc47 222
vipinranka 12:9a20164dcc47 223
vipinranka 12:9a20164dcc47 224 /** \brief Set FPEXC
vipinranka 12:9a20164dcc47 225
vipinranka 12:9a20164dcc47 226 This function assigns the given value to the Floating Point Exception Control register.
vipinranka 12:9a20164dcc47 227
vipinranka 12:9a20164dcc47 228 \param [in] fpscr Floating Point Exception Control value to set
vipinranka 12:9a20164dcc47 229 */
vipinranka 12:9a20164dcc47 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
vipinranka 12:9a20164dcc47 231 {
vipinranka 12:9a20164dcc47 232 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 233 register uint32_t __regfpexc __ASM("fpexc");
vipinranka 12:9a20164dcc47 234 __regfpexc = (fpexc);
vipinranka 12:9a20164dcc47 235 #endif
vipinranka 12:9a20164dcc47 236 }
vipinranka 12:9a20164dcc47 237
vipinranka 12:9a20164dcc47 238 /** \brief Get CPACR
vipinranka 12:9a20164dcc47 239
vipinranka 12:9a20164dcc47 240 This function returns the current value of the Coprocessor Access Control register.
vipinranka 12:9a20164dcc47 241
vipinranka 12:9a20164dcc47 242 \return Coprocessor Access Control register value
vipinranka 12:9a20164dcc47 243 */
vipinranka 12:9a20164dcc47 244 __STATIC_INLINE uint32_t __get_CPACR(void)
vipinranka 12:9a20164dcc47 245 {
vipinranka 12:9a20164dcc47 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
vipinranka 12:9a20164dcc47 247 return __regCPACR;
vipinranka 12:9a20164dcc47 248 }
vipinranka 12:9a20164dcc47 249
vipinranka 12:9a20164dcc47 250 /** \brief Set CPACR
vipinranka 12:9a20164dcc47 251
vipinranka 12:9a20164dcc47 252 This function assigns the given value to the Coprocessor Access Control register.
vipinranka 12:9a20164dcc47 253
vipinranka 12:9a20164dcc47 254 \param [in] cpacr Coprocessor Acccess Control value to set
vipinranka 12:9a20164dcc47 255 */
vipinranka 12:9a20164dcc47 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
vipinranka 12:9a20164dcc47 257 {
vipinranka 12:9a20164dcc47 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
vipinranka 12:9a20164dcc47 259 __regCPACR = cpacr;
vipinranka 12:9a20164dcc47 260 __ISB();
vipinranka 12:9a20164dcc47 261 }
vipinranka 12:9a20164dcc47 262
vipinranka 12:9a20164dcc47 263 /** \brief Get CBAR
vipinranka 12:9a20164dcc47 264
vipinranka 12:9a20164dcc47 265 This function returns the value of the Configuration Base Address register.
vipinranka 12:9a20164dcc47 266
vipinranka 12:9a20164dcc47 267 \return Configuration Base Address register value
vipinranka 12:9a20164dcc47 268 */
vipinranka 12:9a20164dcc47 269 __STATIC_INLINE uint32_t __get_CBAR() {
vipinranka 12:9a20164dcc47 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
vipinranka 12:9a20164dcc47 271 return(__regCBAR);
vipinranka 12:9a20164dcc47 272 }
vipinranka 12:9a20164dcc47 273
vipinranka 12:9a20164dcc47 274 /** \brief Get TTBR0
vipinranka 12:9a20164dcc47 275
vipinranka 12:9a20164dcc47 276 This function returns the value of the Translation Table Base Register 0.
vipinranka 12:9a20164dcc47 277
vipinranka 12:9a20164dcc47 278 \return Translation Table Base Register 0 value
vipinranka 12:9a20164dcc47 279 */
vipinranka 12:9a20164dcc47 280 __STATIC_INLINE uint32_t __get_TTBR0() {
vipinranka 12:9a20164dcc47 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
vipinranka 12:9a20164dcc47 282 return(__regTTBR0);
vipinranka 12:9a20164dcc47 283 }
vipinranka 12:9a20164dcc47 284
vipinranka 12:9a20164dcc47 285 /** \brief Set TTBR0
vipinranka 12:9a20164dcc47 286
vipinranka 12:9a20164dcc47 287 This function assigns the given value to the Translation Table Base Register 0.
vipinranka 12:9a20164dcc47 288
vipinranka 12:9a20164dcc47 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
vipinranka 12:9a20164dcc47 290 */
vipinranka 12:9a20164dcc47 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
vipinranka 12:9a20164dcc47 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
vipinranka 12:9a20164dcc47 293 __regTTBR0 = ttbr0;
vipinranka 12:9a20164dcc47 294 __ISB();
vipinranka 12:9a20164dcc47 295 }
vipinranka 12:9a20164dcc47 296
vipinranka 12:9a20164dcc47 297 /** \brief Get DACR
vipinranka 12:9a20164dcc47 298
vipinranka 12:9a20164dcc47 299 This function returns the value of the Domain Access Control Register.
vipinranka 12:9a20164dcc47 300
vipinranka 12:9a20164dcc47 301 \return Domain Access Control Register value
vipinranka 12:9a20164dcc47 302 */
vipinranka 12:9a20164dcc47 303 __STATIC_INLINE uint32_t __get_DACR() {
vipinranka 12:9a20164dcc47 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
vipinranka 12:9a20164dcc47 305 return(__regDACR);
vipinranka 12:9a20164dcc47 306 }
vipinranka 12:9a20164dcc47 307
vipinranka 12:9a20164dcc47 308 /** \brief Set DACR
vipinranka 12:9a20164dcc47 309
vipinranka 12:9a20164dcc47 310 This function assigns the given value to the Domain Access Control Register.
vipinranka 12:9a20164dcc47 311
vipinranka 12:9a20164dcc47 312 \param [in] dacr Domain Access Control Register value to set
vipinranka 12:9a20164dcc47 313 */
vipinranka 12:9a20164dcc47 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
vipinranka 12:9a20164dcc47 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
vipinranka 12:9a20164dcc47 316 __regDACR = dacr;
vipinranka 12:9a20164dcc47 317 __ISB();
vipinranka 12:9a20164dcc47 318 }
vipinranka 12:9a20164dcc47 319
vipinranka 12:9a20164dcc47 320 /******************************** Cache and BTAC enable ****************************************************/
vipinranka 12:9a20164dcc47 321
vipinranka 12:9a20164dcc47 322 /** \brief Set SCTLR
vipinranka 12:9a20164dcc47 323
vipinranka 12:9a20164dcc47 324 This function assigns the given value to the System Control Register.
vipinranka 12:9a20164dcc47 325
vipinranka 12:9a20164dcc47 326 \param [in] sctlr System Control Register value to set
vipinranka 12:9a20164dcc47 327 */
vipinranka 12:9a20164dcc47 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
vipinranka 12:9a20164dcc47 329 {
vipinranka 12:9a20164dcc47 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
vipinranka 12:9a20164dcc47 331 __regSCTLR = sctlr;
vipinranka 12:9a20164dcc47 332 }
vipinranka 12:9a20164dcc47 333
vipinranka 12:9a20164dcc47 334 /** \brief Get SCTLR
vipinranka 12:9a20164dcc47 335
vipinranka 12:9a20164dcc47 336 This function returns the value of the System Control Register.
vipinranka 12:9a20164dcc47 337
vipinranka 12:9a20164dcc47 338 \return System Control Register value
vipinranka 12:9a20164dcc47 339 */
vipinranka 12:9a20164dcc47 340 __STATIC_INLINE uint32_t __get_SCTLR() {
vipinranka 12:9a20164dcc47 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
vipinranka 12:9a20164dcc47 342 return(__regSCTLR);
vipinranka 12:9a20164dcc47 343 }
vipinranka 12:9a20164dcc47 344
vipinranka 12:9a20164dcc47 345 /** \brief Enable Caches
vipinranka 12:9a20164dcc47 346
vipinranka 12:9a20164dcc47 347 Enable Caches
vipinranka 12:9a20164dcc47 348 */
vipinranka 12:9a20164dcc47 349 __STATIC_INLINE void __enable_caches(void) {
vipinranka 12:9a20164dcc47 350 // Set I bit 12 to enable I Cache
vipinranka 12:9a20164dcc47 351 // Set C bit 2 to enable D Cache
vipinranka 12:9a20164dcc47 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
vipinranka 12:9a20164dcc47 353 }
vipinranka 12:9a20164dcc47 354
vipinranka 12:9a20164dcc47 355 /** \brief Disable Caches
vipinranka 12:9a20164dcc47 356
vipinranka 12:9a20164dcc47 357 Disable Caches
vipinranka 12:9a20164dcc47 358 */
vipinranka 12:9a20164dcc47 359 __STATIC_INLINE void __disable_caches(void) {
vipinranka 12:9a20164dcc47 360 // Clear I bit 12 to disable I Cache
vipinranka 12:9a20164dcc47 361 // Clear C bit 2 to disable D Cache
vipinranka 12:9a20164dcc47 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
vipinranka 12:9a20164dcc47 363 __ISB();
vipinranka 12:9a20164dcc47 364 }
vipinranka 12:9a20164dcc47 365
vipinranka 12:9a20164dcc47 366 /** \brief Enable BTAC
vipinranka 12:9a20164dcc47 367
vipinranka 12:9a20164dcc47 368 Enable BTAC
vipinranka 12:9a20164dcc47 369 */
vipinranka 12:9a20164dcc47 370 __STATIC_INLINE void __enable_btac(void) {
vipinranka 12:9a20164dcc47 371 // Set Z bit 11 to enable branch prediction
vipinranka 12:9a20164dcc47 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
vipinranka 12:9a20164dcc47 373 __ISB();
vipinranka 12:9a20164dcc47 374 }
vipinranka 12:9a20164dcc47 375
vipinranka 12:9a20164dcc47 376 /** \brief Disable BTAC
vipinranka 12:9a20164dcc47 377
vipinranka 12:9a20164dcc47 378 Disable BTAC
vipinranka 12:9a20164dcc47 379 */
vipinranka 12:9a20164dcc47 380 __STATIC_INLINE void __disable_btac(void) {
vipinranka 12:9a20164dcc47 381 // Clear Z bit 11 to disable branch prediction
vipinranka 12:9a20164dcc47 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
vipinranka 12:9a20164dcc47 383 }
vipinranka 12:9a20164dcc47 384
vipinranka 12:9a20164dcc47 385
vipinranka 12:9a20164dcc47 386 /** \brief Enable MMU
vipinranka 12:9a20164dcc47 387
vipinranka 12:9a20164dcc47 388 Enable MMU
vipinranka 12:9a20164dcc47 389 */
vipinranka 12:9a20164dcc47 390 __STATIC_INLINE void __enable_mmu(void) {
vipinranka 12:9a20164dcc47 391 // Set M bit 0 to enable the MMU
vipinranka 12:9a20164dcc47 392 // Set AFE bit to enable simplified access permissions model
vipinranka 12:9a20164dcc47 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
vipinranka 12:9a20164dcc47 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
vipinranka 12:9a20164dcc47 395 __ISB();
vipinranka 12:9a20164dcc47 396 }
vipinranka 12:9a20164dcc47 397
vipinranka 12:9a20164dcc47 398 /** \brief Disable MMU
vipinranka 12:9a20164dcc47 399
vipinranka 12:9a20164dcc47 400 Disable MMU
vipinranka 12:9a20164dcc47 401 */
vipinranka 12:9a20164dcc47 402 __STATIC_INLINE void __disable_mmu(void) {
vipinranka 12:9a20164dcc47 403 // Clear M bit 0 to disable the MMU
vipinranka 12:9a20164dcc47 404 __set_SCTLR( __get_SCTLR() & ~1);
vipinranka 12:9a20164dcc47 405 __ISB();
vipinranka 12:9a20164dcc47 406 }
vipinranka 12:9a20164dcc47 407
vipinranka 12:9a20164dcc47 408 /******************************** TLB maintenance operations ************************************************/
vipinranka 12:9a20164dcc47 409 /** \brief Invalidate the whole tlb
vipinranka 12:9a20164dcc47 410
vipinranka 12:9a20164dcc47 411 TLBIALL. Invalidate the whole tlb
vipinranka 12:9a20164dcc47 412 */
vipinranka 12:9a20164dcc47 413
vipinranka 12:9a20164dcc47 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
vipinranka 12:9a20164dcc47 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
vipinranka 12:9a20164dcc47 416 __TLBIALL = 0;
vipinranka 12:9a20164dcc47 417 __DSB();
vipinranka 12:9a20164dcc47 418 __ISB();
vipinranka 12:9a20164dcc47 419 }
vipinranka 12:9a20164dcc47 420
vipinranka 12:9a20164dcc47 421 /******************************** BTB maintenance operations ************************************************/
vipinranka 12:9a20164dcc47 422 /** \brief Invalidate entire branch predictor array
vipinranka 12:9a20164dcc47 423
vipinranka 12:9a20164dcc47 424 BPIALL. Branch Predictor Invalidate All.
vipinranka 12:9a20164dcc47 425 */
vipinranka 12:9a20164dcc47 426
vipinranka 12:9a20164dcc47 427 __STATIC_INLINE void __v7_inv_btac(void) {
vipinranka 12:9a20164dcc47 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
vipinranka 12:9a20164dcc47 429 __BPIALL = 0;
vipinranka 12:9a20164dcc47 430 __DSB(); //ensure completion of the invalidation
vipinranka 12:9a20164dcc47 431 __ISB(); //ensure instruction fetch path sees new state
vipinranka 12:9a20164dcc47 432 }
vipinranka 12:9a20164dcc47 433
vipinranka 12:9a20164dcc47 434
vipinranka 12:9a20164dcc47 435 /******************************** L1 cache operations ******************************************************/
vipinranka 12:9a20164dcc47 436
vipinranka 12:9a20164dcc47 437 /** \brief Invalidate the whole I$
vipinranka 12:9a20164dcc47 438
vipinranka 12:9a20164dcc47 439 ICIALLU. Instruction Cache Invalidate All to PoU
vipinranka 12:9a20164dcc47 440 */
vipinranka 12:9a20164dcc47 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
vipinranka 12:9a20164dcc47 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
vipinranka 12:9a20164dcc47 443 __ICIALLU = 0;
vipinranka 12:9a20164dcc47 444 __DSB(); //ensure completion of the invalidation
vipinranka 12:9a20164dcc47 445 __ISB(); //ensure instruction fetch path sees new I cache state
vipinranka 12:9a20164dcc47 446 }
vipinranka 12:9a20164dcc47 447
vipinranka 12:9a20164dcc47 448 /** \brief Clean D$ by MVA
vipinranka 12:9a20164dcc47 449
vipinranka 12:9a20164dcc47 450 DCCMVAC. Data cache clean by MVA to PoC
vipinranka 12:9a20164dcc47 451 */
vipinranka 12:9a20164dcc47 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
vipinranka 12:9a20164dcc47 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
vipinranka 12:9a20164dcc47 454 __DCCMVAC = (uint32_t)va;
vipinranka 12:9a20164dcc47 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vipinranka 12:9a20164dcc47 456 }
vipinranka 12:9a20164dcc47 457
vipinranka 12:9a20164dcc47 458 /** \brief Invalidate D$ by MVA
vipinranka 12:9a20164dcc47 459
vipinranka 12:9a20164dcc47 460 DCIMVAC. Data cache invalidate by MVA to PoC
vipinranka 12:9a20164dcc47 461 */
vipinranka 12:9a20164dcc47 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
vipinranka 12:9a20164dcc47 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
vipinranka 12:9a20164dcc47 464 __DCIMVAC = (uint32_t)va;
vipinranka 12:9a20164dcc47 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vipinranka 12:9a20164dcc47 466 }
vipinranka 12:9a20164dcc47 467
vipinranka 12:9a20164dcc47 468 /** \brief Clean and Invalidate D$ by MVA
vipinranka 12:9a20164dcc47 469
vipinranka 12:9a20164dcc47 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
vipinranka 12:9a20164dcc47 471 */
vipinranka 12:9a20164dcc47 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
vipinranka 12:9a20164dcc47 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
vipinranka 12:9a20164dcc47 474 __DCCIMVAC = (uint32_t)va;
vipinranka 12:9a20164dcc47 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vipinranka 12:9a20164dcc47 476 }
vipinranka 12:9a20164dcc47 477
vipinranka 12:9a20164dcc47 478 /** \brief Clean and Invalidate the entire data or unified cache
vipinranka 12:9a20164dcc47 479
vipinranka 12:9a20164dcc47 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
vipinranka 12:9a20164dcc47 481 */
vipinranka 12:9a20164dcc47 482 #pragma push
vipinranka 12:9a20164dcc47 483 #pragma arm
vipinranka 12:9a20164dcc47 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
vipinranka 12:9a20164dcc47 485 ARM
vipinranka 12:9a20164dcc47 486
vipinranka 12:9a20164dcc47 487 PUSH {R4-R11}
vipinranka 12:9a20164dcc47 488
vipinranka 12:9a20164dcc47 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
vipinranka 12:9a20164dcc47 490 ANDS R3, R6, #0x07000000 // Extract coherency level
vipinranka 12:9a20164dcc47 491 MOV R3, R3, LSR #23 // Total cache levels << 1
vipinranka 12:9a20164dcc47 492 BEQ Finished // If 0, no need to clean
vipinranka 12:9a20164dcc47 493
vipinranka 12:9a20164dcc47 494 MOV R10, #0 // R10 holds current cache level << 1
vipinranka 12:9a20164dcc47 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
vipinranka 12:9a20164dcc47 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
vipinranka 12:9a20164dcc47 497 AND R1, R1, #7 // Isolate those lower 3 bits
vipinranka 12:9a20164dcc47 498 CMP R1, #2
vipinranka 12:9a20164dcc47 499 BLT Skip // No cache or only instruction cache at this level
vipinranka 12:9a20164dcc47 500
vipinranka 12:9a20164dcc47 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
vipinranka 12:9a20164dcc47 502 ISB // ISB to sync the change to the CacheSizeID reg
vipinranka 12:9a20164dcc47 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
vipinranka 12:9a20164dcc47 504 AND R2, R1, #7 // Extract the line length field
vipinranka 12:9a20164dcc47 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
vipinranka 12:9a20164dcc47 506 LDR R4, =0x3FF
vipinranka 12:9a20164dcc47 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
vipinranka 12:9a20164dcc47 508 CLZ R5, R4 // R5 is the bit position of the way size increment
vipinranka 12:9a20164dcc47 509 LDR R7, =0x7FFF
vipinranka 12:9a20164dcc47 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
vipinranka 12:9a20164dcc47 511
vipinranka 12:9a20164dcc47 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
vipinranka 12:9a20164dcc47 513
vipinranka 12:9a20164dcc47 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
vipinranka 12:9a20164dcc47 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
vipinranka 12:9a20164dcc47 516 CMP R0, #0
vipinranka 12:9a20164dcc47 517 BNE Dccsw
vipinranka 12:9a20164dcc47 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
vipinranka 12:9a20164dcc47 519 B cont
vipinranka 12:9a20164dcc47 520 Dccsw CMP R0, #1
vipinranka 12:9a20164dcc47 521 BNE Dccisw
vipinranka 12:9a20164dcc47 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
vipinranka 12:9a20164dcc47 523 B cont
vipinranka 12:9a20164dcc47 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
vipinranka 12:9a20164dcc47 525 cont SUBS R9, R9, #1 // Decrement the Way number
vipinranka 12:9a20164dcc47 526 BGE Loop3
vipinranka 12:9a20164dcc47 527 SUBS R7, R7, #1 // Decrement the Set number
vipinranka 12:9a20164dcc47 528 BGE Loop2
vipinranka 12:9a20164dcc47 529 Skip ADD R10, R10, #2 // Increment the cache number
vipinranka 12:9a20164dcc47 530 CMP R3, R10
vipinranka 12:9a20164dcc47 531 BGT Loop1
vipinranka 12:9a20164dcc47 532
vipinranka 12:9a20164dcc47 533 Finished
vipinranka 12:9a20164dcc47 534 DSB
vipinranka 12:9a20164dcc47 535 POP {R4-R11}
vipinranka 12:9a20164dcc47 536 BX lr
vipinranka 12:9a20164dcc47 537
vipinranka 12:9a20164dcc47 538 }
vipinranka 12:9a20164dcc47 539 #pragma pop
vipinranka 12:9a20164dcc47 540
vipinranka 12:9a20164dcc47 541
vipinranka 12:9a20164dcc47 542 /** \brief Invalidate the whole D$
vipinranka 12:9a20164dcc47 543
vipinranka 12:9a20164dcc47 544 DCISW. Invalidate by Set/Way
vipinranka 12:9a20164dcc47 545 */
vipinranka 12:9a20164dcc47 546
vipinranka 12:9a20164dcc47 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
vipinranka 12:9a20164dcc47 548 __v7_all_cache(0);
vipinranka 12:9a20164dcc47 549 }
vipinranka 12:9a20164dcc47 550
vipinranka 12:9a20164dcc47 551 /** \brief Clean the whole D$
vipinranka 12:9a20164dcc47 552
vipinranka 12:9a20164dcc47 553 DCCSW. Clean by Set/Way
vipinranka 12:9a20164dcc47 554 */
vipinranka 12:9a20164dcc47 555
vipinranka 12:9a20164dcc47 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
vipinranka 12:9a20164dcc47 557 __v7_all_cache(1);
vipinranka 12:9a20164dcc47 558 }
vipinranka 12:9a20164dcc47 559
vipinranka 12:9a20164dcc47 560 /** \brief Clean and invalidate the whole D$
vipinranka 12:9a20164dcc47 561
vipinranka 12:9a20164dcc47 562 DCCISW. Clean and Invalidate by Set/Way
vipinranka 12:9a20164dcc47 563 */
vipinranka 12:9a20164dcc47 564
vipinranka 12:9a20164dcc47 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
vipinranka 12:9a20164dcc47 566 __v7_all_cache(2);
vipinranka 12:9a20164dcc47 567 }
vipinranka 12:9a20164dcc47 568
vipinranka 12:9a20164dcc47 569 #include "core_ca_mmu.h"
vipinranka 12:9a20164dcc47 570
vipinranka 12:9a20164dcc47 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
vipinranka 12:9a20164dcc47 572
vipinranka 12:9a20164dcc47 573 #define __inline inline
vipinranka 12:9a20164dcc47 574
vipinranka 12:9a20164dcc47 575 inline static uint32_t __disable_irq_iar() {
vipinranka 12:9a20164dcc47 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
vipinranka 12:9a20164dcc47 577 __disable_irq();
vipinranka 12:9a20164dcc47 578 return irq_dis;
vipinranka 12:9a20164dcc47 579 }
vipinranka 12:9a20164dcc47 580
vipinranka 12:9a20164dcc47 581 #define MODE_USR 0x10
vipinranka 12:9a20164dcc47 582 #define MODE_FIQ 0x11
vipinranka 12:9a20164dcc47 583 #define MODE_IRQ 0x12
vipinranka 12:9a20164dcc47 584 #define MODE_SVC 0x13
vipinranka 12:9a20164dcc47 585 #define MODE_MON 0x16
vipinranka 12:9a20164dcc47 586 #define MODE_ABT 0x17
vipinranka 12:9a20164dcc47 587 #define MODE_HYP 0x1A
vipinranka 12:9a20164dcc47 588 #define MODE_UND 0x1B
vipinranka 12:9a20164dcc47 589 #define MODE_SYS 0x1F
vipinranka 12:9a20164dcc47 590
vipinranka 12:9a20164dcc47 591 /** \brief Set Process Stack Pointer
vipinranka 12:9a20164dcc47 592
vipinranka 12:9a20164dcc47 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
vipinranka 12:9a20164dcc47 594
vipinranka 12:9a20164dcc47 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
vipinranka 12:9a20164dcc47 596 */
vipinranka 12:9a20164dcc47 597 // from rt_CMSIS.c
vipinranka 12:9a20164dcc47 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
vipinranka 12:9a20164dcc47 599 __asm(
vipinranka 12:9a20164dcc47 600 " ARM\n"
vipinranka 12:9a20164dcc47 601 // " PRESERVE8\n"
vipinranka 12:9a20164dcc47 602
vipinranka 12:9a20164dcc47 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
vipinranka 12:9a20164dcc47 604 " MRS R1, CPSR \n"
vipinranka 12:9a20164dcc47 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
vipinranka 12:9a20164dcc47 606 " MOV SP, R0 \n"
vipinranka 12:9a20164dcc47 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
vipinranka 12:9a20164dcc47 608 " ISB \n"
vipinranka 12:9a20164dcc47 609 " BX LR \n");
vipinranka 12:9a20164dcc47 610 }
vipinranka 12:9a20164dcc47 611
vipinranka 12:9a20164dcc47 612 /** \brief Set User Mode
vipinranka 12:9a20164dcc47 613
vipinranka 12:9a20164dcc47 614 This function changes the processor state to User Mode
vipinranka 12:9a20164dcc47 615 */
vipinranka 12:9a20164dcc47 616 // from rt_CMSIS.c
vipinranka 12:9a20164dcc47 617 __arm static inline void __set_CPS_USR(void) {
vipinranka 12:9a20164dcc47 618 __asm(
vipinranka 12:9a20164dcc47 619 " ARM \n"
vipinranka 12:9a20164dcc47 620
vipinranka 12:9a20164dcc47 621 " CPS #0x10 \n" // MODE_USR
vipinranka 12:9a20164dcc47 622 " BX LR\n");
vipinranka 12:9a20164dcc47 623 }
vipinranka 12:9a20164dcc47 624
vipinranka 12:9a20164dcc47 625 /** \brief Set TTBR0
vipinranka 12:9a20164dcc47 626
vipinranka 12:9a20164dcc47 627 This function assigns the given value to the Translation Table Base Register 0.
vipinranka 12:9a20164dcc47 628
vipinranka 12:9a20164dcc47 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
vipinranka 12:9a20164dcc47 630 */
vipinranka 12:9a20164dcc47 631 // from mmu_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
vipinranka 12:9a20164dcc47 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
vipinranka 12:9a20164dcc47 634 __ISB();
vipinranka 12:9a20164dcc47 635 }
vipinranka 12:9a20164dcc47 636
vipinranka 12:9a20164dcc47 637 /** \brief Set DACR
vipinranka 12:9a20164dcc47 638
vipinranka 12:9a20164dcc47 639 This function assigns the given value to the Domain Access Control Register.
vipinranka 12:9a20164dcc47 640
vipinranka 12:9a20164dcc47 641 \param [in] dacr Domain Access Control Register value to set
vipinranka 12:9a20164dcc47 642 */
vipinranka 12:9a20164dcc47 643 // from mmu_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
vipinranka 12:9a20164dcc47 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
vipinranka 12:9a20164dcc47 646 __ISB();
vipinranka 12:9a20164dcc47 647 }
vipinranka 12:9a20164dcc47 648
vipinranka 12:9a20164dcc47 649
vipinranka 12:9a20164dcc47 650 /******************************** Cache and BTAC enable ****************************************************/
vipinranka 12:9a20164dcc47 651 /** \brief Set SCTLR
vipinranka 12:9a20164dcc47 652
vipinranka 12:9a20164dcc47 653 This function assigns the given value to the System Control Register.
vipinranka 12:9a20164dcc47 654
vipinranka 12:9a20164dcc47 655 \param [in] sctlr System Control Register value to set
vipinranka 12:9a20164dcc47 656 */
vipinranka 12:9a20164dcc47 657 // from __enable_mmu()
vipinranka 12:9a20164dcc47 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
vipinranka 12:9a20164dcc47 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
vipinranka 12:9a20164dcc47 660 }
vipinranka 12:9a20164dcc47 661
vipinranka 12:9a20164dcc47 662 /** \brief Get SCTLR
vipinranka 12:9a20164dcc47 663
vipinranka 12:9a20164dcc47 664 This function returns the value of the System Control Register.
vipinranka 12:9a20164dcc47 665
vipinranka 12:9a20164dcc47 666 \return System Control Register value
vipinranka 12:9a20164dcc47 667 */
vipinranka 12:9a20164dcc47 668 // from __enable_mmu()
vipinranka 12:9a20164dcc47 669 __STATIC_INLINE uint32_t __get_SCTLR() {
vipinranka 12:9a20164dcc47 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
vipinranka 12:9a20164dcc47 671 return __regSCTLR;
vipinranka 12:9a20164dcc47 672 }
vipinranka 12:9a20164dcc47 673
vipinranka 12:9a20164dcc47 674 /** \brief Enable Caches
vipinranka 12:9a20164dcc47 675
vipinranka 12:9a20164dcc47 676 Enable Caches
vipinranka 12:9a20164dcc47 677 */
vipinranka 12:9a20164dcc47 678 // from system_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 679 __STATIC_INLINE void __enable_caches(void) {
vipinranka 12:9a20164dcc47 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
vipinranka 12:9a20164dcc47 681 }
vipinranka 12:9a20164dcc47 682
vipinranka 12:9a20164dcc47 683 /** \brief Enable BTAC
vipinranka 12:9a20164dcc47 684
vipinranka 12:9a20164dcc47 685 Enable BTAC
vipinranka 12:9a20164dcc47 686 */
vipinranka 12:9a20164dcc47 687 // from system_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 688 __STATIC_INLINE void __enable_btac(void) {
vipinranka 12:9a20164dcc47 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
vipinranka 12:9a20164dcc47 690 __ISB();
vipinranka 12:9a20164dcc47 691 }
vipinranka 12:9a20164dcc47 692
vipinranka 12:9a20164dcc47 693 /** \brief Enable MMU
vipinranka 12:9a20164dcc47 694
vipinranka 12:9a20164dcc47 695 Enable MMU
vipinranka 12:9a20164dcc47 696 */
vipinranka 12:9a20164dcc47 697 // from system_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 698 __STATIC_INLINE void __enable_mmu(void) {
vipinranka 12:9a20164dcc47 699 // Set M bit 0 to enable the MMU
vipinranka 12:9a20164dcc47 700 // Set AFE bit to enable simplified access permissions model
vipinranka 12:9a20164dcc47 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
vipinranka 12:9a20164dcc47 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
vipinranka 12:9a20164dcc47 703 __ISB();
vipinranka 12:9a20164dcc47 704 }
vipinranka 12:9a20164dcc47 705
vipinranka 12:9a20164dcc47 706 /******************************** TLB maintenance operations ************************************************/
vipinranka 12:9a20164dcc47 707 /** \brief Invalidate the whole tlb
vipinranka 12:9a20164dcc47 708
vipinranka 12:9a20164dcc47 709 TLBIALL. Invalidate the whole tlb
vipinranka 12:9a20164dcc47 710 */
vipinranka 12:9a20164dcc47 711 // from system_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
vipinranka 12:9a20164dcc47 713 uint32_t val = 0;
vipinranka 12:9a20164dcc47 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
vipinranka 12:9a20164dcc47 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
vipinranka 12:9a20164dcc47 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
vipinranka 12:9a20164dcc47 717 __DSB();
vipinranka 12:9a20164dcc47 718 __ISB();
vipinranka 12:9a20164dcc47 719 }
vipinranka 12:9a20164dcc47 720
vipinranka 12:9a20164dcc47 721 /******************************** BTB maintenance operations ************************************************/
vipinranka 12:9a20164dcc47 722 /** \brief Invalidate entire branch predictor array
vipinranka 12:9a20164dcc47 723
vipinranka 12:9a20164dcc47 724 BPIALL. Branch Predictor Invalidate All.
vipinranka 12:9a20164dcc47 725 */
vipinranka 12:9a20164dcc47 726 // from system_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 727 __STATIC_INLINE void __v7_inv_btac(void) {
vipinranka 12:9a20164dcc47 728 uint32_t val = 0;
vipinranka 12:9a20164dcc47 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
vipinranka 12:9a20164dcc47 730 __DSB(); //ensure completion of the invalidation
vipinranka 12:9a20164dcc47 731 __ISB(); //ensure instruction fetch path sees new state
vipinranka 12:9a20164dcc47 732 }
vipinranka 12:9a20164dcc47 733
vipinranka 12:9a20164dcc47 734
vipinranka 12:9a20164dcc47 735 /******************************** L1 cache operations ******************************************************/
vipinranka 12:9a20164dcc47 736
vipinranka 12:9a20164dcc47 737 /** \brief Invalidate the whole I$
vipinranka 12:9a20164dcc47 738
vipinranka 12:9a20164dcc47 739 ICIALLU. Instruction Cache Invalidate All to PoU
vipinranka 12:9a20164dcc47 740 */
vipinranka 12:9a20164dcc47 741 // from system_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
vipinranka 12:9a20164dcc47 743 uint32_t val = 0;
vipinranka 12:9a20164dcc47 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
vipinranka 12:9a20164dcc47 745 __DSB(); //ensure completion of the invalidation
vipinranka 12:9a20164dcc47 746 __ISB(); //ensure instruction fetch path sees new I cache state
vipinranka 12:9a20164dcc47 747 }
vipinranka 12:9a20164dcc47 748
vipinranka 12:9a20164dcc47 749 // from __v7_inv_dcache_all()
vipinranka 12:9a20164dcc47 750 __arm static inline void __v7_all_cache(uint32_t op) {
vipinranka 12:9a20164dcc47 751 __asm(
vipinranka 12:9a20164dcc47 752 " ARM \n"
vipinranka 12:9a20164dcc47 753
vipinranka 12:9a20164dcc47 754 " PUSH {R4-R11} \n"
vipinranka 12:9a20164dcc47 755
vipinranka 12:9a20164dcc47 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
vipinranka 12:9a20164dcc47 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
vipinranka 12:9a20164dcc47 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
vipinranka 12:9a20164dcc47 759 " BEQ Finished\n" // If 0, no need to clean
vipinranka 12:9a20164dcc47 760
vipinranka 12:9a20164dcc47 761 " MOV R10, #0\n" // R10 holds current cache level << 1
vipinranka 12:9a20164dcc47 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
vipinranka 12:9a20164dcc47 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
vipinranka 12:9a20164dcc47 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
vipinranka 12:9a20164dcc47 765 " CMP R1, #2 \n"
vipinranka 12:9a20164dcc47 766 " BLT Skip \n" // No cache or only instruction cache at this level
vipinranka 12:9a20164dcc47 767
vipinranka 12:9a20164dcc47 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
vipinranka 12:9a20164dcc47 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
vipinranka 12:9a20164dcc47 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
vipinranka 12:9a20164dcc47 771 " AND R2, R1, #7 \n" // Extract the line length field
vipinranka 12:9a20164dcc47 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
vipinranka 12:9a20164dcc47 773 " movw R4, #0x3FF \n"
vipinranka 12:9a20164dcc47 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
vipinranka 12:9a20164dcc47 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
vipinranka 12:9a20164dcc47 776 " movw R7, #0x7FFF \n"
vipinranka 12:9a20164dcc47 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
vipinranka 12:9a20164dcc47 778
vipinranka 12:9a20164dcc47 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
vipinranka 12:9a20164dcc47 780
vipinranka 12:9a20164dcc47 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
vipinranka 12:9a20164dcc47 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
vipinranka 12:9a20164dcc47 783 " CMP R0, #0 \n"
vipinranka 12:9a20164dcc47 784 " BNE Dccsw \n"
vipinranka 12:9a20164dcc47 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
vipinranka 12:9a20164dcc47 786 " B cont \n"
vipinranka 12:9a20164dcc47 787 "Dccsw: CMP R0, #1 \n"
vipinranka 12:9a20164dcc47 788 " BNE Dccisw \n"
vipinranka 12:9a20164dcc47 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
vipinranka 12:9a20164dcc47 790 " B cont \n"
vipinranka 12:9a20164dcc47 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
vipinranka 12:9a20164dcc47 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
vipinranka 12:9a20164dcc47 793 " BGE Loop3 \n"
vipinranka 12:9a20164dcc47 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
vipinranka 12:9a20164dcc47 795 " BGE Loop2 \n"
vipinranka 12:9a20164dcc47 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
vipinranka 12:9a20164dcc47 797 " CMP R3, R10 \n"
vipinranka 12:9a20164dcc47 798 " BGT Loop1 \n"
vipinranka 12:9a20164dcc47 799
vipinranka 12:9a20164dcc47 800 "Finished: \n"
vipinranka 12:9a20164dcc47 801 " DSB \n"
vipinranka 12:9a20164dcc47 802 " POP {R4-R11} \n"
vipinranka 12:9a20164dcc47 803 " BX lr \n" );
vipinranka 12:9a20164dcc47 804 }
vipinranka 12:9a20164dcc47 805
vipinranka 12:9a20164dcc47 806 /** \brief Invalidate the whole D$
vipinranka 12:9a20164dcc47 807
vipinranka 12:9a20164dcc47 808 DCISW. Invalidate by Set/Way
vipinranka 12:9a20164dcc47 809 */
vipinranka 12:9a20164dcc47 810 // from system_Renesas_RZ_A1.c
vipinranka 12:9a20164dcc47 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
vipinranka 12:9a20164dcc47 812 __v7_all_cache(0);
vipinranka 12:9a20164dcc47 813 }
vipinranka 12:9a20164dcc47 814 /** \brief Clean the whole D$
vipinranka 12:9a20164dcc47 815
vipinranka 12:9a20164dcc47 816 DCCSW. Clean by Set/Way
vipinranka 12:9a20164dcc47 817 */
vipinranka 12:9a20164dcc47 818
vipinranka 12:9a20164dcc47 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
vipinranka 12:9a20164dcc47 820 __v7_all_cache(1);
vipinranka 12:9a20164dcc47 821 }
vipinranka 12:9a20164dcc47 822
vipinranka 12:9a20164dcc47 823 /** \brief Clean and invalidate the whole D$
vipinranka 12:9a20164dcc47 824
vipinranka 12:9a20164dcc47 825 DCCISW. Clean and Invalidate by Set/Way
vipinranka 12:9a20164dcc47 826 */
vipinranka 12:9a20164dcc47 827
vipinranka 12:9a20164dcc47 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
vipinranka 12:9a20164dcc47 829 __v7_all_cache(2);
vipinranka 12:9a20164dcc47 830 }
vipinranka 12:9a20164dcc47 831 /** \brief Clean and Invalidate D$ by MVA
vipinranka 12:9a20164dcc47 832
vipinranka 12:9a20164dcc47 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
vipinranka 12:9a20164dcc47 834 */
vipinranka 12:9a20164dcc47 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
vipinranka 12:9a20164dcc47 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
vipinranka 12:9a20164dcc47 837 __DMB();
vipinranka 12:9a20164dcc47 838 }
vipinranka 12:9a20164dcc47 839
vipinranka 12:9a20164dcc47 840 #include "core_ca_mmu.h"
vipinranka 12:9a20164dcc47 841
vipinranka 12:9a20164dcc47 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
vipinranka 12:9a20164dcc47 843 /* GNU gcc specific functions */
vipinranka 12:9a20164dcc47 844
vipinranka 12:9a20164dcc47 845 #define MODE_USR 0x10
vipinranka 12:9a20164dcc47 846 #define MODE_FIQ 0x11
vipinranka 12:9a20164dcc47 847 #define MODE_IRQ 0x12
vipinranka 12:9a20164dcc47 848 #define MODE_SVC 0x13
vipinranka 12:9a20164dcc47 849 #define MODE_MON 0x16
vipinranka 12:9a20164dcc47 850 #define MODE_ABT 0x17
vipinranka 12:9a20164dcc47 851 #define MODE_HYP 0x1A
vipinranka 12:9a20164dcc47 852 #define MODE_UND 0x1B
vipinranka 12:9a20164dcc47 853 #define MODE_SYS 0x1F
vipinranka 12:9a20164dcc47 854
vipinranka 12:9a20164dcc47 855
vipinranka 12:9a20164dcc47 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
vipinranka 12:9a20164dcc47 857 {
vipinranka 12:9a20164dcc47 858 __ASM volatile ("cpsie i");
vipinranka 12:9a20164dcc47 859 }
vipinranka 12:9a20164dcc47 860
vipinranka 12:9a20164dcc47 861 /** \brief Disable IRQ Interrupts
vipinranka 12:9a20164dcc47 862
vipinranka 12:9a20164dcc47 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
vipinranka 12:9a20164dcc47 864 Can only be executed in Privileged modes.
vipinranka 12:9a20164dcc47 865 */
vipinranka 12:9a20164dcc47 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
vipinranka 12:9a20164dcc47 867 {
vipinranka 12:9a20164dcc47 868 uint32_t result;
vipinranka 12:9a20164dcc47 869
vipinranka 12:9a20164dcc47 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
vipinranka 12:9a20164dcc47 871 __ASM volatile ("cpsid i");
vipinranka 12:9a20164dcc47 872 return(result & 0x80);
vipinranka 12:9a20164dcc47 873 }
vipinranka 12:9a20164dcc47 874
vipinranka 12:9a20164dcc47 875
vipinranka 12:9a20164dcc47 876 /** \brief Get APSR Register
vipinranka 12:9a20164dcc47 877
vipinranka 12:9a20164dcc47 878 This function returns the content of the APSR Register.
vipinranka 12:9a20164dcc47 879
vipinranka 12:9a20164dcc47 880 \return APSR Register value
vipinranka 12:9a20164dcc47 881 */
vipinranka 12:9a20164dcc47 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
vipinranka 12:9a20164dcc47 883 {
vipinranka 12:9a20164dcc47 884 #if 1
vipinranka 12:9a20164dcc47 885 register uint32_t __regAPSR;
vipinranka 12:9a20164dcc47 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
vipinranka 12:9a20164dcc47 887 #else
vipinranka 12:9a20164dcc47 888 register uint32_t __regAPSR __ASM("apsr");
vipinranka 12:9a20164dcc47 889 #endif
vipinranka 12:9a20164dcc47 890 return(__regAPSR);
vipinranka 12:9a20164dcc47 891 }
vipinranka 12:9a20164dcc47 892
vipinranka 12:9a20164dcc47 893
vipinranka 12:9a20164dcc47 894 /** \brief Get CPSR Register
vipinranka 12:9a20164dcc47 895
vipinranka 12:9a20164dcc47 896 This function returns the content of the CPSR Register.
vipinranka 12:9a20164dcc47 897
vipinranka 12:9a20164dcc47 898 \return CPSR Register value
vipinranka 12:9a20164dcc47 899 */
vipinranka 12:9a20164dcc47 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
vipinranka 12:9a20164dcc47 901 {
vipinranka 12:9a20164dcc47 902 #if 1
vipinranka 12:9a20164dcc47 903 register uint32_t __regCPSR;
vipinranka 12:9a20164dcc47 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
vipinranka 12:9a20164dcc47 905 #else
vipinranka 12:9a20164dcc47 906 register uint32_t __regCPSR __ASM("cpsr");
vipinranka 12:9a20164dcc47 907 #endif
vipinranka 12:9a20164dcc47 908 return(__regCPSR);
vipinranka 12:9a20164dcc47 909 }
vipinranka 12:9a20164dcc47 910
vipinranka 12:9a20164dcc47 911 #if 0
vipinranka 12:9a20164dcc47 912 /** \brief Set Stack Pointer
vipinranka 12:9a20164dcc47 913
vipinranka 12:9a20164dcc47 914 This function assigns the given value to the current stack pointer.
vipinranka 12:9a20164dcc47 915
vipinranka 12:9a20164dcc47 916 \param [in] topOfStack Stack Pointer value to set
vipinranka 12:9a20164dcc47 917 */
vipinranka 12:9a20164dcc47 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
vipinranka 12:9a20164dcc47 919 {
vipinranka 12:9a20164dcc47 920 register uint32_t __regSP __ASM("sp");
vipinranka 12:9a20164dcc47 921 __regSP = topOfStack;
vipinranka 12:9a20164dcc47 922 }
vipinranka 12:9a20164dcc47 923 #endif
vipinranka 12:9a20164dcc47 924
vipinranka 12:9a20164dcc47 925 /** \brief Get link register
vipinranka 12:9a20164dcc47 926
vipinranka 12:9a20164dcc47 927 This function returns the value of the link register
vipinranka 12:9a20164dcc47 928
vipinranka 12:9a20164dcc47 929 \return Value of link register
vipinranka 12:9a20164dcc47 930 */
vipinranka 12:9a20164dcc47 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
vipinranka 12:9a20164dcc47 932 {
vipinranka 12:9a20164dcc47 933 register uint32_t __reglr __ASM("lr");
vipinranka 12:9a20164dcc47 934 return(__reglr);
vipinranka 12:9a20164dcc47 935 }
vipinranka 12:9a20164dcc47 936
vipinranka 12:9a20164dcc47 937 #if 0
vipinranka 12:9a20164dcc47 938 /** \brief Set link register
vipinranka 12:9a20164dcc47 939
vipinranka 12:9a20164dcc47 940 This function sets the value of the link register
vipinranka 12:9a20164dcc47 941
vipinranka 12:9a20164dcc47 942 \param [in] lr LR value to set
vipinranka 12:9a20164dcc47 943 */
vipinranka 12:9a20164dcc47 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
vipinranka 12:9a20164dcc47 945 {
vipinranka 12:9a20164dcc47 946 register uint32_t __reglr __ASM("lr");
vipinranka 12:9a20164dcc47 947 __reglr = lr;
vipinranka 12:9a20164dcc47 948 }
vipinranka 12:9a20164dcc47 949 #endif
vipinranka 12:9a20164dcc47 950
vipinranka 12:9a20164dcc47 951 /** \brief Set Process Stack Pointer
vipinranka 12:9a20164dcc47 952
vipinranka 12:9a20164dcc47 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
vipinranka 12:9a20164dcc47 954
vipinranka 12:9a20164dcc47 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
vipinranka 12:9a20164dcc47 956 */
vipinranka 12:9a20164dcc47 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
vipinranka 12:9a20164dcc47 958 {
vipinranka 12:9a20164dcc47 959 __asm__ volatile (
vipinranka 12:9a20164dcc47 960 ".ARM;"
vipinranka 12:9a20164dcc47 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
vipinranka 12:9a20164dcc47 962
vipinranka 12:9a20164dcc47 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
vipinranka 12:9a20164dcc47 964 "MRS R1, CPSR;"
vipinranka 12:9a20164dcc47 965 "CPS %0;" /* ;no effect in USR mode */
vipinranka 12:9a20164dcc47 966 "MOV SP, R0;"
vipinranka 12:9a20164dcc47 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
vipinranka 12:9a20164dcc47 968 "ISB;"
vipinranka 12:9a20164dcc47 969 //"BX LR;"
vipinranka 12:9a20164dcc47 970 :
vipinranka 12:9a20164dcc47 971 : "i"(MODE_SYS)
vipinranka 12:9a20164dcc47 972 : "r0", "r1");
vipinranka 12:9a20164dcc47 973 return;
vipinranka 12:9a20164dcc47 974 }
vipinranka 12:9a20164dcc47 975
vipinranka 12:9a20164dcc47 976 /** \brief Set User Mode
vipinranka 12:9a20164dcc47 977
vipinranka 12:9a20164dcc47 978 This function changes the processor state to User Mode
vipinranka 12:9a20164dcc47 979 */
vipinranka 12:9a20164dcc47 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
vipinranka 12:9a20164dcc47 981 {
vipinranka 12:9a20164dcc47 982 __asm__ volatile (
vipinranka 12:9a20164dcc47 983 ".ARM;"
vipinranka 12:9a20164dcc47 984
vipinranka 12:9a20164dcc47 985 "CPS %0;"
vipinranka 12:9a20164dcc47 986 //"BX LR;"
vipinranka 12:9a20164dcc47 987 :
vipinranka 12:9a20164dcc47 988 : "i"(MODE_USR)
vipinranka 12:9a20164dcc47 989 : );
vipinranka 12:9a20164dcc47 990 return;
vipinranka 12:9a20164dcc47 991 }
vipinranka 12:9a20164dcc47 992
vipinranka 12:9a20164dcc47 993
vipinranka 12:9a20164dcc47 994 /** \brief Enable FIQ
vipinranka 12:9a20164dcc47 995
vipinranka 12:9a20164dcc47 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
vipinranka 12:9a20164dcc47 997 Can only be executed in Privileged modes.
vipinranka 12:9a20164dcc47 998 */
vipinranka 12:9a20164dcc47 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
vipinranka 12:9a20164dcc47 1000
vipinranka 12:9a20164dcc47 1001
vipinranka 12:9a20164dcc47 1002 /** \brief Disable FIQ
vipinranka 12:9a20164dcc47 1003
vipinranka 12:9a20164dcc47 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
vipinranka 12:9a20164dcc47 1005 Can only be executed in Privileged modes.
vipinranka 12:9a20164dcc47 1006 */
vipinranka 12:9a20164dcc47 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
vipinranka 12:9a20164dcc47 1008
vipinranka 12:9a20164dcc47 1009
vipinranka 12:9a20164dcc47 1010 /** \brief Get FPSCR
vipinranka 12:9a20164dcc47 1011
vipinranka 12:9a20164dcc47 1012 This function returns the current value of the Floating Point Status/Control register.
vipinranka 12:9a20164dcc47 1013
vipinranka 12:9a20164dcc47 1014 \return Floating Point Status/Control register value
vipinranka 12:9a20164dcc47 1015 */
vipinranka 12:9a20164dcc47 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
vipinranka 12:9a20164dcc47 1017 {
vipinranka 12:9a20164dcc47 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vipinranka 12:9a20164dcc47 1019 #if 1
vipinranka 12:9a20164dcc47 1020 uint32_t result;
vipinranka 12:9a20164dcc47 1021
vipinranka 12:9a20164dcc47 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
vipinranka 12:9a20164dcc47 1023 return (result);
vipinranka 12:9a20164dcc47 1024 #else
vipinranka 12:9a20164dcc47 1025 register uint32_t __regfpscr __ASM("fpscr");
vipinranka 12:9a20164dcc47 1026 return(__regfpscr);
vipinranka 12:9a20164dcc47 1027 #endif
vipinranka 12:9a20164dcc47 1028 #else
vipinranka 12:9a20164dcc47 1029 return(0);
vipinranka 12:9a20164dcc47 1030 #endif
vipinranka 12:9a20164dcc47 1031 }
vipinranka 12:9a20164dcc47 1032
vipinranka 12:9a20164dcc47 1033
vipinranka 12:9a20164dcc47 1034 /** \brief Set FPSCR
vipinranka 12:9a20164dcc47 1035
vipinranka 12:9a20164dcc47 1036 This function assigns the given value to the Floating Point Status/Control register.
vipinranka 12:9a20164dcc47 1037
vipinranka 12:9a20164dcc47 1038 \param [in] fpscr Floating Point Status/Control value to set
vipinranka 12:9a20164dcc47 1039 */
vipinranka 12:9a20164dcc47 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
vipinranka 12:9a20164dcc47 1041 {
vipinranka 12:9a20164dcc47 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
vipinranka 12:9a20164dcc47 1043 #if 1
vipinranka 12:9a20164dcc47 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
vipinranka 12:9a20164dcc47 1045 #else
vipinranka 12:9a20164dcc47 1046 register uint32_t __regfpscr __ASM("fpscr");
vipinranka 12:9a20164dcc47 1047 __regfpscr = (fpscr);
vipinranka 12:9a20164dcc47 1048 #endif
vipinranka 12:9a20164dcc47 1049 #endif
vipinranka 12:9a20164dcc47 1050 }
vipinranka 12:9a20164dcc47 1051
vipinranka 12:9a20164dcc47 1052 /** \brief Get FPEXC
vipinranka 12:9a20164dcc47 1053
vipinranka 12:9a20164dcc47 1054 This function returns the current value of the Floating Point Exception Control register.
vipinranka 12:9a20164dcc47 1055
vipinranka 12:9a20164dcc47 1056 \return Floating Point Exception Control register value
vipinranka 12:9a20164dcc47 1057 */
vipinranka 12:9a20164dcc47 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
vipinranka 12:9a20164dcc47 1059 {
vipinranka 12:9a20164dcc47 1060 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 1061 #if 1
vipinranka 12:9a20164dcc47 1062 uint32_t result;
vipinranka 12:9a20164dcc47 1063
vipinranka 12:9a20164dcc47 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
vipinranka 12:9a20164dcc47 1065 return (result);
vipinranka 12:9a20164dcc47 1066 #else
vipinranka 12:9a20164dcc47 1067 register uint32_t __regfpexc __ASM("fpexc");
vipinranka 12:9a20164dcc47 1068 return(__regfpexc);
vipinranka 12:9a20164dcc47 1069 #endif
vipinranka 12:9a20164dcc47 1070 #else
vipinranka 12:9a20164dcc47 1071 return(0);
vipinranka 12:9a20164dcc47 1072 #endif
vipinranka 12:9a20164dcc47 1073 }
vipinranka 12:9a20164dcc47 1074
vipinranka 12:9a20164dcc47 1075
vipinranka 12:9a20164dcc47 1076 /** \brief Set FPEXC
vipinranka 12:9a20164dcc47 1077
vipinranka 12:9a20164dcc47 1078 This function assigns the given value to the Floating Point Exception Control register.
vipinranka 12:9a20164dcc47 1079
vipinranka 12:9a20164dcc47 1080 \param [in] fpscr Floating Point Exception Control value to set
vipinranka 12:9a20164dcc47 1081 */
vipinranka 12:9a20164dcc47 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
vipinranka 12:9a20164dcc47 1083 {
vipinranka 12:9a20164dcc47 1084 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 1085 #if 1
vipinranka 12:9a20164dcc47 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
vipinranka 12:9a20164dcc47 1087 #else
vipinranka 12:9a20164dcc47 1088 register uint32_t __regfpexc __ASM("fpexc");
vipinranka 12:9a20164dcc47 1089 __regfpexc = (fpexc);
vipinranka 12:9a20164dcc47 1090 #endif
vipinranka 12:9a20164dcc47 1091 #endif
vipinranka 12:9a20164dcc47 1092 }
vipinranka 12:9a20164dcc47 1093
vipinranka 12:9a20164dcc47 1094 /** \brief Get CPACR
vipinranka 12:9a20164dcc47 1095
vipinranka 12:9a20164dcc47 1096 This function returns the current value of the Coprocessor Access Control register.
vipinranka 12:9a20164dcc47 1097
vipinranka 12:9a20164dcc47 1098 \return Coprocessor Access Control register value
vipinranka 12:9a20164dcc47 1099 */
vipinranka 12:9a20164dcc47 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
vipinranka 12:9a20164dcc47 1101 {
vipinranka 12:9a20164dcc47 1102 #if 1
vipinranka 12:9a20164dcc47 1103 register uint32_t __regCPACR;
vipinranka 12:9a20164dcc47 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
vipinranka 12:9a20164dcc47 1105 #else
vipinranka 12:9a20164dcc47 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
vipinranka 12:9a20164dcc47 1107 #endif
vipinranka 12:9a20164dcc47 1108 return __regCPACR;
vipinranka 12:9a20164dcc47 1109 }
vipinranka 12:9a20164dcc47 1110
vipinranka 12:9a20164dcc47 1111 /** \brief Set CPACR
vipinranka 12:9a20164dcc47 1112
vipinranka 12:9a20164dcc47 1113 This function assigns the given value to the Coprocessor Access Control register.
vipinranka 12:9a20164dcc47 1114
vipinranka 12:9a20164dcc47 1115 \param [in] cpacr Coprocessor Acccess Control value to set
vipinranka 12:9a20164dcc47 1116 */
vipinranka 12:9a20164dcc47 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
vipinranka 12:9a20164dcc47 1118 {
vipinranka 12:9a20164dcc47 1119 #if 1
vipinranka 12:9a20164dcc47 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
vipinranka 12:9a20164dcc47 1121 #else
vipinranka 12:9a20164dcc47 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
vipinranka 12:9a20164dcc47 1123 __regCPACR = cpacr;
vipinranka 12:9a20164dcc47 1124 #endif
vipinranka 12:9a20164dcc47 1125 __ISB();
vipinranka 12:9a20164dcc47 1126 }
vipinranka 12:9a20164dcc47 1127
vipinranka 12:9a20164dcc47 1128 /** \brief Get CBAR
vipinranka 12:9a20164dcc47 1129
vipinranka 12:9a20164dcc47 1130 This function returns the value of the Configuration Base Address register.
vipinranka 12:9a20164dcc47 1131
vipinranka 12:9a20164dcc47 1132 \return Configuration Base Address register value
vipinranka 12:9a20164dcc47 1133 */
vipinranka 12:9a20164dcc47 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
vipinranka 12:9a20164dcc47 1135 #if 1
vipinranka 12:9a20164dcc47 1136 register uint32_t __regCBAR;
vipinranka 12:9a20164dcc47 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
vipinranka 12:9a20164dcc47 1138 #else
vipinranka 12:9a20164dcc47 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
vipinranka 12:9a20164dcc47 1140 #endif
vipinranka 12:9a20164dcc47 1141 return(__regCBAR);
vipinranka 12:9a20164dcc47 1142 }
vipinranka 12:9a20164dcc47 1143
vipinranka 12:9a20164dcc47 1144 /** \brief Get TTBR0
vipinranka 12:9a20164dcc47 1145
vipinranka 12:9a20164dcc47 1146 This function returns the value of the Translation Table Base Register 0.
vipinranka 12:9a20164dcc47 1147
vipinranka 12:9a20164dcc47 1148 \return Translation Table Base Register 0 value
vipinranka 12:9a20164dcc47 1149 */
vipinranka 12:9a20164dcc47 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
vipinranka 12:9a20164dcc47 1151 #if 1
vipinranka 12:9a20164dcc47 1152 register uint32_t __regTTBR0;
vipinranka 12:9a20164dcc47 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
vipinranka 12:9a20164dcc47 1154 #else
vipinranka 12:9a20164dcc47 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
vipinranka 12:9a20164dcc47 1156 #endif
vipinranka 12:9a20164dcc47 1157 return(__regTTBR0);
vipinranka 12:9a20164dcc47 1158 }
vipinranka 12:9a20164dcc47 1159
vipinranka 12:9a20164dcc47 1160 /** \brief Set TTBR0
vipinranka 12:9a20164dcc47 1161
vipinranka 12:9a20164dcc47 1162 This function assigns the given value to the Translation Table Base Register 0.
vipinranka 12:9a20164dcc47 1163
vipinranka 12:9a20164dcc47 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
vipinranka 12:9a20164dcc47 1165 */
vipinranka 12:9a20164dcc47 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
vipinranka 12:9a20164dcc47 1167 #if 1
vipinranka 12:9a20164dcc47 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
vipinranka 12:9a20164dcc47 1169 #else
vipinranka 12:9a20164dcc47 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
vipinranka 12:9a20164dcc47 1171 __regTTBR0 = ttbr0;
vipinranka 12:9a20164dcc47 1172 #endif
vipinranka 12:9a20164dcc47 1173 __ISB();
vipinranka 12:9a20164dcc47 1174 }
vipinranka 12:9a20164dcc47 1175
vipinranka 12:9a20164dcc47 1176 /** \brief Get DACR
vipinranka 12:9a20164dcc47 1177
vipinranka 12:9a20164dcc47 1178 This function returns the value of the Domain Access Control Register.
vipinranka 12:9a20164dcc47 1179
vipinranka 12:9a20164dcc47 1180 \return Domain Access Control Register value
vipinranka 12:9a20164dcc47 1181 */
vipinranka 12:9a20164dcc47 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
vipinranka 12:9a20164dcc47 1183 #if 1
vipinranka 12:9a20164dcc47 1184 register uint32_t __regDACR;
vipinranka 12:9a20164dcc47 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
vipinranka 12:9a20164dcc47 1186 #else
vipinranka 12:9a20164dcc47 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
vipinranka 12:9a20164dcc47 1188 #endif
vipinranka 12:9a20164dcc47 1189 return(__regDACR);
vipinranka 12:9a20164dcc47 1190 }
vipinranka 12:9a20164dcc47 1191
vipinranka 12:9a20164dcc47 1192 /** \brief Set DACR
vipinranka 12:9a20164dcc47 1193
vipinranka 12:9a20164dcc47 1194 This function assigns the given value to the Domain Access Control Register.
vipinranka 12:9a20164dcc47 1195
vipinranka 12:9a20164dcc47 1196 \param [in] dacr Domain Access Control Register value to set
vipinranka 12:9a20164dcc47 1197 */
vipinranka 12:9a20164dcc47 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
vipinranka 12:9a20164dcc47 1199 #if 1
vipinranka 12:9a20164dcc47 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
vipinranka 12:9a20164dcc47 1201 #else
vipinranka 12:9a20164dcc47 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
vipinranka 12:9a20164dcc47 1203 __regDACR = dacr;
vipinranka 12:9a20164dcc47 1204 #endif
vipinranka 12:9a20164dcc47 1205 __ISB();
vipinranka 12:9a20164dcc47 1206 }
vipinranka 12:9a20164dcc47 1207
vipinranka 12:9a20164dcc47 1208 /******************************** Cache and BTAC enable ****************************************************/
vipinranka 12:9a20164dcc47 1209
vipinranka 12:9a20164dcc47 1210 /** \brief Set SCTLR
vipinranka 12:9a20164dcc47 1211
vipinranka 12:9a20164dcc47 1212 This function assigns the given value to the System Control Register.
vipinranka 12:9a20164dcc47 1213
vipinranka 12:9a20164dcc47 1214 \param [in] sctlr System Control Register value to set
vipinranka 12:9a20164dcc47 1215 */
vipinranka 12:9a20164dcc47 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
vipinranka 12:9a20164dcc47 1217 {
vipinranka 12:9a20164dcc47 1218 #if 1
vipinranka 12:9a20164dcc47 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
vipinranka 12:9a20164dcc47 1220 #else
vipinranka 12:9a20164dcc47 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
vipinranka 12:9a20164dcc47 1222 __regSCTLR = sctlr;
vipinranka 12:9a20164dcc47 1223 #endif
vipinranka 12:9a20164dcc47 1224 }
vipinranka 12:9a20164dcc47 1225
vipinranka 12:9a20164dcc47 1226 /** \brief Get SCTLR
vipinranka 12:9a20164dcc47 1227
vipinranka 12:9a20164dcc47 1228 This function returns the value of the System Control Register.
vipinranka 12:9a20164dcc47 1229
vipinranka 12:9a20164dcc47 1230 \return System Control Register value
vipinranka 12:9a20164dcc47 1231 */
vipinranka 12:9a20164dcc47 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
vipinranka 12:9a20164dcc47 1233 #if 1
vipinranka 12:9a20164dcc47 1234 register uint32_t __regSCTLR;
vipinranka 12:9a20164dcc47 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
vipinranka 12:9a20164dcc47 1236 #else
vipinranka 12:9a20164dcc47 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
vipinranka 12:9a20164dcc47 1238 #endif
vipinranka 12:9a20164dcc47 1239 return(__regSCTLR);
vipinranka 12:9a20164dcc47 1240 }
vipinranka 12:9a20164dcc47 1241
vipinranka 12:9a20164dcc47 1242 /** \brief Enable Caches
vipinranka 12:9a20164dcc47 1243
vipinranka 12:9a20164dcc47 1244 Enable Caches
vipinranka 12:9a20164dcc47 1245 */
vipinranka 12:9a20164dcc47 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
vipinranka 12:9a20164dcc47 1247 // Set I bit 12 to enable I Cache
vipinranka 12:9a20164dcc47 1248 // Set C bit 2 to enable D Cache
vipinranka 12:9a20164dcc47 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
vipinranka 12:9a20164dcc47 1250 }
vipinranka 12:9a20164dcc47 1251
vipinranka 12:9a20164dcc47 1252 /** \brief Disable Caches
vipinranka 12:9a20164dcc47 1253
vipinranka 12:9a20164dcc47 1254 Disable Caches
vipinranka 12:9a20164dcc47 1255 */
vipinranka 12:9a20164dcc47 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
vipinranka 12:9a20164dcc47 1257 // Clear I bit 12 to disable I Cache
vipinranka 12:9a20164dcc47 1258 // Clear C bit 2 to disable D Cache
vipinranka 12:9a20164dcc47 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
vipinranka 12:9a20164dcc47 1260 __ISB();
vipinranka 12:9a20164dcc47 1261 }
vipinranka 12:9a20164dcc47 1262
vipinranka 12:9a20164dcc47 1263 /** \brief Enable BTAC
vipinranka 12:9a20164dcc47 1264
vipinranka 12:9a20164dcc47 1265 Enable BTAC
vipinranka 12:9a20164dcc47 1266 */
vipinranka 12:9a20164dcc47 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
vipinranka 12:9a20164dcc47 1268 // Set Z bit 11 to enable branch prediction
vipinranka 12:9a20164dcc47 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
vipinranka 12:9a20164dcc47 1270 __ISB();
vipinranka 12:9a20164dcc47 1271 }
vipinranka 12:9a20164dcc47 1272
vipinranka 12:9a20164dcc47 1273 /** \brief Disable BTAC
vipinranka 12:9a20164dcc47 1274
vipinranka 12:9a20164dcc47 1275 Disable BTAC
vipinranka 12:9a20164dcc47 1276 */
vipinranka 12:9a20164dcc47 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
vipinranka 12:9a20164dcc47 1278 // Clear Z bit 11 to disable branch prediction
vipinranka 12:9a20164dcc47 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
vipinranka 12:9a20164dcc47 1280 }
vipinranka 12:9a20164dcc47 1281
vipinranka 12:9a20164dcc47 1282
vipinranka 12:9a20164dcc47 1283 /** \brief Enable MMU
vipinranka 12:9a20164dcc47 1284
vipinranka 12:9a20164dcc47 1285 Enable MMU
vipinranka 12:9a20164dcc47 1286 */
vipinranka 12:9a20164dcc47 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
vipinranka 12:9a20164dcc47 1288 // Set M bit 0 to enable the MMU
vipinranka 12:9a20164dcc47 1289 // Set AFE bit to enable simplified access permissions model
vipinranka 12:9a20164dcc47 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
vipinranka 12:9a20164dcc47 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
vipinranka 12:9a20164dcc47 1292 __ISB();
vipinranka 12:9a20164dcc47 1293 }
vipinranka 12:9a20164dcc47 1294
vipinranka 12:9a20164dcc47 1295 /** \brief Disable MMU
vipinranka 12:9a20164dcc47 1296
vipinranka 12:9a20164dcc47 1297 Disable MMU
vipinranka 12:9a20164dcc47 1298 */
vipinranka 12:9a20164dcc47 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
vipinranka 12:9a20164dcc47 1300 // Clear M bit 0 to disable the MMU
vipinranka 12:9a20164dcc47 1301 __set_SCTLR( __get_SCTLR() & ~1);
vipinranka 12:9a20164dcc47 1302 __ISB();
vipinranka 12:9a20164dcc47 1303 }
vipinranka 12:9a20164dcc47 1304
vipinranka 12:9a20164dcc47 1305 /******************************** TLB maintenance operations ************************************************/
vipinranka 12:9a20164dcc47 1306 /** \brief Invalidate the whole tlb
vipinranka 12:9a20164dcc47 1307
vipinranka 12:9a20164dcc47 1308 TLBIALL. Invalidate the whole tlb
vipinranka 12:9a20164dcc47 1309 */
vipinranka 12:9a20164dcc47 1310
vipinranka 12:9a20164dcc47 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
vipinranka 12:9a20164dcc47 1312 #if 1
vipinranka 12:9a20164dcc47 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
vipinranka 12:9a20164dcc47 1314 #else
vipinranka 12:9a20164dcc47 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
vipinranka 12:9a20164dcc47 1316 __TLBIALL = 0;
vipinranka 12:9a20164dcc47 1317 #endif
vipinranka 12:9a20164dcc47 1318 __DSB();
vipinranka 12:9a20164dcc47 1319 __ISB();
vipinranka 12:9a20164dcc47 1320 }
vipinranka 12:9a20164dcc47 1321
vipinranka 12:9a20164dcc47 1322 /******************************** BTB maintenance operations ************************************************/
vipinranka 12:9a20164dcc47 1323 /** \brief Invalidate entire branch predictor array
vipinranka 12:9a20164dcc47 1324
vipinranka 12:9a20164dcc47 1325 BPIALL. Branch Predictor Invalidate All.
vipinranka 12:9a20164dcc47 1326 */
vipinranka 12:9a20164dcc47 1327
vipinranka 12:9a20164dcc47 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
vipinranka 12:9a20164dcc47 1329 #if 1
vipinranka 12:9a20164dcc47 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
vipinranka 12:9a20164dcc47 1331 #else
vipinranka 12:9a20164dcc47 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
vipinranka 12:9a20164dcc47 1333 __BPIALL = 0;
vipinranka 12:9a20164dcc47 1334 #endif
vipinranka 12:9a20164dcc47 1335 __DSB(); //ensure completion of the invalidation
vipinranka 12:9a20164dcc47 1336 __ISB(); //ensure instruction fetch path sees new state
vipinranka 12:9a20164dcc47 1337 }
vipinranka 12:9a20164dcc47 1338
vipinranka 12:9a20164dcc47 1339
vipinranka 12:9a20164dcc47 1340 /******************************** L1 cache operations ******************************************************/
vipinranka 12:9a20164dcc47 1341
vipinranka 12:9a20164dcc47 1342 /** \brief Invalidate the whole I$
vipinranka 12:9a20164dcc47 1343
vipinranka 12:9a20164dcc47 1344 ICIALLU. Instruction Cache Invalidate All to PoU
vipinranka 12:9a20164dcc47 1345 */
vipinranka 12:9a20164dcc47 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
vipinranka 12:9a20164dcc47 1347 #if 1
vipinranka 12:9a20164dcc47 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
vipinranka 12:9a20164dcc47 1349 #else
vipinranka 12:9a20164dcc47 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
vipinranka 12:9a20164dcc47 1351 __ICIALLU = 0;
vipinranka 12:9a20164dcc47 1352 #endif
vipinranka 12:9a20164dcc47 1353 __DSB(); //ensure completion of the invalidation
vipinranka 12:9a20164dcc47 1354 __ISB(); //ensure instruction fetch path sees new I cache state
vipinranka 12:9a20164dcc47 1355 }
vipinranka 12:9a20164dcc47 1356
vipinranka 12:9a20164dcc47 1357 /** \brief Clean D$ by MVA
vipinranka 12:9a20164dcc47 1358
vipinranka 12:9a20164dcc47 1359 DCCMVAC. Data cache clean by MVA to PoC
vipinranka 12:9a20164dcc47 1360 */
vipinranka 12:9a20164dcc47 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
vipinranka 12:9a20164dcc47 1362 #if 1
vipinranka 12:9a20164dcc47 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
vipinranka 12:9a20164dcc47 1364 #else
vipinranka 12:9a20164dcc47 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
vipinranka 12:9a20164dcc47 1366 __DCCMVAC = (uint32_t)va;
vipinranka 12:9a20164dcc47 1367 #endif
vipinranka 12:9a20164dcc47 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vipinranka 12:9a20164dcc47 1369 }
vipinranka 12:9a20164dcc47 1370
vipinranka 12:9a20164dcc47 1371 /** \brief Invalidate D$ by MVA
vipinranka 12:9a20164dcc47 1372
vipinranka 12:9a20164dcc47 1373 DCIMVAC. Data cache invalidate by MVA to PoC
vipinranka 12:9a20164dcc47 1374 */
vipinranka 12:9a20164dcc47 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
vipinranka 12:9a20164dcc47 1376 #if 1
vipinranka 12:9a20164dcc47 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
vipinranka 12:9a20164dcc47 1378 #else
vipinranka 12:9a20164dcc47 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
vipinranka 12:9a20164dcc47 1380 __DCIMVAC = (uint32_t)va;
vipinranka 12:9a20164dcc47 1381 #endif
vipinranka 12:9a20164dcc47 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vipinranka 12:9a20164dcc47 1383 }
vipinranka 12:9a20164dcc47 1384
vipinranka 12:9a20164dcc47 1385 /** \brief Clean and Invalidate D$ by MVA
vipinranka 12:9a20164dcc47 1386
vipinranka 12:9a20164dcc47 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
vipinranka 12:9a20164dcc47 1388 */
vipinranka 12:9a20164dcc47 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
vipinranka 12:9a20164dcc47 1390 #if 1
vipinranka 12:9a20164dcc47 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
vipinranka 12:9a20164dcc47 1392 #else
vipinranka 12:9a20164dcc47 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
vipinranka 12:9a20164dcc47 1394 __DCCIMVAC = (uint32_t)va;
vipinranka 12:9a20164dcc47 1395 #endif
vipinranka 12:9a20164dcc47 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
vipinranka 12:9a20164dcc47 1397 }
vipinranka 12:9a20164dcc47 1398
vipinranka 12:9a20164dcc47 1399 /** \brief Clean and Invalidate the entire data or unified cache
vipinranka 12:9a20164dcc47 1400
vipinranka 12:9a20164dcc47 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
vipinranka 12:9a20164dcc47 1402 */
vipinranka 12:9a20164dcc47 1403 extern void __v7_all_cache(uint32_t op);
vipinranka 12:9a20164dcc47 1404
vipinranka 12:9a20164dcc47 1405
vipinranka 12:9a20164dcc47 1406 /** \brief Invalidate the whole D$
vipinranka 12:9a20164dcc47 1407
vipinranka 12:9a20164dcc47 1408 DCISW. Invalidate by Set/Way
vipinranka 12:9a20164dcc47 1409 */
vipinranka 12:9a20164dcc47 1410
vipinranka 12:9a20164dcc47 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
vipinranka 12:9a20164dcc47 1412 __v7_all_cache(0);
vipinranka 12:9a20164dcc47 1413 }
vipinranka 12:9a20164dcc47 1414
vipinranka 12:9a20164dcc47 1415 /** \brief Clean the whole D$
vipinranka 12:9a20164dcc47 1416
vipinranka 12:9a20164dcc47 1417 DCCSW. Clean by Set/Way
vipinranka 12:9a20164dcc47 1418 */
vipinranka 12:9a20164dcc47 1419
vipinranka 12:9a20164dcc47 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
vipinranka 12:9a20164dcc47 1421 __v7_all_cache(1);
vipinranka 12:9a20164dcc47 1422 }
vipinranka 12:9a20164dcc47 1423
vipinranka 12:9a20164dcc47 1424 /** \brief Clean and invalidate the whole D$
vipinranka 12:9a20164dcc47 1425
vipinranka 12:9a20164dcc47 1426 DCCISW. Clean and Invalidate by Set/Way
vipinranka 12:9a20164dcc47 1427 */
vipinranka 12:9a20164dcc47 1428
vipinranka 12:9a20164dcc47 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
vipinranka 12:9a20164dcc47 1430 __v7_all_cache(2);
vipinranka 12:9a20164dcc47 1431 }
vipinranka 12:9a20164dcc47 1432
vipinranka 12:9a20164dcc47 1433 #include "core_ca_mmu.h"
vipinranka 12:9a20164dcc47 1434
vipinranka 12:9a20164dcc47 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
vipinranka 12:9a20164dcc47 1436
vipinranka 12:9a20164dcc47 1437 #error TASKING Compiler support not implemented for Cortex-A
vipinranka 12:9a20164dcc47 1438
vipinranka 12:9a20164dcc47 1439 #endif
vipinranka 12:9a20164dcc47 1440
vipinranka 12:9a20164dcc47 1441 /*@} end of CMSIS_Core_RegAccFunctions */
vipinranka 12:9a20164dcc47 1442
vipinranka 12:9a20164dcc47 1443
vipinranka 12:9a20164dcc47 1444 #endif /* __CORE_CAFUNC_H__ */