Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

mbed-dev/cmsis/core_ca9.h@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /**************************************************************************//**
vipinranka 12:9a20164dcc47 2 * @file core_ca9.h
vipinranka 12:9a20164dcc47 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
vipinranka 12:9a20164dcc47 4 * @version
vipinranka 12:9a20164dcc47 5 * @date 25 March 2013
vipinranka 12:9a20164dcc47 6 *
vipinranka 12:9a20164dcc47 7 * @note
vipinranka 12:9a20164dcc47 8 *
vipinranka 12:9a20164dcc47 9 ******************************************************************************/
vipinranka 12:9a20164dcc47 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
vipinranka 12:9a20164dcc47 11
vipinranka 12:9a20164dcc47 12 All rights reserved.
vipinranka 12:9a20164dcc47 13 Redistribution and use in source and binary forms, with or without
vipinranka 12:9a20164dcc47 14 modification, are permitted provided that the following conditions are met:
vipinranka 12:9a20164dcc47 15 - Redistributions of source code must retain the above copyright
vipinranka 12:9a20164dcc47 16 notice, this list of conditions and the following disclaimer.
vipinranka 12:9a20164dcc47 17 - Redistributions in binary form must reproduce the above copyright
vipinranka 12:9a20164dcc47 18 notice, this list of conditions and the following disclaimer in the
vipinranka 12:9a20164dcc47 19 documentation and/or other materials provided with the distribution.
vipinranka 12:9a20164dcc47 20 - Neither the name of ARM nor the names of its contributors may be used
vipinranka 12:9a20164dcc47 21 to endorse or promote products derived from this software without
vipinranka 12:9a20164dcc47 22 specific prior written permission.
vipinranka 12:9a20164dcc47 23 *
vipinranka 12:9a20164dcc47 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vipinranka 12:9a20164dcc47 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vipinranka 12:9a20164dcc47 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
vipinranka 12:9a20164dcc47 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
vipinranka 12:9a20164dcc47 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
vipinranka 12:9a20164dcc47 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
vipinranka 12:9a20164dcc47 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
vipinranka 12:9a20164dcc47 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
vipinranka 12:9a20164dcc47 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
vipinranka 12:9a20164dcc47 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
vipinranka 12:9a20164dcc47 34 POSSIBILITY OF SUCH DAMAGE.
vipinranka 12:9a20164dcc47 35 ---------------------------------------------------------------------------*/
vipinranka 12:9a20164dcc47 36
vipinranka 12:9a20164dcc47 37
vipinranka 12:9a20164dcc47 38 #if defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 39 #pragma system_include /* treat file as system include file for MISRA check */
vipinranka 12:9a20164dcc47 40 #endif
vipinranka 12:9a20164dcc47 41
vipinranka 12:9a20164dcc47 42 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 43 extern "C" {
vipinranka 12:9a20164dcc47 44 #endif
vipinranka 12:9a20164dcc47 45
vipinranka 12:9a20164dcc47 46 #ifndef __CORE_CA9_H_GENERIC
vipinranka 12:9a20164dcc47 47 #define __CORE_CA9_H_GENERIC
vipinranka 12:9a20164dcc47 48
vipinranka 12:9a20164dcc47 49
vipinranka 12:9a20164dcc47 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
vipinranka 12:9a20164dcc47 51 CMSIS violates the following MISRA-C:2004 rules:
vipinranka 12:9a20164dcc47 52
vipinranka 12:9a20164dcc47 53 \li Required Rule 8.5, object/function definition in header file.<br>
vipinranka 12:9a20164dcc47 54 Function definitions in header files are used to allow 'inlining'.
vipinranka 12:9a20164dcc47 55
vipinranka 12:9a20164dcc47 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
vipinranka 12:9a20164dcc47 57 Unions are used for effective representation of core registers.
vipinranka 12:9a20164dcc47 58
vipinranka 12:9a20164dcc47 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
vipinranka 12:9a20164dcc47 60 Function-like macros are used to allow more efficient code.
vipinranka 12:9a20164dcc47 61 */
vipinranka 12:9a20164dcc47 62
vipinranka 12:9a20164dcc47 63
vipinranka 12:9a20164dcc47 64 /*******************************************************************************
vipinranka 12:9a20164dcc47 65 * CMSIS definitions
vipinranka 12:9a20164dcc47 66 ******************************************************************************/
vipinranka 12:9a20164dcc47 67 /** \ingroup Cortex_A9
vipinranka 12:9a20164dcc47 68 @{
vipinranka 12:9a20164dcc47 69 */
vipinranka 12:9a20164dcc47 70
vipinranka 12:9a20164dcc47 71 /* CMSIS CA9 definitions */
vipinranka 12:9a20164dcc47 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
vipinranka 12:9a20164dcc47 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
vipinranka 12:9a20164dcc47 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
vipinranka 12:9a20164dcc47 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
vipinranka 12:9a20164dcc47 76
vipinranka 12:9a20164dcc47 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
vipinranka 12:9a20164dcc47 78
vipinranka 12:9a20164dcc47 79
vipinranka 12:9a20164dcc47 80 #if defined ( __CC_ARM )
vipinranka 12:9a20164dcc47 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
vipinranka 12:9a20164dcc47 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
vipinranka 12:9a20164dcc47 83 #define __STATIC_INLINE static __inline
vipinranka 12:9a20164dcc47 84 #define __STATIC_ASM static __asm
vipinranka 12:9a20164dcc47 85
vipinranka 12:9a20164dcc47 86 #elif defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
vipinranka 12:9a20164dcc47 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
vipinranka 12:9a20164dcc47 89 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 90 #define __STATIC_ASM static __asm
vipinranka 12:9a20164dcc47 91
vipinranka 12:9a20164dcc47 92 #include <stdint.h>
vipinranka 12:9a20164dcc47 93 inline uint32_t __get_PSR(void) {
vipinranka 12:9a20164dcc47 94 __ASM("mrs r0, cpsr");
vipinranka 12:9a20164dcc47 95 }
vipinranka 12:9a20164dcc47 96
vipinranka 12:9a20164dcc47 97 #elif defined ( __TMS470__ )
vipinranka 12:9a20164dcc47 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
vipinranka 12:9a20164dcc47 99 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 100 #define __STATIC_ASM static __asm
vipinranka 12:9a20164dcc47 101
vipinranka 12:9a20164dcc47 102 #elif defined ( __GNUC__ )
vipinranka 12:9a20164dcc47 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
vipinranka 12:9a20164dcc47 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
vipinranka 12:9a20164dcc47 105 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 106 #define __STATIC_ASM static __asm
vipinranka 12:9a20164dcc47 107
vipinranka 12:9a20164dcc47 108 #elif defined ( __TASKING__ )
vipinranka 12:9a20164dcc47 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
vipinranka 12:9a20164dcc47 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
vipinranka 12:9a20164dcc47 111 #define __STATIC_INLINE static inline
vipinranka 12:9a20164dcc47 112 #define __STATIC_ASM static __asm
vipinranka 12:9a20164dcc47 113
vipinranka 12:9a20164dcc47 114 #endif
vipinranka 12:9a20164dcc47 115
vipinranka 12:9a20164dcc47 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
vipinranka 12:9a20164dcc47 117 */
vipinranka 12:9a20164dcc47 118 #if defined ( __CC_ARM )
vipinranka 12:9a20164dcc47 119 #if defined __TARGET_FPU_VFP
vipinranka 12:9a20164dcc47 120 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 121 #define __FPU_USED 1
vipinranka 12:9a20164dcc47 122 #else
vipinranka 12:9a20164dcc47 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 124 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 125 #endif
vipinranka 12:9a20164dcc47 126 #else
vipinranka 12:9a20164dcc47 127 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 128 #endif
vipinranka 12:9a20164dcc47 129
vipinranka 12:9a20164dcc47 130 #elif defined ( __ICCARM__ )
vipinranka 12:9a20164dcc47 131 #if defined __ARMVFP__
vipinranka 12:9a20164dcc47 132 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 133 #define __FPU_USED 1
vipinranka 12:9a20164dcc47 134 #else
vipinranka 12:9a20164dcc47 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 136 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 137 #endif
vipinranka 12:9a20164dcc47 138 #else
vipinranka 12:9a20164dcc47 139 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 140 #endif
vipinranka 12:9a20164dcc47 141
vipinranka 12:9a20164dcc47 142 #elif defined ( __TMS470__ )
vipinranka 12:9a20164dcc47 143 #if defined __TI_VFP_SUPPORT__
vipinranka 12:9a20164dcc47 144 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 145 #define __FPU_USED 1
vipinranka 12:9a20164dcc47 146 #else
vipinranka 12:9a20164dcc47 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 148 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 149 #endif
vipinranka 12:9a20164dcc47 150 #else
vipinranka 12:9a20164dcc47 151 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 152 #endif
vipinranka 12:9a20164dcc47 153
vipinranka 12:9a20164dcc47 154 #elif defined ( __GNUC__ )
vipinranka 12:9a20164dcc47 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
vipinranka 12:9a20164dcc47 156 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 157 #define __FPU_USED 1
vipinranka 12:9a20164dcc47 158 #else
vipinranka 12:9a20164dcc47 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 160 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 161 #endif
vipinranka 12:9a20164dcc47 162 #else
vipinranka 12:9a20164dcc47 163 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 164 #endif
vipinranka 12:9a20164dcc47 165
vipinranka 12:9a20164dcc47 166 #elif defined ( __TASKING__ )
vipinranka 12:9a20164dcc47 167 #if defined __FPU_VFP__
vipinranka 12:9a20164dcc47 168 #if (__FPU_PRESENT == 1)
vipinranka 12:9a20164dcc47 169 #define __FPU_USED 1
vipinranka 12:9a20164dcc47 170 #else
vipinranka 12:9a20164dcc47 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
vipinranka 12:9a20164dcc47 172 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 173 #endif
vipinranka 12:9a20164dcc47 174 #else
vipinranka 12:9a20164dcc47 175 #define __FPU_USED 0
vipinranka 12:9a20164dcc47 176 #endif
vipinranka 12:9a20164dcc47 177 #endif
vipinranka 12:9a20164dcc47 178
vipinranka 12:9a20164dcc47 179 #include <stdint.h> /*!< standard types definitions */
vipinranka 12:9a20164dcc47 180 #include "core_caInstr.h" /*!< Core Instruction Access */
vipinranka 12:9a20164dcc47 181 #include "core_caFunc.h" /*!< Core Function Access */
vipinranka 12:9a20164dcc47 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
vipinranka 12:9a20164dcc47 183
vipinranka 12:9a20164dcc47 184 #endif /* __CORE_CA9_H_GENERIC */
vipinranka 12:9a20164dcc47 185
vipinranka 12:9a20164dcc47 186 #ifndef __CMSIS_GENERIC
vipinranka 12:9a20164dcc47 187
vipinranka 12:9a20164dcc47 188 #ifndef __CORE_CA9_H_DEPENDANT
vipinranka 12:9a20164dcc47 189 #define __CORE_CA9_H_DEPENDANT
vipinranka 12:9a20164dcc47 190
vipinranka 12:9a20164dcc47 191 /* check device defines and use defaults */
vipinranka 12:9a20164dcc47 192 #if defined __CHECK_DEVICE_DEFINES
vipinranka 12:9a20164dcc47 193 #ifndef __CA9_REV
vipinranka 12:9a20164dcc47 194 #define __CA9_REV 0x0000
vipinranka 12:9a20164dcc47 195 #warning "__CA9_REV not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 196 #endif
vipinranka 12:9a20164dcc47 197
vipinranka 12:9a20164dcc47 198 #ifndef __FPU_PRESENT
vipinranka 12:9a20164dcc47 199 #define __FPU_PRESENT 1
vipinranka 12:9a20164dcc47 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
vipinranka 12:9a20164dcc47 201 #endif
vipinranka 12:9a20164dcc47 202
vipinranka 12:9a20164dcc47 203 #ifndef __Vendor_SysTickConfig
vipinranka 12:9a20164dcc47 204 #define __Vendor_SysTickConfig 1
vipinranka 12:9a20164dcc47 205 #endif
vipinranka 12:9a20164dcc47 206
vipinranka 12:9a20164dcc47 207 #if __Vendor_SysTickConfig == 0
vipinranka 12:9a20164dcc47 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
vipinranka 12:9a20164dcc47 209 #endif
vipinranka 12:9a20164dcc47 210 #endif
vipinranka 12:9a20164dcc47 211
vipinranka 12:9a20164dcc47 212 /* IO definitions (access restrictions to peripheral registers) */
vipinranka 12:9a20164dcc47 213 /**
vipinranka 12:9a20164dcc47 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
vipinranka 12:9a20164dcc47 215
vipinranka 12:9a20164dcc47 216 <strong>IO Type Qualifiers</strong> are used
vipinranka 12:9a20164dcc47 217 \li to specify the access to peripheral variables.
vipinranka 12:9a20164dcc47 218 \li for automatic generation of peripheral register debug information.
vipinranka 12:9a20164dcc47 219 */
vipinranka 12:9a20164dcc47 220 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 221 #define __I volatile /*!< Defines 'read only' permissions */
vipinranka 12:9a20164dcc47 222 #else
vipinranka 12:9a20164dcc47 223 #define __I volatile const /*!< Defines 'read only' permissions */
vipinranka 12:9a20164dcc47 224 #endif
vipinranka 12:9a20164dcc47 225 #define __O volatile /*!< Defines 'write only' permissions */
vipinranka 12:9a20164dcc47 226 #define __IO volatile /*!< Defines 'read / write' permissions */
vipinranka 12:9a20164dcc47 227
vipinranka 12:9a20164dcc47 228 /*@} end of group Cortex_A9 */
vipinranka 12:9a20164dcc47 229
vipinranka 12:9a20164dcc47 230
vipinranka 12:9a20164dcc47 231 /*******************************************************************************
vipinranka 12:9a20164dcc47 232 * Register Abstraction
vipinranka 12:9a20164dcc47 233 ******************************************************************************/
vipinranka 12:9a20164dcc47 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
vipinranka 12:9a20164dcc47 235 \brief Type definitions and defines for Cortex-A processor based devices.
vipinranka 12:9a20164dcc47 236 */
vipinranka 12:9a20164dcc47 237
vipinranka 12:9a20164dcc47 238 /** \ingroup CMSIS_core_register
vipinranka 12:9a20164dcc47 239 \defgroup CMSIS_CORE Status and Control Registers
vipinranka 12:9a20164dcc47 240 \brief Core Register type definitions.
vipinranka 12:9a20164dcc47 241 @{
vipinranka 12:9a20164dcc47 242 */
vipinranka 12:9a20164dcc47 243
vipinranka 12:9a20164dcc47 244 /** \brief Union type to access the Application Program Status Register (APSR).
vipinranka 12:9a20164dcc47 245 */
vipinranka 12:9a20164dcc47 246 typedef union
vipinranka 12:9a20164dcc47 247 {
vipinranka 12:9a20164dcc47 248 struct
vipinranka 12:9a20164dcc47 249 {
vipinranka 12:9a20164dcc47 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
vipinranka 12:9a20164dcc47 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
vipinranka 12:9a20164dcc47 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
vipinranka 12:9a20164dcc47 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
vipinranka 12:9a20164dcc47 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
vipinranka 12:9a20164dcc47 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
vipinranka 12:9a20164dcc47 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
vipinranka 12:9a20164dcc47 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
vipinranka 12:9a20164dcc47 258 } b; /*!< Structure used for bit access */
vipinranka 12:9a20164dcc47 259 uint32_t w; /*!< Type used for word access */
vipinranka 12:9a20164dcc47 260 } APSR_Type;
vipinranka 12:9a20164dcc47 261
vipinranka 12:9a20164dcc47 262
vipinranka 12:9a20164dcc47 263 /*@} end of group CMSIS_CORE */
vipinranka 12:9a20164dcc47 264
vipinranka 12:9a20164dcc47 265 /*@} end of CMSIS_Core_FPUFunctions */
vipinranka 12:9a20164dcc47 266
vipinranka 12:9a20164dcc47 267
vipinranka 12:9a20164dcc47 268 #endif /* __CORE_CA9_H_GENERIC */
vipinranka 12:9a20164dcc47 269
vipinranka 12:9a20164dcc47 270 #endif /* __CMSIS_GENERIC */
vipinranka 12:9a20164dcc47 271
vipinranka 12:9a20164dcc47 272 #ifdef __cplusplus
vipinranka 12:9a20164dcc47 273 }
vipinranka 12:9a20164dcc47 274
vipinranka 12:9a20164dcc47 275
vipinranka 12:9a20164dcc47 276 #endif