This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest
Dependencies: GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem
Fork of mbed-os-example-mbed5-blinky by
UniGraphic/Inits/ILI932x.cpp@12:9a20164dcc47, 2017-01-11 (annotated)
- Committer:
- vipinranka
- Date:
- Wed Jan 11 11:41:30 2017 +0000
- Revision:
- 12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
vipinranka | 12:9a20164dcc47 | 1 | /* mbed UniGraphic library - Device specific class |
vipinranka | 12:9a20164dcc47 | 2 | * Copyright (c) 2015 Giuliano Dianda |
vipinranka | 12:9a20164dcc47 | 3 | * Released under the MIT License: http://mbed.org/license/mit |
vipinranka | 12:9a20164dcc47 | 4 | */ |
vipinranka | 12:9a20164dcc47 | 5 | |
vipinranka | 12:9a20164dcc47 | 6 | #include "Protocols.h" |
vipinranka | 12:9a20164dcc47 | 7 | #include "ILI932x.h" |
vipinranka | 12:9a20164dcc47 | 8 | |
vipinranka | 12:9a20164dcc47 | 9 | ////////////////////////////////////////////////////////////////////////////////// |
vipinranka | 12:9a20164dcc47 | 10 | // display settings /////////////////////////////////////////////////////// |
vipinranka | 12:9a20164dcc47 | 11 | ///////////////////////////////////////////////////////////////////////// |
vipinranka | 12:9a20164dcc47 | 12 | |
vipinranka | 12:9a20164dcc47 | 13 | |
vipinranka | 12:9a20164dcc47 | 14 | ILI932x::ILI932x(proto_t displayproto, PortName port, PinName CS, PinName reset, PinName DC, PinName WR, PinName RD, const char *name , unsigned int LCDSIZE_X, unsigned int LCDSIZE_Y) |
vipinranka | 12:9a20164dcc47 | 15 | : TFT932x(displayproto, port, CS, reset, DC, WR, RD, LCDSIZE_X, LCDSIZE_Y, name) |
vipinranka | 12:9a20164dcc47 | 16 | { |
vipinranka | 12:9a20164dcc47 | 17 | hw_reset(); |
vipinranka | 12:9a20164dcc47 | 18 | BusEnable(true); //set CS low, will stay low untill manually set high with BusEnable(false); |
vipinranka | 12:9a20164dcc47 | 19 | identify(); // will collect tftID |
vipinranka | 12:9a20164dcc47 | 20 | if(tftID==0x9325) init9325(); |
vipinranka | 12:9a20164dcc47 | 21 | else if(tftID==0x9320) init9320(); |
vipinranka | 12:9a20164dcc47 | 22 | auto_gram_read_format();// try to get read gram pixel format, could be 16bit or 18bit, RGB or BGR. Will set flags accordingly |
vipinranka | 12:9a20164dcc47 | 23 | set_orientation(0); |
vipinranka | 12:9a20164dcc47 | 24 | FastWindow(true); // most but not all controllers support this, even if datasheet tells they should. |
vipinranka | 12:9a20164dcc47 | 25 | cls(); |
vipinranka | 12:9a20164dcc47 | 26 | locate(0,0); |
vipinranka | 12:9a20164dcc47 | 27 | } |
vipinranka | 12:9a20164dcc47 | 28 | ILI932x::ILI932x(proto_t displayproto, PinName* buspins, PinName CS, PinName reset, PinName DC, PinName WR, PinName RD, const char *name , unsigned int LCDSIZE_X, unsigned int LCDSIZE_Y) |
vipinranka | 12:9a20164dcc47 | 29 | : TFT932x(displayproto, buspins, CS, reset, DC, WR, RD, LCDSIZE_X, LCDSIZE_Y, name) |
vipinranka | 12:9a20164dcc47 | 30 | { |
vipinranka | 12:9a20164dcc47 | 31 | hw_reset(); |
vipinranka | 12:9a20164dcc47 | 32 | BusEnable(true); //set CS low, will stay low untill manually set high with BusEnable(false); |
vipinranka | 12:9a20164dcc47 | 33 | identify(); // will collect tftID |
vipinranka | 12:9a20164dcc47 | 34 | if(tftID==0x9325) init9325(); |
vipinranka | 12:9a20164dcc47 | 35 | else if(tftID==0x9320) init9320(); |
vipinranka | 12:9a20164dcc47 | 36 | auto_gram_read_format();// try to get read gram pixel format, could be 16bit or 18bit, RGB or BGR. Will set flags accordingly |
vipinranka | 12:9a20164dcc47 | 37 | set_orientation(0); |
vipinranka | 12:9a20164dcc47 | 38 | FastWindow(true); // most but not all controllers support this, even if datasheet tells they should. |
vipinranka | 12:9a20164dcc47 | 39 | cls(); |
vipinranka | 12:9a20164dcc47 | 40 | locate(0,0); |
vipinranka | 12:9a20164dcc47 | 41 | } |
vipinranka | 12:9a20164dcc47 | 42 | ILI932x::ILI932x(proto_t displayproto, int Hz, PinName mosi, PinName miso, PinName sclk, PinName CS, PinName reset, const char *name, unsigned int LCDSIZE_X, unsigned int LCDSIZE_Y) |
vipinranka | 12:9a20164dcc47 | 43 | : TFT932x(displayproto, Hz, mosi, miso, sclk, CS, reset, LCDSIZE_X, LCDSIZE_Y, name) |
vipinranka | 12:9a20164dcc47 | 44 | { |
vipinranka | 12:9a20164dcc47 | 45 | hw_reset(); //TFT class forwards to Protocol class |
vipinranka | 12:9a20164dcc47 | 46 | BusEnable(true); //set CS low, TFT932x class will toggle CS every transfer |
vipinranka | 12:9a20164dcc47 | 47 | identify(); // will collect tftID |
vipinranka | 12:9a20164dcc47 | 48 | if(tftID==0x9325) init9325(); |
vipinranka | 12:9a20164dcc47 | 49 | else if(tftID==0x9320) init9320(); |
vipinranka | 12:9a20164dcc47 | 50 | auto_gram_read_format();// try to get read gram pixel format, could be 16bit or 18bit, RGB or BGR. Will set flags accordingly |
vipinranka | 12:9a20164dcc47 | 51 | set_orientation(0); |
vipinranka | 12:9a20164dcc47 | 52 | FastWindow(true); // most but not all controllers support this, even if datasheet tells they should. |
vipinranka | 12:9a20164dcc47 | 53 | cls(); |
vipinranka | 12:9a20164dcc47 | 54 | locate(0,0); |
vipinranka | 12:9a20164dcc47 | 55 | } |
vipinranka | 12:9a20164dcc47 | 56 | // reset and init the lcd controller |
vipinranka | 12:9a20164dcc47 | 57 | |
vipinranka | 12:9a20164dcc47 | 58 | void ILI932x::init9325() |
vipinranka | 12:9a20164dcc47 | 59 | { |
vipinranka | 12:9a20164dcc47 | 60 | /* Example for ILI9325 ----------------------------------------------------*/ |
vipinranka | 12:9a20164dcc47 | 61 | |
vipinranka | 12:9a20164dcc47 | 62 | flipped=FLIP_NONE; // FLIP_NONE, FLIP_X, FLIP_Y, FLIP_X|FLIP_Y |
vipinranka | 12:9a20164dcc47 | 63 | |
vipinranka | 12:9a20164dcc47 | 64 | reg_write(0x0001,0x0100); |
vipinranka | 12:9a20164dcc47 | 65 | reg_write(0x0002,0x0700); |
vipinranka | 12:9a20164dcc47 | 66 | reg_write(0x0003,0x1030); |
vipinranka | 12:9a20164dcc47 | 67 | reg_write(0x0004,0x0000); |
vipinranka | 12:9a20164dcc47 | 68 | reg_write(0x0008,0x0207); |
vipinranka | 12:9a20164dcc47 | 69 | reg_write(0x0009,0x0000); |
vipinranka | 12:9a20164dcc47 | 70 | reg_write(0x000A,0x0000); |
vipinranka | 12:9a20164dcc47 | 71 | reg_write(0x000C,0x0000); |
vipinranka | 12:9a20164dcc47 | 72 | reg_write(0x000D,0x0000); |
vipinranka | 12:9a20164dcc47 | 73 | reg_write(0x000F,0x0000); |
vipinranka | 12:9a20164dcc47 | 74 | //power on sequence VGHVGL |
vipinranka | 12:9a20164dcc47 | 75 | reg_write(0x0010,0x0000); |
vipinranka | 12:9a20164dcc47 | 76 | reg_write(0x0011,0x0007); |
vipinranka | 12:9a20164dcc47 | 77 | reg_write(0x0012,0x0000); |
vipinranka | 12:9a20164dcc47 | 78 | reg_write(0x0013,0x0000); |
vipinranka | 12:9a20164dcc47 | 79 | reg_write(0x0007,0x0001); |
vipinranka | 12:9a20164dcc47 | 80 | wait_ms(200); |
vipinranka | 12:9a20164dcc47 | 81 | //vgh |
vipinranka | 12:9a20164dcc47 | 82 | reg_write(0x0010,0x1290); |
vipinranka | 12:9a20164dcc47 | 83 | reg_write(0x0011,0x0227); |
vipinranka | 12:9a20164dcc47 | 84 | wait_ms(50); |
vipinranka | 12:9a20164dcc47 | 85 | //vregiout |
vipinranka | 12:9a20164dcc47 | 86 | reg_write(0x0012,0x001d); //0x001b |
vipinranka | 12:9a20164dcc47 | 87 | wait_ms(50); |
vipinranka | 12:9a20164dcc47 | 88 | //vom amplitude |
vipinranka | 12:9a20164dcc47 | 89 | reg_write(0x0013,0x1500); |
vipinranka | 12:9a20164dcc47 | 90 | wait_ms(50); |
vipinranka | 12:9a20164dcc47 | 91 | //vom H |
vipinranka | 12:9a20164dcc47 | 92 | reg_write(0x0029,0x0018); |
vipinranka | 12:9a20164dcc47 | 93 | reg_write(0x002B,0x000D); |
vipinranka | 12:9a20164dcc47 | 94 | wait_ms(50); |
vipinranka | 12:9a20164dcc47 | 95 | //gamma |
vipinranka | 12:9a20164dcc47 | 96 | reg_write(0x0030,0x0004); |
vipinranka | 12:9a20164dcc47 | 97 | reg_write(0x0031,0x0307); |
vipinranka | 12:9a20164dcc47 | 98 | reg_write(0x0032,0x0002);// 0006 |
vipinranka | 12:9a20164dcc47 | 99 | reg_write(0x0035,0x0206); |
vipinranka | 12:9a20164dcc47 | 100 | reg_write(0x0036,0x0408); |
vipinranka | 12:9a20164dcc47 | 101 | reg_write(0x0037,0x0507); |
vipinranka | 12:9a20164dcc47 | 102 | reg_write(0x0038,0x0204);//0200 |
vipinranka | 12:9a20164dcc47 | 103 | reg_write(0x0039,0x0707); |
vipinranka | 12:9a20164dcc47 | 104 | reg_write(0x003C,0x0405);// 0504 |
vipinranka | 12:9a20164dcc47 | 105 | reg_write(0x003D,0x0F02); |
vipinranka | 12:9a20164dcc47 | 106 | //ram |
vipinranka | 12:9a20164dcc47 | 107 | reg_write(0x0050,0x0000); |
vipinranka | 12:9a20164dcc47 | 108 | reg_write(0x0051,0x00EF); |
vipinranka | 12:9a20164dcc47 | 109 | reg_write(0x0052,0x0000); |
vipinranka | 12:9a20164dcc47 | 110 | reg_write(0x0053,0x013F); |
vipinranka | 12:9a20164dcc47 | 111 | reg_write(0x0060,0xA700); |
vipinranka | 12:9a20164dcc47 | 112 | reg_write(0x0061,0x0001); |
vipinranka | 12:9a20164dcc47 | 113 | reg_write(0x006A,0x0000); |
vipinranka | 12:9a20164dcc47 | 114 | // |
vipinranka | 12:9a20164dcc47 | 115 | reg_write(0x0080,0x0000); |
vipinranka | 12:9a20164dcc47 | 116 | reg_write(0x0081,0x0000); |
vipinranka | 12:9a20164dcc47 | 117 | reg_write(0x0082,0x0000); |
vipinranka | 12:9a20164dcc47 | 118 | reg_write(0x0083,0x0000); |
vipinranka | 12:9a20164dcc47 | 119 | reg_write(0x0084,0x0000); |
vipinranka | 12:9a20164dcc47 | 120 | reg_write(0x0085,0x0000); |
vipinranka | 12:9a20164dcc47 | 121 | // |
vipinranka | 12:9a20164dcc47 | 122 | reg_write(0x0090,0x0010); |
vipinranka | 12:9a20164dcc47 | 123 | reg_write(0x0092,0x0600); |
vipinranka | 12:9a20164dcc47 | 124 | reg_write(0x0093,0x0003); |
vipinranka | 12:9a20164dcc47 | 125 | reg_write(0x0095,0x0110); |
vipinranka | 12:9a20164dcc47 | 126 | reg_write(0x0097,0x0000); |
vipinranka | 12:9a20164dcc47 | 127 | reg_write(0x0098,0x0000); |
vipinranka | 12:9a20164dcc47 | 128 | |
vipinranka | 12:9a20164dcc47 | 129 | reg_write(0x0007,0x0133); // display on |
vipinranka | 12:9a20164dcc47 | 130 | |
vipinranka | 12:9a20164dcc47 | 131 | } |
vipinranka | 12:9a20164dcc47 | 132 | void ILI932x::init9320() |
vipinranka | 12:9a20164dcc47 | 133 | { |
vipinranka | 12:9a20164dcc47 | 134 | /* Example for ILI9320 ----------------------------------------------------*/ |
vipinranka | 12:9a20164dcc47 | 135 | |
vipinranka | 12:9a20164dcc47 | 136 | flipped=FLIP_X; // FLIP_NONE, FLIP_X, FLIP_Y, FLIP_X|FLIP_Y |
vipinranka | 12:9a20164dcc47 | 137 | |
vipinranka | 12:9a20164dcc47 | 138 | reg_write(0x0001,0x0100); |
vipinranka | 12:9a20164dcc47 | 139 | reg_write(0x0002,0x0700); |
vipinranka | 12:9a20164dcc47 | 140 | reg_write(0x0003,0x1030); |
vipinranka | 12:9a20164dcc47 | 141 | reg_write(0x0004,0x0000); |
vipinranka | 12:9a20164dcc47 | 142 | reg_write(0x0008,0x0202); |
vipinranka | 12:9a20164dcc47 | 143 | reg_write(0x0009,0x0000); |
vipinranka | 12:9a20164dcc47 | 144 | reg_write(0x000A,0x0000); |
vipinranka | 12:9a20164dcc47 | 145 | reg_write(0x000C,0x0000); |
vipinranka | 12:9a20164dcc47 | 146 | reg_write(0x000D,0x0000); |
vipinranka | 12:9a20164dcc47 | 147 | reg_write(0x000F,0x0000); |
vipinranka | 12:9a20164dcc47 | 148 | //power on sequence |
vipinranka | 12:9a20164dcc47 | 149 | reg_write(0x0010,0x0000); |
vipinranka | 12:9a20164dcc47 | 150 | reg_write(0x0011,0x0007); |
vipinranka | 12:9a20164dcc47 | 151 | reg_write(0x0012,0x0000); |
vipinranka | 12:9a20164dcc47 | 152 | reg_write(0x0013,0x0000); |
vipinranka | 12:9a20164dcc47 | 153 | reg_write(0x0007,0x0001); |
vipinranka | 12:9a20164dcc47 | 154 | wait_ms(200); |
vipinranka | 12:9a20164dcc47 | 155 | |
vipinranka | 12:9a20164dcc47 | 156 | reg_write(0x0010,0x10C0); |
vipinranka | 12:9a20164dcc47 | 157 | reg_write(0x0011,0x0007); |
vipinranka | 12:9a20164dcc47 | 158 | wait_ms(50); |
vipinranka | 12:9a20164dcc47 | 159 | |
vipinranka | 12:9a20164dcc47 | 160 | reg_write(0x0012,0x0110); |
vipinranka | 12:9a20164dcc47 | 161 | wait_ms(50); |
vipinranka | 12:9a20164dcc47 | 162 | |
vipinranka | 12:9a20164dcc47 | 163 | reg_write(0x0013,0x0b00); |
vipinranka | 12:9a20164dcc47 | 164 | wait_ms(50); |
vipinranka | 12:9a20164dcc47 | 165 | |
vipinranka | 12:9a20164dcc47 | 166 | reg_write(0x0029,0x0000); |
vipinranka | 12:9a20164dcc47 | 167 | reg_write(0x002B,0x4010); // bit 14??? |
vipinranka | 12:9a20164dcc47 | 168 | wait_ms(50); |
vipinranka | 12:9a20164dcc47 | 169 | //gamma |
vipinranka | 12:9a20164dcc47 | 170 | /* |
vipinranka | 12:9a20164dcc47 | 171 | reg_write(0x0030,0x0004); |
vipinranka | 12:9a20164dcc47 | 172 | reg_write(0x0031,0x0307); |
vipinranka | 12:9a20164dcc47 | 173 | reg_write(0x0032,0x0002);// 0006 |
vipinranka | 12:9a20164dcc47 | 174 | reg_write(0x0035,0x0206); |
vipinranka | 12:9a20164dcc47 | 175 | reg_write(0x0036,0x0408); |
vipinranka | 12:9a20164dcc47 | 176 | reg_write(0x0037,0x0507); |
vipinranka | 12:9a20164dcc47 | 177 | reg_write(0x0038,0x0204);//0200 |
vipinranka | 12:9a20164dcc47 | 178 | reg_write(0x0039,0x0707); |
vipinranka | 12:9a20164dcc47 | 179 | reg_write(0x003C,0x0405);// 0504 |
vipinranka | 12:9a20164dcc47 | 180 | reg_write(0x003D,0x0F02); |
vipinranka | 12:9a20164dcc47 | 181 | */ |
vipinranka | 12:9a20164dcc47 | 182 | //ram |
vipinranka | 12:9a20164dcc47 | 183 | reg_write(0x0050,0x0000); |
vipinranka | 12:9a20164dcc47 | 184 | reg_write(0x0051,0x00EF); |
vipinranka | 12:9a20164dcc47 | 185 | reg_write(0x0052,0x0000); |
vipinranka | 12:9a20164dcc47 | 186 | reg_write(0x0053,0x013F); |
vipinranka | 12:9a20164dcc47 | 187 | reg_write(0x0060,0x2700); |
vipinranka | 12:9a20164dcc47 | 188 | reg_write(0x0061,0x0001); |
vipinranka | 12:9a20164dcc47 | 189 | reg_write(0x006A,0x0000); |
vipinranka | 12:9a20164dcc47 | 190 | // |
vipinranka | 12:9a20164dcc47 | 191 | reg_write(0x0080,0x0000); |
vipinranka | 12:9a20164dcc47 | 192 | reg_write(0x0081,0x0000); |
vipinranka | 12:9a20164dcc47 | 193 | reg_write(0x0082,0x0000); |
vipinranka | 12:9a20164dcc47 | 194 | reg_write(0x0083,0x0000); |
vipinranka | 12:9a20164dcc47 | 195 | reg_write(0x0084,0x0000); |
vipinranka | 12:9a20164dcc47 | 196 | reg_write(0x0085,0x0000); |
vipinranka | 12:9a20164dcc47 | 197 | // |
vipinranka | 12:9a20164dcc47 | 198 | reg_write(0x0090,0x0000); |
vipinranka | 12:9a20164dcc47 | 199 | reg_write(0x0092,0x0000); |
vipinranka | 12:9a20164dcc47 | 200 | reg_write(0x0093,0x0001); |
vipinranka | 12:9a20164dcc47 | 201 | reg_write(0x0095,0x0110); |
vipinranka | 12:9a20164dcc47 | 202 | reg_write(0x0097,0x0000); |
vipinranka | 12:9a20164dcc47 | 203 | reg_write(0x0098,0x0000); |
vipinranka | 12:9a20164dcc47 | 204 | |
vipinranka | 12:9a20164dcc47 | 205 | reg_write(0x0007,0x0133); // display on |
vipinranka | 12:9a20164dcc47 | 206 | |
vipinranka | 12:9a20164dcc47 | 207 | } |