Firmware for Nucleo boards for the SLab system Description at http://r6500.blogspot.com.es/2018/02/slab-first-release.html All associated files at https://github.com/R6500/SLab
main.cpp@1:d81bef65eece, 2018-02-11 (annotated)
- Committer:
- vic20
- Date:
- Sun Feb 11 16:14:51 2018 +0000
- Revision:
- 1:d81bef65eece
- Parent:
- 0:39a545e08ccd
Version 1.2 (Halt button added)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
vic20 | 0:39a545e08ccd | 1 | /******************************************************* |
vic20 | 0:39a545e08ccd | 2 | |
vic20 | 0:39a545e08ccd | 3 | SLab - Python |
vic20 | 0:39a545e08ccd | 4 | |
vic20 | 0:39a545e08ccd | 5 | MBED Firmware for Nucleo Boards |
vic20 | 0:39a545e08ccd | 6 | Alternate version for profiling |
vic20 | 0:39a545e08ccd | 7 | |
vic20 | 0:39a545e08ccd | 8 | Program to operate a nucleo board from a PC |
vic20 | 0:39a545e08ccd | 9 | in order to perform measurements. |
vic20 | 0:39a545e08ccd | 10 | |
vic20 | 0:39a545e08ccd | 11 | Desgined for the Nucleo64 F303RE Board |
vic20 | 0:39a545e08ccd | 12 | |
vic20 | 0:39a545e08ccd | 13 | Commands implemented in version 1 |
vic20 | 0:39a545e08ccd | 14 | |
vic20 | 0:39a545e08ccd | 15 | Global |
vic20 | 0:39a545e08ccd | 16 | |
vic20 | 0:39a545e08ccd | 17 | F : Obtain a string that describes the firmware |
vic20 | 0:39a545e08ccd | 18 | M : Obtain 4 byte magic code |
vic20 | 0:39a545e08ccd | 19 | I : Board capabilities identification |
vic20 | 0:39a545e08ccd | 20 | L : Pin list |
vic20 | 0:39a545e08ccd | 21 | E : Soft Reset |
vic20 | 0:39a545e08ccd | 22 | |
vic20 | 0:39a545e08ccd | 23 | DC |
vic20 | 0:39a545e08ccd | 24 | |
vic20 | 0:39a545e08ccd | 25 | A + 1 : Read one ADC channel |
vic20 | 0:39a545e08ccd | 26 | D + 3 : Write one DAC channel |
vic20 | 0:39a545e08ccd | 27 | N + 2 : Set number of reads to average |
vic20 | 0:39a545e08ccd | 28 | |
vic20 | 0:39a545e08ccd | 29 | |
vic20 | 0:39a545e08ccd | 30 | Transient |
vic20 | 0:39a545e08ccd | 31 | |
vic20 | 0:39a545e08ccd | 32 | R + 2 : Set sample time |
vic20 | 0:39a545e08ccd | 33 | S + 4 : Set storage configuration |
vic20 | 0:39a545e08ccd | 34 | Y : Async read |
vic20 | 0:39a545e08ccd | 35 | G + 3 : Triggered read |
vic20 | 0:39a545e08ccd | 36 | P + 2 : Step response |
vic20 | 0:39a545e08ccd | 37 | |
vic20 | 0:39a545e08ccd | 38 | Wavetable |
vic20 | 0:39a545e08ccd | 39 | |
vic20 | 0:39a545e08ccd | 40 | W + n : Load a wavetable |
vic20 | 0:39a545e08ccd | 41 | w + n : Load a secondary wavetable |
vic20 | 0:39a545e08ccd | 42 | V + 2 : Wave response |
vic20 | 0:39a545e08ccd | 43 | v + 2 : Dual wave response |
vic20 | 0:39a545e08ccd | 44 | X + 3 : Single Wave Response |
vic20 | 0:39a545e08ccd | 45 | Q + 2 : Wave Play |
vic20 | 0:39a545e08ccd | 46 | q + 2 : Dual Wave Play |
vic20 | 0:39a545e08ccd | 47 | |
vic20 | 0:39a545e08ccd | 48 | Digital I/O |
vic20 | 0:39a545e08ccd | 49 | |
vic20 | 0:39a545e08ccd | 50 | H + 2 : dio mode |
vic20 | 0:39a545e08ccd | 51 | J + 2 : dio write |
vic20 | 0:39a545e08ccd | 52 | K + 1 : dio read |
vic20 | 0:39a545e08ccd | 53 | |
vic20 | 0:39a545e08ccd | 54 | Incidences: |
vic20 | 0:39a545e08ccd | 55 | |
vic20 | 0:39a545e08ccd | 56 | 06/04/2017 : Open Drain does not work as expected |
vic20 | 0:39a545e08ccd | 57 | It is currently disabled |
vic20 | 0:39a545e08ccd | 58 | |
vic20 | 0:39a545e08ccd | 59 | 25/10/2017 : v1.1 |
vic20 | 0:39a545e08ccd | 60 | Hardware profile lines added |
vic20 | 0:39a545e08ccd | 61 | Improved timings. Minimum sample times: |
vic20 | 0:39a545e08ccd | 62 | Asyn Read: 1CH (13us) 2CH (33us) 3CH (43us) 4CH (54us) |
vic20 | 0:39a545e08ccd | 63 | Trig Read: 1CH (13us) 2CH (33us) 3CH (44us) 4CH (54us) |
vic20 | 0:39a545e08ccd | 64 | Step Resp: 1CH (13us) 2CH (36us) 3CH (46us) 4CH (56us) |
vic20 | 0:39a545e08ccd | 65 | Wave Resp: 1CH (13us) 2CH (38us) 3CH (47us) 4CH (58us) |
vic20 | 0:39a545e08ccd | 66 | Dual Wave: 1CH (13us) 2CH (40us) 3CH (50us) 4CH (61us) |
vic20 | 0:39a545e08ccd | 67 | Sing Wave: 1CH Only (13us) |
vic20 | 0:39a545e08ccd | 68 | Wave play: No ADC (11us) |
vic20 | 0:39a545e08ccd | 69 | Dual wave play: No ADC (11us) |
vic20 | 0:39a545e08ccd | 70 | |
vic20 | 1:d81bef65eece | 71 | 10/02/2018 : v1.2 |
vic20 | 1:d81bef65eece | 72 | Addition of halt button/interrupt |
vic20 | 1:d81bef65eece | 73 | 11/02/2018 : Correction of bug in return code from dualWavePlay |
vic20 | 1:d81bef65eece | 74 | |
vic20 | 0:39a545e08ccd | 75 | ********************************************************/ |
vic20 | 0:39a545e08ccd | 76 | |
vic20 | 0:39a545e08ccd | 77 | #include "mbed.h" |
vic20 | 0:39a545e08ccd | 78 | |
vic20 | 0:39a545e08ccd | 79 | /***************** MAIN DEFINES *************************************/ |
vic20 | 0:39a545e08ccd | 80 | |
vic20 | 0:39a545e08ccd | 81 | // Version string |
vic20 | 1:d81bef65eece | 82 | #define VSTRING " v1.2" |
vic20 | 0:39a545e08ccd | 83 | |
vic20 | 0:39a545e08ccd | 84 | // Major number version changes when new commands are added |
vic20 | 0:39a545e08ccd | 85 | #define VERSION 1 |
vic20 | 0:39a545e08ccd | 86 | |
vic20 | 0:39a545e08ccd | 87 | // Uncomment to use hardware profiling during tests |
vic20 | 0:39a545e08ccd | 88 | // It should be commented for release versions |
vic20 | 0:39a545e08ccd | 89 | //#define USE_PROFILING 1 |
vic20 | 0:39a545e08ccd | 90 | |
vic20 | 0:39a545e08ccd | 91 | // Information about the board |
vic20 | 0:39a545e08ccd | 92 | #include "Nucleo64-F303RE.h" // Board 1 |
vic20 | 0:39a545e08ccd | 93 | //#include "Nucleo32-F303K8.h" // Board 2 |
vic20 | 0:39a545e08ccd | 94 | //#include "Nucleo64-L152RE.h" // Board 3 |
vic20 | 0:39a545e08ccd | 95 | |
vic20 | 0:39a545e08ccd | 96 | /******************* OTHER CONSTANTS ******************************/ |
vic20 | 0:39a545e08ccd | 97 | |
vic20 | 0:39a545e08ccd | 98 | // Max value in unsigned 16bit as float number |
vic20 | 0:39a545e08ccd | 99 | #define MAX16F 65536.0f |
vic20 | 0:39a545e08ccd | 100 | |
vic20 | 0:39a545e08ccd | 101 | // Special serial codes |
vic20 | 0:39a545e08ccd | 102 | #define ACK 181 |
vic20 | 0:39a545e08ccd | 103 | #define NACK 226 |
vic20 | 0:39a545e08ccd | 104 | #define ECRC 37 |
vic20 | 0:39a545e08ccd | 105 | |
vic20 | 0:39a545e08ccd | 106 | // Codes for transient responses |
vic20 | 0:39a545e08ccd | 107 | #define TRAN_OK 0 // Ok |
vic20 | 0:39a545e08ccd | 108 | #define TRAN_OVERRUN 1 // Sample overrun |
vic20 | 0:39a545e08ccd | 109 | #define TRAN_TIMEOUT 2 // Triggered timeout |
vic20 | 1:d81bef65eece | 110 | #define TRAN_HALT 3 // Halt interrupt generated |
vic20 | 0:39a545e08ccd | 111 | |
vic20 | 0:39a545e08ccd | 112 | // Magic data is different for each firmware |
vic20 | 0:39a545e08ccd | 113 | #define MAGIC_SIZE 4 |
vic20 | 0:39a545e08ccd | 114 | const uint8_t magic[MAGIC_SIZE]={56,41,18,1}; |
vic20 | 0:39a545e08ccd | 115 | |
vic20 | 0:39a545e08ccd | 116 | /***************** VARIABLES AND OBJECTS *************************/ |
vic20 | 0:39a545e08ccd | 117 | |
vic20 | 0:39a545e08ccd | 118 | Serial pc(SERIAL_TX, SERIAL_RX, 38400); // Serial link with PC |
vic20 | 0:39a545e08ccd | 119 | |
vic20 | 0:39a545e08ccd | 120 | AnalogIn ain1(AD1); |
vic20 | 0:39a545e08ccd | 121 | AnalogIn ain2(AD2); |
vic20 | 0:39a545e08ccd | 122 | AnalogIn ain3(AD3); |
vic20 | 0:39a545e08ccd | 123 | AnalogIn ain4(AD4); |
vic20 | 0:39a545e08ccd | 124 | |
vic20 | 0:39a545e08ccd | 125 | AnalogIn *ainList[NADCS]; |
vic20 | 0:39a545e08ccd | 126 | |
vic20 | 0:39a545e08ccd | 127 | AnalogOut aout1(DA1); // DAC1 |
vic20 | 0:39a545e08ccd | 128 | AnalogOut aout2(DA2); // DAC2 |
vic20 | 0:39a545e08ccd | 129 | #ifdef EXIST_DAC3 |
vic20 | 0:39a545e08ccd | 130 | AnalogOut aout3(DA3); // DAC3 if exists |
vic20 | 0:39a545e08ccd | 131 | #endif |
vic20 | 0:39a545e08ccd | 132 | |
vic20 | 0:39a545e08ccd | 133 | #ifdef EXIST_DIO // For now, it requires 8 DIO |
vic20 | 0:39a545e08ccd | 134 | DigitalInOut dio1(DIO1); |
vic20 | 0:39a545e08ccd | 135 | DigitalInOut dio2(DIO2); |
vic20 | 0:39a545e08ccd | 136 | DigitalInOut dio3(DIO3); |
vic20 | 0:39a545e08ccd | 137 | DigitalInOut dio4(DIO4); |
vic20 | 0:39a545e08ccd | 138 | DigitalInOut dio5(DIO5); |
vic20 | 0:39a545e08ccd | 139 | DigitalInOut dio6(DIO6); |
vic20 | 0:39a545e08ccd | 140 | DigitalInOut dio7(DIO7); |
vic20 | 0:39a545e08ccd | 141 | DigitalInOut dio8(DIO8); |
vic20 | 0:39a545e08ccd | 142 | |
vic20 | 0:39a545e08ccd | 143 | DigitalInOut *dioList[NDIO]; |
vic20 | 0:39a545e08ccd | 144 | #endif |
vic20 | 0:39a545e08ccd | 145 | |
vic20 | 0:39a545e08ccd | 146 | // Sample time period defaults to 1ms |
vic20 | 0:39a545e08ccd | 147 | float stime = 0.001; |
vic20 | 0:39a545e08ccd | 148 | |
vic20 | 0:39a545e08ccd | 149 | // Buffer for storage of inputs (in U16) |
vic20 | 0:39a545e08ccd | 150 | //uint16_t inBuff[IN_BSIZE]; |
vic20 | 0:39a545e08ccd | 151 | |
vic20 | 0:39a545e08ccd | 152 | // Wavetable buffer (in U16) |
vic20 | 0:39a545e08ccd | 153 | //uint16_t waveBuff[WSIZE]; |
vic20 | 0:39a545e08ccd | 154 | |
vic20 | 0:39a545e08ccd | 155 | // Unified memory buffer |
vic20 | 0:39a545e08ccd | 156 | uint16_t buff[BSIZE]; |
vic20 | 0:39a545e08ccd | 157 | |
vic20 | 0:39a545e08ccd | 158 | // Start of all buffer sections |
vic20 | 0:39a545e08ccd | 159 | uint16_t *wave2buff = NULL; |
vic20 | 0:39a545e08ccd | 160 | uint16_t *tranBuff = NULL; |
vic20 | 0:39a545e08ccd | 161 | |
vic20 | 0:39a545e08ccd | 162 | // DC analog read number of readings |
vic20 | 0:39a545e08ccd | 163 | int nread = 10; |
vic20 | 0:39a545e08ccd | 164 | |
vic20 | 0:39a545e08ccd | 165 | // Input configuration |
vic20 | 0:39a545e08ccd | 166 | int n_ai = 1; // Number of analog inputs |
vic20 | 0:39a545e08ccd | 167 | int n_di = 0; // Number of digital inputs (always zero) |
vic20 | 0:39a545e08ccd | 168 | int n_s = 1000; // Number of samples |
vic20 | 0:39a545e08ccd | 169 | |
vic20 | 0:39a545e08ccd | 170 | // Ticker for readings |
vic20 | 0:39a545e08ccd | 171 | Ticker ticR; |
vic20 | 0:39a545e08ccd | 172 | |
vic20 | 0:39a545e08ccd | 173 | // Sample information for ticker |
vic20 | 0:39a545e08ccd | 174 | int samples = 0; // Number of processed samples |
vic20 | 0:39a545e08ccd | 175 | int inBuffPos = 0; // Current buffer position |
vic20 | 0:39a545e08ccd | 176 | |
vic20 | 0:39a545e08ccd | 177 | int presamples; // Number of samples before trigger |
vic20 | 0:39a545e08ccd | 178 | int postsamples; // Number of samples after trigger |
vic20 | 0:39a545e08ccd | 179 | int triggerSample; // Sample number at trigger point |
vic20 | 0:39a545e08ccd | 180 | int samplePhase; // Sample phase |
vic20 | 0:39a545e08ccd | 181 | int currentBsize; // Current buffer size |
vic20 | 0:39a545e08ccd | 182 | int trigger; // Trigger value |
vic20 | 0:39a545e08ccd | 183 | int triggerMode; // Trigger mode (0 Rise 1 Fall) |
vic20 | 0:39a545e08ccd | 184 | int stepValue; // Value for step analysis |
vic20 | 0:39a545e08ccd | 185 | |
vic20 | 0:39a545e08ccd | 186 | int checkTimeOut; // Indicates if we check timeout |
vic20 | 0:39a545e08ccd | 187 | uint32_t timeOut; // Timeout for triggered capture |
vic20 | 0:39a545e08ccd | 188 | |
vic20 | 0:39a545e08ccd | 189 | // Global to communicate with ISR ticker |
vic20 | 0:39a545e08ccd | 190 | volatile int endTicker = 0; |
vic20 | 0:39a545e08ccd | 191 | |
vic20 | 0:39a545e08ccd | 192 | // Global to check overruns |
vic20 | 0:39a545e08ccd | 193 | volatile int overrun = 0; |
vic20 | 0:39a545e08ccd | 194 | volatile int overrun_error = 0; |
vic20 | 0:39a545e08ccd | 195 | volatile int timeout_error = 0; |
vic20 | 0:39a545e08ccd | 196 | |
vic20 | 0:39a545e08ccd | 197 | int w_s = 0; // Wavetable size (in samples) |
vic20 | 0:39a545e08ccd | 198 | volatile int w_n = 10; // Number of waves before measurement |
vic20 | 0:39a545e08ccd | 199 | volatile int w_pos = 0; // Current wave position |
vic20 | 0:39a545e08ccd | 200 | |
vic20 | 0:39a545e08ccd | 201 | int w_s2 = 0; // Secondary wavetable size (in samples) |
vic20 | 0:39a545e08ccd | 202 | volatile int w_pos2 = 0; // Current secondary wave position |
vic20 | 0:39a545e08ccd | 203 | |
vic20 | 1:d81bef65eece | 204 | int infiniteWave = 0; // Flag for infinite wave play |
vic20 | 1:d81bef65eece | 205 | |
vic20 | 0:39a545e08ccd | 206 | // Globals for CRC |
vic20 | 0:39a545e08ccd | 207 | int crcTx,crcRx; |
vic20 | 0:39a545e08ccd | 208 | |
vic20 | 0:39a545e08ccd | 209 | // Selected ADC for transient |
vic20 | 0:39a545e08ccd | 210 | AnalogIn *ain_tran; |
vic20 | 0:39a545e08ccd | 211 | |
vic20 | 0:39a545e08ccd | 212 | // Indicate that board status is at reset condition |
vic20 | 0:39a545e08ccd | 213 | int resetState=1; |
vic20 | 0:39a545e08ccd | 214 | |
vic20 | 1:d81bef65eece | 215 | // Halt interrupt (if enabled) |
vic20 | 1:d81bef65eece | 216 | #ifdef HALT_PIN |
vic20 | 1:d81bef65eece | 217 | InterruptIn haltInt(HALT_PIN); |
vic20 | 1:d81bef65eece | 218 | #endif |
vic20 | 1:d81bef65eece | 219 | |
vic20 | 1:d81bef65eece | 220 | // Halt condition flag |
vic20 | 1:d81bef65eece | 221 | volatile int halt = 0; |
vic20 | 1:d81bef65eece | 222 | |
vic20 | 1:d81bef65eece | 223 | |
vic20 | 0:39a545e08ccd | 224 | /****************** HARDWARE PROFILING *********************************/ |
vic20 | 0:39a545e08ccd | 225 | // Uses GPIO lines to show system activity |
vic20 | 0:39a545e08ccd | 226 | |
vic20 | 0:39a545e08ccd | 227 | #ifdef USE_PROFILING |
vic20 | 0:39a545e08ccd | 228 | |
vic20 | 0:39a545e08ccd | 229 | // Profiling outputs |
vic20 | 0:39a545e08ccd | 230 | DigitalOut pro1(PRO1_PIN); |
vic20 | 0:39a545e08ccd | 231 | DigitalOut pro2(PRO2_PIN); |
vic20 | 0:39a545e08ccd | 232 | |
vic20 | 0:39a545e08ccd | 233 | #else |
vic20 | 0:39a545e08ccd | 234 | |
vic20 | 0:39a545e08ccd | 235 | #define PRO1_SET /* No code */ |
vic20 | 0:39a545e08ccd | 236 | #define PRO1_CLEAR /* No code */ |
vic20 | 0:39a545e08ccd | 237 | #define PRO2_SET /* No code */ |
vic20 | 0:39a545e08ccd | 238 | #define PRO2_CLEAR /* No code */ |
vic20 | 0:39a545e08ccd | 239 | |
vic20 | 0:39a545e08ccd | 240 | #endif //USE_PROFILING |
vic20 | 0:39a545e08ccd | 241 | |
vic20 | 0:39a545e08ccd | 242 | /*********************** SERIAL CODE **********************************/ |
vic20 | 0:39a545e08ccd | 243 | |
vic20 | 0:39a545e08ccd | 244 | // Start Tx |
vic20 | 0:39a545e08ccd | 245 | // Clears the tx crc |
vic20 | 0:39a545e08ccd | 246 | void startTx() |
vic20 | 0:39a545e08ccd | 247 | { |
vic20 | 0:39a545e08ccd | 248 | crcTx = 0; |
vic20 | 0:39a545e08ccd | 249 | } |
vic20 | 0:39a545e08ccd | 250 | |
vic20 | 0:39a545e08ccd | 251 | // Send Tx CRC |
vic20 | 0:39a545e08ccd | 252 | // Usually that ends transmission |
vic20 | 0:39a545e08ccd | 253 | void sendCRC() |
vic20 | 0:39a545e08ccd | 254 | { |
vic20 | 0:39a545e08ccd | 255 | pc.putc(crcTx); |
vic20 | 0:39a545e08ccd | 256 | } |
vic20 | 0:39a545e08ccd | 257 | |
vic20 | 0:39a545e08ccd | 258 | // Send one byte and computes crc |
vic20 | 0:39a545e08ccd | 259 | void sendByte(int value) |
vic20 | 0:39a545e08ccd | 260 | { |
vic20 | 0:39a545e08ccd | 261 | pc.putc(value); |
vic20 | 0:39a545e08ccd | 262 | crcTx = crcTx ^ value; |
vic20 | 0:39a545e08ccd | 263 | } |
vic20 | 0:39a545e08ccd | 264 | |
vic20 | 0:39a545e08ccd | 265 | // Send one uint16 and computes crc |
vic20 | 0:39a545e08ccd | 266 | void sendU16(int value) |
vic20 | 0:39a545e08ccd | 267 | { |
vic20 | 0:39a545e08ccd | 268 | int low,high; |
vic20 | 0:39a545e08ccd | 269 | |
vic20 | 0:39a545e08ccd | 270 | high = value / 256; |
vic20 | 0:39a545e08ccd | 271 | low = value % 256; |
vic20 | 0:39a545e08ccd | 272 | |
vic20 | 0:39a545e08ccd | 273 | sendByte(low); |
vic20 | 0:39a545e08ccd | 274 | sendByte(high); |
vic20 | 0:39a545e08ccd | 275 | } |
vic20 | 0:39a545e08ccd | 276 | |
vic20 | 0:39a545e08ccd | 277 | // Send float as mantisa and exponent |
vic20 | 0:39a545e08ccd | 278 | void sendMantExp(int mantissa, int exponent) |
vic20 | 0:39a545e08ccd | 279 | { |
vic20 | 0:39a545e08ccd | 280 | sendByte(exponent+128); |
vic20 | 0:39a545e08ccd | 281 | sendU16(mantissa+20000); |
vic20 | 0:39a545e08ccd | 282 | } |
vic20 | 0:39a545e08ccd | 283 | |
vic20 | 0:39a545e08ccd | 284 | // Send one string and computes crc |
vic20 | 0:39a545e08ccd | 285 | void sendString(char *str) |
vic20 | 0:39a545e08ccd | 286 | { |
vic20 | 0:39a545e08ccd | 287 | while (*str) |
vic20 | 0:39a545e08ccd | 288 | { |
vic20 | 0:39a545e08ccd | 289 | sendByte(*str); |
vic20 | 0:39a545e08ccd | 290 | str++; |
vic20 | 0:39a545e08ccd | 291 | } |
vic20 | 0:39a545e08ccd | 292 | } |
vic20 | 0:39a545e08ccd | 293 | |
vic20 | 0:39a545e08ccd | 294 | // Start of a Rx reception |
vic20 | 0:39a545e08ccd | 295 | void startRx() |
vic20 | 0:39a545e08ccd | 296 | { |
vic20 | 0:39a545e08ccd | 297 | crcRx = 0; |
vic20 | 0:39a545e08ccd | 298 | } |
vic20 | 0:39a545e08ccd | 299 | |
vic20 | 0:39a545e08ccd | 300 | |
vic20 | 0:39a545e08ccd | 301 | // Get CRC anc check it |
vic20 | 0:39a545e08ccd | 302 | // It usually ends the Rx reception |
vic20 | 0:39a545e08ccd | 303 | // Returns 1 if CRC is ok, 0 if not |
vic20 | 0:39a545e08ccd | 304 | int getAndCheckCRC() |
vic20 | 0:39a545e08ccd | 305 | { |
vic20 | 0:39a545e08ccd | 306 | int crc; |
vic20 | 0:39a545e08ccd | 307 | |
vic20 | 0:39a545e08ccd | 308 | crc = pc.getc(); |
vic20 | 0:39a545e08ccd | 309 | if (crc != crcRx) return 0; |
vic20 | 0:39a545e08ccd | 310 | return 1; |
vic20 | 0:39a545e08ccd | 311 | } |
vic20 | 0:39a545e08ccd | 312 | |
vic20 | 0:39a545e08ccd | 313 | // Get and check CRC and sends ECRC in case of error |
vic20 | 0:39a545e08ccd | 314 | // If no error, don't respond anything |
vic20 | 0:39a545e08ccd | 315 | // Returns 1 if CRC is ok, 0 if not |
vic20 | 0:39a545e08ccd | 316 | int crcResponse() |
vic20 | 0:39a545e08ccd | 317 | { |
vic20 | 0:39a545e08ccd | 318 | // Check if CRC is ok |
vic20 | 0:39a545e08ccd | 319 | if (getAndCheckCRC()) return 1; |
vic20 | 0:39a545e08ccd | 320 | |
vic20 | 0:39a545e08ccd | 321 | // If CRC is not ok |
vic20 | 0:39a545e08ccd | 322 | sendByte(ECRC); |
vic20 | 0:39a545e08ccd | 323 | // End transmission |
vic20 | 0:39a545e08ccd | 324 | sendCRC(); |
vic20 | 0:39a545e08ccd | 325 | return 0; |
vic20 | 0:39a545e08ccd | 326 | } |
vic20 | 0:39a545e08ccd | 327 | |
vic20 | 0:39a545e08ccd | 328 | |
vic20 | 0:39a545e08ccd | 329 | // Get one byte and computes crc |
vic20 | 0:39a545e08ccd | 330 | int getByte() |
vic20 | 0:39a545e08ccd | 331 | { |
vic20 | 0:39a545e08ccd | 332 | int byte; |
vic20 | 0:39a545e08ccd | 333 | |
vic20 | 0:39a545e08ccd | 334 | byte = pc.getc(); |
vic20 | 0:39a545e08ccd | 335 | crcRx = crcRx ^byte; |
vic20 | 0:39a545e08ccd | 336 | return byte; |
vic20 | 0:39a545e08ccd | 337 | } |
vic20 | 0:39a545e08ccd | 338 | |
vic20 | 0:39a545e08ccd | 339 | |
vic20 | 0:39a545e08ccd | 340 | // Get one uint16 and computes crc |
vic20 | 0:39a545e08ccd | 341 | int getU16() |
vic20 | 0:39a545e08ccd | 342 | { |
vic20 | 0:39a545e08ccd | 343 | int low, high, value; |
vic20 | 0:39a545e08ccd | 344 | |
vic20 | 0:39a545e08ccd | 345 | low = getByte(); |
vic20 | 0:39a545e08ccd | 346 | high = getByte(); |
vic20 | 0:39a545e08ccd | 347 | value = (256 * high) + low; |
vic20 | 0:39a545e08ccd | 348 | |
vic20 | 0:39a545e08ccd | 349 | return value; |
vic20 | 0:39a545e08ccd | 350 | } |
vic20 | 0:39a545e08ccd | 351 | |
vic20 | 0:39a545e08ccd | 352 | |
vic20 | 0:39a545e08ccd | 353 | // Get one float value and computes crc |
vic20 | 0:39a545e08ccd | 354 | float getFloat() |
vic20 | 0:39a545e08ccd | 355 | { |
vic20 | 0:39a545e08ccd | 356 | int exp,mant; |
vic20 | 0:39a545e08ccd | 357 | float value; |
vic20 | 0:39a545e08ccd | 358 | |
vic20 | 0:39a545e08ccd | 359 | exp = getByte() - 128; |
vic20 | 0:39a545e08ccd | 360 | mant = getU16() - 20000; |
vic20 | 0:39a545e08ccd | 361 | |
vic20 | 0:39a545e08ccd | 362 | value = ((float)mant) * pow((float)10.0,(float)exp); |
vic20 | 0:39a545e08ccd | 363 | |
vic20 | 0:39a545e08ccd | 364 | return value; |
vic20 | 0:39a545e08ccd | 365 | } |
vic20 | 0:39a545e08ccd | 366 | |
vic20 | 0:39a545e08ccd | 367 | /*********************** DC CODE ********************************/ |
vic20 | 0:39a545e08ccd | 368 | |
vic20 | 0:39a545e08ccd | 369 | // Reads one analog line 1... |
vic20 | 0:39a545e08ccd | 370 | // Discards the first reading |
vic20 | 0:39a545e08ccd | 371 | // Uses the indicated number of readings |
vic20 | 0:39a545e08ccd | 372 | static int analogRead(int line) |
vic20 | 0:39a545e08ccd | 373 | { |
vic20 | 0:39a545e08ccd | 374 | int i,value; |
vic20 | 0:39a545e08ccd | 375 | uint32_t sum; |
vic20 | 0:39a545e08ccd | 376 | |
vic20 | 0:39a545e08ccd | 377 | sum = 0; |
vic20 | 0:39a545e08ccd | 378 | for(i=0;i<=nread;i++) |
vic20 | 0:39a545e08ccd | 379 | { |
vic20 | 0:39a545e08ccd | 380 | value=ainList[line-1]->read_u16(); |
vic20 | 0:39a545e08ccd | 381 | if (i) sum+=value; |
vic20 | 0:39a545e08ccd | 382 | } |
vic20 | 0:39a545e08ccd | 383 | |
vic20 | 0:39a545e08ccd | 384 | value = sum/nread; |
vic20 | 0:39a545e08ccd | 385 | |
vic20 | 0:39a545e08ccd | 386 | return value; |
vic20 | 0:39a545e08ccd | 387 | } |
vic20 | 0:39a545e08ccd | 388 | |
vic20 | 0:39a545e08ccd | 389 | /********************* TRANSIENT CODE ***************************/ |
vic20 | 0:39a545e08ccd | 390 | |
vic20 | 0:39a545e08ccd | 391 | // Calculates available transize |
vic20 | 0:39a545e08ccd | 392 | static inline uint16_t tranBuffSize() |
vic20 | 0:39a545e08ccd | 393 | { |
vic20 | 0:39a545e08ccd | 394 | uint16_t size; |
vic20 | 0:39a545e08ccd | 395 | |
vic20 | 0:39a545e08ccd | 396 | size = BSIZE - w_s - w_s2; |
vic20 | 0:39a545e08ccd | 397 | return size; |
vic20 | 0:39a545e08ccd | 398 | } |
vic20 | 0:39a545e08ccd | 399 | |
vic20 | 0:39a545e08ccd | 400 | // Calculates available wave 2 buff size |
vic20 | 0:39a545e08ccd | 401 | static inline uint16_t wave2buffSize() |
vic20 | 0:39a545e08ccd | 402 | { |
vic20 | 0:39a545e08ccd | 403 | uint16_t size; |
vic20 | 0:39a545e08ccd | 404 | |
vic20 | 0:39a545e08ccd | 405 | size = BSIZE - w_s; |
vic20 | 0:39a545e08ccd | 406 | return size; |
vic20 | 0:39a545e08ccd | 407 | } |
vic20 | 0:39a545e08ccd | 408 | |
vic20 | 0:39a545e08ccd | 409 | // Implements command 'R' |
vic20 | 0:39a545e08ccd | 410 | // Sets the sample period time |
vic20 | 0:39a545e08ccd | 411 | void setSampleTime() |
vic20 | 0:39a545e08ccd | 412 | { |
vic20 | 0:39a545e08ccd | 413 | //Get sample time |
vic20 | 0:39a545e08ccd | 414 | stime = getFloat(); |
vic20 | 0:39a545e08ccd | 415 | |
vic20 | 0:39a545e08ccd | 416 | // End of message, check CRC |
vic20 | 0:39a545e08ccd | 417 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 418 | |
vic20 | 0:39a545e08ccd | 419 | // Check limits |
vic20 | 0:39a545e08ccd | 420 | if ((stime < MIN_STIME) || (stime > MAX_STIME)) |
vic20 | 0:39a545e08ccd | 421 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 422 | else |
vic20 | 0:39a545e08ccd | 423 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 424 | |
vic20 | 0:39a545e08ccd | 425 | // End of message |
vic20 | 0:39a545e08ccd | 426 | sendCRC(); |
vic20 | 0:39a545e08ccd | 427 | } |
vic20 | 0:39a545e08ccd | 428 | |
vic20 | 0:39a545e08ccd | 429 | // Implements command 'S' |
vic20 | 0:39a545e08ccd | 430 | // Configure storage |
vic20 | 0:39a545e08ccd | 431 | void setStorage() |
vic20 | 0:39a545e08ccd | 432 | { |
vic20 | 0:39a545e08ccd | 433 | int sample_size,size; |
vic20 | 0:39a545e08ccd | 434 | int error = 0; |
vic20 | 0:39a545e08ccd | 435 | |
vic20 | 0:39a545e08ccd | 436 | // Get number of analog inputs |
vic20 | 0:39a545e08ccd | 437 | n_ai = getByte(); |
vic20 | 0:39a545e08ccd | 438 | if (n_ai > 4) error = 1; |
vic20 | 0:39a545e08ccd | 439 | |
vic20 | 0:39a545e08ccd | 440 | // Get number of digital inputs |
vic20 | 0:39a545e08ccd | 441 | // Not implemented yet |
vic20 | 0:39a545e08ccd | 442 | n_di = getByte(); |
vic20 | 0:39a545e08ccd | 443 | if (n_di != 0) error = 1; |
vic20 | 0:39a545e08ccd | 444 | |
vic20 | 0:39a545e08ccd | 445 | // Get the number of samples |
vic20 | 0:39a545e08ccd | 446 | n_s = getU16(); |
vic20 | 0:39a545e08ccd | 447 | |
vic20 | 0:39a545e08ccd | 448 | // End of message, check CRC |
vic20 | 0:39a545e08ccd | 449 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 450 | |
vic20 | 0:39a545e08ccd | 451 | // Check if it fits the buffer |
vic20 | 0:39a545e08ccd | 452 | if (n_di) |
vic20 | 0:39a545e08ccd | 453 | sample_size = n_ai+1; |
vic20 | 0:39a545e08ccd | 454 | else |
vic20 | 0:39a545e08ccd | 455 | sample_size = n_ai; |
vic20 | 0:39a545e08ccd | 456 | |
vic20 | 0:39a545e08ccd | 457 | size = n_s*sample_size; |
vic20 | 0:39a545e08ccd | 458 | if (size > tranBuffSize()) error = 1; |
vic20 | 0:39a545e08ccd | 459 | |
vic20 | 0:39a545e08ccd | 460 | // Response depending on errors |
vic20 | 0:39a545e08ccd | 461 | if (error) |
vic20 | 0:39a545e08ccd | 462 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 463 | else |
vic20 | 0:39a545e08ccd | 464 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 465 | |
vic20 | 0:39a545e08ccd | 466 | // End of message |
vic20 | 0:39a545e08ccd | 467 | sendCRC(); |
vic20 | 0:39a545e08ccd | 468 | } |
vic20 | 0:39a545e08ccd | 469 | |
vic20 | 0:39a545e08ccd | 470 | // Store analog inputs in circular buffer |
vic20 | 0:39a545e08ccd | 471 | static inline int storeAnalog() |
vic20 | 0:39a545e08ccd | 472 | { |
vic20 | 0:39a545e08ccd | 473 | int a1; |
vic20 | 0:39a545e08ccd | 474 | |
vic20 | 0:39a545e08ccd | 475 | a1 = ain1.read_u16(); |
vic20 | 0:39a545e08ccd | 476 | |
vic20 | 0:39a545e08ccd | 477 | if (n_ai >= 1) tranBuff[inBuffPos++]=a1; |
vic20 | 0:39a545e08ccd | 478 | if (n_ai >= 2) tranBuff[inBuffPos++]=ain2.read_u16(); |
vic20 | 0:39a545e08ccd | 479 | if (n_ai >= 3) tranBuff[inBuffPos++]=ain3.read_u16(); |
vic20 | 0:39a545e08ccd | 480 | if (n_ai >= 4) tranBuff[inBuffPos++]=ain4.read_u16(); |
vic20 | 0:39a545e08ccd | 481 | |
vic20 | 0:39a545e08ccd | 482 | if (inBuffPos == currentBsize) inBuffPos = 0; |
vic20 | 0:39a545e08ccd | 483 | |
vic20 | 0:39a545e08ccd | 484 | return a1; |
vic20 | 0:39a545e08ccd | 485 | } |
vic20 | 0:39a545e08ccd | 486 | |
vic20 | 0:39a545e08ccd | 487 | // Dumps the input buffer on serial |
vic20 | 0:39a545e08ccd | 488 | void dumpInBuffer() |
vic20 | 0:39a545e08ccd | 489 | { |
vic20 | 0:39a545e08ccd | 490 | int ia,is; |
vic20 | 0:39a545e08ccd | 491 | |
vic20 | 0:39a545e08ccd | 492 | // Response code |
vic20 | 1:d81bef65eece | 493 | if (halt) |
vic20 | 1:d81bef65eece | 494 | { |
vic20 | 1:d81bef65eece | 495 | sendByte(TRAN_HALT); |
vic20 | 1:d81bef65eece | 496 | return; |
vic20 | 1:d81bef65eece | 497 | } |
vic20 | 1:d81bef65eece | 498 | |
vic20 | 0:39a545e08ccd | 499 | if (overrun_error) |
vic20 | 0:39a545e08ccd | 500 | { |
vic20 | 0:39a545e08ccd | 501 | sendByte(TRAN_OVERRUN); |
vic20 | 0:39a545e08ccd | 502 | return; |
vic20 | 0:39a545e08ccd | 503 | } |
vic20 | 0:39a545e08ccd | 504 | else |
vic20 | 0:39a545e08ccd | 505 | sendByte(TRAN_OK); |
vic20 | 0:39a545e08ccd | 506 | |
vic20 | 0:39a545e08ccd | 507 | sendByte(n_ai); // Number of analog |
vic20 | 0:39a545e08ccd | 508 | sendByte(n_di); // Number of digital (always zero) |
vic20 | 0:39a545e08ccd | 509 | sendU16(n_s); // Number of samples |
vic20 | 0:39a545e08ccd | 510 | |
vic20 | 0:39a545e08ccd | 511 | for(ia=0;ia<n_ai;ia++) // For every analog input |
vic20 | 0:39a545e08ccd | 512 | for(is=0;is<n_s;is++) // For every sample |
vic20 | 0:39a545e08ccd | 513 | sendU16(tranBuff[is*n_ai+ia]); // Send it |
vic20 | 0:39a545e08ccd | 514 | } |
vic20 | 0:39a545e08ccd | 515 | |
vic20 | 0:39a545e08ccd | 516 | // Dumps the input buffer on serial |
vic20 | 0:39a545e08ccd | 517 | // Overrides the nimber of analog channels and sets it to 1 |
vic20 | 0:39a545e08ccd | 518 | void dumpInSingleBuffer() |
vic20 | 0:39a545e08ccd | 519 | { |
vic20 | 0:39a545e08ccd | 520 | int is; |
vic20 | 0:39a545e08ccd | 521 | |
vic20 | 0:39a545e08ccd | 522 | // Response code |
vic20 | 1:d81bef65eece | 523 | if (halt) |
vic20 | 1:d81bef65eece | 524 | { |
vic20 | 1:d81bef65eece | 525 | sendByte(TRAN_HALT); |
vic20 | 1:d81bef65eece | 526 | return; |
vic20 | 1:d81bef65eece | 527 | } |
vic20 | 1:d81bef65eece | 528 | |
vic20 | 0:39a545e08ccd | 529 | if (overrun_error) |
vic20 | 0:39a545e08ccd | 530 | { |
vic20 | 0:39a545e08ccd | 531 | sendByte(TRAN_OVERRUN); |
vic20 | 0:39a545e08ccd | 532 | return; |
vic20 | 0:39a545e08ccd | 533 | } |
vic20 | 0:39a545e08ccd | 534 | else |
vic20 | 0:39a545e08ccd | 535 | sendByte(TRAN_OK); |
vic20 | 0:39a545e08ccd | 536 | |
vic20 | 0:39a545e08ccd | 537 | sendByte(1); // Number of analog is 1 |
vic20 | 0:39a545e08ccd | 538 | sendByte(n_di); // Number of digital (always zero) |
vic20 | 0:39a545e08ccd | 539 | sendU16(n_s); // Number of samples |
vic20 | 0:39a545e08ccd | 540 | |
vic20 | 0:39a545e08ccd | 541 | for(is=0;is<n_s;is++) // For every sample |
vic20 | 0:39a545e08ccd | 542 | sendU16(tranBuff[is]); // Send it |
vic20 | 0:39a545e08ccd | 543 | } |
vic20 | 0:39a545e08ccd | 544 | |
vic20 | 0:39a545e08ccd | 545 | /********************* ASYNC READ ***************************/ |
vic20 | 0:39a545e08ccd | 546 | |
vic20 | 0:39a545e08ccd | 547 | // Hardware profiling operation (if enabled) |
vic20 | 0:39a545e08ccd | 548 | // PRO1 line high during ISR |
vic20 | 0:39a545e08ccd | 549 | // PRO2 line mimics overrun variable |
vic20 | 0:39a545e08ccd | 550 | |
vic20 | 0:39a545e08ccd | 551 | // ISR for the asyncRead function |
vic20 | 0:39a545e08ccd | 552 | void asyncReadISR() |
vic20 | 0:39a545e08ccd | 553 | { |
vic20 | 0:39a545e08ccd | 554 | PRO1_SET // Profiling |
vic20 | 0:39a545e08ccd | 555 | |
vic20 | 0:39a545e08ccd | 556 | // Store analog data |
vic20 | 0:39a545e08ccd | 557 | storeAnalog(); |
vic20 | 0:39a545e08ccd | 558 | |
vic20 | 0:39a545e08ccd | 559 | // Increase sample |
vic20 | 0:39a545e08ccd | 560 | samples++; |
vic20 | 0:39a545e08ccd | 561 | |
vic20 | 0:39a545e08ccd | 562 | // Check if we should end |
vic20 | 0:39a545e08ccd | 563 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 564 | { |
vic20 | 0:39a545e08ccd | 565 | // Disable ticker |
vic20 | 0:39a545e08ccd | 566 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 567 | // Signal end |
vic20 | 0:39a545e08ccd | 568 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 569 | PRO1_CLEAR // Profiling |
vic20 | 0:39a545e08ccd | 570 | return; |
vic20 | 0:39a545e08ccd | 571 | } |
vic20 | 0:39a545e08ccd | 572 | |
vic20 | 1:d81bef65eece | 573 | // Check for halt |
vic20 | 1:d81bef65eece | 574 | if (halt) |
vic20 | 1:d81bef65eece | 575 | { |
vic20 | 1:d81bef65eece | 576 | // Disable ticker |
vic20 | 1:d81bef65eece | 577 | ticR.detach(); |
vic20 | 1:d81bef65eece | 578 | // Signal end |
vic20 | 1:d81bef65eece | 579 | endTicker = 1; |
vic20 | 1:d81bef65eece | 580 | PRO1_CLEAR // Profiling |
vic20 | 1:d81bef65eece | 581 | } |
vic20 | 1:d81bef65eece | 582 | |
vic20 | 0:39a545e08ccd | 583 | // Check for overrun |
vic20 | 0:39a545e08ccd | 584 | if (overrun) |
vic20 | 0:39a545e08ccd | 585 | { |
vic20 | 0:39a545e08ccd | 586 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 587 | } |
vic20 | 0:39a545e08ccd | 588 | |
vic20 | 0:39a545e08ccd | 589 | overrun = 1; |
vic20 | 0:39a545e08ccd | 590 | |
vic20 | 0:39a545e08ccd | 591 | PRO2_SET // Profiling |
vic20 | 0:39a545e08ccd | 592 | PRO1_CLEAR |
vic20 | 0:39a545e08ccd | 593 | } |
vic20 | 0:39a545e08ccd | 594 | |
vic20 | 1:d81bef65eece | 595 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 596 | |
vic20 | 0:39a545e08ccd | 597 | // ISR for the asyncRead function |
vic20 | 0:39a545e08ccd | 598 | // Optimized timing when only reading one input |
vic20 | 0:39a545e08ccd | 599 | // Used only for one input and stime < 25us |
vic20 | 0:39a545e08ccd | 600 | void asyncReadSingleISR() |
vic20 | 0:39a545e08ccd | 601 | { |
vic20 | 0:39a545e08ccd | 602 | PRO1_SET // Profiling |
vic20 | 0:39a545e08ccd | 603 | |
vic20 | 0:39a545e08ccd | 604 | // Direct access to ADC registers |
vic20 | 0:39a545e08ccd | 605 | ADC1->CR |= ADC_CR_ADSTART; |
vic20 | 0:39a545e08ccd | 606 | while (!(ADC1->ISR & ADC_ISR_EOC)); |
vic20 | 0:39a545e08ccd | 607 | tranBuff[inBuffPos++] = (ADC1->DR)<<4; |
vic20 | 0:39a545e08ccd | 608 | |
vic20 | 0:39a545e08ccd | 609 | if (inBuffPos == currentBsize) inBuffPos = 0; |
vic20 | 0:39a545e08ccd | 610 | |
vic20 | 0:39a545e08ccd | 611 | // Increase sample |
vic20 | 0:39a545e08ccd | 612 | samples++; |
vic20 | 0:39a545e08ccd | 613 | |
vic20 | 0:39a545e08ccd | 614 | // Check if we should end |
vic20 | 0:39a545e08ccd | 615 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 616 | { |
vic20 | 0:39a545e08ccd | 617 | // Disable ticker |
vic20 | 0:39a545e08ccd | 618 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 619 | // Signal end |
vic20 | 0:39a545e08ccd | 620 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 621 | PRO1_CLEAR // Profiling |
vic20 | 0:39a545e08ccd | 622 | return; |
vic20 | 0:39a545e08ccd | 623 | } |
vic20 | 1:d81bef65eece | 624 | |
vic20 | 1:d81bef65eece | 625 | // Check for halt |
vic20 | 1:d81bef65eece | 626 | if (halt) |
vic20 | 1:d81bef65eece | 627 | { |
vic20 | 1:d81bef65eece | 628 | // Disable ticker |
vic20 | 1:d81bef65eece | 629 | ticR.detach(); |
vic20 | 1:d81bef65eece | 630 | // Signal end |
vic20 | 1:d81bef65eece | 631 | endTicker = 1; |
vic20 | 1:d81bef65eece | 632 | PRO1_CLEAR // Profiling |
vic20 | 1:d81bef65eece | 633 | } |
vic20 | 0:39a545e08ccd | 634 | |
vic20 | 0:39a545e08ccd | 635 | // Check for overrun |
vic20 | 0:39a545e08ccd | 636 | if (overrun) |
vic20 | 0:39a545e08ccd | 637 | { |
vic20 | 0:39a545e08ccd | 638 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 639 | } |
vic20 | 0:39a545e08ccd | 640 | overrun = 1; |
vic20 | 0:39a545e08ccd | 641 | |
vic20 | 0:39a545e08ccd | 642 | PRO2_SET // Profiling |
vic20 | 0:39a545e08ccd | 643 | PRO1_CLEAR |
vic20 | 1:d81bef65eece | 644 | } |
vic20 | 1:d81bef65eece | 645 | |
vic20 | 1:d81bef65eece | 646 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 647 | |
vic20 | 0:39a545e08ccd | 648 | // Implements command 'Y' |
vic20 | 0:39a545e08ccd | 649 | // Async read |
vic20 | 0:39a545e08ccd | 650 | // This command don't get any parameter |
vic20 | 0:39a545e08ccd | 651 | void asyncRead() |
vic20 | 0:39a545e08ccd | 652 | { |
vic20 | 0:39a545e08ccd | 653 | PRO1_CLEAR // Reset profiling lines |
vic20 | 0:39a545e08ccd | 654 | PRO2_CLEAR |
vic20 | 0:39a545e08ccd | 655 | |
vic20 | 0:39a545e08ccd | 656 | // Check of CRC |
vic20 | 0:39a545e08ccd | 657 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 658 | |
vic20 | 0:39a545e08ccd | 659 | // Send ACK to command |
vic20 | 0:39a545e08ccd | 660 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 661 | |
vic20 | 0:39a545e08ccd | 662 | // Configure ticker ISR |
vic20 | 0:39a545e08ccd | 663 | samples = 0; // Number of processed samples |
vic20 | 0:39a545e08ccd | 664 | inBuffPos = 0; // Current buffer position |
vic20 | 0:39a545e08ccd | 665 | endTicker = 0; // Ticker has not ended |
vic20 | 0:39a545e08ccd | 666 | |
vic20 | 0:39a545e08ccd | 667 | currentBsize = n_ai * n_s; // Current size for buffer |
vic20 | 0:39a545e08ccd | 668 | |
vic20 | 0:39a545e08ccd | 669 | // Clear overrun variables |
vic20 | 0:39a545e08ccd | 670 | overrun_error = 0; |
vic20 | 0:39a545e08ccd | 671 | overrun = 0; |
vic20 | 0:39a545e08ccd | 672 | PRO2_CLEAR // Profiling |
vic20 | 0:39a545e08ccd | 673 | |
vic20 | 1:d81bef65eece | 674 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 675 | |
vic20 | 0:39a545e08ccd | 676 | // Check if we only read one channel and stime is less than 41us |
vic20 | 0:39a545e08ccd | 677 | if ((n_ai==1)&&(stime<25e-6f)) |
vic20 | 0:39a545e08ccd | 678 | { |
vic20 | 0:39a545e08ccd | 679 | // Perform a dummy read |
vic20 | 0:39a545e08ccd | 680 | ain1.read_u16(); |
vic20 | 0:39a545e08ccd | 681 | // Programs the ticker for one input optimized ISR version |
vic20 | 0:39a545e08ccd | 682 | ticR.attach(&asyncReadSingleISR,stime); |
vic20 | 0:39a545e08ccd | 683 | } |
vic20 | 0:39a545e08ccd | 684 | else |
vic20 | 0:39a545e08ccd | 685 | { |
vic20 | 0:39a545e08ccd | 686 | // Programs the ticker for several inputs |
vic20 | 0:39a545e08ccd | 687 | ticR.attach(&asyncReadISR,stime); |
vic20 | 0:39a545e08ccd | 688 | } |
vic20 | 0:39a545e08ccd | 689 | |
vic20 | 1:d81bef65eece | 690 | #else // No FAST_ADC ISR |
vic20 | 1:d81bef65eece | 691 | |
vic20 | 1:d81bef65eece | 692 | // Programs the ticker for several inputs |
vic20 | 1:d81bef65eece | 693 | ticR.attach(&asyncReadISR,stime); |
vic20 | 1:d81bef65eece | 694 | |
vic20 | 1:d81bef65eece | 695 | #endif //FAST_ADC |
vic20 | 1:d81bef65eece | 696 | |
vic20 | 0:39a545e08ccd | 697 | // Wait till end |
vic20 | 0:39a545e08ccd | 698 | while (!endTicker) { overrun = 0; PRO2_CLEAR } |
vic20 | 0:39a545e08ccd | 699 | |
vic20 | 0:39a545e08ccd | 700 | // Return data |
vic20 | 0:39a545e08ccd | 701 | dumpInBuffer(); // Dump data |
vic20 | 0:39a545e08ccd | 702 | |
vic20 | 0:39a545e08ccd | 703 | sendCRC(); // End of Tx |
vic20 | 0:39a545e08ccd | 704 | } |
vic20 | 0:39a545e08ccd | 705 | |
vic20 | 0:39a545e08ccd | 706 | /********************* TRIGGERED READ ***************************/ |
vic20 | 0:39a545e08ccd | 707 | |
vic20 | 0:39a545e08ccd | 708 | // Hardware profiling operation (if enabled) |
vic20 | 0:39a545e08ccd | 709 | // PRO1 line high during ISR |
vic20 | 0:39a545e08ccd | 710 | // PRO2 line mimics overrun variable |
vic20 | 0:39a545e08ccd | 711 | |
vic20 | 0:39a545e08ccd | 712 | // Dumps the input buffer on serial for triggered caputure |
vic20 | 0:39a545e08ccd | 713 | void dumpTriggeredInBuffer() |
vic20 | 0:39a545e08ccd | 714 | { |
vic20 | 0:39a545e08ccd | 715 | int ia,is,pos,sample,first; |
vic20 | 0:39a545e08ccd | 716 | |
vic20 | 0:39a545e08ccd | 717 | presamples = n_s/2; // Number of samples before trigger |
vic20 | 0:39a545e08ccd | 718 | postsamples = n_s - presamples; // Number of samples after trigger |
vic20 | 0:39a545e08ccd | 719 | |
vic20 | 0:39a545e08ccd | 720 | // Response code |
vic20 | 1:d81bef65eece | 721 | if (halt) |
vic20 | 1:d81bef65eece | 722 | { |
vic20 | 1:d81bef65eece | 723 | sendByte(TRAN_HALT); |
vic20 | 1:d81bef65eece | 724 | return; |
vic20 | 1:d81bef65eece | 725 | } |
vic20 | 1:d81bef65eece | 726 | |
vic20 | 0:39a545e08ccd | 727 | if (overrun_error) |
vic20 | 0:39a545e08ccd | 728 | { |
vic20 | 0:39a545e08ccd | 729 | sendByte(TRAN_OVERRUN); |
vic20 | 0:39a545e08ccd | 730 | return; |
vic20 | 0:39a545e08ccd | 731 | } |
vic20 | 0:39a545e08ccd | 732 | |
vic20 | 0:39a545e08ccd | 733 | if (timeout_error) |
vic20 | 0:39a545e08ccd | 734 | { |
vic20 | 0:39a545e08ccd | 735 | sendByte(TRAN_TIMEOUT); |
vic20 | 0:39a545e08ccd | 736 | return; |
vic20 | 0:39a545e08ccd | 737 | } |
vic20 | 0:39a545e08ccd | 738 | |
vic20 | 0:39a545e08ccd | 739 | sendByte(TRAN_OK); |
vic20 | 0:39a545e08ccd | 740 | |
vic20 | 0:39a545e08ccd | 741 | sendByte(n_ai); // Number of analog |
vic20 | 0:39a545e08ccd | 742 | sendByte(n_di); // Number of digital (always zero) |
vic20 | 0:39a545e08ccd | 743 | sendU16(n_s); // Number of samples |
vic20 | 0:39a545e08ccd | 744 | |
vic20 | 0:39a545e08ccd | 745 | // First sample to send |
vic20 | 0:39a545e08ccd | 746 | first = (triggerSample - presamples + n_s)%n_s; |
vic20 | 0:39a545e08ccd | 747 | |
vic20 | 0:39a545e08ccd | 748 | for(ia=0;ia<n_ai;ia++) // For every analog input |
vic20 | 0:39a545e08ccd | 749 | for(is=0;is<n_s;is++) // For every sample |
vic20 | 0:39a545e08ccd | 750 | { |
vic20 | 0:39a545e08ccd | 751 | sample = (first+is)%n_s; // Calculate sample |
vic20 | 0:39a545e08ccd | 752 | pos = sample*n_ai+ia; // Calculate buff position |
vic20 | 0:39a545e08ccd | 753 | sendU16(tranBuff[pos]); // Send it |
vic20 | 0:39a545e08ccd | 754 | } |
vic20 | 0:39a545e08ccd | 755 | } |
vic20 | 0:39a545e08ccd | 756 | |
vic20 | 0:39a545e08ccd | 757 | // ISR for the triggeredRead function |
vic20 | 0:39a545e08ccd | 758 | void triggeredReadISR() |
vic20 | 0:39a545e08ccd | 759 | { |
vic20 | 0:39a545e08ccd | 760 | int a1; |
vic20 | 0:39a545e08ccd | 761 | |
vic20 | 0:39a545e08ccd | 762 | PRO1_SET |
vic20 | 0:39a545e08ccd | 763 | |
vic20 | 0:39a545e08ccd | 764 | // Store analog data |
vic20 | 0:39a545e08ccd | 765 | a1 = storeAnalog(); |
vic20 | 0:39a545e08ccd | 766 | |
vic20 | 0:39a545e08ccd | 767 | // Increase sample |
vic20 | 0:39a545e08ccd | 768 | samples++; |
vic20 | 0:39a545e08ccd | 769 | if (samples == n_s) samples = 0; |
vic20 | 0:39a545e08ccd | 770 | |
vic20 | 0:39a545e08ccd | 771 | // Decrease timeout |
vic20 | 0:39a545e08ccd | 772 | timeOut--; |
vic20 | 0:39a545e08ccd | 773 | |
vic20 | 1:d81bef65eece | 774 | // Check halt |
vic20 | 1:d81bef65eece | 775 | if (halt) |
vic20 | 1:d81bef65eece | 776 | { |
vic20 | 1:d81bef65eece | 777 | // Disable ticker |
vic20 | 1:d81bef65eece | 778 | ticR.detach(); |
vic20 | 1:d81bef65eece | 779 | // Signal end |
vic20 | 1:d81bef65eece | 780 | endTicker = 1; |
vic20 | 1:d81bef65eece | 781 | return; |
vic20 | 1:d81bef65eece | 782 | } |
vic20 | 1:d81bef65eece | 783 | |
vic20 | 0:39a545e08ccd | 784 | // Check phase |
vic20 | 0:39a545e08ccd | 785 | switch(samplePhase) |
vic20 | 0:39a545e08ccd | 786 | { |
vic20 | 0:39a545e08ccd | 787 | case 0: // Prefill of the buffer |
vic20 | 0:39a545e08ccd | 788 | presamples--; |
vic20 | 0:39a545e08ccd | 789 | if (!presamples) samplePhase = 1; |
vic20 | 0:39a545e08ccd | 790 | if (!timeOut) |
vic20 | 0:39a545e08ccd | 791 | { |
vic20 | 0:39a545e08ccd | 792 | // Set error |
vic20 | 0:39a545e08ccd | 793 | timeout_error = 1; |
vic20 | 0:39a545e08ccd | 794 | // Disable ticker |
vic20 | 0:39a545e08ccd | 795 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 796 | // Signal end |
vic20 | 0:39a545e08ccd | 797 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 798 | } |
vic20 | 0:39a545e08ccd | 799 | break; |
vic20 | 0:39a545e08ccd | 800 | case 1: // Wait for trigger precondition |
vic20 | 0:39a545e08ccd | 801 | if (triggerMode == 0) // Rise |
vic20 | 0:39a545e08ccd | 802 | if (a1 < trigger) samplePhase = 2; |
vic20 | 0:39a545e08ccd | 803 | if (triggerMode == 1) // Fall |
vic20 | 0:39a545e08ccd | 804 | if (a1 > trigger) samplePhase = 2; |
vic20 | 0:39a545e08ccd | 805 | if (!timeOut) |
vic20 | 0:39a545e08ccd | 806 | { |
vic20 | 0:39a545e08ccd | 807 | // Set error |
vic20 | 0:39a545e08ccd | 808 | timeout_error = 1; |
vic20 | 0:39a545e08ccd | 809 | // Disable ticker |
vic20 | 0:39a545e08ccd | 810 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 811 | // Signal end |
vic20 | 0:39a545e08ccd | 812 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 813 | } |
vic20 | 0:39a545e08ccd | 814 | break; |
vic20 | 0:39a545e08ccd | 815 | case 2: // Wait for trigger postcondition |
vic20 | 0:39a545e08ccd | 816 | if (triggerMode == 0) // Rise |
vic20 | 0:39a545e08ccd | 817 | if (a1 > trigger) |
vic20 | 0:39a545e08ccd | 818 | { |
vic20 | 0:39a545e08ccd | 819 | samplePhase = 3; |
vic20 | 0:39a545e08ccd | 820 | triggerSample = samples; |
vic20 | 0:39a545e08ccd | 821 | } |
vic20 | 0:39a545e08ccd | 822 | if (triggerMode == 1) // Fall |
vic20 | 0:39a545e08ccd | 823 | if (a1 < trigger) |
vic20 | 0:39a545e08ccd | 824 | { |
vic20 | 0:39a545e08ccd | 825 | samplePhase = 3; |
vic20 | 0:39a545e08ccd | 826 | triggerSample = samples; |
vic20 | 0:39a545e08ccd | 827 | } |
vic20 | 0:39a545e08ccd | 828 | if (!timeOut) |
vic20 | 0:39a545e08ccd | 829 | { |
vic20 | 0:39a545e08ccd | 830 | // Set error |
vic20 | 0:39a545e08ccd | 831 | timeout_error = 1; |
vic20 | 0:39a545e08ccd | 832 | // Disable ticker |
vic20 | 0:39a545e08ccd | 833 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 834 | // Signal end |
vic20 | 0:39a545e08ccd | 835 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 836 | } |
vic20 | 0:39a545e08ccd | 837 | break; |
vic20 | 0:39a545e08ccd | 838 | case 3: // Capture after trigger |
vic20 | 0:39a545e08ccd | 839 | postsamples--; |
vic20 | 0:39a545e08ccd | 840 | if (!postsamples) |
vic20 | 0:39a545e08ccd | 841 | { |
vic20 | 0:39a545e08ccd | 842 | // Disable ticker |
vic20 | 0:39a545e08ccd | 843 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 844 | // Signal end |
vic20 | 0:39a545e08ccd | 845 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 846 | } |
vic20 | 0:39a545e08ccd | 847 | break; |
vic20 | 0:39a545e08ccd | 848 | } |
vic20 | 0:39a545e08ccd | 849 | |
vic20 | 0:39a545e08ccd | 850 | // Check for overrun |
vic20 | 0:39a545e08ccd | 851 | if (overrun) |
vic20 | 0:39a545e08ccd | 852 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 853 | |
vic20 | 0:39a545e08ccd | 854 | overrun = 1; |
vic20 | 0:39a545e08ccd | 855 | |
vic20 | 0:39a545e08ccd | 856 | PRO2_SET |
vic20 | 0:39a545e08ccd | 857 | PRO1_CLEAR |
vic20 | 0:39a545e08ccd | 858 | } |
vic20 | 0:39a545e08ccd | 859 | |
vic20 | 1:d81bef65eece | 860 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 861 | |
vic20 | 0:39a545e08ccd | 862 | // ISR for the triggeredRead function |
vic20 | 0:39a545e08ccd | 863 | // Version optimized for only one channel |
vic20 | 0:39a545e08ccd | 864 | // Only used for single channel and stime < 30us |
vic20 | 0:39a545e08ccd | 865 | void triggeredReadSingleISR() |
vic20 | 0:39a545e08ccd | 866 | { |
vic20 | 0:39a545e08ccd | 867 | int a1; |
vic20 | 0:39a545e08ccd | 868 | |
vic20 | 0:39a545e08ccd | 869 | PRO1_SET |
vic20 | 0:39a545e08ccd | 870 | |
vic20 | 0:39a545e08ccd | 871 | // Direct access to ADC registers |
vic20 | 0:39a545e08ccd | 872 | ADC1->CR |= ADC_CR_ADSTART; |
vic20 | 0:39a545e08ccd | 873 | while (!(ADC1->ISR & ADC_ISR_EOC)); |
vic20 | 0:39a545e08ccd | 874 | a1=(ADC1->DR)<<4; |
vic20 | 0:39a545e08ccd | 875 | tranBuff[inBuffPos++]=a1; |
vic20 | 0:39a545e08ccd | 876 | |
vic20 | 0:39a545e08ccd | 877 | if (inBuffPos == currentBsize) inBuffPos = 0; |
vic20 | 0:39a545e08ccd | 878 | |
vic20 | 0:39a545e08ccd | 879 | // Increase sample |
vic20 | 0:39a545e08ccd | 880 | samples++; |
vic20 | 0:39a545e08ccd | 881 | if (samples == n_s) samples = 0; |
vic20 | 0:39a545e08ccd | 882 | |
vic20 | 0:39a545e08ccd | 883 | // Decrease timeout |
vic20 | 0:39a545e08ccd | 884 | timeOut--; |
vic20 | 0:39a545e08ccd | 885 | |
vic20 | 1:d81bef65eece | 886 | // Check halt |
vic20 | 1:d81bef65eece | 887 | if (halt) |
vic20 | 1:d81bef65eece | 888 | { |
vic20 | 1:d81bef65eece | 889 | // Disable ticker |
vic20 | 1:d81bef65eece | 890 | ticR.detach(); |
vic20 | 1:d81bef65eece | 891 | // Signal end |
vic20 | 1:d81bef65eece | 892 | endTicker = 1; |
vic20 | 1:d81bef65eece | 893 | return; |
vic20 | 1:d81bef65eece | 894 | } |
vic20 | 1:d81bef65eece | 895 | |
vic20 | 0:39a545e08ccd | 896 | // Check phase |
vic20 | 0:39a545e08ccd | 897 | switch(samplePhase) |
vic20 | 0:39a545e08ccd | 898 | { |
vic20 | 0:39a545e08ccd | 899 | case 0: // Prefill of the buffer |
vic20 | 0:39a545e08ccd | 900 | presamples--; |
vic20 | 0:39a545e08ccd | 901 | if (!presamples) samplePhase = 1; |
vic20 | 0:39a545e08ccd | 902 | if (!timeOut) |
vic20 | 0:39a545e08ccd | 903 | { |
vic20 | 0:39a545e08ccd | 904 | // Set error |
vic20 | 0:39a545e08ccd | 905 | timeout_error = 1; |
vic20 | 0:39a545e08ccd | 906 | // Disable ticker |
vic20 | 0:39a545e08ccd | 907 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 908 | // Signal end |
vic20 | 0:39a545e08ccd | 909 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 910 | } |
vic20 | 0:39a545e08ccd | 911 | break; |
vic20 | 0:39a545e08ccd | 912 | case 1: // Wait for trigger precondition |
vic20 | 0:39a545e08ccd | 913 | if (triggerMode == 0) // Rise |
vic20 | 0:39a545e08ccd | 914 | if (a1 < trigger) samplePhase = 2; |
vic20 | 0:39a545e08ccd | 915 | if (triggerMode == 1) // Fall |
vic20 | 0:39a545e08ccd | 916 | if (a1 > trigger) samplePhase = 2; |
vic20 | 0:39a545e08ccd | 917 | if (!timeOut) |
vic20 | 0:39a545e08ccd | 918 | { |
vic20 | 0:39a545e08ccd | 919 | // Set error |
vic20 | 0:39a545e08ccd | 920 | timeout_error = 1; |
vic20 | 0:39a545e08ccd | 921 | // Disable ticker |
vic20 | 0:39a545e08ccd | 922 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 923 | // Signal end |
vic20 | 0:39a545e08ccd | 924 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 925 | } |
vic20 | 0:39a545e08ccd | 926 | break; |
vic20 | 0:39a545e08ccd | 927 | case 2: // Wait for trigger postcondition |
vic20 | 0:39a545e08ccd | 928 | if (triggerMode == 0) // Rise |
vic20 | 0:39a545e08ccd | 929 | if (a1 > trigger) |
vic20 | 0:39a545e08ccd | 930 | { |
vic20 | 0:39a545e08ccd | 931 | samplePhase = 3; |
vic20 | 0:39a545e08ccd | 932 | triggerSample = samples; |
vic20 | 0:39a545e08ccd | 933 | } |
vic20 | 0:39a545e08ccd | 934 | if (triggerMode == 1) // Fall |
vic20 | 0:39a545e08ccd | 935 | if (a1 < trigger) |
vic20 | 0:39a545e08ccd | 936 | { |
vic20 | 0:39a545e08ccd | 937 | samplePhase = 3; |
vic20 | 0:39a545e08ccd | 938 | triggerSample = samples; |
vic20 | 0:39a545e08ccd | 939 | } |
vic20 | 0:39a545e08ccd | 940 | if (!timeOut) |
vic20 | 0:39a545e08ccd | 941 | { |
vic20 | 0:39a545e08ccd | 942 | // Set error |
vic20 | 0:39a545e08ccd | 943 | timeout_error = 1; |
vic20 | 0:39a545e08ccd | 944 | // Disable ticker |
vic20 | 0:39a545e08ccd | 945 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 946 | // Signal end |
vic20 | 0:39a545e08ccd | 947 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 948 | } |
vic20 | 0:39a545e08ccd | 949 | break; |
vic20 | 0:39a545e08ccd | 950 | case 3: // Capture after trigger |
vic20 | 0:39a545e08ccd | 951 | postsamples--; |
vic20 | 0:39a545e08ccd | 952 | if (!postsamples) |
vic20 | 0:39a545e08ccd | 953 | { |
vic20 | 0:39a545e08ccd | 954 | // Disable ticker |
vic20 | 0:39a545e08ccd | 955 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 956 | // Signal end |
vic20 | 0:39a545e08ccd | 957 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 958 | } |
vic20 | 0:39a545e08ccd | 959 | break; |
vic20 | 0:39a545e08ccd | 960 | } |
vic20 | 0:39a545e08ccd | 961 | |
vic20 | 0:39a545e08ccd | 962 | // Check for overrun |
vic20 | 0:39a545e08ccd | 963 | if (overrun) |
vic20 | 0:39a545e08ccd | 964 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 965 | |
vic20 | 0:39a545e08ccd | 966 | overrun = 1; |
vic20 | 0:39a545e08ccd | 967 | |
vic20 | 0:39a545e08ccd | 968 | PRO2_SET |
vic20 | 0:39a545e08ccd | 969 | PRO1_CLEAR |
vic20 | 0:39a545e08ccd | 970 | } |
vic20 | 0:39a545e08ccd | 971 | |
vic20 | 1:d81bef65eece | 972 | #endif //FAST_ADC |
vic20 | 1:d81bef65eece | 973 | |
vic20 | 0:39a545e08ccd | 974 | // Implements command 'G' |
vic20 | 0:39a545e08ccd | 975 | // Triggered read |
vic20 | 0:39a545e08ccd | 976 | void triggeredRead() |
vic20 | 0:39a545e08ccd | 977 | { |
vic20 | 0:39a545e08ccd | 978 | PRO1_CLEAR // Reset profiling lines |
vic20 | 0:39a545e08ccd | 979 | PRO2_CLEAR |
vic20 | 0:39a545e08ccd | 980 | |
vic20 | 0:39a545e08ccd | 981 | // Get trigger point |
vic20 | 0:39a545e08ccd | 982 | trigger = getU16(); |
vic20 | 0:39a545e08ccd | 983 | // Get trigger mode |
vic20 | 0:39a545e08ccd | 984 | triggerMode = getByte(); |
vic20 | 0:39a545e08ccd | 985 | // Get timeout in seconds |
vic20 | 0:39a545e08ccd | 986 | timeOut = getByte(); |
vic20 | 0:39a545e08ccd | 987 | |
vic20 | 0:39a545e08ccd | 988 | if (timeOut) |
vic20 | 0:39a545e08ccd | 989 | { |
vic20 | 0:39a545e08ccd | 990 | checkTimeOut=1; |
vic20 | 0:39a545e08ccd | 991 | // Convert to samples |
vic20 | 0:39a545e08ccd | 992 | timeOut=int(1.0*timeOut/stime); |
vic20 | 0:39a545e08ccd | 993 | } |
vic20 | 0:39a545e08ccd | 994 | else |
vic20 | 0:39a545e08ccd | 995 | checkTimeOut = 0; |
vic20 | 0:39a545e08ccd | 996 | |
vic20 | 0:39a545e08ccd | 997 | // Erase timeout error |
vic20 | 0:39a545e08ccd | 998 | timeout_error = 0; |
vic20 | 0:39a545e08ccd | 999 | |
vic20 | 0:39a545e08ccd | 1000 | // Check of CRC |
vic20 | 0:39a545e08ccd | 1001 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 1002 | |
vic20 | 0:39a545e08ccd | 1003 | // Check mode |
vic20 | 0:39a545e08ccd | 1004 | if ( (triggerMode != 0) && (triggerMode != 1) ) |
vic20 | 0:39a545e08ccd | 1005 | { |
vic20 | 0:39a545e08ccd | 1006 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 1007 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1008 | return; |
vic20 | 0:39a545e08ccd | 1009 | } |
vic20 | 0:39a545e08ccd | 1010 | |
vic20 | 0:39a545e08ccd | 1011 | // All ok |
vic20 | 0:39a545e08ccd | 1012 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 1013 | |
vic20 | 0:39a545e08ccd | 1014 | // Configure ticker ISR |
vic20 | 0:39a545e08ccd | 1015 | samples = 0; // Number of processed samples |
vic20 | 0:39a545e08ccd | 1016 | inBuffPos = 0; // Current buffer position |
vic20 | 0:39a545e08ccd | 1017 | endTicker = 0; // Ticker has not ended |
vic20 | 0:39a545e08ccd | 1018 | |
vic20 | 0:39a545e08ccd | 1019 | presamples = n_s/2; // Number of samples before trigger |
vic20 | 0:39a545e08ccd | 1020 | postsamples = n_s - presamples; // Number of samples after trigger |
vic20 | 0:39a545e08ccd | 1021 | currentBsize = n_ai * n_s; // Current size for buffer |
vic20 | 0:39a545e08ccd | 1022 | |
vic20 | 0:39a545e08ccd | 1023 | samplePhase = 0; // First phase: buffer prefill |
vic20 | 0:39a545e08ccd | 1024 | |
vic20 | 0:39a545e08ccd | 1025 | // Clear overrun variables |
vic20 | 0:39a545e08ccd | 1026 | overrun_error = 0; |
vic20 | 0:39a545e08ccd | 1027 | overrun = 0; |
vic20 | 0:39a545e08ccd | 1028 | |
vic20 | 1:d81bef65eece | 1029 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1030 | |
vic20 | 0:39a545e08ccd | 1031 | // Check if we only read one channel |
vic20 | 0:39a545e08ccd | 1032 | if ((n_ai==1)&&(stime<30e-6f)) |
vic20 | 0:39a545e08ccd | 1033 | { |
vic20 | 0:39a545e08ccd | 1034 | // Perform a dummy read |
vic20 | 0:39a545e08ccd | 1035 | ain1.read_u16(); |
vic20 | 0:39a545e08ccd | 1036 | // Programs the ticker for one input optimized ISR version |
vic20 | 0:39a545e08ccd | 1037 | ticR.attach(&triggeredReadSingleISR,stime); |
vic20 | 0:39a545e08ccd | 1038 | } |
vic20 | 0:39a545e08ccd | 1039 | else |
vic20 | 0:39a545e08ccd | 1040 | { |
vic20 | 0:39a545e08ccd | 1041 | // Programs the ticker for several inputs |
vic20 | 0:39a545e08ccd | 1042 | ticR.attach(&triggeredReadISR,stime); |
vic20 | 0:39a545e08ccd | 1043 | } |
vic20 | 1:d81bef65eece | 1044 | |
vic20 | 1:d81bef65eece | 1045 | #else // No FAST_ADC code |
vic20 | 1:d81bef65eece | 1046 | |
vic20 | 1:d81bef65eece | 1047 | // Programs the ticker for several inputs |
vic20 | 1:d81bef65eece | 1048 | ticR.attach(&triggeredReadISR,stime); |
vic20 | 1:d81bef65eece | 1049 | |
vic20 | 1:d81bef65eece | 1050 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1051 | |
vic20 | 0:39a545e08ccd | 1052 | // Wait till end |
vic20 | 0:39a545e08ccd | 1053 | while (!endTicker) { overrun = 0; PRO2_CLEAR } |
vic20 | 0:39a545e08ccd | 1054 | |
vic20 | 0:39a545e08ccd | 1055 | // Return data |
vic20 | 0:39a545e08ccd | 1056 | dumpTriggeredInBuffer(); // Dump data |
vic20 | 0:39a545e08ccd | 1057 | |
vic20 | 0:39a545e08ccd | 1058 | // Send CRC to end Tx |
vic20 | 0:39a545e08ccd | 1059 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1060 | } |
vic20 | 0:39a545e08ccd | 1061 | |
vic20 | 0:39a545e08ccd | 1062 | /********************* STEP RESPONSE ***************************/ |
vic20 | 0:39a545e08ccd | 1063 | |
vic20 | 0:39a545e08ccd | 1064 | // Hardware profiling operation (if enabled) |
vic20 | 0:39a545e08ccd | 1065 | // Not implemented yet |
vic20 | 0:39a545e08ccd | 1066 | |
vic20 | 0:39a545e08ccd | 1067 | // ISR for the stepResponse function |
vic20 | 0:39a545e08ccd | 1068 | void stepResponseISR() |
vic20 | 0:39a545e08ccd | 1069 | { |
vic20 | 0:39a545e08ccd | 1070 | // Store analog data |
vic20 | 0:39a545e08ccd | 1071 | storeAnalog(); |
vic20 | 0:39a545e08ccd | 1072 | |
vic20 | 0:39a545e08ccd | 1073 | // Increase sample |
vic20 | 0:39a545e08ccd | 1074 | samples++; |
vic20 | 0:39a545e08ccd | 1075 | |
vic20 | 0:39a545e08ccd | 1076 | // Check trigger position |
vic20 | 0:39a545e08ccd | 1077 | if (samples == triggerSample) aout1 = stepValue / MAX16F; |
vic20 | 0:39a545e08ccd | 1078 | |
vic20 | 1:d81bef65eece | 1079 | // Check halt |
vic20 | 1:d81bef65eece | 1080 | if (halt) |
vic20 | 1:d81bef65eece | 1081 | { |
vic20 | 1:d81bef65eece | 1082 | // Disable ticker |
vic20 | 1:d81bef65eece | 1083 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1084 | // Signal end |
vic20 | 1:d81bef65eece | 1085 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1086 | } |
vic20 | 1:d81bef65eece | 1087 | |
vic20 | 0:39a545e08ccd | 1088 | // Check if we should end |
vic20 | 0:39a545e08ccd | 1089 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 1090 | { |
vic20 | 0:39a545e08ccd | 1091 | // Disable ticker |
vic20 | 0:39a545e08ccd | 1092 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 1093 | // Signal end |
vic20 | 0:39a545e08ccd | 1094 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 1095 | } |
vic20 | 0:39a545e08ccd | 1096 | |
vic20 | 0:39a545e08ccd | 1097 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1098 | if (overrun) |
vic20 | 0:39a545e08ccd | 1099 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 1100 | |
vic20 | 0:39a545e08ccd | 1101 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1102 | } |
vic20 | 0:39a545e08ccd | 1103 | |
vic20 | 1:d81bef65eece | 1104 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1105 | |
vic20 | 1:d81bef65eece | 1106 | // ISR for the stepResponse function |
vic20 | 1:d81bef65eece | 1107 | // Time optimized version |
vic20 | 1:d81bef65eece | 1108 | // Only used for one channel and stime < 30us |
vic20 | 1:d81bef65eece | 1109 | void stepResponseSingleISR() |
vic20 | 0:39a545e08ccd | 1110 | { |
vic20 | 0:39a545e08ccd | 1111 | // Direct access to ADC registers |
vic20 | 0:39a545e08ccd | 1112 | ADC1->CR |= ADC_CR_ADSTART; |
vic20 | 0:39a545e08ccd | 1113 | while (!(ADC1->ISR & ADC_ISR_EOC)); |
vic20 | 0:39a545e08ccd | 1114 | tranBuff[inBuffPos++]=(ADC1->DR)<<4; |
vic20 | 0:39a545e08ccd | 1115 | |
vic20 | 0:39a545e08ccd | 1116 | if (inBuffPos == currentBsize) inBuffPos = 0; |
vic20 | 0:39a545e08ccd | 1117 | |
vic20 | 0:39a545e08ccd | 1118 | // Increase sample |
vic20 | 0:39a545e08ccd | 1119 | samples++; |
vic20 | 0:39a545e08ccd | 1120 | |
vic20 | 0:39a545e08ccd | 1121 | // Check trigger position |
vic20 | 0:39a545e08ccd | 1122 | if (samples == triggerSample) |
vic20 | 0:39a545e08ccd | 1123 | DAC->DHR12R1 = (stepValue>>4); |
vic20 | 0:39a545e08ccd | 1124 | |
vic20 | 1:d81bef65eece | 1125 | // Check halt |
vic20 | 1:d81bef65eece | 1126 | if (halt) |
vic20 | 1:d81bef65eece | 1127 | { |
vic20 | 1:d81bef65eece | 1128 | // Disable ticker |
vic20 | 1:d81bef65eece | 1129 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1130 | // Signal end |
vic20 | 1:d81bef65eece | 1131 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1132 | } |
vic20 | 1:d81bef65eece | 1133 | |
vic20 | 0:39a545e08ccd | 1134 | // Check if we should end |
vic20 | 0:39a545e08ccd | 1135 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 1136 | { |
vic20 | 0:39a545e08ccd | 1137 | // Disable ticker |
vic20 | 0:39a545e08ccd | 1138 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 1139 | // Signal end |
vic20 | 0:39a545e08ccd | 1140 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 1141 | } |
vic20 | 0:39a545e08ccd | 1142 | |
vic20 | 0:39a545e08ccd | 1143 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1144 | if (overrun) |
vic20 | 0:39a545e08ccd | 1145 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 1146 | |
vic20 | 0:39a545e08ccd | 1147 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1148 | } |
vic20 | 1:d81bef65eece | 1149 | |
vic20 | 1:d81bef65eece | 1150 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1151 | |
vic20 | 0:39a545e08ccd | 1152 | // Implements command 'P' |
vic20 | 0:39a545e08ccd | 1153 | // Step response |
vic20 | 0:39a545e08ccd | 1154 | void stepResponse() |
vic20 | 0:39a545e08ccd | 1155 | { |
vic20 | 0:39a545e08ccd | 1156 | // Read step value |
vic20 | 0:39a545e08ccd | 1157 | stepValue = getU16(); |
vic20 | 0:39a545e08ccd | 1158 | |
vic20 | 0:39a545e08ccd | 1159 | // Check of CRC |
vic20 | 0:39a545e08ccd | 1160 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 1161 | |
vic20 | 0:39a545e08ccd | 1162 | sendByte(ACK); // All Ok |
vic20 | 0:39a545e08ccd | 1163 | |
vic20 | 0:39a545e08ccd | 1164 | // Configure ticker ISR |
vic20 | 0:39a545e08ccd | 1165 | samples = 0; // Number of processed samples |
vic20 | 0:39a545e08ccd | 1166 | inBuffPos = 0; // Current buffer position |
vic20 | 0:39a545e08ccd | 1167 | endTicker = 0; // Ticker has not ended |
vic20 | 0:39a545e08ccd | 1168 | |
vic20 | 0:39a545e08ccd | 1169 | triggerSample = n_s/5; |
vic20 | 0:39a545e08ccd | 1170 | |
vic20 | 0:39a545e08ccd | 1171 | currentBsize = n_ai * n_s; // Current size for buffer |
vic20 | 0:39a545e08ccd | 1172 | |
vic20 | 0:39a545e08ccd | 1173 | // Clear overrun variables |
vic20 | 0:39a545e08ccd | 1174 | overrun_error = 0; |
vic20 | 0:39a545e08ccd | 1175 | overrun = 0; |
vic20 | 0:39a545e08ccd | 1176 | |
vic20 | 1:d81bef65eece | 1177 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1178 | |
vic20 | 0:39a545e08ccd | 1179 | // Check if we only read one channel |
vic20 | 0:39a545e08ccd | 1180 | if ((n_ai==1)&&(stime<30e-6f)) |
vic20 | 0:39a545e08ccd | 1181 | { |
vic20 | 0:39a545e08ccd | 1182 | // Perform a dummy read |
vic20 | 0:39a545e08ccd | 1183 | ain1.read_u16(); |
vic20 | 0:39a545e08ccd | 1184 | // Programs the ticker |
vic20 | 0:39a545e08ccd | 1185 | ticR.attach(&stepResponseSingleISR,stime); |
vic20 | 0:39a545e08ccd | 1186 | } |
vic20 | 0:39a545e08ccd | 1187 | else |
vic20 | 0:39a545e08ccd | 1188 | { |
vic20 | 0:39a545e08ccd | 1189 | // Programs the ticker |
vic20 | 0:39a545e08ccd | 1190 | ticR.attach(&stepResponseISR,stime); |
vic20 | 0:39a545e08ccd | 1191 | } |
vic20 | 1:d81bef65eece | 1192 | |
vic20 | 1:d81bef65eece | 1193 | #else // No FAST_ADC code |
vic20 | 1:d81bef65eece | 1194 | |
vic20 | 1:d81bef65eece | 1195 | // Programs the ticker |
vic20 | 1:d81bef65eece | 1196 | ticR.attach(&stepResponseISR,stime); |
vic20 | 1:d81bef65eece | 1197 | |
vic20 | 1:d81bef65eece | 1198 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1199 | |
vic20 | 0:39a545e08ccd | 1200 | // Wait till end |
vic20 | 0:39a545e08ccd | 1201 | while (!endTicker) overrun = 0; |
vic20 | 0:39a545e08ccd | 1202 | |
vic20 | 0:39a545e08ccd | 1203 | // Return data |
vic20 | 0:39a545e08ccd | 1204 | dumpInBuffer(); // Dump data |
vic20 | 0:39a545e08ccd | 1205 | |
vic20 | 0:39a545e08ccd | 1206 | // Send CRC to end Tx |
vic20 | 0:39a545e08ccd | 1207 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1208 | } |
vic20 | 0:39a545e08ccd | 1209 | |
vic20 | 0:39a545e08ccd | 1210 | /********************* WAVETABLE CODE ***************************/ |
vic20 | 0:39a545e08ccd | 1211 | |
vic20 | 0:39a545e08ccd | 1212 | // Load a wavetable |
vic20 | 0:39a545e08ccd | 1213 | void loadWaveTable() |
vic20 | 0:39a545e08ccd | 1214 | { |
vic20 | 0:39a545e08ccd | 1215 | int i; |
vic20 | 0:39a545e08ccd | 1216 | |
vic20 | 0:39a545e08ccd | 1217 | // Eliminate secondary wavetable |
vic20 | 0:39a545e08ccd | 1218 | w_s2 = 0; |
vic20 | 0:39a545e08ccd | 1219 | |
vic20 | 0:39a545e08ccd | 1220 | // Get size |
vic20 | 0:39a545e08ccd | 1221 | w_s = getU16(); |
vic20 | 0:39a545e08ccd | 1222 | |
vic20 | 0:39a545e08ccd | 1223 | // Check size |
vic20 | 0:39a545e08ccd | 1224 | if (w_s > BSIZE) |
vic20 | 0:39a545e08ccd | 1225 | { |
vic20 | 0:39a545e08ccd | 1226 | w_s = 0; // Eliminate table |
vic20 | 0:39a545e08ccd | 1227 | |
vic20 | 0:39a545e08ccd | 1228 | // Calculate new memory configuration |
vic20 | 0:39a545e08ccd | 1229 | wave2buff=&buff[w_s]; |
vic20 | 0:39a545e08ccd | 1230 | tranBuff =&buff[w_s]; |
vic20 | 0:39a545e08ccd | 1231 | |
vic20 | 0:39a545e08ccd | 1232 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 1233 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1234 | return; |
vic20 | 0:39a545e08ccd | 1235 | } |
vic20 | 0:39a545e08ccd | 1236 | |
vic20 | 0:39a545e08ccd | 1237 | // Calculate new memory configuration |
vic20 | 0:39a545e08ccd | 1238 | wave2buff=&buff[w_s]; |
vic20 | 0:39a545e08ccd | 1239 | tranBuff =&buff[w_s]; |
vic20 | 0:39a545e08ccd | 1240 | |
vic20 | 0:39a545e08ccd | 1241 | if (w_s > 0) |
vic20 | 0:39a545e08ccd | 1242 | { |
vic20 | 0:39a545e08ccd | 1243 | // Load samples |
vic20 | 0:39a545e08ccd | 1244 | for(i=0;i<w_s;i++) |
vic20 | 0:39a545e08ccd | 1245 | buff[i] = getU16(); |
vic20 | 0:39a545e08ccd | 1246 | } |
vic20 | 0:39a545e08ccd | 1247 | |
vic20 | 0:39a545e08ccd | 1248 | // Check of CRC |
vic20 | 0:39a545e08ccd | 1249 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 1250 | |
vic20 | 0:39a545e08ccd | 1251 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 1252 | |
vic20 | 0:39a545e08ccd | 1253 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1254 | } |
vic20 | 0:39a545e08ccd | 1255 | |
vic20 | 0:39a545e08ccd | 1256 | // Load a secondary wavetable |
vic20 | 0:39a545e08ccd | 1257 | void loadSecondaryWaveTable() |
vic20 | 0:39a545e08ccd | 1258 | { |
vic20 | 0:39a545e08ccd | 1259 | int i; |
vic20 | 0:39a545e08ccd | 1260 | |
vic20 | 0:39a545e08ccd | 1261 | // Get size |
vic20 | 0:39a545e08ccd | 1262 | w_s2 = getU16(); |
vic20 | 0:39a545e08ccd | 1263 | |
vic20 | 0:39a545e08ccd | 1264 | // Check size and primary wavetable |
vic20 | 0:39a545e08ccd | 1265 | if (w_s2 > wave2buffSize()) |
vic20 | 0:39a545e08ccd | 1266 | { |
vic20 | 0:39a545e08ccd | 1267 | w_s2 = 0; |
vic20 | 0:39a545e08ccd | 1268 | // Calculate new memory configuration |
vic20 | 0:39a545e08ccd | 1269 | tranBuff =&buff[w_s+w_s2]; |
vic20 | 0:39a545e08ccd | 1270 | |
vic20 | 0:39a545e08ccd | 1271 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 1272 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1273 | return; |
vic20 | 0:39a545e08ccd | 1274 | } |
vic20 | 0:39a545e08ccd | 1275 | |
vic20 | 0:39a545e08ccd | 1276 | // Calculate new memory configuration |
vic20 | 0:39a545e08ccd | 1277 | tranBuff =&buff[w_s+w_s2]; |
vic20 | 0:39a545e08ccd | 1278 | |
vic20 | 0:39a545e08ccd | 1279 | for(i=0;i<w_s2;i++) |
vic20 | 0:39a545e08ccd | 1280 | wave2buff[i] = getU16(); |
vic20 | 0:39a545e08ccd | 1281 | |
vic20 | 0:39a545e08ccd | 1282 | // Check of CRC |
vic20 | 0:39a545e08ccd | 1283 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 1284 | |
vic20 | 0:39a545e08ccd | 1285 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 1286 | |
vic20 | 0:39a545e08ccd | 1287 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1288 | } |
vic20 | 0:39a545e08ccd | 1289 | |
vic20 | 0:39a545e08ccd | 1290 | |
vic20 | 0:39a545e08ccd | 1291 | /****************** WAVE RESPONSE CODE *************************/ |
vic20 | 0:39a545e08ccd | 1292 | |
vic20 | 0:39a545e08ccd | 1293 | // Hardware profiling operation (if enabled) |
vic20 | 0:39a545e08ccd | 1294 | // Not implemented |
vic20 | 0:39a545e08ccd | 1295 | |
vic20 | 0:39a545e08ccd | 1296 | // ISR for the waveResponse function |
vic20 | 0:39a545e08ccd | 1297 | void waveResponseISR() |
vic20 | 0:39a545e08ccd | 1298 | { |
vic20 | 0:39a545e08ccd | 1299 | // Write DAC |
vic20 | 0:39a545e08ccd | 1300 | aout1 = buff[w_pos++] / MAX16F; |
vic20 | 0:39a545e08ccd | 1301 | |
vic20 | 0:39a545e08ccd | 1302 | // Store analog data |
vic20 | 0:39a545e08ccd | 1303 | if (!w_n) |
vic20 | 0:39a545e08ccd | 1304 | { |
vic20 | 0:39a545e08ccd | 1305 | storeAnalog(); |
vic20 | 0:39a545e08ccd | 1306 | |
vic20 | 0:39a545e08ccd | 1307 | // Increase sample |
vic20 | 0:39a545e08ccd | 1308 | samples++; |
vic20 | 0:39a545e08ccd | 1309 | |
vic20 | 0:39a545e08ccd | 1310 | // Check if we should end |
vic20 | 0:39a545e08ccd | 1311 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 1312 | { |
vic20 | 0:39a545e08ccd | 1313 | // Disable ticker |
vic20 | 0:39a545e08ccd | 1314 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 1315 | // Signal end |
vic20 | 0:39a545e08ccd | 1316 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 1317 | } |
vic20 | 0:39a545e08ccd | 1318 | |
vic20 | 0:39a545e08ccd | 1319 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1320 | if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1321 | } |
vic20 | 0:39a545e08ccd | 1322 | else |
vic20 | 0:39a545e08ccd | 1323 | { |
vic20 | 0:39a545e08ccd | 1324 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1325 | if (w_pos == w_s) |
vic20 | 0:39a545e08ccd | 1326 | { |
vic20 | 0:39a545e08ccd | 1327 | w_pos = 0; |
vic20 | 0:39a545e08ccd | 1328 | w_n--; |
vic20 | 0:39a545e08ccd | 1329 | } |
vic20 | 0:39a545e08ccd | 1330 | } |
vic20 | 0:39a545e08ccd | 1331 | |
vic20 | 0:39a545e08ccd | 1332 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1333 | // if (w_pos == w_s) w_pos = 0; |
vic20 | 1:d81bef65eece | 1334 | |
vic20 | 1:d81bef65eece | 1335 | // Check halt |
vic20 | 1:d81bef65eece | 1336 | if (halt) |
vic20 | 1:d81bef65eece | 1337 | { |
vic20 | 1:d81bef65eece | 1338 | // Disable ticker |
vic20 | 1:d81bef65eece | 1339 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1340 | // Signal end |
vic20 | 1:d81bef65eece | 1341 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1342 | return; |
vic20 | 1:d81bef65eece | 1343 | } |
vic20 | 0:39a545e08ccd | 1344 | |
vic20 | 0:39a545e08ccd | 1345 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1346 | if (overrun) |
vic20 | 0:39a545e08ccd | 1347 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 1348 | |
vic20 | 0:39a545e08ccd | 1349 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1350 | } |
vic20 | 0:39a545e08ccd | 1351 | |
vic20 | 1:d81bef65eece | 1352 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1353 | |
vic20 | 0:39a545e08ccd | 1354 | // ISR for the waveResponse function |
vic20 | 0:39a545e08ccd | 1355 | // Time optimized version |
vic20 | 0:39a545e08ccd | 1356 | // Only used for single ADC and stime < 30us |
vic20 | 0:39a545e08ccd | 1357 | void waveResponseSingleISR() |
vic20 | 0:39a545e08ccd | 1358 | { |
vic20 | 0:39a545e08ccd | 1359 | // Write DAC |
vic20 | 0:39a545e08ccd | 1360 | DAC->DHR12R1 = (buff[w_pos++]>>4); |
vic20 | 0:39a545e08ccd | 1361 | |
vic20 | 0:39a545e08ccd | 1362 | // Store analog data |
vic20 | 0:39a545e08ccd | 1363 | if (!w_n) |
vic20 | 0:39a545e08ccd | 1364 | { |
vic20 | 0:39a545e08ccd | 1365 | // Direct access to ADC registers |
vic20 | 0:39a545e08ccd | 1366 | ADC1->CR |= ADC_CR_ADSTART; |
vic20 | 0:39a545e08ccd | 1367 | while (!(ADC1->ISR & ADC_ISR_EOC)); |
vic20 | 0:39a545e08ccd | 1368 | tranBuff[inBuffPos++]=(ADC1->DR)<<4; |
vic20 | 0:39a545e08ccd | 1369 | |
vic20 | 0:39a545e08ccd | 1370 | if (inBuffPos == currentBsize) inBuffPos = 0; |
vic20 | 0:39a545e08ccd | 1371 | |
vic20 | 0:39a545e08ccd | 1372 | // Increase sample |
vic20 | 0:39a545e08ccd | 1373 | samples++; |
vic20 | 0:39a545e08ccd | 1374 | |
vic20 | 0:39a545e08ccd | 1375 | // Check if we should end |
vic20 | 0:39a545e08ccd | 1376 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 1377 | { |
vic20 | 0:39a545e08ccd | 1378 | // Disable ticker |
vic20 | 0:39a545e08ccd | 1379 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 1380 | // Signal end |
vic20 | 0:39a545e08ccd | 1381 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 1382 | } |
vic20 | 0:39a545e08ccd | 1383 | |
vic20 | 0:39a545e08ccd | 1384 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1385 | if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1386 | } |
vic20 | 0:39a545e08ccd | 1387 | else |
vic20 | 0:39a545e08ccd | 1388 | { |
vic20 | 0:39a545e08ccd | 1389 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1390 | if (w_pos == w_s) |
vic20 | 0:39a545e08ccd | 1391 | { |
vic20 | 0:39a545e08ccd | 1392 | w_pos = 0; |
vic20 | 0:39a545e08ccd | 1393 | w_n--; |
vic20 | 0:39a545e08ccd | 1394 | } |
vic20 | 0:39a545e08ccd | 1395 | } |
vic20 | 0:39a545e08ccd | 1396 | |
vic20 | 0:39a545e08ccd | 1397 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1398 | // if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1399 | |
vic20 | 1:d81bef65eece | 1400 | // Check halt |
vic20 | 1:d81bef65eece | 1401 | if (halt) |
vic20 | 1:d81bef65eece | 1402 | { |
vic20 | 1:d81bef65eece | 1403 | // Disable ticker |
vic20 | 1:d81bef65eece | 1404 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1405 | // Signal end |
vic20 | 1:d81bef65eece | 1406 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1407 | return; |
vic20 | 1:d81bef65eece | 1408 | } |
vic20 | 1:d81bef65eece | 1409 | |
vic20 | 0:39a545e08ccd | 1410 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1411 | if (overrun) |
vic20 | 0:39a545e08ccd | 1412 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 1413 | |
vic20 | 0:39a545e08ccd | 1414 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1415 | } |
vic20 | 1:d81bef65eece | 1416 | |
vic20 | 1:d81bef65eece | 1417 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1418 | |
vic20 | 0:39a545e08ccd | 1419 | // Wave response |
vic20 | 0:39a545e08ccd | 1420 | void waveResponse() |
vic20 | 0:39a545e08ccd | 1421 | { |
vic20 | 0:39a545e08ccd | 1422 | // Read number of waves before mesurement |
vic20 | 0:39a545e08ccd | 1423 | w_n = getU16(); |
vic20 | 0:39a545e08ccd | 1424 | |
vic20 | 0:39a545e08ccd | 1425 | // Check of CRC |
vic20 | 0:39a545e08ccd | 1426 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 1427 | |
vic20 | 0:39a545e08ccd | 1428 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 1429 | |
vic20 | 0:39a545e08ccd | 1430 | // Configure ticker ISR |
vic20 | 0:39a545e08ccd | 1431 | samples = 0; // Number of processed samples |
vic20 | 0:39a545e08ccd | 1432 | inBuffPos = 0; // Current buffer position |
vic20 | 0:39a545e08ccd | 1433 | endTicker = 0; // Ticker has not ended |
vic20 | 0:39a545e08ccd | 1434 | w_pos = 0; // Current wave position |
vic20 | 0:39a545e08ccd | 1435 | |
vic20 | 0:39a545e08ccd | 1436 | currentBsize = n_ai * n_s; // Current size for buffer |
vic20 | 0:39a545e08ccd | 1437 | |
vic20 | 0:39a545e08ccd | 1438 | // Clear overrun variables |
vic20 | 0:39a545e08ccd | 1439 | overrun_error = 0; |
vic20 | 0:39a545e08ccd | 1440 | overrun = 0; |
vic20 | 0:39a545e08ccd | 1441 | |
vic20 | 1:d81bef65eece | 1442 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1443 | |
vic20 | 0:39a545e08ccd | 1444 | // Check if we only read one channel |
vic20 | 0:39a545e08ccd | 1445 | if ((n_ai==1)&&(stime<30e-6f)) |
vic20 | 0:39a545e08ccd | 1446 | { |
vic20 | 0:39a545e08ccd | 1447 | // Perform a dummy read |
vic20 | 0:39a545e08ccd | 1448 | ain1.read_u16(); |
vic20 | 0:39a545e08ccd | 1449 | // Programs the ticker |
vic20 | 0:39a545e08ccd | 1450 | ticR.attach(&waveResponseSingleISR,stime); |
vic20 | 0:39a545e08ccd | 1451 | } |
vic20 | 0:39a545e08ccd | 1452 | else |
vic20 | 0:39a545e08ccd | 1453 | { |
vic20 | 0:39a545e08ccd | 1454 | // Programs the ticker |
vic20 | 0:39a545e08ccd | 1455 | ticR.attach(&waveResponseISR,stime); |
vic20 | 0:39a545e08ccd | 1456 | } |
vic20 | 1:d81bef65eece | 1457 | |
vic20 | 1:d81bef65eece | 1458 | #else //No FAST_ADC code |
vic20 | 1:d81bef65eece | 1459 | |
vic20 | 1:d81bef65eece | 1460 | // Programs the ticker |
vic20 | 1:d81bef65eece | 1461 | ticR.attach(&waveResponseISR,stime); |
vic20 | 1:d81bef65eece | 1462 | |
vic20 | 1:d81bef65eece | 1463 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1464 | |
vic20 | 0:39a545e08ccd | 1465 | // Wait till end |
vic20 | 0:39a545e08ccd | 1466 | while (!endTicker) overrun = 0; |
vic20 | 0:39a545e08ccd | 1467 | |
vic20 | 0:39a545e08ccd | 1468 | // Return data |
vic20 | 0:39a545e08ccd | 1469 | dumpInBuffer(); // Dump data |
vic20 | 0:39a545e08ccd | 1470 | |
vic20 | 0:39a545e08ccd | 1471 | // End sending CRC |
vic20 | 0:39a545e08ccd | 1472 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1473 | } |
vic20 | 0:39a545e08ccd | 1474 | |
vic20 | 0:39a545e08ccd | 1475 | /*************** DUAL WAVE RESPONSE CODE *************************/ |
vic20 | 0:39a545e08ccd | 1476 | |
vic20 | 0:39a545e08ccd | 1477 | // ISR for the dualWaveResponse function |
vic20 | 0:39a545e08ccd | 1478 | void dualWaveResponseISR() |
vic20 | 0:39a545e08ccd | 1479 | { |
vic20 | 0:39a545e08ccd | 1480 | // Write DACs |
vic20 | 0:39a545e08ccd | 1481 | aout1 = buff[w_pos++] / MAX16F; |
vic20 | 0:39a545e08ccd | 1482 | aout2 = wave2buff[w_pos2++] / MAX16F; |
vic20 | 0:39a545e08ccd | 1483 | |
vic20 | 0:39a545e08ccd | 1484 | // Store analog data |
vic20 | 0:39a545e08ccd | 1485 | if (!w_n) |
vic20 | 0:39a545e08ccd | 1486 | { |
vic20 | 0:39a545e08ccd | 1487 | storeAnalog(); |
vic20 | 0:39a545e08ccd | 1488 | |
vic20 | 0:39a545e08ccd | 1489 | // Increase sample |
vic20 | 0:39a545e08ccd | 1490 | samples++; |
vic20 | 0:39a545e08ccd | 1491 | |
vic20 | 0:39a545e08ccd | 1492 | // Check if we should end |
vic20 | 0:39a545e08ccd | 1493 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 1494 | { |
vic20 | 0:39a545e08ccd | 1495 | // Disable ticker |
vic20 | 0:39a545e08ccd | 1496 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 1497 | // Signal end |
vic20 | 0:39a545e08ccd | 1498 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 1499 | } |
vic20 | 0:39a545e08ccd | 1500 | |
vic20 | 0:39a545e08ccd | 1501 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1502 | if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1503 | if (w_pos2 == w_s2) w_pos2 = 0; |
vic20 | 0:39a545e08ccd | 1504 | } |
vic20 | 0:39a545e08ccd | 1505 | else |
vic20 | 0:39a545e08ccd | 1506 | { |
vic20 | 0:39a545e08ccd | 1507 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1508 | if (w_pos == w_s) |
vic20 | 0:39a545e08ccd | 1509 | { |
vic20 | 0:39a545e08ccd | 1510 | w_pos = 0; |
vic20 | 0:39a545e08ccd | 1511 | w_n--; |
vic20 | 0:39a545e08ccd | 1512 | } |
vic20 | 0:39a545e08ccd | 1513 | if (w_pos2 == w_s2) w_pos2 = 0; |
vic20 | 0:39a545e08ccd | 1514 | } |
vic20 | 0:39a545e08ccd | 1515 | |
vic20 | 0:39a545e08ccd | 1516 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1517 | //if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1518 | |
vic20 | 1:d81bef65eece | 1519 | // Check halt |
vic20 | 1:d81bef65eece | 1520 | if (halt) |
vic20 | 1:d81bef65eece | 1521 | { |
vic20 | 1:d81bef65eece | 1522 | // Disable ticker |
vic20 | 1:d81bef65eece | 1523 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1524 | // Signal end |
vic20 | 1:d81bef65eece | 1525 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1526 | return; |
vic20 | 1:d81bef65eece | 1527 | } |
vic20 | 1:d81bef65eece | 1528 | |
vic20 | 0:39a545e08ccd | 1529 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1530 | if (overrun) |
vic20 | 0:39a545e08ccd | 1531 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 1532 | |
vic20 | 0:39a545e08ccd | 1533 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1534 | } |
vic20 | 0:39a545e08ccd | 1535 | |
vic20 | 1:d81bef65eece | 1536 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1537 | |
vic20 | 0:39a545e08ccd | 1538 | // ISR for the dualWaveResponse function |
vic20 | 0:39a545e08ccd | 1539 | // Time optimized version |
vic20 | 0:39a545e08ccd | 1540 | // Use only for single ADC read and stime < 35us |
vic20 | 0:39a545e08ccd | 1541 | void dualWaveResponseSingleISR() |
vic20 | 0:39a545e08ccd | 1542 | { |
vic20 | 0:39a545e08ccd | 1543 | // Write DACs |
vic20 | 0:39a545e08ccd | 1544 | DAC->DHR12R1 = (buff[w_pos++]>>4); |
vic20 | 0:39a545e08ccd | 1545 | DAC->DHR12R2 = (wave2buff[w_pos2++]>>4); |
vic20 | 0:39a545e08ccd | 1546 | |
vic20 | 0:39a545e08ccd | 1547 | // Store analog data |
vic20 | 0:39a545e08ccd | 1548 | if (!w_n) |
vic20 | 0:39a545e08ccd | 1549 | { |
vic20 | 0:39a545e08ccd | 1550 | // Direct access to ADC registers |
vic20 | 0:39a545e08ccd | 1551 | ADC1->CR |= ADC_CR_ADSTART; |
vic20 | 0:39a545e08ccd | 1552 | while (!(ADC1->ISR & ADC_ISR_EOC)); |
vic20 | 0:39a545e08ccd | 1553 | tranBuff[inBuffPos++]=(ADC1->DR)<<4; |
vic20 | 0:39a545e08ccd | 1554 | |
vic20 | 0:39a545e08ccd | 1555 | if (inBuffPos == currentBsize) inBuffPos = 0; |
vic20 | 0:39a545e08ccd | 1556 | |
vic20 | 0:39a545e08ccd | 1557 | // Increase sample |
vic20 | 0:39a545e08ccd | 1558 | samples++; |
vic20 | 0:39a545e08ccd | 1559 | |
vic20 | 0:39a545e08ccd | 1560 | // Check if we should end |
vic20 | 0:39a545e08ccd | 1561 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 1562 | { |
vic20 | 0:39a545e08ccd | 1563 | // Disable ticker |
vic20 | 0:39a545e08ccd | 1564 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 1565 | // Signal end |
vic20 | 0:39a545e08ccd | 1566 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 1567 | } |
vic20 | 0:39a545e08ccd | 1568 | |
vic20 | 0:39a545e08ccd | 1569 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1570 | if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1571 | if (w_pos2 == w_s2) w_pos2 = 0; |
vic20 | 0:39a545e08ccd | 1572 | } |
vic20 | 0:39a545e08ccd | 1573 | else |
vic20 | 0:39a545e08ccd | 1574 | { |
vic20 | 0:39a545e08ccd | 1575 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1576 | if (w_pos == w_s) |
vic20 | 0:39a545e08ccd | 1577 | { |
vic20 | 0:39a545e08ccd | 1578 | w_pos = 0; |
vic20 | 0:39a545e08ccd | 1579 | w_n--; |
vic20 | 0:39a545e08ccd | 1580 | } |
vic20 | 0:39a545e08ccd | 1581 | if (w_pos2 == w_s2) w_pos2 = 0; |
vic20 | 0:39a545e08ccd | 1582 | } |
vic20 | 0:39a545e08ccd | 1583 | |
vic20 | 0:39a545e08ccd | 1584 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1585 | //if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1586 | |
vic20 | 1:d81bef65eece | 1587 | // Check halt |
vic20 | 1:d81bef65eece | 1588 | if (halt) |
vic20 | 1:d81bef65eece | 1589 | { |
vic20 | 1:d81bef65eece | 1590 | // Disable ticker |
vic20 | 1:d81bef65eece | 1591 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1592 | // Signal end |
vic20 | 1:d81bef65eece | 1593 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1594 | return; |
vic20 | 1:d81bef65eece | 1595 | } |
vic20 | 1:d81bef65eece | 1596 | |
vic20 | 0:39a545e08ccd | 1597 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1598 | if (overrun) |
vic20 | 0:39a545e08ccd | 1599 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 1600 | |
vic20 | 0:39a545e08ccd | 1601 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1602 | } |
vic20 | 1:d81bef65eece | 1603 | |
vic20 | 1:d81bef65eece | 1604 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1605 | |
vic20 | 0:39a545e08ccd | 1606 | // Dual wave response |
vic20 | 0:39a545e08ccd | 1607 | void dualWaveResponse() |
vic20 | 0:39a545e08ccd | 1608 | { |
vic20 | 0:39a545e08ccd | 1609 | // Read number of primary waves before mesurement |
vic20 | 0:39a545e08ccd | 1610 | w_n = getU16(); |
vic20 | 0:39a545e08ccd | 1611 | |
vic20 | 0:39a545e08ccd | 1612 | // Check of CRC |
vic20 | 0:39a545e08ccd | 1613 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 1614 | |
vic20 | 0:39a545e08ccd | 1615 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 1616 | |
vic20 | 0:39a545e08ccd | 1617 | // Configure ticker ISR |
vic20 | 0:39a545e08ccd | 1618 | samples = 0; // Number of processed samples |
vic20 | 0:39a545e08ccd | 1619 | inBuffPos = 0; // Current buffer position |
vic20 | 0:39a545e08ccd | 1620 | endTicker = 0; // Ticker has not ended |
vic20 | 0:39a545e08ccd | 1621 | w_pos = 0; // Current wave position |
vic20 | 0:39a545e08ccd | 1622 | w_pos2 = 0; // Secondary wave position |
vic20 | 0:39a545e08ccd | 1623 | |
vic20 | 0:39a545e08ccd | 1624 | currentBsize = n_ai * n_s; // Current size for buffer |
vic20 | 0:39a545e08ccd | 1625 | |
vic20 | 0:39a545e08ccd | 1626 | // Clear overrun variables |
vic20 | 0:39a545e08ccd | 1627 | overrun_error = 0; |
vic20 | 0:39a545e08ccd | 1628 | overrun = 0; |
vic20 | 0:39a545e08ccd | 1629 | |
vic20 | 1:d81bef65eece | 1630 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1631 | |
vic20 | 0:39a545e08ccd | 1632 | // Check if we only read one channel |
vic20 | 0:39a545e08ccd | 1633 | if ((n_ai==1)&&(stime<35e-6f)) |
vic20 | 0:39a545e08ccd | 1634 | { |
vic20 | 0:39a545e08ccd | 1635 | // Perform a dummy read |
vic20 | 0:39a545e08ccd | 1636 | ain1.read_u16(); |
vic20 | 0:39a545e08ccd | 1637 | // Programs the ticker |
vic20 | 0:39a545e08ccd | 1638 | ticR.attach(&dualWaveResponseSingleISR,stime); |
vic20 | 0:39a545e08ccd | 1639 | } |
vic20 | 0:39a545e08ccd | 1640 | else |
vic20 | 0:39a545e08ccd | 1641 | { |
vic20 | 0:39a545e08ccd | 1642 | // Programs the ticker |
vic20 | 0:39a545e08ccd | 1643 | ticR.attach(&dualWaveResponseISR,stime); |
vic20 | 0:39a545e08ccd | 1644 | } |
vic20 | 1:d81bef65eece | 1645 | |
vic20 | 1:d81bef65eece | 1646 | #else //No FAST_ADC code |
vic20 | 1:d81bef65eece | 1647 | |
vic20 | 1:d81bef65eece | 1648 | // Programs the ticker |
vic20 | 1:d81bef65eece | 1649 | ticR.attach(&dualWaveResponseISR,stime); |
vic20 | 1:d81bef65eece | 1650 | |
vic20 | 1:d81bef65eece | 1651 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1652 | |
vic20 | 0:39a545e08ccd | 1653 | // Wait till end |
vic20 | 0:39a545e08ccd | 1654 | while (!endTicker) overrun = 0; |
vic20 | 0:39a545e08ccd | 1655 | |
vic20 | 0:39a545e08ccd | 1656 | // Return data |
vic20 | 0:39a545e08ccd | 1657 | dumpInBuffer(); // Dump data |
vic20 | 0:39a545e08ccd | 1658 | |
vic20 | 0:39a545e08ccd | 1659 | // End sending CRC |
vic20 | 0:39a545e08ccd | 1660 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1661 | } |
vic20 | 0:39a545e08ccd | 1662 | |
vic20 | 0:39a545e08ccd | 1663 | /*************** SINGLE WAVE RESPONSE CODE **********************/ |
vic20 | 0:39a545e08ccd | 1664 | // Hardware profiling operation (if enabled) |
vic20 | 0:39a545e08ccd | 1665 | // PRO1 line high during ISR |
vic20 | 0:39a545e08ccd | 1666 | // PRO2 line mimics overrun variable |
vic20 | 0:39a545e08ccd | 1667 | |
vic20 | 0:39a545e08ccd | 1668 | // ISR for the singleWaveResponse function |
vic20 | 0:39a545e08ccd | 1669 | void singleWaveResponseISR() |
vic20 | 0:39a545e08ccd | 1670 | { |
vic20 | 0:39a545e08ccd | 1671 | int a1; |
vic20 | 0:39a545e08ccd | 1672 | |
vic20 | 0:39a545e08ccd | 1673 | PRO1_SET |
vic20 | 0:39a545e08ccd | 1674 | |
vic20 | 0:39a545e08ccd | 1675 | // Write DAC1 |
vic20 | 0:39a545e08ccd | 1676 | aout1 = buff[w_pos++] / MAX16F; |
vic20 | 0:39a545e08ccd | 1677 | |
vic20 | 0:39a545e08ccd | 1678 | // Store analog data |
vic20 | 0:39a545e08ccd | 1679 | if (!w_n) |
vic20 | 0:39a545e08ccd | 1680 | { |
vic20 | 0:39a545e08ccd | 1681 | // Store data |
vic20 | 0:39a545e08ccd | 1682 | // Store data |
vic20 | 0:39a545e08ccd | 1683 | a1 = ain_tran->read_u16(); |
vic20 | 0:39a545e08ccd | 1684 | tranBuff[inBuffPos++]=a1; |
vic20 | 0:39a545e08ccd | 1685 | |
vic20 | 0:39a545e08ccd | 1686 | // Increase sample |
vic20 | 0:39a545e08ccd | 1687 | samples++; |
vic20 | 0:39a545e08ccd | 1688 | |
vic20 | 0:39a545e08ccd | 1689 | // Check if we should end |
vic20 | 0:39a545e08ccd | 1690 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 1691 | { |
vic20 | 0:39a545e08ccd | 1692 | // Disable ticker |
vic20 | 0:39a545e08ccd | 1693 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 1694 | // Signal end |
vic20 | 0:39a545e08ccd | 1695 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 1696 | } |
vic20 | 0:39a545e08ccd | 1697 | |
vic20 | 0:39a545e08ccd | 1698 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1699 | if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1700 | } |
vic20 | 0:39a545e08ccd | 1701 | else |
vic20 | 0:39a545e08ccd | 1702 | { |
vic20 | 0:39a545e08ccd | 1703 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1704 | if (w_pos == w_s) |
vic20 | 0:39a545e08ccd | 1705 | { |
vic20 | 0:39a545e08ccd | 1706 | w_pos = 0; |
vic20 | 0:39a545e08ccd | 1707 | w_n--; |
vic20 | 0:39a545e08ccd | 1708 | } |
vic20 | 0:39a545e08ccd | 1709 | } |
vic20 | 0:39a545e08ccd | 1710 | |
vic20 | 0:39a545e08ccd | 1711 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1712 | if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1713 | |
vic20 | 0:39a545e08ccd | 1714 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1715 | if (overrun) |
vic20 | 0:39a545e08ccd | 1716 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 1717 | |
vic20 | 1:d81bef65eece | 1718 | // Check halt |
vic20 | 1:d81bef65eece | 1719 | if (halt) |
vic20 | 1:d81bef65eece | 1720 | { |
vic20 | 1:d81bef65eece | 1721 | // Disable ticker |
vic20 | 1:d81bef65eece | 1722 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1723 | // Signal end |
vic20 | 1:d81bef65eece | 1724 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1725 | return; |
vic20 | 1:d81bef65eece | 1726 | } |
vic20 | 1:d81bef65eece | 1727 | |
vic20 | 0:39a545e08ccd | 1728 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1729 | |
vic20 | 0:39a545e08ccd | 1730 | PRO2_SET |
vic20 | 0:39a545e08ccd | 1731 | PRO1_CLEAR |
vic20 | 0:39a545e08ccd | 1732 | } |
vic20 | 0:39a545e08ccd | 1733 | |
vic20 | 1:d81bef65eece | 1734 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1735 | |
vic20 | 0:39a545e08ccd | 1736 | // ISR for the singleWaveResponse function |
vic20 | 0:39a545e08ccd | 1737 | // Time optimized version |
vic20 | 0:39a545e08ccd | 1738 | // Only used for stime < 30us |
vic20 | 0:39a545e08ccd | 1739 | void singleWaveResponseFastISR() |
vic20 | 0:39a545e08ccd | 1740 | { |
vic20 | 0:39a545e08ccd | 1741 | int a1; |
vic20 | 0:39a545e08ccd | 1742 | |
vic20 | 0:39a545e08ccd | 1743 | PRO1_SET |
vic20 | 0:39a545e08ccd | 1744 | |
vic20 | 0:39a545e08ccd | 1745 | // Write DAC1 |
vic20 | 0:39a545e08ccd | 1746 | DAC->DHR12R1 = (buff[w_pos++]>>4); /* New faster code */ |
vic20 | 0:39a545e08ccd | 1747 | |
vic20 | 0:39a545e08ccd | 1748 | // Store analog data |
vic20 | 0:39a545e08ccd | 1749 | if (!w_n) |
vic20 | 0:39a545e08ccd | 1750 | { |
vic20 | 0:39a545e08ccd | 1751 | // Store data |
vic20 | 0:39a545e08ccd | 1752 | // Direct access to registers |
vic20 | 0:39a545e08ccd | 1753 | ADC1->CR |= ADC_CR_ADSTART; |
vic20 | 0:39a545e08ccd | 1754 | while (!(ADC1->ISR & ADC_ISR_EOC)); |
vic20 | 0:39a545e08ccd | 1755 | a1 = ADC1->DR; |
vic20 | 0:39a545e08ccd | 1756 | tranBuff[inBuffPos++]=a1<<4; |
vic20 | 0:39a545e08ccd | 1757 | |
vic20 | 0:39a545e08ccd | 1758 | // Increase sample |
vic20 | 0:39a545e08ccd | 1759 | samples++; |
vic20 | 0:39a545e08ccd | 1760 | |
vic20 | 0:39a545e08ccd | 1761 | // Check if we should end |
vic20 | 0:39a545e08ccd | 1762 | if (samples >= n_s) |
vic20 | 0:39a545e08ccd | 1763 | { |
vic20 | 0:39a545e08ccd | 1764 | // Disable ticker |
vic20 | 0:39a545e08ccd | 1765 | ticR.detach(); |
vic20 | 0:39a545e08ccd | 1766 | // Signal end |
vic20 | 0:39a545e08ccd | 1767 | endTicker = 1; |
vic20 | 0:39a545e08ccd | 1768 | } |
vic20 | 0:39a545e08ccd | 1769 | |
vic20 | 0:39a545e08ccd | 1770 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1771 | if (w_pos == w_s) w_pos = 0; |
vic20 | 0:39a545e08ccd | 1772 | } |
vic20 | 0:39a545e08ccd | 1773 | else |
vic20 | 0:39a545e08ccd | 1774 | { |
vic20 | 0:39a545e08ccd | 1775 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1776 | if (w_pos == w_s) |
vic20 | 0:39a545e08ccd | 1777 | { |
vic20 | 0:39a545e08ccd | 1778 | w_pos = 0; |
vic20 | 0:39a545e08ccd | 1779 | w_n--; |
vic20 | 0:39a545e08ccd | 1780 | } |
vic20 | 0:39a545e08ccd | 1781 | } |
vic20 | 0:39a545e08ccd | 1782 | |
vic20 | 0:39a545e08ccd | 1783 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1784 | if (w_pos == w_s) w_pos = 0; |
vic20 | 1:d81bef65eece | 1785 | |
vic20 | 1:d81bef65eece | 1786 | // Check halt |
vic20 | 1:d81bef65eece | 1787 | if (halt) |
vic20 | 1:d81bef65eece | 1788 | { |
vic20 | 1:d81bef65eece | 1789 | // Disable ticker |
vic20 | 1:d81bef65eece | 1790 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1791 | // Signal end |
vic20 | 1:d81bef65eece | 1792 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1793 | return; |
vic20 | 1:d81bef65eece | 1794 | } |
vic20 | 0:39a545e08ccd | 1795 | |
vic20 | 0:39a545e08ccd | 1796 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1797 | if (overrun) |
vic20 | 0:39a545e08ccd | 1798 | overrun_error = 1; |
vic20 | 1:d81bef65eece | 1799 | |
vic20 | 0:39a545e08ccd | 1800 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1801 | |
vic20 | 0:39a545e08ccd | 1802 | PRO2_SET |
vic20 | 0:39a545e08ccd | 1803 | PRO1_CLEAR |
vic20 | 0:39a545e08ccd | 1804 | } |
vic20 | 1:d81bef65eece | 1805 | |
vic20 | 1:d81bef65eece | 1806 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1807 | |
vic20 | 0:39a545e08ccd | 1808 | // Select analog channel |
vic20 | 0:39a545e08ccd | 1809 | // In case of error, closes the communication and returns 0 |
vic20 | 0:39a545e08ccd | 1810 | // If all is ok, returns 1 |
vic20 | 0:39a545e08ccd | 1811 | int selectTranChannel(int channel) |
vic20 | 0:39a545e08ccd | 1812 | { |
vic20 | 0:39a545e08ccd | 1813 | if ((channel<0) || (channel>4)) |
vic20 | 0:39a545e08ccd | 1814 | { |
vic20 | 0:39a545e08ccd | 1815 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 1816 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1817 | return 0; |
vic20 | 0:39a545e08ccd | 1818 | } |
vic20 | 0:39a545e08ccd | 1819 | |
vic20 | 0:39a545e08ccd | 1820 | switch(channel) |
vic20 | 0:39a545e08ccd | 1821 | { |
vic20 | 0:39a545e08ccd | 1822 | case 1: |
vic20 | 0:39a545e08ccd | 1823 | ain_tran=&ain1; |
vic20 | 0:39a545e08ccd | 1824 | break; |
vic20 | 0:39a545e08ccd | 1825 | case 2: |
vic20 | 0:39a545e08ccd | 1826 | ain_tran=&ain2; |
vic20 | 0:39a545e08ccd | 1827 | break; |
vic20 | 0:39a545e08ccd | 1828 | case 3: |
vic20 | 0:39a545e08ccd | 1829 | ain_tran=&ain3; |
vic20 | 0:39a545e08ccd | 1830 | break; |
vic20 | 0:39a545e08ccd | 1831 | case 4: |
vic20 | 0:39a545e08ccd | 1832 | ain_tran=&ain4; |
vic20 | 0:39a545e08ccd | 1833 | break; |
vic20 | 0:39a545e08ccd | 1834 | } |
vic20 | 0:39a545e08ccd | 1835 | |
vic20 | 0:39a545e08ccd | 1836 | return 1; |
vic20 | 0:39a545e08ccd | 1837 | } |
vic20 | 0:39a545e08ccd | 1838 | |
vic20 | 0:39a545e08ccd | 1839 | // Single Wave response |
vic20 | 0:39a545e08ccd | 1840 | void singleWaveResponse() |
vic20 | 0:39a545e08ccd | 1841 | { |
vic20 | 0:39a545e08ccd | 1842 | int channel; |
vic20 | 0:39a545e08ccd | 1843 | |
vic20 | 0:39a545e08ccd | 1844 | PRO1_CLEAR // Reset profile lines |
vic20 | 0:39a545e08ccd | 1845 | PRO2_CLEAR |
vic20 | 0:39a545e08ccd | 1846 | |
vic20 | 0:39a545e08ccd | 1847 | // Read channel to read |
vic20 | 0:39a545e08ccd | 1848 | channel = getByte(); |
vic20 | 0:39a545e08ccd | 1849 | |
vic20 | 0:39a545e08ccd | 1850 | // Read number of waves before mesurement |
vic20 | 0:39a545e08ccd | 1851 | w_n = getU16(); |
vic20 | 0:39a545e08ccd | 1852 | |
vic20 | 0:39a545e08ccd | 1853 | // Check of CRC |
vic20 | 0:39a545e08ccd | 1854 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 1855 | |
vic20 | 0:39a545e08ccd | 1856 | // Configure the input channel |
vic20 | 0:39a545e08ccd | 1857 | if (!selectTranChannel(channel)) return; |
vic20 | 0:39a545e08ccd | 1858 | |
vic20 | 0:39a545e08ccd | 1859 | // Dummy read |
vic20 | 0:39a545e08ccd | 1860 | ain_tran->read_u16(); |
vic20 | 0:39a545e08ccd | 1861 | |
vic20 | 0:39a545e08ccd | 1862 | // Send ACK |
vic20 | 0:39a545e08ccd | 1863 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 1864 | |
vic20 | 0:39a545e08ccd | 1865 | // Configure ticker ISR |
vic20 | 0:39a545e08ccd | 1866 | samples = 0; // Number of processed samples |
vic20 | 0:39a545e08ccd | 1867 | inBuffPos = 0; // Current buffer position |
vic20 | 0:39a545e08ccd | 1868 | endTicker = 0; // Ticker has not ended |
vic20 | 0:39a545e08ccd | 1869 | w_pos = 0; // Current wave position |
vic20 | 0:39a545e08ccd | 1870 | |
vic20 | 0:39a545e08ccd | 1871 | currentBsize = n_s; // Current size for buffer |
vic20 | 0:39a545e08ccd | 1872 | |
vic20 | 0:39a545e08ccd | 1873 | // Clear overrun variables |
vic20 | 0:39a545e08ccd | 1874 | overrun_error = 0; |
vic20 | 0:39a545e08ccd | 1875 | overrun = 0; |
vic20 | 0:39a545e08ccd | 1876 | |
vic20 | 1:d81bef65eece | 1877 | #ifdef FAST_ADC |
vic20 | 1:d81bef65eece | 1878 | |
vic20 | 0:39a545e08ccd | 1879 | if (stime < 30e-6f) |
vic20 | 0:39a545e08ccd | 1880 | { |
vic20 | 0:39a545e08ccd | 1881 | // Programs the ticker with fast version |
vic20 | 0:39a545e08ccd | 1882 | ticR.attach(&singleWaveResponseFastISR,stime); |
vic20 | 0:39a545e08ccd | 1883 | } |
vic20 | 0:39a545e08ccd | 1884 | else |
vic20 | 0:39a545e08ccd | 1885 | { |
vic20 | 0:39a545e08ccd | 1886 | // Programs the ticker with normal version |
vic20 | 0:39a545e08ccd | 1887 | ticR.attach(&singleWaveResponseISR,stime); |
vic20 | 0:39a545e08ccd | 1888 | } |
vic20 | 1:d81bef65eece | 1889 | |
vic20 | 1:d81bef65eece | 1890 | #else //No FAST_ADC code |
vic20 | 1:d81bef65eece | 1891 | |
vic20 | 1:d81bef65eece | 1892 | // Programs the ticker with normal version |
vic20 | 1:d81bef65eece | 1893 | ticR.attach(&singleWaveResponseISR,stime); |
vic20 | 1:d81bef65eece | 1894 | |
vic20 | 1:d81bef65eece | 1895 | #endif //FAST_ADC |
vic20 | 0:39a545e08ccd | 1896 | |
vic20 | 0:39a545e08ccd | 1897 | // Wait till end |
vic20 | 0:39a545e08ccd | 1898 | while (!endTicker) { overrun = 0; PRO2_CLEAR } |
vic20 | 0:39a545e08ccd | 1899 | |
vic20 | 0:39a545e08ccd | 1900 | // Return data |
vic20 | 0:39a545e08ccd | 1901 | dumpInSingleBuffer(); // Dump data |
vic20 | 0:39a545e08ccd | 1902 | |
vic20 | 0:39a545e08ccd | 1903 | // End sending CRC |
vic20 | 0:39a545e08ccd | 1904 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1905 | } |
vic20 | 0:39a545e08ccd | 1906 | |
vic20 | 0:39a545e08ccd | 1907 | /****************** WAVE PLAY CODE *************************/ |
vic20 | 0:39a545e08ccd | 1908 | |
vic20 | 0:39a545e08ccd | 1909 | // ISR for the wavePlay function |
vic20 | 0:39a545e08ccd | 1910 | void wavePlayISR() |
vic20 | 0:39a545e08ccd | 1911 | { |
vic20 | 0:39a545e08ccd | 1912 | // Write DAC (Old code) |
vic20 | 0:39a545e08ccd | 1913 | // aout1 = buff[w_pos++] / MAX16F; |
vic20 | 0:39a545e08ccd | 1914 | |
vic20 | 0:39a545e08ccd | 1915 | // Write DACs (New faster code) |
vic20 | 0:39a545e08ccd | 1916 | DAC->DHR12R1 = (buff[w_pos++]>>4); |
vic20 | 0:39a545e08ccd | 1917 | |
vic20 | 0:39a545e08ccd | 1918 | // Check wave rollover |
vic20 | 0:39a545e08ccd | 1919 | if (w_pos == w_s) |
vic20 | 0:39a545e08ccd | 1920 | { |
vic20 | 1:d81bef65eece | 1921 | w_pos = 0; |
vic20 | 1:d81bef65eece | 1922 | if (!infiniteWave) |
vic20 | 1:d81bef65eece | 1923 | { |
vic20 | 1:d81bef65eece | 1924 | w_n--; |
vic20 | 1:d81bef65eece | 1925 | if (w_n <= 0) |
vic20 | 1:d81bef65eece | 1926 | { |
vic20 | 1:d81bef65eece | 1927 | // Disable ticker |
vic20 | 1:d81bef65eece | 1928 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1929 | // Signal end |
vic20 | 1:d81bef65eece | 1930 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1931 | return; |
vic20 | 1:d81bef65eece | 1932 | } |
vic20 | 1:d81bef65eece | 1933 | } |
vic20 | 0:39a545e08ccd | 1934 | } |
vic20 | 1:d81bef65eece | 1935 | |
vic20 | 1:d81bef65eece | 1936 | // Check for halt |
vic20 | 1:d81bef65eece | 1937 | if (halt) |
vic20 | 1:d81bef65eece | 1938 | { |
vic20 | 1:d81bef65eece | 1939 | // Disable ticker |
vic20 | 1:d81bef65eece | 1940 | ticR.detach(); |
vic20 | 1:d81bef65eece | 1941 | // Signal end |
vic20 | 1:d81bef65eece | 1942 | endTicker = 1; |
vic20 | 1:d81bef65eece | 1943 | return; |
vic20 | 1:d81bef65eece | 1944 | } |
vic20 | 0:39a545e08ccd | 1945 | |
vic20 | 0:39a545e08ccd | 1946 | // Check for overrun |
vic20 | 0:39a545e08ccd | 1947 | if (overrun) |
vic20 | 0:39a545e08ccd | 1948 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 1949 | |
vic20 | 0:39a545e08ccd | 1950 | overrun = 1; |
vic20 | 0:39a545e08ccd | 1951 | } |
vic20 | 0:39a545e08ccd | 1952 | |
vic20 | 0:39a545e08ccd | 1953 | // Wave Play |
vic20 | 0:39a545e08ccd | 1954 | void wavePlay() |
vic20 | 0:39a545e08ccd | 1955 | { |
vic20 | 0:39a545e08ccd | 1956 | PRO1_SET |
vic20 | 0:39a545e08ccd | 1957 | // Read number of waves to send |
vic20 | 1:d81bef65eece | 1958 | infiniteWave = 0; |
vic20 | 1:d81bef65eece | 1959 | w_n = getU16(); |
vic20 | 1:d81bef65eece | 1960 | if (w_n==0) |
vic20 | 1:d81bef65eece | 1961 | infiniteWave = 1; |
vic20 | 0:39a545e08ccd | 1962 | |
vic20 | 0:39a545e08ccd | 1963 | // Check of CRC |
vic20 | 0:39a545e08ccd | 1964 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 1965 | |
vic20 | 0:39a545e08ccd | 1966 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 1967 | |
vic20 | 0:39a545e08ccd | 1968 | // Configure ticker ISR |
vic20 | 0:39a545e08ccd | 1969 | endTicker = 0; // Ticker has not ended |
vic20 | 0:39a545e08ccd | 1970 | w_pos = 0; // Current wave position |
vic20 | 0:39a545e08ccd | 1971 | |
vic20 | 0:39a545e08ccd | 1972 | // Clear overrun variables |
vic20 | 0:39a545e08ccd | 1973 | overrun_error = 0; |
vic20 | 0:39a545e08ccd | 1974 | overrun = 0; |
vic20 | 0:39a545e08ccd | 1975 | |
vic20 | 0:39a545e08ccd | 1976 | // Programs the ticker |
vic20 | 0:39a545e08ccd | 1977 | ticR.attach(&wavePlayISR,stime); |
vic20 | 0:39a545e08ccd | 1978 | |
vic20 | 0:39a545e08ccd | 1979 | // Wait till end |
vic20 | 0:39a545e08ccd | 1980 | while (!endTicker) overrun = 0; |
vic20 | 0:39a545e08ccd | 1981 | |
vic20 | 0:39a545e08ccd | 1982 | PRO1_CLEAR |
vic20 | 0:39a545e08ccd | 1983 | |
vic20 | 0:39a545e08ccd | 1984 | // Response code |
vic20 | 1:d81bef65eece | 1985 | if (halt) |
vic20 | 1:d81bef65eece | 1986 | sendByte(TRAN_HALT); |
vic20 | 1:d81bef65eece | 1987 | else |
vic20 | 1:d81bef65eece | 1988 | if (overrun_error) |
vic20 | 0:39a545e08ccd | 1989 | sendByte(TRAN_OVERRUN); |
vic20 | 0:39a545e08ccd | 1990 | else |
vic20 | 0:39a545e08ccd | 1991 | sendByte(TRAN_OK); |
vic20 | 0:39a545e08ccd | 1992 | |
vic20 | 0:39a545e08ccd | 1993 | // End sending CRC |
vic20 | 0:39a545e08ccd | 1994 | sendCRC(); |
vic20 | 0:39a545e08ccd | 1995 | } |
vic20 | 0:39a545e08ccd | 1996 | |
vic20 | 0:39a545e08ccd | 1997 | /****************** DUAL WAVE PLAY CODE *************************/ |
vic20 | 0:39a545e08ccd | 1998 | |
vic20 | 0:39a545e08ccd | 1999 | // ISR for the dualWavePlay function |
vic20 | 0:39a545e08ccd | 2000 | void dualWavePlayISR() |
vic20 | 0:39a545e08ccd | 2001 | { |
vic20 | 0:39a545e08ccd | 2002 | // Write DAC (Old code) |
vic20 | 0:39a545e08ccd | 2003 | //aout1 = buff[w_pos++] / MAX16F; |
vic20 | 0:39a545e08ccd | 2004 | //aout2 = wave2buff[w_pos2++] / MAX16F; |
vic20 | 0:39a545e08ccd | 2005 | |
vic20 | 0:39a545e08ccd | 2006 | // Write DACs (New faster code) |
vic20 | 0:39a545e08ccd | 2007 | DAC->DHR12R1 = (buff[w_pos++]>>4); |
vic20 | 0:39a545e08ccd | 2008 | DAC->DHR12R2 = (wave2buff[w_pos2++]>>4); |
vic20 | 0:39a545e08ccd | 2009 | |
vic20 | 0:39a545e08ccd | 2010 | // Check primary wave rollover |
vic20 | 0:39a545e08ccd | 2011 | if (w_pos == w_s) |
vic20 | 0:39a545e08ccd | 2012 | { |
vic20 | 0:39a545e08ccd | 2013 | w_pos = 0; |
vic20 | 1:d81bef65eece | 2014 | if (!infiniteWave) |
vic20 | 1:d81bef65eece | 2015 | { |
vic20 | 1:d81bef65eece | 2016 | w_n--; |
vic20 | 1:d81bef65eece | 2017 | if (w_n <= 0) |
vic20 | 1:d81bef65eece | 2018 | { |
vic20 | 1:d81bef65eece | 2019 | // Disable ticker |
vic20 | 1:d81bef65eece | 2020 | ticR.detach(); |
vic20 | 1:d81bef65eece | 2021 | // Signal end |
vic20 | 1:d81bef65eece | 2022 | endTicker = 1; |
vic20 | 1:d81bef65eece | 2023 | } |
vic20 | 1:d81bef65eece | 2024 | } |
vic20 | 0:39a545e08ccd | 2025 | } |
vic20 | 0:39a545e08ccd | 2026 | |
vic20 | 0:39a545e08ccd | 2027 | // Check for secondary wave rollover |
vic20 | 0:39a545e08ccd | 2028 | if (w_pos2 == w_s2) w_pos2 = 0; |
vic20 | 1:d81bef65eece | 2029 | |
vic20 | 1:d81bef65eece | 2030 | // Check for halt |
vic20 | 1:d81bef65eece | 2031 | if (halt) |
vic20 | 1:d81bef65eece | 2032 | { |
vic20 | 1:d81bef65eece | 2033 | // Disable ticker |
vic20 | 1:d81bef65eece | 2034 | ticR.detach(); |
vic20 | 1:d81bef65eece | 2035 | // Signal end |
vic20 | 1:d81bef65eece | 2036 | endTicker = 1; |
vic20 | 1:d81bef65eece | 2037 | return; |
vic20 | 1:d81bef65eece | 2038 | } |
vic20 | 0:39a545e08ccd | 2039 | |
vic20 | 0:39a545e08ccd | 2040 | // Check for overrun |
vic20 | 0:39a545e08ccd | 2041 | if (overrun) |
vic20 | 0:39a545e08ccd | 2042 | overrun_error = 1; |
vic20 | 0:39a545e08ccd | 2043 | |
vic20 | 0:39a545e08ccd | 2044 | overrun = 1; |
vic20 | 0:39a545e08ccd | 2045 | } |
vic20 | 0:39a545e08ccd | 2046 | |
vic20 | 0:39a545e08ccd | 2047 | // Dual Wave Play |
vic20 | 0:39a545e08ccd | 2048 | void dualWavePlay() |
vic20 | 0:39a545e08ccd | 2049 | { |
vic20 | 1:d81bef65eece | 2050 | // Read number of waves to send |
vic20 | 1:d81bef65eece | 2051 | infiniteWave = 0; |
vic20 | 1:d81bef65eece | 2052 | w_n = getU16(); |
vic20 | 1:d81bef65eece | 2053 | if (w_n==0) |
vic20 | 1:d81bef65eece | 2054 | infiniteWave = 1; |
vic20 | 0:39a545e08ccd | 2055 | |
vic20 | 0:39a545e08ccd | 2056 | // Check of CRC |
vic20 | 0:39a545e08ccd | 2057 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2058 | |
vic20 | 0:39a545e08ccd | 2059 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2060 | |
vic20 | 0:39a545e08ccd | 2061 | // Configure ticker ISR |
vic20 | 0:39a545e08ccd | 2062 | endTicker = 0; // Ticker has not ended |
vic20 | 0:39a545e08ccd | 2063 | w_pos = 0; // Current primary wave position |
vic20 | 0:39a545e08ccd | 2064 | w_pos2 = 0; // Current secondary wave position |
vic20 | 0:39a545e08ccd | 2065 | |
vic20 | 0:39a545e08ccd | 2066 | // Clear overrun variables |
vic20 | 0:39a545e08ccd | 2067 | overrun_error = 0; |
vic20 | 0:39a545e08ccd | 2068 | overrun = 0; |
vic20 | 0:39a545e08ccd | 2069 | |
vic20 | 0:39a545e08ccd | 2070 | // Programs the ticker |
vic20 | 0:39a545e08ccd | 2071 | ticR.attach(&dualWavePlayISR,stime); |
vic20 | 0:39a545e08ccd | 2072 | |
vic20 | 0:39a545e08ccd | 2073 | // Wait till end |
vic20 | 0:39a545e08ccd | 2074 | while (!endTicker) overrun = 0; |
vic20 | 0:39a545e08ccd | 2075 | |
vic20 | 0:39a545e08ccd | 2076 | // Response code |
vic20 | 1:d81bef65eece | 2077 | if (halt) |
vic20 | 1:d81bef65eece | 2078 | sendByte(TRAN_HALT); |
vic20 | 1:d81bef65eece | 2079 | else |
vic20 | 1:d81bef65eece | 2080 | if (overrun_error) |
vic20 | 0:39a545e08ccd | 2081 | sendByte(TRAN_OVERRUN); |
vic20 | 0:39a545e08ccd | 2082 | else |
vic20 | 0:39a545e08ccd | 2083 | sendByte(TRAN_OK); |
vic20 | 0:39a545e08ccd | 2084 | |
vic20 | 0:39a545e08ccd | 2085 | // End sending CRC |
vic20 | 0:39a545e08ccd | 2086 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2087 | } |
vic20 | 0:39a545e08ccd | 2088 | |
vic20 | 0:39a545e08ccd | 2089 | /***************** DC DIGITAL IO *********************************/ |
vic20 | 0:39a545e08ccd | 2090 | |
vic20 | 0:39a545e08ccd | 2091 | // Digital IO mode |
vic20 | 0:39a545e08ccd | 2092 | void dioMode() |
vic20 | 0:39a545e08ccd | 2093 | { |
vic20 | 0:39a545e08ccd | 2094 | int line,mode,error; |
vic20 | 0:39a545e08ccd | 2095 | |
vic20 | 0:39a545e08ccd | 2096 | // Read line to configure |
vic20 | 0:39a545e08ccd | 2097 | line = getByte(); |
vic20 | 0:39a545e08ccd | 2098 | |
vic20 | 0:39a545e08ccd | 2099 | // Read mode to set |
vic20 | 0:39a545e08ccd | 2100 | mode = getByte(); |
vic20 | 0:39a545e08ccd | 2101 | |
vic20 | 0:39a545e08ccd | 2102 | // Check of CRC |
vic20 | 0:39a545e08ccd | 2103 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2104 | |
vic20 | 0:39a545e08ccd | 2105 | // No error for now |
vic20 | 0:39a545e08ccd | 2106 | error = 0; |
vic20 | 0:39a545e08ccd | 2107 | |
vic20 | 0:39a545e08ccd | 2108 | // Check line number |
vic20 | 0:39a545e08ccd | 2109 | if ((line <= 0)||(line > NDIO)) error = 1; |
vic20 | 0:39a545e08ccd | 2110 | |
vic20 | 0:39a545e08ccd | 2111 | // Set dio mode |
vic20 | 0:39a545e08ccd | 2112 | if (!error) |
vic20 | 0:39a545e08ccd | 2113 | switch(mode) |
vic20 | 0:39a545e08ccd | 2114 | { |
vic20 | 0:39a545e08ccd | 2115 | case 10: |
vic20 | 0:39a545e08ccd | 2116 | dioList[line-1]->input(); |
vic20 | 0:39a545e08ccd | 2117 | dioList[line-1]->mode(PullNone); |
vic20 | 0:39a545e08ccd | 2118 | break; |
vic20 | 0:39a545e08ccd | 2119 | case 11: |
vic20 | 0:39a545e08ccd | 2120 | dioList[line-1]->input(); |
vic20 | 0:39a545e08ccd | 2121 | dioList[line-1]->mode(PullUp); |
vic20 | 0:39a545e08ccd | 2122 | break; |
vic20 | 0:39a545e08ccd | 2123 | case 12: |
vic20 | 0:39a545e08ccd | 2124 | dioList[line-1]->input(); |
vic20 | 0:39a545e08ccd | 2125 | dioList[line-1]->mode(PullDown); |
vic20 | 0:39a545e08ccd | 2126 | break; |
vic20 | 0:39a545e08ccd | 2127 | case 20: |
vic20 | 0:39a545e08ccd | 2128 | dioList[line-1]->mode(PullNone); |
vic20 | 0:39a545e08ccd | 2129 | dioList[line-1]->output(); |
vic20 | 0:39a545e08ccd | 2130 | break; |
vic20 | 0:39a545e08ccd | 2131 | // case 21: |
vic20 | 0:39a545e08ccd | 2132 | // dioList[line-1]->mode(OpenDrain); |
vic20 | 0:39a545e08ccd | 2133 | // dioList[line-1]->output(); |
vic20 | 0:39a545e08ccd | 2134 | // break; |
vic20 | 0:39a545e08ccd | 2135 | default: |
vic20 | 0:39a545e08ccd | 2136 | error = 1; |
vic20 | 0:39a545e08ccd | 2137 | break; |
vic20 | 0:39a545e08ccd | 2138 | } |
vic20 | 0:39a545e08ccd | 2139 | |
vic20 | 0:39a545e08ccd | 2140 | if (error) |
vic20 | 0:39a545e08ccd | 2141 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 2142 | else |
vic20 | 0:39a545e08ccd | 2143 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2144 | |
vic20 | 0:39a545e08ccd | 2145 | // End sending CRC |
vic20 | 0:39a545e08ccd | 2146 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2147 | } |
vic20 | 0:39a545e08ccd | 2148 | |
vic20 | 0:39a545e08ccd | 2149 | // Digital Write |
vic20 | 0:39a545e08ccd | 2150 | void dioWrite() |
vic20 | 0:39a545e08ccd | 2151 | { |
vic20 | 0:39a545e08ccd | 2152 | int line,value; |
vic20 | 0:39a545e08ccd | 2153 | |
vic20 | 0:39a545e08ccd | 2154 | // Read line to write |
vic20 | 0:39a545e08ccd | 2155 | line = getByte(); |
vic20 | 0:39a545e08ccd | 2156 | |
vic20 | 0:39a545e08ccd | 2157 | // Value to set |
vic20 | 0:39a545e08ccd | 2158 | value = getByte(); |
vic20 | 0:39a545e08ccd | 2159 | |
vic20 | 0:39a545e08ccd | 2160 | // Check of CRC |
vic20 | 0:39a545e08ccd | 2161 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2162 | |
vic20 | 0:39a545e08ccd | 2163 | // Check line number |
vic20 | 0:39a545e08ccd | 2164 | if ((line <= 0)||(line > NDIO)) |
vic20 | 0:39a545e08ccd | 2165 | { |
vic20 | 0:39a545e08ccd | 2166 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 2167 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2168 | return; |
vic20 | 0:39a545e08ccd | 2169 | } |
vic20 | 0:39a545e08ccd | 2170 | |
vic20 | 0:39a545e08ccd | 2171 | // Set dio value |
vic20 | 0:39a545e08ccd | 2172 | dioList[line-1]->write(value); |
vic20 | 0:39a545e08ccd | 2173 | |
vic20 | 0:39a545e08ccd | 2174 | // Send ACK and CRC |
vic20 | 0:39a545e08ccd | 2175 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2176 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2177 | } |
vic20 | 0:39a545e08ccd | 2178 | |
vic20 | 0:39a545e08ccd | 2179 | // Digital Read |
vic20 | 0:39a545e08ccd | 2180 | void dioRead() |
vic20 | 0:39a545e08ccd | 2181 | { |
vic20 | 0:39a545e08ccd | 2182 | int line,value; |
vic20 | 0:39a545e08ccd | 2183 | |
vic20 | 0:39a545e08ccd | 2184 | // Read line to read |
vic20 | 0:39a545e08ccd | 2185 | line = getByte(); |
vic20 | 0:39a545e08ccd | 2186 | |
vic20 | 0:39a545e08ccd | 2187 | // Check of CRC |
vic20 | 0:39a545e08ccd | 2188 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2189 | |
vic20 | 0:39a545e08ccd | 2190 | // Check line number |
vic20 | 0:39a545e08ccd | 2191 | if ((line <= 0)||(line > NDIO)) |
vic20 | 0:39a545e08ccd | 2192 | { |
vic20 | 0:39a545e08ccd | 2193 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 2194 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2195 | return; |
vic20 | 0:39a545e08ccd | 2196 | } |
vic20 | 0:39a545e08ccd | 2197 | |
vic20 | 0:39a545e08ccd | 2198 | // Send ACK |
vic20 | 0:39a545e08ccd | 2199 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2200 | |
vic20 | 0:39a545e08ccd | 2201 | // Read and send dio value |
vic20 | 0:39a545e08ccd | 2202 | value=dioList[line-1]->read(); |
vic20 | 0:39a545e08ccd | 2203 | if (value) |
vic20 | 0:39a545e08ccd | 2204 | sendByte(1); |
vic20 | 0:39a545e08ccd | 2205 | else |
vic20 | 0:39a545e08ccd | 2206 | sendByte(0); |
vic20 | 0:39a545e08ccd | 2207 | |
vic20 | 0:39a545e08ccd | 2208 | // Send CRC |
vic20 | 0:39a545e08ccd | 2209 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2210 | } |
vic20 | 0:39a545e08ccd | 2211 | |
vic20 | 0:39a545e08ccd | 2212 | /***************** MAIN LOOP CODE ********************************/ |
vic20 | 0:39a545e08ccd | 2213 | |
vic20 | 0:39a545e08ccd | 2214 | // Soft reset |
vic20 | 0:39a545e08ccd | 2215 | // Put the system in default reset state |
vic20 | 0:39a545e08ccd | 2216 | void softReset(void) |
vic20 | 0:39a545e08ccd | 2217 | { |
vic20 | 0:39a545e08ccd | 2218 | int i; |
vic20 | 0:39a545e08ccd | 2219 | |
vic20 | 0:39a545e08ccd | 2220 | // Sample time period defaults to 1ms |
vic20 | 0:39a545e08ccd | 2221 | stime = 0.001; |
vic20 | 0:39a545e08ccd | 2222 | |
vic20 | 0:39a545e08ccd | 2223 | // Set number of DC readings to 10 |
vic20 | 0:39a545e08ccd | 2224 | nread = 10; |
vic20 | 0:39a545e08ccd | 2225 | |
vic20 | 0:39a545e08ccd | 2226 | // Input configuration |
vic20 | 0:39a545e08ccd | 2227 | n_ai = 1; // Number of analog inputs |
vic20 | 0:39a545e08ccd | 2228 | n_di = 0; // Number of digital inputs (always zero) |
vic20 | 0:39a545e08ccd | 2229 | n_s = 1000; // Number of samples |
vic20 | 0:39a545e08ccd | 2230 | |
vic20 | 0:39a545e08ccd | 2231 | // Eliminate wavetables |
vic20 | 0:39a545e08ccd | 2232 | w_s = 0; |
vic20 | 0:39a545e08ccd | 2233 | w_s2 = 0; |
vic20 | 0:39a545e08ccd | 2234 | |
vic20 | 0:39a545e08ccd | 2235 | // Initialize unified memory |
vic20 | 0:39a545e08ccd | 2236 | wave2buff = buff; |
vic20 | 0:39a545e08ccd | 2237 | tranBuff = buff; |
vic20 | 0:39a545e08ccd | 2238 | |
vic20 | 0:39a545e08ccd | 2239 | // Set DACs to zero |
vic20 | 0:39a545e08ccd | 2240 | aout1 = 0.0; |
vic20 | 0:39a545e08ccd | 2241 | aout2 = 0.0; |
vic20 | 0:39a545e08ccd | 2242 | |
vic20 | 0:39a545e08ccd | 2243 | // Fill ain list |
vic20 | 0:39a545e08ccd | 2244 | ainList[0]=&ain1; |
vic20 | 0:39a545e08ccd | 2245 | ainList[1]=&ain2; |
vic20 | 0:39a545e08ccd | 2246 | ainList[2]=&ain3; |
vic20 | 0:39a545e08ccd | 2247 | ainList[3]=&ain4; |
vic20 | 0:39a545e08ccd | 2248 | |
vic20 | 0:39a545e08ccd | 2249 | // Configure DIO |
vic20 | 0:39a545e08ccd | 2250 | #ifdef EXIST_DIO |
vic20 | 0:39a545e08ccd | 2251 | // Setup dioList |
vic20 | 0:39a545e08ccd | 2252 | dioList[0]=&dio1; |
vic20 | 0:39a545e08ccd | 2253 | dioList[1]=&dio2; |
vic20 | 0:39a545e08ccd | 2254 | dioList[2]=&dio3; |
vic20 | 0:39a545e08ccd | 2255 | dioList[3]=&dio4; |
vic20 | 0:39a545e08ccd | 2256 | dioList[4]=&dio5; |
vic20 | 0:39a545e08ccd | 2257 | dioList[5]=&dio6; |
vic20 | 0:39a545e08ccd | 2258 | dioList[6]=&dio7; |
vic20 | 0:39a545e08ccd | 2259 | dioList[7]=&dio8; |
vic20 | 0:39a545e08ccd | 2260 | // Default configuration |
vic20 | 0:39a545e08ccd | 2261 | for(i=0;i<NDIO;i++) |
vic20 | 0:39a545e08ccd | 2262 | { |
vic20 | 0:39a545e08ccd | 2263 | dioList[i]->mode(PullNone); |
vic20 | 0:39a545e08ccd | 2264 | dioList[i]->input(); |
vic20 | 0:39a545e08ccd | 2265 | } |
vic20 | 0:39a545e08ccd | 2266 | #endif |
vic20 | 0:39a545e08ccd | 2267 | } |
vic20 | 0:39a545e08ccd | 2268 | |
vic20 | 1:d81bef65eece | 2269 | |
vic20 | 1:d81bef65eece | 2270 | // Halt funcion |
vic20 | 1:d81bef65eece | 2271 | // Called when the halt interrupt is generated |
vic20 | 1:d81bef65eece | 2272 | void haltFunction() |
vic20 | 1:d81bef65eece | 2273 | { |
vic20 | 1:d81bef65eece | 2274 | halt=1; // Just turn on the halt flag |
vic20 | 1:d81bef65eece | 2275 | } |
vic20 | 1:d81bef65eece | 2276 | |
vic20 | 0:39a545e08ccd | 2277 | // Process one character received from the PC |
vic20 | 0:39a545e08ccd | 2278 | void process(int car) |
vic20 | 0:39a545e08ccd | 2279 | { |
vic20 | 0:39a545e08ccd | 2280 | int i; |
vic20 | 0:39a545e08ccd | 2281 | uint16_t value; |
vic20 | 0:39a545e08ccd | 2282 | |
vic20 | 0:39a545e08ccd | 2283 | // Initialize Tx CRC |
vic20 | 0:39a545e08ccd | 2284 | startTx(); |
vic20 | 0:39a545e08ccd | 2285 | |
vic20 | 0:39a545e08ccd | 2286 | switch(car) |
vic20 | 0:39a545e08ccd | 2287 | { |
vic20 | 0:39a545e08ccd | 2288 | case 'F': // Get firmware string |
vic20 | 0:39a545e08ccd | 2289 | sendString(BSTRING); |
vic20 | 0:39a545e08ccd | 2290 | sendString(VSTRING); |
vic20 | 0:39a545e08ccd | 2291 | sendString("\n\r"); |
vic20 | 0:39a545e08ccd | 2292 | break; |
vic20 | 0:39a545e08ccd | 2293 | case 'M': // Get magic |
vic20 | 0:39a545e08ccd | 2294 | // Check CRC of command. Returns 1 if Ok |
vic20 | 0:39a545e08ccd | 2295 | // On error Sends ECRC + CRC and return 0 |
vic20 | 0:39a545e08ccd | 2296 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2297 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2298 | // Send magic |
vic20 | 0:39a545e08ccd | 2299 | for(i=0;i<MAGIC_SIZE;i++) |
vic20 | 0:39a545e08ccd | 2300 | sendByte(magic[i]); |
vic20 | 0:39a545e08ccd | 2301 | // Send CRC |
vic20 | 0:39a545e08ccd | 2302 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2303 | break; |
vic20 | 0:39a545e08ccd | 2304 | case 'I': // Get board capabilities |
vic20 | 0:39a545e08ccd | 2305 | // Check CRC of command. Returns 1 if Ok |
vic20 | 0:39a545e08ccd | 2306 | // On error Sends ECRC + CRC and return 0 |
vic20 | 0:39a545e08ccd | 2307 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2308 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2309 | |
vic20 | 0:39a545e08ccd | 2310 | sendByte(NDACS); // 1 |
vic20 | 0:39a545e08ccd | 2311 | sendByte(NADCS); // 2 |
vic20 | 0:39a545e08ccd | 2312 | sendU16(BSIZE); // 4 Buffer |
vic20 | 0:39a545e08ccd | 2313 | sendMantExp(MAX_S_M,MAX_S_E); // 7 |
vic20 | 0:39a545e08ccd | 2314 | sendMantExp(MIN_S_M,MIN_S_E); // 10 |
vic20 | 0:39a545e08ccd | 2315 | sendMantExp(VDD_M,VDD_E); // 13 |
vic20 | 0:39a545e08ccd | 2316 | sendMantExp(MAX_SF_M,MAX_SF_E); // 16 |
vic20 | 0:39a545e08ccd | 2317 | sendMantExp(VREF_M,VREF_E); // 29 |
vic20 | 0:39a545e08ccd | 2318 | sendByte(DAC_BITS); // 20 |
vic20 | 0:39a545e08ccd | 2319 | sendByte(ADC_BITS); // 21 |
vic20 | 0:39a545e08ccd | 2320 | sendByte(NDIO); // 22 |
vic20 | 0:39a545e08ccd | 2321 | sendByte(resetState); // 23 |
vic20 | 0:39a545e08ccd | 2322 | |
vic20 | 0:39a545e08ccd | 2323 | // Send CRC |
vic20 | 0:39a545e08ccd | 2324 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2325 | break; |
vic20 | 0:39a545e08ccd | 2326 | case 'L' : // Send pin list |
vic20 | 0:39a545e08ccd | 2327 | // Check CRC of command. Returns 1 if Ok |
vic20 | 0:39a545e08ccd | 2328 | // On error Sends ECRC + CRC and return 0 |
vic20 | 0:39a545e08ccd | 2329 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2330 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2331 | |
vic20 | 0:39a545e08ccd | 2332 | sendString(PIN_LIST); |
vic20 | 0:39a545e08ccd | 2333 | |
vic20 | 0:39a545e08ccd | 2334 | // Send CRC |
vic20 | 0:39a545e08ccd | 2335 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2336 | break; |
vic20 | 0:39a545e08ccd | 2337 | |
vic20 | 0:39a545e08ccd | 2338 | |
vic20 | 0:39a545e08ccd | 2339 | case 'A' : // ADC Read |
vic20 | 0:39a545e08ccd | 2340 | i = getByte(); // Channel to read |
vic20 | 0:39a545e08ccd | 2341 | // Check CRC of command. Returns 1 if Ok |
vic20 | 0:39a545e08ccd | 2342 | // On error Sends ECRC + CRC and return 0 |
vic20 | 0:39a545e08ccd | 2343 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2344 | |
vic20 | 0:39a545e08ccd | 2345 | /* |
vic20 | 0:39a545e08ccd | 2346 | switch(i) |
vic20 | 0:39a545e08ccd | 2347 | { |
vic20 | 0:39a545e08ccd | 2348 | case 1: |
vic20 | 0:39a545e08ccd | 2349 | value = ain1.read_u16(); // Two reads |
vic20 | 0:39a545e08ccd | 2350 | value = ain1.read_u16(); |
vic20 | 0:39a545e08ccd | 2351 | break; |
vic20 | 0:39a545e08ccd | 2352 | case 2: |
vic20 | 0:39a545e08ccd | 2353 | value = ain2.read_u16(); // Two reads |
vic20 | 0:39a545e08ccd | 2354 | value = ain2.read_u16(); |
vic20 | 0:39a545e08ccd | 2355 | break; |
vic20 | 0:39a545e08ccd | 2356 | case 3: |
vic20 | 0:39a545e08ccd | 2357 | value = ain3.read_u16(); // Two reads |
vic20 | 0:39a545e08ccd | 2358 | value = ain3.read_u16(); |
vic20 | 0:39a545e08ccd | 2359 | break; |
vic20 | 0:39a545e08ccd | 2360 | case 4: |
vic20 | 0:39a545e08ccd | 2361 | value = ain4.read_u16(); // Two reads |
vic20 | 0:39a545e08ccd | 2362 | value = ain4.read_u16(); |
vic20 | 0:39a545e08ccd | 2363 | break; |
vic20 | 0:39a545e08ccd | 2364 | default: |
vic20 | 0:39a545e08ccd | 2365 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 2366 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2367 | return; |
vic20 | 0:39a545e08ccd | 2368 | } |
vic20 | 0:39a545e08ccd | 2369 | */ |
vic20 | 0:39a545e08ccd | 2370 | if ((i<1)||(i>NADCS)) |
vic20 | 0:39a545e08ccd | 2371 | { |
vic20 | 0:39a545e08ccd | 2372 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 2373 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2374 | return; |
vic20 | 0:39a545e08ccd | 2375 | } |
vic20 | 0:39a545e08ccd | 2376 | |
vic20 | 0:39a545e08ccd | 2377 | value = analogRead(i); |
vic20 | 0:39a545e08ccd | 2378 | |
vic20 | 0:39a545e08ccd | 2379 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2380 | sendU16(value); |
vic20 | 0:39a545e08ccd | 2381 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2382 | break; |
vic20 | 0:39a545e08ccd | 2383 | |
vic20 | 0:39a545e08ccd | 2384 | case 'D' : // DAC Write |
vic20 | 0:39a545e08ccd | 2385 | i = getByte(); // Channel to write |
vic20 | 0:39a545e08ccd | 2386 | value = getU16(); // Read value to set |
vic20 | 0:39a545e08ccd | 2387 | // Check CRC of command. Returns 1 if Ok |
vic20 | 0:39a545e08ccd | 2388 | // On error Sends ECRC + CRC and return 0 |
vic20 | 0:39a545e08ccd | 2389 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2390 | switch(i) |
vic20 | 0:39a545e08ccd | 2391 | { |
vic20 | 0:39a545e08ccd | 2392 | case 1: |
vic20 | 0:39a545e08ccd | 2393 | aout1 = value / MAX16F; // Scale to float and send |
vic20 | 0:39a545e08ccd | 2394 | break; |
vic20 | 0:39a545e08ccd | 2395 | case 2: |
vic20 | 0:39a545e08ccd | 2396 | aout2 = value / MAX16F; // Scale to float and send |
vic20 | 0:39a545e08ccd | 2397 | break; |
vic20 | 0:39a545e08ccd | 2398 | #ifdef EXIST_DAC3 |
vic20 | 0:39a545e08ccd | 2399 | case 3: |
vic20 | 0:39a545e08ccd | 2400 | aout3 = value / MAX16F; // Scale to float and send |
vic20 | 0:39a545e08ccd | 2401 | break; |
vic20 | 0:39a545e08ccd | 2402 | #endif |
vic20 | 0:39a545e08ccd | 2403 | default: |
vic20 | 0:39a545e08ccd | 2404 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 2405 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2406 | return; |
vic20 | 0:39a545e08ccd | 2407 | } |
vic20 | 0:39a545e08ccd | 2408 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2409 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2410 | resetState=0; // State change |
vic20 | 0:39a545e08ccd | 2411 | break; |
vic20 | 0:39a545e08ccd | 2412 | |
vic20 | 0:39a545e08ccd | 2413 | case 'R': // Set sample period time |
vic20 | 0:39a545e08ccd | 2414 | setSampleTime(); |
vic20 | 0:39a545e08ccd | 2415 | resetState=0; // State change |
vic20 | 0:39a545e08ccd | 2416 | break; |
vic20 | 0:39a545e08ccd | 2417 | case 'S': // Set Storage |
vic20 | 0:39a545e08ccd | 2418 | setStorage(); |
vic20 | 0:39a545e08ccd | 2419 | resetState=0; // State change |
vic20 | 0:39a545e08ccd | 2420 | break; |
vic20 | 0:39a545e08ccd | 2421 | case 'Y': // Async Read |
vic20 | 0:39a545e08ccd | 2422 | asyncRead(); |
vic20 | 0:39a545e08ccd | 2423 | break; |
vic20 | 0:39a545e08ccd | 2424 | case 'G': // Triggered Read |
vic20 | 0:39a545e08ccd | 2425 | triggeredRead(); |
vic20 | 0:39a545e08ccd | 2426 | break; |
vic20 | 0:39a545e08ccd | 2427 | case 'P': // Step response |
vic20 | 0:39a545e08ccd | 2428 | stepResponse(); |
vic20 | 0:39a545e08ccd | 2429 | break; |
vic20 | 0:39a545e08ccd | 2430 | |
vic20 | 0:39a545e08ccd | 2431 | case 'W': // Load wavetable |
vic20 | 0:39a545e08ccd | 2432 | loadWaveTable(); |
vic20 | 0:39a545e08ccd | 2433 | resetState=0; // State change |
vic20 | 0:39a545e08ccd | 2434 | break; |
vic20 | 0:39a545e08ccd | 2435 | case 'w': // Load secondary wavetable |
vic20 | 0:39a545e08ccd | 2436 | loadSecondaryWaveTable(); |
vic20 | 0:39a545e08ccd | 2437 | resetState=0; // State change |
vic20 | 0:39a545e08ccd | 2438 | break; |
vic20 | 0:39a545e08ccd | 2439 | case 'V': // Wave response |
vic20 | 0:39a545e08ccd | 2440 | waveResponse(); |
vic20 | 0:39a545e08ccd | 2441 | break; |
vic20 | 0:39a545e08ccd | 2442 | case 'v': // Dual wave response |
vic20 | 0:39a545e08ccd | 2443 | dualWaveResponse(); |
vic20 | 0:39a545e08ccd | 2444 | break; |
vic20 | 0:39a545e08ccd | 2445 | case 'X': // Single Wave response |
vic20 | 0:39a545e08ccd | 2446 | singleWaveResponse(); |
vic20 | 0:39a545e08ccd | 2447 | break; |
vic20 | 0:39a545e08ccd | 2448 | case 'Q': // Wave Play |
vic20 | 0:39a545e08ccd | 2449 | wavePlay(); |
vic20 | 0:39a545e08ccd | 2450 | break; |
vic20 | 0:39a545e08ccd | 2451 | case 'q': // Wave Play |
vic20 | 0:39a545e08ccd | 2452 | dualWavePlay(); |
vic20 | 0:39a545e08ccd | 2453 | break; |
vic20 | 0:39a545e08ccd | 2454 | |
vic20 | 0:39a545e08ccd | 2455 | case 'E': // Soft Reset |
vic20 | 0:39a545e08ccd | 2456 | if (!crcResponse()) return; |
vic20 | 0:39a545e08ccd | 2457 | |
vic20 | 0:39a545e08ccd | 2458 | softReset(); |
vic20 | 0:39a545e08ccd | 2459 | resetState=1; // Return to reset state |
vic20 | 0:39a545e08ccd | 2460 | |
vic20 | 0:39a545e08ccd | 2461 | sendByte(ACK); |
vic20 | 0:39a545e08ccd | 2462 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2463 | break; |
vic20 | 0:39a545e08ccd | 2464 | |
vic20 | 0:39a545e08ccd | 2465 | case 'H': // DIO mode |
vic20 | 0:39a545e08ccd | 2466 | dioMode(); |
vic20 | 0:39a545e08ccd | 2467 | resetState=0; // State change |
vic20 | 0:39a545e08ccd | 2468 | break; |
vic20 | 0:39a545e08ccd | 2469 | case 'J': // DIO Write |
vic20 | 0:39a545e08ccd | 2470 | dioWrite(); |
vic20 | 0:39a545e08ccd | 2471 | resetState=0; // State change |
vic20 | 0:39a545e08ccd | 2472 | break; |
vic20 | 0:39a545e08ccd | 2473 | case 'K': // DIO Read |
vic20 | 0:39a545e08ccd | 2474 | dioRead(); |
vic20 | 0:39a545e08ccd | 2475 | break; |
vic20 | 0:39a545e08ccd | 2476 | |
vic20 | 0:39a545e08ccd | 2477 | case 'N': // Number of reads in DC |
vic20 | 0:39a545e08ccd | 2478 | value = getU16(); // Read value to set |
vic20 | 0:39a545e08ccd | 2479 | if (!crcResponse()) return; // Check CRC |
vic20 | 0:39a545e08ccd | 2480 | if (value==0) value=1; // At least it shall be one |
vic20 | 0:39a545e08ccd | 2481 | nread = value; |
vic20 | 0:39a545e08ccd | 2482 | sendByte(ACK); // Send ACK and CRC |
vic20 | 0:39a545e08ccd | 2483 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2484 | resetState=0; // State change |
vic20 | 0:39a545e08ccd | 2485 | break; |
vic20 | 0:39a545e08ccd | 2486 | |
vic20 | 0:39a545e08ccd | 2487 | default: |
vic20 | 0:39a545e08ccd | 2488 | // Unknown command |
vic20 | 0:39a545e08ccd | 2489 | sendByte(NACK); |
vic20 | 0:39a545e08ccd | 2490 | sendCRC(); |
vic20 | 0:39a545e08ccd | 2491 | break; |
vic20 | 0:39a545e08ccd | 2492 | } |
vic20 | 0:39a545e08ccd | 2493 | } |
vic20 | 0:39a545e08ccd | 2494 | |
vic20 | 0:39a545e08ccd | 2495 | int main() |
vic20 | 0:39a545e08ccd | 2496 | { |
vic20 | 0:39a545e08ccd | 2497 | int car; |
vic20 | 0:39a545e08ccd | 2498 | |
vic20 | 0:39a545e08ccd | 2499 | // Generate soft reset |
vic20 | 0:39a545e08ccd | 2500 | softReset(); |
vic20 | 0:39a545e08ccd | 2501 | |
vic20 | 0:39a545e08ccd | 2502 | pc.printf("%s%s\n\r",BSTRING,VSTRING); |
vic20 | 0:39a545e08ccd | 2503 | |
vic20 | 0:39a545e08ccd | 2504 | // Reset profile lines (if enabled) |
vic20 | 0:39a545e08ccd | 2505 | PRO1_CLEAR |
vic20 | 0:39a545e08ccd | 2506 | PRO2_CLEAR |
vic20 | 0:39a545e08ccd | 2507 | |
vic20 | 1:d81bef65eece | 2508 | // Program halt interrupt (if enabled) |
vic20 | 1:d81bef65eece | 2509 | #ifdef HALT_PIN |
vic20 | 1:d81bef65eece | 2510 | #ifdef HALT_RISING |
vic20 | 1:d81bef65eece | 2511 | haltInt.rise(&haltFunction); |
vic20 | 1:d81bef65eece | 2512 | #else |
vic20 | 1:d81bef65eece | 2513 | haltInt.fall(&haltFunction); |
vic20 | 1:d81bef65eece | 2514 | #endif |
vic20 | 1:d81bef65eece | 2515 | #endif |
vic20 | 1:d81bef65eece | 2516 | |
vic20 | 0:39a545e08ccd | 2517 | // New ADC code |
vic20 | 0:39a545e08ccd | 2518 | //adc_init(); |
vic20 | 0:39a545e08ccd | 2519 | |
vic20 | 0:39a545e08ccd | 2520 | // Loop that processes each received char |
vic20 | 0:39a545e08ccd | 2521 | while(1) |
vic20 | 0:39a545e08ccd | 2522 | { |
vic20 | 0:39a545e08ccd | 2523 | startRx(); // Init Rx CRC |
vic20 | 0:39a545e08ccd | 2524 | car = getByte(); // Get command |
vic20 | 1:d81bef65eece | 2525 | halt = 0; // Remove halt condition if present |
vic20 | 0:39a545e08ccd | 2526 | process(car); // Process command |
vic20 | 0:39a545e08ccd | 2527 | } |
vic20 | 0:39a545e08ccd | 2528 | } |
vic20 | 0:39a545e08ccd | 2529 | |
vic20 | 0:39a545e08ccd | 2530 |