Firmware for Nucleo boards for the SLab system Description at http://r6500.blogspot.com.es/2018/02/slab-first-release.html All associated files at https://github.com/R6500/SLab
Nucleo64-L152RE.h@1:d81bef65eece, 2018-02-11 (annotated)
- Committer:
- vic20
- Date:
- Sun Feb 11 16:14:51 2018 +0000
- Revision:
- 1:d81bef65eece
- Parent:
- 0:39a545e08ccd
Version 1.2 (Halt button added)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
vic20 | 0:39a545e08ccd | 1 | /*********************************************************************** |
vic20 | 0:39a545e08ccd | 2 | |
vic20 | 0:39a545e08ccd | 3 | Header file for the Nucleo64 L152RE Board |
vic20 | 0:39a545e08ccd | 4 | |
vic20 | 1:d81bef65eece | 5 | MBED page for the board: |
vic20 | 1:d81bef65eece | 6 | https://os.mbed.com/platforms/ST-Nucleo-L152RE/ |
vic20 | 1:d81bef65eece | 7 | |
vic20 | 0:39a545e08ccd | 8 | Basic requirements for a board are: |
vic20 | 0:39a545e08ccd | 9 | MBED Compatible |
vic20 | 0:39a545e08ccd | 10 | 2 DACs or more |
vic20 | 0:39a545e08ccd | 11 | 4 ADCs or more |
vic20 | 0:39a545e08ccd | 12 | That includes the following Nucleo Boards |
vic20 | 0:39a545e08ccd | 13 | |
vic20 | 0:39a545e08ccd | 14 | Board DACs Flash RAM |
vic20 | 0:39a545e08ccd | 15 | Nucleo64-F303RE 2* 512k 64k + 16k |
vic20 | 0:39a545e08ccd | 16 | Nucleo64-L152RE 2* 512k 80k (This board) |
vic20 | 0:39a545e08ccd | 17 | Nucleo32-F303K8 3 64k 12k + 4k |
vic20 | 0:39a545e08ccd | 18 | Nucleo64-F072RB 2 128k 16k |
vic20 | 0:39a545e08ccd | 19 | Nucleo64-F091RC 2 256k 32k |
vic20 | 0:39a545e08ccd | 20 | Nucleo64-F334R8 3 64k 12k + 4k |
vic20 | 0:39a545e08ccd | 21 | Nucleo64-F446RE 2 512k 128k |
vic20 | 0:39a545e08ccd | 22 | Nucleo64-L073RZ 2 192k 20k |
vic20 | 0:39a545e08ccd | 23 | Nucleo64-L476RG 2 1M 128k |
vic20 | 0:39a545e08ccd | 24 | |
vic20 | 0:39a545e08ccd | 25 | (*) In DACs mean that one DAC has reduced range because |
vic20 | 0:39a545e08ccd | 26 | it is connected to the board LCD |
vic20 | 0:39a545e08ccd | 27 | |
vic20 | 0:39a545e08ccd | 28 | (*) In DACs mean that one DAC has reduced range because |
vic20 | 0:39a545e08ccd | 29 | it is connected to the board LCD |
vic20 | 0:39a545e08ccd | 30 | |
vic20 | 0:39a545e08ccd | 31 | History: |
vic20 | 0:39a545e08ccd | 32 | |
vic20 | 0:39a545e08ccd | 33 | 2017/02/24 : First version |
vic20 | 0:39a545e08ccd | 34 | |
vic20 | 0:39a545e08ccd | 35 | **********************************************************************/ |
vic20 | 0:39a545e08ccd | 36 | |
vic20 | 0:39a545e08ccd | 37 | #define BSTRING "Nucleo64-L152RE SLab" |
vic20 | 0:39a545e08ccd | 38 | |
vic20 | 0:39a545e08ccd | 39 | #define F_SIZE 512 |
vic20 | 0:39a545e08ccd | 40 | #define R_SIZE 64 |
vic20 | 0:39a545e08ccd | 41 | |
vic20 | 0:39a545e08ccd | 42 | // ADCs |
vic20 | 0:39a545e08ccd | 43 | |
vic20 | 0:39a545e08ccd | 44 | #define AD1 A0 |
vic20 | 0:39a545e08ccd | 45 | #define AD2 A1 |
vic20 | 0:39a545e08ccd | 46 | #define AD3 A4 |
vic20 | 0:39a545e08ccd | 47 | #define AD4 A5 |
vic20 | 0:39a545e08ccd | 48 | |
vic20 | 1:d81bef65eece | 49 | //#define FAST_ADC // Non Optimized code for single readings |
vic20 | 1:d81bef65eece | 50 | |
vic20 | 0:39a545e08ccd | 51 | // DACs |
vic20 | 0:39a545e08ccd | 52 | #define DA1 A2 |
vic20 | 0:39a545e08ccd | 53 | #define DA2 D13 |
vic20 | 0:39a545e08ccd | 54 | //#define EXIST_DAC3 |
vic20 | 0:39a545e08ccd | 55 | |
vic20 | 1:d81bef65eece | 56 | // Digital I/O |
vic20 | 1:d81bef65eece | 57 | #define EXIST_DIO |
vic20 | 1:d81bef65eece | 58 | #define DIO1 D2 |
vic20 | 1:d81bef65eece | 59 | #define DIO2 D3 |
vic20 | 1:d81bef65eece | 60 | #define DIO3 D4 |
vic20 | 1:d81bef65eece | 61 | #define DIO4 D5 |
vic20 | 1:d81bef65eece | 62 | #define DIO5 D6 |
vic20 | 1:d81bef65eece | 63 | #define DIO6 D7 |
vic20 | 1:d81bef65eece | 64 | #define DIO7 D8 |
vic20 | 1:d81bef65eece | 65 | #define DIO8 D9 |
vic20 | 1:d81bef65eece | 66 | |
vic20 | 0:39a545e08ccd | 67 | // Board capabilities implemented in firmware |
vic20 | 0:39a545e08ccd | 68 | #define NDACS 2 // Number of DACs |
vic20 | 0:39a545e08ccd | 69 | #define NADCS 4 // Number of ADCs |
vic20 | 0:39a545e08ccd | 70 | #define BSIZE 18000 // Unified buffer size (in samples) |
vic20 | 0:39a545e08ccd | 71 | #define MAX_STIME 100.0f // Maximum sample period is 100s |
vic20 | 0:39a545e08ccd | 72 | #define MAX_S_M 100 // Mantissa |
vic20 | 0:39a545e08ccd | 73 | #define MAX_S_E 0 // Exponent |
vic20 | 0:39a545e08ccd | 74 | #define MIN_STIME 0.000050f // Minimum sample period is 50us |
vic20 | 0:39a545e08ccd | 75 | #define MIN_S_M 50 // Mantissa |
vic20 | 0:39a545e08ccd | 76 | #define MIN_S_E -6 // Exponent |
vic20 | 0:39a545e08ccd | 77 | #define VDD_M 33 // Vdd Mantissa |
vic20 | 0:39a545e08ccd | 78 | #define VDD_E -1 // Exponent |
vic20 | 0:39a545e08ccd | 79 | #define VREF_M 33 // Vref Mantissa |
vic20 | 0:39a545e08ccd | 80 | #define VREF_E -1 // Exponent |
vic20 | 0:39a545e08ccd | 81 | #define DAC_BITS 12 // Number of DAC bits |
vic20 | 0:39a545e08ccd | 82 | #define ADC_BITS 12 // Number of ADC bits |
vic20 | 0:39a545e08ccd | 83 | #define MAX_SF 20000 // Maximum sample freq. for f response |
vic20 | 0:39a545e08ccd | 84 | #define MAX_SF_M 20 // Mantissa |
vic20 | 0:39a545e08ccd | 85 | #define MAX_SF_E 3 // Exponent |
vic20 | 1:d81bef65eece | 86 | #define NDIO 8 // Number of digital I/O |
vic20 | 0:39a545e08ccd | 87 | |
vic20 | 0:39a545e08ccd | 88 | // List of DAC and ADC pins |
vic20 | 1:d81bef65eece | 89 | #define PIN_LIST "A2|D13|A0|A1|A4|A5|D2|D3|D4|D5|D6|D7|D8|D9|$" |
vic20 | 1:d81bef65eece | 90 | |
vic20 | 1:d81bef65eece | 91 | // HALT signal |
vic20 | 1:d81bef65eece | 92 | #define HALT_PIN USER_BUTTON |
vic20 | 1:d81bef65eece | 93 | //#define HALT_RISING // Interrupt is on falling |
vic20 | 1:d81bef65eece | 94 | |
vic20 | 1:d81bef65eece | 95 | // No profiling is defined for this board yet |
vic20 | 1:d81bef65eece | 96 |