Vicente Jimenez / Mbed 2 deprecated SLab_Python

Firmware for Nucleo boards for the SLab system Description at http://r6500.blogspot.com.es/2018/02/slab-first-release.html All associated files at https://github.com/R6500/SLab

Dependencies:   mbed

Nucleo64-F303RE.h@0:39a545e08ccd, 2018-02-10 (annotated)

Committer:
vic20
Date:
Sat Feb 10 09:43:16 2018 +0000
Revision:
0:39a545e08ccd
Child:
1:d81bef65eece
First commit (Version 1.10)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vic20 0:39a545e08ccd 1 /***********************************************************************
vic20 0:39a545e08ccd 2
vic20 0:39a545e08ccd 3 Header file for the Nucleo64 F303RE Board
vic20 0:39a545e08ccd 4
vic20 0:39a545e08ccd 5 Basic requirements for a board are:
vic20 0:39a545e08ccd 6 MBED Compatible
vic20 0:39a545e08ccd 7 2 DACs or more
vic20 0:39a545e08ccd 8 4 ADCs or more
vic20 0:39a545e08ccd 9 That includes the following Nucleo Boards
vic20 0:39a545e08ccd 10
vic20 0:39a545e08ccd 11 Board DACs Flash RAM
vic20 0:39a545e08ccd 12 Nucleo64-F303RE 2* 512k 64k + 16k (This board)
vic20 0:39a545e08ccd 13 Nucleo64-L152RE 2* 512k 80k
vic20 0:39a545e08ccd 14 Nucleo32-F303K8 3 64k 12k + 4k
vic20 0:39a545e08ccd 15 Nucleo64-F072RB 2 128k 16k
vic20 0:39a545e08ccd 16 Nucleo64-F091RC 2 256k 32k
vic20 0:39a545e08ccd 17 Nucleo64-F334R8 3 64k 12k + 4k
vic20 0:39a545e08ccd 18 Nucleo64-F446RE 2 512k 128k
vic20 0:39a545e08ccd 19 Nucleo64-L073RZ 2 192k 20k
vic20 0:39a545e08ccd 20 Nucleo64-L476RG 2 1M 128k
vic20 0:39a545e08ccd 21
vic20 0:39a545e08ccd 22 (*) In DACs mean that one DAC has reduced range because
vic20 0:39a545e08ccd 23 it is connected to the board LCD
vic20 0:39a545e08ccd 24
vic20 0:39a545e08ccd 25 It seems that the DAC set value is more precise than
vic20 0:39a545e08ccd 26 the ADC. It is recommended to calibrate ADC against DAC.
vic20 0:39a545e08ccd 27
vic20 0:39a545e08ccd 28 History:
vic20 0:39a545e08ccd 29
vic20 0:39a545e08ccd 30 2017/02/23 : First version
vic20 0:39a545e08ccd 31 2017/10/26 : Updated for v1.1 of cpp file
vic20 0:39a545e08ccd 32
vic20 0:39a545e08ccd 33 **********************************************************************/
vic20 0:39a545e08ccd 34
vic20 0:39a545e08ccd 35 #define BSTRING "Nucleo64-F303RE MBED SLab"
vic20 0:39a545e08ccd 36
vic20 0:39a545e08ccd 37 #define F_SIZE 512
vic20 0:39a545e08ccd 38 #define R_SIZE 64
vic20 0:39a545e08ccd 39
vic20 0:39a545e08ccd 40 // ADCs
vic20 0:39a545e08ccd 41
vic20 0:39a545e08ccd 42 #define AD1 A0
vic20 0:39a545e08ccd 43 #define AD2 A1
vic20 0:39a545e08ccd 44 #define AD3 A4
vic20 0:39a545e08ccd 45 #define AD4 A5
vic20 0:39a545e08ccd 46
vic20 0:39a545e08ccd 47 // DACs
vic20 0:39a545e08ccd 48 #define DA1 A2
vic20 0:39a545e08ccd 49 #define DA2 D13
vic20 0:39a545e08ccd 50 //#define EXIST_DAC3
vic20 0:39a545e08ccd 51
vic20 0:39a545e08ccd 52 // Digital I/O
vic20 0:39a545e08ccd 53 #define EXIST_DIO
vic20 0:39a545e08ccd 54 #define DIO1 D2
vic20 0:39a545e08ccd 55 #define DIO2 D3
vic20 0:39a545e08ccd 56 #define DIO3 D4
vic20 0:39a545e08ccd 57 #define DIO4 D5
vic20 0:39a545e08ccd 58 #define DIO5 D6
vic20 0:39a545e08ccd 59 #define DIO6 D7
vic20 0:39a545e08ccd 60 #define DIO7 D8
vic20 0:39a545e08ccd 61 #define DIO8 D9
vic20 0:39a545e08ccd 62
vic20 0:39a545e08ccd 63 // Board capabilities implemented in firmware
vic20 0:39a545e08ccd 64 #define NDACS 2 // Number of DACs
vic20 0:39a545e08ccd 65 #define NADCS 4 // Number of ADCs
vic20 0:39a545e08ccd 66 #define BSIZE 20000 // Unified buffer size (in samples)
vic20 0:39a545e08ccd 67 #define MAX_STIME 100.0f // Maximum sample period is 100s
vic20 0:39a545e08ccd 68 #define MAX_S_M 100 // Mantissa
vic20 0:39a545e08ccd 69 #define MAX_S_E 0 // Exponent
vic20 0:39a545e08ccd 70 #define MIN_STIME 0.000001f // Minimum sample period is 1us
vic20 0:39a545e08ccd 71 #define MIN_S_M 1 // Mantissa
vic20 0:39a545e08ccd 72 #define MIN_S_E -6 // Exponent
vic20 0:39a545e08ccd 73 #define VDD_M 33 // Vdd Mantissa
vic20 0:39a545e08ccd 74 #define VDD_E -1 // Exponent
vic20 0:39a545e08ccd 75 #define VREF_M 33 // Vref Mantissa
vic20 0:39a545e08ccd 76 #define VREF_E -1 // Exponent
vic20 0:39a545e08ccd 77 #define DAC_BITS 12 // Number of DAC bits
vic20 0:39a545e08ccd 78 #define ADC_BITS 12 // Number of ADC bits
vic20 0:39a545e08ccd 79 #define MAX_SF 38000 // Maximum sample freq. for f response
vic20 0:39a545e08ccd 80 #define MAX_SF_M 38 // Mantissa
vic20 0:39a545e08ccd 81 #define MAX_SF_E 3 // Exponent
vic20 0:39a545e08ccd 82 #define NDIO 8 // Number of digital I/O
vic20 0:39a545e08ccd 83
vic20 0:39a545e08ccd 84 // Delay between setting DAC and reading ADC
vic20 0:39a545e08ccd 85 // Removed as is not usefull enough
vic20 0:39a545e08ccd 86 //#define DELAY_M 9 // Mantissa
vic20 0:39a545e08ccd 87 //#define DELAY_E -6 // Exponent
vic20 0:39a545e08ccd 88
vic20 0:39a545e08ccd 89 // List of DAC and ADC pins
vic20 0:39a545e08ccd 90 #define PIN_LIST "A2|D13|A0|A1|A4|A5|D2|D3|D4|D5|D6|D7|D8|D9|$"
vic20 0:39a545e08ccd 91
vic20 0:39a545e08ccd 92
vic20 0:39a545e08ccd 93 // Hardware profiling defines
vic20 0:39a545e08ccd 94 #ifdef USE_PROFILING
vic20 0:39a545e08ccd 95
vic20 0:39a545e08ccd 96 // Profiling pins to be delared as outputs at main()
vic20 0:39a545e08ccd 97 #define PRO1_PIN PC_4
vic20 0:39a545e08ccd 98 #define PRO2_PIN PB_13
vic20 0:39a545e08ccd 99
vic20 0:39a545e08ccd 100 // Profiling code
vic20 0:39a545e08ccd 101 // Code to set or clear each profile line
vic20 0:39a545e08ccd 102 // They use low level calls to minimize effect on profiled code
vic20 0:39a545e08ccd 103 #define PRO1_SET GPIOC->BSRR = 1<<4;
vic20 0:39a545e08ccd 104 #define PRO1_CLEAR GPIOC->BSRR = 1<<(16+4);
vic20 0:39a545e08ccd 105 #define PRO2_SET GPIOB->BSRR = 1<<13;
vic20 0:39a545e08ccd 106 #define PRO2_CLEAR GPIOB->BSRR = 1<<(16+13);
vic20 0:39a545e08ccd 107
vic20 0:39a545e08ccd 108 #endif //USE_PROFILING
vic20 0:39a545e08ccd 109