Norimasa Okamoto / Mbed 2 deprecated emu812

mbed LPC812 emulator pre-alpha version

Dependencies:   BaseV6M mbed F12RFileSystem F32RFileSystem ROMSLOT SDStorage

320 340

Example

TTB_mbed_LPC812.bin save as "LPC812.IMG" .
internal boot rom image(0x1fff0000-0x1fff1fff) save as "LPC812.ROM".

Tested programs

EMU81x.cpp@5:f22e2df90a70, 2016-04-09 (annotated)

Committer:
va009039
Date:
Sat Apr 09 07:59:56 2016 +0000
Revision:
5:f22e2df90a70
Parent:
2:3f3637d7c2bc 
add Nucleo-L152RE.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 2:3f3637d7c2bc 1 // EMU81x.cpp 2015/8/12
va009039 1:913dfd59e25a 2 #include "mbed.h"
va009039 1:913dfd59e25a 3 #include "EMU81x.h"
va009039 1:913dfd59e25a 4 #define V6M_LOG_LEVEL 2
va009039 1:913dfd59e25a 5 #include "v6m_log.h"
va009039 1:913dfd59e25a 6
va009039 1:913dfd59e25a 7 const int EMU81x_RAM_SIZE = (1024*4);
va009039 1:913dfd59e25a 8 const int EMU81x_FLASH_SIZE = (1024*16);
va009039 1:913dfd59e25a 9 const int EMU81x_ROM_SIZE = (1024*8);
va009039 1:913dfd59e25a 10
va009039 1:913dfd59e25a 11 const uint32_t EMU81x_FLASH_BASE = 0x00000000;
va009039 1:913dfd59e25a 12 const uint32_t EMU81x_RAM_BASE = 0x10000000;
va009039 1:913dfd59e25a 13 const uint32_t EMU81x_ROM_BASE = 0x1fff0000;
va009039 1:913dfd59e25a 14 const uint32_t EMU81x_APB_BASE = 0x40000000;
va009039 1:913dfd59e25a 15 const uint32_t EMU81x_AHB_BASE = 0x50000000;
va009039 1:913dfd59e25a 16 const uint32_t EMU81x_GPIO_PORT_BASE = 0xa0000000;
va009039 1:913dfd59e25a 17 const uint32_t EMU81x_SCS_BASE = 0xe000e000;
va009039 1:913dfd59e25a 18
va009039 1:913dfd59e25a 19 EMU81x_USART::EMU81x_USART(EMU81x& mcu_, int ch_):mcu(mcu_),ch(ch_) {
va009039 1:913dfd59e25a 20 V6M_ASSERT(ch >= 0 && ch <= 2);
va009039 2:3f3637d7c2bc 21 CFG = 0x00;
va009039 2:3f3637d7c2bc 22 STAT = 0x0e;
va009039 2:3f3637d7c2bc 23 BRG = 0x00;
va009039 1:913dfd59e25a 24 }
va009039 1:913dfd59e25a 25
va009039 1:913dfd59e25a 26 void EMU81x_USART::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 27 switch(a&0xff) {
va009039 2:3f3637d7c2bc 28 #define c(OFFSET,NAME) case OFFSET: NAME = d; V6M_INFO("P: LPC_USART%d->%s << %08x", ch, #NAME, d); break;
va009039 2:3f3637d7c2bc 29 c(0x00, CFG);
va009039 2:3f3637d7c2bc 30 c(0x08, STAT);
va009039 2:3f3637d7c2bc 31 c(0x10, INTENCLR);
va009039 2:3f3637d7c2bc 32 case 0x1c:
va009039 1:913dfd59e25a 33 mcu.SerialPutc_Callback(ch, d);
va009039 1:913dfd59e25a 34 V6M_INFO("P: LPC_USART%d->TXDATA << %08x", ch, d);
va009039 1:913dfd59e25a 35 break;
va009039 2:3f3637d7c2bc 36 c(0x20, BRG);
va009039 2:3f3637d7c2bc 37 #undef c
va009039 2:3f3637d7c2bc 38 default:
va009039 1:913dfd59e25a 39 V6M_WARN("P: LPC_UART%d %08x << %08x", ch, a, d);
va009039 1:913dfd59e25a 40 break;
va009039 1:913dfd59e25a 41 }
va009039 1:913dfd59e25a 42 }
va009039 1:913dfd59e25a 43
va009039 1:913dfd59e25a 44 uint32_t EMU81x_USART::peek32(uint32_t a) {
va009039 1:913dfd59e25a 45 uint32_t d = 0x00;
va009039 1:913dfd59e25a 46 switch(a&0xff) {
va009039 2:3f3637d7c2bc 47 #define c(OFFSET,NAME) case OFFSET: d = NAME; V6M_INFO("P: LPC_USART%d->%s >> %08x", ch, #NAME, d); break;
va009039 2:3f3637d7c2bc 48 c(0x00, CFG);
va009039 1:913dfd59e25a 49 case 0x08:
va009039 1:913dfd59e25a 50 d = 0x04;
va009039 1:913dfd59e25a 51 if (mcu.SerialReadable_Callback(ch)) {
va009039 1:913dfd59e25a 52 d |= 0x01;
va009039 1:913dfd59e25a 53 }
va009039 1:913dfd59e25a 54 V6M_INFO("P: LPC_USART%d->STAT >> %08x", ch, d);
va009039 1:913dfd59e25a 55 break;
va009039 1:913dfd59e25a 56 case 0x14:
va009039 1:913dfd59e25a 57 d = mcu.SerialGetc_Callback(ch);
va009039 1:913dfd59e25a 58 V6M_INFO("P: LPC_USART%d->RXDATA >> %08x", ch, d);
va009039 1:913dfd59e25a 59 break;
va009039 2:3f3637d7c2bc 60 c(0x20, BRG);
va009039 2:3f3637d7c2bc 61 #undef c
va009039 1:913dfd59e25a 62 default:
va009039 1:913dfd59e25a 63 V6M_WARN("P: LPC_USART%d %08x >> %08x", ch, a, d);
va009039 1:913dfd59e25a 64 break;
va009039 1:913dfd59e25a 65 }
va009039 1:913dfd59e25a 66 return d;
va009039 1:913dfd59e25a 67 }
va009039 1:913dfd59e25a 68
va009039 1:913dfd59e25a 69 EMU81x_MRT::EMU81x_MRT():timer0(0x7fffffff) {
va009039 1:913dfd59e25a 70 }
va009039 1:913dfd59e25a 71
va009039 1:913dfd59e25a 72 void EMU81x_MRT::clock_in(uint32_t n) {
va009039 1:913dfd59e25a 73 V6M_ASSERT(n != 0);
va009039 1:913dfd59e25a 74 timer0 = (timer0 - n) & 0x7fffffff;
va009039 1:913dfd59e25a 75 }
va009039 1:913dfd59e25a 76
va009039 1:913dfd59e25a 77 void EMU81x_MRT::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 78 switch(a&0xff) {
va009039 2:3f3637d7c2bc 79 #define c(OFFSET,NAME) case OFFSET: V6M_INFO("P: LPC_MRT->%s << %08x", #NAME, d); break;
va009039 2:3f3637d7c2bc 80 c(0x00, INTVAL0);
va009039 2:3f3637d7c2bc 81 c(0x08, CTRL0);
va009039 2:3f3637d7c2bc 82 c(0x10, INTVAL1);
va009039 2:3f3637d7c2bc 83 c(0x18, CTRL1);
va009039 2:3f3637d7c2bc 84 #undef c
va009039 1:913dfd59e25a 85 default:
va009039 1:913dfd59e25a 86 V6M_WARN("P: LPC_MRT %08x << %08x", a, d);
va009039 1:913dfd59e25a 87 break;
va009039 1:913dfd59e25a 88 }
va009039 1:913dfd59e25a 89 }
va009039 1:913dfd59e25a 90
va009039 1:913dfd59e25a 91 uint32_t EMU81x_MRT::peek32(uint32_t a) {
va009039 1:913dfd59e25a 92 uint32_t d = 0x00;
va009039 1:913dfd59e25a 93 switch(a&0xff) {
va009039 1:913dfd59e25a 94 case 0x04:
va009039 1:913dfd59e25a 95 d = timer0;
va009039 1:913dfd59e25a 96 V6M_INFO("P: LPC_MRT->TIMER0 >> %u", timer0);
va009039 1:913dfd59e25a 97 break;
va009039 1:913dfd59e25a 98 default:
va009039 1:913dfd59e25a 99 V6M_WARN("P: LPC_MRT %08x >> %02x", a, d);
va009039 1:913dfd59e25a 100 break;
va009039 1:913dfd59e25a 101 }
va009039 1:913dfd59e25a 102 return d;
va009039 1:913dfd59e25a 103 }
va009039 1:913dfd59e25a 104
va009039 1:913dfd59e25a 105 EMU81x_IOCON::EMU81x_IOCON() {
va009039 2:3f3637d7c2bc 106 PIO0_17 = 0x90;
va009039 2:3f3637d7c2bc 107 PIO0_13 = 0x90;
va009039 2:3f3637d7c2bc 108 PIO0_12 = 0x90;
va009039 2:3f3637d7c2bc 109 PIO0_5 = 0x90;
va009039 2:3f3637d7c2bc 110 PIO0_4 = 0x90;
va009039 2:3f3637d7c2bc 111 PIO0_3 = 0x90;
va009039 2:3f3637d7c2bc 112 PIO0_2 = 0x90;
va009039 2:3f3637d7c2bc 113 PIO0_11 = 0x80;
va009039 2:3f3637d7c2bc 114 PIO0_10 = 0x80;
va009039 2:3f3637d7c2bc 115 PIO0_16 = 0x90;
va009039 2:3f3637d7c2bc 116 PIO0_15 = 0x90;
va009039 2:3f3637d7c2bc 117 PIO0_1 = 0x90;
va009039 2:3f3637d7c2bc 118 PIO0_9 = 0x90;
va009039 2:3f3637d7c2bc 119 PIO0_8 = 0x90;
va009039 2:3f3637d7c2bc 120 PIO0_7 = 0x90;
va009039 2:3f3637d7c2bc 121 PIO0_6 = 0x90;
va009039 2:3f3637d7c2bc 122 PIO0_0 = 0x90;
va009039 2:3f3637d7c2bc 123 PIO0_14 = 0x90;
va009039 1:913dfd59e25a 124 }
va009039 1:913dfd59e25a 125
va009039 1:913dfd59e25a 126 void EMU81x_IOCON::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 127 switch(a&0xff) {
va009039 2:3f3637d7c2bc 128 #define c(OFFSET,NAME) case OFFSET: NAME = d; V6M_INFO("P: LPC_IOCON->PIO0_%s << %08x", #NAME, d); break;
va009039 2:3f3637d7c2bc 129 c(0x00, PIO0_17);
va009039 2:3f3637d7c2bc 130 c(0x04, PIO0_13);
va009039 2:3f3637d7c2bc 131 c(0x08, PIO0_12);
va009039 2:3f3637d7c2bc 132 c(0x0c, PIO0_5);
va009039 2:3f3637d7c2bc 133 c(0x10, PIO0_3);
va009039 2:3f3637d7c2bc 134 c(0x14, PIO0_4);
va009039 2:3f3637d7c2bc 135 c(0x18, PIO0_2);
va009039 2:3f3637d7c2bc 136 c(0x1c, PIO0_11);
va009039 2:3f3637d7c2bc 137 c(0x20, PIO0_10);
va009039 2:3f3637d7c2bc 138 c(0x24, PIO0_16);
va009039 2:3f3637d7c2bc 139 c(0x28, PIO0_15);
va009039 2:3f3637d7c2bc 140 c(0x2c, PIO0_1);
va009039 2:3f3637d7c2bc 141 c(0x34, PIO0_9);
va009039 2:3f3637d7c2bc 142 c(0x38, PIO0_8);
va009039 2:3f3637d7c2bc 143 c(0x3c, PIO0_7);
va009039 2:3f3637d7c2bc 144 c(0x40, PIO0_6);
va009039 2:3f3637d7c2bc 145 c(0x44, PIO0_0);
va009039 2:3f3637d7c2bc 146 c(0x48, PIO0_14);
va009039 2:3f3637d7c2bc 147 #undef c
va009039 2:3f3637d7c2bc 148 default:
va009039 2:3f3637d7c2bc 149 V6M_WARN("P: LPC_IOCON %08x << %04x", a, d);
va009039 2:3f3637d7c2bc 150 break;
va009039 1:913dfd59e25a 151 }
va009039 1:913dfd59e25a 152 }
va009039 1:913dfd59e25a 153
va009039 1:913dfd59e25a 154 uint32_t EMU81x_IOCON::peek32(uint32_t a) {
va009039 1:913dfd59e25a 155 uint32_t d = 0x00;
va009039 1:913dfd59e25a 156 switch(a&0xff) {
va009039 2:3f3637d7c2bc 157 #define c(OFFSET,NAME) case OFFSET: d = NAME; V6M_INFO("P: LPC_IOCON->PIO0_%s >> %08x", #NAME, d); break;
va009039 2:3f3637d7c2bc 158 c(0x00, PIO0_17);
va009039 2:3f3637d7c2bc 159 c(0x04, PIO0_13);
va009039 2:3f3637d7c2bc 160 c(0x08, PIO0_12);
va009039 2:3f3637d7c2bc 161 c(0x0c, PIO0_5);
va009039 2:3f3637d7c2bc 162 c(0x10, PIO0_3);
va009039 2:3f3637d7c2bc 163 c(0x14, PIO0_4);
va009039 2:3f3637d7c2bc 164 c(0x18, PIO0_2);
va009039 2:3f3637d7c2bc 165 c(0x1c, PIO0_11);
va009039 2:3f3637d7c2bc 166 c(0x20, PIO0_10);
va009039 2:3f3637d7c2bc 167 c(0x24, PIO0_16);
va009039 2:3f3637d7c2bc 168 c(0x28, PIO0_15);
va009039 2:3f3637d7c2bc 169 c(0x2c, PIO0_1);
va009039 2:3f3637d7c2bc 170 c(0x34, PIO0_9);
va009039 2:3f3637d7c2bc 171 c(0x38, PIO0_8);
va009039 2:3f3637d7c2bc 172 c(0x3c, PIO0_7);
va009039 2:3f3637d7c2bc 173 c(0x40, PIO0_6);
va009039 2:3f3637d7c2bc 174 c(0x44, PIO0_0);
va009039 2:3f3637d7c2bc 175 c(0x48, PIO0_14);
va009039 2:3f3637d7c2bc 176 #undef c
va009039 2:3f3637d7c2bc 177 default:
va009039 2:3f3637d7c2bc 178 V6M_WARN("P: LPC_IOCON %08x >> %04x", a, d);
va009039 2:3f3637d7c2bc 179 break;
va009039 1:913dfd59e25a 180 }
va009039 1:913dfd59e25a 181 return d;
va009039 1:913dfd59e25a 182 }
va009039 1:913dfd59e25a 183
va009039 1:913dfd59e25a 184 EMU81x_SYSCON::EMU81x_SYSCON() {
va009039 1:913dfd59e25a 185 }
va009039 1:913dfd59e25a 186
va009039 1:913dfd59e25a 187 void EMU81x_SYSCON::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 188 switch(a&0xfff) {
va009039 2:3f3637d7c2bc 189 #define c(OFFSET,NAME) case OFFSET: V6M_INFO("P: LPC_SYSCON->%s << %08x", #NAME, d); break;
va009039 2:3f3637d7c2bc 190 c(0x004, PRESETCTRL);
va009039 2:3f3637d7c2bc 191 c(0x008, SYSPLLCTRL);
va009039 2:3f3637d7c2bc 192 c(0x040, SYSPLLCLKSEL);
va009039 2:3f3637d7c2bc 193 c(0x044, SYSPLLCLKUEN);
va009039 2:3f3637d7c2bc 194 c(0x070, MAINCLKSEL);
va009039 2:3f3637d7c2bc 195 c(0x074, MAINCLKUEN);
va009039 2:3f3637d7c2bc 196 c(0x078, SYSAHBCLKDIV);
va009039 2:3f3637d7c2bc 197 c(0x080, SYSAHBCLKCTRL);
va009039 2:3f3637d7c2bc 198 c(0x094, UARTCLKDIV);
va009039 2:3f3637d7c2bc 199 c(0x0f0, UARTFRGDIV);
va009039 2:3f3637d7c2bc 200 c(0x0f4, UARTFRGMULT);
va009039 2:3f3637d7c2bc 201 c(0x238, PDRUNCFG);
va009039 2:3f3637d7c2bc 202 #undef c
va009039 1:913dfd59e25a 203 default:
va009039 1:913dfd59e25a 204 V6M_WARN("P: LPC_SYSCON %08x << %08x", a, d);
va009039 1:913dfd59e25a 205 break;
va009039 1:913dfd59e25a 206 }
va009039 1:913dfd59e25a 207 }
va009039 1:913dfd59e25a 208
va009039 1:913dfd59e25a 209 uint32_t EMU81x_SYSCON::peek32(uint32_t a) {
va009039 1:913dfd59e25a 210 uint32_t d = 0x00;
va009039 1:913dfd59e25a 211 switch(a&0xfff) {
va009039 2:3f3637d7c2bc 212 #define c(OFFSET,NAME) case OFFSET: V6M_INFO("P: LPC_SYSCON->%s >> %08x", #NAME, d); break;
va009039 2:3f3637d7c2bc 213 c(0x004, PRESETCTRL);
va009039 1:913dfd59e25a 214 case 0x00c:
va009039 1:913dfd59e25a 215 d = 0x01;
va009039 1:913dfd59e25a 216 V6M_INFO("P: LPC_SYSCON->SYSPLLSTAT >> %08x", d);
va009039 1:913dfd59e25a 217 break;
va009039 1:913dfd59e25a 218 case 0x044:
va009039 1:913dfd59e25a 219 d = 0x01;
va009039 1:913dfd59e25a 220 V6M_INFO("P: LPC_SYSCON->SYSPLLCLKUEN >> %08x", d);
va009039 1:913dfd59e25a 221 break;
va009039 1:913dfd59e25a 222 case 0x074:
va009039 1:913dfd59e25a 223 d = 0x01;
va009039 1:913dfd59e25a 224 V6M_INFO("P: LPC_SYSCON->MAINCLKUEN >> %08x", d);
va009039 1:913dfd59e25a 225 break;
va009039 2:3f3637d7c2bc 226 c(0x080, SYSAHBCLKCTRL);
va009039 2:3f3637d7c2bc 227 c(0x094, UARTCLKDIV);
va009039 2:3f3637d7c2bc 228 c(0x0f0, UARTFRGDIV);
va009039 2:3f3637d7c2bc 229 c(0x0f4, UARTFRGMULT);
va009039 2:3f3637d7c2bc 230 c(0x238, PDRUNCFG);
va009039 2:3f3637d7c2bc 231 #undef c
va009039 1:913dfd59e25a 232 default:
va009039 1:913dfd59e25a 233 V6M_WARN("P: LPC_SYSCON %08x >> %08x", a, d);
va009039 1:913dfd59e25a 234 break;
va009039 1:913dfd59e25a 235 }
va009039 1:913dfd59e25a 236 return d;
va009039 1:913dfd59e25a 237 }
va009039 1:913dfd59e25a 238
va009039 1:913dfd59e25a 239 EMU81x_SWM::EMU81x_SWM() {
va009039 1:913dfd59e25a 240 memset(pinassign, 0xff, sizeof(pinassign));
va009039 1:913dfd59e25a 241 pinenable0 = 0x1b3;
va009039 1:913dfd59e25a 242 }
va009039 1:913dfd59e25a 243
va009039 1:913dfd59e25a 244 void EMU81x_SWM::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 245 int n = (a&0xff) / 4;
va009039 1:913dfd59e25a 246 switch(a&0xfff) {
va009039 1:913dfd59e25a 247 case 0x00: case 0x04: case 0x08: case 0x0c: case 0x10: case 0x14: case 0x1c: case 0x20:
va009039 1:913dfd59e25a 248 pinassign[n] = d;
va009039 1:913dfd59e25a 249 V6M_INFO("P: LPC_SWM->PINASSIGN%d << %08x", n, d);
va009039 1:913dfd59e25a 250 break;
va009039 1:913dfd59e25a 251 case 0x1c0:
va009039 1:913dfd59e25a 252 pinenable0 = d;
va009039 1:913dfd59e25a 253 V6M_INFO("P: LPC_SWM->PINENABLE0 << %08x", d);
va009039 1:913dfd59e25a 254 break;
va009039 1:913dfd59e25a 255 default:
va009039 1:913dfd59e25a 256 V6M_INFO("P: LPC_SWM %08x << %08x", a, d);
va009039 1:913dfd59e25a 257 break;
va009039 1:913dfd59e25a 258 }
va009039 1:913dfd59e25a 259 }
va009039 1:913dfd59e25a 260
va009039 1:913dfd59e25a 261 uint32_t EMU81x_SWM::peek32(uint32_t a) {
va009039 1:913dfd59e25a 262 int n = (a&0xff) / 4;
va009039 1:913dfd59e25a 263 uint32_t d = 0x00;
va009039 1:913dfd59e25a 264 switch(a&0xfff) {
va009039 1:913dfd59e25a 265 case 0x00: case 0x04: case 0x08: case 0x0c: case 0x10: case 0x14: case 0x1c: case 0x20:
va009039 1:913dfd59e25a 266 d = pinassign[n];
va009039 1:913dfd59e25a 267 V6M_INFO("P: LPC_SWM->PINASSIGN%d >> %08x", n, d);
va009039 1:913dfd59e25a 268 break;
va009039 1:913dfd59e25a 269 case 0x1c0:
va009039 1:913dfd59e25a 270 d = pinenable0;
va009039 1:913dfd59e25a 271 V6M_INFO("P: LPC_SWM->PINENABLE0 >> %08x", d);
va009039 1:913dfd59e25a 272 break;
va009039 1:913dfd59e25a 273 default:
va009039 1:913dfd59e25a 274 V6M_INFO("P: LPC_SWM %08x >> %08x", a, d);
va009039 1:913dfd59e25a 275 break;
va009039 1:913dfd59e25a 276 }
va009039 1:913dfd59e25a 277 return d;
va009039 1:913dfd59e25a 278 }
va009039 1:913dfd59e25a 279
va009039 1:913dfd59e25a 280 EMU81x_GPIO::EMU81x_GPIO(EMU81x& mcu_):mcu(mcu_) {
va009039 1:913dfd59e25a 281 dir0 = 0;
va009039 1:913dfd59e25a 282 data0 = 0;
va009039 1:913dfd59e25a 283 }
va009039 1:913dfd59e25a 284
va009039 1:913dfd59e25a 285 void EMU81x_GPIO::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 286 V6M_ASSERT((a&0xffff0000) == 0xa0000000);
va009039 1:913dfd59e25a 287 switch(a&0xffff) {
va009039 1:913dfd59e25a 288 case 0x2000:
va009039 1:913dfd59e25a 289 dir0 = d;
va009039 1:913dfd59e25a 290 V6M_INFO("P: LPC_GPIO_PORT->DIR0 << %08x", d);
va009039 1:913dfd59e25a 291 break;
va009039 1:913dfd59e25a 292 case 0x2200:
va009039 1:913dfd59e25a 293 data0 |= d;
va009039 1:913dfd59e25a 294 for(int pin = 0; pin <24; pin++) {
va009039 1:913dfd59e25a 295 if (d & (1UL<<pin)) {
va009039 1:913dfd59e25a 296 mcu.DigitalWrite_Callback(0, pin, 1);
va009039 1:913dfd59e25a 297 }
va009039 1:913dfd59e25a 298 }
va009039 1:913dfd59e25a 299 V6M_INFO("P: LPC_GPIO_PORT->SET0 << %08x", d);
va009039 1:913dfd59e25a 300 break;
va009039 1:913dfd59e25a 301 case 0x2280:
va009039 1:913dfd59e25a 302 data0 &= (~d)&0xffffffff;
va009039 1:913dfd59e25a 303 for(int pin = 0; pin <24; pin++) {
va009039 1:913dfd59e25a 304 if (d & (1UL<<pin)) {
va009039 1:913dfd59e25a 305 mcu.DigitalWrite_Callback(0, pin, 0);
va009039 1:913dfd59e25a 306 }
va009039 1:913dfd59e25a 307 }
va009039 1:913dfd59e25a 308 V6M_INFO("P: LPC_GPIO_PORT->CLR0 << %08x", d);
va009039 1:913dfd59e25a 309 break;
va009039 1:913dfd59e25a 310 default:
va009039 1:913dfd59e25a 311 V6M_WARN("P: LPC_GPIO_PORT %08x << %08x", a, d);
va009039 1:913dfd59e25a 312 break;
va009039 1:913dfd59e25a 313 }
va009039 1:913dfd59e25a 314 }
va009039 1:913dfd59e25a 315
va009039 1:913dfd59e25a 316 uint32_t EMU81x_GPIO::peek32(uint32_t a) {
va009039 1:913dfd59e25a 317 V6M_ASSERT((a&0xffff0000) == 0xa0000000);
va009039 1:913dfd59e25a 318 uint32_t d = 0x00000000;
va009039 1:913dfd59e25a 319 switch(a&0xffff) {
va009039 1:913dfd59e25a 320 case 0x2000:
va009039 1:913dfd59e25a 321 d = dir0;
va009039 1:913dfd59e25a 322 V6M_INFO("P: LPC_GPIO_PORT->DIR0 >> %08x", d);
va009039 1:913dfd59e25a 323 break;
va009039 1:913dfd59e25a 324 case 0x2100:
va009039 1:913dfd59e25a 325 d = data0;
va009039 1:913dfd59e25a 326 V6M_INFO("P: LPC_GPIO_PORT->PIN0 >> %08x", d);
va009039 1:913dfd59e25a 327 break;
va009039 1:913dfd59e25a 328 default:
va009039 1:913dfd59e25a 329 V6M_WARN("P: LPC_GPIO_PORT %08x >> %08x", a, d);
va009039 1:913dfd59e25a 330 break;
va009039 1:913dfd59e25a 331 }
va009039 1:913dfd59e25a 332 return d;
va009039 1:913dfd59e25a 333 }
va009039 1:913dfd59e25a 334
va009039 1:913dfd59e25a 335 EMU81x_I2C::EMU81x_I2C(EMU81x& mcu_):mcu(mcu_) {
va009039 1:913dfd59e25a 336 cfg = 0x00;
va009039 1:913dfd59e25a 337 mststate = 0;
va009039 1:913dfd59e25a 338 }
va009039 1:913dfd59e25a 339
va009039 1:913dfd59e25a 340 void EMU81x_I2C::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 341 switch(a&0xff) {
va009039 1:913dfd59e25a 342 case 0x00:
va009039 1:913dfd59e25a 343 cfg = d;
va009039 1:913dfd59e25a 344 V6M_INFO("P: LPC_I2C->CFG << %08x", d);
va009039 1:913dfd59e25a 345 break;
va009039 1:913dfd59e25a 346 case 0x0c:
va009039 1:913dfd59e25a 347 V6M_INFO("P: LPC_I2C->INTENCLR << %08x", d);
va009039 1:913dfd59e25a 348 break;
va009039 1:913dfd59e25a 349 case 0x14:
va009039 1:913dfd59e25a 350 V6M_INFO("P: LPC_I2C->DIV << %08x", d);
va009039 1:913dfd59e25a 351 break;
va009039 1:913dfd59e25a 352 case 0x20:
va009039 1:913dfd59e25a 353 if (d & 0x02) { // master start
va009039 1:913dfd59e25a 354 i2c_addr = mstdat;
va009039 1:913dfd59e25a 355 if (i2c_addr & 0x01) {
va009039 2:3f3637d7c2bc 356 mcu.I2CRead_Callback(i2c_addr, i2c_data, sizeof(i2c_data));
va009039 1:913dfd59e25a 357 mststate = 1; // receive ready
va009039 1:913dfd59e25a 358 i2c_pos = 0;
va009039 1:913dfd59e25a 359 } else {
va009039 1:913dfd59e25a 360 i2c_pos = 0;
va009039 1:913dfd59e25a 361 mststate = 2; // transmit ready
va009039 1:913dfd59e25a 362 }
va009039 1:913dfd59e25a 363 } else if (d & 0x04) { // master stop
va009039 1:913dfd59e25a 364 if (i2c_addr & 0x01) {
va009039 1:913dfd59e25a 365 mststate = 0; // idle
va009039 1:913dfd59e25a 366 } else {
va009039 1:913dfd59e25a 367 mcu.I2CWrite_Callback(i2c_addr, i2c_data, i2c_pos);
va009039 1:913dfd59e25a 368 mststate = 0;
va009039 1:913dfd59e25a 369 }
va009039 1:913dfd59e25a 370 } else if (d & 0x01) { // master continue
va009039 1:913dfd59e25a 371 if (i2c_pos < sizeof(i2c_data)) {
va009039 1:913dfd59e25a 372 i2c_data[i2c_pos++] = mstdat;
va009039 1:913dfd59e25a 373 }
va009039 1:913dfd59e25a 374 mststate = 2; // transmit ready
va009039 1:913dfd59e25a 375 } else {
va009039 1:913dfd59e25a 376 V6M_ERROR("MSTCTL=%02x", d);
va009039 1:913dfd59e25a 377 }
va009039 1:913dfd59e25a 378 V6M_INFO("P: LPC_I2C->MSTCTL << %08x", d);
va009039 1:913dfd59e25a 379 break;
va009039 1:913dfd59e25a 380 case 0x24:
va009039 1:913dfd59e25a 381 V6M_INFO("P: LPC_I2C->MSTTIME << %08x", d);
va009039 1:913dfd59e25a 382 break;
va009039 1:913dfd59e25a 383 case 0x28:
va009039 1:913dfd59e25a 384 mstdat = d & 0xff;
va009039 1:913dfd59e25a 385 V6M_INFO("P: LPC_I2C->MSTDAT << %08x", d);
va009039 1:913dfd59e25a 386 break;
va009039 1:913dfd59e25a 387 default:
va009039 1:913dfd59e25a 388 V6M_WARN("P: LPC_I2C %08x << %08x", a, d);
va009039 1:913dfd59e25a 389 break;
va009039 1:913dfd59e25a 390 }
va009039 1:913dfd59e25a 391 }
va009039 1:913dfd59e25a 392
va009039 1:913dfd59e25a 393 uint32_t EMU81x_I2C::peek32(uint32_t a) {
va009039 1:913dfd59e25a 394 uint32_t d = 0x00000000;
va009039 1:913dfd59e25a 395 switch(a&0xff) {
va009039 1:913dfd59e25a 396 case 0x00:
va009039 1:913dfd59e25a 397 d = cfg;
va009039 1:913dfd59e25a 398 V6M_INFO("P: LPC_I2C->CFG >> %08x", d);
va009039 1:913dfd59e25a 399 break;
va009039 1:913dfd59e25a 400 case 0x04:
va009039 1:913dfd59e25a 401 d = 0x801|mststate<<1;
va009039 1:913dfd59e25a 402 V6M_INFO("P: LPC_I2C->STAT >> %08x", d);
va009039 1:913dfd59e25a 403 break;
va009039 1:913dfd59e25a 404 case 0x28:
va009039 2:3f3637d7c2bc 405 if (i2c_pos < sizeof(i2c_data)) {
va009039 1:913dfd59e25a 406 d = i2c_data[i2c_pos++];
va009039 1:913dfd59e25a 407 }
va009039 1:913dfd59e25a 408 V6M_INFO("P: LPC_I2C->MSTDAT >> %08x", d);
va009039 1:913dfd59e25a 409 break;
va009039 1:913dfd59e25a 410 default:
va009039 1:913dfd59e25a 411 V6M_INFO("P: LPC_I2C %08x >> %08x", a, d);
va009039 1:913dfd59e25a 412 break;
va009039 1:913dfd59e25a 413 }
va009039 1:913dfd59e25a 414 return d;
va009039 1:913dfd59e25a 415 }
va009039 1:913dfd59e25a 416
va009039 1:913dfd59e25a 417 EMU81x_SPI::EMU81x_SPI(EMU81x& mcu_, int ch_):mcu(mcu_),ch(ch_) {
va009039 1:913dfd59e25a 418 }
va009039 1:913dfd59e25a 419
va009039 1:913dfd59e25a 420 void EMU81x_SPI::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 421 switch(a&0xff) {
va009039 1:913dfd59e25a 422 case 0x00:
va009039 1:913dfd59e25a 423 V6M_INFO("P: LPC_SPI%d->CFG << %08x", ch, d);
va009039 1:913dfd59e25a 424 break;
va009039 1:913dfd59e25a 425 case 0x04:
va009039 1:913dfd59e25a 426 V6M_INFO("P: LPC_SPI%d->DLY << %08x", ch, d);
va009039 1:913dfd59e25a 427 break;
va009039 1:913dfd59e25a 428 case 0x10:
va009039 1:913dfd59e25a 429 V6M_INFO("P: LPC_SPI%d->INTENCLR << %08x", ch, d);
va009039 1:913dfd59e25a 430 break;
va009039 1:913dfd59e25a 431 case 0x18:
va009039 1:913dfd59e25a 432 V6M_INFO("P: LPC_SPI%d->TXDATCTL << %08x", ch, d);
va009039 1:913dfd59e25a 433 break;
va009039 1:913dfd59e25a 434 case 0x1c:
va009039 1:913dfd59e25a 435 rxdat = mcu.SPIWrite_Callback(ch, d);
va009039 1:913dfd59e25a 436 V6M_INFO("P: LPC_SPI%d->TXDAT << %08x", ch, d);
va009039 1:913dfd59e25a 437 break;
va009039 1:913dfd59e25a 438 case 0x24:
va009039 1:913dfd59e25a 439 V6M_INFO("P: LPC_SPI%d->DIV << %08x", ch, d);
va009039 1:913dfd59e25a 440 break;
va009039 1:913dfd59e25a 441 default:
va009039 1:913dfd59e25a 442 V6M_WARN("P: LPC_SPI%d %08x << %08x", ch, a, d);
va009039 1:913dfd59e25a 443 break;
va009039 1:913dfd59e25a 444 }
va009039 1:913dfd59e25a 445 }
va009039 1:913dfd59e25a 446
va009039 1:913dfd59e25a 447 uint32_t EMU81x_SPI::peek32(uint32_t a) {
va009039 1:913dfd59e25a 448 uint32_t d = 0;
va009039 1:913dfd59e25a 449 switch(a&0xff) {
va009039 1:913dfd59e25a 450 case 0x00:
va009039 1:913dfd59e25a 451 V6M_INFO("P: LPC_SPI%d->CFG >> %08x", ch, d);
va009039 1:913dfd59e25a 452 break;
va009039 1:913dfd59e25a 453 case 0x08:
va009039 1:913dfd59e25a 454 d = 0x03;
va009039 1:913dfd59e25a 455 V6M_INFO("P: LPC_SPI%d->STAT >> %08x", ch, d);
va009039 1:913dfd59e25a 456 break;
va009039 1:913dfd59e25a 457 case 0x14:
va009039 1:913dfd59e25a 458 d = rxdat;
va009039 1:913dfd59e25a 459 V6M_INFO("P: LPC_SPI%d->RXDAT >> %08x", ch, d);
va009039 1:913dfd59e25a 460 break;
va009039 1:913dfd59e25a 461 case 0x18:
va009039 1:913dfd59e25a 462 V6M_INFO("P: LPC_SPI%d->TXDATCTL >> %08x", ch, d);
va009039 1:913dfd59e25a 463 break;
va009039 1:913dfd59e25a 464 default:
va009039 1:913dfd59e25a 465 V6M_WARN("P: LPC_SPI%d %08x >> %08x", ch, a, d);
va009039 1:913dfd59e25a 466 break;
va009039 1:913dfd59e25a 467 }
va009039 1:913dfd59e25a 468 return d;
va009039 1:913dfd59e25a 469 }
va009039 1:913dfd59e25a 470
va009039 1:913dfd59e25a 471 EMU81x_SCB::EMU81x_SCB() {
va009039 1:913dfd59e25a 472 vtor = 0;
va009039 1:913dfd59e25a 473 }
va009039 1:913dfd59e25a 474
va009039 1:913dfd59e25a 475 void EMU81x_SCB::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 476 switch(a&0xfff) {
va009039 1:913dfd59e25a 477 case 0xd08:
va009039 1:913dfd59e25a 478 vtor = d;
va009039 1:913dfd59e25a 479 V6M_INFO("P: SCB->VTOR << %08x", d);
va009039 1:913dfd59e25a 480 break;
va009039 1:913dfd59e25a 481 default:
va009039 1:913dfd59e25a 482 V6M_WARN("P: SCB %08x << %08x", a, d);
va009039 1:913dfd59e25a 483 break;
va009039 1:913dfd59e25a 484 }
va009039 1:913dfd59e25a 485 }
va009039 1:913dfd59e25a 486
va009039 1:913dfd59e25a 487 uint32_t EMU81x_SCB::peek32(uint32_t a) {
va009039 1:913dfd59e25a 488 uint32_t d = 0x00;
va009039 1:913dfd59e25a 489 switch(a&0xfff) {
va009039 1:913dfd59e25a 490 case 0xd08:
va009039 1:913dfd59e25a 491 d = vtor;
va009039 1:913dfd59e25a 492 V6M_INFO("P: SCB->VTOR >> %08x", d);
va009039 1:913dfd59e25a 493 break;
va009039 1:913dfd59e25a 494 default:
va009039 1:913dfd59e25a 495 V6M_WARN("P: SCB %08x >> %08x", a, d);
va009039 1:913dfd59e25a 496 break;
va009039 1:913dfd59e25a 497 }
va009039 1:913dfd59e25a 498 return d;
va009039 1:913dfd59e25a 499 }
va009039 1:913dfd59e25a 500
va009039 1:913dfd59e25a 501 void EMU81x_NVIC::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 502 switch(a) {
va009039 1:913dfd59e25a 503 case 0xe000e100:
va009039 1:913dfd59e25a 504 iser = d;
va009039 1:913dfd59e25a 505 V6M_INFO("P: NVIC->ISER[0] << %08x", d);
va009039 1:913dfd59e25a 506 break;
va009039 2:3f3637d7c2bc 507 case 0xe000e180:
va009039 2:3f3637d7c2bc 508 V6M_INFO("P: NVIC->ICPR[0] << %08x", d);
va009039 2:3f3637d7c2bc 509 break;
va009039 1:913dfd59e25a 510 default:
va009039 1:913dfd59e25a 511 V6M_WARN("P: NVIC %08x >> %08x", a, d);
va009039 1:913dfd59e25a 512 break;
va009039 1:913dfd59e25a 513 }
va009039 1:913dfd59e25a 514 }
va009039 1:913dfd59e25a 515
va009039 2:3f3637d7c2bc 516 EMU81x::EMU81x():_uart0(*this,0),_uart1(*this,1),_uart2(*this,2),gpio(*this)
va009039 2:3f3637d7c2bc 517 ,_i2c(*this), _spi0(*this, 0), _spi1(*this, 1) {
va009039 1:913dfd59e25a 518 flash = NULL;
va009039 1:913dfd59e25a 519 rom = NULL;
va009039 1:913dfd59e25a 520 ram = new uint8_t[EMU81x_RAM_SIZE];
va009039 1:913dfd59e25a 521 }
va009039 1:913dfd59e25a 522
va009039 1:913dfd59e25a 523 EMU81x::~EMU81x() {
va009039 1:913dfd59e25a 524 delete[] ram;
va009039 1:913dfd59e25a 525 }
va009039 1:913dfd59e25a 526
va009039 1:913dfd59e25a 527 void EMU81x::poke32(uint32_t a, uint32_t d) {
va009039 1:913dfd59e25a 528 switch(a>>24) {
va009039 1:913dfd59e25a 529 case EMU81x_RAM_BASE>>24:
va009039 1:913dfd59e25a 530 V6M_ASSERT(a < (EMU81x_RAM_BASE+EMU81x_RAM_SIZE));
va009039 1:913dfd59e25a 531 V6M_ASSERT(ram);
va009039 1:913dfd59e25a 532 ram[a - EMU81x_RAM_BASE + 0] = d>>0;
va009039 1:913dfd59e25a 533 ram[a - EMU81x_RAM_BASE + 1] = d>>8;
va009039 1:913dfd59e25a 534 ram[a - EMU81x_RAM_BASE + 2] = d>>16;
va009039 1:913dfd59e25a 535 ram[a - EMU81x_RAM_BASE + 3] = d>>24;
va009039 1:913dfd59e25a 536 V6M_INFO("W: %08x << %08x", a, d);
va009039 1:913dfd59e25a 537 break;
va009039 1:913dfd59e25a 538 case EMU81x_APB_BASE>>24:
va009039 1:913dfd59e25a 539 switch((a>>12)&0xff) {
va009039 1:913dfd59e25a 540 case 0x04: mrt.poke32(a, d); break;
va009039 1:913dfd59e25a 541 case 0x0c: swm.poke32(a, d); break;
va009039 1:913dfd59e25a 542 case 0x48: syscon.poke32(a, d); break;
va009039 1:913dfd59e25a 543 case 0x44: iocon.poke32(a, d); break;
va009039 2:3f3637d7c2bc 544 case 0x50: _i2c.poke32(a, d); break;
va009039 2:3f3637d7c2bc 545 case 0x58: _spi0.poke32(a, d); break;
va009039 2:3f3637d7c2bc 546 case 0x5c: _spi1.poke32(a, d); break;
va009039 2:3f3637d7c2bc 547 case 0x64: _uart0.poke32(a, d); break;
va009039 2:3f3637d7c2bc 548 case 0x68: _uart1.poke32(a, d); break;
va009039 2:3f3637d7c2bc 549 case 0x6c: _uart2.poke32(a, d); break;
va009039 1:913dfd59e25a 550 default:
va009039 1:913dfd59e25a 551 V6M_WARN("P: %08x << %08x", a, d);
va009039 1:913dfd59e25a 552 break;
va009039 1:913dfd59e25a 553 }
va009039 1:913dfd59e25a 554 break;
va009039 1:913dfd59e25a 555 case EMU81x_AHB_BASE>>24:
va009039 1:913dfd59e25a 556 V6M_WARN("P: %08x << %08x", a, d);
va009039 1:913dfd59e25a 557 break;
va009039 1:913dfd59e25a 558 case EMU81x_FLASH_BASE>>24:
va009039 1:913dfd59e25a 559 case EMU81x_ROM_BASE>>24:
va009039 1:913dfd59e25a 560 V6M_ASSERT(0);
va009039 1:913dfd59e25a 561 break;
va009039 1:913dfd59e25a 562 case EMU81x_GPIO_PORT_BASE>>24:
va009039 1:913dfd59e25a 563 gpio.poke32(a, d);
va009039 1:913dfd59e25a 564 break;
va009039 1:913dfd59e25a 565 case EMU81x_SCS_BASE>>24:
va009039 1:913dfd59e25a 566 switch(a&0xffffff) {
va009039 1:913dfd59e25a 567 case 0x00e100:
va009039 2:3f3637d7c2bc 568 case 0x00e180:
va009039 1:913dfd59e25a 569 nvic.poke32(a, d);
va009039 1:913dfd59e25a 570 break;
va009039 1:913dfd59e25a 571 case 0x00ed08:
va009039 1:913dfd59e25a 572 scb.poke32(a, d);
va009039 1:913dfd59e25a 573 break;
va009039 1:913dfd59e25a 574 default:
va009039 1:913dfd59e25a 575 V6M_WARN("P: %08x << %08x", a, d);
va009039 1:913dfd59e25a 576 break;
va009039 1:913dfd59e25a 577 }
va009039 1:913dfd59e25a 578 break;
va009039 1:913dfd59e25a 579 default:
va009039 1:913dfd59e25a 580 V6M_WARN("P: %08x << %08x", a, d);
va009039 1:913dfd59e25a 581 break;
va009039 1:913dfd59e25a 582 }
va009039 1:913dfd59e25a 583 }
va009039 1:913dfd59e25a 584
va009039 1:913dfd59e25a 585 uint32_t EMU81x::peek32(uint32_t a) {
va009039 1:913dfd59e25a 586 uint32_t d = 0x00;
va009039 1:913dfd59e25a 587 switch(a>>24) {
va009039 1:913dfd59e25a 588 case EMU81x_RAM_BASE>>24:
va009039 1:913dfd59e25a 589 V6M_ASSERT(a < (EMU81x_RAM_BASE+EMU81x_RAM_SIZE));
va009039 1:913dfd59e25a 590 d = ram[a - EMU81x_RAM_BASE];
va009039 1:913dfd59e25a 591 d |= ram[a - EMU81x_RAM_BASE + 1]<<8;
va009039 1:913dfd59e25a 592 d |= ram[a - EMU81x_RAM_BASE + 2]<<16;
va009039 1:913dfd59e25a 593 d |= ram[a - EMU81x_RAM_BASE + 3]<<24;
va009039 1:913dfd59e25a 594 V6M_INFO("R: %08x >> %08x", a, d);
va009039 1:913dfd59e25a 595 break;
va009039 1:913dfd59e25a 596 case EMU81x_FLASH_BASE>>24:
va009039 1:913dfd59e25a 597 V6M_ASSERT(a < (EMU81x_FLASH_BASE+EMU81x_FLASH_SIZE));
va009039 1:913dfd59e25a 598 V6M_ASSERT(flash);
va009039 1:913dfd59e25a 599 d = flash[a - EMU81x_FLASH_BASE];
va009039 1:913dfd59e25a 600 d |= flash[a - EMU81x_FLASH_BASE + 1]<<8;
va009039 1:913dfd59e25a 601 d |= flash[a - EMU81x_FLASH_BASE + 2]<<16;
va009039 1:913dfd59e25a 602 d |= flash[a - EMU81x_FLASH_BASE + 3]<<24;
va009039 1:913dfd59e25a 603 break;
va009039 1:913dfd59e25a 604 case EMU81x_ROM_BASE>>24:
va009039 1:913dfd59e25a 605 V6M_ASSERT(a < (EMU81x_ROM_BASE+EMU81x_ROM_SIZE));
va009039 1:913dfd59e25a 606 V6M_ASSERT(rom);
va009039 1:913dfd59e25a 607 d = rom[a - EMU81x_ROM_BASE];
va009039 1:913dfd59e25a 608 d |= rom[a - EMU81x_ROM_BASE + 1]<<8;
va009039 1:913dfd59e25a 609 d |= rom[a - EMU81x_ROM_BASE + 2]<<16;
va009039 1:913dfd59e25a 610 d |= rom[a - EMU81x_ROM_BASE + 3]<<24;
va009039 1:913dfd59e25a 611 break;
va009039 1:913dfd59e25a 612 case EMU81x_APB_BASE>>24:
va009039 1:913dfd59e25a 613 switch((a>>12)&0xff) {
va009039 1:913dfd59e25a 614 case 0x04: d = mrt.peek32(a); break;
va009039 1:913dfd59e25a 615 case 0x0c: d = swm.peek32(a); break;
va009039 1:913dfd59e25a 616 case 0x44: d = iocon.peek32(a); break;
va009039 1:913dfd59e25a 617 case 0x48: d = syscon.peek32(a); break;
va009039 2:3f3637d7c2bc 618 case 0x50: d = _i2c.peek32(a); break;
va009039 2:3f3637d7c2bc 619 case 0x58: d = _spi0.peek32(a); break;
va009039 2:3f3637d7c2bc 620 case 0x5c: d = _spi1.peek32(a); break;
va009039 2:3f3637d7c2bc 621 case 0x64: d = _uart0.peek32(a); break;
va009039 2:3f3637d7c2bc 622 case 0x68: d = _uart1.peek32(a); break;
va009039 2:3f3637d7c2bc 623 case 0x6c: d = _uart2.peek32(a); break;
va009039 1:913dfd59e25a 624 default:
va009039 1:913dfd59e25a 625 V6M_WARN("P: %08x >> %08x", a, d);
va009039 1:913dfd59e25a 626 break;
va009039 1:913dfd59e25a 627 }
va009039 1:913dfd59e25a 628 break;
va009039 1:913dfd59e25a 629 case EMU81x_GPIO_PORT_BASE>>24:
va009039 1:913dfd59e25a 630 d = gpio.peek32(a);
va009039 1:913dfd59e25a 631 break;
va009039 1:913dfd59e25a 632 case 0xe0:
va009039 1:913dfd59e25a 633 switch(a&0xffffff) {
va009039 1:913dfd59e25a 634 case 0x00ed08:
va009039 1:913dfd59e25a 635 d = scb.peek32(a);
va009039 1:913dfd59e25a 636 break;
va009039 1:913dfd59e25a 637 default:
va009039 1:913dfd59e25a 638 V6M_WARN("P: %08x >> %08x", a, d);
va009039 1:913dfd59e25a 639 break;
va009039 1:913dfd59e25a 640 }
va009039 1:913dfd59e25a 641 break;
va009039 1:913dfd59e25a 642 default:
va009039 1:913dfd59e25a 643 V6M_WARN("P: %08x >> %08x", a, d);
va009039 1:913dfd59e25a 644 break;
va009039 1:913dfd59e25a 645 }
va009039 1:913dfd59e25a 646 return d;
va009039 1:913dfd59e25a 647 }
va009039 1:913dfd59e25a 648
va009039 1:913dfd59e25a 649 void EMU81x::poke8(uint32_t a, uint8_t d) {
va009039 1:913dfd59e25a 650 switch(a>>24) {
va009039 1:913dfd59e25a 651 case EMU81x_RAM_BASE>>24:
va009039 1:913dfd59e25a 652 V6M_ASSERT(a < (EMU81x_RAM_BASE+EMU81x_RAM_SIZE));
va009039 1:913dfd59e25a 653 V6M_ASSERT(ram);
va009039 1:913dfd59e25a 654 ram[a - EMU81x_RAM_BASE] = d;
va009039 1:913dfd59e25a 655 V6M_INFO("W: %08x << %02x", a, d);
va009039 1:913dfd59e25a 656 break;
va009039 1:913dfd59e25a 657 default:
va009039 1:913dfd59e25a 658 V6M_ASSERT(0);
va009039 1:913dfd59e25a 659 break;
va009039 1:913dfd59e25a 660 }
va009039 1:913dfd59e25a 661 }
va009039 1:913dfd59e25a 662
va009039 1:913dfd59e25a 663 uint8_t EMU81x::peek8(uint32_t a) {
va009039 1:913dfd59e25a 664 uint8_t d = 0x00;
va009039 1:913dfd59e25a 665 switch(a>>24) {
va009039 1:913dfd59e25a 666 case EMU81x_RAM_BASE>>24:
va009039 1:913dfd59e25a 667 V6M_ASSERT(a < (EMU81x_RAM_BASE+EMU81x_RAM_SIZE));
va009039 1:913dfd59e25a 668 d = ram[a - EMU81x_RAM_BASE];
va009039 1:913dfd59e25a 669 V6M_INFO("R: %08x >> %02x", a, d);
va009039 1:913dfd59e25a 670 break;
va009039 1:913dfd59e25a 671 case EMU81x_FLASH_BASE>>24:
va009039 1:913dfd59e25a 672 V6M_ASSERT(a < (EMU81x_FLASH_BASE+EMU81x_FLASH_SIZE));
va009039 1:913dfd59e25a 673 d = flash[a - EMU81x_FLASH_BASE];
va009039 1:913dfd59e25a 674 break;
va009039 1:913dfd59e25a 675 case EMU81x_ROM_BASE>>24:
va009039 1:913dfd59e25a 676 V6M_ASSERT(a < (EMU81x_ROM_BASE+EMU81x_ROM_SIZE));
va009039 1:913dfd59e25a 677 d = rom[a - EMU81x_ROM_BASE];
va009039 1:913dfd59e25a 678 break;
va009039 1:913dfd59e25a 679 default:
va009039 1:913dfd59e25a 680 V6M_ASSERT(0);
va009039 1:913dfd59e25a 681 break;
va009039 1:913dfd59e25a 682 }
va009039 1:913dfd59e25a 683 return d;
va009039 1:913dfd59e25a 684 }
va009039 1:913dfd59e25a 685
va009039 1:913dfd59e25a 686 void EMU81x::clock_in(uint32_t n) {
va009039 1:913dfd59e25a 687 mrt.clock_in(n);
va009039 1:913dfd59e25a 688 }
va009039 1:913dfd59e25a 689
va009039 1:913dfd59e25a 690 void EMU81x::trace() {
va009039 1:913dfd59e25a 691 V6M_INFO("S: r0=%08x r1=%08x r2=%08x r3=%08x r4=%08x r5=%08x r6=%08x r7=%08x", R[0],R[1],R[2],R[3],R[4],R[5],R[6],R[7]);
va009039 1:913dfd59e25a 692 V6M_INFO("S: r8=%08x r9=%08x r10=%08x r11=%08x r12=%08x sp=%08x lr=%08x pc=%08x", R[8],R[9],R[10],R[11],R[12],R[13],R[14],R[15]);
va009039 1:913dfd59e25a 693 V6M_INFO("S: xPSR=%08x N=%d Z=%d C=%d V=%d", R[16], N(), Z(), C(), V());
va009039 1:913dfd59e25a 694 V6M_DEBUG("S: cycle=%d code=%02x code2nd=%02x im=%08x d=%d n=%d m=%d", cycle, code, code2nd, R[17], GetRegIndex(Rd), GetRegIndex(Rn), GetRegIndex(Rm));
va009039 1:913dfd59e25a 695
va009039 1:913dfd59e25a 696 }
va009039 1:913dfd59e25a 697