mbed LPC812 emulator pre-alpha version
Dependencies: BaseV6M mbed F12RFileSystem F32RFileSystem ROMSLOT SDStorage
Example
TTB_mbed_LPC812.bin save as "LPC812.IMG" .
internal boot rom image(0x1fff0000-0x1fff1fff) save as "LPC812.ROM".
Tested programs
- TTB_mbed - TOYOSHIKI TINY BASIC mbed Edition
- mbed_blinky - LED1 blinky
EMU81x.cpp@1:913dfd59e25a, 2015-08-10 (annotated)
- Committer:
- va009039
- Date:
- Mon Aug 10 22:52:48 2015 +0900
- Revision:
- 1:913dfd59e25a
- Child:
- 2:3f3637d7c2bc
add files.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
va009039 |
1:913dfd59e25a | 1 | // EMU81x.cpp 2015/8/8 |
va009039 |
1:913dfd59e25a | 2 | #include "mbed.h" |
va009039 |
1:913dfd59e25a | 3 | #include "EMU81x.h" |
va009039 |
1:913dfd59e25a | 4 | #define V6M_LOG_LEVEL 2 |
va009039 |
1:913dfd59e25a | 5 | #include "v6m_log.h" |
va009039 |
1:913dfd59e25a | 6 | |
va009039 |
1:913dfd59e25a | 7 | const int EMU81x_RAM_SIZE = (1024*4); |
va009039 |
1:913dfd59e25a | 8 | const int EMU81x_FLASH_SIZE = (1024*16); |
va009039 |
1:913dfd59e25a | 9 | const int EMU81x_ROM_SIZE = (1024*8); |
va009039 |
1:913dfd59e25a | 10 | |
va009039 |
1:913dfd59e25a | 11 | const uint32_t EMU81x_FLASH_BASE = 0x00000000; |
va009039 |
1:913dfd59e25a | 12 | const uint32_t EMU81x_RAM_BASE = 0x10000000; |
va009039 |
1:913dfd59e25a | 13 | const uint32_t EMU81x_ROM_BASE = 0x1fff0000; |
va009039 |
1:913dfd59e25a | 14 | const uint32_t EMU81x_APB_BASE = 0x40000000; |
va009039 |
1:913dfd59e25a | 15 | const uint32_t EMU81x_AHB_BASE = 0x50000000; |
va009039 |
1:913dfd59e25a | 16 | const uint32_t EMU81x_GPIO_PORT_BASE = 0xa0000000; |
va009039 |
1:913dfd59e25a | 17 | const uint32_t EMU81x_SCS_BASE = 0xe000e000; |
va009039 |
1:913dfd59e25a | 18 | |
va009039 |
1:913dfd59e25a | 19 | EMU81x_USART::EMU81x_USART(EMU81x& mcu_, int ch_):mcu(mcu_),ch(ch_) { |
va009039 |
1:913dfd59e25a | 20 | V6M_ASSERT(ch >= 0 && ch <= 2); |
va009039 |
1:913dfd59e25a | 21 | cfg = 0x00; |
va009039 |
1:913dfd59e25a | 22 | } |
va009039 |
1:913dfd59e25a | 23 | |
va009039 |
1:913dfd59e25a | 24 | void EMU81x_USART::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 25 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 26 | case 0x00: |
va009039 |
1:913dfd59e25a | 27 | cfg = d; |
va009039 |
1:913dfd59e25a | 28 | V6M_INFO("P: LPC_USART%d->CFG << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 29 | break; |
va009039 |
1:913dfd59e25a | 30 | case 0x08: |
va009039 |
1:913dfd59e25a | 31 | V6M_INFO("P: LPC_USART%d->STAT << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 32 | break; |
va009039 |
1:913dfd59e25a | 33 | case 0x10: |
va009039 |
1:913dfd59e25a | 34 | V6M_INFO("P: LPC_USART%d->INTENCLR << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 35 | break; |
va009039 |
1:913dfd59e25a | 36 | case 0x1c: |
va009039 |
1:913dfd59e25a | 37 | mcu.SerialPutc_Callback(ch, d); |
va009039 |
1:913dfd59e25a | 38 | V6M_INFO("P: LPC_USART%d->TXDATA << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 39 | break; |
va009039 |
1:913dfd59e25a | 40 | case 0x20: |
va009039 |
1:913dfd59e25a | 41 | V6M_INFO("P: LPC_USART%d->TXCTRL << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 42 | break; |
va009039 |
1:913dfd59e25a | 43 | default: |
va009039 |
1:913dfd59e25a | 44 | V6M_WARN("P: LPC_UART%d %08x << %08x", ch, a, d); |
va009039 |
1:913dfd59e25a | 45 | break; |
va009039 |
1:913dfd59e25a | 46 | } |
va009039 |
1:913dfd59e25a | 47 | } |
va009039 |
1:913dfd59e25a | 48 | |
va009039 |
1:913dfd59e25a | 49 | uint32_t EMU81x_USART::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 50 | uint32_t d = 0x00; |
va009039 |
1:913dfd59e25a | 51 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 52 | case 0x00: |
va009039 |
1:913dfd59e25a | 53 | d = cfg; |
va009039 |
1:913dfd59e25a | 54 | V6M_INFO("P: LPC_USART%d->CFG >> %08x", ch, d); |
va009039 |
1:913dfd59e25a | 55 | break; |
va009039 |
1:913dfd59e25a | 56 | case 0x08: |
va009039 |
1:913dfd59e25a | 57 | d = 0x04; |
va009039 |
1:913dfd59e25a | 58 | if (mcu.SerialReadable_Callback(ch)) { |
va009039 |
1:913dfd59e25a | 59 | d |= 0x01; |
va009039 |
1:913dfd59e25a | 60 | } |
va009039 |
1:913dfd59e25a | 61 | V6M_INFO("P: LPC_USART%d->STAT >> %08x", ch, d); |
va009039 |
1:913dfd59e25a | 62 | break; |
va009039 |
1:913dfd59e25a | 63 | case 0x14: |
va009039 |
1:913dfd59e25a | 64 | d = mcu.SerialGetc_Callback(ch); |
va009039 |
1:913dfd59e25a | 65 | V6M_INFO("P: LPC_USART%d->RXDATA >> %08x", ch, d); |
va009039 |
1:913dfd59e25a | 66 | break; |
va009039 |
1:913dfd59e25a | 67 | default: |
va009039 |
1:913dfd59e25a | 68 | V6M_WARN("P: LPC_USART%d %08x >> %08x", ch, a, d); |
va009039 |
1:913dfd59e25a | 69 | break; |
va009039 |
1:913dfd59e25a | 70 | } |
va009039 |
1:913dfd59e25a | 71 | return d; |
va009039 |
1:913dfd59e25a | 72 | } |
va009039 |
1:913dfd59e25a | 73 | |
va009039 |
1:913dfd59e25a | 74 | EMU81x_MRT::EMU81x_MRT():timer0(0x7fffffff) { |
va009039 |
1:913dfd59e25a | 75 | } |
va009039 |
1:913dfd59e25a | 76 | |
va009039 |
1:913dfd59e25a | 77 | void EMU81x_MRT::clock_in(uint32_t n) { |
va009039 |
1:913dfd59e25a | 78 | V6M_ASSERT(n != 0); |
va009039 |
1:913dfd59e25a | 79 | timer0 = (timer0 - n) & 0x7fffffff; |
va009039 |
1:913dfd59e25a | 80 | } |
va009039 |
1:913dfd59e25a | 81 | |
va009039 |
1:913dfd59e25a | 82 | void EMU81x_MRT::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 83 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 84 | case 0x00: |
va009039 |
1:913dfd59e25a | 85 | V6M_INFO("P: LPC_MRT->INTVAL0 << %08x", d); |
va009039 |
1:913dfd59e25a | 86 | break; |
va009039 |
1:913dfd59e25a | 87 | case 0x08: |
va009039 |
1:913dfd59e25a | 88 | V6M_INFO("P: LPC_MRT->CTRL0 << %08x", d); |
va009039 |
1:913dfd59e25a | 89 | break; |
va009039 |
1:913dfd59e25a | 90 | case 0x10: |
va009039 |
1:913dfd59e25a | 91 | V6M_INFO("P: LPC_MRT->INTVAL1 << %08x", d); |
va009039 |
1:913dfd59e25a | 92 | break; |
va009039 |
1:913dfd59e25a | 93 | case 0x18: |
va009039 |
1:913dfd59e25a | 94 | V6M_INFO("P: LPC_MRT->CTRL1 << %08x", d); |
va009039 |
1:913dfd59e25a | 95 | break; |
va009039 |
1:913dfd59e25a | 96 | default: |
va009039 |
1:913dfd59e25a | 97 | V6M_WARN("P: LPC_MRT %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 98 | break; |
va009039 |
1:913dfd59e25a | 99 | } |
va009039 |
1:913dfd59e25a | 100 | } |
va009039 |
1:913dfd59e25a | 101 | |
va009039 |
1:913dfd59e25a | 102 | uint32_t EMU81x_MRT::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 103 | uint32_t d = 0x00; |
va009039 |
1:913dfd59e25a | 104 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 105 | case 0x04: |
va009039 |
1:913dfd59e25a | 106 | d = timer0; |
va009039 |
1:913dfd59e25a | 107 | V6M_INFO("P: LPC_MRT->TIMER0 >> %u", timer0); |
va009039 |
1:913dfd59e25a | 108 | break; |
va009039 |
1:913dfd59e25a | 109 | default: |
va009039 |
1:913dfd59e25a | 110 | V6M_WARN("P: LPC_MRT %08x >> %02x", a, d); |
va009039 |
1:913dfd59e25a | 111 | break; |
va009039 |
1:913dfd59e25a | 112 | } |
va009039 |
1:913dfd59e25a | 113 | return d; |
va009039 |
1:913dfd59e25a | 114 | } |
va009039 |
1:913dfd59e25a | 115 | |
va009039 |
1:913dfd59e25a | 116 | EMU81x_IOCON::EMU81x_IOCON() { |
va009039 |
1:913dfd59e25a | 117 | pio0_17 = 0x90; |
va009039 |
1:913dfd59e25a | 118 | pio0_13 = 0x90; |
va009039 |
1:913dfd59e25a | 119 | pio0_12 = 0x90; |
va009039 |
1:913dfd59e25a | 120 | pio0_5 = 0x90; |
va009039 |
1:913dfd59e25a | 121 | pio0_4 = 0x90; |
va009039 |
1:913dfd59e25a | 122 | pio0_3 = 0x90; |
va009039 |
1:913dfd59e25a | 123 | pio0_2 = 0x90; |
va009039 |
1:913dfd59e25a | 124 | pio0_11 = 0x80; |
va009039 |
1:913dfd59e25a | 125 | pio0_10 = 0x80; |
va009039 |
1:913dfd59e25a | 126 | pio0_16 = 0x90; |
va009039 |
1:913dfd59e25a | 127 | pio0_15 = 0x90; |
va009039 |
1:913dfd59e25a | 128 | pio0_1 = 0x90; |
va009039 |
1:913dfd59e25a | 129 | pio0_9 = 0x90; |
va009039 |
1:913dfd59e25a | 130 | pio0_8 = 0x90; |
va009039 |
1:913dfd59e25a | 131 | pio0_7 = 0x90; |
va009039 |
1:913dfd59e25a | 132 | pio0_6 = 0x90; |
va009039 |
1:913dfd59e25a | 133 | pio0_0 = 0x90; |
va009039 |
1:913dfd59e25a | 134 | pio0_14 = 0x90; |
va009039 |
1:913dfd59e25a | 135 | } |
va009039 |
1:913dfd59e25a | 136 | |
va009039 |
1:913dfd59e25a | 137 | void EMU81x_IOCON::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 138 | int pin = -1; |
va009039 |
1:913dfd59e25a | 139 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 140 | case 0x00: pio0_17 = d; pin = 17; break; |
va009039 |
1:913dfd59e25a | 141 | case 0x04: pio0_13 = d; pin = 13; break; |
va009039 |
1:913dfd59e25a | 142 | case 0x08: pio0_12 = d; pin = 12; break; |
va009039 |
1:913dfd59e25a | 143 | case 0x0c: pio0_5 = d; pin = 5; break; |
va009039 |
1:913dfd59e25a | 144 | case 0x10: pio0_3 = d; pin = 3; break; |
va009039 |
1:913dfd59e25a | 145 | case 0x14: pio0_4 = d; pin = 4; break; |
va009039 |
1:913dfd59e25a | 146 | case 0x18: pio0_2 = d; pin = 2; break; |
va009039 |
1:913dfd59e25a | 147 | case 0x1c: pio0_11 = d; pin = 11; break; |
va009039 |
1:913dfd59e25a | 148 | case 0x20: pio0_10 = d; pin = 10; break; |
va009039 |
1:913dfd59e25a | 149 | case 0x24: pio0_16 = d; pin = 16; break; |
va009039 |
1:913dfd59e25a | 150 | case 0x28: pio0_15 = d; pin = 15; break; |
va009039 |
1:913dfd59e25a | 151 | case 0x2c: pio0_1 = d; pin = 1; break; |
va009039 |
1:913dfd59e25a | 152 | case 0x34: pio0_9 = d; pin = 9; break; |
va009039 |
1:913dfd59e25a | 153 | case 0x38: pio0_8 = d; pin = 8; break; |
va009039 |
1:913dfd59e25a | 154 | case 0x3c: pio0_7 = d; pin = 7; break; |
va009039 |
1:913dfd59e25a | 155 | case 0x40: pio0_6 = d; pin = 6; break; |
va009039 |
1:913dfd59e25a | 156 | case 0x44: pio0_0 = d; pin = 0; break; |
va009039 |
1:913dfd59e25a | 157 | case 0x48: pio0_14 = d; pin = 14; break; |
va009039 |
1:913dfd59e25a | 158 | } |
va009039 |
1:913dfd59e25a | 159 | if (pin >= 0) { |
va009039 |
1:913dfd59e25a | 160 | V6M_INFO("P: LPC_IOCON->PIO0_%d << %04x", pin, d); |
va009039 |
1:913dfd59e25a | 161 | } else { |
va009039 |
1:913dfd59e25a | 162 | V6M_WARN("P: LPC_IOCON %08x << %04x", a, d); |
va009039 |
1:913dfd59e25a | 163 | } |
va009039 |
1:913dfd59e25a | 164 | } |
va009039 |
1:913dfd59e25a | 165 | |
va009039 |
1:913dfd59e25a | 166 | uint32_t EMU81x_IOCON::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 167 | int pin = -1; |
va009039 |
1:913dfd59e25a | 168 | uint32_t d = 0x00; |
va009039 |
1:913dfd59e25a | 169 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 170 | case 0x00: d = pio0_17; pin = 17; break; |
va009039 |
1:913dfd59e25a | 171 | case 0x04: d = pio0_13; pin = 13; break; |
va009039 |
1:913dfd59e25a | 172 | case 0x08: d = pio0_12; pin = 12; break; |
va009039 |
1:913dfd59e25a | 173 | case 0x0c: d = pio0_5; pin = 5; break; |
va009039 |
1:913dfd59e25a | 174 | case 0x10: d = pio0_3; pin = 3; break; |
va009039 |
1:913dfd59e25a | 175 | case 0x14: d = pio0_4; pin = 4; break; |
va009039 |
1:913dfd59e25a | 176 | case 0x18: d = pio0_2; pin = 2; break; |
va009039 |
1:913dfd59e25a | 177 | case 0x1c: d = pio0_11; pin = 11; break; |
va009039 |
1:913dfd59e25a | 178 | case 0x20: d = pio0_10; pin = 10; break; |
va009039 |
1:913dfd59e25a | 179 | case 0x24: d = pio0_16; pin = 16; break; |
va009039 |
1:913dfd59e25a | 180 | case 0x28: d = pio0_15; pin = 15; break; |
va009039 |
1:913dfd59e25a | 181 | case 0x2c: d = pio0_1; pin = 1; break; |
va009039 |
1:913dfd59e25a | 182 | case 0x34: d = pio0_9; pin = 9; break; |
va009039 |
1:913dfd59e25a | 183 | case 0x38: d = pio0_8; pin = 8; break; |
va009039 |
1:913dfd59e25a | 184 | case 0x3c: d = pio0_7; pin = 7; break; |
va009039 |
1:913dfd59e25a | 185 | case 0x40: d = pio0_6; pin = 6; break; |
va009039 |
1:913dfd59e25a | 186 | case 0x44: d = pio0_0; pin = 0; break; |
va009039 |
1:913dfd59e25a | 187 | case 0x48: d = pio0_14; pin = 14; break; |
va009039 |
1:913dfd59e25a | 188 | } |
va009039 |
1:913dfd59e25a | 189 | if (pin >= 0) { |
va009039 |
1:913dfd59e25a | 190 | V6M_INFO("P: LPC_IOCON->PIO0_%d >> %04x", pin, d); |
va009039 |
1:913dfd59e25a | 191 | } else { |
va009039 |
1:913dfd59e25a | 192 | V6M_WARN("P: LPC_IOCON %08x >> %04x", a, d); |
va009039 |
1:913dfd59e25a | 193 | } |
va009039 |
1:913dfd59e25a | 194 | return d; |
va009039 |
1:913dfd59e25a | 195 | } |
va009039 |
1:913dfd59e25a | 196 | |
va009039 |
1:913dfd59e25a | 197 | EMU81x_SYSCON::EMU81x_SYSCON() { |
va009039 |
1:913dfd59e25a | 198 | } |
va009039 |
1:913dfd59e25a | 199 | |
va009039 |
1:913dfd59e25a | 200 | void EMU81x_SYSCON::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 201 | switch(a&0xfff) { |
va009039 |
1:913dfd59e25a | 202 | case 0x004: |
va009039 |
1:913dfd59e25a | 203 | V6M_INFO("P: LPC_SYSCON->PRESETCTRL << %08x", d); |
va009039 |
1:913dfd59e25a | 204 | break; |
va009039 |
1:913dfd59e25a | 205 | case 0x008: |
va009039 |
1:913dfd59e25a | 206 | V6M_INFO("P: LPC_SYSCON->SYSPLLCTRL << %08x", d); |
va009039 |
1:913dfd59e25a | 207 | break; |
va009039 |
1:913dfd59e25a | 208 | case 0x040: |
va009039 |
1:913dfd59e25a | 209 | V6M_INFO("P: LPC_SYSCON->SYSPLLCLKSEL << %08x", d); |
va009039 |
1:913dfd59e25a | 210 | break; |
va009039 |
1:913dfd59e25a | 211 | case 0x044: |
va009039 |
1:913dfd59e25a | 212 | V6M_INFO("P: LPC_SYSCON->SYSPLLCLKUEN << %08x", d); |
va009039 |
1:913dfd59e25a | 213 | break; |
va009039 |
1:913dfd59e25a | 214 | case 0x070: |
va009039 |
1:913dfd59e25a | 215 | V6M_INFO("P: LPC_SYSCON->MAINCLKSEL << %08x", d); |
va009039 |
1:913dfd59e25a | 216 | break; |
va009039 |
1:913dfd59e25a | 217 | case 0x074: |
va009039 |
1:913dfd59e25a | 218 | V6M_INFO("P: LPC_SYSCON->MAINCLKUEN << %08x", d); |
va009039 |
1:913dfd59e25a | 219 | break; |
va009039 |
1:913dfd59e25a | 220 | case 0x078: |
va009039 |
1:913dfd59e25a | 221 | V6M_INFO("P: LPC_SYSCON->SYSAHBCLKDIV << %08x", d); |
va009039 |
1:913dfd59e25a | 222 | break; |
va009039 |
1:913dfd59e25a | 223 | case 0x080: |
va009039 |
1:913dfd59e25a | 224 | V6M_INFO("P: LPC_SYSCON->SYSAHBCLKCTRL << %08x", d); |
va009039 |
1:913dfd59e25a | 225 | break; |
va009039 |
1:913dfd59e25a | 226 | case 0x094: |
va009039 |
1:913dfd59e25a | 227 | V6M_INFO("P: LPC_SYSCON->UARTCLKDIV << %08x", d); |
va009039 |
1:913dfd59e25a | 228 | break; |
va009039 |
1:913dfd59e25a | 229 | case 0x238: |
va009039 |
1:913dfd59e25a | 230 | V6M_INFO("P: LPC_SYSCON->PDRUNCFG << %08x", d); |
va009039 |
1:913dfd59e25a | 231 | break; |
va009039 |
1:913dfd59e25a | 232 | default: |
va009039 |
1:913dfd59e25a | 233 | V6M_WARN("P: LPC_SYSCON %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 234 | break; |
va009039 |
1:913dfd59e25a | 235 | } |
va009039 |
1:913dfd59e25a | 236 | } |
va009039 |
1:913dfd59e25a | 237 | |
va009039 |
1:913dfd59e25a | 238 | uint32_t EMU81x_SYSCON::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 239 | uint32_t d = 0x00; |
va009039 |
1:913dfd59e25a | 240 | switch(a&0xfff) { |
va009039 |
1:913dfd59e25a | 241 | case 0x004: |
va009039 |
1:913dfd59e25a | 242 | V6M_INFO("P: LPC_SYSCON->PRESETCTRL >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 243 | break; |
va009039 |
1:913dfd59e25a | 244 | case 0x00c: |
va009039 |
1:913dfd59e25a | 245 | d = 0x01; |
va009039 |
1:913dfd59e25a | 246 | V6M_INFO("P: LPC_SYSCON->SYSPLLSTAT >> %08x", d); |
va009039 |
1:913dfd59e25a | 247 | break; |
va009039 |
1:913dfd59e25a | 248 | case 0x044: |
va009039 |
1:913dfd59e25a | 249 | d = 0x01; |
va009039 |
1:913dfd59e25a | 250 | V6M_INFO("P: LPC_SYSCON->SYSPLLCLKUEN >> %08x", d); |
va009039 |
1:913dfd59e25a | 251 | break; |
va009039 |
1:913dfd59e25a | 252 | case 0x074: |
va009039 |
1:913dfd59e25a | 253 | d = 0x01; |
va009039 |
1:913dfd59e25a | 254 | V6M_INFO("P: LPC_SYSCON->MAINCLKUEN >> %08x", d); |
va009039 |
1:913dfd59e25a | 255 | break; |
va009039 |
1:913dfd59e25a | 256 | case 0x080: |
va009039 |
1:913dfd59e25a | 257 | V6M_INFO("P: LPC_SYSCON->SYSAHBCLKCTRL >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 258 | break; |
va009039 |
1:913dfd59e25a | 259 | case 0x238: |
va009039 |
1:913dfd59e25a | 260 | V6M_INFO("P: LPC_SYSCON->PDRUNCFG >> %08x", d); |
va009039 |
1:913dfd59e25a | 261 | break; |
va009039 |
1:913dfd59e25a | 262 | default: |
va009039 |
1:913dfd59e25a | 263 | V6M_WARN("P: LPC_SYSCON %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 264 | break; |
va009039 |
1:913dfd59e25a | 265 | } |
va009039 |
1:913dfd59e25a | 266 | return d; |
va009039 |
1:913dfd59e25a | 267 | } |
va009039 |
1:913dfd59e25a | 268 | |
va009039 |
1:913dfd59e25a | 269 | EMU81x_SWM::EMU81x_SWM() { |
va009039 |
1:913dfd59e25a | 270 | memset(pinassign, 0xff, sizeof(pinassign)); |
va009039 |
1:913dfd59e25a | 271 | pinenable0 = 0x1b3; |
va009039 |
1:913dfd59e25a | 272 | } |
va009039 |
1:913dfd59e25a | 273 | |
va009039 |
1:913dfd59e25a | 274 | void EMU81x_SWM::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 275 | int n = (a&0xff) / 4; |
va009039 |
1:913dfd59e25a | 276 | switch(a&0xfff) { |
va009039 |
1:913dfd59e25a | 277 | case 0x00: case 0x04: case 0x08: case 0x0c: case 0x10: case 0x14: case 0x1c: case 0x20: |
va009039 |
1:913dfd59e25a | 278 | pinassign[n] = d; |
va009039 |
1:913dfd59e25a | 279 | V6M_INFO("P: LPC_SWM->PINASSIGN%d << %08x", n, d); |
va009039 |
1:913dfd59e25a | 280 | break; |
va009039 |
1:913dfd59e25a | 281 | case 0x1c0: |
va009039 |
1:913dfd59e25a | 282 | pinenable0 = d; |
va009039 |
1:913dfd59e25a | 283 | V6M_INFO("P: LPC_SWM->PINENABLE0 << %08x", d); |
va009039 |
1:913dfd59e25a | 284 | break; |
va009039 |
1:913dfd59e25a | 285 | default: |
va009039 |
1:913dfd59e25a | 286 | V6M_INFO("P: LPC_SWM %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 287 | break; |
va009039 |
1:913dfd59e25a | 288 | } |
va009039 |
1:913dfd59e25a | 289 | } |
va009039 |
1:913dfd59e25a | 290 | |
va009039 |
1:913dfd59e25a | 291 | uint32_t EMU81x_SWM::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 292 | int n = (a&0xff) / 4; |
va009039 |
1:913dfd59e25a | 293 | uint32_t d = 0x00; |
va009039 |
1:913dfd59e25a | 294 | switch(a&0xfff) { |
va009039 |
1:913dfd59e25a | 295 | case 0x00: case 0x04: case 0x08: case 0x0c: case 0x10: case 0x14: case 0x1c: case 0x20: |
va009039 |
1:913dfd59e25a | 296 | d = pinassign[n]; |
va009039 |
1:913dfd59e25a | 297 | V6M_INFO("P: LPC_SWM->PINASSIGN%d >> %08x", n, d); |
va009039 |
1:913dfd59e25a | 298 | break; |
va009039 |
1:913dfd59e25a | 299 | case 0x1c0: |
va009039 |
1:913dfd59e25a | 300 | d = pinenable0; |
va009039 |
1:913dfd59e25a | 301 | V6M_INFO("P: LPC_SWM->PINENABLE0 >> %08x", d); |
va009039 |
1:913dfd59e25a | 302 | break; |
va009039 |
1:913dfd59e25a | 303 | default: |
va009039 |
1:913dfd59e25a | 304 | V6M_INFO("P: LPC_SWM %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 305 | break; |
va009039 |
1:913dfd59e25a | 306 | } |
va009039 |
1:913dfd59e25a | 307 | return d; |
va009039 |
1:913dfd59e25a | 308 | } |
va009039 |
1:913dfd59e25a | 309 | |
va009039 |
1:913dfd59e25a | 310 | EMU81x_GPIO::EMU81x_GPIO(EMU81x& mcu_):mcu(mcu_) { |
va009039 |
1:913dfd59e25a | 311 | dir0 = 0; |
va009039 |
1:913dfd59e25a | 312 | data0 = 0; |
va009039 |
1:913dfd59e25a | 313 | } |
va009039 |
1:913dfd59e25a | 314 | |
va009039 |
1:913dfd59e25a | 315 | void EMU81x_GPIO::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 316 | V6M_ASSERT((a&0xffff0000) == 0xa0000000); |
va009039 |
1:913dfd59e25a | 317 | switch(a&0xffff) { |
va009039 |
1:913dfd59e25a | 318 | case 0x2000: |
va009039 |
1:913dfd59e25a | 319 | dir0 = d; |
va009039 |
1:913dfd59e25a | 320 | V6M_INFO("P: LPC_GPIO_PORT->DIR0 << %08x", d); |
va009039 |
1:913dfd59e25a | 321 | break; |
va009039 |
1:913dfd59e25a | 322 | case 0x2200: |
va009039 |
1:913dfd59e25a | 323 | data0 |= d; |
va009039 |
1:913dfd59e25a | 324 | for(int pin = 0; pin <24; pin++) { |
va009039 |
1:913dfd59e25a | 325 | if (d & (1UL<<pin)) { |
va009039 |
1:913dfd59e25a | 326 | mcu.DigitalWrite_Callback(0, pin, 1); |
va009039 |
1:913dfd59e25a | 327 | } |
va009039 |
1:913dfd59e25a | 328 | } |
va009039 |
1:913dfd59e25a | 329 | V6M_INFO("P: LPC_GPIO_PORT->SET0 << %08x", d); |
va009039 |
1:913dfd59e25a | 330 | break; |
va009039 |
1:913dfd59e25a | 331 | case 0x2280: |
va009039 |
1:913dfd59e25a | 332 | data0 &= (~d)&0xffffffff; |
va009039 |
1:913dfd59e25a | 333 | for(int pin = 0; pin <24; pin++) { |
va009039 |
1:913dfd59e25a | 334 | if (d & (1UL<<pin)) { |
va009039 |
1:913dfd59e25a | 335 | mcu.DigitalWrite_Callback(0, pin, 0); |
va009039 |
1:913dfd59e25a | 336 | } |
va009039 |
1:913dfd59e25a | 337 | } |
va009039 |
1:913dfd59e25a | 338 | V6M_INFO("P: LPC_GPIO_PORT->CLR0 << %08x", d); |
va009039 |
1:913dfd59e25a | 339 | break; |
va009039 |
1:913dfd59e25a | 340 | default: |
va009039 |
1:913dfd59e25a | 341 | V6M_WARN("P: LPC_GPIO_PORT %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 342 | break; |
va009039 |
1:913dfd59e25a | 343 | } |
va009039 |
1:913dfd59e25a | 344 | } |
va009039 |
1:913dfd59e25a | 345 | |
va009039 |
1:913dfd59e25a | 346 | uint32_t EMU81x_GPIO::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 347 | V6M_ASSERT((a&0xffff0000) == 0xa0000000); |
va009039 |
1:913dfd59e25a | 348 | uint32_t d = 0x00000000; |
va009039 |
1:913dfd59e25a | 349 | switch(a&0xffff) { |
va009039 |
1:913dfd59e25a | 350 | case 0x2000: |
va009039 |
1:913dfd59e25a | 351 | d = dir0; |
va009039 |
1:913dfd59e25a | 352 | V6M_INFO("P: LPC_GPIO_PORT->DIR0 >> %08x", d); |
va009039 |
1:913dfd59e25a | 353 | break; |
va009039 |
1:913dfd59e25a | 354 | case 0x2100: |
va009039 |
1:913dfd59e25a | 355 | d = data0; |
va009039 |
1:913dfd59e25a | 356 | V6M_INFO("P: LPC_GPIO_PORT->PIN0 >> %08x", d); |
va009039 |
1:913dfd59e25a | 357 | break; |
va009039 |
1:913dfd59e25a | 358 | default: |
va009039 |
1:913dfd59e25a | 359 | V6M_WARN("P: LPC_GPIO_PORT %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 360 | break; |
va009039 |
1:913dfd59e25a | 361 | } |
va009039 |
1:913dfd59e25a | 362 | return d; |
va009039 |
1:913dfd59e25a | 363 | } |
va009039 |
1:913dfd59e25a | 364 | |
va009039 |
1:913dfd59e25a | 365 | EMU81x_I2C::EMU81x_I2C(EMU81x& mcu_):mcu(mcu_) { |
va009039 |
1:913dfd59e25a | 366 | cfg = 0x00; |
va009039 |
1:913dfd59e25a | 367 | mststate = 0; |
va009039 |
1:913dfd59e25a | 368 | } |
va009039 |
1:913dfd59e25a | 369 | |
va009039 |
1:913dfd59e25a | 370 | void EMU81x_I2C::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 371 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 372 | case 0x00: |
va009039 |
1:913dfd59e25a | 373 | cfg = d; |
va009039 |
1:913dfd59e25a | 374 | V6M_INFO("P: LPC_I2C->CFG << %08x", d); |
va009039 |
1:913dfd59e25a | 375 | break; |
va009039 |
1:913dfd59e25a | 376 | case 0x0c: |
va009039 |
1:913dfd59e25a | 377 | V6M_INFO("P: LPC_I2C->INTENCLR << %08x", d); |
va009039 |
1:913dfd59e25a | 378 | break; |
va009039 |
1:913dfd59e25a | 379 | case 0x14: |
va009039 |
1:913dfd59e25a | 380 | V6M_INFO("P: LPC_I2C->DIV << %08x", d); |
va009039 |
1:913dfd59e25a | 381 | break; |
va009039 |
1:913dfd59e25a | 382 | case 0x20: |
va009039 |
1:913dfd59e25a | 383 | if (d & 0x02) { // master start |
va009039 |
1:913dfd59e25a | 384 | i2c_addr = mstdat; |
va009039 |
1:913dfd59e25a | 385 | if (i2c_addr & 0x01) { |
va009039 |
1:913dfd59e25a | 386 | i2c_size = mcu.I2CRead_Callback(i2c_addr, i2c_data, sizeof(i2c_data)); |
va009039 |
1:913dfd59e25a | 387 | mststate = 1; // receive ready |
va009039 |
1:913dfd59e25a | 388 | i2c_pos = 0; |
va009039 |
1:913dfd59e25a | 389 | } else { |
va009039 |
1:913dfd59e25a | 390 | i2c_pos = 0; |
va009039 |
1:913dfd59e25a | 391 | mststate = 2; // transmit ready |
va009039 |
1:913dfd59e25a | 392 | } |
va009039 |
1:913dfd59e25a | 393 | } else if (d & 0x04) { // master stop |
va009039 |
1:913dfd59e25a | 394 | if (i2c_addr & 0x01) { |
va009039 |
1:913dfd59e25a | 395 | mststate = 0; // idle |
va009039 |
1:913dfd59e25a | 396 | } else { |
va009039 |
1:913dfd59e25a | 397 | mcu.I2CWrite_Callback(i2c_addr, i2c_data, i2c_pos); |
va009039 |
1:913dfd59e25a | 398 | mststate = 0; |
va009039 |
1:913dfd59e25a | 399 | } |
va009039 |
1:913dfd59e25a | 400 | } else if (d & 0x01) { // master continue |
va009039 |
1:913dfd59e25a | 401 | if (i2c_pos < sizeof(i2c_data)) { |
va009039 |
1:913dfd59e25a | 402 | i2c_data[i2c_pos++] = mstdat; |
va009039 |
1:913dfd59e25a | 403 | } |
va009039 |
1:913dfd59e25a | 404 | mststate = 2; // transmit ready |
va009039 |
1:913dfd59e25a | 405 | } else { |
va009039 |
1:913dfd59e25a | 406 | V6M_ERROR("MSTCTL=%02x", d); |
va009039 |
1:913dfd59e25a | 407 | } |
va009039 |
1:913dfd59e25a | 408 | V6M_INFO("P: LPC_I2C->MSTCTL << %08x", d); |
va009039 |
1:913dfd59e25a | 409 | break; |
va009039 |
1:913dfd59e25a | 410 | case 0x24: |
va009039 |
1:913dfd59e25a | 411 | V6M_INFO("P: LPC_I2C->MSTTIME << %08x", d); |
va009039 |
1:913dfd59e25a | 412 | break; |
va009039 |
1:913dfd59e25a | 413 | case 0x28: |
va009039 |
1:913dfd59e25a | 414 | mstdat = d & 0xff; |
va009039 |
1:913dfd59e25a | 415 | V6M_INFO("P: LPC_I2C->MSTDAT << %08x", d); |
va009039 |
1:913dfd59e25a | 416 | break; |
va009039 |
1:913dfd59e25a | 417 | default: |
va009039 |
1:913dfd59e25a | 418 | V6M_WARN("P: LPC_I2C %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 419 | break; |
va009039 |
1:913dfd59e25a | 420 | } |
va009039 |
1:913dfd59e25a | 421 | } |
va009039 |
1:913dfd59e25a | 422 | |
va009039 |
1:913dfd59e25a | 423 | uint32_t EMU81x_I2C::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 424 | uint32_t d = 0x00000000; |
va009039 |
1:913dfd59e25a | 425 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 426 | case 0x00: |
va009039 |
1:913dfd59e25a | 427 | d = cfg; |
va009039 |
1:913dfd59e25a | 428 | V6M_INFO("P: LPC_I2C->CFG >> %08x", d); |
va009039 |
1:913dfd59e25a | 429 | break; |
va009039 |
1:913dfd59e25a | 430 | case 0x04: |
va009039 |
1:913dfd59e25a | 431 | d = 0x801|mststate<<1; |
va009039 |
1:913dfd59e25a | 432 | V6M_INFO("P: LPC_I2C->STAT >> %08x", d); |
va009039 |
1:913dfd59e25a | 433 | break; |
va009039 |
1:913dfd59e25a | 434 | case 0x28: |
va009039 |
1:913dfd59e25a | 435 | if (i2c_pos < i2c_size) { |
va009039 |
1:913dfd59e25a | 436 | d = i2c_data[i2c_pos++]; |
va009039 |
1:913dfd59e25a | 437 | } |
va009039 |
1:913dfd59e25a | 438 | V6M_INFO("P: LPC_I2C->MSTDAT >> %08x", d); |
va009039 |
1:913dfd59e25a | 439 | break; |
va009039 |
1:913dfd59e25a | 440 | default: |
va009039 |
1:913dfd59e25a | 441 | V6M_INFO("P: LPC_I2C %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 442 | break; |
va009039 |
1:913dfd59e25a | 443 | } |
va009039 |
1:913dfd59e25a | 444 | return d; |
va009039 |
1:913dfd59e25a | 445 | } |
va009039 |
1:913dfd59e25a | 446 | |
va009039 |
1:913dfd59e25a | 447 | EMU81x_SPI::EMU81x_SPI(EMU81x& mcu_, int ch_):mcu(mcu_),ch(ch_) { |
va009039 |
1:913dfd59e25a | 448 | } |
va009039 |
1:913dfd59e25a | 449 | |
va009039 |
1:913dfd59e25a | 450 | void EMU81x_SPI::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 451 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 452 | case 0x00: |
va009039 |
1:913dfd59e25a | 453 | V6M_INFO("P: LPC_SPI%d->CFG << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 454 | break; |
va009039 |
1:913dfd59e25a | 455 | case 0x04: |
va009039 |
1:913dfd59e25a | 456 | V6M_INFO("P: LPC_SPI%d->DLY << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 457 | break; |
va009039 |
1:913dfd59e25a | 458 | case 0x10: |
va009039 |
1:913dfd59e25a | 459 | V6M_INFO("P: LPC_SPI%d->INTENCLR << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 460 | break; |
va009039 |
1:913dfd59e25a | 461 | case 0x18: |
va009039 |
1:913dfd59e25a | 462 | V6M_INFO("P: LPC_SPI%d->TXDATCTL << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 463 | break; |
va009039 |
1:913dfd59e25a | 464 | case 0x1c: |
va009039 |
1:913dfd59e25a | 465 | rxdat = mcu.SPIWrite_Callback(ch, d); |
va009039 |
1:913dfd59e25a | 466 | V6M_INFO("P: LPC_SPI%d->TXDAT << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 467 | break; |
va009039 |
1:913dfd59e25a | 468 | case 0x24: |
va009039 |
1:913dfd59e25a | 469 | V6M_INFO("P: LPC_SPI%d->DIV << %08x", ch, d); |
va009039 |
1:913dfd59e25a | 470 | break; |
va009039 |
1:913dfd59e25a | 471 | default: |
va009039 |
1:913dfd59e25a | 472 | V6M_WARN("P: LPC_SPI%d %08x << %08x", ch, a, d); |
va009039 |
1:913dfd59e25a | 473 | break; |
va009039 |
1:913dfd59e25a | 474 | } |
va009039 |
1:913dfd59e25a | 475 | } |
va009039 |
1:913dfd59e25a | 476 | |
va009039 |
1:913dfd59e25a | 477 | uint32_t EMU81x_SPI::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 478 | uint32_t d = 0; |
va009039 |
1:913dfd59e25a | 479 | switch(a&0xff) { |
va009039 |
1:913dfd59e25a | 480 | case 0x00: |
va009039 |
1:913dfd59e25a | 481 | V6M_INFO("P: LPC_SPI%d->CFG >> %08x", ch, d); |
va009039 |
1:913dfd59e25a | 482 | break; |
va009039 |
1:913dfd59e25a | 483 | case 0x08: |
va009039 |
1:913dfd59e25a | 484 | d = 0x03; |
va009039 |
1:913dfd59e25a | 485 | V6M_INFO("P: LPC_SPI%d->STAT >> %08x", ch, d); |
va009039 |
1:913dfd59e25a | 486 | break; |
va009039 |
1:913dfd59e25a | 487 | case 0x14: |
va009039 |
1:913dfd59e25a | 488 | d = rxdat; |
va009039 |
1:913dfd59e25a | 489 | V6M_INFO("P: LPC_SPI%d->RXDAT >> %08x", ch, d); |
va009039 |
1:913dfd59e25a | 490 | break; |
va009039 |
1:913dfd59e25a | 491 | case 0x18: |
va009039 |
1:913dfd59e25a | 492 | V6M_INFO("P: LPC_SPI%d->TXDATCTL >> %08x", ch, d); |
va009039 |
1:913dfd59e25a | 493 | break; |
va009039 |
1:913dfd59e25a | 494 | default: |
va009039 |
1:913dfd59e25a | 495 | V6M_WARN("P: LPC_SPI%d %08x >> %08x", ch, a, d); |
va009039 |
1:913dfd59e25a | 496 | break; |
va009039 |
1:913dfd59e25a | 497 | } |
va009039 |
1:913dfd59e25a | 498 | return d; |
va009039 |
1:913dfd59e25a | 499 | } |
va009039 |
1:913dfd59e25a | 500 | |
va009039 |
1:913dfd59e25a | 501 | EMU81x_SCB::EMU81x_SCB() { |
va009039 |
1:913dfd59e25a | 502 | vtor = 0; |
va009039 |
1:913dfd59e25a | 503 | } |
va009039 |
1:913dfd59e25a | 504 | |
va009039 |
1:913dfd59e25a | 505 | void EMU81x_SCB::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 506 | switch(a&0xfff) { |
va009039 |
1:913dfd59e25a | 507 | case 0xd08: |
va009039 |
1:913dfd59e25a | 508 | vtor = d; |
va009039 |
1:913dfd59e25a | 509 | V6M_INFO("P: SCB->VTOR << %08x", d); |
va009039 |
1:913dfd59e25a | 510 | break; |
va009039 |
1:913dfd59e25a | 511 | default: |
va009039 |
1:913dfd59e25a | 512 | V6M_WARN("P: SCB %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 513 | break; |
va009039 |
1:913dfd59e25a | 514 | } |
va009039 |
1:913dfd59e25a | 515 | } |
va009039 |
1:913dfd59e25a | 516 | |
va009039 |
1:913dfd59e25a | 517 | uint32_t EMU81x_SCB::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 518 | uint32_t d = 0x00; |
va009039 |
1:913dfd59e25a | 519 | switch(a&0xfff) { |
va009039 |
1:913dfd59e25a | 520 | case 0xd08: |
va009039 |
1:913dfd59e25a | 521 | d = vtor; |
va009039 |
1:913dfd59e25a | 522 | V6M_INFO("P: SCB->VTOR >> %08x", d); |
va009039 |
1:913dfd59e25a | 523 | break; |
va009039 |
1:913dfd59e25a | 524 | default: |
va009039 |
1:913dfd59e25a | 525 | V6M_WARN("P: SCB %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 526 | break; |
va009039 |
1:913dfd59e25a | 527 | } |
va009039 |
1:913dfd59e25a | 528 | return d; |
va009039 |
1:913dfd59e25a | 529 | } |
va009039 |
1:913dfd59e25a | 530 | |
va009039 |
1:913dfd59e25a | 531 | void EMU81x_NVIC::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 532 | switch(a) { |
va009039 |
1:913dfd59e25a | 533 | case 0xe000e100: |
va009039 |
1:913dfd59e25a | 534 | iser = d; |
va009039 |
1:913dfd59e25a | 535 | V6M_INFO("P: NVIC->ISER[0] << %08x", d); |
va009039 |
1:913dfd59e25a | 536 | break; |
va009039 |
1:913dfd59e25a | 537 | default: |
va009039 |
1:913dfd59e25a | 538 | V6M_WARN("P: NVIC %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 539 | break; |
va009039 |
1:913dfd59e25a | 540 | } |
va009039 |
1:913dfd59e25a | 541 | } |
va009039 |
1:913dfd59e25a | 542 | |
va009039 |
1:913dfd59e25a | 543 | EMU81x::EMU81x():uart0(*this,0),uart1(*this,1),uart2(*this,2),gpio(*this) |
va009039 |
1:913dfd59e25a | 544 | ,i2c(*this), spi0(*this, 0), spi1(*this, 1) { |
va009039 |
1:913dfd59e25a | 545 | flash = NULL; |
va009039 |
1:913dfd59e25a | 546 | rom = NULL; |
va009039 |
1:913dfd59e25a | 547 | ram = new uint8_t[EMU81x_RAM_SIZE]; |
va009039 |
1:913dfd59e25a | 548 | } |
va009039 |
1:913dfd59e25a | 549 | |
va009039 |
1:913dfd59e25a | 550 | EMU81x::~EMU81x() { |
va009039 |
1:913dfd59e25a | 551 | delete[] ram; |
va009039 |
1:913dfd59e25a | 552 | } |
va009039 |
1:913dfd59e25a | 553 | |
va009039 |
1:913dfd59e25a | 554 | void EMU81x::poke32(uint32_t a, uint32_t d) { |
va009039 |
1:913dfd59e25a | 555 | switch(a>>24) { |
va009039 |
1:913dfd59e25a | 556 | case EMU81x_RAM_BASE>>24: |
va009039 |
1:913dfd59e25a | 557 | V6M_ASSERT(a < (EMU81x_RAM_BASE+EMU81x_RAM_SIZE)); |
va009039 |
1:913dfd59e25a | 558 | V6M_ASSERT(ram); |
va009039 |
1:913dfd59e25a | 559 | ram[a - EMU81x_RAM_BASE + 0] = d>>0; |
va009039 |
1:913dfd59e25a | 560 | ram[a - EMU81x_RAM_BASE + 1] = d>>8; |
va009039 |
1:913dfd59e25a | 561 | ram[a - EMU81x_RAM_BASE + 2] = d>>16; |
va009039 |
1:913dfd59e25a | 562 | ram[a - EMU81x_RAM_BASE + 3] = d>>24; |
va009039 |
1:913dfd59e25a | 563 | V6M_INFO("W: %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 564 | break; |
va009039 |
1:913dfd59e25a | 565 | case EMU81x_APB_BASE>>24: |
va009039 |
1:913dfd59e25a | 566 | switch((a>>12)&0xff) { |
va009039 |
1:913dfd59e25a | 567 | case 0x04: mrt.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 568 | case 0x0c: swm.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 569 | case 0x48: syscon.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 570 | case 0x44: iocon.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 571 | case 0x50: i2c.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 572 | case 0x58: spi0.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 573 | case 0x5c: spi1.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 574 | case 0x64: uart0.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 575 | case 0x68: uart1.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 576 | case 0x6c: uart2.poke32(a, d); break; |
va009039 |
1:913dfd59e25a | 577 | default: |
va009039 |
1:913dfd59e25a | 578 | V6M_WARN("P: %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 579 | break; |
va009039 |
1:913dfd59e25a | 580 | } |
va009039 |
1:913dfd59e25a | 581 | break; |
va009039 |
1:913dfd59e25a | 582 | case EMU81x_AHB_BASE>>24: |
va009039 |
1:913dfd59e25a | 583 | V6M_WARN("P: %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 584 | break; |
va009039 |
1:913dfd59e25a | 585 | case EMU81x_FLASH_BASE>>24: |
va009039 |
1:913dfd59e25a | 586 | case EMU81x_ROM_BASE>>24: |
va009039 |
1:913dfd59e25a | 587 | V6M_ASSERT(0); |
va009039 |
1:913dfd59e25a | 588 | break; |
va009039 |
1:913dfd59e25a | 589 | case EMU81x_GPIO_PORT_BASE>>24: |
va009039 |
1:913dfd59e25a | 590 | gpio.poke32(a, d); |
va009039 |
1:913dfd59e25a | 591 | break; |
va009039 |
1:913dfd59e25a | 592 | case EMU81x_SCS_BASE>>24: |
va009039 |
1:913dfd59e25a | 593 | switch(a&0xffffff) { |
va009039 |
1:913dfd59e25a | 594 | case 0x00e100: |
va009039 |
1:913dfd59e25a | 595 | nvic.poke32(a, d); |
va009039 |
1:913dfd59e25a | 596 | break; |
va009039 |
1:913dfd59e25a | 597 | case 0x00ed08: |
va009039 |
1:913dfd59e25a | 598 | scb.poke32(a, d); |
va009039 |
1:913dfd59e25a | 599 | break; |
va009039 |
1:913dfd59e25a | 600 | default: |
va009039 |
1:913dfd59e25a | 601 | V6M_WARN("P: %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 602 | break; |
va009039 |
1:913dfd59e25a | 603 | } |
va009039 |
1:913dfd59e25a | 604 | break; |
va009039 |
1:913dfd59e25a | 605 | default: |
va009039 |
1:913dfd59e25a | 606 | V6M_WARN("P: %08x << %08x", a, d); |
va009039 |
1:913dfd59e25a | 607 | break; |
va009039 |
1:913dfd59e25a | 608 | } |
va009039 |
1:913dfd59e25a | 609 | } |
va009039 |
1:913dfd59e25a | 610 | |
va009039 |
1:913dfd59e25a | 611 | uint32_t EMU81x::peek32(uint32_t a) { |
va009039 |
1:913dfd59e25a | 612 | uint32_t d = 0x00; |
va009039 |
1:913dfd59e25a | 613 | switch(a>>24) { |
va009039 |
1:913dfd59e25a | 614 | case EMU81x_RAM_BASE>>24: |
va009039 |
1:913dfd59e25a | 615 | V6M_ASSERT(a < (EMU81x_RAM_BASE+EMU81x_RAM_SIZE)); |
va009039 |
1:913dfd59e25a | 616 | d = ram[a - EMU81x_RAM_BASE]; |
va009039 |
1:913dfd59e25a | 617 | d |= ram[a - EMU81x_RAM_BASE + 1]<<8; |
va009039 |
1:913dfd59e25a | 618 | d |= ram[a - EMU81x_RAM_BASE + 2]<<16; |
va009039 |
1:913dfd59e25a | 619 | d |= ram[a - EMU81x_RAM_BASE + 3]<<24; |
va009039 |
1:913dfd59e25a | 620 | V6M_INFO("R: %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 621 | break; |
va009039 |
1:913dfd59e25a | 622 | case EMU81x_FLASH_BASE>>24: |
va009039 |
1:913dfd59e25a | 623 | V6M_ASSERT(a < (EMU81x_FLASH_BASE+EMU81x_FLASH_SIZE)); |
va009039 |
1:913dfd59e25a | 624 | V6M_ASSERT(flash); |
va009039 |
1:913dfd59e25a | 625 | d = flash[a - EMU81x_FLASH_BASE]; |
va009039 |
1:913dfd59e25a | 626 | d |= flash[a - EMU81x_FLASH_BASE + 1]<<8; |
va009039 |
1:913dfd59e25a | 627 | d |= flash[a - EMU81x_FLASH_BASE + 2]<<16; |
va009039 |
1:913dfd59e25a | 628 | d |= flash[a - EMU81x_FLASH_BASE + 3]<<24; |
va009039 |
1:913dfd59e25a | 629 | break; |
va009039 |
1:913dfd59e25a | 630 | case EMU81x_ROM_BASE>>24: |
va009039 |
1:913dfd59e25a | 631 | V6M_ASSERT(a < (EMU81x_ROM_BASE+EMU81x_ROM_SIZE)); |
va009039 |
1:913dfd59e25a | 632 | V6M_ASSERT(rom); |
va009039 |
1:913dfd59e25a | 633 | d = rom[a - EMU81x_ROM_BASE]; |
va009039 |
1:913dfd59e25a | 634 | d |= rom[a - EMU81x_ROM_BASE + 1]<<8; |
va009039 |
1:913dfd59e25a | 635 | d |= rom[a - EMU81x_ROM_BASE + 2]<<16; |
va009039 |
1:913dfd59e25a | 636 | d |= rom[a - EMU81x_ROM_BASE + 3]<<24; |
va009039 |
1:913dfd59e25a | 637 | break; |
va009039 |
1:913dfd59e25a | 638 | case EMU81x_APB_BASE>>24: |
va009039 |
1:913dfd59e25a | 639 | switch((a>>12)&0xff) { |
va009039 |
1:913dfd59e25a | 640 | case 0x04: d = mrt.peek32(a); break; |
va009039 |
1:913dfd59e25a | 641 | case 0x0c: d = swm.peek32(a); break; |
va009039 |
1:913dfd59e25a | 642 | case 0x44: d = iocon.peek32(a); break; |
va009039 |
1:913dfd59e25a | 643 | case 0x48: d = syscon.peek32(a); break; |
va009039 |
1:913dfd59e25a | 644 | case 0x50: d = i2c.peek32(a); break; |
va009039 |
1:913dfd59e25a | 645 | case 0x58: d = spi0.peek32(a); break; |
va009039 |
1:913dfd59e25a | 646 | case 0x5c: d = spi1.peek32(a); break; |
va009039 |
1:913dfd59e25a | 647 | case 0x64: d = uart0.peek32(a); break; |
va009039 |
1:913dfd59e25a | 648 | case 0x68: d = uart1.peek32(a); break; |
va009039 |
1:913dfd59e25a | 649 | case 0x6c: d = uart2.peek32(a); break; |
va009039 |
1:913dfd59e25a | 650 | default: |
va009039 |
1:913dfd59e25a | 651 | V6M_WARN("P: %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 652 | break; |
va009039 |
1:913dfd59e25a | 653 | } |
va009039 |
1:913dfd59e25a | 654 | break; |
va009039 |
1:913dfd59e25a | 655 | case EMU81x_GPIO_PORT_BASE>>24: |
va009039 |
1:913dfd59e25a | 656 | d = gpio.peek32(a); |
va009039 |
1:913dfd59e25a | 657 | break; |
va009039 |
1:913dfd59e25a | 658 | case 0xe0: |
va009039 |
1:913dfd59e25a | 659 | switch(a&0xffffff) { |
va009039 |
1:913dfd59e25a | 660 | case 0x00ed08: |
va009039 |
1:913dfd59e25a | 661 | d = scb.peek32(a); |
va009039 |
1:913dfd59e25a | 662 | break; |
va009039 |
1:913dfd59e25a | 663 | default: |
va009039 |
1:913dfd59e25a | 664 | V6M_WARN("P: %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 665 | break; |
va009039 |
1:913dfd59e25a | 666 | } |
va009039 |
1:913dfd59e25a | 667 | break; |
va009039 |
1:913dfd59e25a | 668 | default: |
va009039 |
1:913dfd59e25a | 669 | V6M_WARN("P: %08x >> %08x", a, d); |
va009039 |
1:913dfd59e25a | 670 | break; |
va009039 |
1:913dfd59e25a | 671 | } |
va009039 |
1:913dfd59e25a | 672 | return d; |
va009039 |
1:913dfd59e25a | 673 | } |
va009039 |
1:913dfd59e25a | 674 | |
va009039 |
1:913dfd59e25a | 675 | void EMU81x::poke8(uint32_t a, uint8_t d) { |
va009039 |
1:913dfd59e25a | 676 | switch(a>>24) { |
va009039 |
1:913dfd59e25a | 677 | case EMU81x_RAM_BASE>>24: |
va009039 |
1:913dfd59e25a | 678 | V6M_ASSERT(a < (EMU81x_RAM_BASE+EMU81x_RAM_SIZE)); |
va009039 |
1:913dfd59e25a | 679 | V6M_ASSERT(ram); |
va009039 |
1:913dfd59e25a | 680 | ram[a - EMU81x_RAM_BASE] = d; |
va009039 |
1:913dfd59e25a | 681 | V6M_INFO("W: %08x << %02x", a, d); |
va009039 |
1:913dfd59e25a | 682 | break; |
va009039 |
1:913dfd59e25a | 683 | default: |
va009039 |
1:913dfd59e25a | 684 | V6M_ASSERT(0); |
va009039 |
1:913dfd59e25a | 685 | break; |
va009039 |
1:913dfd59e25a | 686 | } |
va009039 |
1:913dfd59e25a | 687 | } |
va009039 |
1:913dfd59e25a | 688 | |
va009039 |
1:913dfd59e25a | 689 | uint8_t EMU81x::peek8(uint32_t a) { |
va009039 |
1:913dfd59e25a | 690 | uint8_t d = 0x00; |
va009039 |
1:913dfd59e25a | 691 | switch(a>>24) { |
va009039 |
1:913dfd59e25a | 692 | case EMU81x_RAM_BASE>>24: |
va009039 |
1:913dfd59e25a | 693 | V6M_ASSERT(a < (EMU81x_RAM_BASE+EMU81x_RAM_SIZE)); |
va009039 |
1:913dfd59e25a | 694 | d = ram[a - EMU81x_RAM_BASE]; |
va009039 |
1:913dfd59e25a | 695 | V6M_INFO("R: %08x >> %02x", a, d); |
va009039 |
1:913dfd59e25a | 696 | break; |
va009039 |
1:913dfd59e25a | 697 | case EMU81x_FLASH_BASE>>24: |
va009039 |
1:913dfd59e25a | 698 | V6M_ASSERT(a < (EMU81x_FLASH_BASE+EMU81x_FLASH_SIZE)); |
va009039 |
1:913dfd59e25a | 699 | d = flash[a - EMU81x_FLASH_BASE]; |
va009039 |
1:913dfd59e25a | 700 | break; |
va009039 |
1:913dfd59e25a | 701 | case EMU81x_ROM_BASE>>24: |
va009039 |
1:913dfd59e25a | 702 | V6M_ASSERT(a < (EMU81x_ROM_BASE+EMU81x_ROM_SIZE)); |
va009039 |
1:913dfd59e25a | 703 | d = rom[a - EMU81x_ROM_BASE]; |
va009039 |
1:913dfd59e25a | 704 | break; |
va009039 |
1:913dfd59e25a | 705 | default: |
va009039 |
1:913dfd59e25a | 706 | V6M_ASSERT(0); |
va009039 |
1:913dfd59e25a | 707 | break; |
va009039 |
1:913dfd59e25a | 708 | } |
va009039 |
1:913dfd59e25a | 709 | return d; |
va009039 |
1:913dfd59e25a | 710 | } |
va009039 |
1:913dfd59e25a | 711 | |
va009039 |
1:913dfd59e25a | 712 | void EMU81x::clock_in(uint32_t n) { |
va009039 |
1:913dfd59e25a | 713 | mrt.clock_in(n); |
va009039 |
1:913dfd59e25a | 714 | } |
va009039 |
1:913dfd59e25a | 715 | |
va009039 |
1:913dfd59e25a | 716 | void EMU81x::trace() { |
va009039 |
1:913dfd59e25a | 717 | V6M_INFO("S: r0=%08x r1=%08x r2=%08x r3=%08x r4=%08x r5=%08x r6=%08x r7=%08x", R[0],R[1],R[2],R[3],R[4],R[5],R[6],R[7]); |
va009039 |
1:913dfd59e25a | 718 | V6M_INFO("S: r8=%08x r9=%08x r10=%08x r11=%08x r12=%08x sp=%08x lr=%08x pc=%08x", R[8],R[9],R[10],R[11],R[12],R[13],R[14],R[15]); |
va009039 |
1:913dfd59e25a | 719 | V6M_INFO("S: xPSR=%08x N=%d Z=%d C=%d V=%d", R[16], N(), Z(), C(), V()); |
va009039 |
1:913dfd59e25a | 720 | V6M_DEBUG("S: cycle=%d code=%02x code2nd=%02x im=%08x d=%d n=%d m=%d", cycle, code, code2nd, R[17], GetRegIndex(Rd), GetRegIndex(Rn), GetRegIndex(Rm)); |
va009039 |
1:913dfd59e25a | 721 | |
va009039 |
1:913dfd59e25a | 722 | } |
va009039 |
1:913dfd59e25a | 723 |