Norimasa Okamoto / Mbed 2 deprecated emu1114

mbed LPC1114 emulator pre-alpha version

Dependencies:   BaseV6M mbed F12RFileSystem F32RFileSystem ROMSLOT SDStorage

Fork of emu812 by Norimasa Okamoto

480
TOYOSHIKI TINY BASIC mbed Edition TTB_mbed_LPC1114.bin save as "LPC1114.IMG" .

EMU111x.cpp@2:b8b4f07d4691, 2015-08-11 (annotated)

Committer:
va009039
Date:
Tue Aug 11 06:49:07 2015 +0900
Revision:
2:b8b4f07d4691
Child:
3:5df725af50e0
add files.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 2:b8b4f07d4691 1 // EMU111x.cpp 2015/8/8
va009039 2:b8b4f07d4691 2 #include "mbed.h"
va009039 2:b8b4f07d4691 3 #include "EMU111x.h"
va009039 2:b8b4f07d4691 4 #define V6M_LOG_LEVEL 2
va009039 2:b8b4f07d4691 5 #include "v6m_log.h"
va009039 2:b8b4f07d4691 6
va009039 2:b8b4f07d4691 7 const int EMU111x_RAM_SIZE = (1024*4);
va009039 2:b8b4f07d4691 8 const int EMU111x_FLASH_SIZE = (1024*32);
va009039 2:b8b4f07d4691 9 const int EMU111x_ROM_SIZE = (1024*16);
va009039 2:b8b4f07d4691 10
va009039 2:b8b4f07d4691 11 const uint32_t EMU111x_FLASH_BASE = 0x00000000;
va009039 2:b8b4f07d4691 12 const uint32_t EMU111x_RAM_BASE = 0x10000000;
va009039 2:b8b4f07d4691 13 const uint32_t EMU111x_ROM_BASE = 0x1fff0000;
va009039 2:b8b4f07d4691 14 const uint32_t EMU111x_APB_BASE = 0x40000000;
va009039 2:b8b4f07d4691 15 const uint32_t EMU111x_AHB_BASE = 0x50000000;
va009039 2:b8b4f07d4691 16 const uint32_t EMU111x_SCS_BASE = 0xe000e000;
va009039 2:b8b4f07d4691 17
va009039 2:b8b4f07d4691 18 EMU111x_SYSCON::EMU111x_SYSCON() {
va009039 2:b8b4f07d4691 19 }
va009039 2:b8b4f07d4691 20
va009039 2:b8b4f07d4691 21 void EMU111x_SYSCON::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 22 switch(a&0xfff) {
va009039 2:b8b4f07d4691 23 case 0x000:
va009039 2:b8b4f07d4691 24 V6M_INFO("P: LPC_SYSCON->SYSMEMREMAP << %08x", d);
va009039 2:b8b4f07d4691 25 break;
va009039 2:b8b4f07d4691 26 case 0x004:
va009039 2:b8b4f07d4691 27 V6M_INFO("P: LPC_SYSCON->PRESETCTRL << %08x", d);
va009039 2:b8b4f07d4691 28 break;
va009039 2:b8b4f07d4691 29 case 0x008:
va009039 2:b8b4f07d4691 30 V6M_INFO("P: LPC_SYSCON->SYSPLLCTRL << %08x", d);
va009039 2:b8b4f07d4691 31 break;
va009039 2:b8b4f07d4691 32 case 0x040:
va009039 2:b8b4f07d4691 33 V6M_INFO("P: LPC_SYSCON->SYSPLLCLKSEL << %08x", d);
va009039 2:b8b4f07d4691 34 break;
va009039 2:b8b4f07d4691 35 case 0x044:
va009039 2:b8b4f07d4691 36 V6M_INFO("P: LPC_SYSCON->SYSPLLCLKUEN << %08x", d);
va009039 2:b8b4f07d4691 37 break;
va009039 2:b8b4f07d4691 38 case 0x070:
va009039 2:b8b4f07d4691 39 V6M_INFO("P: LPC_SYSCON->MAINCLKSEL << %08x", d);
va009039 2:b8b4f07d4691 40 break;
va009039 2:b8b4f07d4691 41 case 0x074:
va009039 2:b8b4f07d4691 42 V6M_INFO("P: LPC_SYSCON->MAINCLKUEN << %08x", d);
va009039 2:b8b4f07d4691 43 break;
va009039 2:b8b4f07d4691 44 case 0x078:
va009039 2:b8b4f07d4691 45 V6M_INFO("P: LPC_SYSCON->SYSAHBCLKDIV << %08x", d);
va009039 2:b8b4f07d4691 46 break;
va009039 2:b8b4f07d4691 47 case 0x080:
va009039 2:b8b4f07d4691 48 V6M_INFO("P: LPC_SYSCON->SYSAHBCLKCTRL << %08x", d);
va009039 2:b8b4f07d4691 49 break;
va009039 2:b8b4f07d4691 50 case 0x094:
va009039 2:b8b4f07d4691 51 V6M_INFO("P: LPC_SYSCON->SSP0CLKDIV << %08x", d);
va009039 2:b8b4f07d4691 52 break;
va009039 2:b8b4f07d4691 53 case 0x098:
va009039 2:b8b4f07d4691 54 V6M_INFO("P: LPC_SYSCON->UARTCLKDIV << %08x", d);
va009039 2:b8b4f07d4691 55 break;
va009039 2:b8b4f07d4691 56 case 0x238:
va009039 2:b8b4f07d4691 57 V6M_INFO("P: LPC_SYSCON->PDRUNCFG << %08x", d);
va009039 2:b8b4f07d4691 58 break;
va009039 2:b8b4f07d4691 59 default:
va009039 2:b8b4f07d4691 60 V6M_WARN("P: LPC_SYSCON %08x << %08x", a, d);
va009039 2:b8b4f07d4691 61 break;
va009039 2:b8b4f07d4691 62 }
va009039 2:b8b4f07d4691 63 }
va009039 2:b8b4f07d4691 64
va009039 2:b8b4f07d4691 65 uint32_t EMU111x_SYSCON::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 66 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 67 switch(a&0xfff) {
va009039 2:b8b4f07d4691 68 case 0x000:
va009039 2:b8b4f07d4691 69 V6M_INFO("P: LPC_SYSCON->SYSMEMREMAP >> %08x", a, d);
va009039 2:b8b4f07d4691 70 break;
va009039 2:b8b4f07d4691 71 case 0x004:
va009039 2:b8b4f07d4691 72 V6M_INFO("P: LPC_SYSCON->PRESETCTRL >> %08x", a, d);
va009039 2:b8b4f07d4691 73 break;
va009039 2:b8b4f07d4691 74 case 0x00c:
va009039 2:b8b4f07d4691 75 d = 0x01;
va009039 2:b8b4f07d4691 76 V6M_INFO("P: LPC_SYSCON->SYSPLLSTAT >> %08x", a, d);
va009039 2:b8b4f07d4691 77 break;
va009039 2:b8b4f07d4691 78 case 0x044:
va009039 2:b8b4f07d4691 79 d = 0x01;
va009039 2:b8b4f07d4691 80 V6M_INFO("P: LPC_SYSCON->SYSPLLCLKUEN >> %08x", a, d);
va009039 2:b8b4f07d4691 81 break;
va009039 2:b8b4f07d4691 82 case 0x074:
va009039 2:b8b4f07d4691 83 d = 0x01;
va009039 2:b8b4f07d4691 84 V6M_INFO("P: LPC_SYSCON->MAINCLKUEN >> %08x", a, d);
va009039 2:b8b4f07d4691 85 break;
va009039 2:b8b4f07d4691 86 case 0x080:
va009039 2:b8b4f07d4691 87 V6M_INFO("P: LPC_SYSCON->SYSAHBCLKCTRL >> %08x", a, d);
va009039 2:b8b4f07d4691 88 break;
va009039 2:b8b4f07d4691 89 case 0x238:
va009039 2:b8b4f07d4691 90 V6M_INFO("P: LPC_SYSCON->PDRUNCFG >> %08x", d);
va009039 2:b8b4f07d4691 91 break;
va009039 2:b8b4f07d4691 92 default:
va009039 2:b8b4f07d4691 93 V6M_WARN("P: LPC_SYSCON %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 94 break;
va009039 2:b8b4f07d4691 95 }
va009039 2:b8b4f07d4691 96 return d;
va009039 2:b8b4f07d4691 97 }
va009039 2:b8b4f07d4691 98
va009039 2:b8b4f07d4691 99 EMU111x_IOCON::EMU111x_IOCON() {
va009039 2:b8b4f07d4691 100 PIO0_4 = 0xd0;
va009039 2:b8b4f07d4691 101 PIO0_5 = 0xd0;
va009039 2:b8b4f07d4691 102 PIO0_6 = 0xd0;
va009039 2:b8b4f07d4691 103 PIO0_8 = 0xd0;
va009039 2:b8b4f07d4691 104 PIO0_9 = 0xd0;
va009039 2:b8b4f07d4691 105 R_PIO0_11 = 0xd0;
va009039 2:b8b4f07d4691 106 SCK_LOC = 0x00;
va009039 2:b8b4f07d4691 107 }
va009039 2:b8b4f07d4691 108
va009039 2:b8b4f07d4691 109 void EMU111x_IOCON::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 110 switch(a&0xff) {
va009039 2:b8b4f07d4691 111 #define c(V,PIN) case V: PIN = d; V6M_INFO("P: LPC_IOCON->%s << %08x", #PIN, d); break;
va009039 2:b8b4f07d4691 112 c(0x30, PIO0_4);
va009039 2:b8b4f07d4691 113 c(0x34, PIO0_5);
va009039 2:b8b4f07d4691 114 c(0x4c, PIO0_6);
va009039 2:b8b4f07d4691 115 c(0x60, PIO0_8);
va009039 2:b8b4f07d4691 116 c(0x64, PIO0_9);
va009039 2:b8b4f07d4691 117 c(0x74, R_PIO0_11);
va009039 2:b8b4f07d4691 118 c(0xa0, PIO1_5);
va009039 2:b8b4f07d4691 119 c(0xa4, PIO1_6);
va009039 2:b8b4f07d4691 120 c(0xa8, PIO1_7);
va009039 2:b8b4f07d4691 121 c(0xb0, SCK_LOC);
va009039 2:b8b4f07d4691 122 #undef c
va009039 2:b8b4f07d4691 123 default: V6M_WARN("P: LPC_IOCON %08x << %08x", a, d); break;
va009039 2:b8b4f07d4691 124 }
va009039 2:b8b4f07d4691 125 }
va009039 2:b8b4f07d4691 126
va009039 2:b8b4f07d4691 127 uint32_t EMU111x_IOCON::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 128 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 129 switch(a&0xff) {
va009039 2:b8b4f07d4691 130 #define c(V,PIN) case V: d = PIN; V6M_INFO("P: LPC_IOCON->%s >> %08x", #PIN, d); break;
va009039 2:b8b4f07d4691 131 c(0x30, PIO0_4);
va009039 2:b8b4f07d4691 132 c(0x34, PIO0_5);
va009039 2:b8b4f07d4691 133 c(0x4c, PIO0_6);
va009039 2:b8b4f07d4691 134 c(0x60, PIO0_8);
va009039 2:b8b4f07d4691 135 c(0x64, PIO0_9);
va009039 2:b8b4f07d4691 136 c(0x74, R_PIO0_11);
va009039 2:b8b4f07d4691 137 c(0xa0, PIO1_5);
va009039 2:b8b4f07d4691 138 c(0xa4, PIO1_6);
va009039 2:b8b4f07d4691 139 c(0xa8, PIO1_7);
va009039 2:b8b4f07d4691 140 c(0xb0, SCK_LOC);
va009039 2:b8b4f07d4691 141 #undef c
va009039 2:b8b4f07d4691 142 default: V6M_WARN("P: LPC_IOCON %08x >> %08x", a, d); break;
va009039 2:b8b4f07d4691 143 }
va009039 2:b8b4f07d4691 144 return d;
va009039 2:b8b4f07d4691 145 }
va009039 2:b8b4f07d4691 146
va009039 2:b8b4f07d4691 147 EMU111x_GPIO::EMU111x_GPIO(EMU111x& mcu_, int port_):mcu(mcu_),port(port_) {
va009039 2:b8b4f07d4691 148 data = 0x00;
va009039 2:b8b4f07d4691 149 dir = 0x00;
va009039 2:b8b4f07d4691 150 }
va009039 2:b8b4f07d4691 151
va009039 2:b8b4f07d4691 152 void EMU111x_GPIO::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 153 switch(a&0xffff) {
va009039 2:b8b4f07d4691 154 case 0x3ffc:
va009039 2:b8b4f07d4691 155 data = d;
va009039 2:b8b4f07d4691 156 for(int pin = 0; pin < 12; pin++) {
va009039 2:b8b4f07d4691 157 uint32_t mask = 1UL<<pin;
va009039 2:b8b4f07d4691 158 if (dir & mask) { // output
va009039 2:b8b4f07d4691 159 mcu.DigitalWrite_Callback(port, pin, (d&mask) ? 1 : 0);
va009039 2:b8b4f07d4691 160 }
va009039 2:b8b4f07d4691 161 }
va009039 2:b8b4f07d4691 162 V6M_INFO("P: LPC_GPIO%d->DATA %08x << %08x", port, a, d);
va009039 2:b8b4f07d4691 163 break;
va009039 2:b8b4f07d4691 164 case 0x8000:
va009039 2:b8b4f07d4691 165 dir = d;
va009039 2:b8b4f07d4691 166 V6M_INFO("P: LPC_GPIO%d->DIR << %08x", port, d);
va009039 2:b8b4f07d4691 167 break;
va009039 2:b8b4f07d4691 168 default:
va009039 2:b8b4f07d4691 169 V6M_WARN("P: LPC_GPIO%d %08x << %08x", port, a, d);
va009039 2:b8b4f07d4691 170 break;
va009039 2:b8b4f07d4691 171 }
va009039 2:b8b4f07d4691 172 }
va009039 2:b8b4f07d4691 173
va009039 2:b8b4f07d4691 174 static int pinpos(uint32_t data) {
va009039 2:b8b4f07d4691 175 for(int pin = 0; pin < 12; pin++) {
va009039 2:b8b4f07d4691 176 if (data & (1UL<<pin)) {
va009039 2:b8b4f07d4691 177 return pin;
va009039 2:b8b4f07d4691 178 }
va009039 2:b8b4f07d4691 179 }
va009039 2:b8b4f07d4691 180 return 0;
va009039 2:b8b4f07d4691 181 }
va009039 2:b8b4f07d4691 182
va009039 2:b8b4f07d4691 183 uint32_t EMU111x_GPIO::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 184 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 185 uint32_t mask;
va009039 2:b8b4f07d4691 186 int pin;
va009039 2:b8b4f07d4691 187 switch(a&0xffff) {
va009039 2:b8b4f07d4691 188 case 0x0080:
va009039 2:b8b4f07d4691 189 mask = (a>>2)&0xfff;
va009039 2:b8b4f07d4691 190 pin = pinpos(mask);
va009039 2:b8b4f07d4691 191 if (dir & mask) { // output
va009039 2:b8b4f07d4691 192 d = data & mask;
va009039 2:b8b4f07d4691 193 } else { // input
va009039 2:b8b4f07d4691 194 if (mcu.DigitalRead_Callback(port, pin)) {
va009039 2:b8b4f07d4691 195 d = mask;
va009039 2:b8b4f07d4691 196 }
va009039 2:b8b4f07d4691 197 }
va009039 2:b8b4f07d4691 198 V6M_WARN("P: LPC_GPIO%d->MASKED_ACCESS[%03x] >> %08x", port, mask, d);
va009039 2:b8b4f07d4691 199 break;
va009039 2:b8b4f07d4691 200 case 0x3ffc:
va009039 2:b8b4f07d4691 201 d = data;
va009039 2:b8b4f07d4691 202 V6M_INFO("P: LPC_GPIO%d->DATA >> %08x", port, d);
va009039 2:b8b4f07d4691 203 break;
va009039 2:b8b4f07d4691 204 case 0x8000:
va009039 2:b8b4f07d4691 205 d = dir;
va009039 2:b8b4f07d4691 206 V6M_INFO("P: LPC_GPIO%d->DIR >> %08x", port, d);
va009039 2:b8b4f07d4691 207 break;
va009039 2:b8b4f07d4691 208 default:
va009039 2:b8b4f07d4691 209 V6M_WARN("P: LPC_GPIO%d %08x >> %08x", port, a, d);
va009039 2:b8b4f07d4691 210 break;
va009039 2:b8b4f07d4691 211 }
va009039 2:b8b4f07d4691 212 return d;
va009039 2:b8b4f07d4691 213 }
va009039 2:b8b4f07d4691 214
va009039 2:b8b4f07d4691 215 EMU111x_TMR32B::EMU111x_TMR32B(int ch_):ch(ch_) {
va009039 2:b8b4f07d4691 216 V6M_ASSERT(ch == 0 || ch == 1);
va009039 2:b8b4f07d4691 217 tc = 0;
va009039 2:b8b4f07d4691 218 }
va009039 2:b8b4f07d4691 219
va009039 2:b8b4f07d4691 220 void EMU111x_TMR32B::clock_in(uint32_t n) {
va009039 2:b8b4f07d4691 221 V6M_ASSERT(n != 0);
va009039 2:b8b4f07d4691 222 tc += n;
va009039 2:b8b4f07d4691 223 }
va009039 2:b8b4f07d4691 224
va009039 2:b8b4f07d4691 225 void EMU111x_TMR32B::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 226 switch(a&0xff) {
va009039 2:b8b4f07d4691 227 case 0x04:
va009039 2:b8b4f07d4691 228 V6M_INFO("P: LPC_TMR32B->TCR << %08x", d);
va009039 2:b8b4f07d4691 229 break;
va009039 2:b8b4f07d4691 230 case 0x0c:
va009039 2:b8b4f07d4691 231 V6M_INFO("P: LPC_TMR32B->PR << %08x", d);
va009039 2:b8b4f07d4691 232 break;
va009039 2:b8b4f07d4691 233 default:
va009039 2:b8b4f07d4691 234 V6M_WARN("P: LPC_TMR32B %08x << %08x", a, d);
va009039 2:b8b4f07d4691 235 break;
va009039 2:b8b4f07d4691 236 }
va009039 2:b8b4f07d4691 237 }
va009039 2:b8b4f07d4691 238
va009039 2:b8b4f07d4691 239 uint32_t EMU111x_TMR32B::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 240 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 241 switch(a&0xff) {
va009039 2:b8b4f07d4691 242 case 0x08:
va009039 2:b8b4f07d4691 243 d = tc;
va009039 2:b8b4f07d4691 244 V6M_INFO("P: LPC_TMR32B%d->TC >> %u", ch, d);
va009039 2:b8b4f07d4691 245 break;
va009039 2:b8b4f07d4691 246 default:
va009039 2:b8b4f07d4691 247 V6M_WARN("P: LPC_TMR32B%d %08x >> %02x", ch, a, d);
va009039 2:b8b4f07d4691 248 break;
va009039 2:b8b4f07d4691 249 }
va009039 2:b8b4f07d4691 250 return d;
va009039 2:b8b4f07d4691 251 }
va009039 2:b8b4f07d4691 252
va009039 2:b8b4f07d4691 253 EMU111x_UART::EMU111x_UART(EMU111x& mcu_):mcu(mcu_) {
va009039 2:b8b4f07d4691 254 lcr = 0x00;
va009039 2:b8b4f07d4691 255 }
va009039 2:b8b4f07d4691 256
va009039 2:b8b4f07d4691 257 void EMU111x_UART::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 258 switch(a&0xff) {
va009039 2:b8b4f07d4691 259 case 0x00:
va009039 2:b8b4f07d4691 260 mcu.SerialPutc_Callback(0, d);
va009039 2:b8b4f07d4691 261 V6M_INFO("P: LPC_UART->THR << %08x", d);
va009039 2:b8b4f07d4691 262 break;
va009039 2:b8b4f07d4691 263 case 0x04:
va009039 2:b8b4f07d4691 264 V6M_INFO("P: LPC_UART->IER << %08x", d);
va009039 2:b8b4f07d4691 265 break;
va009039 2:b8b4f07d4691 266 case 0x08:
va009039 2:b8b4f07d4691 267 V6M_INFO("P: LPC_UART->FCR << %08x", d);
va009039 2:b8b4f07d4691 268 break;
va009039 2:b8b4f07d4691 269 case 0x0c:
va009039 2:b8b4f07d4691 270 lcr = d;
va009039 2:b8b4f07d4691 271 V6M_INFO("P: LPC_UART->LCR << %08x", d);
va009039 2:b8b4f07d4691 272 break;
va009039 2:b8b4f07d4691 273 case 0x28:
va009039 2:b8b4f07d4691 274 fdr = d;
va009039 2:b8b4f07d4691 275 V6M_INFO("P: LPC_UART->FDR << %08x", d);
va009039 2:b8b4f07d4691 276 break;
va009039 2:b8b4f07d4691 277 default:
va009039 2:b8b4f07d4691 278 V6M_WARN("P: LPC_UART %08x << %08x", a, d);
va009039 2:b8b4f07d4691 279 break;
va009039 2:b8b4f07d4691 280 }
va009039 2:b8b4f07d4691 281 }
va009039 2:b8b4f07d4691 282
va009039 2:b8b4f07d4691 283 uint32_t EMU111x_UART::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 284 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 285 switch(a&0xff) {
va009039 2:b8b4f07d4691 286 case 0x00:
va009039 2:b8b4f07d4691 287 d = mcu.SerialGetc_Callback(0);
va009039 2:b8b4f07d4691 288 V6M_INFO("P: LPC_UART->RBR >> %08x", a, d);
va009039 2:b8b4f07d4691 289 break;
va009039 2:b8b4f07d4691 290 case 0x0c:
va009039 2:b8b4f07d4691 291 d = lcr;
va009039 2:b8b4f07d4691 292 V6M_INFO("P: LPC_UART->LCR >> %08x", a, d);
va009039 2:b8b4f07d4691 293 break;
va009039 2:b8b4f07d4691 294 case 0x14:
va009039 2:b8b4f07d4691 295 d = 0x20;
va009039 2:b8b4f07d4691 296 if (mcu.SerialReadable_Callback(0)) {
va009039 2:b8b4f07d4691 297 d |= 0x01;
va009039 2:b8b4f07d4691 298 }
va009039 2:b8b4f07d4691 299 V6M_INFO("P: LPC_UART->LSR >> %08x", a, d);
va009039 2:b8b4f07d4691 300 break;
va009039 2:b8b4f07d4691 301 default:
va009039 2:b8b4f07d4691 302 V6M_WARN("P: LPC_UART %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 303 break;
va009039 2:b8b4f07d4691 304 }
va009039 2:b8b4f07d4691 305 return d;
va009039 2:b8b4f07d4691 306 }
va009039 2:b8b4f07d4691 307
va009039 2:b8b4f07d4691 308 EMU111x_I2C::EMU111x_I2C(EMU111x& mcu_):mcu(mcu_) {
va009039 2:b8b4f07d4691 309 con = 0;
va009039 2:b8b4f07d4691 310 stat = 0xf8;
va009039 2:b8b4f07d4691 311 }
va009039 2:b8b4f07d4691 312
va009039 2:b8b4f07d4691 313 void EMU111x_I2C::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 314 switch(a&0xff) {
va009039 2:b8b4f07d4691 315 case 0x00: // CONSET
va009039 2:b8b4f07d4691 316 if (d == 0x40) {
va009039 2:b8b4f07d4691 317 con = 0x40;
va009039 2:b8b4f07d4691 318 } else if (d == 0x24) { // start
va009039 2:b8b4f07d4691 319 con = 0x48;
va009039 2:b8b4f07d4691 320 stat = 0x10;
va009039 2:b8b4f07d4691 321 } else if (d == 0x10) { // stop
va009039 2:b8b4f07d4691 322 if ((i2c_addr&0x01) == 0x00) {
va009039 2:b8b4f07d4691 323 mcu.I2CWrite_Callback(i2c_addr, i2c_data, i2c_pos);
va009039 2:b8b4f07d4691 324 }
va009039 2:b8b4f07d4691 325 } else {
va009039 2:b8b4f07d4691 326 V6M_ASSERT(0);
va009039 2:b8b4f07d4691 327 }
va009039 2:b8b4f07d4691 328 V6M_INFO("P: LPC_I2C->CONSET << %08x", d);
va009039 2:b8b4f07d4691 329 break;
va009039 2:b8b4f07d4691 330 case 0x08: // DAT
va009039 2:b8b4f07d4691 331 if (stat == 0x10) { // start
va009039 2:b8b4f07d4691 332 i2c_addr = d & 0xff;
va009039 2:b8b4f07d4691 333 i2c_pos = 0;
va009039 2:b8b4f07d4691 334 if (i2c_addr & 0x01) {
va009039 2:b8b4f07d4691 335 i2c_size = mcu.I2CRead_Callback(i2c_addr, i2c_data, sizeof(i2c_data));
va009039 2:b8b4f07d4691 336 stat = 0x40;
va009039 2:b8b4f07d4691 337 i2c_pos = 0;
va009039 2:b8b4f07d4691 338 } else {
va009039 2:b8b4f07d4691 339 stat = 0x18;
va009039 2:b8b4f07d4691 340 }
va009039 2:b8b4f07d4691 341 } else {
va009039 2:b8b4f07d4691 342 if (i2c_pos < sizeof(i2c_data)) {
va009039 2:b8b4f07d4691 343 i2c_data[i2c_pos++] = d & 0xff;
va009039 2:b8b4f07d4691 344 }
va009039 2:b8b4f07d4691 345 stat = 0x18;
va009039 2:b8b4f07d4691 346 }
va009039 2:b8b4f07d4691 347 V6M_INFO("P: LPC_I2C->DAT << %08x", d);
va009039 2:b8b4f07d4691 348 break;
va009039 2:b8b4f07d4691 349 case 0x10:
va009039 2:b8b4f07d4691 350 V6M_INFO("P: LPC_I2C->SCLH << %08x", d);
va009039 2:b8b4f07d4691 351 break;
va009039 2:b8b4f07d4691 352 case 0x14:
va009039 2:b8b4f07d4691 353 V6M_INFO("P: LPC_I2C->SCLL << %08x", d);
va009039 2:b8b4f07d4691 354 break;
va009039 2:b8b4f07d4691 355 case 0x18:
va009039 2:b8b4f07d4691 356 V6M_INFO("P: LPC_I2C->CONCLR << %08x", d);
va009039 2:b8b4f07d4691 357 break;
va009039 2:b8b4f07d4691 358 default:
va009039 2:b8b4f07d4691 359 V6M_WARN("P: LPC_I2C %08x << %08x", a, d);
va009039 2:b8b4f07d4691 360 break;
va009039 2:b8b4f07d4691 361 }
va009039 2:b8b4f07d4691 362 }
va009039 2:b8b4f07d4691 363
va009039 2:b8b4f07d4691 364 uint32_t EMU111x_I2C::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 365 uint32_t d = 0x00000000;
va009039 2:b8b4f07d4691 366 switch(a&0xff) {
va009039 2:b8b4f07d4691 367 case 0x00:
va009039 2:b8b4f07d4691 368 d = con;
va009039 2:b8b4f07d4691 369 V6M_INFO("P: LPC_I2C->CON >> %08x", d);
va009039 2:b8b4f07d4691 370 break;
va009039 2:b8b4f07d4691 371 case 0x04:
va009039 2:b8b4f07d4691 372 d = stat;
va009039 2:b8b4f07d4691 373 V6M_INFO("P: LPC_I2C->STAT >> %08x", d);
va009039 2:b8b4f07d4691 374 break;
va009039 2:b8b4f07d4691 375 case 0x08:
va009039 2:b8b4f07d4691 376 if (i2c_pos < i2c_size) {
va009039 2:b8b4f07d4691 377 d = i2c_data[i2c_pos++];
va009039 2:b8b4f07d4691 378 }
va009039 2:b8b4f07d4691 379 if (i2c_pos < i2c_size) {
va009039 2:b8b4f07d4691 380 stat = 0x50;
va009039 2:b8b4f07d4691 381 } else {
va009039 2:b8b4f07d4691 382 stat = 0x58;
va009039 2:b8b4f07d4691 383 }
va009039 2:b8b4f07d4691 384 V6M_INFO("P: LPC_I2C->DAT >> %08x", d);
va009039 2:b8b4f07d4691 385 break;
va009039 2:b8b4f07d4691 386 default:
va009039 2:b8b4f07d4691 387 V6M_WARN("P: LPC_I2C %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 388 break;
va009039 2:b8b4f07d4691 389 }
va009039 2:b8b4f07d4691 390 return d;
va009039 2:b8b4f07d4691 391 }
va009039 2:b8b4f07d4691 392
va009039 2:b8b4f07d4691 393 EMU111x_SPI::EMU111x_SPI(EMU111x& mcu_, int ch_):mcu(mcu_),ch(ch_) {
va009039 2:b8b4f07d4691 394 cr0 = 0;
va009039 2:b8b4f07d4691 395 cr1 = 0;
va009039 2:b8b4f07d4691 396 }
va009039 2:b8b4f07d4691 397
va009039 2:b8b4f07d4691 398 void EMU111x_SPI::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 399 switch(a&0xff) {
va009039 2:b8b4f07d4691 400 case 0x00:
va009039 2:b8b4f07d4691 401 cr0 = d;
va009039 2:b8b4f07d4691 402 V6M_INFO("P: LPC_SPI%d->CR0 << %08x", ch, d);
va009039 2:b8b4f07d4691 403 break;
va009039 2:b8b4f07d4691 404 case 0x04:
va009039 2:b8b4f07d4691 405 cr1 = d;
va009039 2:b8b4f07d4691 406 V6M_INFO("P: LPC_SPI%d->CR1 << %08x", ch, d);
va009039 2:b8b4f07d4691 407 break;
va009039 2:b8b4f07d4691 408 case 0x08:
va009039 2:b8b4f07d4691 409 dr = mcu.SPIWrite_Callback(ch, d);
va009039 2:b8b4f07d4691 410 V6M_INFO("P: LPC_SPI%d->DR << %08x", ch, d);
va009039 2:b8b4f07d4691 411 break;
va009039 2:b8b4f07d4691 412 case 0x10:
va009039 2:b8b4f07d4691 413 V6M_INFO("P: LPC_SPI%d->CPSR << %08x", ch, d);
va009039 2:b8b4f07d4691 414 break;
va009039 2:b8b4f07d4691 415 default:
va009039 2:b8b4f07d4691 416 V6M_WARN("P: LPC_SPI%d %08x << %08x", ch, a, d);
va009039 2:b8b4f07d4691 417 break;
va009039 2:b8b4f07d4691 418 }
va009039 2:b8b4f07d4691 419 }
va009039 2:b8b4f07d4691 420
va009039 2:b8b4f07d4691 421 uint32_t EMU111x_SPI::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 422 uint32_t d = 0;
va009039 2:b8b4f07d4691 423 switch(a&0xff) {
va009039 2:b8b4f07d4691 424 case 0x00:
va009039 2:b8b4f07d4691 425 d = cr0;
va009039 2:b8b4f07d4691 426 V6M_INFO("P: LPC_SPI%d->CR0 >> %08x", ch, d);
va009039 2:b8b4f07d4691 427 break;
va009039 2:b8b4f07d4691 428 case 0x04:
va009039 2:b8b4f07d4691 429 d = cr1;
va009039 2:b8b4f07d4691 430 V6M_INFO("P: LPC_SPI%d->CR1 >> %08x", ch, d);
va009039 2:b8b4f07d4691 431 break;
va009039 2:b8b4f07d4691 432 case 0x08:
va009039 2:b8b4f07d4691 433 d = dr;
va009039 2:b8b4f07d4691 434 V6M_INFO("P: LPC_SPI%d->DR >> %08x", ch, d);
va009039 2:b8b4f07d4691 435 break;
va009039 2:b8b4f07d4691 436 case 0x0c:
va009039 2:b8b4f07d4691 437 d = 0x06;
va009039 2:b8b4f07d4691 438 V6M_INFO("P: LPC_SPI%d->SR >> %08x", ch, d);
va009039 2:b8b4f07d4691 439 break;
va009039 2:b8b4f07d4691 440 default:
va009039 2:b8b4f07d4691 441 V6M_WARN("P: LPC_SPI%d %08x >> %08x", ch, a, d);
va009039 2:b8b4f07d4691 442 break;
va009039 2:b8b4f07d4691 443 }
va009039 2:b8b4f07d4691 444 return d;
va009039 2:b8b4f07d4691 445 }
va009039 2:b8b4f07d4691 446
va009039 2:b8b4f07d4691 447 void EMU111x_NVIC::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 448 switch(a) {
va009039 2:b8b4f07d4691 449 case 0xe000e100:
va009039 2:b8b4f07d4691 450 iser = d;
va009039 2:b8b4f07d4691 451 V6M_INFO("P: NVIC->ISER[0] << %08x", d);
va009039 2:b8b4f07d4691 452 break;
va009039 2:b8b4f07d4691 453 default:
va009039 2:b8b4f07d4691 454 V6M_WARN("P: NVIC %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 455 break;
va009039 2:b8b4f07d4691 456 }
va009039 2:b8b4f07d4691 457 }
va009039 2:b8b4f07d4691 458
va009039 2:b8b4f07d4691 459 EMU111x::EMU111x():tmr32b1(1),uart(*this),i2c(*this),spi0(*this,0),spi1(*this,1),gpio0(*this,0),gpio1(*this,1) {
va009039 2:b8b4f07d4691 460 flash = NULL;
va009039 2:b8b4f07d4691 461 rom = NULL;
va009039 2:b8b4f07d4691 462 ram = new uint8_t[EMU111x_RAM_SIZE];
va009039 2:b8b4f07d4691 463 }
va009039 2:b8b4f07d4691 464
va009039 2:b8b4f07d4691 465 void EMU111x::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 466 switch(a>>24) {
va009039 2:b8b4f07d4691 467 case EMU111x_RAM_BASE>>24:
va009039 2:b8b4f07d4691 468 V6M_ASSERT(a < (EMU111x_RAM_BASE+EMU111x_RAM_SIZE));
va009039 2:b8b4f07d4691 469 ram[a - EMU111x_RAM_BASE] = d;
va009039 2:b8b4f07d4691 470 ram[a - EMU111x_RAM_BASE + 1] = d>>8;
va009039 2:b8b4f07d4691 471 ram[a - EMU111x_RAM_BASE + 2] = d>>16;
va009039 2:b8b4f07d4691 472 ram[a - EMU111x_RAM_BASE + 3] = d>>24;
va009039 2:b8b4f07d4691 473 V6M_INFO("W: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 474 break;
va009039 2:b8b4f07d4691 475 case EMU111x_APB_BASE>>24:
va009039 2:b8b4f07d4691 476 switch((a>>12)&0xff) {
va009039 2:b8b4f07d4691 477 case 0x00: i2c.poke32(a, d); break;
va009039 2:b8b4f07d4691 478 case 0x08: uart.poke32(a, d); break;
va009039 2:b8b4f07d4691 479 case 0x18: tmr32b1.poke32(a, d); break;
va009039 2:b8b4f07d4691 480 case 0x40: spi0.poke32(a, d); break;
va009039 2:b8b4f07d4691 481 case 0x44: iocon.poke32(a, d); break;
va009039 2:b8b4f07d4691 482 case 0x48: syscon.poke32(a, d); break;
va009039 2:b8b4f07d4691 483 case 0x58: spi1.poke32(a, d); break;
va009039 2:b8b4f07d4691 484 default:
va009039 2:b8b4f07d4691 485 V6M_WARN("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 486 break;
va009039 2:b8b4f07d4691 487 }
va009039 2:b8b4f07d4691 488 break;
va009039 2:b8b4f07d4691 489 case EMU111x_AHB_BASE>>24:
va009039 2:b8b4f07d4691 490 switch((a>>16)&0xff) {
va009039 2:b8b4f07d4691 491 case 0: gpio0.poke32(a, d); break;
va009039 2:b8b4f07d4691 492 case 1: gpio1.poke32(a, d); break;
va009039 2:b8b4f07d4691 493 default:
va009039 2:b8b4f07d4691 494 V6M_ERROR("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 495 break;
va009039 2:b8b4f07d4691 496 }
va009039 2:b8b4f07d4691 497 break;
va009039 2:b8b4f07d4691 498 case EMU111x_FLASH_BASE>>24:
va009039 2:b8b4f07d4691 499 case EMU111x_ROM_BASE>>24:
va009039 2:b8b4f07d4691 500 V6M_ERROR("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 501 V6M_ASSERT(0);
va009039 2:b8b4f07d4691 502 break;
va009039 2:b8b4f07d4691 503 case EMU111x_SCS_BASE>>24:
va009039 2:b8b4f07d4691 504 switch(a&0xffffff) {
va009039 2:b8b4f07d4691 505 case 0x00e100:
va009039 2:b8b4f07d4691 506 nvic.poke32(a, d);
va009039 2:b8b4f07d4691 507 break;
va009039 2:b8b4f07d4691 508 default:
va009039 2:b8b4f07d4691 509 V6M_WARN("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 510 break;
va009039 2:b8b4f07d4691 511 }
va009039 2:b8b4f07d4691 512 break;
va009039 2:b8b4f07d4691 513 default:
va009039 2:b8b4f07d4691 514 V6M_WARN("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 515 break;
va009039 2:b8b4f07d4691 516 }
va009039 2:b8b4f07d4691 517 }
va009039 2:b8b4f07d4691 518
va009039 2:b8b4f07d4691 519 uint32_t EMU111x::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 520 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 521 switch(a>>24) {
va009039 2:b8b4f07d4691 522 case EMU111x_RAM_BASE>>24:
va009039 2:b8b4f07d4691 523 V6M_ASSERT(a < (EMU111x_RAM_BASE+EMU111x_RAM_SIZE));
va009039 2:b8b4f07d4691 524 d = ram[a - EMU111x_RAM_BASE];
va009039 2:b8b4f07d4691 525 d |= ram[a - EMU111x_RAM_BASE + 1]<<8;
va009039 2:b8b4f07d4691 526 d |= ram[a - EMU111x_RAM_BASE + 2]<<16;
va009039 2:b8b4f07d4691 527 d |= ram[a - EMU111x_RAM_BASE + 3]<<24;
va009039 2:b8b4f07d4691 528 V6M_INFO("R: %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 529 break;
va009039 2:b8b4f07d4691 530 case EMU111x_FLASH_BASE>>24:
va009039 2:b8b4f07d4691 531 V6M_ASSERT(a < (EMU111x_FLASH_BASE+EMU111x_FLASH_SIZE));
va009039 2:b8b4f07d4691 532 d = flash[a - EMU111x_FLASH_BASE];
va009039 2:b8b4f07d4691 533 d |= flash[a - EMU111x_FLASH_BASE + 1]<<8;
va009039 2:b8b4f07d4691 534 d |= flash[a - EMU111x_FLASH_BASE + 2]<<16;
va009039 2:b8b4f07d4691 535 d |= flash[a - EMU111x_FLASH_BASE + 3]<<24;
va009039 2:b8b4f07d4691 536 break;
va009039 2:b8b4f07d4691 537 case EMU111x_ROM_BASE>>24:
va009039 2:b8b4f07d4691 538 V6M_ERROR("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 539 V6M_ASSERT(0);
va009039 2:b8b4f07d4691 540 break;
va009039 2:b8b4f07d4691 541 case EMU111x_APB_BASE>>24:
va009039 2:b8b4f07d4691 542 switch((a>>12)&0xff) {
va009039 2:b8b4f07d4691 543 case 0x00: d = i2c.peek32(a); break;
va009039 2:b8b4f07d4691 544 case 0x08: d = uart.peek32(a); break;
va009039 2:b8b4f07d4691 545 case 0x18: d = tmr32b1.peek32(a); break;
va009039 2:b8b4f07d4691 546 case 0x40: d = spi0.peek32(a); break;
va009039 2:b8b4f07d4691 547 case 0x44: d = iocon.peek32(a); break;
va009039 2:b8b4f07d4691 548 case 0x48: d = syscon.peek32(a); break;
va009039 2:b8b4f07d4691 549 case 0x58: d = spi1.peek32(a); break;
va009039 2:b8b4f07d4691 550 default:
va009039 2:b8b4f07d4691 551 V6M_WARN("P: %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 552 break;
va009039 2:b8b4f07d4691 553 }
va009039 2:b8b4f07d4691 554 break;
va009039 2:b8b4f07d4691 555 case EMU111x_AHB_BASE>>24:
va009039 2:b8b4f07d4691 556 switch((a>>16)&0xff) {
va009039 2:b8b4f07d4691 557 case 0: d = gpio0.peek32(a); break;
va009039 2:b8b4f07d4691 558 case 1: d = gpio1.peek32(a); break;
va009039 2:b8b4f07d4691 559 default:
va009039 2:b8b4f07d4691 560 V6M_ERROR("P: %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 561 break;
va009039 2:b8b4f07d4691 562 }
va009039 2:b8b4f07d4691 563 break;
va009039 2:b8b4f07d4691 564 default:
va009039 2:b8b4f07d4691 565 V6M_WARN("P: %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 566 break;
va009039 2:b8b4f07d4691 567 }
va009039 2:b8b4f07d4691 568 return d;
va009039 2:b8b4f07d4691 569 }
va009039 2:b8b4f07d4691 570
va009039 2:b8b4f07d4691 571 void EMU111x::poke8(uint32_t a, uint8_t d) {
va009039 2:b8b4f07d4691 572 switch(a>>24) {
va009039 2:b8b4f07d4691 573 case EMU111x_RAM_BASE>>24:
va009039 2:b8b4f07d4691 574 V6M_ASSERT(a < (EMU111x_RAM_BASE+EMU111x_RAM_SIZE));
va009039 2:b8b4f07d4691 575 ram[a - EMU111x_RAM_BASE] = d;
va009039 2:b8b4f07d4691 576 V6M_INFO("W: %08x << %02x", a, d);
va009039 2:b8b4f07d4691 577 break;
va009039 2:b8b4f07d4691 578 default:
va009039 2:b8b4f07d4691 579 V6M_ERROR("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 580 V6M_ASSERT(0);
va009039 2:b8b4f07d4691 581 break;
va009039 2:b8b4f07d4691 582 }
va009039 2:b8b4f07d4691 583 }
va009039 2:b8b4f07d4691 584
va009039 2:b8b4f07d4691 585 uint8_t EMU111x::peek8(uint32_t a) {
va009039 2:b8b4f07d4691 586 uint8_t d = 0x00;
va009039 2:b8b4f07d4691 587 switch(a>>24) {
va009039 2:b8b4f07d4691 588 case EMU111x_RAM_BASE>>24:
va009039 2:b8b4f07d4691 589 V6M_ASSERT(a < (EMU111x_RAM_BASE+EMU111x_RAM_SIZE));
va009039 2:b8b4f07d4691 590 d = ram[a - EMU111x_RAM_BASE];
va009039 2:b8b4f07d4691 591 V6M_INFO("R: %08x >> %02x", a, d);
va009039 2:b8b4f07d4691 592 break;
va009039 2:b8b4f07d4691 593 case EMU111x_FLASH_BASE>>24:
va009039 2:b8b4f07d4691 594 V6M_ASSERT(a < (EMU111x_FLASH_BASE+EMU111x_FLASH_SIZE));
va009039 2:b8b4f07d4691 595 d = flash[a - EMU111x_FLASH_BASE];
va009039 2:b8b4f07d4691 596 break;
va009039 2:b8b4f07d4691 597 case EMU111x_ROM_BASE>>24:
va009039 2:b8b4f07d4691 598 V6M_ASSERT(a < (EMU111x_ROM_BASE+EMU111x_ROM_SIZE));
va009039 2:b8b4f07d4691 599 d = flash[a - EMU111x_ROM_BASE];
va009039 2:b8b4f07d4691 600 break;
va009039 2:b8b4f07d4691 601 default:
va009039 2:b8b4f07d4691 602 V6M_ASSERT(0);
va009039 2:b8b4f07d4691 603 break;
va009039 2:b8b4f07d4691 604 }
va009039 2:b8b4f07d4691 605 return d;
va009039 2:b8b4f07d4691 606 }
va009039 2:b8b4f07d4691 607
va009039 2:b8b4f07d4691 608 void EMU111x::clock_in(uint32_t n) {
va009039 2:b8b4f07d4691 609 tmr32b1.clock_in(n);
va009039 2:b8b4f07d4691 610 }
va009039 2:b8b4f07d4691 611
va009039 2:b8b4f07d4691 612 void EMU111x::trace() {
va009039 2:b8b4f07d4691 613 V6M_INFO("S: r0=%08x r1=%08x r2=%08x r3=%08x r4=%08x r5=%08x r6=%08x r7=%08x", R[0],R[1],R[2],R[3],R[4],R[5],R[6],R[7]);
va009039 2:b8b4f07d4691 614 V6M_INFO("S: r8=%08x r9=%08x r10=%08x r11=%08x r12=%08x sp=%08x lr=%08x pc=%08x", R[8],R[9],R[10],R[11],R[12],R[13],R[14],R[15]);
va009039 2:b8b4f07d4691 615 V6M_INFO("S: xPSR=%08x N=%d Z=%d C=%d V=%d", R[16], N(), Z(), C(), V());
va009039 2:b8b4f07d4691 616 V6M_DEBUG("S: cycle=%d code=%02x code2nd=%02x im=%08x d=%d n=%d m=%d", cycle, code, code2nd, R[17], GetRegIndex(Rd), GetRegIndex(Rn), GetRegIndex(Rm));
va009039 2:b8b4f07d4691 617 }
va009039 2:b8b4f07d4691 618