Webcam Server.

Dependencies:   uvchost FatFileSystem mbed HTTPServer NetServicesMin

Committer:
va009039
Date:
Wed Jun 06 11:47:06 2012 +0000
Revision:
0:2b4ea8a138e5

        

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 0:2b4ea8a138e5 1
va009039 0:2b4ea8a138e5 2 /*
va009039 0:2b4ea8a138e5 3 Copyright (c) 2010 Donatien Garnier (donatiengar [at] gmail [dot] com)
va009039 0:2b4ea8a138e5 4
va009039 0:2b4ea8a138e5 5 Permission is hereby granted, free of charge, to any person obtaining a copy
va009039 0:2b4ea8a138e5 6 of this software and associated documentation files (the "Software"), to deal
va009039 0:2b4ea8a138e5 7 in the Software without restriction, including without limitation the rights
va009039 0:2b4ea8a138e5 8 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
va009039 0:2b4ea8a138e5 9 copies of the Software, and to permit persons to whom the Software is
va009039 0:2b4ea8a138e5 10 furnished to do so, subject to the following conditions:
va009039 0:2b4ea8a138e5 11
va009039 0:2b4ea8a138e5 12 The above copyright notice and this permission notice shall be included in
va009039 0:2b4ea8a138e5 13 all copies or substantial portions of the Software.
va009039 0:2b4ea8a138e5 14
va009039 0:2b4ea8a138e5 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
va009039 0:2b4ea8a138e5 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
va009039 0:2b4ea8a138e5 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
va009039 0:2b4ea8a138e5 18 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
va009039 0:2b4ea8a138e5 19 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
va009039 0:2b4ea8a138e5 20 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
va009039 0:2b4ea8a138e5 21 THE SOFTWARE.
va009039 0:2b4ea8a138e5 22 */
va009039 0:2b4ea8a138e5 23
va009039 0:2b4ea8a138e5 24 #ifndef USB_INC_H
va009039 0:2b4ea8a138e5 25 #define USB_INC_H
va009039 0:2b4ea8a138e5 26
va009039 0:2b4ea8a138e5 27 #include "mbed.h"
va009039 0:2b4ea8a138e5 28
va009039 0:2b4ea8a138e5 29 #define MIN(a,b) ((a)<(b)?(a):(b))
va009039 0:2b4ea8a138e5 30 #define MAX(a,b) ((a)>(b)?(a):(b))
va009039 0:2b4ea8a138e5 31
va009039 0:2b4ea8a138e5 32 //typedef int32_t RC;
va009039 0:2b4ea8a138e5 33
va009039 0:2b4ea8a138e5 34 typedef uint8_t byte;
va009039 0:2b4ea8a138e5 35 typedef uint16_t word;
va009039 0:2b4ea8a138e5 36
va009039 0:2b4ea8a138e5 37 enum UsbErr
va009039 0:2b4ea8a138e5 38 {
va009039 0:2b4ea8a138e5 39 __USBERR_MIN = -0xFFFF,
va009039 0:2b4ea8a138e5 40 USBERR_DISCONNECTED,
va009039 0:2b4ea8a138e5 41 USBERR_NOTFOUND,
va009039 0:2b4ea8a138e5 42 USBERR_BADCONFIG,
va009039 0:2b4ea8a138e5 43 USBERR_PROCESSING,
va009039 0:2b4ea8a138e5 44 USBERR_HALTED, //Transfer on an ep is stalled
va009039 0:2b4ea8a138e5 45 USBERR_BUSY,
va009039 0:2b4ea8a138e5 46 USBERR_TDFAIL,
va009039 0:2b4ea8a138e5 47 USBERR_ERROR,
va009039 0:2b4ea8a138e5 48 USBERR_OK = 0
va009039 0:2b4ea8a138e5 49 };
va009039 0:2b4ea8a138e5 50
va009039 0:2b4ea8a138e5 51
va009039 0:2b4ea8a138e5 52 /* From NXP's USBHostLite stack's usbhost_lpc17xx.h */
va009039 0:2b4ea8a138e5 53 /* Only the types names have been changed to avoid unecessary typedefs */
va009039 0:2b4ea8a138e5 54
va009039 0:2b4ea8a138e5 55
va009039 0:2b4ea8a138e5 56 /*
va009039 0:2b4ea8a138e5 57 **************************************************************************************************************
va009039 0:2b4ea8a138e5 58 * NXP USB Host Stack
va009039 0:2b4ea8a138e5 59 *
va009039 0:2b4ea8a138e5 60 * (c) Copyright 2008, NXP SemiConductors
va009039 0:2b4ea8a138e5 61 * (c) Copyright 2008, OnChip Technologies LLC
va009039 0:2b4ea8a138e5 62 * All Rights Reserved
va009039 0:2b4ea8a138e5 63 *
va009039 0:2b4ea8a138e5 64 * www.nxp.com
va009039 0:2b4ea8a138e5 65 * www.onchiptech.com
va009039 0:2b4ea8a138e5 66 *
va009039 0:2b4ea8a138e5 67 * File : usbhost_lpc17xx.h
va009039 0:2b4ea8a138e5 68 * Programmer(s) : Ravikanth.P
va009039 0:2b4ea8a138e5 69 * Version :
va009039 0:2b4ea8a138e5 70 *
va009039 0:2b4ea8a138e5 71 **************************************************************************************************************
va009039 0:2b4ea8a138e5 72 */
va009039 0:2b4ea8a138e5 73
va009039 0:2b4ea8a138e5 74
va009039 0:2b4ea8a138e5 75
va009039 0:2b4ea8a138e5 76 /*
va009039 0:2b4ea8a138e5 77 **************************************************************************************************************
va009039 0:2b4ea8a138e5 78 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
va009039 0:2b4ea8a138e5 79 **************************************************************************************************************
va009039 0:2b4ea8a138e5 80 */
va009039 0:2b4ea8a138e5 81
va009039 0:2b4ea8a138e5 82 /* ------------------ HcControl Register --------------------- */
va009039 0:2b4ea8a138e5 83 #define OR_CONTROL_PLE 0x00000004
va009039 0:2b4ea8a138e5 84 #define OR_CONTROL_IE 0x00000008
va009039 0:2b4ea8a138e5 85 #define OR_CONTROL_CLE 0x00000010
va009039 0:2b4ea8a138e5 86 #define OR_CONTROL_BLE 0x00000020
va009039 0:2b4ea8a138e5 87 #define OR_CONTROL_HCFS 0x000000C0
va009039 0:2b4ea8a138e5 88 #define OR_CONTROL_HC_OPER 0x00000080
va009039 0:2b4ea8a138e5 89 /* ----------------- HcCommandStatus Register ----------------- */
va009039 0:2b4ea8a138e5 90 #define OR_CMD_STATUS_HCR 0x00000001
va009039 0:2b4ea8a138e5 91 #define OR_CMD_STATUS_CLF 0x00000002
va009039 0:2b4ea8a138e5 92 #define OR_CMD_STATUS_BLF 0x00000004
va009039 0:2b4ea8a138e5 93 /* --------------- HcInterruptStatus Register ----------------- */
va009039 0:2b4ea8a138e5 94 #define OR_INTR_STATUS_WDH 0x00000002
va009039 0:2b4ea8a138e5 95 #define OR_INTR_STATUS_RHSC 0x00000040
va009039 0:2b4ea8a138e5 96 #define OR_INTR_STATUS_UE 0x00000010
va009039 0:2b4ea8a138e5 97 /* --------------- HcInterruptEnable Register ----------------- */
va009039 0:2b4ea8a138e5 98 #define OR_INTR_ENABLE_WDH 0x00000002
va009039 0:2b4ea8a138e5 99 #define OR_INTR_ENABLE_RHSC 0x00000040
va009039 0:2b4ea8a138e5 100 #define OR_INTR_ENABLE_MIE 0x80000000
va009039 0:2b4ea8a138e5 101 /* ---------------- HcRhDescriptorA Register ------------------ */
va009039 0:2b4ea8a138e5 102 #define OR_RH_STATUS_LPSC 0x00010000
va009039 0:2b4ea8a138e5 103 #define OR_RH_STATUS_DRWE 0x00008000
va009039 0:2b4ea8a138e5 104 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
va009039 0:2b4ea8a138e5 105 #define OR_RH_PORT_CCS 0x00000001
va009039 0:2b4ea8a138e5 106 #define OR_RH_PORT_PRS 0x00000010
va009039 0:2b4ea8a138e5 107 #define OR_RH_PORT_CSC 0x00010000
va009039 0:2b4ea8a138e5 108 #define OR_RH_PORT_PRSC 0x00100000
va009039 0:2b4ea8a138e5 109
va009039 0:2b4ea8a138e5 110
va009039 0:2b4ea8a138e5 111 /*
va009039 0:2b4ea8a138e5 112 **************************************************************************************************************
va009039 0:2b4ea8a138e5 113 * FRAME INTERVAL
va009039 0:2b4ea8a138e5 114 **************************************************************************************************************
va009039 0:2b4ea8a138e5 115 */
va009039 0:2b4ea8a138e5 116
va009039 0:2b4ea8a138e5 117 #define FI 0x2EDF /* 12000 bits per frame (-1) */
va009039 0:2b4ea8a138e5 118 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
va009039 0:2b4ea8a138e5 119
va009039 0:2b4ea8a138e5 120 /*
va009039 0:2b4ea8a138e5 121 **************************************************************************************************************
va009039 0:2b4ea8a138e5 122 * ENDPOINT DESCRIPTOR CONTROL FIELDS
va009039 0:2b4ea8a138e5 123 **************************************************************************************************************
va009039 0:2b4ea8a138e5 124 */
va009039 0:2b4ea8a138e5 125
va009039 0:2b4ea8a138e5 126 #define ED_SKIP (uint32_t) (0x00001000) /* Skip this ep in queue */
va009039 0:2b4ea8a138e5 127
va009039 0:2b4ea8a138e5 128 /*
va009039 0:2b4ea8a138e5 129 **************************************************************************************************************
va009039 0:2b4ea8a138e5 130 * TRANSFER DESCRIPTOR CONTROL FIELDS
va009039 0:2b4ea8a138e5 131 **************************************************************************************************************
va009039 0:2b4ea8a138e5 132 */
va009039 0:2b4ea8a138e5 133
va009039 0:2b4ea8a138e5 134 #define TD_ROUNDING (uint32_t) (0x00040000) /* Buffer Rounding */
va009039 0:2b4ea8a138e5 135 #define TD_SETUP (uint32_t)(0) /* Direction of Setup Packet */
va009039 0:2b4ea8a138e5 136 #define TD_IN (uint32_t)(0x00100000) /* Direction In */
va009039 0:2b4ea8a138e5 137 #define TD_OUT (uint32_t)(0x00080000) /* Direction Out */
va009039 0:2b4ea8a138e5 138 #define TD_DELAY_INT(x) (uint32_t)((x) << 21) /* Delay Interrupt */
va009039 0:2b4ea8a138e5 139 #define TD_TOGGLE_0 (uint32_t)(0x02000000) /* Toggle 0 */
va009039 0:2b4ea8a138e5 140 #define TD_TOGGLE_1 (uint32_t)(0x03000000) /* Toggle 1 */
va009039 0:2b4ea8a138e5 141 #define TD_CC (uint32_t)(0xF0000000) /* Completion Code */
va009039 0:2b4ea8a138e5 142
va009039 0:2b4ea8a138e5 143 #define ITD_SF (uint32_t)(0x0000FFFF) /* Starting Frame */
va009039 0:2b4ea8a138e5 144 #define ITD_FC (uint32_t)(0x07000000) /* FrameCount */
va009039 0:2b4ea8a138e5 145
va009039 0:2b4ea8a138e5 146 /*
va009039 0:2b4ea8a138e5 147 **************************************************************************************************************
va009039 0:2b4ea8a138e5 148 * USB STANDARD REQUEST DEFINITIONS
va009039 0:2b4ea8a138e5 149 **************************************************************************************************************
va009039 0:2b4ea8a138e5 150 */
va009039 0:2b4ea8a138e5 151
va009039 0:2b4ea8a138e5 152 #define USB_DESCRIPTOR_TYPE_DEVICE 1
va009039 0:2b4ea8a138e5 153 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
va009039 0:2b4ea8a138e5 154 #define USB_DESCRIPTOR_TYPE_STRING 3
va009039 0:2b4ea8a138e5 155 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
va009039 0:2b4ea8a138e5 156 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
va009039 0:2b4ea8a138e5 157 #define USB_DESCRIPTOR_TYPE_HUB 0x29
va009039 0:2b4ea8a138e5 158 /* ----------- Control RequestType Fields ----------- */
va009039 0:2b4ea8a138e5 159 #define USB_DEVICE_TO_HOST 0x80
va009039 0:2b4ea8a138e5 160 #define USB_HOST_TO_DEVICE 0x00
va009039 0:2b4ea8a138e5 161 #define USB_REQUEST_TYPE_CLASS 0x20
va009039 0:2b4ea8a138e5 162 #define USB_RECIPIENT_DEVICE 0x00
va009039 0:2b4ea8a138e5 163 #define USB_RECIPIENT_INTERFACE 0x01
va009039 0:2b4ea8a138e5 164 #define USB_RECIPIENT_OTHER 0x03
va009039 0:2b4ea8a138e5 165
va009039 0:2b4ea8a138e5 166 /* -------------- USB Standard Requests -------------- */
va009039 0:2b4ea8a138e5 167 #define GET_STATUS 0
va009039 0:2b4ea8a138e5 168 #define CLEAR_FEATURE 1
va009039 0:2b4ea8a138e5 169 #define SET_FEATURE 3
va009039 0:2b4ea8a138e5 170 #define SET_ADDRESS 5
va009039 0:2b4ea8a138e5 171 #define GET_DESCRIPTOR 6
va009039 0:2b4ea8a138e5 172 #define SET_CONFIGURATION 9
va009039 0:2b4ea8a138e5 173 #define SET_INTERFACE 11
va009039 0:2b4ea8a138e5 174
va009039 0:2b4ea8a138e5 175 /*
va009039 0:2b4ea8a138e5 176 **************************************************************************************************************
va009039 0:2b4ea8a138e5 177 * TYPE DEFINITIONS
va009039 0:2b4ea8a138e5 178 **************************************************************************************************************
va009039 0:2b4ea8a138e5 179 */
va009039 0:2b4ea8a138e5 180
va009039 0:2b4ea8a138e5 181 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
va009039 0:2b4ea8a138e5 182 volatile uint32_t Control; /* Endpoint descriptor control */
va009039 0:2b4ea8a138e5 183 volatile uint32_t TailTd; /* Physical address of tail in Transfer descriptor list */
va009039 0:2b4ea8a138e5 184 volatile uint32_t HeadTd; /* Physcial address of head in Transfer descriptor list */
va009039 0:2b4ea8a138e5 185 volatile uint32_t Next; /* Physical address of next Endpoint descriptor */
va009039 0:2b4ea8a138e5 186 } HCED;
va009039 0:2b4ea8a138e5 187
va009039 0:2b4ea8a138e5 188 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
va009039 0:2b4ea8a138e5 189 volatile uint32_t Control; /* Transfer descriptor control */
va009039 0:2b4ea8a138e5 190 volatile uint32_t CurrBufPtr; /* Physical address of current buffer pointer */
va009039 0:2b4ea8a138e5 191 volatile uint32_t Next; /* Physical pointer to next Transfer Descriptor */
va009039 0:2b4ea8a138e5 192 volatile uint32_t BufEnd; /* Physical address of end of buffer */
va009039 0:2b4ea8a138e5 193 } HCTD;
va009039 0:2b4ea8a138e5 194
va009039 0:2b4ea8a138e5 195 typedef struct hcItd { // HostController Isochronous Transfer Descriptor
va009039 0:2b4ea8a138e5 196 volatile uint32_t Control; // Transfer descriptor control
va009039 0:2b4ea8a138e5 197 volatile uint32_t BufferPage0; // Buffer Page 0
va009039 0:2b4ea8a138e5 198 volatile uint32_t Next; // Physical pointer to next Transfer Descriptor
va009039 0:2b4ea8a138e5 199 volatile uint32_t BufferEnd; // buffer End
va009039 0:2b4ea8a138e5 200 volatile uint32_t OffsetPSW10; // Offset1/PSW1 Offset0/PSW0
va009039 0:2b4ea8a138e5 201 volatile uint32_t OffsetPSW32; // Offset3/PSW3 Offset2/PSW2
va009039 0:2b4ea8a138e5 202 volatile uint32_t OffsetPSW54; // Offset5/PSW5 Offset4/PSW4
va009039 0:2b4ea8a138e5 203 volatile uint32_t OffsetPSW76; // Offset7/PSW7 Offset6/PSW6
va009039 0:2b4ea8a138e5 204 } HCITD;
va009039 0:2b4ea8a138e5 205
va009039 0:2b4ea8a138e5 206 typedef struct hcUtd {
va009039 0:2b4ea8a138e5 207 union {
va009039 0:2b4ea8a138e5 208 HCTD hctd;
va009039 0:2b4ea8a138e5 209 HCITD hcitd;
va009039 0:2b4ea8a138e5 210 };
va009039 0:2b4ea8a138e5 211 volatile uint32_t type; // 1:TD, 2:ITD
va009039 0:2b4ea8a138e5 212 volatile uint32_t UsbEndpoint;
va009039 0:2b4ea8a138e5 213 volatile uint32_t reserve1;
va009039 0:2b4ea8a138e5 214 volatile uint32_t reserve2;
va009039 0:2b4ea8a138e5 215 } HCUTD;
va009039 0:2b4ea8a138e5 216
va009039 0:2b4ea8a138e5 217 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
va009039 0:2b4ea8a138e5 218 volatile uint32_t IntTable[32]; /* Interrupt Table */
va009039 0:2b4ea8a138e5 219 volatile uint32_t FrameNumber; /* Frame Number */
va009039 0:2b4ea8a138e5 220 volatile uint32_t DoneHead; /* Done Head */
va009039 0:2b4ea8a138e5 221 volatile uint8_t Reserved[116]; /* Reserved for future use */
va009039 0:2b4ea8a138e5 222 volatile uint8_t Unknown[4]; /* Unused */
va009039 0:2b4ea8a138e5 223 } HCCA;
va009039 0:2b4ea8a138e5 224
va009039 0:2b4ea8a138e5 225
va009039 0:2b4ea8a138e5 226
va009039 0:2b4ea8a138e5 227 #endif