Target2.h

00001 // Target2.h 2013/9/23
00002 #pragma once
00003 #include "mbed.h"
00004 #include "SWD.h"
00005 
00006 #define TARGET_RUNNING  (1<<0)
00007 #define TARGET_HALTED   (1<<1)
00008 
00009 class Target2;
00010 class CoreReg {
00011 public:
00012     void setup(Target2* target, uint8_t reg);
00013     uint32_t read();
00014     void write(uint32_t value);
00015     
00016     CoreReg& operator= (int value) {
00017         write(value);
00018         return *this;
00019     }
00020 
00021     CoreReg& operator= (CoreReg& rhs) {
00022         write(rhs.read());
00023         return *this;
00024     }
00025 
00026     operator uint32_t() {
00027         return read();
00028     }
00029 protected:
00030     Target2* _target;
00031     uint8_t _reg;    
00032 };
00033 
00034 /** Target MCU interface
00035  */
00036 class Target2 {
00037 public:
00038     /** create target MCU interface
00039      * @param swdio SWD(swdio) pin
00040      * @param swclk SWD(swclk) pin
00041      * @param reset reset pin
00042      */
00043     Target2(PinName swdio, PinName swclk, PinName reset);
00044 
00045     /** create target MCU interface
00046      * @param swd SWD interface
00047      */
00048     Target2(SWD* swd);
00049     bool setup();
00050     void SWJClock(uint32_t clock_hz);
00051     uint32_t readMemory(uint32_t addr);
00052     void readMemory(uint32_t addr, uint32_t* data, int count);
00053     void writeMemory(uint32_t addr, uint32_t data);
00054     void writeMemory(uint32_t addr, uint32_t* data, int count);
00055     uint8_t readMemory8(uint32_t addr);
00056     void writeMemory8(uint32_t addr, uint8_t data);
00057     void halt();
00058     void resume();
00059     void step();
00060     void Abort();
00061     void HardwareReset();
00062     void SoftwareReset();
00063     int getStatus();
00064     bool wait_status(int status, int timeout_ms = 500);
00065     bool prog_status();
00066     bool setBreakpoint0(uint32_t addr);
00067     void removeBreakpoint0(uint32_t addr);
00068 
00069     CoreReg r0;
00070     CoreReg r1; 
00071     CoreReg r2; 
00072     CoreReg r3; 
00073     CoreReg r4; 
00074     CoreReg r5; 
00075     CoreReg r6; 
00076     CoreReg r7; 
00077     CoreReg r8; 
00078     CoreReg r9; 
00079     CoreReg r10; 
00080     CoreReg r11; 
00081     CoreReg r12; 
00082     CoreReg sp; 
00083     CoreReg lr; 
00084     CoreReg pc;
00085     CoreReg xpsr;
00086     
00087     uint32_t idcode;
00088 protected:
00089     void inst();
00090     void _setaddr(uint32_t addr); 
00091     void _setaddr8(uint32_t addr); 
00092     void JTAG2SWD();
00093 
00094     SWD* _swd;
00095 };