Norimasa Okamoto / BaseUsbHost

USB host library, support isochronous,bulk,interrupt and control.

Dependents:   BaseUsbHost_example BaseJpegDecode_example SimpleJpegDecode_example

Import programBaseUsbHost_example

BaseUsbHost example program

Last commit 25 Jan 2013 by Norimasa Okamoto

BaseUsbHost.h@3:ae77d63a1eda, 2013-01-06 (annotated)

Committer:
va009039
Date:
Sun Jan 06 11:45:18 2013 +0000
Revision:
3:ae77d63a1eda
Parent:
2:fe1e62051d88
Child:
4:d931d24c2f81
change interface usbhub class

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 3:ae77d63a1eda 1 // BaseUsbHost.h 2013/1/5
va009039 3:ae77d63a1eda 2 #pragma once
va009039 3:ae77d63a1eda 3 #include <vector>
va009039 0:b7d6879637a8 4
va009039 2:fe1e62051d88 5 #define USB_OK 0
va009039 2:fe1e62051d88 6 #define USB_PROCESSING -1
va009039 2:fe1e62051d88 7 #define USB_ERROR -2
va009039 2:fe1e62051d88 8 #define USB_ERROR_MEMORY -3
va009039 3:ae77d63a1eda 9 #define USB_ERROR_STALL -4
va009039 3:ae77d63a1eda 10 #define USB_ERROR_DEVICE_NOT_RESPONDING -5
va009039 0:b7d6879637a8 11
va009039 0:b7d6879637a8 12 // USB STANDARD REQUEST DEFINITIONS
va009039 0:b7d6879637a8 13 #define USB_DESCRIPTOR_TYPE_DEVICE 1
va009039 0:b7d6879637a8 14 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
va009039 0:b7d6879637a8 15 #define USB_DESCRIPTOR_TYPE_STRING 3
va009039 0:b7d6879637a8 16 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
va009039 0:b7d6879637a8 17 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
va009039 0:b7d6879637a8 18 #define USB_DESCRIPTOR_TYPE_HUB 0x29
va009039 0:b7d6879637a8 19 // ----------- Control RequestType Fields -----------
va009039 0:b7d6879637a8 20 #define USB_DEVICE_TO_HOST 0x80
va009039 0:b7d6879637a8 21 #define USB_HOST_TO_DEVICE 0x00
va009039 0:b7d6879637a8 22 #define USB_REQUEST_TYPE_CLASS 0x20
va009039 0:b7d6879637a8 23 #define USB_RECIPIENT_DEVICE 0x00
va009039 0:b7d6879637a8 24 #define USB_RECIPIENT_INTERFACE 0x01
va009039 0:b7d6879637a8 25 #define USB_RECIPIENT_OTHER 0x03
va009039 0:b7d6879637a8 26 // -------------- USB Standard Requests --------------
va009039 0:b7d6879637a8 27 #define GET_STATUS 0
va009039 0:b7d6879637a8 28 #define CLEAR_FEATURE 1
va009039 0:b7d6879637a8 29 #define SET_FEATURE 3
va009039 0:b7d6879637a8 30 #define SET_ADDRESS 5
va009039 0:b7d6879637a8 31 #define GET_DESCRIPTOR 6
va009039 0:b7d6879637a8 32 #define SET_CONFIGURATION 9
va009039 0:b7d6879637a8 33 #define SET_INTERFACE 11
va009039 3:ae77d63a1eda 34
va009039 3:ae77d63a1eda 35 #pragma pack(push,1)
va009039 3:ae77d63a1eda 36 typedef struct { // offset
va009039 3:ae77d63a1eda 37 uint8_t bLength; // +0
va009039 3:ae77d63a1eda 38 uint8_t bDescriptorType; // +1
va009039 3:ae77d63a1eda 39 uint16_t bcdUSB; // +2
va009039 3:ae77d63a1eda 40 uint8_t bDeviceClass; // +4
va009039 3:ae77d63a1eda 41 uint8_t bDeviceSubClass; // +5
va009039 3:ae77d63a1eda 42 uint8_t bDeviceProtocol; // +6
va009039 3:ae77d63a1eda 43 uint8_t bMaxPacketSize; // +7
va009039 3:ae77d63a1eda 44 uint16_t idVendor; // +8
va009039 3:ae77d63a1eda 45 uint16_t idProduct; // +10
va009039 3:ae77d63a1eda 46 uint16_t bcdDevice; // +12
va009039 3:ae77d63a1eda 47 uint8_t iManufacturer; // +14
va009039 3:ae77d63a1eda 48 uint8_t iProduct; // +15
va009039 3:ae77d63a1eda 49 uint8_t iSerialNumber; // +16
va009039 3:ae77d63a1eda 50 uint8_t bNumConfigurations; // +17
va009039 3:ae77d63a1eda 51 } StandardDeviceDescriptor; // +18
va009039 3:ae77d63a1eda 52
va009039 3:ae77d63a1eda 53 typedef struct { // offset
va009039 3:ae77d63a1eda 54 uint8_t bLength; // +0
va009039 3:ae77d63a1eda 55 uint8_t bDescriptorType; // +1
va009039 3:ae77d63a1eda 56 uint16_t wTotalLength; // +2
va009039 3:ae77d63a1eda 57 uint8_t bNumInterfaces; // +4
va009039 3:ae77d63a1eda 58 uint8_t bConfigurationValue; // +5
va009039 3:ae77d63a1eda 59 uint8_t iConfiguration; // +6
va009039 3:ae77d63a1eda 60 uint8_t bmAttributes; // +7
va009039 3:ae77d63a1eda 61 uint8_t bMaxPower; // +8
va009039 3:ae77d63a1eda 62 } StandardConfigurationDescriptor; // +9
va009039 3:ae77d63a1eda 63
va009039 3:ae77d63a1eda 64 typedef struct { // offset
va009039 3:ae77d63a1eda 65 uint8_t bLength; // +0
va009039 3:ae77d63a1eda 66 uint8_t bDescriptorType; // +1
va009039 3:ae77d63a1eda 67 uint8_t bInterfaceNumber; // +2
va009039 3:ae77d63a1eda 68 uint8_t bAlternateSetting; // +3
va009039 3:ae77d63a1eda 69 uint8_t bNumEndpoints; // +4
va009039 3:ae77d63a1eda 70 uint8_t bInterfaceClass; // +5
va009039 3:ae77d63a1eda 71 uint8_t bInterfaceSubClass;// +6
va009039 3:ae77d63a1eda 72 uint8_t bInterfaceProtocol;// +7
va009039 3:ae77d63a1eda 73 uint8_t iInterface; // +8
va009039 3:ae77d63a1eda 74 } StandardInterfaceDescriptor; // +9
va009039 3:ae77d63a1eda 75
va009039 3:ae77d63a1eda 76 typedef struct { // offset
va009039 3:ae77d63a1eda 77 uint8_t bLength; // +0
va009039 3:ae77d63a1eda 78 uint8_t bDescriptorType; // +1
va009039 3:ae77d63a1eda 79 uint8_t bEndpointAddress; // +2
va009039 3:ae77d63a1eda 80 uint8_t bmAttributes; // +3
va009039 3:ae77d63a1eda 81 uint16_t wMaxPacketSize; // +4
va009039 3:ae77d63a1eda 82 uint8_t bInterval; // +6
va009039 3:ae77d63a1eda 83 } StandardEndpointDescriptor; // +7
va009039 3:ae77d63a1eda 84
va009039 3:ae77d63a1eda 85 typedef struct { // offset
va009039 3:ae77d63a1eda 86 uint8_t bDescLength; // +0
va009039 3:ae77d63a1eda 87 uint8_t bDescriptorType; // +1
va009039 3:ae77d63a1eda 88 uint8_t bNbrPorts; // +2
va009039 3:ae77d63a1eda 89 uint16_t wHubCharacteristics;// +3
va009039 3:ae77d63a1eda 90 uint8_t bPwrOn2PwrGood; // +5
va009039 3:ae77d63a1eda 91 uint8_t bHubContrCurrent; // +6
va009039 3:ae77d63a1eda 92 uint8_t DeviceRemovable; // +7
va009039 3:ae77d63a1eda 93 uint8_t PortPweCtrlMak; // +8
va009039 3:ae77d63a1eda 94 } HubDescriptor; // +9
va009039 3:ae77d63a1eda 95 #pragma pack(pop)
va009039 3:ae77d63a1eda 96
va009039 0:b7d6879637a8 97 // ------------------ HcControl Register ---------------------
va009039 0:b7d6879637a8 98 #define OR_CONTROL_PLE 0x00000004
va009039 0:b7d6879637a8 99 #define OR_CONTROL_IE 0x00000008
va009039 0:b7d6879637a8 100 #define OR_CONTROL_CLE 0x00000010
va009039 0:b7d6879637a8 101 #define OR_CONTROL_BLE 0x00000020
va009039 0:b7d6879637a8 102 #define OR_CONTROL_HCFS 0x000000C0
va009039 0:b7d6879637a8 103 #define OR_CONTROL_HC_OPER 0x00000080
va009039 0:b7d6879637a8 104 // ----------------- HcCommandStatus Register -----------------
va009039 0:b7d6879637a8 105 #define OR_CMD_STATUS_HCR 0x00000001
va009039 0:b7d6879637a8 106 #define OR_CMD_STATUS_CLF 0x00000002
va009039 0:b7d6879637a8 107 #define OR_CMD_STATUS_BLF 0x00000004
va009039 0:b7d6879637a8 108 // --------------- HcInterruptStatus Register -----------------
va009039 0:b7d6879637a8 109 #define OR_INTR_STATUS_WDH 0x00000002
va009039 0:b7d6879637a8 110 #define OR_INTR_STATUS_UE 0x00000010
va009039 0:b7d6879637a8 111 #define OR_INTR_STATUS_FNO 0x00000020
va009039 0:b7d6879637a8 112 #define OR_INTR_STATUS_RHSC 0x00000040
va009039 0:b7d6879637a8 113 // --------------- HcInterruptEnable Register -----------------
va009039 0:b7d6879637a8 114 #define OR_INTR_ENABLE_WDH 0x00000002
va009039 0:b7d6879637a8 115 #define OR_INTR_ENABLE_FNO 0x00000020
va009039 0:b7d6879637a8 116 #define OR_INTR_ENABLE_RHSC 0x00000040
va009039 0:b7d6879637a8 117 #define OR_INTR_ENABLE_MIE 0x80000000
va009039 0:b7d6879637a8 118 // ---------------- HcRhDescriptorA Register ------------------
va009039 0:b7d6879637a8 119 #define OR_RH_STATUS_LPSC 0x00010000
va009039 0:b7d6879637a8 120 #define OR_RH_STATUS_DRWE 0x00008000
va009039 0:b7d6879637a8 121 // -------------- HcRhPortStatus[1:NDP] Register --------------
va009039 0:b7d6879637a8 122 #define OR_RH_PORT_CCS 0x00000001
va009039 0:b7d6879637a8 123 #define OR_RH_PORT_PRS 0x00000010
va009039 0:b7d6879637a8 124 #define OR_RH_PORT_CSC 0x00010000
va009039 0:b7d6879637a8 125 #define OR_RH_PORT_PRSC 0x00100000
va009039 0:b7d6879637a8 126
va009039 0:b7d6879637a8 127 // TRANSFER DESCRIPTOR CONTROL FIELDS
va009039 0:b7d6879637a8 128 #define TD_ROUNDING (uint32_t)(0x00040000) /* Buffer Rounding */
va009039 0:b7d6879637a8 129 #define TD_SETUP (uint32_t)(0x00000000) /* Direction of Setup Packet */
va009039 0:b7d6879637a8 130 #define TD_IN (uint32_t)(0x00100000) /* Direction In */
va009039 0:b7d6879637a8 131 #define TD_OUT (uint32_t)(0x00080000) /* Direction Out */
va009039 0:b7d6879637a8 132 #define TD_DELAY_INT(x) (uint32_t)((x) << 21) /* Delay Interrupt */
va009039 0:b7d6879637a8 133 #define TD_DI (uint32_t)(7<<21) /* desable interrupt */
va009039 0:b7d6879637a8 134 #define TD_TOGGLE_0 (uint32_t)(0x02000000) /* Toggle 0 */
va009039 0:b7d6879637a8 135 #define TD_TOGGLE_1 (uint32_t)(0x03000000) /* Toggle 1 */
va009039 0:b7d6879637a8 136 #define TD_CC (uint32_t)(0xF0000000) /* Completion Code */
va009039 0:b7d6879637a8 137
va009039 0:b7d6879637a8 138 typedef struct { // Host Controller Communication Area
va009039 0:b7d6879637a8 139 uint32_t InterruptTable[32]; // Interrupt Table
va009039 0:b7d6879637a8 140 __IO uint16_t FrameNumber; // Frame Number
va009039 0:b7d6879637a8 141 __IO uint16_t Pad1;
va009039 0:b7d6879637a8 142 __IO uint32_t DoneHead; // Done Head
va009039 0:b7d6879637a8 143 uint8_t Reserved[116]; // Reserved for future use
va009039 0:b7d6879637a8 144 uint8_t Unknown[4]; // Unused
va009039 0:b7d6879637a8 145 } HCCA;
va009039 0:b7d6879637a8 146
va009039 0:b7d6879637a8 147 typedef struct { // HostController Transfer Descriptor
va009039 0:b7d6879637a8 148 __IO uint32_t Control; // +0 Transfer descriptor control
va009039 0:b7d6879637a8 149 __IO uint8_t* CurrBufPtr; // +4 Physical address of current buffer pointer
va009039 0:b7d6879637a8 150 __IO uint32_t Next; // +8 Physical pointer to next Transfer Descriptor
va009039 0:b7d6879637a8 151 uint8_t* BufEnd; // +12 Physical address of end of buffer
va009039 0:b7d6879637a8 152 uint8_t* buf_top; // +16 Buffer start address
va009039 0:b7d6879637a8 153 uint16_t buf_size; // +20 buffer size size
va009039 0:b7d6879637a8 154 uint8_t setup[8]; // +22 setup cmd area
va009039 0:b7d6879637a8 155 uint8_t _dummy[2]; // +30 dummy
va009039 0:b7d6879637a8 156 void *ep; // +32 endpoint object
va009039 0:b7d6879637a8 157 __IO uint8_t buf[0]; // +36 buffer
va009039 0:b7d6879637a8 158 } HCTD; // +36
va009039 0:b7d6879637a8 159
va009039 0:b7d6879637a8 160 typedef struct { // HostController Isochronous Transfer Descriptor
va009039 0:b7d6879637a8 161 __IO uint32_t Control; // +0 Transfer descriptor control
va009039 0:b7d6879637a8 162 uint8_t* BufferPage0; // +4 Buffer Page 0
va009039 0:b7d6879637a8 163 __IO uint32_t Next; // +8 Physical pointer to next Transfer Descriptor
va009039 0:b7d6879637a8 164 uint8_t* BufferEnd; // +12 buffer End
va009039 0:b7d6879637a8 165 __IO uint16_t OffsetPSW[8]; // +16 Offset/PSW
va009039 0:b7d6879637a8 166 void *ep; // +32 endpoint object
va009039 0:b7d6879637a8 167 __IO uint8_t buf[0]; // +36 buffer
va009039 0:b7d6879637a8 168 } HCITD; // +36
va009039 0:b7d6879637a8 169
va009039 0:b7d6879637a8 170 typedef struct { // HostController EndPoint Descriptor
va009039 0:b7d6879637a8 171 __IO uint32_t Control; // +0 Endpoint descriptor control
va009039 0:b7d6879637a8 172 HCTD* TailTd; // +4 Physical address of tail in Transfer descriptor list
va009039 0:b7d6879637a8 173 __IO HCTD* HeadTd; // +8 Physcial address of head in Transfer descriptor list
va009039 0:b7d6879637a8 174 uint32_t Next; // +12 Physical address of next Endpoint descriptor
va009039 0:b7d6879637a8 175 } HCED;
va009039 0:b7d6879637a8 176
va009039 0:b7d6879637a8 177 class BaseUsbHost {
va009039 0:b7d6879637a8 178 public:
va009039 0:b7d6879637a8 179 BaseUsbHost();
va009039 0:b7d6879637a8 180 void irqHandler();
va009039 0:b7d6879637a8 181 // report
va009039 0:b7d6879637a8 182 uint32_t m_report_irq;
va009039 0:b7d6879637a8 183 uint32_t m_report_RHSC;
va009039 0:b7d6879637a8 184 uint32_t m_report_FNO;
va009039 0:b7d6879637a8 185 uint32_t m_report_WDH;
va009039 0:b7d6879637a8 186 uint32_t m_report_sp;
va009039 3:ae77d63a1eda 187 private:
va009039 3:ae77d63a1eda 188 void init_hw_ohci(HCCA* pHcca);
va009039 3:ae77d63a1eda 189 void ResetRootHub();
va009039 3:ae77d63a1eda 190 HCCA* m_pHcca;
va009039 0:b7d6879637a8 191 };
va009039 0:b7d6879637a8 192
va009039 0:b7d6879637a8 193 #define HCTD_QUEUE_SIZE 3
va009039 0:b7d6879637a8 194
va009039 0:b7d6879637a8 195 class BaseEp { // endpoint
va009039 0:b7d6879637a8 196 public:
va009039 0:b7d6879637a8 197 BaseEp(int addr, uint8_t ep = 0, uint16_t size = 8, int lowSpeed = 0);
va009039 0:b7d6879637a8 198 int GetAddr();
va009039 0:b7d6879637a8 199 int GetLowSpeed();
va009039 0:b7d6879637a8 200 void update_FunctionAddress(int addr);
va009039 0:b7d6879637a8 201 void update_MaxPacketSize(uint16_t size);
va009039 3:ae77d63a1eda 202 int transfer(uint8_t* buf, int len);
va009039 3:ae77d63a1eda 203 int status(uint32_t millisec=osWaitForever);
va009039 0:b7d6879637a8 204 //
va009039 3:ae77d63a1eda 205 virtual void enable() = 0;
va009039 0:b7d6879637a8 206 HCTD* new_HCTD(int buf_size=0);
va009039 0:b7d6879637a8 207 void delete_HCTD(HCTD* p);
va009039 3:ae77d63a1eda 208 virtual void irqWdhHandler(HCTD* td) {m_queue.put(td);} // WDH
va009039 0:b7d6879637a8 209 int wait_queue_HCTD(HCTD* wait_td, uint32_t millisec=osWaitForever);
va009039 0:b7d6879637a8 210 // report
va009039 0:b7d6879637a8 211 uint8_t m_ConditionCode;
va009039 0:b7d6879637a8 212 int m_report_queue_error;
va009039 3:ae77d63a1eda 213 protected:
va009039 3:ae77d63a1eda 214 int send_receive(uint8_t* buf, int len, int millisec);
va009039 3:ae77d63a1eda 215 HCTD* get_queue_HCTD(uint32_t millisec=osWaitForever);
va009039 3:ae77d63a1eda 216 HCED* m_pED;
va009039 3:ae77d63a1eda 217 Queue<HCTD, HCTD_QUEUE_SIZE> m_queue; // TD done queue
va009039 3:ae77d63a1eda 218 int m_td_queue_count;
va009039 0:b7d6879637a8 219 };
va009039 0:b7d6879637a8 220
va009039 0:b7d6879637a8 221 class ControlEp : public BaseEp {
va009039 0:b7d6879637a8 222 public:
va009039 0:b7d6879637a8 223 ControlEp(int lowSpeed = 0);
va009039 0:b7d6879637a8 224 int GetDescriptor(int descType, int descIndex, uint8_t* data, int length);
va009039 0:b7d6879637a8 225 int SetAddress(int addr); // device address
va009039 0:b7d6879637a8 226 int SetConfiguration(int config);
va009039 0:b7d6879637a8 227 int GetConfiguration(int *config);
va009039 0:b7d6879637a8 228 int SetInterfaceAlternate(int interface, int alternate);
va009039 0:b7d6879637a8 229 int GetInterface(int interface, int *alternate);
va009039 0:b7d6879637a8 230 int controlSend(uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex=0, const uint8_t* data=NULL, int length=0);
va009039 0:b7d6879637a8 231 int controlReceive(uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint8_t* data, int length);
va009039 3:ae77d63a1eda 232 private:
va009039 0:b7d6879637a8 233 int open(int addr);
va009039 0:b7d6879637a8 234 void setup(HCTD* td, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex=0, uint16_t wLength=0);
va009039 3:ae77d63a1eda 235 virtual void enable(){};
va009039 0:b7d6879637a8 236 };
va009039 0:b7d6879637a8 237
va009039 0:b7d6879637a8 238 class BulkEp : public BaseEp {
va009039 0:b7d6879637a8 239 public:
va009039 0:b7d6879637a8 240 BulkEp(int addr, uint8_t ep, uint16_t size);
va009039 1:3b7bc4f87a61 241 int bulkSend(const uint8_t* buf, int len, int millisec=osWaitForever);
va009039 1:3b7bc4f87a61 242 int bulkReceive(uint8_t* buf, int len, int millisec=osWaitForever);
va009039 3:ae77d63a1eda 243 private:
va009039 3:ae77d63a1eda 244 virtual void enable();
va009039 0:b7d6879637a8 245 };
va009039 0:b7d6879637a8 246
va009039 0:b7d6879637a8 247 class InterruptEp : public BaseEp {
va009039 0:b7d6879637a8 248 public:
va009039 0:b7d6879637a8 249 InterruptEp(int addr, uint8_t ep, uint16_t size, int lowSpeed=0);
va009039 1:3b7bc4f87a61 250 int interruptReceive(uint8_t* buf, int len, int millisec=osWaitForever);
va009039 3:ae77d63a1eda 251 private:
va009039 3:ae77d63a1eda 252 virtual void enable();
va009039 0:b7d6879637a8 253 };
va009039 0:b7d6879637a8 254
va009039 0:b7d6879637a8 255 class IsochronousEp : public BaseEp {
va009039 0:b7d6879637a8 256 public:
va009039 0:b7d6879637a8 257 IsochronousEp(int addr, uint8_t ep, uint16_t size);
va009039 3:ae77d63a1eda 258 void reset(int delay_ms = 100);
va009039 2:fe1e62051d88 259 HCITD* isochronousReveive(int millisec=osWaitForever);
va009039 2:fe1e62051d88 260 int isochronousSend(uint8_t* buf, int len, int millisec=osWaitForever);
va009039 3:ae77d63a1eda 261 HCITD* get_queue_HCITD(int millisec);
va009039 3:ae77d63a1eda 262 int m_PacketSize; // 128,192
va009039 3:ae77d63a1eda 263 private:
va009039 0:b7d6879637a8 264 HCITD* new_HCITD();
va009039 0:b7d6879637a8 265 int m_itd_queue_count;
va009039 0:b7d6879637a8 266 uint16_t m_FrameNumber;
va009039 0:b7d6879637a8 267 int m_FrameCount; // 1-8
va009039 3:ae77d63a1eda 268 virtual void enable();
va009039 0:b7d6879637a8 269 };
va009039 0:b7d6879637a8 270
va009039 1:3b7bc4f87a61 271 // --- HUB --------------------------------------------------
va009039 0:b7d6879637a8 272 class UsbHub {
va009039 0:b7d6879637a8 273 public:
va009039 0:b7d6879637a8 274 UsbHub(ControlEp* ctlEp = NULL);
va009039 3:ae77d63a1eda 275 static bool check(ControlEp* ctlEp);
va009039 2:fe1e62051d88 276 int SetPortPower(int port);
va009039 2:fe1e62051d88 277 int ClearPortPower(int port);
va009039 3:ae77d63a1eda 278 vector<ControlEp*> PortEp;
va009039 3:ae77d63a1eda 279 private:
va009039 0:b7d6879637a8 280 int PortReset(int port);
va009039 0:b7d6879637a8 281 int SetPortFeature(int feature, int index);
va009039 0:b7d6879637a8 282 int ClearPortFeature(int feature, int index);
va009039 0:b7d6879637a8 283 int SetPortReset(int port);
va009039 0:b7d6879637a8 284 int GetPortStatus(int port, uint32_t* status);
va009039 0:b7d6879637a8 285 ControlEp* m_ctlEp;
va009039 0:b7d6879637a8 286 };
va009039 0:b7d6879637a8 287
va009039 1:3b7bc4f87a61 288 // --- UVC --------------------------------------------------
va009039 1:3b7bc4f87a61 289 #define _30FPS 333333
va009039 1:3b7bc4f87a61 290 #define _25FPS 400000
va009039 1:3b7bc4f87a61 291 #define _20FPS 500000
va009039 1:3b7bc4f87a61 292 #define _15FPS 666666
va009039 1:3b7bc4f87a61 293 #define _10FPS 1000000
va009039 1:3b7bc4f87a61 294 #define _5FPS 2000000
va009039 1:3b7bc4f87a61 295 #define _1FPS 10000000
va009039 1:3b7bc4f87a61 296
va009039 1:3b7bc4f87a61 297 #define SET_CUR 0x01
va009039 1:3b7bc4f87a61 298 #define GET_CUR 0x81
va009039 1:3b7bc4f87a61 299 #define GET_MIN 0x82
va009039 1:3b7bc4f87a61 300 #define GET_MAX 0x83
va009039 1:3b7bc4f87a61 301 #define GET_RES 0x84
va009039 1:3b7bc4f87a61 302 #define GET_LEN 0x85
va009039 1:3b7bc4f87a61 303 #define GET_INFO 0x86
va009039 1:3b7bc4f87a61 304 #define GET_DEF 0x87
va009039 1:3b7bc4f87a61 305
va009039 1:3b7bc4f87a61 306 #define VS_PROBE_CONTROL 0x01
va009039 1:3b7bc4f87a61 307 #define VS_COMMIT_CONTROL 0x02
va009039 1:3b7bc4f87a61 308
va009039 1:3b7bc4f87a61 309 class BaseUvc {
va009039 1:3b7bc4f87a61 310 public:
va009039 2:fe1e62051d88 311 void poll(int millisec=osWaitForever);
va009039 1:3b7bc4f87a61 312 int Control(int req, int cs, int index, uint8_t* buf, int size);
va009039 1:3b7bc4f87a61 313 ControlEp* m_ctlEp;
va009039 1:3b7bc4f87a61 314 IsochronousEp* m_isoEp;
va009039 1:3b7bc4f87a61 315 uint32_t report_cc_count[16]; // ConditionCode
va009039 1:3b7bc4f87a61 316 uint32_t report_ps_cc_count[16]; // Packt Status ConditionCode
va009039 1:3b7bc4f87a61 317 // callback
va009039 1:3b7bc4f87a61 318 void onResult(uint16_t frame, uint8_t* buf, int len);
va009039 1:3b7bc4f87a61 319 void setOnResult( void (*pMethod)(uint16_t, uint8_t*, int) );
va009039 1:3b7bc4f87a61 320 class CDummy;
va009039 1:3b7bc4f87a61 321 template<class T>
va009039 1:3b7bc4f87a61 322 void setOnResult( T* pItem, void (T::*pMethod)(uint16_t, uint8_t*, int) )
va009039 1:3b7bc4f87a61 323 {
va009039 1:3b7bc4f87a61 324 m_pCb = NULL;
va009039 1:3b7bc4f87a61 325 m_pCbItem = (CDummy*) pItem;
va009039 1:3b7bc4f87a61 326 m_pCbMeth = (void (CDummy::*)(uint16_t, uint8_t*, int)) pMethod;
va009039 1:3b7bc4f87a61 327 }
va009039 1:3b7bc4f87a61 328 void clearOnResult();
va009039 1:3b7bc4f87a61 329 CDummy* m_pCbItem;
va009039 1:3b7bc4f87a61 330 void (CDummy::*m_pCbMeth)(uint16_t, uint8_t*, int);
va009039 1:3b7bc4f87a61 331 void (*m_pCb)(uint16_t, uint8_t*, int);
va009039 1:3b7bc4f87a61 332 };