Anand vaidyanathan / Mbed OS Racket_VibrAnalyzer

Tennis Racket Vibration Analyzer

Dependencies:   Hexi_KW40Z Hexi_OLED_SSD1351

FXOS8700CQ.h@0:f9598a5afb72, 2016-10-02 (annotated)

Committer:
v_anand_786
Date:
Sun Oct 02 16:08:43 2016 -0400
Revision:
0:f9598a5afb72
Initial Version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
v_anand_786 0:f9598a5afb72 1 #ifndef _HEXIWEAR_FXOS8700CQ_H_
v_anand_786 0:f9598a5afb72 2 #define _HEXIWEAR_FXOS8700CQ_H_
v_anand_786 0:f9598a5afb72 3
v_anand_786 0:f9598a5afb72 4 #include "mbed.h"
v_anand_786 0:f9598a5afb72 5
v_anand_786 0:f9598a5afb72 6 #define I2C_SLAVE_ADDR1 (0x1E<<1)
v_anand_786 0:f9598a5afb72 7 #define I2C_SUCCESS 0x00
v_anand_786 0:f9598a5afb72 8 #define I2C_ERROR 0xff
v_anand_786 0:f9598a5afb72 9
v_anand_786 0:f9598a5afb72 10 #define UINT14_MAX 16383
v_anand_786 0:f9598a5afb72 11
v_anand_786 0:f9598a5afb72 12 #define FXOS8700CQ_STATUS 0x00
v_anand_786 0:f9598a5afb72 13 #define FXOS8700CQ_OUT_X_MSB 0x01
v_anand_786 0:f9598a5afb72 14 #define FXOS8700CQ_WHOAMI 0x0D
v_anand_786 0:f9598a5afb72 15
v_anand_786 0:f9598a5afb72 16 #define FXOS8700CQ_CTRL_REG1 0x2A
v_anand_786 0:f9598a5afb72 17 #define FXOS8700CQ_CTRL_REG2 0x2B
v_anand_786 0:f9598a5afb72 18 #define FXOS8700CQ_CTRL_REG3 0x2C
v_anand_786 0:f9598a5afb72 19 #define FXOS8700CQ_CTRL_REG4 0x2D
v_anand_786 0:f9598a5afb72 20 #define FXOS8700CQ_CTRL_REG5 0x2E
v_anand_786 0:f9598a5afb72 21
v_anand_786 0:f9598a5afb72 22 #define FXOS8700CQ_TRANSIENT_CFG 0x1D
v_anand_786 0:f9598a5afb72 23 #define FXOS8700CQ_TRANSIENT_SRC 0x1E
v_anand_786 0:f9598a5afb72 24 #define FXOS8700CQ_TRANSIENT_THS 0x1F
v_anand_786 0:f9598a5afb72 25 #define FXOS8700CQ_TRANSIENT_CNT 0x20
v_anand_786 0:f9598a5afb72 26
v_anand_786 0:f9598a5afb72 27 #define FXOS8700CQ_M_THS_COUNT 0x5A
v_anand_786 0:f9598a5afb72 28 #define FXOS8700CQ_M_CTRL_REG1 0x5B
v_anand_786 0:f9598a5afb72 29 #define FXOS8700CQ_M_CTRL_REG2 0x5C
v_anand_786 0:f9598a5afb72 30
v_anand_786 0:f9598a5afb72 31 typedef struct
v_anand_786 0:f9598a5afb72 32 {
v_anand_786 0:f9598a5afb72 33 int16_t x;
v_anand_786 0:f9598a5afb72 34 int16_t y;
v_anand_786 0:f9598a5afb72 35 int16_t z;
v_anand_786 0:f9598a5afb72 36 } SRAWDATA;
v_anand_786 0:f9598a5afb72 37
v_anand_786 0:f9598a5afb72 38 class FXOS8700CQ
v_anand_786 0:f9598a5afb72 39 {
v_anand_786 0:f9598a5afb72 40 I2C i2cAcc;
v_anand_786 0:f9598a5afb72 41
v_anand_786 0:f9598a5afb72 42 void write_regs(char* d, uint8_t len)
v_anand_786 0:f9598a5afb72 43 {
v_anand_786 0:f9598a5afb72 44 i2cAcc.write(I2C_SLAVE_ADDR1, d, 2);
v_anand_786 0:f9598a5afb72 45 }
v_anand_786 0:f9598a5afb72 46 void read_regs(uint8_t reg_addr, char* data, int len)
v_anand_786 0:f9598a5afb72 47 {
v_anand_786 0:f9598a5afb72 48 char t[1] = {reg_addr};
v_anand_786 0:f9598a5afb72 49 i2cAcc.write(I2C_SLAVE_ADDR1, t, 1, true);
v_anand_786 0:f9598a5afb72 50 i2cAcc.read(I2C_SLAVE_ADDR1, data, len);
v_anand_786 0:f9598a5afb72 51 }
v_anand_786 0:f9598a5afb72 52
v_anand_786 0:f9598a5afb72 53 void soft_reset()
v_anand_786 0:f9598a5afb72 54 {
v_anand_786 0:f9598a5afb72 55 /* soft reset */
v_anand_786 0:f9598a5afb72 56 char d[2] = {FXOS8700CQ_CTRL_REG2, 0x40};
v_anand_786 0:f9598a5afb72 57 write_regs(d, 2);
v_anand_786 0:f9598a5afb72 58 wait_ms(100);
v_anand_786 0:f9598a5afb72 59 }
v_anand_786 0:f9598a5afb72 60 void set_trans_ths()
v_anand_786 0:f9598a5afb72 61 {
v_anand_786 0:f9598a5afb72 62 /* TRANSIENT_THS: debounce = clear when cond not true; resolution = 63mg x 5*/
v_anand_786 0:f9598a5afb72 63 char d[2] = {FXOS8700CQ_TRANSIENT_THS, 0x85};
v_anand_786 0:f9598a5afb72 64 write_regs(d, 2);
v_anand_786 0:f9598a5afb72 65 }
v_anand_786 0:f9598a5afb72 66 void set_trans_count()
v_anand_786 0:f9598a5afb72 67 {
v_anand_786 0:f9598a5afb72 68 /* TRANSIENT_COUNT: min num of debounce counts = 80ms*/
v_anand_786 0:f9598a5afb72 69 char d[2] = {FXOS8700CQ_TRANSIENT_CNT, 0x02};
v_anand_786 0:f9598a5afb72 70 write_regs(d, 2);
v_anand_786 0:f9598a5afb72 71 }
v_anand_786 0:f9598a5afb72 72 void init_tran_msb()
v_anand_786 0:f9598a5afb72 73 {
v_anand_786 0:f9598a5afb72 74 /* A_TRAN_INIT_MSB: init ref to 0g for all axes */
v_anand_786 0:f9598a5afb72 75 char d1[2] = {0x79, 0x00};
v_anand_786 0:f9598a5afb72 76 write_regs(d1, 2);
v_anand_786 0:f9598a5afb72 77
v_anand_786 0:f9598a5afb72 78 char d2[2] = {0x7A, 0x00};
v_anand_786 0:f9598a5afb72 79 write_regs(d2, 2);
v_anand_786 0:f9598a5afb72 80
v_anand_786 0:f9598a5afb72 81 char d3[2] = {0x7B, 0x00};
v_anand_786 0:f9598a5afb72 82 write_regs(d3, 2);
v_anand_786 0:f9598a5afb72 83
v_anand_786 0:f9598a5afb72 84 char d4[2] = {0x7C, 0x00};
v_anand_786 0:f9598a5afb72 85 write_regs(d4, 2);
v_anand_786 0:f9598a5afb72 86 }
v_anand_786 0:f9598a5afb72 87 void set_trans_cfg()
v_anand_786 0:f9598a5afb72 88 {
v_anand_786 0:f9598a5afb72 89 /* TRANSIENT_CFG: evt latch, no Z-axis, Y-axis, X-axis, HPF */
v_anand_786 0:f9598a5afb72 90 char d[2] = {FXOS8700CQ_TRANSIENT_CFG, 0x16};
v_anand_786 0:f9598a5afb72 91 write_regs(d, 2);
v_anand_786 0:f9598a5afb72 92 }
v_anand_786 0:f9598a5afb72 93 void enable_int()
v_anand_786 0:f9598a5afb72 94 {
v_anand_786 0:f9598a5afb72 95 /* Enable interrupts using CTRL_REG4 */
v_anand_786 0:f9598a5afb72 96 char d[2] = {FXOS8700CQ_CTRL_REG4, 0x20};
v_anand_786 0:f9598a5afb72 97 write_regs(d, 2);
v_anand_786 0:f9598a5afb72 98 }
v_anand_786 0:f9598a5afb72 99 void route_int()
v_anand_786 0:f9598a5afb72 100 {
v_anand_786 0:f9598a5afb72 101 /* Route interrupts to INT1 using CTRL_REG5 */
v_anand_786 0:f9598a5afb72 102 char d[2] = {FXOS8700CQ_CTRL_REG5, 0x20};
v_anand_786 0:f9598a5afb72 103 write_regs(d, 2);
v_anand_786 0:f9598a5afb72 104 }
v_anand_786 0:f9598a5afb72 105 void set_hybrid()
v_anand_786 0:f9598a5afb72 106 {
v_anand_786 0:f9598a5afb72 107 /* Setup device for hybrid mode, enable hybrid mode, auto-inc, ODR=50Hz OSR=32 */
v_anand_786 0:f9598a5afb72 108 char d1[2] = {FXOS8700CQ_M_CTRL_REG1, 0x1F};
v_anand_786 0:f9598a5afb72 109 write_regs(d1, 2);
v_anand_786 0:f9598a5afb72 110
v_anand_786 0:f9598a5afb72 111 char d2[2] = {FXOS8700CQ_M_CTRL_REG2, 0x20};
v_anand_786 0:f9598a5afb72 112 write_regs(d2, 2);
v_anand_786 0:f9598a5afb72 113
v_anand_786 0:f9598a5afb72 114 char d3[2] = {FXOS8700CQ_CTRL_REG1, 0x19};
v_anand_786 0:f9598a5afb72 115 write_regs(d3, 2);
v_anand_786 0:f9598a5afb72 116 }
v_anand_786 0:f9598a5afb72 117
v_anand_786 0:f9598a5afb72 118 public:
v_anand_786 0:f9598a5afb72 119
v_anand_786 0:f9598a5afb72 120 FXOS8700CQ(PinName sda, PinName scl)
v_anand_786 0:f9598a5afb72 121 : i2cAcc(sda, scl)
v_anand_786 0:f9598a5afb72 122 {
v_anand_786 0:f9598a5afb72 123 }
v_anand_786 0:f9598a5afb72 124
v_anand_786 0:f9598a5afb72 125 /* AN4461 */
v_anand_786 0:f9598a5afb72 126 void enable_trans_accel()
v_anand_786 0:f9598a5afb72 127 {
v_anand_786 0:f9598a5afb72 128 soft_reset();
v_anand_786 0:f9598a5afb72 129 set_trans_ths();
v_anand_786 0:f9598a5afb72 130 set_trans_count();
v_anand_786 0:f9598a5afb72 131 init_tran_msb();
v_anand_786 0:f9598a5afb72 132 set_trans_cfg();
v_anand_786 0:f9598a5afb72 133 enable_int();
v_anand_786 0:f9598a5afb72 134 route_int();
v_anand_786 0:f9598a5afb72 135 set_hybrid();
v_anand_786 0:f9598a5afb72 136 }
v_anand_786 0:f9598a5afb72 137 int read_accel(SRAWDATA* accelData)
v_anand_786 0:f9598a5afb72 138 {
v_anand_786 0:f9598a5afb72 139 uint8_t d[1];
v_anand_786 0:f9598a5afb72 140 read_regs(FXOS8700CQ_TRANSIENT_SRC, (char*)d, 1);
v_anand_786 0:f9598a5afb72 141 if (0x40 == (d[0] & 0x40)) {
v_anand_786 0:f9598a5afb72 142 uint8_t acc[6];
v_anand_786 0:f9598a5afb72 143 read_regs(FXOS8700CQ_OUT_X_MSB, (char*)acc, 6);
v_anand_786 0:f9598a5afb72 144 accelData->x = ((acc[0]<<8)|(acc[1]))>>2;
v_anand_786 0:f9598a5afb72 145 accelData->y = ((acc[2]<<8)|(acc[3]))>>2;
v_anand_786 0:f9598a5afb72 146 accelData->z = ((acc[4]<<8)|(acc[5]))>>2;
v_anand_786 0:f9598a5afb72 147 return I2C_SUCCESS;
v_anand_786 0:f9598a5afb72 148 }
v_anand_786 0:f9598a5afb72 149 return I2C_ERROR;
v_anand_786 0:f9598a5afb72 150 }
v_anand_786 0:f9598a5afb72 151 void display_status(Serial* pc)
v_anand_786 0:f9598a5afb72 152 {
v_anand_786 0:f9598a5afb72 153 pc->printf( "\r\n\nFXOS8700CQ Who Am I= %X Status = %X\r\n",
v_anand_786 0:f9598a5afb72 154 who_am_i(),
v_anand_786 0:f9598a5afb72 155 status());
v_anand_786 0:f9598a5afb72 156 }
v_anand_786 0:f9598a5afb72 157 uint8_t status()
v_anand_786 0:f9598a5afb72 158 {
v_anand_786 0:f9598a5afb72 159 return 0;
v_anand_786 0:f9598a5afb72 160 }
v_anand_786 0:f9598a5afb72 161 uint8_t who_am_i()
v_anand_786 0:f9598a5afb72 162 {
v_anand_786 0:f9598a5afb72 163 return 0;
v_anand_786 0:f9598a5afb72 164 }
v_anand_786 0:f9598a5afb72 165 };
v_anand_786 0:f9598a5afb72 166
v_anand_786 0:f9598a5afb72 167 #endif /* _HEXIWEAR_FXOS8700CQ_H_ */