S K UCI / SDFileSystemFilinfo

Example SDFileSystem in which FATDirHandle exposes the file info struct of the current file/directory.

SDFileSystem.cpp@1:a7d8fc28a863, 2014-11-28 (annotated)

Committer:
uci1
Date:
Fri Nov 28 05:12:38 2014 +0000
Revision:
1:a7d8fc28a863
Parent:
0:687056ba3278 
change SD init so it won't stall on failed initialization

Who changed what in which revision?

UserRevisionLine numberNew contents of line
uci1 0:687056ba3278 1 /* mbed Microcontroller Library
uci1 0:687056ba3278 2 * Copyright (c) 2006-2012 ARM Limited
uci1 0:687056ba3278 3 *
uci1 0:687056ba3278 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
uci1 0:687056ba3278 5 * of this software and associated documentation files (the "Software"), to deal
uci1 0:687056ba3278 6 * in the Software without restriction, including without limitation the rights
uci1 0:687056ba3278 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
uci1 0:687056ba3278 8 * copies of the Software, and to permit persons to whom the Software is
uci1 0:687056ba3278 9 * furnished to do so, subject to the following conditions:
uci1 0:687056ba3278 10 *
uci1 0:687056ba3278 11 * The above copyright notice and this permission notice shall be included in
uci1 0:687056ba3278 12 * all copies or substantial portions of the Software.
uci1 0:687056ba3278 13 *
uci1 0:687056ba3278 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
uci1 0:687056ba3278 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
uci1 0:687056ba3278 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
uci1 0:687056ba3278 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
uci1 0:687056ba3278 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
uci1 0:687056ba3278 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
uci1 0:687056ba3278 20 * SOFTWARE.
uci1 0:687056ba3278 21 */
uci1 1:a7d8fc28a863 22
uci1 0:687056ba3278 23 /* Introduction
uci1 0:687056ba3278 24 * ------------
uci1 0:687056ba3278 25 * SD and MMC cards support a number of interfaces, but common to them all
uci1 0:687056ba3278 26 * is one based on SPI. This is the one I'm implmenting because it means
uci1 0:687056ba3278 27 * it is much more portable even though not so performant, and we already
uci1 0:687056ba3278 28 * have the mbed SPI Interface!
uci1 0:687056ba3278 29 *
uci1 0:687056ba3278 30 * The main reference I'm using is Chapter 7, "SPI Mode" of:
uci1 0:687056ba3278 31 * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
uci1 0:687056ba3278 32 *
uci1 0:687056ba3278 33 * SPI Startup
uci1 0:687056ba3278 34 * -----------
uci1 0:687056ba3278 35 * The SD card powers up in SD mode. The SPI interface mode is selected by
uci1 0:687056ba3278 36 * asserting CS low and sending the reset command (CMD0). The card will
uci1 0:687056ba3278 37 * respond with a (R1) response.
uci1 0:687056ba3278 38 *
uci1 0:687056ba3278 39 * CMD8 is optionally sent to determine the voltage range supported, and
uci1 0:687056ba3278 40 * indirectly determine whether it is a version 1.x SD/non-SD card or
uci1 0:687056ba3278 41 * version 2.x. I'll just ignore this for now.
uci1 0:687056ba3278 42 *
uci1 0:687056ba3278 43 * ACMD41 is repeatedly issued to initialise the card, until "in idle"
uci1 0:687056ba3278 44 * (bit 0) of the R1 response goes to '0', indicating it is initialised.
uci1 0:687056ba3278 45 *
uci1 0:687056ba3278 46 * You should also indicate whether the host supports High Capicity cards,
uci1 0:687056ba3278 47 * and check whether the card is high capacity - i'll also ignore this
uci1 0:687056ba3278 48 *
uci1 0:687056ba3278 49 * SPI Protocol
uci1 0:687056ba3278 50 * ------------
uci1 0:687056ba3278 51 * The SD SPI protocol is based on transactions made up of 8-bit words, with
uci1 0:687056ba3278 52 * the host starting every bus transaction by asserting the CS signal low. The
uci1 0:687056ba3278 53 * card always responds to commands, data blocks and errors.
uci1 0:687056ba3278 54 *
uci1 0:687056ba3278 55 * The protocol supports a CRC, but by default it is off (except for the
uci1 0:687056ba3278 56 * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
uci1 0:687056ba3278 57 * I'll leave the CRC off I think!
uci1 0:687056ba3278 58 *
uci1 0:687056ba3278 59 * Standard capacity cards have variable data block sizes, whereas High
uci1 0:687056ba3278 60 * Capacity cards fix the size of data block to 512 bytes. I'll therefore
uci1 0:687056ba3278 61 * just always use the Standard Capacity cards with a block size of 512 bytes.
uci1 0:687056ba3278 62 * This is set with CMD16.
uci1 0:687056ba3278 63 *
uci1 0:687056ba3278 64 * You can read and write single blocks (CMD17, CMD25) or multiple blocks
uci1 0:687056ba3278 65 * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
uci1 0:687056ba3278 66 * the card gets a read command, it responds with a response token, and then
uci1 0:687056ba3278 67 * a data token or an error.
uci1 0:687056ba3278 68 *
uci1 0:687056ba3278 69 * SPI Command Format
uci1 0:687056ba3278 70 * ------------------
uci1 0:687056ba3278 71 * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
uci1 0:687056ba3278 72 *
uci1 0:687056ba3278 73 * +---------------+------------+------------+-----------+----------+--------------+
uci1 0:687056ba3278 74 * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
uci1 0:687056ba3278 75 * +---------------+------------+------------+-----------+----------+--------------+
uci1 0:687056ba3278 76 *
uci1 0:687056ba3278 77 * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
uci1 0:687056ba3278 78 *
uci1 0:687056ba3278 79 * All Application Specific commands shall be preceded with APP_CMD (CMD55).
uci1 0:687056ba3278 80 *
uci1 0:687056ba3278 81 * SPI Response Format
uci1 0:687056ba3278 82 * -------------------
uci1 0:687056ba3278 83 * The main response format (R1) is a status byte (normally zero). Key flags:
uci1 0:687056ba3278 84 * idle - 1 if the card is in an idle state/initialising
uci1 0:687056ba3278 85 * cmd - 1 if an illegal command code was detected
uci1 0:687056ba3278 86 *
uci1 0:687056ba3278 87 * +-------------------------------------------------+
uci1 0:687056ba3278 88 * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
uci1 0:687056ba3278 89 * +-------------------------------------------------+
uci1 0:687056ba3278 90 *
uci1 0:687056ba3278 91 * R1b is the same, except it is followed by a busy signal (zeros) until
uci1 0:687056ba3278 92 * the first non-zero byte when it is ready again.
uci1 0:687056ba3278 93 *
uci1 0:687056ba3278 94 * Data Response Token
uci1 0:687056ba3278 95 * -------------------
uci1 0:687056ba3278 96 * Every data block written to the card is acknowledged by a byte
uci1 0:687056ba3278 97 * response token
uci1 0:687056ba3278 98 *
uci1 0:687056ba3278 99 * +----------------------+
uci1 0:687056ba3278 100 * | xxx | 0 | status | 1 |
uci1 0:687056ba3278 101 * +----------------------+
uci1 0:687056ba3278 102 * 010 - OK!
uci1 0:687056ba3278 103 * 101 - CRC Error
uci1 0:687056ba3278 104 * 110 - Write Error
uci1 0:687056ba3278 105 *
uci1 0:687056ba3278 106 * Single Block Read and Write
uci1 0:687056ba3278 107 * ---------------------------
uci1 0:687056ba3278 108 *
uci1 0:687056ba3278 109 * Block transfers have a byte header, followed by the data, followed
uci1 0:687056ba3278 110 * by a 16-bit CRC. In our case, the data will always be 512 bytes.
uci1 0:687056ba3278 111 *
uci1 0:687056ba3278 112 * +------+---------+---------+- - - -+---------+-----------+----------+
uci1 0:687056ba3278 113 * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
uci1 0:687056ba3278 114 * +------+---------+---------+- - - -+---------+-----------+----------+
uci1 0:687056ba3278 115 */
uci1 0:687056ba3278 116 #include "SDFileSystem.h"
uci1 0:687056ba3278 117 #include "mbed_debug.h"
uci1 0:687056ba3278 118
uci1 0:687056ba3278 119 #define SD_COMMAND_TIMEOUT 5000
uci1 0:687056ba3278 120
uci1 0:687056ba3278 121 #define SD_DBG 0
uci1 0:687056ba3278 122
uci1 0:687056ba3278 123 SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
uci1 0:687056ba3278 124 FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs) {
uci1 0:687056ba3278 125 _cs = 1;
uci1 0:687056ba3278 126 }
uci1 0:687056ba3278 127
uci1 0:687056ba3278 128 #define R1_IDLE_STATE (1 << 0)
uci1 0:687056ba3278 129 #define R1_ERASE_RESET (1 << 1)
uci1 0:687056ba3278 130 #define R1_ILLEGAL_COMMAND (1 << 2)
uci1 0:687056ba3278 131 #define R1_COM_CRC_ERROR (1 << 3)
uci1 0:687056ba3278 132 #define R1_ERASE_SEQUENCE_ERROR (1 << 4)
uci1 0:687056ba3278 133 #define R1_ADDRESS_ERROR (1 << 5)
uci1 0:687056ba3278 134 #define R1_PARAMETER_ERROR (1 << 6)
uci1 0:687056ba3278 135
uci1 0:687056ba3278 136 // Types
uci1 1:a7d8fc28a863 137 #define SDCARD_FAIL 0 //!< v1.x Standard Capacity
uci1 1:a7d8fc28a863 138 #define SDCARD_V1 1 //!< v2.x Standard Capacity
uci1 1:a7d8fc28a863 139 #define SDCARD_V2 2 //!< v2.x High Capacity
uci1 1:a7d8fc28a863 140 #define SDCARD_V2HC 3 //!< Not recognised as an SD Card
uci1 0:687056ba3278 141
uci1 0:687056ba3278 142 int SDFileSystem::initialise_card() {
uci1 0:687056ba3278 143 // Set to 100kHz for initialisation, and clock card with cs = 1
uci1 0:687056ba3278 144 _spi.frequency(100000);
uci1 0:687056ba3278 145 _cs = 1;
uci1 0:687056ba3278 146 for (int i = 0; i < 16; i++) {
uci1 0:687056ba3278 147 _spi.write(0xFF);
uci1 0:687056ba3278 148 }
uci1 0:687056ba3278 149
uci1 1:a7d8fc28a863 150 int ret = SDCARD_FAIL;
uci1 1:a7d8fc28a863 151
uci1 0:687056ba3278 152 // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
uci1 0:687056ba3278 153 if (_cmd(0, 0) != R1_IDLE_STATE) {
uci1 0:687056ba3278 154 debug("No disk, or could not put SD card in to SPI idle state\n");
uci1 0:687056ba3278 155 }
uci1 0:687056ba3278 156
uci1 0:687056ba3278 157 // send CMD8 to determine whther it is ver 2.x
uci1 0:687056ba3278 158 int r = _cmd8();
uci1 0:687056ba3278 159 if (r == R1_IDLE_STATE) {
uci1 1:a7d8fc28a863 160 ret = initialise_card_v2();
uci1 0:687056ba3278 161 } else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
uci1 1:a7d8fc28a863 162 ret = initialise_card_v1();
uci1 0:687056ba3278 163 } else {
uci1 0:687056ba3278 164 debug("Not in idle state after sending CMD8 (not an SD card?)\n");
uci1 0:687056ba3278 165 }
uci1 1:a7d8fc28a863 166 return ret;
uci1 0:687056ba3278 167 }
uci1 0:687056ba3278 168
uci1 0:687056ba3278 169 int SDFileSystem::initialise_card_v1() {
uci1 0:687056ba3278 170 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
uci1 0:687056ba3278 171 _cmd(55, 0);
uci1 0:687056ba3278 172 if (_cmd(41, 0) == 0) {
uci1 0:687056ba3278 173 cdv = 512;
uci1 0:687056ba3278 174 debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
uci1 0:687056ba3278 175 return SDCARD_V1;
uci1 0:687056ba3278 176 }
uci1 0:687056ba3278 177 }
uci1 0:687056ba3278 178
uci1 0:687056ba3278 179 debug("Timeout waiting for v1.x card\n");
uci1 0:687056ba3278 180 return SDCARD_FAIL;
uci1 0:687056ba3278 181 }
uci1 0:687056ba3278 182
uci1 0:687056ba3278 183 int SDFileSystem::initialise_card_v2() {
uci1 0:687056ba3278 184 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
uci1 0:687056ba3278 185 wait_ms(50);
uci1 0:687056ba3278 186 _cmd58();
uci1 0:687056ba3278 187 _cmd(55, 0);
uci1 0:687056ba3278 188 if (_cmd(41, 0x40000000) == 0) {
uci1 0:687056ba3278 189 _cmd58();
uci1 0:687056ba3278 190 debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
uci1 0:687056ba3278 191 cdv = 1;
uci1 0:687056ba3278 192 return SDCARD_V2;
uci1 0:687056ba3278 193 }
uci1 0:687056ba3278 194 }
uci1 0:687056ba3278 195
uci1 0:687056ba3278 196 debug("Timeout waiting for v2.x card\n");
uci1 0:687056ba3278 197 return SDCARD_FAIL;
uci1 0:687056ba3278 198 }
uci1 0:687056ba3278 199
uci1 0:687056ba3278 200 int SDFileSystem::disk_initialize() {
uci1 0:687056ba3278 201 int i = initialise_card();
uci1 0:687056ba3278 202 debug_if(SD_DBG, "init card = %d\n", i);
uci1 1:a7d8fc28a863 203 if (i==SDCARD_FAIL) {
uci1 1:a7d8fc28a863 204 return 1;
uci1 1:a7d8fc28a863 205 }
uci1 0:687056ba3278 206 _sectors = _sd_sectors();
uci1 0:687056ba3278 207
uci1 0:687056ba3278 208 // Set block length to 512 (CMD16)
uci1 0:687056ba3278 209 if (_cmd(16, 512) != 0) {
uci1 0:687056ba3278 210 debug("Set 512-byte block timed out\n");
uci1 0:687056ba3278 211 return 1;
uci1 0:687056ba3278 212 }
uci1 0:687056ba3278 213
uci1 0:687056ba3278 214 _spi.frequency(1000000); // Set to 1MHz for data transfer
uci1 0:687056ba3278 215 return 0;
uci1 0:687056ba3278 216 }
uci1 0:687056ba3278 217
uci1 0:687056ba3278 218 int SDFileSystem::disk_write(const uint8_t *buffer, uint64_t block_number) {
uci1 0:687056ba3278 219 // set write address for single block (CMD24)
uci1 0:687056ba3278 220 if (_cmd(24, block_number * cdv) != 0) {
uci1 0:687056ba3278 221 return 1;
uci1 0:687056ba3278 222 }
uci1 0:687056ba3278 223
uci1 0:687056ba3278 224 // send the data block
uci1 0:687056ba3278 225 _write(buffer, 512);
uci1 0:687056ba3278 226 return 0;
uci1 0:687056ba3278 227 }
uci1 0:687056ba3278 228
uci1 0:687056ba3278 229 int SDFileSystem::disk_read(uint8_t *buffer, uint64_t block_number) {
uci1 0:687056ba3278 230 // set read address for single block (CMD17)
uci1 0:687056ba3278 231 if (_cmd(17, block_number * cdv) != 0) {
uci1 0:687056ba3278 232 return 1;
uci1 0:687056ba3278 233 }
uci1 0:687056ba3278 234
uci1 0:687056ba3278 235 // receive the data
uci1 0:687056ba3278 236 _read(buffer, 512);
uci1 0:687056ba3278 237 return 0;
uci1 0:687056ba3278 238 }
uci1 0:687056ba3278 239
uci1 0:687056ba3278 240 int SDFileSystem::disk_status() { return 0; }
uci1 0:687056ba3278 241 int SDFileSystem::disk_sync() { return 0; }
uci1 0:687056ba3278 242 uint64_t SDFileSystem::disk_sectors() { return _sectors; }
uci1 0:687056ba3278 243
uci1 0:687056ba3278 244
uci1 0:687056ba3278 245 // PRIVATE FUNCTIONS
uci1 0:687056ba3278 246 int SDFileSystem::_cmd(int cmd, int arg) {
uci1 0:687056ba3278 247 _cs = 0;
uci1 0:687056ba3278 248
uci1 0:687056ba3278 249 // send a command
uci1 0:687056ba3278 250 _spi.write(0x40 | cmd);
uci1 0:687056ba3278 251 _spi.write(arg >> 24);
uci1 0:687056ba3278 252 _spi.write(arg >> 16);
uci1 0:687056ba3278 253 _spi.write(arg >> 8);
uci1 0:687056ba3278 254 _spi.write(arg >> 0);
uci1 0:687056ba3278 255 _spi.write(0x95);
uci1 0:687056ba3278 256
uci1 0:687056ba3278 257 // wait for the repsonse (response[7] == 0)
uci1 0:687056ba3278 258 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
uci1 0:687056ba3278 259 int response = _spi.write(0xFF);
uci1 0:687056ba3278 260 if (!(response & 0x80)) {
uci1 0:687056ba3278 261 _cs = 1;
uci1 0:687056ba3278 262 _spi.write(0xFF);
uci1 0:687056ba3278 263 return response;
uci1 0:687056ba3278 264 }
uci1 0:687056ba3278 265 }
uci1 0:687056ba3278 266 _cs = 1;
uci1 0:687056ba3278 267 _spi.write(0xFF);
uci1 0:687056ba3278 268 return -1; // timeout
uci1 0:687056ba3278 269 }
uci1 0:687056ba3278 270 int SDFileSystem::_cmdx(int cmd, int arg) {
uci1 0:687056ba3278 271 _cs = 0;
uci1 0:687056ba3278 272
uci1 0:687056ba3278 273 // send a command
uci1 0:687056ba3278 274 _spi.write(0x40 | cmd);
uci1 0:687056ba3278 275 _spi.write(arg >> 24);
uci1 0:687056ba3278 276 _spi.write(arg >> 16);
uci1 0:687056ba3278 277 _spi.write(arg >> 8);
uci1 0:687056ba3278 278 _spi.write(arg >> 0);
uci1 0:687056ba3278 279 _spi.write(0x95);
uci1 0:687056ba3278 280
uci1 0:687056ba3278 281 // wait for the repsonse (response[7] == 0)
uci1 0:687056ba3278 282 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
uci1 0:687056ba3278 283 int response = _spi.write(0xFF);
uci1 0:687056ba3278 284 if (!(response & 0x80)) {
uci1 0:687056ba3278 285 return response;
uci1 0:687056ba3278 286 }
uci1 0:687056ba3278 287 }
uci1 0:687056ba3278 288 _cs = 1;
uci1 0:687056ba3278 289 _spi.write(0xFF);
uci1 0:687056ba3278 290 return -1; // timeout
uci1 0:687056ba3278 291 }
uci1 0:687056ba3278 292
uci1 0:687056ba3278 293
uci1 0:687056ba3278 294 int SDFileSystem::_cmd58() {
uci1 0:687056ba3278 295 _cs = 0;
uci1 0:687056ba3278 296 int arg = 0;
uci1 0:687056ba3278 297
uci1 0:687056ba3278 298 // send a command
uci1 0:687056ba3278 299 _spi.write(0x40 | 58);
uci1 0:687056ba3278 300 _spi.write(arg >> 24);
uci1 0:687056ba3278 301 _spi.write(arg >> 16);
uci1 0:687056ba3278 302 _spi.write(arg >> 8);
uci1 0:687056ba3278 303 _spi.write(arg >> 0);
uci1 0:687056ba3278 304 _spi.write(0x95);
uci1 0:687056ba3278 305
uci1 0:687056ba3278 306 // wait for the repsonse (response[7] == 0)
uci1 0:687056ba3278 307 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
uci1 0:687056ba3278 308 int response = _spi.write(0xFF);
uci1 0:687056ba3278 309 if (!(response & 0x80)) {
uci1 0:687056ba3278 310 int ocr = _spi.write(0xFF) << 24;
uci1 0:687056ba3278 311 ocr |= _spi.write(0xFF) << 16;
uci1 0:687056ba3278 312 ocr |= _spi.write(0xFF) << 8;
uci1 0:687056ba3278 313 ocr |= _spi.write(0xFF) << 0;
uci1 0:687056ba3278 314 _cs = 1;
uci1 0:687056ba3278 315 _spi.write(0xFF);
uci1 0:687056ba3278 316 return response;
uci1 0:687056ba3278 317 }
uci1 0:687056ba3278 318 }
uci1 0:687056ba3278 319 _cs = 1;
uci1 0:687056ba3278 320 _spi.write(0xFF);
uci1 0:687056ba3278 321 return -1; // timeout
uci1 0:687056ba3278 322 }
uci1 0:687056ba3278 323
uci1 0:687056ba3278 324 int SDFileSystem::_cmd8() {
uci1 0:687056ba3278 325 _cs = 0;
uci1 0:687056ba3278 326
uci1 0:687056ba3278 327 // send a command
uci1 0:687056ba3278 328 _spi.write(0x40 | 8); // CMD8
uci1 0:687056ba3278 329 _spi.write(0x00); // reserved
uci1 0:687056ba3278 330 _spi.write(0x00); // reserved
uci1 0:687056ba3278 331 _spi.write(0x01); // 3.3v
uci1 0:687056ba3278 332 _spi.write(0xAA); // check pattern
uci1 0:687056ba3278 333 _spi.write(0x87); // crc
uci1 0:687056ba3278 334
uci1 0:687056ba3278 335 // wait for the repsonse (response[7] == 0)
uci1 0:687056ba3278 336 for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
uci1 0:687056ba3278 337 char response[5];
uci1 0:687056ba3278 338 response[0] = _spi.write(0xFF);
uci1 0:687056ba3278 339 if (!(response[0] & 0x80)) {
uci1 0:687056ba3278 340 for (int j = 1; j < 5; j++) {
uci1 0:687056ba3278 341 response[i] = _spi.write(0xFF);
uci1 0:687056ba3278 342 }
uci1 0:687056ba3278 343 _cs = 1;
uci1 0:687056ba3278 344 _spi.write(0xFF);
uci1 0:687056ba3278 345 return response[0];
uci1 0:687056ba3278 346 }
uci1 0:687056ba3278 347 }
uci1 0:687056ba3278 348 _cs = 1;
uci1 0:687056ba3278 349 _spi.write(0xFF);
uci1 0:687056ba3278 350 return -1; // timeout
uci1 0:687056ba3278 351 }
uci1 0:687056ba3278 352
uci1 0:687056ba3278 353 int SDFileSystem::_read(uint8_t *buffer, uint32_t length) {
uci1 0:687056ba3278 354 _cs = 0;
uci1 0:687056ba3278 355
uci1 0:687056ba3278 356 // read until start byte (0xFF)
uci1 0:687056ba3278 357 while (_spi.write(0xFF) != 0xFE);
uci1 0:687056ba3278 358
uci1 0:687056ba3278 359 // read data
uci1 0:687056ba3278 360 for (int i = 0; i < length; i++) {
uci1 0:687056ba3278 361 buffer[i] = _spi.write(0xFF);
uci1 0:687056ba3278 362 }
uci1 0:687056ba3278 363 _spi.write(0xFF); // checksum
uci1 0:687056ba3278 364 _spi.write(0xFF);
uci1 0:687056ba3278 365
uci1 0:687056ba3278 366 _cs = 1;
uci1 0:687056ba3278 367 _spi.write(0xFF);
uci1 0:687056ba3278 368 return 0;
uci1 0:687056ba3278 369 }
uci1 0:687056ba3278 370
uci1 0:687056ba3278 371 int SDFileSystem::_write(const uint8_t*buffer, uint32_t length) {
uci1 0:687056ba3278 372 _cs = 0;
uci1 0:687056ba3278 373
uci1 0:687056ba3278 374 // indicate start of block
uci1 0:687056ba3278 375 _spi.write(0xFE);
uci1 0:687056ba3278 376
uci1 0:687056ba3278 377 // write the data
uci1 0:687056ba3278 378 for (int i = 0; i < length; i++) {
uci1 0:687056ba3278 379 _spi.write(buffer[i]);
uci1 0:687056ba3278 380 }
uci1 0:687056ba3278 381
uci1 0:687056ba3278 382 // write the checksum
uci1 0:687056ba3278 383 _spi.write(0xFF);
uci1 0:687056ba3278 384 _spi.write(0xFF);
uci1 0:687056ba3278 385
uci1 0:687056ba3278 386 // check the response token
uci1 0:687056ba3278 387 if ((_spi.write(0xFF) & 0x1F) != 0x05) {
uci1 0:687056ba3278 388 _cs = 1;
uci1 0:687056ba3278 389 _spi.write(0xFF);
uci1 0:687056ba3278 390 return 1;
uci1 0:687056ba3278 391 }
uci1 0:687056ba3278 392
uci1 0:687056ba3278 393 // wait for write to finish
uci1 0:687056ba3278 394 while (_spi.write(0xFF) == 0);
uci1 0:687056ba3278 395
uci1 0:687056ba3278 396 _cs = 1;
uci1 0:687056ba3278 397 _spi.write(0xFF);
uci1 0:687056ba3278 398 return 0;
uci1 0:687056ba3278 399 }
uci1 0:687056ba3278 400
uci1 0:687056ba3278 401 static uint32_t ext_bits(unsigned char *data, int msb, int lsb) {
uci1 0:687056ba3278 402 uint32_t bits = 0;
uci1 0:687056ba3278 403 uint32_t size = 1 + msb - lsb;
uci1 0:687056ba3278 404 for (int i = 0; i < size; i++) {
uci1 0:687056ba3278 405 uint32_t position = lsb + i;
uci1 0:687056ba3278 406 uint32_t byte = 15 - (position >> 3);
uci1 0:687056ba3278 407 uint32_t bit = position & 0x7;
uci1 0:687056ba3278 408 uint32_t value = (data[byte] >> bit) & 1;
uci1 0:687056ba3278 409 bits |= value << i;
uci1 0:687056ba3278 410 }
uci1 0:687056ba3278 411 return bits;
uci1 0:687056ba3278 412 }
uci1 0:687056ba3278 413
uci1 0:687056ba3278 414 uint64_t SDFileSystem::_sd_sectors() {
uci1 0:687056ba3278 415 uint32_t c_size, c_size_mult, read_bl_len;
uci1 0:687056ba3278 416 uint32_t block_len, mult, blocknr, capacity;
uci1 0:687056ba3278 417 uint32_t hc_c_size;
uci1 0:687056ba3278 418 uint64_t blocks;
uci1 0:687056ba3278 419
uci1 0:687056ba3278 420 // CMD9, Response R2 (R1 byte + 16-byte block read)
uci1 0:687056ba3278 421 if (_cmdx(9, 0) != 0) {
uci1 0:687056ba3278 422 debug("Didn't get a response from the disk\n");
uci1 0:687056ba3278 423 return 0;
uci1 0:687056ba3278 424 }
uci1 0:687056ba3278 425
uci1 0:687056ba3278 426 uint8_t csd[16];
uci1 0:687056ba3278 427 if (_read(csd, 16) != 0) {
uci1 0:687056ba3278 428 debug("Couldn't read csd response from disk\n");
uci1 0:687056ba3278 429 return 0;
uci1 0:687056ba3278 430 }
uci1 0:687056ba3278 431
uci1 0:687056ba3278 432 // csd_structure : csd[127:126]
uci1 0:687056ba3278 433 // c_size : csd[73:62]
uci1 0:687056ba3278 434 // c_size_mult : csd[49:47]
uci1 0:687056ba3278 435 // read_bl_len : csd[83:80] - the *maximum* read block length
uci1 0:687056ba3278 436
uci1 0:687056ba3278 437 int csd_structure = ext_bits(csd, 127, 126);
uci1 0:687056ba3278 438
uci1 0:687056ba3278 439 switch (csd_structure) {
uci1 0:687056ba3278 440 case 0:
uci1 0:687056ba3278 441 cdv = 512;
uci1 0:687056ba3278 442 c_size = ext_bits(csd, 73, 62);
uci1 0:687056ba3278 443 c_size_mult = ext_bits(csd, 49, 47);
uci1 0:687056ba3278 444 read_bl_len = ext_bits(csd, 83, 80);
uci1 0:687056ba3278 445
uci1 0:687056ba3278 446 block_len = 1 << read_bl_len;
uci1 0:687056ba3278 447 mult = 1 << (c_size_mult + 2);
uci1 0:687056ba3278 448 blocknr = (c_size + 1) * mult;
uci1 0:687056ba3278 449 capacity = blocknr * block_len;
uci1 0:687056ba3278 450 blocks = capacity / 512;
uci1 0:687056ba3278 451 debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, capacity, blocks);
uci1 0:687056ba3278 452 break;
uci1 0:687056ba3278 453
uci1 0:687056ba3278 454 case 1:
uci1 0:687056ba3278 455 cdv = 1;
uci1 0:687056ba3278 456 hc_c_size = ext_bits(csd, 63, 48);
uci1 0:687056ba3278 457 blocks = (hc_c_size+1)*1024;
uci1 0:687056ba3278 458 debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks*512, blocks);
uci1 0:687056ba3278 459 break;
uci1 0:687056ba3278 460
uci1 0:687056ba3278 461 default:
uci1 0:687056ba3278 462 debug("CSD struct unsupported\r\n");
uci1 0:687056ba3278 463 return 0;
uci1 0:687056ba3278 464 };
uci1 0:687056ba3278 465 return blocks;
uci1 0:687056ba3278 466 }