S K UCI / PowerControlClkPatch

Patched version of the PowerControl library that handles (re)starting clocks such that (ETH) power can be brought up and down repeatedly without stalling the mbed.

Dependents:   AutonomousDAQ AutonomousDAQ

PowerControl.h@0:334c4560cd83, 2012-10-08 (annotated)

Committer:
uci1
Date:
Mon Oct 08 22:07:41 2012 +0000
Revision:
0:334c4560cd83
Child:
3:4ab735b9a69f
From PowerControl. Move (re-)starting of clock to before the EMAC_Init. This fixes a bug in which EMAC_Init would stall if the clock were still off (after a power down, for example).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
uci1 0:334c4560cd83 1 /* mbed PowerControl Library
uci1 0:334c4560cd83 2 * Copyright (c) 2010 Michael Wei
uci1 0:334c4560cd83 3 */
uci1 0:334c4560cd83 4
uci1 0:334c4560cd83 5 #ifndef MBED_POWERCONTROL_H
uci1 0:334c4560cd83 6 #define MBED_POWERCONTROL_H
uci1 0:334c4560cd83 7
uci1 0:334c4560cd83 8 //shouldn't have to include, but fixes weird problems with defines
uci1 0:334c4560cd83 9 #include "LPC1768/LPC17xx.h"
uci1 0:334c4560cd83 10
uci1 0:334c4560cd83 11 //System Control Register
uci1 0:334c4560cd83 12 // bit 0: Reserved
uci1 0:334c4560cd83 13 // bit 1: Sleep on Exit
uci1 0:334c4560cd83 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
uci1 0:334c4560cd83 15 // bit 2: Deep Sleep
uci1 0:334c4560cd83 16 #define LPC1768_SCR_SLEEPDEEP 0x4
uci1 0:334c4560cd83 17 // bit 3: Resereved
uci1 0:334c4560cd83 18 // bit 4: Send on Pending
uci1 0:334c4560cd83 19 #define LPC1768_SCR_SEVONPEND 0x10
uci1 0:334c4560cd83 20 // bit 5-31: Reserved
uci1 0:334c4560cd83 21
uci1 0:334c4560cd83 22 //Power Control Register
uci1 0:334c4560cd83 23 // bit 0: Power mode control bit 0 (power-down mode)
uci1 0:334c4560cd83 24 #define LPC1768_PCON_PM0 0x1
uci1 0:334c4560cd83 25 // bit 1: Power mode control bit 1 (deep power-down mode)
uci1 0:334c4560cd83 26 #define LPC1768_PCON_PM1 0x2
uci1 0:334c4560cd83 27 // bit 2: Brown-out reduced power mode
uci1 0:334c4560cd83 28 #define LPC1768_PCON_BODRPM 0x4
uci1 0:334c4560cd83 29 // bit 3: Brown-out global disable
uci1 0:334c4560cd83 30 #define LPC1768_PCON_BOGD 0x8
uci1 0:334c4560cd83 31 // bit 4: Brown-out reset disable
uci1 0:334c4560cd83 32 #define LPC1768_PCON_BORD 0x10
uci1 0:334c4560cd83 33 // bit 5-7 : Reserved
uci1 0:334c4560cd83 34 // bit 8: Sleep Mode Entry Flag
uci1 0:334c4560cd83 35 #define LPC1768_PCON_SMFLAG 0x100
uci1 0:334c4560cd83 36 // bit 9: Deep Sleep Entry Flag
uci1 0:334c4560cd83 37 #define LPC1768_PCON_DSFLAG 0x200
uci1 0:334c4560cd83 38 // bit 10: Power Down Entry Flag
uci1 0:334c4560cd83 39 #define LPC1768_PCON_PDFLAG 0x400
uci1 0:334c4560cd83 40 // bit 11: Deep Power Down Entry Flag
uci1 0:334c4560cd83 41 #define LPC1768_PCON_DPDFLAG 0x800
uci1 0:334c4560cd83 42 // bit 12-31: Reserved
uci1 0:334c4560cd83 43
uci1 0:334c4560cd83 44 //"Sleep Mode" (WFI).
uci1 0:334c4560cd83 45 inline void Sleep(void)
uci1 0:334c4560cd83 46 {
uci1 0:334c4560cd83 47 __WFI();
uci1 0:334c4560cd83 48 }
uci1 0:334c4560cd83 49
uci1 0:334c4560cd83 50 //"Deep Sleep" Mode
uci1 0:334c4560cd83 51 inline void DeepSleep(void)
uci1 0:334c4560cd83 52 {
uci1 0:334c4560cd83 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
uci1 0:334c4560cd83 54 __WFI();
uci1 0:334c4560cd83 55 }
uci1 0:334c4560cd83 56
uci1 0:334c4560cd83 57 //"Power-Down" Mode
uci1 0:334c4560cd83 58 inline void PowerDown(void)
uci1 0:334c4560cd83 59 {
uci1 0:334c4560cd83 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
uci1 0:334c4560cd83 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
uci1 0:334c4560cd83 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
uci1 0:334c4560cd83 63 __WFI();
uci1 0:334c4560cd83 64 //reset back to normal
uci1 0:334c4560cd83 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
uci1 0:334c4560cd83 66 }
uci1 0:334c4560cd83 67
uci1 0:334c4560cd83 68 //"Deep Power-Down" Mode
uci1 0:334c4560cd83 69 inline void DeepPowerDown(void)
uci1 0:334c4560cd83 70 {
uci1 0:334c4560cd83 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
uci1 0:334c4560cd83 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
uci1 0:334c4560cd83 73 __WFI();
uci1 0:334c4560cd83 74 //reset back to normal
uci1 0:334c4560cd83 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
uci1 0:334c4560cd83 76 }
uci1 0:334c4560cd83 77
uci1 0:334c4560cd83 78 //shut down BOD during power-down/deep sleep
uci1 0:334c4560cd83 79 inline void BrownOut_ReducedPowerMode_Enable(void)
uci1 0:334c4560cd83 80 {
uci1 0:334c4560cd83 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
uci1 0:334c4560cd83 82 }
uci1 0:334c4560cd83 83
uci1 0:334c4560cd83 84 //turn on BOD during power-down/deep sleep
uci1 0:334c4560cd83 85 inline void BrownOut_ReducedPowerMode_Disable(void)
uci1 0:334c4560cd83 86 {
uci1 0:334c4560cd83 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
uci1 0:334c4560cd83 88 }
uci1 0:334c4560cd83 89
uci1 0:334c4560cd83 90 //turn off brown out circutry
uci1 0:334c4560cd83 91 inline void BrownOut_Global_Disable(void)
uci1 0:334c4560cd83 92 {
uci1 0:334c4560cd83 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
uci1 0:334c4560cd83 94 }
uci1 0:334c4560cd83 95
uci1 0:334c4560cd83 96 //turn on brown out circutry
uci1 0:334c4560cd83 97 inline void BrownOut_Global_Enable(void)
uci1 0:334c4560cd83 98 {
uci1 0:334c4560cd83 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
uci1 0:334c4560cd83 100 }
uci1 0:334c4560cd83 101
uci1 0:334c4560cd83 102 //turn off brown out reset circutry
uci1 0:334c4560cd83 103 inline void BrownOut_Reset_Disable(void)
uci1 0:334c4560cd83 104 {
uci1 0:334c4560cd83 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
uci1 0:334c4560cd83 106 }
uci1 0:334c4560cd83 107
uci1 0:334c4560cd83 108 //turn on brown outreset circutry
uci1 0:334c4560cd83 109 inline void BrownOut_Reset_Enable(void)
uci1 0:334c4560cd83 110 {
uci1 0:334c4560cd83 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
uci1 0:334c4560cd83 112 }
uci1 0:334c4560cd83 113 //Peripheral Control Register
uci1 0:334c4560cd83 114 // bit 0: Reserved
uci1 0:334c4560cd83 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
uci1 0:334c4560cd83 116 #define LPC1768_PCONP_PCTIM0 0x2
uci1 0:334c4560cd83 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
uci1 0:334c4560cd83 118 #define LPC1768_PCONP_PCTIM1 0x4
uci1 0:334c4560cd83 119 // bit 3: PCUART0: UART 0 power/clock enable
uci1 0:334c4560cd83 120 #define LPC1768_PCONP_PCUART0 0x8
uci1 0:334c4560cd83 121 // bit 4: PCUART1: UART 1 power/clock enable
uci1 0:334c4560cd83 122 #define LPC1768_PCONP_PCUART1 0x10
uci1 0:334c4560cd83 123 // bit 5: Reserved
uci1 0:334c4560cd83 124 // bit 6: PCPWM1: PWM 1 power/clock enable
uci1 0:334c4560cd83 125 #define LPC1768_PCONP_PCPWM1 0x40
uci1 0:334c4560cd83 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
uci1 0:334c4560cd83 127 #define LPC1768_PCONP_PCI2C0 0x80
uci1 0:334c4560cd83 128 // bit 8: PCSPI: SPI interface power/clock enable
uci1 0:334c4560cd83 129 #define LPC1768_PCONP_PCSPI 0x100
uci1 0:334c4560cd83 130 // bit 9: PCRTC: RTC power/clock enable
uci1 0:334c4560cd83 131 #define LPC1768_PCONP_PCRTC 0x200
uci1 0:334c4560cd83 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
uci1 0:334c4560cd83 133 #define LPC1768_PCONP_PCSSP1 0x400
uci1 0:334c4560cd83 134 // bit 11: Reserved
uci1 0:334c4560cd83 135 // bit 12: PCADC: A/D converter power/clock enable
uci1 0:334c4560cd83 136 #define LPC1768_PCONP_PCADC 0x1000
uci1 0:334c4560cd83 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
uci1 0:334c4560cd83 138 #define LPC1768_PCONP_PCCAN1 0x2000
uci1 0:334c4560cd83 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
uci1 0:334c4560cd83 140 #define LPC1768_PCONP_PCCAN2 0x4000
uci1 0:334c4560cd83 141 // bit 15: PCGPIO: GPIOs power/clock enable
uci1 0:334c4560cd83 142 #define LPC1768_PCONP_PCGPIO 0x8000
uci1 0:334c4560cd83 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
uci1 0:334c4560cd83 144 #define LPC1768_PCONP_PCRIT 0x10000
uci1 0:334c4560cd83 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
uci1 0:334c4560cd83 146 #define LPC1768_PCONP_PCMCPWM 0x20000
uci1 0:334c4560cd83 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
uci1 0:334c4560cd83 148 #define LPC1768_PCONP_PCQEI 0x40000
uci1 0:334c4560cd83 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
uci1 0:334c4560cd83 150 #define LPC1768_PCONP_PCI2C1 0x80000
uci1 0:334c4560cd83 151 // bit 20: Reserved
uci1 0:334c4560cd83 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
uci1 0:334c4560cd83 153 #define LPC1768_PCONP_PCSSP0 0x200000
uci1 0:334c4560cd83 154 // bit 22: PCTIM2: Timer 2 power/clock enable
uci1 0:334c4560cd83 155 #define LPC1768_PCONP_PCTIM2 0x400000
uci1 0:334c4560cd83 156 // bit 23: PCTIM3: Timer 3 power/clock enable
uci1 0:334c4560cd83 157 #define LPC1768_PCONP_PCQTIM3 0x800000
uci1 0:334c4560cd83 158 // bit 24: PCUART2: UART 2 power/clock enable
uci1 0:334c4560cd83 159 #define LPC1768_PCONP_PCUART2 0x1000000
uci1 0:334c4560cd83 160 // bit 25: PCUART3: UART 3 power/clock enable
uci1 0:334c4560cd83 161 #define LPC1768_PCONP_PCUART3 0x2000000
uci1 0:334c4560cd83 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
uci1 0:334c4560cd83 163 #define LPC1768_PCONP_PCI2C2 0x4000000
uci1 0:334c4560cd83 164 // bit 27: PCI2S: I2S interface power/clock enable
uci1 0:334c4560cd83 165 #define LPC1768_PCONP_PCI2S 0x8000000
uci1 0:334c4560cd83 166 // bit 28: Reserved
uci1 0:334c4560cd83 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
uci1 0:334c4560cd83 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
uci1 0:334c4560cd83 169 // bit 30: PCENET: Ethernet block power/clock enable
uci1 0:334c4560cd83 170 #define LPC1768_PCONP_PCENET 0x40000000
uci1 0:334c4560cd83 171 // bit 31: PCUSB: USB interface power/clock enable
uci1 0:334c4560cd83 172 #define LPC1768_PCONP_PCUSB 0x80000000
uci1 0:334c4560cd83 173
uci1 0:334c4560cd83 174 //Powers Up specified Peripheral(s)
uci1 0:334c4560cd83 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
uci1 0:334c4560cd83 176 {
uci1 0:334c4560cd83 177 return LPC_SC->PCONP |= bitMask;
uci1 0:334c4560cd83 178 }
uci1 0:334c4560cd83 179
uci1 0:334c4560cd83 180 //Powers Down specified Peripheral(s)
uci1 0:334c4560cd83 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
uci1 0:334c4560cd83 182 {
uci1 0:334c4560cd83 183 return LPC_SC->PCONP &= ~bitMask;
uci1 0:334c4560cd83 184 }
uci1 0:334c4560cd83 185
uci1 0:334c4560cd83 186 //returns if the peripheral is on or off
uci1 0:334c4560cd83 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
uci1 0:334c4560cd83 188 {
uci1 0:334c4560cd83 189 return (LPC_SC->PCONP & peripheral) ? true : false;
uci1 0:334c4560cd83 190 }
uci1 0:334c4560cd83 191
uci1 0:334c4560cd83 192 #endif