Diff: targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c

Revision:

186:707f6e361f3e

Parent:

184:08ed48f1de7f

diff -r 08ed48f1de7f -r 707f6e361f3e targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c
--- a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c	Fri Jun 22 16:45:37 2018 +0100
@@ -100,7 +100,7 @@
 
 void rtc_free(void)
 {
-    // N/A
+    CLK_DisableModuleClock(rtc_modinit.clkidx);
 }
 
 int rtc_isenabled(void)
@@ -114,6 +114,7 @@
     // NOTE: Check RTC Init Active flag to support crossing reset cycle.
     return !! (RTC->INIT & RTC_INIT_ACTIVE_Msk);
 }
+
 time_t rtc_read(void)
 {
     /* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
@@ -137,9 +138,16 @@
         if (! _rtc_maketime(&datetime_tm, &t_hwrtc_origin, RTC_FULL_LEAP_YEAR_SUPPORT)) {
             return 0;
         }
+
+        /* Load t_write from RTC spare register to cross reset cycle */
+        RTC_WaitAccessEnable();
+        RTC_EnableSpareAccess();
+        RTC_WaitAccessEnable();
+        t_write = RTC_READ_SPARE_REGISTER(0);
     }
 
     S_RTC_TIME_DATA_T hwrtc_datetime_2K_present;
+    RTC_WaitAccessEnable();
     RTC_GetDateAndTime(&hwrtc_datetime_2K_present);
     /* Convert date time from H/W RTC to struct TM */
     rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &hwrtc_datetime_2K_present);
@@ -162,6 +170,13 @@
 
     t_write = t;
 
+    /* Store t_write to RTC spare register to cross reset cycle */
+    RTC_WaitAccessEnable();
+    RTC_EnableSpareAccess();
+    RTC_WaitAccessEnable();
+    RTC_WRITE_SPARE_REGISTER(0, t_write);
+
+    RTC_WaitAccessEnable();
     RTC_SetDateAndTime((S_RTC_TIME_DATA_T *) &DATETIME_HWRTC_ORIGIN);
     /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
     wait_us((NU_US_PER_SEC / NU_RTCCLK_PER_SEC) * 3);