Genadi Zawidowski
mbed library sources. Supersedes mbed-src. Edited target satm32f446 for user USART3 pins
Fork of
mbed-dev
by 
mbed official
targets/TARGET_Maxim/TARGET_MAX32620C/PeripheralPins.c@186:707f6e361f3e, 2018-06-22 (annotated)
- Committer:
- Anna Bridge
- Date:
- Fri Jun 22 16:45:37 2018 +0100
- Revision:
- 186:707f6e361f3e
mbed-dev library. Release version 162
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
186:707f6e361f3e | 1 | /******************************************************************************* |
| Anna Bridge |
186:707f6e361f3e | 2 | * Copyright (c) 2017 Maxim Integrated Products, Inc., All Rights Reserved. |
| Anna Bridge |
186:707f6e361f3e | 3 | * |
| Anna Bridge |
186:707f6e361f3e | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Anna Bridge |
186:707f6e361f3e | 5 | * copy of this software and associated documentation files (the "Software"), |
| Anna Bridge |
186:707f6e361f3e | 6 | * to deal in the Software without restriction, including without limitation |
| Anna Bridge |
186:707f6e361f3e | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Anna Bridge |
186:707f6e361f3e | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Anna Bridge |
186:707f6e361f3e | 9 | * Software is furnished to do so, subject to the following conditions: |
| Anna Bridge |
186:707f6e361f3e | 10 | * |
| Anna Bridge |
186:707f6e361f3e | 11 | * The above copyright notice and this permission notice shall be included |
| Anna Bridge |
186:707f6e361f3e | 12 | * in all copies or substantial portions of the Software. |
| Anna Bridge |
186:707f6e361f3e | 13 | * |
| Anna Bridge |
186:707f6e361f3e | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Anna Bridge |
186:707f6e361f3e | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Anna Bridge |
186:707f6e361f3e | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Anna Bridge |
186:707f6e361f3e | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Anna Bridge |
186:707f6e361f3e | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Anna Bridge |
186:707f6e361f3e | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Anna Bridge |
186:707f6e361f3e | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Anna Bridge |
186:707f6e361f3e | 21 | * |
| Anna Bridge |
186:707f6e361f3e | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Anna Bridge |
186:707f6e361f3e | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Anna Bridge |
186:707f6e361f3e | 24 | * Products, Inc. Branding Policy. |
| Anna Bridge |
186:707f6e361f3e | 25 | * |
| Anna Bridge |
186:707f6e361f3e | 26 | * The mere transfer of this software does not imply any licenses |
| Anna Bridge |
186:707f6e361f3e | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Anna Bridge |
186:707f6e361f3e | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Anna Bridge |
186:707f6e361f3e | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Anna Bridge |
186:707f6e361f3e | 30 | * ownership rights. |
| Anna Bridge |
186:707f6e361f3e | 31 | ******************************************************************************* |
| Anna Bridge |
186:707f6e361f3e | 32 | */ |
| Anna Bridge |
186:707f6e361f3e | 33 | |
| Anna Bridge |
186:707f6e361f3e | 34 | #include "device.h" |
| Anna Bridge |
186:707f6e361f3e | 35 | #include "PeripheralPins.h" |
| Anna Bridge |
186:707f6e361f3e | 36 | #include "ioman_regs.h" |
| Anna Bridge |
186:707f6e361f3e | 37 | #include "ioman.h" |
| Anna Bridge |
186:707f6e361f3e | 38 | #include "adc.h" |
| Anna Bridge |
186:707f6e361f3e | 39 | |
| Anna Bridge |
186:707f6e361f3e | 40 | /* |
| Anna Bridge |
186:707f6e361f3e | 41 | * To select a peripheral function on Maxim microcontrollers, multiple |
| Anna Bridge |
186:707f6e361f3e | 42 | * configurations must be made. The mbed PinMap structure only includes one |
| Anna Bridge |
186:707f6e361f3e | 43 | * data member to hold this information. To extend the configuration storage, |
| Anna Bridge |
186:707f6e361f3e | 44 | * the "function" data member is used as a pointer to a pin_function_t |
| Anna Bridge |
186:707f6e361f3e | 45 | * structure. This structure is defined in objects.h. The definitions below |
| Anna Bridge |
186:707f6e361f3e | 46 | * include the creation of the pin_function_t structures and the assignment of |
| Anna Bridge |
186:707f6e361f3e | 47 | * the pointers to the "function" data members. |
| Anna Bridge |
186:707f6e361f3e | 48 | */ |
| Anna Bridge |
186:707f6e361f3e | 49 | |
| Anna Bridge |
186:707f6e361f3e | 50 | #ifdef TOOLCHAIN_ARM_STD |
| Anna Bridge |
186:707f6e361f3e | 51 | #pragma diag_suppress 1296 |
| Anna Bridge |
186:707f6e361f3e | 52 | #endif |
| Anna Bridge |
186:707f6e361f3e | 53 | |
| Anna Bridge |
186:707f6e361f3e | 54 | /************I2C***************/ |
| Anna Bridge |
186:707f6e361f3e | 55 | const PinMap PinMap_I2C_SDA[] = { |
| Anna Bridge |
186:707f6e361f3e | 56 | { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 57 | { P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 58 | { P5_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 59 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 60 | }; |
| Anna Bridge |
186:707f6e361f3e | 61 | |
| Anna Bridge |
186:707f6e361f3e | 62 | const PinMap PinMap_I2C_SCL[] = { |
| Anna Bridge |
186:707f6e361f3e | 63 | { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 64 | { P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 65 | { P6_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 66 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 67 | }; |
| Anna Bridge |
186:707f6e361f3e | 68 | |
| Anna Bridge |
186:707f6e361f3e | 69 | /************UART***************/ |
| Anna Bridge |
186:707f6e361f3e | 70 | const PinMap PinMap_UART_TX[] = { |
| Anna Bridge |
186:707f6e361f3e | 71 | { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 72 | { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 73 | { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 74 | { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 75 | { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 76 | { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 77 | { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 78 | { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 79 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 80 | }; |
| Anna Bridge |
186:707f6e361f3e | 81 | |
| Anna Bridge |
186:707f6e361f3e | 82 | const PinMap PinMap_UART_RX[] = { |
| Anna Bridge |
186:707f6e361f3e | 83 | { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 84 | { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 85 | { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 86 | { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 87 | { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 88 | { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 89 | { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 90 | { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 91 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 92 | }; |
| Anna Bridge |
186:707f6e361f3e | 93 | |
| Anna Bridge |
186:707f6e361f3e | 94 | const PinMap PinMap_UART_CTS[] = { |
| Anna Bridge |
186:707f6e361f3e | 95 | { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 96 | { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 97 | { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 98 | { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 99 | { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 100 | { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 101 | { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 102 | { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 103 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 104 | }; |
| Anna Bridge |
186:707f6e361f3e | 105 | |
| Anna Bridge |
186:707f6e361f3e | 106 | const PinMap PinMap_UART_RTS[] = { |
| Anna Bridge |
186:707f6e361f3e | 107 | { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 108 | { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 109 | { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 110 | { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 111 | { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 112 | { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 113 | { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 114 | { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 115 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 116 | }; |
| Anna Bridge |
186:707f6e361f3e | 117 | |
| Anna Bridge |
186:707f6e361f3e | 118 | /************SPI***************/ |
| Anna Bridge |
186:707f6e361f3e | 119 | const PinMap PinMap_SPI_SCLK[] = { |
| Anna Bridge |
186:707f6e361f3e | 120 | { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 121 | { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 122 | { P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 123 | { P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 124 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 125 | }; |
| Anna Bridge |
186:707f6e361f3e | 126 | |
| Anna Bridge |
186:707f6e361f3e | 127 | const PinMap PinMap_SPI_MOSI[] = { |
| Anna Bridge |
186:707f6e361f3e | 128 | { P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 129 | { P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 130 | { P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 131 | { P5_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 132 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 133 | }; |
| Anna Bridge |
186:707f6e361f3e | 134 | |
| Anna Bridge |
186:707f6e361f3e | 135 | const PinMap PinMap_SPI_MISO[] = { |
| Anna Bridge |
186:707f6e361f3e | 136 | { P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 137 | { P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 138 | { P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 139 | { P5_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 140 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 141 | }; |
| Anna Bridge |
186:707f6e361f3e | 142 | |
| Anna Bridge |
186:707f6e361f3e | 143 | const PinMap PinMap_SPI_SSEL[] = { |
| Anna Bridge |
186:707f6e361f3e | 144 | { P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 145 | { P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 146 | { P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 147 | { P5_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ | MXC_F_IOMAN_SPIM_REQ_SR0_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK | MXC_F_IOMAN_SPIM_ACK_SR0_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 148 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 149 | }; |
| Anna Bridge |
186:707f6e361f3e | 150 | |
| Anna Bridge |
186:707f6e361f3e | 151 | const PinMap PinMap_SPI_QUAD[] = { |
| Anna Bridge |
186:707f6e361f3e | 152 | { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ, MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 153 | { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ, MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK}) }, |
| Anna Bridge |
186:707f6e361f3e | 154 | { P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ | MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK | MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK)}) }, |
| Anna Bridge |
186:707f6e361f3e | 155 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 156 | }; |
| Anna Bridge |
186:707f6e361f3e | 157 | |
| Anna Bridge |
186:707f6e361f3e | 158 | /************PWM***************/ |
| Anna Bridge |
186:707f6e361f3e | 159 | const PinMap PinMap_PWM[] = { |
| Anna Bridge |
186:707f6e361f3e | 160 | { P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, { P6_0, PWM_0, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 161 | { P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 162 | { P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 163 | { P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 164 | { P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 165 | { P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 166 | { P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 167 | { P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 168 | { P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 169 | { P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 170 | { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 171 | { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 172 | { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 173 | { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 174 | { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 175 | { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 }, |
| Anna Bridge |
186:707f6e361f3e | 176 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 177 | }; |
| Anna Bridge |
186:707f6e361f3e | 178 | |
| Anna Bridge |
186:707f6e361f3e | 179 | /************ADC***************/ |
| Anna Bridge |
186:707f6e361f3e | 180 | const PinMap PinMap_ADC[] = { |
| Anna Bridge |
186:707f6e361f3e | 181 | { AIN_0, ADC, ADC_CH_0 }, |
| Anna Bridge |
186:707f6e361f3e | 182 | { AIN_1, ADC, ADC_CH_1 }, |
| Anna Bridge |
186:707f6e361f3e | 183 | { AIN_2, ADC, ADC_CH_2 }, |
| Anna Bridge |
186:707f6e361f3e | 184 | { AIN_3, ADC, ADC_CH_3 }, |
| Anna Bridge |
186:707f6e361f3e | 185 | { AIN_4, ADC, ADC_CH_0_DIV_5 }, |
| Anna Bridge |
186:707f6e361f3e | 186 | { AIN_5, ADC, ADC_CH_1_DIV_5 }, |
| Anna Bridge |
186:707f6e361f3e | 187 | { AIN_6, ADC, ADC_CH_VDDB_DIV_4 }, |
| Anna Bridge |
186:707f6e361f3e | 188 | { AIN_7, ADC, ADC_CH_VDD18 }, |
| Anna Bridge |
186:707f6e361f3e | 189 | { AIN_8, ADC, ADC_CH_VDD12 }, |
| Anna Bridge |
186:707f6e361f3e | 190 | { AIN_9, ADC, ADC_CH_VRTC_DIV_2 }, |
| Anna Bridge |
186:707f6e361f3e | 191 | { AIN_10, ADC, ADC_CH_VDDIO_DIV_4 }, |
| Anna Bridge |
186:707f6e361f3e | 192 | { AIN_11, ADC, ADC_CH_VDDIOH_DIV_4 }, |
| Anna Bridge |
186:707f6e361f3e | 193 | { NC, NC, 0 } |
| Anna Bridge |
186:707f6e361f3e | 194 | }; |