Genadi Zawidowski / mbed-dev

mbed library sources. Supersedes mbed-src. Edited target satm32f446 for user USART3 pins

Dependents:   IGLOO_board

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c@188:3f10722804f9, 2018-07-30 (annotated)

Committer:
ua1arn
Date:
Mon Jul 30 12:31:10 2018 +0000
Revision:
188:3f10722804f9
Parent:
184:08ed48f1de7f 
before add multi-configuration USB descriptors

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 #include "rtc_api.h"
AnnaBridge 167:e84263d55307 19 #include "mbed_mktime.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 // ensure rtc is running (unchanged if already running)
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 /* Setup the RTC based on a time structure, ensuring RTC is enabled
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock
<> 144:ef7eb2e8f9f7 26 * - We want to use the 32khz clock, allowing for sleep mode
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * Most registers are not changed by a Reset
<> 144:ef7eb2e8f9f7 29 * - We must initialize these registers between power-on and setting the RTC into operation
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 * Clock Control Register
<> 144:ef7eb2e8f9f7 32 * RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
<> 144:ef7eb2e8f9f7 33 * RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
<> 144:ef7eb2e8f9f7 34 * RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 * The RTC may already be running, so we should set it up
<> 144:ef7eb2e8f9f7 37 * without impacting if it is the case
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 void rtc_init(void) {
<> 144:ef7eb2e8f9f7 41 // Return, if already enabled
<> 144:ef7eb2e8f9f7 42 if (LPC_RTC->CCR & 1)
<> 144:ef7eb2e8f9f7 43 return;
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 // Enable 1kHz output of 32kHz oscillator
<> 144:ef7eb2e8f9f7 46 LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
<> 144:ef7eb2e8f9f7 47 LPC_CREG->CREG0 |= (0x03 << 6) | (1 << 1) | (1 << 0);
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 // Enable RTC
<> 144:ef7eb2e8f9f7 50 do {
<> 144:ef7eb2e8f9f7 51 LPC_RTC->CCR |= 1 << 0;
<> 144:ef7eb2e8f9f7 52 } while ((LPC_RTC->CCR & 1) == 0);
<> 144:ef7eb2e8f9f7 53 }
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 void rtc_free(void) {
<> 144:ef7eb2e8f9f7 56 // [TODO]
<> 144:ef7eb2e8f9f7 57 }
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /*
<> 144:ef7eb2e8f9f7 60 * Little check routine to see if the RTC has been enabled
<> 144:ef7eb2e8f9f7 61 *
<> 144:ef7eb2e8f9f7 62 * Clock Control Register
<> 144:ef7eb2e8f9f7 63 * RTC_CCR[0] : 0 = Disabled, 1 = Enabled
<> 144:ef7eb2e8f9f7 64 *
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 int rtc_isenabled(void) {
<> 144:ef7eb2e8f9f7 67 return(((LPC_RTC->CCR) & 0x01) != 0);
<> 144:ef7eb2e8f9f7 68 }
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /*
<> 144:ef7eb2e8f9f7 71 * RTC Registers
<> 144:ef7eb2e8f9f7 72 * RTC_SEC Seconds 0-59
<> 144:ef7eb2e8f9f7 73 * RTC_MIN Minutes 0-59
<> 144:ef7eb2e8f9f7 74 * RTC_HOUR Hour 0-23
<> 144:ef7eb2e8f9f7 75 * RTC_DOM Day of Month 1-28..31
<> 144:ef7eb2e8f9f7 76 * RTC_DOW Day of Week 0-6
<> 144:ef7eb2e8f9f7 77 * RTC_DOY Day of Year 1-365
<> 144:ef7eb2e8f9f7 78 * RTC_MONTH Month 1-12
<> 144:ef7eb2e8f9f7 79 * RTC_YEAR Year 0-4095
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * struct tm
<> 144:ef7eb2e8f9f7 82 * tm_sec seconds after the minute 0-61
<> 144:ef7eb2e8f9f7 83 * tm_min minutes after the hour 0-59
<> 144:ef7eb2e8f9f7 84 * tm_hour hours since midnight 0-23
<> 144:ef7eb2e8f9f7 85 * tm_mday day of the month 1-31
<> 144:ef7eb2e8f9f7 86 * tm_mon months since January 0-11
<> 144:ef7eb2e8f9f7 87 * tm_year years since 1900
<> 144:ef7eb2e8f9f7 88 * tm_wday days since Sunday 0-6
<> 144:ef7eb2e8f9f7 89 * tm_yday days since January 1 0-365
<> 144:ef7eb2e8f9f7 90 * tm_isdst Daylight Saving Time flag
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92 time_t rtc_read(void) {
<> 144:ef7eb2e8f9f7 93 // Setup a tm structure based on the RTC
<> 144:ef7eb2e8f9f7 94 struct tm timeinfo;
<> 144:ef7eb2e8f9f7 95 timeinfo.tm_sec = LPC_RTC->TIME[RTC_TIMETYPE_SECOND];
<> 144:ef7eb2e8f9f7 96 timeinfo.tm_min = LPC_RTC->TIME[RTC_TIMETYPE_MINUTE];
<> 144:ef7eb2e8f9f7 97 timeinfo.tm_hour = LPC_RTC->TIME[RTC_TIMETYPE_HOUR];
<> 144:ef7eb2e8f9f7 98 timeinfo.tm_mday = LPC_RTC->TIME[RTC_TIMETYPE_DAYOFMONTH];
<> 144:ef7eb2e8f9f7 99 timeinfo.tm_wday = LPC_RTC->TIME[RTC_TIMETYPE_DAYOFWEEK];
<> 144:ef7eb2e8f9f7 100 timeinfo.tm_yday = LPC_RTC->TIME[RTC_TIMETYPE_DAYOFYEAR];
<> 144:ef7eb2e8f9f7 101 timeinfo.tm_mon = LPC_RTC->TIME[RTC_TIMETYPE_MONTH] - 1;
<> 144:ef7eb2e8f9f7 102 timeinfo.tm_year = LPC_RTC->TIME[RTC_TIMETYPE_YEAR] - 1900;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 // Convert to timestamp
AnnaBridge 184:08ed48f1de7f 105 time_t t;
AnnaBridge 184:08ed48f1de7f 106 if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
AnnaBridge 184:08ed48f1de7f 107 return 0;
AnnaBridge 184:08ed48f1de7f 108 }
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 return t;
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 void rtc_write(time_t t) {
<> 144:ef7eb2e8f9f7 114 // Convert the time in to a tm
AnnaBridge 167:e84263d55307 115 struct tm timeinfo;
AnnaBridge 184:08ed48f1de7f 116 if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
AnnaBridge 167:e84263d55307 117 return;
AnnaBridge 167:e84263d55307 118 }
AnnaBridge 184:08ed48f1de7f 119
<> 144:ef7eb2e8f9f7 120 // Pause clock, and clear counter register (clears us count)
<> 144:ef7eb2e8f9f7 121 LPC_RTC->CCR |= 2;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 // Set the RTC
AnnaBridge 167:e84263d55307 124 LPC_RTC->TIME[RTC_TIMETYPE_SECOND] = timeinfo.tm_sec;
AnnaBridge 167:e84263d55307 125 LPC_RTC->TIME[RTC_TIMETYPE_MINUTE] = timeinfo.tm_min;
AnnaBridge 167:e84263d55307 126 LPC_RTC->TIME[RTC_TIMETYPE_HOUR] = timeinfo.tm_hour;
AnnaBridge 167:e84263d55307 127 LPC_RTC->TIME[RTC_TIMETYPE_DAYOFMONTH] = timeinfo.tm_mday;
AnnaBridge 167:e84263d55307 128 LPC_RTC->TIME[RTC_TIMETYPE_DAYOFWEEK] = timeinfo.tm_wday;
AnnaBridge 167:e84263d55307 129 LPC_RTC->TIME[RTC_TIMETYPE_DAYOFYEAR] = timeinfo.tm_yday;
AnnaBridge 167:e84263d55307 130 LPC_RTC->TIME[RTC_TIMETYPE_MONTH] = timeinfo.tm_mon + 1;
AnnaBridge 167:e84263d55307 131 LPC_RTC->TIME[RTC_TIMETYPE_YEAR] = timeinfo.tm_year + 1900;
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 // Restart clock
<> 144:ef7eb2e8f9f7 134 LPC_RTC->CCR &= ~((uint32_t)2);
<> 144:ef7eb2e8f9f7 135 }