Genadi Zawidowski / IGLOO_board

boart test board

Dependencies:   USBDevice mbed-dev lwip

Fork of USBSerial_HelloWorld by Compass Yap

STM32_FMC.cpp@23:121b78470d39, 2018-08-03 (annotated)

Committer:
ua1arn
Date:
Fri Aug 03 05:41:14 2018 +0000
Revision:
23:121b78470d39
Parent:
20:4b2a3c310b61 
mistyped

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ua1arn 19:8b7595ced647 1 #include "mbed.h"
ua1arn 17:8279856460a8 2 #include "platform/mbed_critical.h"
ua1arn 17:8279856460a8 3 #include "platform/mbed_power_mgmt.h"
ua1arn 17:8279856460a8 4
ua1arn 17:8279856460a8 5 #include "platform/platform.h"
ua1arn 17:8279856460a8 6 #include "hal/pinmap.h"
ua1arn 17:8279856460a8 7
ua1arn 20:4b2a3c310b61 8 #define BLD446 1
ua1arn 19:8b7595ced647 9
ua1arn 19:8b7595ced647 10
ua1arn 20:4b2a3c310b61 11 #define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
ua1arn 19:8b7595ced647 12
ua1arn 19:8b7595ced647 13 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
ua1arn 19:8b7595ced647 14 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
ua1arn 19:8b7595ced647 15 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
ua1arn 19:8b7595ced647 16 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
ua1arn 19:8b7595ced647 17 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
ua1arn 19:8b7595ced647 18 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
ua1arn 19:8b7595ced647 19 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
ua1arn 19:8b7595ced647 20 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
ua1arn 19:8b7595ced647 21 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
ua1arn 20:4b2a3c310b61 22 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
ua1arn 20:4b2a3c310b61 23 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
ua1arn 19:8b7595ced647 24
ua1arn 19:8b7595ced647 25 #define REFRESH_COUNT ((uint32_t)0x056A) /* SDRAM refresh counter (90MHz SDRAM clock) */
ua1arn 19:8b7595ced647 26
ua1arn 19:8b7595ced647 27 /**
ua1arn 19:8b7595ced647 28 * @brief Perform the SDRAM exernal memory inialization sequence
ua1arn 19:8b7595ced647 29 * @param hsdram: SDRAM handle
ua1arn 19:8b7595ced647 30 * @param Command: Pointer to SDRAM command structure
ua1arn 19:8b7595ced647 31 * @retval None
ua1arn 19:8b7595ced647 32 */
ua1arn 20:4b2a3c310b61 33 static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram)
ua1arn 19:8b7595ced647 34 {
ua1arn 20:4b2a3c310b61 35 FMC_SDRAM_CommandTypeDef Command = { 0 };
ua1arn 20:4b2a3c310b61 36 #if BLD446
ua1arn 20:4b2a3c310b61 37 unsigned CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
ua1arn 20:4b2a3c310b61 38 #else
ua1arn 20:4b2a3c310b61 39 unsigned CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; // 429
ua1arn 20:4b2a3c310b61 40 #endif
ua1arn 20:4b2a3c310b61 41 uint32_t tmpmrd = 0;
ua1arn 19:8b7595ced647 42 /* Step 3: Configure a clock configuration enable command */
ua1arn 20:4b2a3c310b61 43 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
ua1arn 20:4b2a3c310b61 44 Command.CommandTarget = CommandTarget;
ua1arn 20:4b2a3c310b61 45 Command.AutoRefreshNumber = 1;
ua1arn 20:4b2a3c310b61 46 Command.ModeRegisterDefinition = 0;
ua1arn 19:8b7595ced647 47
ua1arn 19:8b7595ced647 48 /* Send the command */
ua1arn 20:4b2a3c310b61 49 HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
ua1arn 19:8b7595ced647 50
ua1arn 19:8b7595ced647 51 /* Step 4: Insert 100 ms delay */
ua1arn 19:8b7595ced647 52 wait((float)0.1);
ua1arn 19:8b7595ced647 53
ua1arn 19:8b7595ced647 54 /* Step 5: Configure a PALL (precharge all) command */
ua1arn 20:4b2a3c310b61 55 Command.CommandMode = FMC_SDRAM_CMD_PALL;
ua1arn 20:4b2a3c310b61 56 Command.CommandTarget = CommandTarget;
ua1arn 20:4b2a3c310b61 57 Command.AutoRefreshNumber = 1;
ua1arn 20:4b2a3c310b61 58 Command.ModeRegisterDefinition = 0;
ua1arn 19:8b7595ced647 59
ua1arn 19:8b7595ced647 60 /* Send the command */
ua1arn 20:4b2a3c310b61 61 HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
ua1arn 20:4b2a3c310b61 62 wait((float)0.1);
ua1arn 19:8b7595ced647 63
ua1arn 19:8b7595ced647 64 /* Step 6 : Configure a Auto-Refresh command */
ua1arn 20:4b2a3c310b61 65 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
ua1arn 20:4b2a3c310b61 66 Command.CommandTarget = CommandTarget;
ua1arn 20:4b2a3c310b61 67 Command.AutoRefreshNumber = 4;
ua1arn 20:4b2a3c310b61 68 Command.ModeRegisterDefinition = 0;
ua1arn 19:8b7595ced647 69
ua1arn 19:8b7595ced647 70 /* Send the command */
ua1arn 20:4b2a3c310b61 71 HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
ua1arn 20:4b2a3c310b61 72 wait((float)0.1);
ua1arn 19:8b7595ced647 73
ua1arn 19:8b7595ced647 74 /* Step 7: Program the external memory mode register */
ua1arn 19:8b7595ced647 75 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
ua1arn 19:8b7595ced647 76 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
ua1arn 19:8b7595ced647 77 SDRAM_MODEREG_CAS_LATENCY_2 |
ua1arn 19:8b7595ced647 78 SDRAM_MODEREG_OPERATING_MODE_STANDARD |
ua1arn 19:8b7595ced647 79 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
ua1arn 19:8b7595ced647 80
ua1arn 20:4b2a3c310b61 81 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
ua1arn 20:4b2a3c310b61 82 Command.CommandTarget = CommandTarget;
ua1arn 20:4b2a3c310b61 83 Command.AutoRefreshNumber = 1;
ua1arn 20:4b2a3c310b61 84 Command.ModeRegisterDefinition = tmpmrd;
ua1arn 19:8b7595ced647 85
ua1arn 19:8b7595ced647 86 /* Send the command */
ua1arn 20:4b2a3c310b61 87 HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
ua1arn 20:4b2a3c310b61 88 wait((float)0.1);
ua1arn 19:8b7595ced647 89
ua1arn 19:8b7595ced647 90 /* Step 8: Set the refresh rate counter */
ua1arn 19:8b7595ced647 91 /* (15.62 us x Freq) - 20 */
ua1arn 19:8b7595ced647 92 /* Set the device refresh counter */
ua1arn 19:8b7595ced647 93 HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
ua1arn 20:4b2a3c310b61 94 wait((float)0.1);
ua1arn 19:8b7595ced647 95 }
ua1arn 19:8b7595ced647 96
ua1arn 18:c276f3d01630 97 typedef class fmc
ua1arn 17:8279856460a8 98 {
ua1arn 17:8279856460a8 99 public:
ua1arn 17:8279856460a8 100
ua1arn 18:c276f3d01630 101 ~fmc() {
ua1arn 17:8279856460a8 102 core_util_critical_section_enter();
ua1arn 17:8279856460a8 103 unlock_deep_sleep();
ua1arn 17:8279856460a8 104 core_util_critical_section_exit();
ua1arn 17:8279856460a8 105 }
ua1arn 17:8279856460a8 106
ua1arn 18:c276f3d01630 107 fmc() :
ua1arn 17:8279856460a8 108 _deep_sleep_locked(false) {
ua1arn 17:8279856460a8 109 core_util_critical_section_enter();
ua1arn 18:c276f3d01630 110
ua1arn 20:4b2a3c310b61 111 __HAL_RCC_GPIOB_CLK_ENABLE(); // 429
ua1arn 17:8279856460a8 112 __HAL_RCC_GPIOC_CLK_ENABLE();
ua1arn 17:8279856460a8 113 __HAL_RCC_GPIOD_CLK_ENABLE();
ua1arn 17:8279856460a8 114 __HAL_RCC_GPIOE_CLK_ENABLE();
ua1arn 17:8279856460a8 115 __HAL_RCC_GPIOF_CLK_ENABLE();
ua1arn 17:8279856460a8 116 __HAL_RCC_GPIOG_CLK_ENABLE();
ua1arn 17:8279856460a8 117
ua1arn 18:c276f3d01630 118
ua1arn 18:c276f3d01630 119 /** FMC GPIO Configuration
ua1arn 18:c276f3d01630 120 PF0 ------> FMC_A0
ua1arn 18:c276f3d01630 121 PF1 ------> FMC_A1
ua1arn 18:c276f3d01630 122 PF2 ------> FMC_A2
ua1arn 18:c276f3d01630 123 PF3 ------> FMC_A3
ua1arn 18:c276f3d01630 124 PF4 ------> FMC_A4
ua1arn 18:c276f3d01630 125 PF5 ------> FMC_A5
ua1arn 18:c276f3d01630 126 PC0 ------> FMC_SDNWE
ua1arn 18:c276f3d01630 127 PC2 ------> FMC_SDNE0
ua1arn 18:c276f3d01630 128 PC3 ------> FMC_SDCKE0
ua1arn 18:c276f3d01630 129 PF11 ------> FMC_SDNRAS
ua1arn 18:c276f3d01630 130 PF12 ------> FMC_A6
ua1arn 18:c276f3d01630 131 PF13 ------> FMC_A7
ua1arn 18:c276f3d01630 132 PF14 ------> FMC_A8
ua1arn 18:c276f3d01630 133 PF15 ------> FMC_A9
ua1arn 18:c276f3d01630 134 PG0 ------> FMC_A10
ua1arn 18:c276f3d01630 135 PG1 ------> FMC_A11
ua1arn 18:c276f3d01630 136 PE7 ------> FMC_D4
ua1arn 18:c276f3d01630 137 PE8 ------> FMC_D5
ua1arn 18:c276f3d01630 138 PE9 ------> FMC_D6
ua1arn 18:c276f3d01630 139 PE10 ------> FMC_D7
ua1arn 18:c276f3d01630 140 PE11 ------> FMC_D8
ua1arn 18:c276f3d01630 141 PE12 ------> FMC_D9
ua1arn 18:c276f3d01630 142 PE13 ------> FMC_D10
ua1arn 18:c276f3d01630 143 PE14 ------> FMC_D11
ua1arn 18:c276f3d01630 144 PE15 ------> FMC_D12
ua1arn 18:c276f3d01630 145 PD8 ------> FMC_D13
ua1arn 18:c276f3d01630 146 PD9 ------> FMC_D14
ua1arn 18:c276f3d01630 147 PD10 ------> FMC_D15
ua1arn 18:c276f3d01630 148 PD14 ------> FMC_D0
ua1arn 18:c276f3d01630 149 PD15 ------> FMC_D1
ua1arn 18:c276f3d01630 150 PG4 ------> FMC_BA0
ua1arn 18:c276f3d01630 151 PG5 ------> FMC_BA1
ua1arn 18:c276f3d01630 152 PG8 ------> FMC_SDCLK
ua1arn 18:c276f3d01630 153 PD0 ------> FMC_D2
ua1arn 18:c276f3d01630 154 PD1 ------> FMC_D3
ua1arn 18:c276f3d01630 155 PG15 ------> FMC_SDNCAS
ua1arn 18:c276f3d01630 156 PE0 ------> FMC_NBL0
ua1arn 18:c276f3d01630 157 PE1 ------> FMC_NBL1
ua1arn 18:c276f3d01630 158 */
ua1arn 18:c276f3d01630 159 pin_function(PF_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A0
ua1arn 18:c276f3d01630 160 pin_function(PF_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A1
ua1arn 18:c276f3d01630 161 pin_function(PF_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A2
ua1arn 18:c276f3d01630 162 pin_function(PF_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A3
ua1arn 18:c276f3d01630 163 pin_function(PF_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A4
ua1arn 18:c276f3d01630 164 pin_function(PF_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A5
ua1arn 18:c276f3d01630 165 pin_function(PF_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A6
ua1arn 18:c276f3d01630 166 pin_function(PF_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A7
ua1arn 18:c276f3d01630 167 pin_function(PF_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A8
ua1arn 18:c276f3d01630 168 pin_function(PF_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A9
ua1arn 18:c276f3d01630 169 pin_function(PG_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A10
ua1arn 18:c276f3d01630 170 pin_function(PG_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A11
ua1arn 19:8b7595ced647 171
ua1arn 19:8b7595ced647 172 pin_function(PD_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D0
ua1arn 19:8b7595ced647 173 pin_function(PD_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D1
ua1arn 19:8b7595ced647 174 pin_function(PD_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D2
ua1arn 19:8b7595ced647 175 pin_function(PD_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D3
ua1arn 18:c276f3d01630 176 pin_function(PE_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D4
ua1arn 18:c276f3d01630 177 pin_function(PE_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D5
ua1arn 18:c276f3d01630 178 pin_function(PE_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D6
ua1arn 18:c276f3d01630 179 pin_function(PE_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D7
ua1arn 18:c276f3d01630 180 pin_function(PE_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D8
ua1arn 18:c276f3d01630 181 pin_function(PE_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D9
ua1arn 18:c276f3d01630 182 pin_function(PE_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D10
ua1arn 18:c276f3d01630 183 pin_function(PE_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D11
ua1arn 18:c276f3d01630 184 pin_function(PE_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D12
ua1arn 18:c276f3d01630 185 pin_function(PD_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D13
ua1arn 18:c276f3d01630 186 pin_function(PD_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D14
ua1arn 18:c276f3d01630 187 pin_function(PD_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D15
ua1arn 19:8b7595ced647 188
ua1arn 20:4b2a3c310b61 189 #if BLD446
ua1arn 20:4b2a3c310b61 190 // STM32F446
ua1arn 20:4b2a3c310b61 191 pin_function(PC_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDCKE0
ua1arn 20:4b2a3c310b61 192 pin_function(PC_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNE0
ua1arn 20:4b2a3c310b61 193 #else
ua1arn 20:4b2a3c310b61 194 // STM32F429
ua1arn 20:4b2a3c310b61 195 pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDCKE1
ua1arn 20:4b2a3c310b61 196 pin_function(PB_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNE1
ua1arn 20:4b2a3c310b61 197 #endif
ua1arn 20:4b2a3c310b61 198 pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNWE
ua1arn 20:4b2a3c310b61 199 pin_function(PE_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_NBL0
ua1arn 20:4b2a3c310b61 200 pin_function(PE_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_NBL1
ua1arn 20:4b2a3c310b61 201 pin_function(PF_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNRAS
ua1arn 18:c276f3d01630 202 pin_function(PG_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_BA0
ua1arn 18:c276f3d01630 203 pin_function(PG_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_BA1
ua1arn 18:c276f3d01630 204 pin_function(PG_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDCLK
ua1arn 18:c276f3d01630 205 pin_function(PG_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNCAS
ua1arn 17:8279856460a8 206
ua1arn 17:8279856460a8 207 __HAL_RCC_FMC_CLK_ENABLE();
ua1arn 18:c276f3d01630 208
ua1arn 19:8b7595ced647 209 FMC_SDRAM_TimingTypeDef SdramTiming = { 0 };
ua1arn 18:c276f3d01630 210 /** Perform the SDRAM1 memory initialization sequence
ua1arn 18:c276f3d01630 211 */
ua1arn 19:8b7595ced647 212 SDRAM_HandleTypeDef hsdram1 = { 0 };
ua1arn 18:c276f3d01630 213
ua1arn 19:8b7595ced647 214 hsdram1.Instance = FMC_Bank5_6;
ua1arn 20:4b2a3c310b61 215
ua1arn 18:c276f3d01630 216 /* hsdram1.Init */
ua1arn 20:4b2a3c310b61 217 #if BLD446
ua1arn 20:4b2a3c310b61 218 hsdram1.Init.SDBank = FMC_SDRAM_BANK1; // 446
ua1arn 20:4b2a3c310b61 219 #else
ua1arn 20:4b2a3c310b61 220 hsdram1.Init.SDBank = FMC_SDRAM_BANK2; // 429
ua1arn 20:4b2a3c310b61 221 #endif
ua1arn 18:c276f3d01630 222 hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
ua1arn 18:c276f3d01630 223 hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
ua1arn 18:c276f3d01630 224 hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
ua1arn 18:c276f3d01630 225 hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
ua1arn 18:c276f3d01630 226 hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
ua1arn 18:c276f3d01630 227 hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
ua1arn 18:c276f3d01630 228 hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3;
ua1arn 18:c276f3d01630 229 hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
ua1arn 18:c276f3d01630 230 hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
ua1arn 18:c276f3d01630 231 /* SdramTiming */
ua1arn 18:c276f3d01630 232 SdramTiming.LoadToActiveDelay = 2;
ua1arn 18:c276f3d01630 233 SdramTiming.ExitSelfRefreshDelay = 7;
ua1arn 18:c276f3d01630 234 SdramTiming.SelfRefreshTime = 4;
ua1arn 18:c276f3d01630 235 SdramTiming.RowCycleDelay = 2;
ua1arn 18:c276f3d01630 236 SdramTiming.WriteRecoveryTime = 2;
ua1arn 18:c276f3d01630 237 SdramTiming.RPDelay = 2;
ua1arn 18:c276f3d01630 238 SdramTiming.RCDDelay = 2;
ua1arn 18:c276f3d01630 239
ua1arn 18:c276f3d01630 240 if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) {
ua1arn 18:c276f3d01630 241 //_Error_Handler(__FILE__, __LINE__);
ua1arn 18:c276f3d01630 242 }
ua1arn 19:8b7595ced647 243 /* Program the SDRAM external device */
ua1arn 20:4b2a3c310b61 244 SDRAM_Initialization_Sequence(&hsdram1);
ua1arn 18:c276f3d01630 245
ua1arn 17:8279856460a8 246 core_util_critical_section_exit();
ua1arn 18:c276f3d01630 247 }
ua1arn 17:8279856460a8 248
ua1arn 17:8279856460a8 249 protected:
ua1arn 17:8279856460a8 250 /** Lock deep sleep only if it is not yet locked */
ua1arn 17:8279856460a8 251 void lock_deep_sleep() {
ua1arn 17:8279856460a8 252 if (_deep_sleep_locked == false) {
ua1arn 17:8279856460a8 253 sleep_manager_lock_deep_sleep();
ua1arn 17:8279856460a8 254 _deep_sleep_locked = true;
ua1arn 17:8279856460a8 255 }
ua1arn 17:8279856460a8 256 }
ua1arn 17:8279856460a8 257
ua1arn 17:8279856460a8 258 /** Unlock deep sleep in case it is locked */
ua1arn 17:8279856460a8 259 void unlock_deep_sleep() {
ua1arn 17:8279856460a8 260 if (_deep_sleep_locked == true) {
ua1arn 17:8279856460a8 261 sleep_manager_unlock_deep_sleep();
ua1arn 17:8279856460a8 262 _deep_sleep_locked = false;
ua1arn 17:8279856460a8 263 }
ua1arn 17:8279856460a8 264 }
ua1arn 17:8279856460a8 265
ua1arn 17:8279856460a8 266 bool _deep_sleep_locked;
ua1arn 17:8279856460a8 267
ua1arn 17:8279856460a8 268 } FMC;
ua1arn 17:8279856460a8 269
ua1arn 20:4b2a3c310b61 270 //static FMC fmc;