FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

Users » tushki7 » Code » FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_NUCLEO_L152RE/stm32l152xe.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1	/**
tushki7	0:60d829a0353a	2	******************************************************************************
tushki7	0:60d829a0353a	3	* @file stm32l152xe.h
tushki7	0:60d829a0353a	4	* @author MCD Application Team
tushki7	0:60d829a0353a	5	* @version V2.0.0
tushki7	0:60d829a0353a	6	* @date 5-September-2014
tushki7	0:60d829a0353a	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
tushki7	0:60d829a0353a	8	* This file contains all the peripheral register's definitions, bits
tushki7	0:60d829a0353a	9	* definitions and memory mapping for STM32L1xx devices.
tushki7	0:60d829a0353a	10	*
tushki7	0:60d829a0353a	11	* This file contains:
tushki7	0:60d829a0353a	12	* - Data structures and the address mapping for all peripherals
tushki7	0:60d829a0353a	13	* - Peripheral's registers declarations and bits definition
tushki7	0:60d829a0353a	14	* - Macros to access peripherals registers hardware
tushki7	0:60d829a0353a	15	*
tushki7	0:60d829a0353a	16	******************************************************************************
tushki7	0:60d829a0353a	17	* @attention
tushki7	0:60d829a0353a	18	*
tushki7	0:60d829a0353a	19	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
tushki7	0:60d829a0353a	20	*
tushki7	0:60d829a0353a	21	* Redistribution and use in source and binary forms, with or without modification,
tushki7	0:60d829a0353a	22	* are permitted provided that the following conditions are met:
tushki7	0:60d829a0353a	23	* 1. Redistributions of source code must retain the above copyright notice,
tushki7	0:60d829a0353a	24	* this list of conditions and the following disclaimer.
tushki7	0:60d829a0353a	25	* 2. Redistributions in binary form must reproduce the above copyright notice,
tushki7	0:60d829a0353a	26	* this list of conditions and the following disclaimer in the documentation
tushki7	0:60d829a0353a	27	* and/or other materials provided with the distribution.
tushki7	0:60d829a0353a	28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
tushki7	0:60d829a0353a	29	* may be used to endorse or promote products derived from this software
tushki7	0:60d829a0353a	30	* without specific prior written permission.
tushki7	0:60d829a0353a	31	*
tushki7	0:60d829a0353a	32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7	0:60d829a0353a	33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7	0:60d829a0353a	34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7	0:60d829a0353a	35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
tushki7	0:60d829a0353a	36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tushki7	0:60d829a0353a	37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
tushki7	0:60d829a0353a	38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
tushki7	0:60d829a0353a	39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
tushki7	0:60d829a0353a	40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
tushki7	0:60d829a0353a	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7	0:60d829a0353a	42	*
tushki7	0:60d829a0353a	43	******************************************************************************
tushki7	0:60d829a0353a	44	*/
tushki7	0:60d829a0353a	45
tushki7	0:60d829a0353a	46	/** @addtogroup CMSIS
tushki7	0:60d829a0353a	47	* @{
tushki7	0:60d829a0353a	48	*/
tushki7	0:60d829a0353a	49
tushki7	0:60d829a0353a	50	/** @addtogroup stm32l152xe
tushki7	0:60d829a0353a	51	* @{
tushki7	0:60d829a0353a	52	*/
tushki7	0:60d829a0353a	53
tushki7	0:60d829a0353a	54	#ifndef __STM32L152xE_H
tushki7	0:60d829a0353a	55	#define __STM32L152xE_H
tushki7	0:60d829a0353a	56
tushki7	0:60d829a0353a	57	#ifdef __cplusplus
tushki7	0:60d829a0353a	58	extern "C" {
tushki7	0:60d829a0353a	59	#endif
tushki7	0:60d829a0353a	60
tushki7	0:60d829a0353a	61
tushki7	0:60d829a0353a	62	/** @addtogroup Configuration_section_for_CMSIS
tushki7	0:60d829a0353a	63	* @{
tushki7	0:60d829a0353a	64	*/
tushki7	0:60d829a0353a	65	/**
tushki7	0:60d829a0353a	66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
tushki7	0:60d829a0353a	67	*/
tushki7	0:60d829a0353a	68	#define __CM3_REV 0x200 /!< Cortex-M3 Revision r2p0 /
tushki7	0:60d829a0353a	69	#define __MPU_PRESENT 1 /!< STM32L1xx provides MPU /
tushki7	0:60d829a0353a	70	#define __NVIC_PRIO_BITS 4 /!< STM32L1xx uses 4 Bits for the Priority Levels /
tushki7	0:60d829a0353a	71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
tushki7	0:60d829a0353a	72
tushki7	0:60d829a0353a	73	/**
tushki7	0:60d829a0353a	74	* @}
tushki7	0:60d829a0353a	75	*/
tushki7	0:60d829a0353a	76
tushki7	0:60d829a0353a	77	/** @addtogroup Peripheral_interrupt_number_definition
tushki7	0:60d829a0353a	78	* @{
tushki7	0:60d829a0353a	79	*/
tushki7	0:60d829a0353a	80
tushki7	0:60d829a0353a	81	/**
tushki7	0:60d829a0353a	82	* @brief STM32L1xx Interrupt Number Definition, according to the selected device
tushki7	0:60d829a0353a	83	* in @ref Library_configuration_section
tushki7	0:60d829a0353a	84	*/
tushki7	0:60d829a0353a	85
tushki7	0:60d829a0353a	86	/!< Interrupt Number Definition /
tushki7	0:60d829a0353a	87	typedef enum
tushki7	0:60d829a0353a	88	{
tushki7	0:60d829a0353a	89	/**** Cortex-M3 Processor Exceptions Numbers ****************************************************/
tushki7	0:60d829a0353a	90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
tushki7	0:60d829a0353a	91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
tushki7	0:60d829a0353a	92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
tushki7	0:60d829a0353a	93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
tushki7	0:60d829a0353a	94	SVC_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
tushki7	0:60d829a0353a	95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
tushki7	0:60d829a0353a	96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
tushki7	0:60d829a0353a	97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
tushki7	0:60d829a0353a	98
tushki7	0:60d829a0353a	99	/**** STM32L specific Interrupt Numbers *********************************************************/
tushki7	0:60d829a0353a	100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
tushki7	0:60d829a0353a	101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
tushki7	0:60d829a0353a	102	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
tushki7	0:60d829a0353a	103	RTC_WKUP_IRQn = 3, /!< RTC Wakeup Timer through EXTI Line Interrupt /
tushki7	0:60d829a0353a	104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
tushki7	0:60d829a0353a	105	RCC_IRQn = 5, /!< RCC global Interrupt /
tushki7	0:60d829a0353a	106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
tushki7	0:60d829a0353a	107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
tushki7	0:60d829a0353a	108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
tushki7	0:60d829a0353a	109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
tushki7	0:60d829a0353a	110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
tushki7	0:60d829a0353a	111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
tushki7	0:60d829a0353a	112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
tushki7	0:60d829a0353a	113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
tushki7	0:60d829a0353a	114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
tushki7	0:60d829a0353a	115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
tushki7	0:60d829a0353a	116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
tushki7	0:60d829a0353a	117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
tushki7	0:60d829a0353a	118	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
tushki7	0:60d829a0353a	119	USB_HP_IRQn = 19, /!< USB High Priority Interrupt /
tushki7	0:60d829a0353a	120	USB_LP_IRQn = 20, /!< USB Low Priority Interrupt /
tushki7	0:60d829a0353a	121	DAC_IRQn = 21, /!< DAC Interrupt /
tushki7	0:60d829a0353a	122	COMP_IRQn = 22, /!< Comparator through EXTI Line Interrupt /
tushki7	0:60d829a0353a	123	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
tushki7	0:60d829a0353a	124	LCD_IRQn = 24, /!< LCD Interrupt /
tushki7	0:60d829a0353a	125	TIM9_IRQn = 25, /!< TIM9 global Interrupt /
tushki7	0:60d829a0353a	126	TIM10_IRQn = 26, /!< TIM10 global Interrupt /
tushki7	0:60d829a0353a	127	TIM11_IRQn = 27, /!< TIM11 global Interrupt /
tushki7	0:60d829a0353a	128	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
tushki7	0:60d829a0353a	129	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
tushki7	0:60d829a0353a	130	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
tushki7	0:60d829a0353a	131	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
tushki7	0:60d829a0353a	132	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
tushki7	0:60d829a0353a	133	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
tushki7	0:60d829a0353a	134	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
tushki7	0:60d829a0353a	135	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
tushki7	0:60d829a0353a	136	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
tushki7	0:60d829a0353a	137	USART1_IRQn = 37, /!< USART1 global Interrupt /
tushki7	0:60d829a0353a	138	USART2_IRQn = 38, /!< USART2 global Interrupt /
tushki7	0:60d829a0353a	139	USART3_IRQn = 39, /!< USART3 global Interrupt /
tushki7	0:60d829a0353a	140	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
tushki7	0:60d829a0353a	141	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
tushki7	0:60d829a0353a	142	USB_FS_WKUP_IRQn = 42, /!< USB FS WakeUp from suspend through EXTI Line Interrupt /
tushki7	0:60d829a0353a	143	TIM6_IRQn = 43, /!< TIM6 global Interrupt /
tushki7	0:60d829a0353a	144	TIM7_IRQn = 44, /!< TIM7 global Interrupt /
tushki7	0:60d829a0353a	145	TIM5_IRQn = 46, /!< TIM5 global Interrupt /
tushki7	0:60d829a0353a	146	SPI3_IRQn = 47, /!< SPI3 global Interrupt /
tushki7	0:60d829a0353a	147	UART4_IRQn = 48, /!< UART4 global Interrupt /
tushki7	0:60d829a0353a	148	UART5_IRQn = 49, /!< UART5 global Interrupt /
tushki7	0:60d829a0353a	149	DMA2_Channel1_IRQn = 50, /!< DMA2 Channel 1 global Interrupt /
tushki7	0:60d829a0353a	150	DMA2_Channel2_IRQn = 51, /!< DMA2 Channel 2 global Interrupt /
tushki7	0:60d829a0353a	151	DMA2_Channel3_IRQn = 52, /!< DMA2 Channel 3 global Interrupt /
tushki7	0:60d829a0353a	152	DMA2_Channel4_IRQn = 53, /!< DMA2 Channel 4 global Interrupt /
tushki7	0:60d829a0353a	153	DMA2_Channel5_IRQn = 54, /!< DMA2 Channel 5 global Interrupt /
tushki7	0:60d829a0353a	154	COMP_ACQ_IRQn = 56 /!< Comparator Channel Acquisition global Interrupt /
tushki7	0:60d829a0353a	155	} IRQn_Type;
tushki7	0:60d829a0353a	156
tushki7	0:60d829a0353a	157	/**
tushki7	0:60d829a0353a	158	* @}
tushki7	0:60d829a0353a	159	*/
tushki7	0:60d829a0353a	160
tushki7	0:60d829a0353a	161	#include "core_cm3.h"
tushki7	0:60d829a0353a	162	#include "system_stm32l1xx.h"
tushki7	0:60d829a0353a	163	#include <stdint.h>
tushki7	0:60d829a0353a	164
tushki7	0:60d829a0353a	165	/** @addtogroup Peripheral_registers_structures
tushki7	0:60d829a0353a	166	* @{
tushki7	0:60d829a0353a	167	*/
tushki7	0:60d829a0353a	168
tushki7	0:60d829a0353a	169	/**
tushki7	0:60d829a0353a	170	* @brief Analog to Digital Converter
tushki7	0:60d829a0353a	171	*/
tushki7	0:60d829a0353a	172
tushki7	0:60d829a0353a	173	typedef struct
tushki7	0:60d829a0353a	174	{
tushki7	0:60d829a0353a	175	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
tushki7	0:60d829a0353a	176	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
tushki7	0:60d829a0353a	177	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
tushki7	0:60d829a0353a	178	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
tushki7	0:60d829a0353a	179	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
tushki7	0:60d829a0353a	180	__IO uint32_t SMPR3; /!< ADC sample time register 3, Address offset: 0x14 /
tushki7	0:60d829a0353a	181	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x18 /
tushki7	0:60d829a0353a	182	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x1C /
tushki7	0:60d829a0353a	183	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x20 /
tushki7	0:60d829a0353a	184	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x24 /
tushki7	0:60d829a0353a	185	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x28 /
tushki7	0:60d829a0353a	186	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x2C /
tushki7	0:60d829a0353a	187	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
tushki7	0:60d829a0353a	188	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
tushki7	0:60d829a0353a	189	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
tushki7	0:60d829a0353a	190	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
tushki7	0:60d829a0353a	191	__IO uint32_t SQR5; /!< ADC regular sequence register 5, Address offset: 0x40 /
tushki7	0:60d829a0353a	192	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x44 /
tushki7	0:60d829a0353a	193	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x48 /
tushki7	0:60d829a0353a	194	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x4C /
tushki7	0:60d829a0353a	195	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x50 /
tushki7	0:60d829a0353a	196	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x54 /
tushki7	0:60d829a0353a	197	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x58 /
tushki7	0:60d829a0353a	198	__IO uint32_t SMPR0; /!< ADC sample time register 0, Address offset: 0x5C /
tushki7	0:60d829a0353a	199	} ADC_TypeDef;
tushki7	0:60d829a0353a	200
tushki7	0:60d829a0353a	201	typedef struct
tushki7	0:60d829a0353a	202	{
tushki7	0:60d829a0353a	203	__IO uint32_t CSR; /!< ADC common status register, Address offset: ADC1 base address + 0x300 /
tushki7	0:60d829a0353a	204	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
tushki7	0:60d829a0353a	205	} ADC_Common_TypeDef;
tushki7	0:60d829a0353a	206
tushki7	0:60d829a0353a	207	/**
tushki7	0:60d829a0353a	208	* @brief Comparator
tushki7	0:60d829a0353a	209	*/
tushki7	0:60d829a0353a	210
tushki7	0:60d829a0353a	211	typedef struct
tushki7	0:60d829a0353a	212	{
tushki7	0:60d829a0353a	213	__IO uint32_t CSR; /!< COMP comparator control and status register, Address offset: 0x00 /
tushki7	0:60d829a0353a	214	} COMP_TypeDef;
tushki7	0:60d829a0353a	215
tushki7	0:60d829a0353a	216	/**
tushki7	0:60d829a0353a	217	* @brief CRC calculation unit
tushki7	0:60d829a0353a	218	*/
tushki7	0:60d829a0353a	219
tushki7	0:60d829a0353a	220	typedef struct
tushki7	0:60d829a0353a	221	{
tushki7	0:60d829a0353a	222	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
tushki7	0:60d829a0353a	223	__IO uint32_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
tushki7	0:60d829a0353a	224	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
tushki7	0:60d829a0353a	225	} CRC_TypeDef;
tushki7	0:60d829a0353a	226
tushki7	0:60d829a0353a	227	/**
tushki7	0:60d829a0353a	228	* @brief Digital to Analog Converter
tushki7	0:60d829a0353a	229	*/
tushki7	0:60d829a0353a	230
tushki7	0:60d829a0353a	231	typedef struct
tushki7	0:60d829a0353a	232	{
tushki7	0:60d829a0353a	233	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
tushki7	0:60d829a0353a	234	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
tushki7	0:60d829a0353a	235	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
tushki7	0:60d829a0353a	236	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
tushki7	0:60d829a0353a	237	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
tushki7	0:60d829a0353a	238	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
tushki7	0:60d829a0353a	239	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
tushki7	0:60d829a0353a	240	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
tushki7	0:60d829a0353a	241	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
tushki7	0:60d829a0353a	242	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
tushki7	0:60d829a0353a	243	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
tushki7	0:60d829a0353a	244	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
tushki7	0:60d829a0353a	245	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
tushki7	0:60d829a0353a	246	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
tushki7	0:60d829a0353a	247	} DAC_TypeDef;
tushki7	0:60d829a0353a	248
tushki7	0:60d829a0353a	249	/**
tushki7	0:60d829a0353a	250	* @brief Debug MCU
tushki7	0:60d829a0353a	251	*/
tushki7	0:60d829a0353a	252
tushki7	0:60d829a0353a	253	typedef struct
tushki7	0:60d829a0353a	254	{
tushki7	0:60d829a0353a	255	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
tushki7	0:60d829a0353a	256	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
tushki7	0:60d829a0353a	257	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
tushki7	0:60d829a0353a	258	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
tushki7	0:60d829a0353a	259	}DBGMCU_TypeDef;
tushki7	0:60d829a0353a	260
tushki7	0:60d829a0353a	261	/**
tushki7	0:60d829a0353a	262	* @brief DMA Controller
tushki7	0:60d829a0353a	263	*/
tushki7	0:60d829a0353a	264
tushki7	0:60d829a0353a	265	typedef struct
tushki7	0:60d829a0353a	266	{
tushki7	0:60d829a0353a	267	__IO uint32_t CCR; /!< DMA channel x configuration register /
tushki7	0:60d829a0353a	268	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
tushki7	0:60d829a0353a	269	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
tushki7	0:60d829a0353a	270	__IO uint32_t CMAR; /!< DMA channel x memory address register /
tushki7	0:60d829a0353a	271	} DMA_Channel_TypeDef;
tushki7	0:60d829a0353a	272
tushki7	0:60d829a0353a	273	typedef struct
tushki7	0:60d829a0353a	274	{
tushki7	0:60d829a0353a	275	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
tushki7	0:60d829a0353a	276	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
tushki7	0:60d829a0353a	277	} DMA_TypeDef;
tushki7	0:60d829a0353a	278
tushki7	0:60d829a0353a	279	/**
tushki7	0:60d829a0353a	280	* @brief External Interrupt/Event Controller
tushki7	0:60d829a0353a	281	*/
tushki7	0:60d829a0353a	282
tushki7	0:60d829a0353a	283	typedef struct
tushki7	0:60d829a0353a	284	{
tushki7	0:60d829a0353a	285	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
tushki7	0:60d829a0353a	286	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
tushki7	0:60d829a0353a	287	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
tushki7	0:60d829a0353a	288	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
tushki7	0:60d829a0353a	289	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
tushki7	0:60d829a0353a	290	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
tushki7	0:60d829a0353a	291	} EXTI_TypeDef;
tushki7	0:60d829a0353a	292
tushki7	0:60d829a0353a	293	/**
tushki7	0:60d829a0353a	294	* @brief FLASH Registers
tushki7	0:60d829a0353a	295	*/
tushki7	0:60d829a0353a	296	typedef struct
tushki7	0:60d829a0353a	297	{
tushki7	0:60d829a0353a	298	__IO uint32_t ACR; /!< Access control register, Address offset: 0x00 /
tushki7	0:60d829a0353a	299	__IO uint32_t PECR; /!< Program/erase control register, Address offset: 0x04 /
tushki7	0:60d829a0353a	300	__IO uint32_t PDKEYR; /!< Power down key register, Address offset: 0x08 /
tushki7	0:60d829a0353a	301	__IO uint32_t PEKEYR; /!< Program/erase key register, Address offset: 0x0c /
tushki7	0:60d829a0353a	302	__IO uint32_t PRGKEYR; /!< Program memory key register, Address offset: 0x10 /
tushki7	0:60d829a0353a	303	__IO uint32_t OPTKEYR; /!< Option byte key register, Address offset: 0x14 /
tushki7	0:60d829a0353a	304	__IO uint32_t SR; /!< Status register, Address offset: 0x18 /
tushki7	0:60d829a0353a	305	__IO uint32_t OBR; /!< Option byte register, Address offset: 0x1c /
tushki7	0:60d829a0353a	306	__IO uint32_t WRPR1; /!< Write protection register 1, Address offset: 0x20 /
tushki7	0:60d829a0353a	307	uint32_t RESERVED[23]; /!< Reserved, Address offset: 0x24 /
tushki7	0:60d829a0353a	308	__IO uint32_t WRPR2; /!< Write protection register 2, Address offset: 0x80 /
tushki7	0:60d829a0353a	309	__IO uint32_t WRPR3; /!< Write protection register 3, Address offset: 0x84 /
tushki7	0:60d829a0353a	310	__IO uint32_t WRPR4; /!< Write protection register 4, Address offset: 0x88 /
tushki7	0:60d829a0353a	311	} FLASH_TypeDef;
tushki7	0:60d829a0353a	312
tushki7	0:60d829a0353a	313	/**
tushki7	0:60d829a0353a	314	* @brief Option Bytes Registers
tushki7	0:60d829a0353a	315	*/
tushki7	0:60d829a0353a	316	typedef struct
tushki7	0:60d829a0353a	317	{
tushki7	0:60d829a0353a	318	__IO uint32_t RDP; /!< Read protection register, Address offset: 0x00 /
tushki7	0:60d829a0353a	319	__IO uint32_t USER; /!< user register, Address offset: 0x04 /
tushki7	0:60d829a0353a	320	__IO uint32_t WRP01; /!< write protection register 0 1, Address offset: 0x08 /
tushki7	0:60d829a0353a	321	__IO uint32_t WRP23; /!< write protection register 2 3, Address offset: 0x0C /
tushki7	0:60d829a0353a	322	__IO uint32_t WRP45; /!< write protection register 4 5, Address offset: 0x10 /
tushki7	0:60d829a0353a	323	__IO uint32_t WRP67; /!< write protection register 6 7, Address offset: 0x14 /
tushki7	0:60d829a0353a	324	__IO uint32_t WRP89; /!< write protection register 8 9, Address offset: 0x18 /
tushki7	0:60d829a0353a	325	__IO uint32_t WRP1011; /!< write protection register 10 11, Address offset: 0x1C /
tushki7	0:60d829a0353a	326	uint32_t RESERVED[24]; /!< Reserved, 0x20 -> 0x7C /
tushki7	0:60d829a0353a	327	__IO uint32_t WRP1213; /!< write protection register 12 13, Address offset: 0x80 /
tushki7	0:60d829a0353a	328	__IO uint32_t WRP1415; /!< write protection register 14 15, Address offset: 0x84 /
tushki7	0:60d829a0353a	329	} OB_TypeDef;
tushki7	0:60d829a0353a	330
tushki7	0:60d829a0353a	331	/**
tushki7	0:60d829a0353a	332	* @brief Operational Amplifier (OPAMP)
tushki7	0:60d829a0353a	333	*/
tushki7	0:60d829a0353a	334	typedef struct
tushki7	0:60d829a0353a	335	{
tushki7	0:60d829a0353a	336	__IO uint32_t CSR; /!< OPAMP control/status register, Address offset: 0x00 /
tushki7	0:60d829a0353a	337	__IO uint32_t OTR; /!< OPAMP offset trimming register for normal mode, Address offset: 0x04 /
tushki7	0:60d829a0353a	338	__IO uint32_t LPOTR; /!< OPAMP offset trimming register for low power mode, Address offset: 0x08 /
tushki7	0:60d829a0353a	339	} OPAMP_TypeDef;
tushki7	0:60d829a0353a	340
tushki7	0:60d829a0353a	341	/**
tushki7	0:60d829a0353a	342	* @brief General Purpose IO
tushki7	0:60d829a0353a	343	*/
tushki7	0:60d829a0353a	344
tushki7	0:60d829a0353a	345	typedef struct
tushki7	0:60d829a0353a	346	{
tushki7	0:60d829a0353a	347	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
tushki7	0:60d829a0353a	348	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
tushki7	0:60d829a0353a	349	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
tushki7	0:60d829a0353a	350	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
tushki7	0:60d829a0353a	351	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
tushki7	0:60d829a0353a	352	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
tushki7	0:60d829a0353a	353	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
tushki7	0:60d829a0353a	354	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
tushki7	0:60d829a0353a	355	__IO uint32_t AFR[2]; /!< GPIO alternate function register, Address offset: 0x20-0x24 /
tushki7	0:60d829a0353a	356	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
tushki7	0:60d829a0353a	357	} GPIO_TypeDef;
tushki7	0:60d829a0353a	358
tushki7	0:60d829a0353a	359	/**
tushki7	0:60d829a0353a	360	* @brief SysTem Configuration
tushki7	0:60d829a0353a	361	*/
tushki7	0:60d829a0353a	362
tushki7	0:60d829a0353a	363	typedef struct
tushki7	0:60d829a0353a	364	{
tushki7	0:60d829a0353a	365	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
tushki7	0:60d829a0353a	366	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
tushki7	0:60d829a0353a	367	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
tushki7	0:60d829a0353a	368	} SYSCFG_TypeDef;
tushki7	0:60d829a0353a	369
tushki7	0:60d829a0353a	370	/**
tushki7	0:60d829a0353a	371	* @brief Inter-integrated Circuit Interface
tushki7	0:60d829a0353a	372	*/
tushki7	0:60d829a0353a	373
tushki7	0:60d829a0353a	374	typedef struct
tushki7	0:60d829a0353a	375	{
tushki7	0:60d829a0353a	376	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
tushki7	0:60d829a0353a	377	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
tushki7	0:60d829a0353a	378	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
tushki7	0:60d829a0353a	379	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
tushki7	0:60d829a0353a	380	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
tushki7	0:60d829a0353a	381	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
tushki7	0:60d829a0353a	382	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
tushki7	0:60d829a0353a	383	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
tushki7	0:60d829a0353a	384	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
tushki7	0:60d829a0353a	385	} I2C_TypeDef;
tushki7	0:60d829a0353a	386
tushki7	0:60d829a0353a	387	/**
tushki7	0:60d829a0353a	388	* @brief Independent WATCHDOG
tushki7	0:60d829a0353a	389	*/
tushki7	0:60d829a0353a	390
tushki7	0:60d829a0353a	391	typedef struct
tushki7	0:60d829a0353a	392	{
tushki7	0:60d829a0353a	393	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
tushki7	0:60d829a0353a	394	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
tushki7	0:60d829a0353a	395	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
tushki7	0:60d829a0353a	396	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
tushki7	0:60d829a0353a	397	} IWDG_TypeDef;
tushki7	0:60d829a0353a	398
tushki7	0:60d829a0353a	399	/**
tushki7	0:60d829a0353a	400	* @brief LCD
tushki7	0:60d829a0353a	401	*/
tushki7	0:60d829a0353a	402
tushki7	0:60d829a0353a	403	typedef struct
tushki7	0:60d829a0353a	404	{
tushki7	0:60d829a0353a	405	__IO uint32_t CR; /!< LCD control register, Address offset: 0x00 /
tushki7	0:60d829a0353a	406	__IO uint32_t FCR; /!< LCD frame control register, Address offset: 0x04 /
tushki7	0:60d829a0353a	407	__IO uint32_t SR; /!< LCD status register, Address offset: 0x08 /
tushki7	0:60d829a0353a	408	__IO uint32_t CLR; /!< LCD clear register, Address offset: 0x0C /
tushki7	0:60d829a0353a	409	uint32_t RESERVED; /!< Reserved, Address offset: 0x10 /
tushki7	0:60d829a0353a	410	__IO uint32_t RAM[16]; /!< LCD display memory, Address offset: 0x14-0x50 /
tushki7	0:60d829a0353a	411	} LCD_TypeDef;
tushki7	0:60d829a0353a	412
tushki7	0:60d829a0353a	413	/**
tushki7	0:60d829a0353a	414	* @brief Power Control
tushki7	0:60d829a0353a	415	*/
tushki7	0:60d829a0353a	416
tushki7	0:60d829a0353a	417	typedef struct
tushki7	0:60d829a0353a	418	{
tushki7	0:60d829a0353a	419	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
tushki7	0:60d829a0353a	420	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
tushki7	0:60d829a0353a	421	} PWR_TypeDef;
tushki7	0:60d829a0353a	422
tushki7	0:60d829a0353a	423	/**
tushki7	0:60d829a0353a	424	* @brief Reset and Clock Control
tushki7	0:60d829a0353a	425	*/
tushki7	0:60d829a0353a	426
tushki7	0:60d829a0353a	427	typedef struct
tushki7	0:60d829a0353a	428	{
tushki7	0:60d829a0353a	429	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
tushki7	0:60d829a0353a	430	__IO uint32_t ICSCR; /!< RCC Internal clock sources calibration register, Address offset: 0x04 /
tushki7	0:60d829a0353a	431	__IO uint32_t CFGR; /!< RCC Clock configuration register, Address offset: 0x08 /
tushki7	0:60d829a0353a	432	__IO uint32_t CIR; /!< RCC Clock interrupt register, Address offset: 0x0C /
tushki7	0:60d829a0353a	433	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x10 /
tushki7	0:60d829a0353a	434	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x14 /
tushki7	0:60d829a0353a	435	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x18 /
tushki7	0:60d829a0353a	436	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock enable register, Address offset: 0x1C /
tushki7	0:60d829a0353a	437	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x20 /
tushki7	0:60d829a0353a	438	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x24 /
tushki7	0:60d829a0353a	439	__IO uint32_t AHBLPENR; /!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 /
tushki7	0:60d829a0353a	440	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C /
tushki7	0:60d829a0353a	441	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 /
tushki7	0:60d829a0353a	442	__IO uint32_t CSR; /!< RCC Control/status register, Address offset: 0x34 /
tushki7	0:60d829a0353a	443	} RCC_TypeDef;
tushki7	0:60d829a0353a	444
tushki7	0:60d829a0353a	445	/**
tushki7	0:60d829a0353a	446	* @brief Routing Interface
tushki7	0:60d829a0353a	447	*/
tushki7	0:60d829a0353a	448
tushki7	0:60d829a0353a	449	typedef struct
tushki7	0:60d829a0353a	450	{
tushki7	0:60d829a0353a	451	__IO uint32_t ICR; /!< RI input capture register, Address offset: 0x00 /
tushki7	0:60d829a0353a	452	__IO uint32_t ASCR1; /!< RI analog switches control register, Address offset: 0x04 /
tushki7	0:60d829a0353a	453	__IO uint32_t ASCR2; /!< RI analog switch control register 2, Address offset: 0x08 /
tushki7	0:60d829a0353a	454	__IO uint32_t HYSCR1; /!< RI hysteresis control register, Address offset: 0x0C /
tushki7	0:60d829a0353a	455	__IO uint32_t HYSCR2; /!< RI Hysteresis control register, Address offset: 0x10 /
tushki7	0:60d829a0353a	456	__IO uint32_t HYSCR3; /!< RI Hysteresis control register, Address offset: 0x14 /
tushki7	0:60d829a0353a	457	__IO uint32_t HYSCR4; /!< RI Hysteresis control register, Address offset: 0x18 /
tushki7	0:60d829a0353a	458	__IO uint32_t ASMR1; /!< RI Analog switch mode register 1, Address offset: 0x1C /
tushki7	0:60d829a0353a	459	__IO uint32_t CMR1; /!< RI Channel mask register 1, Address offset: 0x20 /
tushki7	0:60d829a0353a	460	__IO uint32_t CICR1; /!< RI Channel Iden for capture register 1, Address offset: 0x24 /
tushki7	0:60d829a0353a	461	__IO uint32_t ASMR2; /!< RI Analog switch mode register 2, Address offset: 0x28 /
tushki7	0:60d829a0353a	462	__IO uint32_t CMR2; /!< RI Channel mask register 2, Address offset: 0x2C /
tushki7	0:60d829a0353a	463	__IO uint32_t CICR2; /!< RI Channel Iden for capture register 2, Address offset: 0x30 /
tushki7	0:60d829a0353a	464	__IO uint32_t ASMR3; /!< RI Analog switch mode register 3, Address offset: 0x34 /
tushki7	0:60d829a0353a	465	__IO uint32_t CMR3; /!< RI Channel mask register 3, Address offset: 0x38 /
tushki7	0:60d829a0353a	466	__IO uint32_t CICR3; /!< RI Channel Iden for capture register 3, Address offset: 0x3C /
tushki7	0:60d829a0353a	467	__IO uint32_t ASMR4; /!< RI Analog switch mode register 4, Address offset: 0x40 /
tushki7	0:60d829a0353a	468	__IO uint32_t CMR4; /!< RI Channel mask register 4, Address offset: 0x44 /
tushki7	0:60d829a0353a	469	__IO uint32_t CICR4; /!< RI Channel Iden for capture register 4, Address offset: 0x48 /
tushki7	0:60d829a0353a	470	__IO uint32_t ASMR5; /!< RI Analog switch mode register 5, Address offset: 0x4C /
tushki7	0:60d829a0353a	471	__IO uint32_t CMR5; /!< RI Channel mask register 5, Address offset: 0x50 /
tushki7	0:60d829a0353a	472	__IO uint32_t CICR5; /!< RI Channel Iden for capture register 5, Address offset: 0x54 /
tushki7	0:60d829a0353a	473	} RI_TypeDef;
tushki7	0:60d829a0353a	474
tushki7	0:60d829a0353a	475	/**
tushki7	0:60d829a0353a	476	* @brief Real-Time Clock
tushki7	0:60d829a0353a	477	*/
tushki7	0:60d829a0353a	478	typedef struct
tushki7	0:60d829a0353a	479	{
tushki7	0:60d829a0353a	480	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
tushki7	0:60d829a0353a	481	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
tushki7	0:60d829a0353a	482	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
tushki7	0:60d829a0353a	483	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
tushki7	0:60d829a0353a	484	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
tushki7	0:60d829a0353a	485	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
tushki7	0:60d829a0353a	486	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
tushki7	0:60d829a0353a	487	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
tushki7	0:60d829a0353a	488	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
tushki7	0:60d829a0353a	489	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
tushki7	0:60d829a0353a	490	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
tushki7	0:60d829a0353a	491	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
tushki7	0:60d829a0353a	492	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
tushki7	0:60d829a0353a	493	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
tushki7	0:60d829a0353a	494	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
tushki7	0:60d829a0353a	495	__IO uint32_t CALR; /!< RRTC calibration register, Address offset: 0x3C /
tushki7	0:60d829a0353a	496	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
tushki7	0:60d829a0353a	497	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
tushki7	0:60d829a0353a	498	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
tushki7	0:60d829a0353a	499	uint32_t RESERVED7; /!< Reserved, 0x4C /
tushki7	0:60d829a0353a	500	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
tushki7	0:60d829a0353a	501	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
tushki7	0:60d829a0353a	502	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
tushki7	0:60d829a0353a	503	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
tushki7	0:60d829a0353a	504	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
tushki7	0:60d829a0353a	505	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
tushki7	0:60d829a0353a	506	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
tushki7	0:60d829a0353a	507	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
tushki7	0:60d829a0353a	508	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
tushki7	0:60d829a0353a	509	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
tushki7	0:60d829a0353a	510	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
tushki7	0:60d829a0353a	511	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
tushki7	0:60d829a0353a	512	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
tushki7	0:60d829a0353a	513	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
tushki7	0:60d829a0353a	514	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
tushki7	0:60d829a0353a	515	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
tushki7	0:60d829a0353a	516	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
tushki7	0:60d829a0353a	517	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
tushki7	0:60d829a0353a	518	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
tushki7	0:60d829a0353a	519	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
tushki7	0:60d829a0353a	520	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
tushki7	0:60d829a0353a	521	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
tushki7	0:60d829a0353a	522	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
tushki7	0:60d829a0353a	523	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
tushki7	0:60d829a0353a	524	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
tushki7	0:60d829a0353a	525	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
tushki7	0:60d829a0353a	526	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
tushki7	0:60d829a0353a	527	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
tushki7	0:60d829a0353a	528	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
tushki7	0:60d829a0353a	529	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
tushki7	0:60d829a0353a	530	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
tushki7	0:60d829a0353a	531	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
tushki7	0:60d829a0353a	532	} RTC_TypeDef;
tushki7	0:60d829a0353a	533
tushki7	0:60d829a0353a	534	/**
tushki7	0:60d829a0353a	535	* @brief Serial Peripheral Interface
tushki7	0:60d829a0353a	536	*/
tushki7	0:60d829a0353a	537
tushki7	0:60d829a0353a	538	typedef struct
tushki7	0:60d829a0353a	539	{
tushki7	0:60d829a0353a	540	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
tushki7	0:60d829a0353a	541	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
tushki7	0:60d829a0353a	542	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
tushki7	0:60d829a0353a	543	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
tushki7	0:60d829a0353a	544	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
tushki7	0:60d829a0353a	545	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
tushki7	0:60d829a0353a	546	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
tushki7	0:60d829a0353a	547	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
tushki7	0:60d829a0353a	548	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
tushki7	0:60d829a0353a	549	} SPI_TypeDef;
tushki7	0:60d829a0353a	550
tushki7	0:60d829a0353a	551	/**
tushki7	0:60d829a0353a	552	* @brief TIM
tushki7	0:60d829a0353a	553	*/
tushki7	0:60d829a0353a	554	typedef struct
tushki7	0:60d829a0353a	555	{
tushki7	0:60d829a0353a	556	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
tushki7	0:60d829a0353a	557	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
tushki7	0:60d829a0353a	558	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
tushki7	0:60d829a0353a	559	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
tushki7	0:60d829a0353a	560	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
tushki7	0:60d829a0353a	561	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
tushki7	0:60d829a0353a	562	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
tushki7	0:60d829a0353a	563	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
tushki7	0:60d829a0353a	564	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
tushki7	0:60d829a0353a	565	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
tushki7	0:60d829a0353a	566	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
tushki7	0:60d829a0353a	567	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
tushki7	0:60d829a0353a	568	uint32_t RESERVED12; /!< Reserved, 0x30 /
tushki7	0:60d829a0353a	569	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
tushki7	0:60d829a0353a	570	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
tushki7	0:60d829a0353a	571	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
tushki7	0:60d829a0353a	572	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
tushki7	0:60d829a0353a	573	uint32_t RESERVED17; /!< Reserved, 0x44 /
tushki7	0:60d829a0353a	574	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
tushki7	0:60d829a0353a	575	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
tushki7	0:60d829a0353a	576	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
tushki7	0:60d829a0353a	577	} TIM_TypeDef;
tushki7	0:60d829a0353a	578	/**
tushki7	0:60d829a0353a	579	* @brief Universal Synchronous Asynchronous Receiver Transmitter
tushki7	0:60d829a0353a	580	*/
tushki7	0:60d829a0353a	581
tushki7	0:60d829a0353a	582	typedef struct
tushki7	0:60d829a0353a	583	{
tushki7	0:60d829a0353a	584	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
tushki7	0:60d829a0353a	585	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
tushki7	0:60d829a0353a	586	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
tushki7	0:60d829a0353a	587	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
tushki7	0:60d829a0353a	588	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
tushki7	0:60d829a0353a	589	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
tushki7	0:60d829a0353a	590	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
tushki7	0:60d829a0353a	591	} USART_TypeDef;
tushki7	0:60d829a0353a	592
tushki7	0:60d829a0353a	593	/**
tushki7	0:60d829a0353a	594	* @brief Universal Serial Bus Full Speed Device
tushki7	0:60d829a0353a	595	*/
tushki7	0:60d829a0353a	596
tushki7	0:60d829a0353a	597	typedef struct
tushki7	0:60d829a0353a	598	{
tushki7	0:60d829a0353a	599	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
tushki7	0:60d829a0353a	600	__IO uint16_t RESERVED0; /!< Reserved /
tushki7	0:60d829a0353a	601	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
tushki7	0:60d829a0353a	602	__IO uint16_t RESERVED1; /!< Reserved /
tushki7	0:60d829a0353a	603	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
tushki7	0:60d829a0353a	604	__IO uint16_t RESERVED2; /!< Reserved /
tushki7	0:60d829a0353a	605	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
tushki7	0:60d829a0353a	606	__IO uint16_t RESERVED3; /!< Reserved /
tushki7	0:60d829a0353a	607	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
tushki7	0:60d829a0353a	608	__IO uint16_t RESERVED4; /!< Reserved /
tushki7	0:60d829a0353a	609	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
tushki7	0:60d829a0353a	610	__IO uint16_t RESERVED5; /!< Reserved /
tushki7	0:60d829a0353a	611	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
tushki7	0:60d829a0353a	612	__IO uint16_t RESERVED6; /!< Reserved /
tushki7	0:60d829a0353a	613	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
tushki7	0:60d829a0353a	614	__IO uint16_t RESERVED7[17]; /!< Reserved /
tushki7	0:60d829a0353a	615	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
tushki7	0:60d829a0353a	616	__IO uint16_t RESERVED8; /!< Reserved /
tushki7	0:60d829a0353a	617	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
tushki7	0:60d829a0353a	618	__IO uint16_t RESERVED9; /!< Reserved /
tushki7	0:60d829a0353a	619	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
tushki7	0:60d829a0353a	620	__IO uint16_t RESERVEDA; /!< Reserved /
tushki7	0:60d829a0353a	621	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
tushki7	0:60d829a0353a	622	__IO uint16_t RESERVEDB; /!< Reserved /
tushki7	0:60d829a0353a	623	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
tushki7	0:60d829a0353a	624	__IO uint16_t RESERVEDC; /!< Reserved /
tushki7	0:60d829a0353a	625	} USB_TypeDef;
tushki7	0:60d829a0353a	626
tushki7	0:60d829a0353a	627	/**
tushki7	0:60d829a0353a	628	* @brief Window WATCHDOG
tushki7	0:60d829a0353a	629	*/
tushki7	0:60d829a0353a	630	typedef struct
tushki7	0:60d829a0353a	631	{
tushki7	0:60d829a0353a	632	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
tushki7	0:60d829a0353a	633	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
tushki7	0:60d829a0353a	634	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
tushki7	0:60d829a0353a	635	} WWDG_TypeDef;
tushki7	0:60d829a0353a	636
tushki7	0:60d829a0353a	637	/**
tushki7	0:60d829a0353a	638	* @brief Universal Serial Bus Full Speed Device
tushki7	0:60d829a0353a	639	*/
tushki7	0:60d829a0353a	640	/**
tushki7	0:60d829a0353a	641	* @}
tushki7	0:60d829a0353a	642	*/
tushki7	0:60d829a0353a	643
tushki7	0:60d829a0353a	644	/** @addtogroup Peripheral_memory_map
tushki7	0:60d829a0353a	645	* @{
tushki7	0:60d829a0353a	646	*/
tushki7	0:60d829a0353a	647
tushki7	0:60d829a0353a	648	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
tushki7	0:60d829a0353a	649	#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /!< FLASH EEPROM base address in the alias region /
tushki7	0:60d829a0353a	650	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
tushki7	0:60d829a0353a	651	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
tushki7	0:60d829a0353a	652	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
tushki7	0:60d829a0353a	653	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
tushki7	0:60d829a0353a	654	#define FLASH_BANK2_BASE ((uint32_t)0x08040000) /!< FLASH BANK2 base address in the alias region /
tushki7	0:60d829a0353a	655	#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /!< Program end FLASH BANK1 address /
tushki7	0:60d829a0353a	656	#define FLASH_BANK2_END ((uint32_t)0x0807FFFF) /!< Program end FLASH BANK2 address /
tushki7	0:60d829a0353a	657	#define FLASH_EEPROM_END ((uint32_t)0x08083FFF) /!< FLASH EEPROM end address (16KB) /
tushki7	0:60d829a0353a	658
tushki7	0:60d829a0353a	659	/!< Peripheral memory map /
tushki7	0:60d829a0353a	660	#define APB1PERIPH_BASE PERIPH_BASE
tushki7	0:60d829a0353a	661	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
tushki7	0:60d829a0353a	662	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
tushki7	0:60d829a0353a	663
tushki7	0:60d829a0353a	664	/!< APB1 peripherals /
tushki7	0:60d829a0353a	665	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
tushki7	0:60d829a0353a	666	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
tushki7	0:60d829a0353a	667	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
tushki7	0:60d829a0353a	668	#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00)
tushki7	0:60d829a0353a	669	#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
tushki7	0:60d829a0353a	670	#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
tushki7	0:60d829a0353a	671	#define LCD_BASE (APB1PERIPH_BASE + 0x00002400)
tushki7	0:60d829a0353a	672	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
tushki7	0:60d829a0353a	673	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
tushki7	0:60d829a0353a	674	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
tushki7	0:60d829a0353a	675	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
tushki7	0:60d829a0353a	676	#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
tushki7	0:60d829a0353a	677	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
tushki7	0:60d829a0353a	678	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
tushki7	0:60d829a0353a	679	#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
tushki7	0:60d829a0353a	680	#define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
tushki7	0:60d829a0353a	681	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
tushki7	0:60d829a0353a	682	#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
tushki7	0:60d829a0353a	683
tushki7	0:60d829a0353a	684	/* USB device FS */
tushki7	0:60d829a0353a	685	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
tushki7	0:60d829a0353a	686	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
tushki7	0:60d829a0353a	687
tushki7	0:60d829a0353a	688	/* USB device FS SRAM */
tushki7	0:60d829a0353a	689	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
tushki7	0:60d829a0353a	690	#define DAC_BASE (APB1PERIPH_BASE + 0x00007400)
tushki7	0:60d829a0353a	691	#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00)
tushki7	0:60d829a0353a	692	#define RI_BASE (APB1PERIPH_BASE + 0x00007C04)
tushki7	0:60d829a0353a	693	#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C)
tushki7	0:60d829a0353a	694
tushki7	0:60d829a0353a	695	/!< APB2 peripherals /
tushki7	0:60d829a0353a	696	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
tushki7	0:60d829a0353a	697	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
tushki7	0:60d829a0353a	698	#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800)
tushki7	0:60d829a0353a	699	#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00)
tushki7	0:60d829a0353a	700	#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000)
tushki7	0:60d829a0353a	701	#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400)
tushki7	0:60d829a0353a	702	#define ADC_BASE (APB2PERIPH_BASE + 0x00002700)
tushki7	0:60d829a0353a	703	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
tushki7	0:60d829a0353a	704	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
tushki7	0:60d829a0353a	705
tushki7	0:60d829a0353a	706	/!< AHB peripherals /
tushki7	0:60d829a0353a	707	#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000)
tushki7	0:60d829a0353a	708	#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400)
tushki7	0:60d829a0353a	709	#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800)
tushki7	0:60d829a0353a	710	#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00)
tushki7	0:60d829a0353a	711	#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000)
tushki7	0:60d829a0353a	712	#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400)
tushki7	0:60d829a0353a	713	#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800)
tushki7	0:60d829a0353a	714	#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00)
tushki7	0:60d829a0353a	715	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
tushki7	0:60d829a0353a	716	#define RCC_BASE (AHBPERIPH_BASE + 0x00003800)
tushki7	0:60d829a0353a	717	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /!< FLASH registers base address /
tushki7	0:60d829a0353a	718	#define OB_BASE ((uint32_t)0x1FF80000) /!< FLASH Option Bytes base address /
tushki7	0:60d829a0353a	719	#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000)
tushki7	0:60d829a0353a	720	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
tushki7	0:60d829a0353a	721	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
tushki7	0:60d829a0353a	722	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
tushki7	0:60d829a0353a	723	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
tushki7	0:60d829a0353a	724	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
tushki7	0:60d829a0353a	725	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
tushki7	0:60d829a0353a	726	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
tushki7	0:60d829a0353a	727	#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400)
tushki7	0:60d829a0353a	728	#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
tushki7	0:60d829a0353a	729	#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
tushki7	0:60d829a0353a	730	#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
tushki7	0:60d829a0353a	731	#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
tushki7	0:60d829a0353a	732	#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
tushki7	0:60d829a0353a	733	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
tushki7	0:60d829a0353a	734
tushki7	0:60d829a0353a	735	/**
tushki7	0:60d829a0353a	736	* @}
tushki7	0:60d829a0353a	737	*/
tushki7	0:60d829a0353a	738
tushki7	0:60d829a0353a	739	/** @addtogroup Peripheral_declaration
tushki7	0:60d829a0353a	740	* @{
tushki7	0:60d829a0353a	741	*/
tushki7	0:60d829a0353a	742
tushki7	0:60d829a0353a	743	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
tushki7	0:60d829a0353a	744	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
tushki7	0:60d829a0353a	745	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
tushki7	0:60d829a0353a	746	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
tushki7	0:60d829a0353a	747	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
tushki7	0:60d829a0353a	748	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
tushki7	0:60d829a0353a	749	#define LCD ((LCD_TypeDef *) LCD_BASE)
tushki7	0:60d829a0353a	750	#define RTC ((RTC_TypeDef *) RTC_BASE)
tushki7	0:60d829a0353a	751	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
tushki7	0:60d829a0353a	752	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
tushki7	0:60d829a0353a	753	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
tushki7	0:60d829a0353a	754	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
tushki7	0:60d829a0353a	755	#define USART2 ((USART_TypeDef *) USART2_BASE)
tushki7	0:60d829a0353a	756	#define USART3 ((USART_TypeDef *) USART3_BASE)
tushki7	0:60d829a0353a	757	#define UART4 ((USART_TypeDef *) UART4_BASE)
tushki7	0:60d829a0353a	758	#define UART5 ((USART_TypeDef *) UART5_BASE)
tushki7	0:60d829a0353a	759	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
tushki7	0:60d829a0353a	760	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
tushki7	0:60d829a0353a	761	/* USB device FS */
tushki7	0:60d829a0353a	762	#define USB ((USB_TypeDef *) USB_BASE)
tushki7	0:60d829a0353a	763	/* USB device FS SRAM */
tushki7	0:60d829a0353a	764	#define PWR ((PWR_TypeDef *) PWR_BASE)
tushki7	0:60d829a0353a	765	#define DAC ((DAC_TypeDef *) DAC_BASE)
tushki7	0:60d829a0353a	766	#define COMP ((COMP_TypeDef *) COMP_BASE)
tushki7	0:60d829a0353a	767	#define COMP1 ((COMP_TypeDef *) COMP_BASE)
tushki7	0:60d829a0353a	768	#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
tushki7	0:60d829a0353a	769	#define RI ((RI_TypeDef *) RI_BASE)
tushki7	0:60d829a0353a	770	#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
tushki7	0:60d829a0353a	771	#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
tushki7	0:60d829a0353a	772	#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
tushki7	0:60d829a0353a	773	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
tushki7	0:60d829a0353a	774	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
tushki7	0:60d829a0353a	775	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
tushki7	0:60d829a0353a	776	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
tushki7	0:60d829a0353a	777	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
tushki7	0:60d829a0353a	778	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
tushki7	0:60d829a0353a	779	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
tushki7	0:60d829a0353a	780	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
tushki7	0:60d829a0353a	781	#define USART1 ((USART_TypeDef *) USART1_BASE)
tushki7	0:60d829a0353a	782	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
tushki7	0:60d829a0353a	783	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
tushki7	0:60d829a0353a	784	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
tushki7	0:60d829a0353a	785	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
tushki7	0:60d829a0353a	786	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
tushki7	0:60d829a0353a	787	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
tushki7	0:60d829a0353a	788	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
tushki7	0:60d829a0353a	789	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
tushki7	0:60d829a0353a	790	#define CRC ((CRC_TypeDef *) CRC_BASE)
tushki7	0:60d829a0353a	791	#define RCC ((RCC_TypeDef *) RCC_BASE)
tushki7	0:60d829a0353a	792	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
tushki7	0:60d829a0353a	793	#define OB ((OB_TypeDef *) OB_BASE)
tushki7	0:60d829a0353a	794	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
tushki7	0:60d829a0353a	795	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
tushki7	0:60d829a0353a	796	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
tushki7	0:60d829a0353a	797	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
tushki7	0:60d829a0353a	798	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
tushki7	0:60d829a0353a	799	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
tushki7	0:60d829a0353a	800	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
tushki7	0:60d829a0353a	801	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
tushki7	0:60d829a0353a	802	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
tushki7	0:60d829a0353a	803	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
tushki7	0:60d829a0353a	804	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
tushki7	0:60d829a0353a	805	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
tushki7	0:60d829a0353a	806	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
tushki7	0:60d829a0353a	807	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
tushki7	0:60d829a0353a	808	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
tushki7	0:60d829a0353a	809
tushki7	0:60d829a0353a	810	/**
tushki7	0:60d829a0353a	811	* @}
tushki7	0:60d829a0353a	812	*/
tushki7	0:60d829a0353a	813
tushki7	0:60d829a0353a	814	/** @addtogroup Exported_constants
tushki7	0:60d829a0353a	815	* @{
tushki7	0:60d829a0353a	816	*/
tushki7	0:60d829a0353a	817
tushki7	0:60d829a0353a	818	/** @addtogroup Peripheral_Registers_Bits_Definition
tushki7	0:60d829a0353a	819	* @{
tushki7	0:60d829a0353a	820	*/
tushki7	0:60d829a0353a	821
tushki7	0:60d829a0353a	822	/******************************************************************************/
tushki7	0:60d829a0353a	823	/* Peripheral Registers Bits Definition */
tushki7	0:60d829a0353a	824	/******************************************************************************/
tushki7	0:60d829a0353a	825	/******************************************************************************/
tushki7	0:60d829a0353a	826	/* */
tushki7	0:60d829a0353a	827	/* Analog to Digital Converter (ADC) */
tushki7	0:60d829a0353a	828	/* */
tushki7	0:60d829a0353a	829	/******************************************************************************/
tushki7	0:60d829a0353a	830
tushki7	0:60d829a0353a	831	/****************** Bit definition for ADC_SR register ******************/
tushki7	0:60d829a0353a	832	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
tushki7	0:60d829a0353a	833	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
tushki7	0:60d829a0353a	834	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
tushki7	0:60d829a0353a	835	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
tushki7	0:60d829a0353a	836	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
tushki7	0:60d829a0353a	837	#define ADC_SR_OVR ((uint32_t)0x00000020) /!< Overrun flag /
tushki7	0:60d829a0353a	838	#define ADC_SR_ADONS ((uint32_t)0x00000040) /!< ADC ON status /
tushki7	0:60d829a0353a	839	#define ADC_SR_RCNR ((uint32_t)0x00000100) /!< Regular channel not ready flag /
tushki7	0:60d829a0353a	840	#define ADC_SR_JCNR ((uint32_t)0x00000200) /!< Injected channel not ready flag /
tushki7	0:60d829a0353a	841
tushki7	0:60d829a0353a	842	/***************** Bit definition for ADC_CR1 register ******************/
tushki7	0:60d829a0353a	843	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
tushki7	0:60d829a0353a	844	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	845	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	846	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	847	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	848	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	849
tushki7	0:60d829a0353a	850	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
tushki7	0:60d829a0353a	851	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
tushki7	0:60d829a0353a	852	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
tushki7	0:60d829a0353a	853	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
tushki7	0:60d829a0353a	854	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
tushki7	0:60d829a0353a	855	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
tushki7	0:60d829a0353a	856	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
tushki7	0:60d829a0353a	857	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
tushki7	0:60d829a0353a	858
tushki7	0:60d829a0353a	859	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
tushki7	0:60d829a0353a	860	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
tushki7	0:60d829a0353a	861	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
tushki7	0:60d829a0353a	862	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
tushki7	0:60d829a0353a	863
tushki7	0:60d829a0353a	864	#define ADC_CR1_PDD ((uint32_t)0x00010000) /!< Power Down during Delay phase /
tushki7	0:60d829a0353a	865	#define ADC_CR1_PDI ((uint32_t)0x00020000) /!< Power Down during Idle phase /
tushki7	0:60d829a0353a	866
tushki7	0:60d829a0353a	867	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
tushki7	0:60d829a0353a	868	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
tushki7	0:60d829a0353a	869
tushki7	0:60d829a0353a	870	#define ADC_CR1_RES ((uint32_t)0x03000000) /!< RES[1:0] bits (Resolution) /
tushki7	0:60d829a0353a	871	#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	872	#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	873
tushki7	0:60d829a0353a	874	#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /!< Overrun interrupt enable /
tushki7	0:60d829a0353a	875
tushki7	0:60d829a0353a	876	/***************** Bit definition for ADC_CR2 register ******************/
tushki7	0:60d829a0353a	877	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
tushki7	0:60d829a0353a	878	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
tushki7	0:60d829a0353a	879	#define ADC_CR2_CFG ((uint32_t)0x00000004) /!< ADC Configuration /
tushki7	0:60d829a0353a	880
tushki7	0:60d829a0353a	881	#define ADC_CR2_DELS ((uint32_t)0x00000070) /!< DELS[2:0] bits (Delay selection) /
tushki7	0:60d829a0353a	882	#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	883	#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	884	#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /!< Bit 2 /
tushki7	0:60d829a0353a	885
tushki7	0:60d829a0353a	886	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
tushki7	0:60d829a0353a	887	#define ADC_CR2_DDS ((uint32_t)0x00000200) /!< DMA disable selection (Single ADC) /
tushki7	0:60d829a0353a	888	#define ADC_CR2_EOCS ((uint32_t)0x00000400) /!< End of conversion selection /
tushki7	0:60d829a0353a	889	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
tushki7	0:60d829a0353a	890
tushki7	0:60d829a0353a	891	#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /!< JEXTSEL[3:0] bits (External event select for injected group) /
tushki7	0:60d829a0353a	892	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	893	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	894	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /!< Bit 2 /
tushki7	0:60d829a0353a	895	#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /!< Bit 3 /
tushki7	0:60d829a0353a	896
tushki7	0:60d829a0353a	897	#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) /
tushki7	0:60d829a0353a	898	#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	899	#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	900
tushki7	0:60d829a0353a	901	#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /!< Start Conversion of injected channels /
tushki7	0:60d829a0353a	902
tushki7	0:60d829a0353a	903	#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /!< EXTSEL[3:0] bits (External Event Select for regular group) /
tushki7	0:60d829a0353a	904	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	905	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	906	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /!< Bit 2 /
tushki7	0:60d829a0353a	907	#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /!< Bit 3 /
tushki7	0:60d829a0353a	908
tushki7	0:60d829a0353a	909	#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
tushki7	0:60d829a0353a	910	#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /!< Bit 0 /
tushki7	0:60d829a0353a	911	#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /!< Bit 1 /
tushki7	0:60d829a0353a	912
tushki7	0:60d829a0353a	913	#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /!< Start Conversion of regular channels /
tushki7	0:60d829a0353a	914
tushki7	0:60d829a0353a	915	/**************** Bit definition for ADC_SMPR1 register *****************/
tushki7	0:60d829a0353a	916	#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /!< SMP20[2:0] bits (Channel 20 Sample time selection) /
tushki7	0:60d829a0353a	917	#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	918	#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	919	#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	920
tushki7	0:60d829a0353a	921	#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /!< SMP21[2:0] bits (Channel 21 Sample time selection) /
tushki7	0:60d829a0353a	922	#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /!< Bit 0 /
tushki7	0:60d829a0353a	923	#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /!< Bit 1 /
tushki7	0:60d829a0353a	924	#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /!< Bit 2 /
tushki7	0:60d829a0353a	925
tushki7	0:60d829a0353a	926	#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /!< SMP22[2:0] bits (Channel 22 Sample time selection) /
tushki7	0:60d829a0353a	927	#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	928	#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	929	#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /!< Bit 2 /
tushki7	0:60d829a0353a	930
tushki7	0:60d829a0353a	931	#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /!< SMP23[2:0] bits (Channel 23 Sample time selection) /
tushki7	0:60d829a0353a	932	#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	933	#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	934	#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /!< Bit 2 /
tushki7	0:60d829a0353a	935
tushki7	0:60d829a0353a	936	#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /!< SMP24[2:0] bits (Channel 24 Sample time selection) /
tushki7	0:60d829a0353a	937	#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	938	#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	939	#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /!< Bit 2 /
tushki7	0:60d829a0353a	940
tushki7	0:60d829a0353a	941	#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /!< SMP25[2:0] bits (Channel 25 Sample time selection) /
tushki7	0:60d829a0353a	942	#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	943	#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	944	#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	945
tushki7	0:60d829a0353a	946	#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /!< SMP26[2:0] bits (Channel 26 Sample time selection) /
tushki7	0:60d829a0353a	947	#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	948	#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	949	#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /!< Bit 2 /
tushki7	0:60d829a0353a	950
tushki7	0:60d829a0353a	951	#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /!< SMP27[2:0] bits (Channel 27 Sample time selection) /
tushki7	0:60d829a0353a	952	#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /!< Bit 0 /
tushki7	0:60d829a0353a	953	#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /!< Bit 1 /
tushki7	0:60d829a0353a	954	#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /!< Bit 2 /
tushki7	0:60d829a0353a	955
tushki7	0:60d829a0353a	956	#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /!< SMP28[2:0] bits (Channel 28 Sample time selection) /
tushki7	0:60d829a0353a	957	#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	958	#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	959	#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /!< Bit 2 /
tushki7	0:60d829a0353a	960
tushki7	0:60d829a0353a	961	#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /!< SMP29[2:0] bits (Channel 29 Sample time selection) /
tushki7	0:60d829a0353a	962	#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /!< Bit 0 /
tushki7	0:60d829a0353a	963	#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /!< Bit 1 /
tushki7	0:60d829a0353a	964	#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /!< Bit 2 /
tushki7	0:60d829a0353a	965
tushki7	0:60d829a0353a	966	/**************** Bit definition for ADC_SMPR2 register *****************/
tushki7	0:60d829a0353a	967	#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
tushki7	0:60d829a0353a	968	#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	969	#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	970	#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	971
tushki7	0:60d829a0353a	972	#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
tushki7	0:60d829a0353a	973	#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
tushki7	0:60d829a0353a	974	#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
tushki7	0:60d829a0353a	975	#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
tushki7	0:60d829a0353a	976
tushki7	0:60d829a0353a	977	#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
tushki7	0:60d829a0353a	978	#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	979	#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	980	#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
tushki7	0:60d829a0353a	981
tushki7	0:60d829a0353a	982	#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
tushki7	0:60d829a0353a	983	#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	984	#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	985	#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
tushki7	0:60d829a0353a	986
tushki7	0:60d829a0353a	987	#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
tushki7	0:60d829a0353a	988	#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	989	#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	990	#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
tushki7	0:60d829a0353a	991
tushki7	0:60d829a0353a	992	#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 5 Sample time selection) /
tushki7	0:60d829a0353a	993	#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	994	#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	995	#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	996
tushki7	0:60d829a0353a	997	#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
tushki7	0:60d829a0353a	998	#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	999	#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	1000	#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
tushki7	0:60d829a0353a	1001
tushki7	0:60d829a0353a	1002	#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
tushki7	0:60d829a0353a	1003	#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
tushki7	0:60d829a0353a	1004	#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
tushki7	0:60d829a0353a	1005	#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
tushki7	0:60d829a0353a	1006
tushki7	0:60d829a0353a	1007	#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /!< SMP18[2:0] bits (Channel 18 Sample time selection) /
tushki7	0:60d829a0353a	1008	#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1009	#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1010	#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1011
tushki7	0:60d829a0353a	1012	#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /!< SMP19[2:0] bits (Channel 19 Sample time selection) /
tushki7	0:60d829a0353a	1013	#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1014	#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1015	#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1016
tushki7	0:60d829a0353a	1017	/**************** Bit definition for ADC_SMPR3 register *****************/
tushki7	0:60d829a0353a	1018	#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
tushki7	0:60d829a0353a	1019	#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1020	#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1021	#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1022
tushki7	0:60d829a0353a	1023	#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
tushki7	0:60d829a0353a	1024	#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
tushki7	0:60d829a0353a	1025	#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
tushki7	0:60d829a0353a	1026	#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
tushki7	0:60d829a0353a	1027
tushki7	0:60d829a0353a	1028	#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
tushki7	0:60d829a0353a	1029	#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	1030	#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	1031	#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
tushki7	0:60d829a0353a	1032
tushki7	0:60d829a0353a	1033	#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
tushki7	0:60d829a0353a	1034	#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	1035	#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	1036	#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
tushki7	0:60d829a0353a	1037
tushki7	0:60d829a0353a	1038	#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
tushki7	0:60d829a0353a	1039	#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	1040	#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	1041	#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
tushki7	0:60d829a0353a	1042
tushki7	0:60d829a0353a	1043	#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
tushki7	0:60d829a0353a	1044	#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	1045	#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	1046	#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	1047
tushki7	0:60d829a0353a	1048	#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
tushki7	0:60d829a0353a	1049	#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	1050	#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	1051	#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
tushki7	0:60d829a0353a	1052
tushki7	0:60d829a0353a	1053	#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
tushki7	0:60d829a0353a	1054	#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
tushki7	0:60d829a0353a	1055	#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
tushki7	0:60d829a0353a	1056	#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
tushki7	0:60d829a0353a	1057
tushki7	0:60d829a0353a	1058	#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
tushki7	0:60d829a0353a	1059	#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1060	#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1061	#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1062
tushki7	0:60d829a0353a	1063	#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
tushki7	0:60d829a0353a	1064	#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1065	#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1066	#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1067
tushki7	0:60d829a0353a	1068	/**************** Bit definition for ADC_JOFR1 register *****************/
tushki7	0:60d829a0353a	1069	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
tushki7	0:60d829a0353a	1070
tushki7	0:60d829a0353a	1071	/**************** Bit definition for ADC_JOFR2 register *****************/
tushki7	0:60d829a0353a	1072	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
tushki7	0:60d829a0353a	1073
tushki7	0:60d829a0353a	1074	/**************** Bit definition for ADC_JOFR3 register *****************/
tushki7	0:60d829a0353a	1075	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
tushki7	0:60d829a0353a	1076
tushki7	0:60d829a0353a	1077	/**************** Bit definition for ADC_JOFR4 register *****************/
tushki7	0:60d829a0353a	1078	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
tushki7	0:60d829a0353a	1079
tushki7	0:60d829a0353a	1080	/***************** Bit definition for ADC_HTR register ******************/
tushki7	0:60d829a0353a	1081	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
tushki7	0:60d829a0353a	1082
tushki7	0:60d829a0353a	1083	/***************** Bit definition for ADC_LTR register ******************/
tushki7	0:60d829a0353a	1084	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
tushki7	0:60d829a0353a	1085
tushki7	0:60d829a0353a	1086	/***************** Bit definition for ADC_SQR1 register *****************/
tushki7	0:60d829a0353a	1087	#define ADC_SQR1_L ((uint32_t)0x01F00000) /!< L[4:0] bits (Regular channel sequence length) /
tushki7	0:60d829a0353a	1088	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	1089	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	1090	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
tushki7	0:60d829a0353a	1091	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
tushki7	0:60d829a0353a	1092	#define ADC_SQR1_L_4 ((uint32_t)0x01000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1093
tushki7	0:60d829a0353a	1094	#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /!< SQ28[4:0] bits (25th conversion in regular sequence) /
tushki7	0:60d829a0353a	1095	#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	1096	#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	1097	#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	1098	#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	1099	#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	1100
tushki7	0:60d829a0353a	1101	#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /!< SQ27[4:0] bits (27th conversion in regular sequence) /
tushki7	0:60d829a0353a	1102	#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1103	#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1104	#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	1105	#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	1106	#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	1107
tushki7	0:60d829a0353a	1108	#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /!< SQ26[4:0] bits (26th conversion in regular sequence) /
tushki7	0:60d829a0353a	1109	#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	1110	#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	1111	#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	1112	#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	1113	#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	1114
tushki7	0:60d829a0353a	1115	#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /!< SQ25[4:0] bits (25th conversion in regular sequence) /
tushki7	0:60d829a0353a	1116	#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1117	#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1118	#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1119	#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	1120	#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	1121
tushki7	0:60d829a0353a	1122	/***************** Bit definition for ADC_SQR2 register *****************/
tushki7	0:60d829a0353a	1123	#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /!< SQ19[4:0] bits (19th conversion in regular sequence) /
tushki7	0:60d829a0353a	1124	#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1125	#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1126	#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1127	#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	1128	#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	1129
tushki7	0:60d829a0353a	1130	#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /!< SQ20[4:0] bits (20th conversion in regular sequence) /
tushki7	0:60d829a0353a	1131	#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	1132	#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	1133	#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	1134	#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	1135	#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	1136
tushki7	0:60d829a0353a	1137	#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /!< SQ21[4:0] bits (21th conversion in regular sequence) /
tushki7	0:60d829a0353a	1138	#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1139	#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1140	#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	1141	#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	1142	#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	1143
tushki7	0:60d829a0353a	1144	#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /!< SQ22[4:0] bits (22th conversion in regular sequence) /
tushki7	0:60d829a0353a	1145	#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	1146	#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	1147	#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	1148	#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	1149	#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	1150
tushki7	0:60d829a0353a	1151	#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /!< SQ23[4:0] bits (23th conversion in regular sequence) /
tushki7	0:60d829a0353a	1152	#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	1153	#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	1154	#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /!< Bit 2 /
tushki7	0:60d829a0353a	1155	#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /!< Bit 3 /
tushki7	0:60d829a0353a	1156	#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1157
tushki7	0:60d829a0353a	1158	#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /!< SQ24[4:0] bits (24th conversion in regular sequence) /
tushki7	0:60d829a0353a	1159	#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1160	#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1161	#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1162	#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /!< Bit 3 /
tushki7	0:60d829a0353a	1163	#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1164
tushki7	0:60d829a0353a	1165	/***************** Bit definition for ADC_SQR3 register *****************/
tushki7	0:60d829a0353a	1166	#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
tushki7	0:60d829a0353a	1167	#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1168	#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1169	#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1170	#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	1171	#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	1172
tushki7	0:60d829a0353a	1173	#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
tushki7	0:60d829a0353a	1174	#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	1175	#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	1176	#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	1177	#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	1178	#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	1179
tushki7	0:60d829a0353a	1180	#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
tushki7	0:60d829a0353a	1181	#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1182	#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1183	#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	1184	#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	1185	#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	1186
tushki7	0:60d829a0353a	1187	#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
tushki7	0:60d829a0353a	1188	#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	1189	#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	1190	#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	1191	#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	1192	#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	1193
tushki7	0:60d829a0353a	1194	#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /!< SQ17[4:0] bits (17th conversion in regular sequence) /
tushki7	0:60d829a0353a	1195	#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	1196	#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	1197	#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /!< Bit 2 /
tushki7	0:60d829a0353a	1198	#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /!< Bit 3 /
tushki7	0:60d829a0353a	1199	#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1200
tushki7	0:60d829a0353a	1201	#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /!< SQ18[4:0] bits (18th conversion in regular sequence) /
tushki7	0:60d829a0353a	1202	#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1203	#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1204	#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1205	#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /!< Bit 3 /
tushki7	0:60d829a0353a	1206	#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1207
tushki7	0:60d829a0353a	1208	/***************** Bit definition for ADC_SQR4 register *****************/
tushki7	0:60d829a0353a	1209	#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
tushki7	0:60d829a0353a	1210	#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1211	#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1212	#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1213	#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	1214	#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	1215
tushki7	0:60d829a0353a	1216	#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
tushki7	0:60d829a0353a	1217	#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	1218	#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	1219	#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	1220	#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	1221	#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	1222
tushki7	0:60d829a0353a	1223	#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
tushki7	0:60d829a0353a	1224	#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1225	#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1226	#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	1227	#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	1228	#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	1229
tushki7	0:60d829a0353a	1230	#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
tushki7	0:60d829a0353a	1231	#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	1232	#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	1233	#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	1234	#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	1235	#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	1236
tushki7	0:60d829a0353a	1237	#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
tushki7	0:60d829a0353a	1238	#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	1239	#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	1240	#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
tushki7	0:60d829a0353a	1241	#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
tushki7	0:60d829a0353a	1242	#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1243
tushki7	0:60d829a0353a	1244	#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
tushki7	0:60d829a0353a	1245	#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1246	#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1247	#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1248	#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
tushki7	0:60d829a0353a	1249	#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1250
tushki7	0:60d829a0353a	1251	/***************** Bit definition for ADC_SQR5 register *****************/
tushki7	0:60d829a0353a	1252	#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
tushki7	0:60d829a0353a	1253	#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1254	#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1255	#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1256	#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	1257	#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	1258
tushki7	0:60d829a0353a	1259	#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
tushki7	0:60d829a0353a	1260	#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	1261	#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	1262	#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	1263	#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	1264	#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	1265
tushki7	0:60d829a0353a	1266	#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
tushki7	0:60d829a0353a	1267	#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1268	#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1269	#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	1270	#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	1271	#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	1272
tushki7	0:60d829a0353a	1273	#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
tushki7	0:60d829a0353a	1274	#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	1275	#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	1276	#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	1277	#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	1278	#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	1279
tushki7	0:60d829a0353a	1280	#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
tushki7	0:60d829a0353a	1281	#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	1282	#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	1283	#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
tushki7	0:60d829a0353a	1284	#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
tushki7	0:60d829a0353a	1285	#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1286
tushki7	0:60d829a0353a	1287	#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
tushki7	0:60d829a0353a	1288	#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1289	#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1290	#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1291	#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
tushki7	0:60d829a0353a	1292	#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
tushki7	0:60d829a0353a	1293
tushki7	0:60d829a0353a	1294
tushki7	0:60d829a0353a	1295	/***************** Bit definition for ADC_JSQR register *****************/
tushki7	0:60d829a0353a	1296	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
tushki7	0:60d829a0353a	1297	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1298	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1299	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1300	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	1301	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	1302
tushki7	0:60d829a0353a	1303	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
tushki7	0:60d829a0353a	1304	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	1305	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	1306	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	1307	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	1308	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	1309
tushki7	0:60d829a0353a	1310	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
tushki7	0:60d829a0353a	1311	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1312	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1313	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	1314	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	1315	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	1316
tushki7	0:60d829a0353a	1317	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
tushki7	0:60d829a0353a	1318	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	1319	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	1320	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	1321	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	1322	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	1323
tushki7	0:60d829a0353a	1324	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
tushki7	0:60d829a0353a	1325	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	1326	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	1327
tushki7	0:60d829a0353a	1328	/***************** Bit definition for ADC_JDR1 register *****************/
tushki7	0:60d829a0353a	1329	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
tushki7	0:60d829a0353a	1330
tushki7	0:60d829a0353a	1331	/***************** Bit definition for ADC_JDR2 register *****************/
tushki7	0:60d829a0353a	1332	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
tushki7	0:60d829a0353a	1333
tushki7	0:60d829a0353a	1334	/***************** Bit definition for ADC_JDR3 register *****************/
tushki7	0:60d829a0353a	1335	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
tushki7	0:60d829a0353a	1336
tushki7	0:60d829a0353a	1337	/***************** Bit definition for ADC_JDR4 register *****************/
tushki7	0:60d829a0353a	1338	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
tushki7	0:60d829a0353a	1339
tushki7	0:60d829a0353a	1340	/****************** Bit definition for ADC_DR register ******************/
tushki7	0:60d829a0353a	1341	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
tushki7	0:60d829a0353a	1342
tushki7	0:60d829a0353a	1343	/**************** Bit definition for ADC_SMPR0 register *****************/
tushki7	0:60d829a0353a	1344	#define ADC_SMPR0_SMP30 ((uint32_t)0x00000007) /!< SMP30[2:0] bits (Channel 30 Sample time selection) /
tushki7	0:60d829a0353a	1345	#define ADC_SMPR0_SMP30_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1346	#define ADC_SMPR0_SMP30_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1347	#define ADC_SMPR0_SMP30_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1348
tushki7	0:60d829a0353a	1349	#define ADC_SMPR0_SMP31 ((uint32_t)0x00000038) /!< SMP31[2:0] bits (Channel 31 Sample time selection) /
tushki7	0:60d829a0353a	1350	#define ADC_SMPR0_SMP31_0 ((uint32_t)0x00000008) /!< Bit 0 /
tushki7	0:60d829a0353a	1351	#define ADC_SMPR0_SMP31_1 ((uint32_t)0x00000010) /!< Bit 1 /
tushki7	0:60d829a0353a	1352	#define ADC_SMPR0_SMP31_2 ((uint32_t)0x00000020) /!< Bit 2 /
tushki7	0:60d829a0353a	1353
tushki7	0:60d829a0353a	1354	/***************** Bit definition for ADC_CSR register ******************/
tushki7	0:60d829a0353a	1355	#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /!< ADC1 Analog watchdog flag /
tushki7	0:60d829a0353a	1356	#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /!< ADC1 End of conversion /
tushki7	0:60d829a0353a	1357	#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /!< ADC1 Injected channel end of conversion /
tushki7	0:60d829a0353a	1358	#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /!< ADC1 Injected channel Start flag /
tushki7	0:60d829a0353a	1359	#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /!< ADC1 Regular channel Start flag /
tushki7	0:60d829a0353a	1360	#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /!< ADC1 overrun flag /
tushki7	0:60d829a0353a	1361	#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /!< ADON status of ADC1 /
tushki7	0:60d829a0353a	1362
tushki7	0:60d829a0353a	1363	/***************** Bit definition for ADC_CCR register ******************/
tushki7	0:60d829a0353a	1364	#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /!< ADC prescaler/
tushki7	0:60d829a0353a	1365	#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	1366	#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	1367	#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
tushki7	0:60d829a0353a	1368
tushki7	0:60d829a0353a	1369	/******************************************************************************/
tushki7	0:60d829a0353a	1370	/* */
tushki7	0:60d829a0353a	1371	/* Analog Comparators (COMP) */
tushki7	0:60d829a0353a	1372	/* */
tushki7	0:60d829a0353a	1373	/******************************************************************************/
tushki7	0:60d829a0353a	1374
tushki7	0:60d829a0353a	1375	/**************** Bit definition for COMP_CSR register ******************/
tushki7	0:60d829a0353a	1376	#define COMP_CSR_10KPU ((uint32_t)0x00000001) /!< 10K pull-up resistor /
tushki7	0:60d829a0353a	1377	#define COMP_CSR_400KPU ((uint32_t)0x00000002) /!< 400K pull-up resistor /
tushki7	0:60d829a0353a	1378	#define COMP_CSR_10KPD ((uint32_t)0x00000004) /!< 10K pull-down resistor /
tushki7	0:60d829a0353a	1379	#define COMP_CSR_400KPD ((uint32_t)0x00000008) /!< 400K pull-down resistor /
tushki7	0:60d829a0353a	1380	#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /!< Comparator 1 enable /
tushki7	0:60d829a0353a	1381	#define COMP_CSR_SW1 ((uint32_t)0x00000020) /!< SW1 analog switch enable /
tushki7	0:60d829a0353a	1382	#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /!< Comparator 1 output /
tushki7	0:60d829a0353a	1383
tushki7	0:60d829a0353a	1384	#define COMP_CSR_SPEED ((uint32_t)0x00001000) /!< Comparator 2 speed /
tushki7	0:60d829a0353a	1385	#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /!< Comparator 2 ouput /
tushki7	0:60d829a0353a	1386	#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /!< Comparator Vref Enable /
tushki7	0:60d829a0353a	1387	#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /!< Window mode enable /
tushki7	0:60d829a0353a	1388	#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /!< INSEL[2:0] Inversion input Selection /
tushki7	0:60d829a0353a	1389	#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	1390	#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	1391	#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /!< Bit 2 /
tushki7	0:60d829a0353a	1392	#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /!< OUTSEL[2:0] comparator 2 output redirection /
tushki7	0:60d829a0353a	1393	#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /!< Bit 0 /
tushki7	0:60d829a0353a	1394	#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /!< Bit 1 /
tushki7	0:60d829a0353a	1395	#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /!< Bit 2 /
tushki7	0:60d829a0353a	1396
tushki7	0:60d829a0353a	1397	#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /!< Bit 26 /
tushki7	0:60d829a0353a	1398	#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /!< Bit 27 /
tushki7	0:60d829a0353a	1399	#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /!< Bit 28 /
tushki7	0:60d829a0353a	1400
tushki7	0:60d829a0353a	1401	#define COMP_CSR_CAIE ((uint32_t)0x20000000) /!< Bit 29 /
tushki7	0:60d829a0353a	1402	#define COMP_CSR_CAIF ((uint32_t)0x40000000) /!< Bit 30 /
tushki7	0:60d829a0353a	1403	#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /!< Bit 31 /
tushki7	0:60d829a0353a	1404
tushki7	0:60d829a0353a	1405	/******************************************************************************/
tushki7	0:60d829a0353a	1406	/* */
tushki7	0:60d829a0353a	1407	/* Operational Amplifier (OPAMP) */
tushki7	0:60d829a0353a	1408	/* */
tushki7	0:60d829a0353a	1409	/******************************************************************************/
tushki7	0:60d829a0353a	1410	/***************** Bit definition for OPAMP_CSR register ****************/
tushki7	0:60d829a0353a	1411	#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /!< OPAMP1 disable /
tushki7	0:60d829a0353a	1412	#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /!< Switch 3 for OPAMP1 Enable /
tushki7	0:60d829a0353a	1413	#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /!< Switch 4 for OPAMP1 Enable /
tushki7	0:60d829a0353a	1414	#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /!< Switch 5 for OPAMP1 Enable /
tushki7	0:60d829a0353a	1415	#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /!< Switch 6 for OPAMP1 Enable /
tushki7	0:60d829a0353a	1416	#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /!< OPAMP1 Offset calibration for P differential pair /
tushki7	0:60d829a0353a	1417	#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /!< OPAMP1 Offset calibration for N differential pair /
tushki7	0:60d829a0353a	1418	#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /!< OPAMP1 Low power enable /
tushki7	0:60d829a0353a	1419	#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /!< OPAMP2 disable /
tushki7	0:60d829a0353a	1420	#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /!< Switch 3 for OPAMP2 Enable /
tushki7	0:60d829a0353a	1421	#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /!< Switch 4 for OPAMP2 Enable /
tushki7	0:60d829a0353a	1422	#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /!< Switch 5 for OPAMP2 Enable /
tushki7	0:60d829a0353a	1423	#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /!< Switch 6 for OPAMP2 Enable /
tushki7	0:60d829a0353a	1424	#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /!< OPAMP2 Offset calibration for P differential pair /
tushki7	0:60d829a0353a	1425	#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /!< OPAMP2 Offset calibration for N differential pair /
tushki7	0:60d829a0353a	1426	#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /!< OPAMP2 Low power enable /
tushki7	0:60d829a0353a	1427	#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /!< Switch ANA Enable for OPAMP1 /
tushki7	0:60d829a0353a	1428	#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /!< Switch ANA Enable for OPAMP2 /
tushki7	0:60d829a0353a	1429	#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /!< Switch 7 for OPAMP2 Enable /
tushki7	0:60d829a0353a	1430	#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /!< Power range selection /
tushki7	0:60d829a0353a	1431	#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /!< OPAMP1 calibration output /
tushki7	0:60d829a0353a	1432	#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /!< OPAMP2 calibration output /
tushki7	0:60d829a0353a	1433
tushki7	0:60d829a0353a	1434	/***************** Bit definition for OPAMP_OTR register ****************/
tushki7	0:60d829a0353a	1435	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /!< Offset trim for transistors differential pair PMOS of OPAMP1 /
tushki7	0:60d829a0353a	1436	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /!< Offset trim for transistors differential pair NMOS of OPAMP1 /
tushki7	0:60d829a0353a	1437	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /!< Offset trim for transistors differential pair PMOS of OPAMP2 /
tushki7	0:60d829a0353a	1438	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /!< Offset trim for transistors differential pair NMOS of OPAMP2 /
tushki7	0:60d829a0353a	1439	#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /!< Switch to OPAMP offset user trimmed values /
tushki7	0:60d829a0353a	1440
tushki7	0:60d829a0353a	1441	/***************** Bit definition for OPAMP_LPOTR register **************/
tushki7	0:60d829a0353a	1442	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /!< Offset trim for transistors differential pair PMOS of OPAMP1 /
tushki7	0:60d829a0353a	1443	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /!< Offset trim for transistors differential pair NMOS of OPAMP1 /
tushki7	0:60d829a0353a	1444	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /!< Offset trim for transistors differential pair PMOS of OPAMP2 /
tushki7	0:60d829a0353a	1445	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /!< Offset trim for transistors differential pair NMOS of OPAMP2 /
tushki7	0:60d829a0353a	1446
tushki7	0:60d829a0353a	1447	/******************************************************************************/
tushki7	0:60d829a0353a	1448	/* */
tushki7	0:60d829a0353a	1449	/* CRC calculation unit (CRC) */
tushki7	0:60d829a0353a	1450	/* */
tushki7	0:60d829a0353a	1451	/******************************************************************************/
tushki7	0:60d829a0353a	1452
tushki7	0:60d829a0353a	1453	/***************** Bit definition for CRC_DR register *******************/
tushki7	0:60d829a0353a	1454	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
tushki7	0:60d829a0353a	1455
tushki7	0:60d829a0353a	1456	/***************** Bit definition for CRC_IDR register ******************/
tushki7	0:60d829a0353a	1457	#define CRC_IDR_IDR ((uint32_t)0x000000FF) /!< General-purpose 8-bit data register bits /
tushki7	0:60d829a0353a	1458
tushki7	0:60d829a0353a	1459	/****************** Bit definition for CRC_CR register ******************/
tushki7	0:60d829a0353a	1460	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
tushki7	0:60d829a0353a	1461
tushki7	0:60d829a0353a	1462	/******************************************************************************/
tushki7	0:60d829a0353a	1463	/* */
tushki7	0:60d829a0353a	1464	/* Digital to Analog Converter (DAC) */
tushki7	0:60d829a0353a	1465	/* */
tushki7	0:60d829a0353a	1466	/******************************************************************************/
tushki7	0:60d829a0353a	1467
tushki7	0:60d829a0353a	1468	/****************** Bit definition for DAC_CR register ******************/
tushki7	0:60d829a0353a	1469	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
tushki7	0:60d829a0353a	1470	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!<DAC channel1 output buffer disable /
tushki7	0:60d829a0353a	1471	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
tushki7	0:60d829a0353a	1472
tushki7	0:60d829a0353a	1473	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
tushki7	0:60d829a0353a	1474	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
tushki7	0:60d829a0353a	1475	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
tushki7	0:60d829a0353a	1476	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
tushki7	0:60d829a0353a	1477
tushki7	0:60d829a0353a	1478	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
tushki7	0:60d829a0353a	1479	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
tushki7	0:60d829a0353a	1480	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
tushki7	0:60d829a0353a	1481
tushki7	0:60d829a0353a	1482	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
tushki7	0:60d829a0353a	1483	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	1484	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	1485	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
tushki7	0:60d829a0353a	1486	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
tushki7	0:60d829a0353a	1487
tushki7	0:60d829a0353a	1488	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
tushki7	0:60d829a0353a	1489	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!<DAC channel1 DMA Interrupt enable /
tushki7	0:60d829a0353a	1490	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
tushki7	0:60d829a0353a	1491	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!<DAC channel2 output buffer disable /
tushki7	0:60d829a0353a	1492	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
tushki7	0:60d829a0353a	1493
tushki7	0:60d829a0353a	1494	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
tushki7	0:60d829a0353a	1495	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
tushki7	0:60d829a0353a	1496	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
tushki7	0:60d829a0353a	1497	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
tushki7	0:60d829a0353a	1498
tushki7	0:60d829a0353a	1499	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
tushki7	0:60d829a0353a	1500	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
tushki7	0:60d829a0353a	1501	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
tushki7	0:60d829a0353a	1502
tushki7	0:60d829a0353a	1503	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
tushki7	0:60d829a0353a	1504	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
tushki7	0:60d829a0353a	1505	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
tushki7	0:60d829a0353a	1506	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
tushki7	0:60d829a0353a	1507	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
tushki7	0:60d829a0353a	1508
tushki7	0:60d829a0353a	1509	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
tushki7	0:60d829a0353a	1510	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun interrupt enable /
tushki7	0:60d829a0353a	1511	/*************** Bit definition for DAC_SWTRIGR register ****************/
tushki7	0:60d829a0353a	1512	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!<DAC channel1 software trigger /
tushki7	0:60d829a0353a	1513	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!<DAC channel2 software trigger /
tushki7	0:60d829a0353a	1514
tushki7	0:60d829a0353a	1515	/*************** Bit definition for DAC_DHR12R1 register ****************/
tushki7	0:60d829a0353a	1516	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
tushki7	0:60d829a0353a	1517
tushki7	0:60d829a0353a	1518	/*************** Bit definition for DAC_DHR12L1 register ****************/
tushki7	0:60d829a0353a	1519	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
tushki7	0:60d829a0353a	1520
tushki7	0:60d829a0353a	1521	/**************** Bit definition for DAC_DHR8R1 register ****************/
tushki7	0:60d829a0353a	1522	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
tushki7	0:60d829a0353a	1523
tushki7	0:60d829a0353a	1524	/*************** Bit definition for DAC_DHR12R2 register ****************/
tushki7	0:60d829a0353a	1525	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!<DAC channel2 12-bit Right aligned data /
tushki7	0:60d829a0353a	1526
tushki7	0:60d829a0353a	1527	/*************** Bit definition for DAC_DHR12L2 register ****************/
tushki7	0:60d829a0353a	1528	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!<DAC channel2 12-bit Left aligned data /
tushki7	0:60d829a0353a	1529
tushki7	0:60d829a0353a	1530	/**************** Bit definition for DAC_DHR8R2 register ****************/
tushki7	0:60d829a0353a	1531	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!<DAC channel2 8-bit Right aligned data /
tushki7	0:60d829a0353a	1532
tushki7	0:60d829a0353a	1533	/*************** Bit definition for DAC_DHR12RD register ****************/
tushki7	0:60d829a0353a	1534	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
tushki7	0:60d829a0353a	1535	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
tushki7	0:60d829a0353a	1536
tushki7	0:60d829a0353a	1537	/*************** Bit definition for DAC_DHR12LD register ****************/
tushki7	0:60d829a0353a	1538	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
tushki7	0:60d829a0353a	1539	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
tushki7	0:60d829a0353a	1540
tushki7	0:60d829a0353a	1541	/**************** Bit definition for DAC_DHR8RD register ****************/
tushki7	0:60d829a0353a	1542	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
tushki7	0:60d829a0353a	1543	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!<DAC channel2 8-bit Right aligned data /
tushki7	0:60d829a0353a	1544
tushki7	0:60d829a0353a	1545	/***************** Bit definition for DAC_DOR1 register *****************/
tushki7	0:60d829a0353a	1546	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!<DAC channel1 data output /
tushki7	0:60d829a0353a	1547
tushki7	0:60d829a0353a	1548	/***************** Bit definition for DAC_DOR2 register *****************/
tushki7	0:60d829a0353a	1549	#define DAC_DOR2_DACC2DOR ((uint_t)0x00000FFF) /!<DAC channel2 data output /
tushki7	0:60d829a0353a	1550
tushki7	0:60d829a0353a	1551	/****************** Bit definition for DAC_SR register ******************/
tushki7	0:60d829a0353a	1552	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
tushki7	0:60d829a0353a	1553	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
tushki7	0:60d829a0353a	1554
tushki7	0:60d829a0353a	1555	/******************************************************************************/
tushki7	0:60d829a0353a	1556	/* */
tushki7	0:60d829a0353a	1557	/* Debug MCU (DBGMCU) */
tushki7	0:60d829a0353a	1558	/* */
tushki7	0:60d829a0353a	1559	/******************************************************************************/
tushki7	0:60d829a0353a	1560
tushki7	0:60d829a0353a	1561	/************** Bit definition for DBGMCU_IDCODE register ***************/
tushki7	0:60d829a0353a	1562	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
tushki7	0:60d829a0353a	1563
tushki7	0:60d829a0353a	1564	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
tushki7	0:60d829a0353a	1565	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	1566	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	1567	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
tushki7	0:60d829a0353a	1568	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
tushki7	0:60d829a0353a	1569	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
tushki7	0:60d829a0353a	1570	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
tushki7	0:60d829a0353a	1571	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
tushki7	0:60d829a0353a	1572	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
tushki7	0:60d829a0353a	1573	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
tushki7	0:60d829a0353a	1574	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
tushki7	0:60d829a0353a	1575	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
tushki7	0:60d829a0353a	1576	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
tushki7	0:60d829a0353a	1577	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
tushki7	0:60d829a0353a	1578	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
tushki7	0:60d829a0353a	1579	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
tushki7	0:60d829a0353a	1580	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
tushki7	0:60d829a0353a	1581
tushki7	0:60d829a0353a	1582	/**************** Bit definition for DBGMCU_CR register *****************/
tushki7	0:60d829a0353a	1583	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
tushki7	0:60d829a0353a	1584	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
tushki7	0:60d829a0353a	1585	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
tushki7	0:60d829a0353a	1586	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
tushki7	0:60d829a0353a	1587
tushki7	0:60d829a0353a	1588	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
tushki7	0:60d829a0353a	1589	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	1590	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	1591
tushki7	0:60d829a0353a	1592	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
tushki7	0:60d829a0353a	1593
tushki7	0:60d829a0353a	1594	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
tushki7	0:60d829a0353a	1595	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
tushki7	0:60d829a0353a	1596	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /!< TIM4 counter stopped when core is halted /
tushki7	0:60d829a0353a	1597	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /!< TIM5 counter stopped when core is halted /
tushki7	0:60d829a0353a	1598	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted /
tushki7	0:60d829a0353a	1599	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /!< TIM7 counter stopped when core is halted /
tushki7	0:60d829a0353a	1600	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Counter stopped when Core is halted /
tushki7	0:60d829a0353a	1601	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
tushki7	0:60d829a0353a	1602	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
tushki7	0:60d829a0353a	1603	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< SMBUS timeout mode stopped when Core is halted /
tushki7	0:60d829a0353a	1604	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /!< SMBUS timeout mode stopped when Core is halted /
tushki7	0:60d829a0353a	1605
tushki7	0:60d829a0353a	1606	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
tushki7	0:60d829a0353a	1607
tushki7	0:60d829a0353a	1608	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /!< TIM9 counter stopped when core is halted /
tushki7	0:60d829a0353a	1609	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /!< TIM10 counter stopped when core is halted /
tushki7	0:60d829a0353a	1610	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /!< TIM11 counter stopped when core is halted /
tushki7	0:60d829a0353a	1611
tushki7	0:60d829a0353a	1612	/******************************************************************************/
tushki7	0:60d829a0353a	1613	/* */
tushki7	0:60d829a0353a	1614	/* DMA Controller (DMA) */
tushki7	0:60d829a0353a	1615	/* */
tushki7	0:60d829a0353a	1616	/******************************************************************************/
tushki7	0:60d829a0353a	1617
tushki7	0:60d829a0353a	1618	/***************** Bit definition for DMA_ISR register ******************/
tushki7	0:60d829a0353a	1619	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
tushki7	0:60d829a0353a	1620	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
tushki7	0:60d829a0353a	1621	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
tushki7	0:60d829a0353a	1622	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
tushki7	0:60d829a0353a	1623	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
tushki7	0:60d829a0353a	1624	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
tushki7	0:60d829a0353a	1625	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
tushki7	0:60d829a0353a	1626	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
tushki7	0:60d829a0353a	1627	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
tushki7	0:60d829a0353a	1628	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
tushki7	0:60d829a0353a	1629	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
tushki7	0:60d829a0353a	1630	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
tushki7	0:60d829a0353a	1631	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
tushki7	0:60d829a0353a	1632	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
tushki7	0:60d829a0353a	1633	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
tushki7	0:60d829a0353a	1634	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
tushki7	0:60d829a0353a	1635	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
tushki7	0:60d829a0353a	1636	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
tushki7	0:60d829a0353a	1637	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
tushki7	0:60d829a0353a	1638	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
tushki7	0:60d829a0353a	1639	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
tushki7	0:60d829a0353a	1640	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
tushki7	0:60d829a0353a	1641	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
tushki7	0:60d829a0353a	1642	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
tushki7	0:60d829a0353a	1643	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
tushki7	0:60d829a0353a	1644	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
tushki7	0:60d829a0353a	1645	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
tushki7	0:60d829a0353a	1646	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
tushki7	0:60d829a0353a	1647
tushki7	0:60d829a0353a	1648	/***************** Bit definition for DMA_IFCR register *****************/
tushki7	0:60d829a0353a	1649	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
tushki7	0:60d829a0353a	1650	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
tushki7	0:60d829a0353a	1651	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
tushki7	0:60d829a0353a	1652	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
tushki7	0:60d829a0353a	1653	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
tushki7	0:60d829a0353a	1654	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
tushki7	0:60d829a0353a	1655	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
tushki7	0:60d829a0353a	1656	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
tushki7	0:60d829a0353a	1657	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
tushki7	0:60d829a0353a	1658	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
tushki7	0:60d829a0353a	1659	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
tushki7	0:60d829a0353a	1660	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
tushki7	0:60d829a0353a	1661	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
tushki7	0:60d829a0353a	1662	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
tushki7	0:60d829a0353a	1663	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
tushki7	0:60d829a0353a	1664	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
tushki7	0:60d829a0353a	1665	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
tushki7	0:60d829a0353a	1666	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
tushki7	0:60d829a0353a	1667	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
tushki7	0:60d829a0353a	1668	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
tushki7	0:60d829a0353a	1669	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
tushki7	0:60d829a0353a	1670	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
tushki7	0:60d829a0353a	1671	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
tushki7	0:60d829a0353a	1672	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
tushki7	0:60d829a0353a	1673	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
tushki7	0:60d829a0353a	1674	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
tushki7	0:60d829a0353a	1675	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
tushki7	0:60d829a0353a	1676	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
tushki7	0:60d829a0353a	1677
tushki7	0:60d829a0353a	1678	/***************** Bit definition for DMA_CCR register *****************/
tushki7	0:60d829a0353a	1679	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable/
tushki7	0:60d829a0353a	1680	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
tushki7	0:60d829a0353a	1681	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
tushki7	0:60d829a0353a	1682	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
tushki7	0:60d829a0353a	1683	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
tushki7	0:60d829a0353a	1684	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
tushki7	0:60d829a0353a	1685	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
tushki7	0:60d829a0353a	1686	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
tushki7	0:60d829a0353a	1687
tushki7	0:60d829a0353a	1688	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
tushki7	0:60d829a0353a	1689	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	1690	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	1691
tushki7	0:60d829a0353a	1692	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
tushki7	0:60d829a0353a	1693	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1694	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1695
tushki7	0:60d829a0353a	1696	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
tushki7	0:60d829a0353a	1697	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	1698	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	1699
tushki7	0:60d829a0353a	1700	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
tushki7	0:60d829a0353a	1701
tushki7	0:60d829a0353a	1702	/**************** Bit definition for DMA_CNDTR1 register ****************/
tushki7	0:60d829a0353a	1703	#define DMA_CNDTR1_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
tushki7	0:60d829a0353a	1704
tushki7	0:60d829a0353a	1705	/**************** Bit definition for DMA_CNDTR2 register ****************/
tushki7	0:60d829a0353a	1706	#define DMA_CNDTR2_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
tushki7	0:60d829a0353a	1707
tushki7	0:60d829a0353a	1708	/**************** Bit definition for DMA_CNDTR3 register ****************/
tushki7	0:60d829a0353a	1709	#define DMA_CNDTR3_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
tushki7	0:60d829a0353a	1710
tushki7	0:60d829a0353a	1711	/**************** Bit definition for DMA_CNDTR4 register ****************/
tushki7	0:60d829a0353a	1712	#define DMA_CNDTR4_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
tushki7	0:60d829a0353a	1713
tushki7	0:60d829a0353a	1714	/**************** Bit definition for DMA_CNDTR5 register ****************/
tushki7	0:60d829a0353a	1715	#define DMA_CNDTR5_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
tushki7	0:60d829a0353a	1716
tushki7	0:60d829a0353a	1717	/**************** Bit definition for DMA_CNDTR6 register ****************/
tushki7	0:60d829a0353a	1718	#define DMA_CNDTR6_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
tushki7	0:60d829a0353a	1719
tushki7	0:60d829a0353a	1720	/**************** Bit definition for DMA_CNDTR7 register ****************/
tushki7	0:60d829a0353a	1721	#define DMA_CNDTR7_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
tushki7	0:60d829a0353a	1722
tushki7	0:60d829a0353a	1723	/**************** Bit definition for DMA_CPAR1 register *****************/
tushki7	0:60d829a0353a	1724	#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
tushki7	0:60d829a0353a	1725
tushki7	0:60d829a0353a	1726	/**************** Bit definition for DMA_CPAR2 register *****************/
tushki7	0:60d829a0353a	1727	#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
tushki7	0:60d829a0353a	1728
tushki7	0:60d829a0353a	1729	/**************** Bit definition for DMA_CPAR3 register *****************/
tushki7	0:60d829a0353a	1730	#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
tushki7	0:60d829a0353a	1731
tushki7	0:60d829a0353a	1732
tushki7	0:60d829a0353a	1733	/**************** Bit definition for DMA_CPAR4 register *****************/
tushki7	0:60d829a0353a	1734	#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
tushki7	0:60d829a0353a	1735
tushki7	0:60d829a0353a	1736	/**************** Bit definition for DMA_CPAR5 register *****************/
tushki7	0:60d829a0353a	1737	#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
tushki7	0:60d829a0353a	1738
tushki7	0:60d829a0353a	1739	/**************** Bit definition for DMA_CPAR6 register *****************/
tushki7	0:60d829a0353a	1740	#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
tushki7	0:60d829a0353a	1741
tushki7	0:60d829a0353a	1742
tushki7	0:60d829a0353a	1743	/**************** Bit definition for DMA_CPAR7 register *****************/
tushki7	0:60d829a0353a	1744	#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
tushki7	0:60d829a0353a	1745
tushki7	0:60d829a0353a	1746	/**************** Bit definition for DMA_CMAR1 register *****************/
tushki7	0:60d829a0353a	1747	#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
tushki7	0:60d829a0353a	1748
tushki7	0:60d829a0353a	1749	/**************** Bit definition for DMA_CMAR2 register *****************/
tushki7	0:60d829a0353a	1750	#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
tushki7	0:60d829a0353a	1751
tushki7	0:60d829a0353a	1752	/**************** Bit definition for DMA_CMAR3 register *****************/
tushki7	0:60d829a0353a	1753	#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
tushki7	0:60d829a0353a	1754
tushki7	0:60d829a0353a	1755
tushki7	0:60d829a0353a	1756	/**************** Bit definition for DMA_CMAR4 register *****************/
tushki7	0:60d829a0353a	1757	#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
tushki7	0:60d829a0353a	1758
tushki7	0:60d829a0353a	1759	/**************** Bit definition for DMA_CMAR5 register *****************/
tushki7	0:60d829a0353a	1760	#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
tushki7	0:60d829a0353a	1761
tushki7	0:60d829a0353a	1762	/**************** Bit definition for DMA_CMAR6 register *****************/
tushki7	0:60d829a0353a	1763	#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
tushki7	0:60d829a0353a	1764
tushki7	0:60d829a0353a	1765	/**************** Bit definition for DMA_CMAR7 register *****************/
tushki7	0:60d829a0353a	1766	#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
tushki7	0:60d829a0353a	1767
tushki7	0:60d829a0353a	1768	/******************************************************************************/
tushki7	0:60d829a0353a	1769	/* */
tushki7	0:60d829a0353a	1770	/* External Interrupt/Event Controller (EXTI) */
tushki7	0:60d829a0353a	1771	/* */
tushki7	0:60d829a0353a	1772	/******************************************************************************/
tushki7	0:60d829a0353a	1773
tushki7	0:60d829a0353a	1774	/***************** Bit definition for EXTI_IMR register *****************/
tushki7	0:60d829a0353a	1775	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
tushki7	0:60d829a0353a	1776	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
tushki7	0:60d829a0353a	1777	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
tushki7	0:60d829a0353a	1778	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
tushki7	0:60d829a0353a	1779	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
tushki7	0:60d829a0353a	1780	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
tushki7	0:60d829a0353a	1781	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
tushki7	0:60d829a0353a	1782	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
tushki7	0:60d829a0353a	1783	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
tushki7	0:60d829a0353a	1784	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
tushki7	0:60d829a0353a	1785	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
tushki7	0:60d829a0353a	1786	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
tushki7	0:60d829a0353a	1787	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
tushki7	0:60d829a0353a	1788	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
tushki7	0:60d829a0353a	1789	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
tushki7	0:60d829a0353a	1790	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
tushki7	0:60d829a0353a	1791	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
tushki7	0:60d829a0353a	1792	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
tushki7	0:60d829a0353a	1793	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
tushki7	0:60d829a0353a	1794	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
tushki7	0:60d829a0353a	1795	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
tushki7	0:60d829a0353a	1796	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
tushki7	0:60d829a0353a	1797	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
tushki7	0:60d829a0353a	1798	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
tushki7	0:60d829a0353a	1799
tushki7	0:60d829a0353a	1800	/***************** Bit definition for EXTI_EMR register *****************/
tushki7	0:60d829a0353a	1801	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
tushki7	0:60d829a0353a	1802	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
tushki7	0:60d829a0353a	1803	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
tushki7	0:60d829a0353a	1804	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
tushki7	0:60d829a0353a	1805	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
tushki7	0:60d829a0353a	1806	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
tushki7	0:60d829a0353a	1807	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
tushki7	0:60d829a0353a	1808	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
tushki7	0:60d829a0353a	1809	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
tushki7	0:60d829a0353a	1810	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
tushki7	0:60d829a0353a	1811	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
tushki7	0:60d829a0353a	1812	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
tushki7	0:60d829a0353a	1813	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
tushki7	0:60d829a0353a	1814	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
tushki7	0:60d829a0353a	1815	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
tushki7	0:60d829a0353a	1816	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
tushki7	0:60d829a0353a	1817	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
tushki7	0:60d829a0353a	1818	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
tushki7	0:60d829a0353a	1819	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
tushki7	0:60d829a0353a	1820	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
tushki7	0:60d829a0353a	1821	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
tushki7	0:60d829a0353a	1822	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
tushki7	0:60d829a0353a	1823	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
tushki7	0:60d829a0353a	1824	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
tushki7	0:60d829a0353a	1825
tushki7	0:60d829a0353a	1826	/**************** Bit definition for EXTI_RTSR register *****************/
tushki7	0:60d829a0353a	1827	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
tushki7	0:60d829a0353a	1828	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
tushki7	0:60d829a0353a	1829	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
tushki7	0:60d829a0353a	1830	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
tushki7	0:60d829a0353a	1831	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
tushki7	0:60d829a0353a	1832	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
tushki7	0:60d829a0353a	1833	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
tushki7	0:60d829a0353a	1834	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
tushki7	0:60d829a0353a	1835	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
tushki7	0:60d829a0353a	1836	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
tushki7	0:60d829a0353a	1837	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
tushki7	0:60d829a0353a	1838	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
tushki7	0:60d829a0353a	1839	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
tushki7	0:60d829a0353a	1840	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
tushki7	0:60d829a0353a	1841	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
tushki7	0:60d829a0353a	1842	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
tushki7	0:60d829a0353a	1843	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
tushki7	0:60d829a0353a	1844	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
tushki7	0:60d829a0353a	1845	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
tushki7	0:60d829a0353a	1846	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
tushki7	0:60d829a0353a	1847	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
tushki7	0:60d829a0353a	1848	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
tushki7	0:60d829a0353a	1849	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
tushki7	0:60d829a0353a	1850	#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /!< Rising trigger event configuration bit of line 23 /
tushki7	0:60d829a0353a	1851
tushki7	0:60d829a0353a	1852	/**************** Bit definition for EXTI_FTSR register *****************/
tushki7	0:60d829a0353a	1853	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
tushki7	0:60d829a0353a	1854	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
tushki7	0:60d829a0353a	1855	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
tushki7	0:60d829a0353a	1856	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
tushki7	0:60d829a0353a	1857	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
tushki7	0:60d829a0353a	1858	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
tushki7	0:60d829a0353a	1859	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
tushki7	0:60d829a0353a	1860	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
tushki7	0:60d829a0353a	1861	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
tushki7	0:60d829a0353a	1862	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
tushki7	0:60d829a0353a	1863	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
tushki7	0:60d829a0353a	1864	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
tushki7	0:60d829a0353a	1865	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
tushki7	0:60d829a0353a	1866	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
tushki7	0:60d829a0353a	1867	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
tushki7	0:60d829a0353a	1868	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
tushki7	0:60d829a0353a	1869	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
tushki7	0:60d829a0353a	1870	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
tushki7	0:60d829a0353a	1871	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
tushki7	0:60d829a0353a	1872	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
tushki7	0:60d829a0353a	1873	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
tushki7	0:60d829a0353a	1874	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
tushki7	0:60d829a0353a	1875	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
tushki7	0:60d829a0353a	1876	#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /!< Falling trigger event configuration bit of line 23 /
tushki7	0:60d829a0353a	1877
tushki7	0:60d829a0353a	1878	/**************** Bit definition for EXTI_SWIER register ****************/
tushki7	0:60d829a0353a	1879	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
tushki7	0:60d829a0353a	1880	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
tushki7	0:60d829a0353a	1881	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
tushki7	0:60d829a0353a	1882	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
tushki7	0:60d829a0353a	1883	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
tushki7	0:60d829a0353a	1884	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
tushki7	0:60d829a0353a	1885	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
tushki7	0:60d829a0353a	1886	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
tushki7	0:60d829a0353a	1887	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
tushki7	0:60d829a0353a	1888	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
tushki7	0:60d829a0353a	1889	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
tushki7	0:60d829a0353a	1890	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
tushki7	0:60d829a0353a	1891	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
tushki7	0:60d829a0353a	1892	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
tushki7	0:60d829a0353a	1893	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
tushki7	0:60d829a0353a	1894	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
tushki7	0:60d829a0353a	1895	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
tushki7	0:60d829a0353a	1896	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
tushki7	0:60d829a0353a	1897	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
tushki7	0:60d829a0353a	1898	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
tushki7	0:60d829a0353a	1899	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
tushki7	0:60d829a0353a	1900	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
tushki7	0:60d829a0353a	1901	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
tushki7	0:60d829a0353a	1902	#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /!< Software Interrupt on line 23 /
tushki7	0:60d829a0353a	1903
tushki7	0:60d829a0353a	1904	/***************** Bit definition for EXTI_PR register ******************/
tushki7	0:60d829a0353a	1905	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
tushki7	0:60d829a0353a	1906	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
tushki7	0:60d829a0353a	1907	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
tushki7	0:60d829a0353a	1908	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
tushki7	0:60d829a0353a	1909	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
tushki7	0:60d829a0353a	1910	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
tushki7	0:60d829a0353a	1911	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
tushki7	0:60d829a0353a	1912	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
tushki7	0:60d829a0353a	1913	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
tushki7	0:60d829a0353a	1914	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
tushki7	0:60d829a0353a	1915	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
tushki7	0:60d829a0353a	1916	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
tushki7	0:60d829a0353a	1917	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
tushki7	0:60d829a0353a	1918	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
tushki7	0:60d829a0353a	1919	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
tushki7	0:60d829a0353a	1920	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
tushki7	0:60d829a0353a	1921	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
tushki7	0:60d829a0353a	1922	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
tushki7	0:60d829a0353a	1923	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit 18 /
tushki7	0:60d829a0353a	1924	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
tushki7	0:60d829a0353a	1925	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit 20 /
tushki7	0:60d829a0353a	1926	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit 21 /
tushki7	0:60d829a0353a	1927	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit 22 /
tushki7	0:60d829a0353a	1928	#define EXTI_PR_PR23 ((uint32_t)0x00800000) /!< Pending bit 23 /
tushki7	0:60d829a0353a	1929
tushki7	0:60d829a0353a	1930	/******************************************************************************/
tushki7	0:60d829a0353a	1931	/* */
tushki7	0:60d829a0353a	1932	/* FLASH, DATA EEPROM and Option Bytes Registers */
tushki7	0:60d829a0353a	1933	/* (FLASH, DATA_EEPROM, OB) */
tushki7	0:60d829a0353a	1934	/* */
tushki7	0:60d829a0353a	1935	/******************************************************************************/
tushki7	0:60d829a0353a	1936
tushki7	0:60d829a0353a	1937	/***************** Bit definition for FLASH_ACR register ****************/
tushki7	0:60d829a0353a	1938	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< Latency /
tushki7	0:60d829a0353a	1939	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /!< Prefetch Buffer Enable /
tushki7	0:60d829a0353a	1940	#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /!< Access 64 bits /
tushki7	0:60d829a0353a	1941	#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /!< Flash mode during sleep mode /
tushki7	0:60d829a0353a	1942	#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /!< Flash mode during RUN mode /
tushki7	0:60d829a0353a	1943
tushki7	0:60d829a0353a	1944	/***************** Bit definition for FLASH_PECR register ****************/
tushki7	0:60d829a0353a	1945	#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /!< FLASH_PECR and Flash data Lock /
tushki7	0:60d829a0353a	1946	#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /!< Program matrix Lock /
tushki7	0:60d829a0353a	1947	#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /!< Option byte matrix Lock /
tushki7	0:60d829a0353a	1948	#define FLASH_PECR_PROG ((uint32_t)0x00000008) /!< Program matrix selection /
tushki7	0:60d829a0353a	1949	#define FLASH_PECR_DATA ((uint32_t)0x00000010) /!< Data matrix selection /
tushki7	0:60d829a0353a	1950	#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /!< Fixed Time Data write for Word/Half Word/Byte programming /
tushki7	0:60d829a0353a	1951	#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /!< Page erasing mode /
tushki7	0:60d829a0353a	1952	#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /!< Fast Page/Half Page programming mode /
tushki7	0:60d829a0353a	1953	#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /!< Parallel Bank mode /
tushki7	0:60d829a0353a	1954	#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /!< End of programming interrupt /
tushki7	0:60d829a0353a	1955	#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /!< Error interrupt /
tushki7	0:60d829a0353a	1956	#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /!< Launch the option byte loading /
tushki7	0:60d829a0353a	1957
tushki7	0:60d829a0353a	1958	/**************** Bit definition for FLASH_PDKEYR register ****************/
tushki7	0:60d829a0353a	1959	#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /!< FLASH_PEC and data matrix Key /
tushki7	0:60d829a0353a	1960
tushki7	0:60d829a0353a	1961	/**************** Bit definition for FLASH_PEKEYR register ****************/
tushki7	0:60d829a0353a	1962	#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /!< FLASH_PEC and data matrix Key /
tushki7	0:60d829a0353a	1963
tushki7	0:60d829a0353a	1964	/**************** Bit definition for FLASH_PRGKEYR register ****************/
tushki7	0:60d829a0353a	1965	#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /!< Program matrix Key /
tushki7	0:60d829a0353a	1966
tushki7	0:60d829a0353a	1967	/**************** Bit definition for FLASH_OPTKEYR register ****************/
tushki7	0:60d829a0353a	1968	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option bytes matrix Key /
tushki7	0:60d829a0353a	1969
tushki7	0:60d829a0353a	1970	/**************** Bit definition for FLASH_SR register *****************/
tushki7	0:60d829a0353a	1971	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
tushki7	0:60d829a0353a	1972	#define FLASH_SR_EOP ((uint32_t)0x00000002) /!< End Of Programming/
tushki7	0:60d829a0353a	1973	#define FLASH_SR_ENDHV ((uint32_t)0x00000004) /!< End of high voltage /
tushki7	0:60d829a0353a	1974	#define FLASH_SR_READY ((uint32_t)0x00000008) /!< Flash ready after low power mode /
tushki7	0:60d829a0353a	1975
tushki7	0:60d829a0353a	1976	#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /!< Write protected error /
tushki7	0:60d829a0353a	1977	#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /!< Programming Alignment Error /
tushki7	0:60d829a0353a	1978	#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /!< Size error /
tushki7	0:60d829a0353a	1979	#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /!< Option validity error /
tushki7	0:60d829a0353a	1980	#define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /!< Option User validity error /
tushki7	0:60d829a0353a	1981
tushki7	0:60d829a0353a	1982	/**************** Bit definition for FLASH_OBR register *****************/
tushki7	0:60d829a0353a	1983	#define FLASH_OBR_RDPRT ((uint32_t)0x000000FF) /!< Read Protection /
tushki7	0:60d829a0353a	1984	#define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /!< BOR_LEV[3:0] Brown Out Reset Threshold Level/
tushki7	0:60d829a0353a	1985	#define FLASH_OBR_USER ((uint32_t)0x00F00000) /!< User Option Bytes /
tushki7	0:60d829a0353a	1986	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /!< IWDG_SW /
tushki7	0:60d829a0353a	1987	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /!< nRST_STOP /
tushki7	0:60d829a0353a	1988	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /!< nRST_STDBY /
tushki7	0:60d829a0353a	1989	#define FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000) /!< BFB2 /
tushki7	0:60d829a0353a	1990
tushki7	0:60d829a0353a	1991	/**************** Bit definition for FLASH_WRPR register ****************/
tushki7	0:60d829a0353a	1992	#define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
tushki7	0:60d829a0353a	1993	#define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
tushki7	0:60d829a0353a	1994	#define FLASH_WRPR3_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
tushki7	0:60d829a0353a	1995	#define FLASH_WRPR4_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
tushki7	0:60d829a0353a	1996
tushki7	0:60d829a0353a	1997	/******************************************************************************/
tushki7	0:60d829a0353a	1998	/* */
tushki7	0:60d829a0353a	1999	/* General Purpose I/O */
tushki7	0:60d829a0353a	2000	/* */
tushki7	0:60d829a0353a	2001	/******************************************************************************/
tushki7	0:60d829a0353a	2002	/**************** Bits definition for GPIO_MODER register ***************/
tushki7	0:60d829a0353a	2003	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
tushki7	0:60d829a0353a	2004	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2005	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2006
tushki7	0:60d829a0353a	2007	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
tushki7	0:60d829a0353a	2008	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2009	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2010
tushki7	0:60d829a0353a	2011	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
tushki7	0:60d829a0353a	2012	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2013	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2014
tushki7	0:60d829a0353a	2015	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
tushki7	0:60d829a0353a	2016	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2017	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2018
tushki7	0:60d829a0353a	2019	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
tushki7	0:60d829a0353a	2020	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2021	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2022
tushki7	0:60d829a0353a	2023	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
tushki7	0:60d829a0353a	2024	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2025	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2026
tushki7	0:60d829a0353a	2027	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
tushki7	0:60d829a0353a	2028	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2029	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2030
tushki7	0:60d829a0353a	2031	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
tushki7	0:60d829a0353a	2032	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2033	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2034
tushki7	0:60d829a0353a	2035	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
tushki7	0:60d829a0353a	2036	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	2037	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	2038
tushki7	0:60d829a0353a	2039	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
tushki7	0:60d829a0353a	2040	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	2041	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	2042
tushki7	0:60d829a0353a	2043	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
tushki7	0:60d829a0353a	2044	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	2045	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	2046
tushki7	0:60d829a0353a	2047	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
tushki7	0:60d829a0353a	2048	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	2049	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	2050
tushki7	0:60d829a0353a	2051	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
tushki7	0:60d829a0353a	2052	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	2053	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	2054
tushki7	0:60d829a0353a	2055	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
tushki7	0:60d829a0353a	2056	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	2057	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
tushki7	0:60d829a0353a	2058
tushki7	0:60d829a0353a	2059	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
tushki7	0:60d829a0353a	2060	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
tushki7	0:60d829a0353a	2061	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
tushki7	0:60d829a0353a	2062
tushki7	0:60d829a0353a	2063	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
tushki7	0:60d829a0353a	2064	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
tushki7	0:60d829a0353a	2065	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
tushki7	0:60d829a0353a	2066
tushki7	0:60d829a0353a	2067	/**************** Bits definition for GPIO_OTYPER register **************/
tushki7	0:60d829a0353a	2068	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2069	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2070	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2071	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2072	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2073	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2074	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2075	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2076	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2077	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2078	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2079	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2080	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2081	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2082	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2083	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2084
tushki7	0:60d829a0353a	2085	/**************** Bits definition for GPIO_OSPEEDR register *************/
tushki7	0:60d829a0353a	2086	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
tushki7	0:60d829a0353a	2087	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2088	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2089
tushki7	0:60d829a0353a	2090	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
tushki7	0:60d829a0353a	2091	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2092	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2093
tushki7	0:60d829a0353a	2094	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
tushki7	0:60d829a0353a	2095	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2096	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2097
tushki7	0:60d829a0353a	2098	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
tushki7	0:60d829a0353a	2099	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2100	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2101
tushki7	0:60d829a0353a	2102	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
tushki7	0:60d829a0353a	2103	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2104	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2105
tushki7	0:60d829a0353a	2106	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
tushki7	0:60d829a0353a	2107	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2108	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2109
tushki7	0:60d829a0353a	2110	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
tushki7	0:60d829a0353a	2111	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2112	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2113
tushki7	0:60d829a0353a	2114	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
tushki7	0:60d829a0353a	2115	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2116	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2117
tushki7	0:60d829a0353a	2118	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
tushki7	0:60d829a0353a	2119	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	2120	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	2121
tushki7	0:60d829a0353a	2122	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
tushki7	0:60d829a0353a	2123	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	2124	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	2125
tushki7	0:60d829a0353a	2126	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
tushki7	0:60d829a0353a	2127	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	2128	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	2129
tushki7	0:60d829a0353a	2130	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
tushki7	0:60d829a0353a	2131	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	2132	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	2133
tushki7	0:60d829a0353a	2134	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
tushki7	0:60d829a0353a	2135	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	2136	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	2137
tushki7	0:60d829a0353a	2138	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
tushki7	0:60d829a0353a	2139	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	2140	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
tushki7	0:60d829a0353a	2141
tushki7	0:60d829a0353a	2142	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
tushki7	0:60d829a0353a	2143	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
tushki7	0:60d829a0353a	2144	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
tushki7	0:60d829a0353a	2145
tushki7	0:60d829a0353a	2146	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
tushki7	0:60d829a0353a	2147	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
tushki7	0:60d829a0353a	2148	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
tushki7	0:60d829a0353a	2149
tushki7	0:60d829a0353a	2150	/**************** Bits definition for GPIO_PUPDR register ***************/
tushki7	0:60d829a0353a	2151	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
tushki7	0:60d829a0353a	2152	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2153	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2154
tushki7	0:60d829a0353a	2155	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
tushki7	0:60d829a0353a	2156	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2157	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2158
tushki7	0:60d829a0353a	2159	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
tushki7	0:60d829a0353a	2160	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2161	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2162
tushki7	0:60d829a0353a	2163	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
tushki7	0:60d829a0353a	2164	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2165	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2166
tushki7	0:60d829a0353a	2167	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
tushki7	0:60d829a0353a	2168	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2169	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2170
tushki7	0:60d829a0353a	2171	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
tushki7	0:60d829a0353a	2172	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2173	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2174
tushki7	0:60d829a0353a	2175	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
tushki7	0:60d829a0353a	2176	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2177	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2178
tushki7	0:60d829a0353a	2179	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
tushki7	0:60d829a0353a	2180	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2181	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2182
tushki7	0:60d829a0353a	2183	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
tushki7	0:60d829a0353a	2184	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	2185	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	2186
tushki7	0:60d829a0353a	2187	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
tushki7	0:60d829a0353a	2188	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	2189	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	2190
tushki7	0:60d829a0353a	2191	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
tushki7	0:60d829a0353a	2192	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	2193	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	2194
tushki7	0:60d829a0353a	2195	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
tushki7	0:60d829a0353a	2196	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	2197	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	2198
tushki7	0:60d829a0353a	2199	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
tushki7	0:60d829a0353a	2200	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	2201	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	2202
tushki7	0:60d829a0353a	2203	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
tushki7	0:60d829a0353a	2204	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	2205	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
tushki7	0:60d829a0353a	2206
tushki7	0:60d829a0353a	2207	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
tushki7	0:60d829a0353a	2208	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
tushki7	0:60d829a0353a	2209	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
tushki7	0:60d829a0353a	2210	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
tushki7	0:60d829a0353a	2211	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
tushki7	0:60d829a0353a	2212	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
tushki7	0:60d829a0353a	2213
tushki7	0:60d829a0353a	2214	/**************** Bits definition for GPIO_IDR register *****************/
tushki7	0:60d829a0353a	2215	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2216	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2217	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2218	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2219	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2220	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2221	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2222	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2223	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2224	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2225	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2226	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2227	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2228	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2229	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2230	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2231
tushki7	0:60d829a0353a	2232	/**************** Bits definition for GPIO_ODR register *****************/
tushki7	0:60d829a0353a	2233	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2234	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2235	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2236	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2237	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2238	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2239	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2240	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2241	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2242	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2243	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2244	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2245	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2246	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2247	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2248	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2249
tushki7	0:60d829a0353a	2250	/**************** Bits definition for GPIO_BSRR register ****************/
tushki7	0:60d829a0353a	2251	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2252	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2253	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2254	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2255	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2256	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2257	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2258	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2259	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2260	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2261	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2262	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2263	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2264	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2265	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2266	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2267	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	2268	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	2269	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	2270	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	2271	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	2272	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	2273	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	2274	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	2275	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	2276	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	2277	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	2278	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
tushki7	0:60d829a0353a	2279	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
tushki7	0:60d829a0353a	2280	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
tushki7	0:60d829a0353a	2281	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
tushki7	0:60d829a0353a	2282	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
tushki7	0:60d829a0353a	2283
tushki7	0:60d829a0353a	2284	/**************** Bit definition for GPIO_LCKR register ******************/
tushki7	0:60d829a0353a	2285	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2286	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2287	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2288	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2289	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2290	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2291	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2292	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2293	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2294	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2295	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2296	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2297	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2298	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2299	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2300	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2301	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	2302
tushki7	0:60d829a0353a	2303	/**************** Bit definition for GPIO_AFRL register ******************/
tushki7	0:60d829a0353a	2304	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
tushki7	0:60d829a0353a	2305	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
tushki7	0:60d829a0353a	2306	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
tushki7	0:60d829a0353a	2307	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
tushki7	0:60d829a0353a	2308	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
tushki7	0:60d829a0353a	2309	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
tushki7	0:60d829a0353a	2310	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
tushki7	0:60d829a0353a	2311	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
tushki7	0:60d829a0353a	2312
tushki7	0:60d829a0353a	2313	/**************** Bit definition for GPIO_AFRH register ******************/
tushki7	0:60d829a0353a	2314	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
tushki7	0:60d829a0353a	2315	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
tushki7	0:60d829a0353a	2316	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
tushki7	0:60d829a0353a	2317	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
tushki7	0:60d829a0353a	2318	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
tushki7	0:60d829a0353a	2319	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
tushki7	0:60d829a0353a	2320	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
tushki7	0:60d829a0353a	2321	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
tushki7	0:60d829a0353a	2322
tushki7	0:60d829a0353a	2323	/**************** Bit definition for GPIO_BRR register *******************/
tushki7	0:60d829a0353a	2324	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2325	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2326	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2327	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2328	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2329	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2330	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2331	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	2332	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2333	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2334	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2335	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2336	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2337	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2338	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2339	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2340
tushki7	0:60d829a0353a	2341
tushki7	0:60d829a0353a	2342	/******************************************************************************/
tushki7	0:60d829a0353a	2343	/* */
tushki7	0:60d829a0353a	2344	/* Inter-integrated Circuit Interface (I2C) */
tushki7	0:60d829a0353a	2345	/* */
tushki7	0:60d829a0353a	2346	/******************************************************************************/
tushki7	0:60d829a0353a	2347
tushki7	0:60d829a0353a	2348	/***************** Bit definition for I2C_CR1 register ******************/
tushki7	0:60d829a0353a	2349	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
tushki7	0:60d829a0353a	2350	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
tushki7	0:60d829a0353a	2351	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
tushki7	0:60d829a0353a	2352	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
tushki7	0:60d829a0353a	2353	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
tushki7	0:60d829a0353a	2354	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
tushki7	0:60d829a0353a	2355	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
tushki7	0:60d829a0353a	2356	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
tushki7	0:60d829a0353a	2357	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
tushki7	0:60d829a0353a	2358	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
tushki7	0:60d829a0353a	2359	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
tushki7	0:60d829a0353a	2360	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
tushki7	0:60d829a0353a	2361	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
tushki7	0:60d829a0353a	2362	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
tushki7	0:60d829a0353a	2363
tushki7	0:60d829a0353a	2364	/***************** Bit definition for I2C_CR2 register ******************/
tushki7	0:60d829a0353a	2365	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
tushki7	0:60d829a0353a	2366	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2367	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2368	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2369	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	2370	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	2371	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	2372
tushki7	0:60d829a0353a	2373	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
tushki7	0:60d829a0353a	2374	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
tushki7	0:60d829a0353a	2375	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
tushki7	0:60d829a0353a	2376	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
tushki7	0:60d829a0353a	2377	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
tushki7	0:60d829a0353a	2378
tushki7	0:60d829a0353a	2379	/***************** Bit definition for I2C_OAR1 register *****************/
tushki7	0:60d829a0353a	2380	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
tushki7	0:60d829a0353a	2381	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
tushki7	0:60d829a0353a	2382
tushki7	0:60d829a0353a	2383	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2384	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2385	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2386	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	2387	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	2388	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	2389	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	2390	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	2391	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	2392	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	2393
tushki7	0:60d829a0353a	2394	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
tushki7	0:60d829a0353a	2395
tushki7	0:60d829a0353a	2396	/***************** Bit definition for I2C_OAR2 register *****************/
tushki7	0:60d829a0353a	2397	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
tushki7	0:60d829a0353a	2398	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
tushki7	0:60d829a0353a	2399
tushki7	0:60d829a0353a	2400	/****************** Bit definition for I2C_DR register ******************/
tushki7	0:60d829a0353a	2401	#define I2C_DR_DR ((uint32_t)0x000000FF) /!< 8-bit Data Register /
tushki7	0:60d829a0353a	2402
tushki7	0:60d829a0353a	2403	/***************** Bit definition for I2C_SR1 register ******************/
tushki7	0:60d829a0353a	2404	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
tushki7	0:60d829a0353a	2405	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
tushki7	0:60d829a0353a	2406	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
tushki7	0:60d829a0353a	2407	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
tushki7	0:60d829a0353a	2408	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
tushki7	0:60d829a0353a	2409	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
tushki7	0:60d829a0353a	2410	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
tushki7	0:60d829a0353a	2411	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
tushki7	0:60d829a0353a	2412	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
tushki7	0:60d829a0353a	2413	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
tushki7	0:60d829a0353a	2414	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
tushki7	0:60d829a0353a	2415	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
tushki7	0:60d829a0353a	2416	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
tushki7	0:60d829a0353a	2417	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
tushki7	0:60d829a0353a	2418
tushki7	0:60d829a0353a	2419	/***************** Bit definition for I2C_SR2 register ******************/
tushki7	0:60d829a0353a	2420	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
tushki7	0:60d829a0353a	2421	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
tushki7	0:60d829a0353a	2422	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
tushki7	0:60d829a0353a	2423	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
tushki7	0:60d829a0353a	2424	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
tushki7	0:60d829a0353a	2425	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
tushki7	0:60d829a0353a	2426	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
tushki7	0:60d829a0353a	2427	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
tushki7	0:60d829a0353a	2428
tushki7	0:60d829a0353a	2429	/***************** Bit definition for I2C_CCR register ******************/
tushki7	0:60d829a0353a	2430	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
tushki7	0:60d829a0353a	2431	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
tushki7	0:60d829a0353a	2432	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
tushki7	0:60d829a0353a	2433
tushki7	0:60d829a0353a	2434	/**************** Bit definition for I2C_TRISE register *****************/
tushki7	0:60d829a0353a	2435	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
tushki7	0:60d829a0353a	2436
tushki7	0:60d829a0353a	2437	/******************************************************************************/
tushki7	0:60d829a0353a	2438	/* */
tushki7	0:60d829a0353a	2439	/* Independent WATCHDOG (IWDG) */
tushki7	0:60d829a0353a	2440	/* */
tushki7	0:60d829a0353a	2441	/******************************************************************************/
tushki7	0:60d829a0353a	2442
tushki7	0:60d829a0353a	2443	/***************** Bit definition for IWDG_KR register ******************/
tushki7	0:60d829a0353a	2444	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
tushki7	0:60d829a0353a	2445
tushki7	0:60d829a0353a	2446	/***************** Bit definition for IWDG_PR register ******************/
tushki7	0:60d829a0353a	2447	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
tushki7	0:60d829a0353a	2448	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2449	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2450	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2451
tushki7	0:60d829a0353a	2452	/***************** Bit definition for IWDG_RLR register *****************/
tushki7	0:60d829a0353a	2453	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
tushki7	0:60d829a0353a	2454
tushki7	0:60d829a0353a	2455	/***************** Bit definition for IWDG_SR register ******************/
tushki7	0:60d829a0353a	2456	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
tushki7	0:60d829a0353a	2457	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
tushki7	0:60d829a0353a	2458
tushki7	0:60d829a0353a	2459	/******************************************************************************/
tushki7	0:60d829a0353a	2460	/* */
tushki7	0:60d829a0353a	2461	/* LCD Controller (LCD) */
tushki7	0:60d829a0353a	2462	/* */
tushki7	0:60d829a0353a	2463	/******************************************************************************/
tushki7	0:60d829a0353a	2464
tushki7	0:60d829a0353a	2465	/***************** Bit definition for LCD_CR register *******************/
tushki7	0:60d829a0353a	2466	#define LCD_CR_LCDEN ((uint32_t)0x00000001) /!< LCD Enable Bit /
tushki7	0:60d829a0353a	2467	#define LCD_CR_VSEL ((uint32_t)0x00000002) /!< Voltage source selector Bit /
tushki7	0:60d829a0353a	2468
tushki7	0:60d829a0353a	2469	#define LCD_CR_DUTY ((uint32_t)0x0000001C) /!< DUTY[2:0] bits (Duty selector) /
tushki7	0:60d829a0353a	2470	#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /!< Duty selector Bit 0 /
tushki7	0:60d829a0353a	2471	#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /!< Duty selector Bit 1 /
tushki7	0:60d829a0353a	2472	#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /!< Duty selector Bit 2 /
tushki7	0:60d829a0353a	2473
tushki7	0:60d829a0353a	2474	#define LCD_CR_BIAS ((uint32_t)0x00000060) /!< BIAS[1:0] bits (Bias selector) /
tushki7	0:60d829a0353a	2475	#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /!< Bias selector Bit 0 /
tushki7	0:60d829a0353a	2476	#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /!< Bias selector Bit 1 /
tushki7	0:60d829a0353a	2477
tushki7	0:60d829a0353a	2478	#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /!< Mux Segment Enable Bit /
tushki7	0:60d829a0353a	2479
tushki7	0:60d829a0353a	2480	/***************** Bit definition for LCD_FCR register ******************/
tushki7	0:60d829a0353a	2481	#define LCD_FCR_HD ((uint32_t)0x00000001) /!< High Drive Enable Bit /
tushki7	0:60d829a0353a	2482	#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /!< Start of Frame Interrupt Enable Bit /
tushki7	0:60d829a0353a	2483	#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /!< Update Display Done Interrupt Enable Bit /
tushki7	0:60d829a0353a	2484
tushki7	0:60d829a0353a	2485	#define LCD_FCR_PON ((uint32_t)0x00000070) /!< PON[2:0] bits (Puls ON Duration) /
tushki7	0:60d829a0353a	2486	#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	2487	#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	2488	#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /!< Bit 2 /
tushki7	0:60d829a0353a	2489
tushki7	0:60d829a0353a	2490	#define LCD_FCR_DEAD ((uint32_t)0x00000380) /!< DEAD[2:0] bits (DEAD Time) /
tushki7	0:60d829a0353a	2491	#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /!< Bit 0 /
tushki7	0:60d829a0353a	2492	#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /!< Bit 1 /
tushki7	0:60d829a0353a	2493	#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /!< Bit 2 /
tushki7	0:60d829a0353a	2494
tushki7	0:60d829a0353a	2495	#define LCD_FCR_CC ((uint32_t)0x00001C00) /!< CC[2:0] bits (Contrast Control) /
tushki7	0:60d829a0353a	2496	#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	2497	#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	2498	#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	2499
tushki7	0:60d829a0353a	2500	#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /!< BLINKF[2:0] bits (Blink Frequency) /
tushki7	0:60d829a0353a	2501	#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /!< Bit 0 /
tushki7	0:60d829a0353a	2502	#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /!< Bit 1 /
tushki7	0:60d829a0353a	2503	#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /!< Bit 2 /
tushki7	0:60d829a0353a	2504
tushki7	0:60d829a0353a	2505	#define LCD_FCR_BLINK ((uint32_t)0x00030000) /!< BLINK[1:0] bits (Blink Enable) /
tushki7	0:60d829a0353a	2506	#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	2507	#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	2508
tushki7	0:60d829a0353a	2509	#define LCD_FCR_DIV ((uint32_t)0x003C0000) /!< DIV[3:0] bits (Divider) /
tushki7	0:60d829a0353a	2510	#define LCD_FCR_PS ((uint32_t)0x03C00000) /!< PS[3:0] bits (Prescaler) /
tushki7	0:60d829a0353a	2511
tushki7	0:60d829a0353a	2512	/***************** Bit definition for LCD_SR register *******************/
tushki7	0:60d829a0353a	2513	#define LCD_SR_ENS ((uint32_t)0x00000001) /!< LCD Enabled Bit /
tushki7	0:60d829a0353a	2514	#define LCD_SR_SOF ((uint32_t)0x00000002) /!< Start Of Frame Flag Bit /
tushki7	0:60d829a0353a	2515	#define LCD_SR_UDR ((uint32_t)0x00000004) /!< Update Display Request Bit /
tushki7	0:60d829a0353a	2516	#define LCD_SR_UDD ((uint32_t)0x00000008) /!< Update Display Done Flag Bit /
tushki7	0:60d829a0353a	2517	#define LCD_SR_RDY ((uint32_t)0x00000010) /!< Ready Flag Bit /
tushki7	0:60d829a0353a	2518	#define LCD_SR_FCRSR ((uint32_t)0x00000020) /!< LCD FCR Register Synchronization Flag Bit /
tushki7	0:60d829a0353a	2519
tushki7	0:60d829a0353a	2520	/***************** Bit definition for LCD_CLR register ******************/
tushki7	0:60d829a0353a	2521	#define LCD_CLR_SOFC ((uint32_t)0x00000002) /!< Start Of Frame Flag Clear Bit /
tushki7	0:60d829a0353a	2522	#define LCD_CLR_UDDC ((uint32_t)0x00000008) /!< Update Display Done Flag Clear Bit /
tushki7	0:60d829a0353a	2523
tushki7	0:60d829a0353a	2524	/***************** Bit definition for LCD_RAM register ******************/
tushki7	0:60d829a0353a	2525	#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /!< Segment Data Bits /
tushki7	0:60d829a0353a	2526
tushki7	0:60d829a0353a	2527	/******************************************************************************/
tushki7	0:60d829a0353a	2528	/* */
tushki7	0:60d829a0353a	2529	/* Power Control (PWR) */
tushki7	0:60d829a0353a	2530	/* */
tushki7	0:60d829a0353a	2531	/******************************************************************************/
tushki7	0:60d829a0353a	2532
tushki7	0:60d829a0353a	2533	/****************** Bit definition for PWR_CR register ******************/
tushki7	0:60d829a0353a	2534	#define PWR_CR_LPSDSR ((uint32_t)0x00000001) /!< Low-power deepsleep/sleep/low power run /
tushki7	0:60d829a0353a	2535	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
tushki7	0:60d829a0353a	2536	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
tushki7	0:60d829a0353a	2537	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
tushki7	0:60d829a0353a	2538	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
tushki7	0:60d829a0353a	2539
tushki7	0:60d829a0353a	2540	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
tushki7	0:60d829a0353a	2541	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	2542	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	2543	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	2544
tushki7	0:60d829a0353a	2545	/!< PVD level configuration /
tushki7	0:60d829a0353a	2546	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
tushki7	0:60d829a0353a	2547	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
tushki7	0:60d829a0353a	2548	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
tushki7	0:60d829a0353a	2549	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
tushki7	0:60d829a0353a	2550	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
tushki7	0:60d829a0353a	2551	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
tushki7	0:60d829a0353a	2552	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
tushki7	0:60d829a0353a	2553	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
tushki7	0:60d829a0353a	2554
tushki7	0:60d829a0353a	2555	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
tushki7	0:60d829a0353a	2556	#define PWR_CR_ULP ((uint32_t)0x00000200) /!< Ultra Low Power mode /
tushki7	0:60d829a0353a	2557	#define PWR_CR_FWU ((uint32_t)0x00000400) /!< Fast wakeup /
tushki7	0:60d829a0353a	2558
tushki7	0:60d829a0353a	2559	#define PWR_CR_VOS ((uint32_t)0x00001800) /!< VOS[1:0] bits (Voltage scaling range selection) /
tushki7	0:60d829a0353a	2560	#define PWR_CR_VOS_0 ((uint32_t)0x00000800) /!< Bit 0 /
tushki7	0:60d829a0353a	2561	#define PWR_CR_VOS_1 ((uint32_t)0x00001000) /!< Bit 1 /
tushki7	0:60d829a0353a	2562	#define PWR_CR_LPRUN ((uint32_t)0x00004000) /!< Low power run mode /
tushki7	0:60d829a0353a	2563
tushki7	0:60d829a0353a	2564	/***************** Bit definition for PWR_CSR register ******************/
tushki7	0:60d829a0353a	2565	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
tushki7	0:60d829a0353a	2566	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
tushki7	0:60d829a0353a	2567	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
tushki7	0:60d829a0353a	2568	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /!< Internal voltage reference (VREFINT) ready flag /
tushki7	0:60d829a0353a	2569	#define PWR_CSR_VOSF ((uint32_t)0x00000010) /!< Voltage Scaling select flag /
tushki7	0:60d829a0353a	2570	#define PWR_CSR_REGLPF ((uint32_t)0x00000020) /!< Regulator LP flag /
tushki7	0:60d829a0353a	2571
tushki7	0:60d829a0353a	2572	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
tushki7	0:60d829a0353a	2573	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
tushki7	0:60d829a0353a	2574	#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /!< Enable WKUP pin 3 /
tushki7	0:60d829a0353a	2575
tushki7	0:60d829a0353a	2576	/******************************************************************************/
tushki7	0:60d829a0353a	2577	/* */
tushki7	0:60d829a0353a	2578	/* Reset and Clock Control (RCC) */
tushki7	0:60d829a0353a	2579	/* */
tushki7	0:60d829a0353a	2580	/******************************************************************************/
tushki7	0:60d829a0353a	2581	/****************** Bit definition for RCC_CR register ******************/
tushki7	0:60d829a0353a	2582	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
tushki7	0:60d829a0353a	2583	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
tushki7	0:60d829a0353a	2584
tushki7	0:60d829a0353a	2585	#define RCC_CR_MSION ((uint32_t)0x00000100) /!< Internal Multi Speed clock enable /
tushki7	0:60d829a0353a	2586	#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /!< Internal Multi Speed clock ready flag /
tushki7	0:60d829a0353a	2587
tushki7	0:60d829a0353a	2588	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
tushki7	0:60d829a0353a	2589	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
tushki7	0:60d829a0353a	2590	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
tushki7	0:60d829a0353a	2591
tushki7	0:60d829a0353a	2592	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
tushki7	0:60d829a0353a	2593	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
tushki7	0:60d829a0353a	2594	#define RCC_CR_CSSON ((uint32_t)0x10000000) /!< Clock Security System enable /
tushki7	0:60d829a0353a	2595
tushki7	0:60d829a0353a	2596	#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /!< RTC/LCD Prescaler /
tushki7	0:60d829a0353a	2597	#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /!< Bit0 /
tushki7	0:60d829a0353a	2598	#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /!< Bit1 /
tushki7	0:60d829a0353a	2599
tushki7	0:60d829a0353a	2600	/****************** Bit definition for RCC_ICSCR register ***************/
tushki7	0:60d829a0353a	2601	#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /!< Internal High Speed clock Calibration /
tushki7	0:60d829a0353a	2602	#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /!< Internal High Speed clock trimming /
tushki7	0:60d829a0353a	2603
tushki7	0:60d829a0353a	2604	#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /!< Internal Multi Speed clock Range /
tushki7	0:60d829a0353a	2605	#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /!< Internal Multi Speed clock Range 65.536 KHz /
tushki7	0:60d829a0353a	2606	#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /!< Internal Multi Speed clock Range 131.072 KHz /
tushki7	0:60d829a0353a	2607	#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /!< Internal Multi Speed clock Range 262.144 KHz /
tushki7	0:60d829a0353a	2608	#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /!< Internal Multi Speed clock Range 524.288 KHz /
tushki7	0:60d829a0353a	2609	#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /!< Internal Multi Speed clock Range 1.048 MHz /
tushki7	0:60d829a0353a	2610	#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /!< Internal Multi Speed clock Range 2.097 MHz /
tushki7	0:60d829a0353a	2611	#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /!< Internal Multi Speed clock Range 4.194 MHz /
tushki7	0:60d829a0353a	2612	#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /!< Internal Multi Speed clock Calibration /
tushki7	0:60d829a0353a	2613	#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /!< Internal Multi Speed clock trimming /
tushki7	0:60d829a0353a	2614
tushki7	0:60d829a0353a	2615	/****************** Bit definition for RCC_CFGR register ****************/
tushki7	0:60d829a0353a	2616	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
tushki7	0:60d829a0353a	2617	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2618	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2619
tushki7	0:60d829a0353a	2620	/!< SW configuration /
tushki7	0:60d829a0353a	2621	#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /!< MSI selected as system clock /
tushki7	0:60d829a0353a	2622	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /!< HSI selected as system clock /
tushki7	0:60d829a0353a	2623	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /!< HSE selected as system clock /
tushki7	0:60d829a0353a	2624	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /!< PLL selected as system clock /
tushki7	0:60d829a0353a	2625
tushki7	0:60d829a0353a	2626	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
tushki7	0:60d829a0353a	2627	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
tushki7	0:60d829a0353a	2628	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
tushki7	0:60d829a0353a	2629
tushki7	0:60d829a0353a	2630	/!< SWS configuration /
tushki7	0:60d829a0353a	2631	#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /!< MSI oscillator used as system clock /
tushki7	0:60d829a0353a	2632	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /!< HSI oscillator used as system clock /
tushki7	0:60d829a0353a	2633	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /!< HSE oscillator used as system clock /
tushki7	0:60d829a0353a	2634	#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /!< PLL used as system clock /
tushki7	0:60d829a0353a	2635
tushki7	0:60d829a0353a	2636	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
tushki7	0:60d829a0353a	2637	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	2638	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	2639	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
tushki7	0:60d829a0353a	2640	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
tushki7	0:60d829a0353a	2641
tushki7	0:60d829a0353a	2642	/!< HPRE configuration /
tushki7	0:60d829a0353a	2643	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
tushki7	0:60d829a0353a	2644	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
tushki7	0:60d829a0353a	2645	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
tushki7	0:60d829a0353a	2646	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
tushki7	0:60d829a0353a	2647	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
tushki7	0:60d829a0353a	2648	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
tushki7	0:60d829a0353a	2649	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
tushki7	0:60d829a0353a	2650	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
tushki7	0:60d829a0353a	2651	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
tushki7	0:60d829a0353a	2652
tushki7	0:60d829a0353a	2653	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
tushki7	0:60d829a0353a	2654	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	2655	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	2656	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
tushki7	0:60d829a0353a	2657
tushki7	0:60d829a0353a	2658	/!< PPRE1 configuration /
tushki7	0:60d829a0353a	2659	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
tushki7	0:60d829a0353a	2660	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
tushki7	0:60d829a0353a	2661	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
tushki7	0:60d829a0353a	2662	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
tushki7	0:60d829a0353a	2663	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
tushki7	0:60d829a0353a	2664
tushki7	0:60d829a0353a	2665	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
tushki7	0:60d829a0353a	2666	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
tushki7	0:60d829a0353a	2667	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
tushki7	0:60d829a0353a	2668	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
tushki7	0:60d829a0353a	2669
tushki7	0:60d829a0353a	2670	/!< PPRE2 configuration /
tushki7	0:60d829a0353a	2671	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
tushki7	0:60d829a0353a	2672	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
tushki7	0:60d829a0353a	2673	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
tushki7	0:60d829a0353a	2674	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
tushki7	0:60d829a0353a	2675	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
tushki7	0:60d829a0353a	2676
tushki7	0:60d829a0353a	2677	/!< PLL entry clock source/
tushki7	0:60d829a0353a	2678	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
tushki7	0:60d829a0353a	2679
tushki7	0:60d829a0353a	2680	#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /!< HSI as PLL entry clock source /
tushki7	0:60d829a0353a	2681	#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /!< HSE as PLL entry clock source /
tushki7	0:60d829a0353a	2682
tushki7	0:60d829a0353a	2683
tushki7	0:60d829a0353a	2684	/!< PLLMUL configuration /
tushki7	0:60d829a0353a	2685	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
tushki7	0:60d829a0353a	2686	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	2687	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	2688	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
tushki7	0:60d829a0353a	2689	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
tushki7	0:60d829a0353a	2690
tushki7	0:60d829a0353a	2691	/!< PLLMUL configuration /
tushki7	0:60d829a0353a	2692	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /!< PLL input clock 3 */
tushki7	0:60d829a0353a	2693	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /!< PLL input clock 4 */
tushki7	0:60d829a0353a	2694	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /!< PLL input clock 6 */
tushki7	0:60d829a0353a	2695	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /!< PLL input clock 8 */
tushki7	0:60d829a0353a	2696	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /!< PLL input clock 12 */
tushki7	0:60d829a0353a	2697	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /!< PLL input clock 16 */
tushki7	0:60d829a0353a	2698	#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /!< PLL input clock 24 */
tushki7	0:60d829a0353a	2699	#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /!< PLL input clock 32 */
tushki7	0:60d829a0353a	2700	#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /!< PLL input clock 48 */
tushki7	0:60d829a0353a	2701
tushki7	0:60d829a0353a	2702	/!< PLLDIV configuration /
tushki7	0:60d829a0353a	2703	#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /!< PLLDIV[1:0] bits (PLL Output Division) /
tushki7	0:60d829a0353a	2704	#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /!< Bit0 /
tushki7	0:60d829a0353a	2705	#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /!< Bit1 /
tushki7	0:60d829a0353a	2706
tushki7	0:60d829a0353a	2707
tushki7	0:60d829a0353a	2708	/!< PLLDIV configuration /
tushki7	0:60d829a0353a	2709	#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /!< PLL clock output = CKVCO / 1 /
tushki7	0:60d829a0353a	2710	#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /!< PLL clock output = CKVCO / 2 /
tushki7	0:60d829a0353a	2711	#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /!< PLL clock output = CKVCO / 3 /
tushki7	0:60d829a0353a	2712	#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /!< PLL clock output = CKVCO / 4 /
tushki7	0:60d829a0353a	2713
tushki7	0:60d829a0353a	2714
tushki7	0:60d829a0353a	2715	#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
tushki7	0:60d829a0353a	2716	#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	2717	#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	2718	#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /!< Bit 2 /
tushki7	0:60d829a0353a	2719
tushki7	0:60d829a0353a	2720	/!< MCO configuration /
tushki7	0:60d829a0353a	2721	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
tushki7	0:60d829a0353a	2722	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /!< System clock selected /
tushki7	0:60d829a0353a	2723	#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /!< Internal 16 MHz RC oscillator clock selected /
tushki7	0:60d829a0353a	2724	#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /!< Internal Medium Speed RC oscillator clock selected /
tushki7	0:60d829a0353a	2725	#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /!< External 1-25 MHz oscillator clock selected /
tushki7	0:60d829a0353a	2726	#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /!< PLL clock divided /
tushki7	0:60d829a0353a	2727	#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /!< LSI selected /
tushki7	0:60d829a0353a	2728	#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /!< LSE selected /
tushki7	0:60d829a0353a	2729
tushki7	0:60d829a0353a	2730	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) /
tushki7	0:60d829a0353a	2731	#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /!< Bit 0 /
tushki7	0:60d829a0353a	2732	#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /!< Bit 1 /
tushki7	0:60d829a0353a	2733	#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /!< Bit 2 /
tushki7	0:60d829a0353a	2734
tushki7	0:60d829a0353a	2735	/!< MCO Prescaler configuration /
tushki7	0:60d829a0353a	2736	#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /!< MCO Clock divided by 1 /
tushki7	0:60d829a0353a	2737	#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /!< MCO Clock divided by 2 /
tushki7	0:60d829a0353a	2738	#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /!< MCO Clock divided by 4 /
tushki7	0:60d829a0353a	2739	#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /!< MCO Clock divided by 8 /
tushki7	0:60d829a0353a	2740	#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /!< MCO Clock divided by 16 /
tushki7	0:60d829a0353a	2741
tushki7	0:60d829a0353a	2742	/!<*************** Bit definition for RCC_CIR register ******************/
tushki7	0:60d829a0353a	2743	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
tushki7	0:60d829a0353a	2744	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
tushki7	0:60d829a0353a	2745	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
tushki7	0:60d829a0353a	2746	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
tushki7	0:60d829a0353a	2747	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
tushki7	0:60d829a0353a	2748	#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /!< MSI Ready Interrupt flag /
tushki7	0:60d829a0353a	2749	#define RCC_CIR_LSECSS ((uint32_t)0x00000040) /!< LSE CSS Interrupt flag /
tushki7	0:60d829a0353a	2750	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
tushki7	0:60d829a0353a	2751
tushki7	0:60d829a0353a	2752	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
tushki7	0:60d829a0353a	2753	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
tushki7	0:60d829a0353a	2754	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
tushki7	0:60d829a0353a	2755	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
tushki7	0:60d829a0353a	2756	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
tushki7	0:60d829a0353a	2757	#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /!< MSI Ready Interrupt Enable /
tushki7	0:60d829a0353a	2758	#define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /!< LSE CSS Interrupt Enable /
tushki7	0:60d829a0353a	2759
tushki7	0:60d829a0353a	2760	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
tushki7	0:60d829a0353a	2761	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
tushki7	0:60d829a0353a	2762	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
tushki7	0:60d829a0353a	2763	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
tushki7	0:60d829a0353a	2764	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
tushki7	0:60d829a0353a	2765	#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /!< MSI Ready Interrupt Clear /
tushki7	0:60d829a0353a	2766	#define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /!< LSE CSS Interrupt Clear /
tushki7	0:60d829a0353a	2767	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
tushki7	0:60d829a0353a	2768
tushki7	0:60d829a0353a	2769	/*************** Bit definition for RCC_AHBRSTR register ****************/
tushki7	0:60d829a0353a	2770	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /!< GPIO port A reset /
tushki7	0:60d829a0353a	2771	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /!< GPIO port B reset /
tushki7	0:60d829a0353a	2772	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /!< GPIO port C reset /
tushki7	0:60d829a0353a	2773	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /!< GPIO port D reset /
tushki7	0:60d829a0353a	2774	#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /!< GPIO port E reset /
tushki7	0:60d829a0353a	2775	#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /!< GPIO port H reset /
tushki7	0:60d829a0353a	2776	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) /!< GPIO port F reset /
tushki7	0:60d829a0353a	2777	#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) /!< GPIO port G reset /
tushki7	0:60d829a0353a	2778	#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /!< CRC reset /
tushki7	0:60d829a0353a	2779	#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /!< FLITF reset /
tushki7	0:60d829a0353a	2780	#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /!< DMA1 reset /
tushki7	0:60d829a0353a	2781	#define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /!< DMA2 reset /
tushki7	0:60d829a0353a	2782
tushki7	0:60d829a0353a	2783	/*************** Bit definition for RCC_APB2RSTR register ***************/
tushki7	0:60d829a0353a	2784	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< System Configuration SYSCFG reset /
tushki7	0:60d829a0353a	2785	#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /!< TIM9 reset /
tushki7	0:60d829a0353a	2786	#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /!< TIM10 reset /
tushki7	0:60d829a0353a	2787	#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /!< TIM11 reset /
tushki7	0:60d829a0353a	2788	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC1 reset /
tushki7	0:60d829a0353a	2789	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 reset /
tushki7	0:60d829a0353a	2790	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
tushki7	0:60d829a0353a	2791
tushki7	0:60d829a0353a	2792	/*************** Bit definition for RCC_APB1RSTR register ***************/
tushki7	0:60d829a0353a	2793	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
tushki7	0:60d829a0353a	2794	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
tushki7	0:60d829a0353a	2795	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
tushki7	0:60d829a0353a	2796	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /!< Timer 5 reset /
tushki7	0:60d829a0353a	2797	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
tushki7	0:60d829a0353a	2798	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
tushki7	0:60d829a0353a	2799	#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /!< LCD reset /
tushki7	0:60d829a0353a	2800	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
tushki7	0:60d829a0353a	2801	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
tushki7	0:60d829a0353a	2802	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI 3 reset /
tushki7	0:60d829a0353a	2803	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
tushki7	0:60d829a0353a	2804	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
tushki7	0:60d829a0353a	2805	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
tushki7	0:60d829a0353a	2806	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
tushki7	0:60d829a0353a	2807	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
tushki7	0:60d829a0353a	2808	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
tushki7	0:60d829a0353a	2809	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB reset /
tushki7	0:60d829a0353a	2810	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
tushki7	0:60d829a0353a	2811	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
tushki7	0:60d829a0353a	2812	#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /!< Comparator interface reset /
tushki7	0:60d829a0353a	2813
tushki7	0:60d829a0353a	2814	/**************** Bit definition for RCC_AHBENR register ****************/
tushki7	0:60d829a0353a	2815	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /!< GPIO port A clock enable /
tushki7	0:60d829a0353a	2816	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /!< GPIO port B clock enable /
tushki7	0:60d829a0353a	2817	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /!< GPIO port C clock enable /
tushki7	0:60d829a0353a	2818	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /!< GPIO port D clock enable /
tushki7	0:60d829a0353a	2819	#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /!< GPIO port E clock enable /
tushki7	0:60d829a0353a	2820	#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /!< GPIO port H clock enable /
tushki7	0:60d829a0353a	2821	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) /!< GPIO port F clock enable /
tushki7	0:60d829a0353a	2822	#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) /!< GPIO port G clock enable /
tushki7	0:60d829a0353a	2823	#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /!< CRC clock enable /
tushki7	0:60d829a0353a	2824	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
tushki7	0:60d829a0353a	2825	the Flash memory is in power down mode) */
tushki7	0:60d829a0353a	2826	#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /!< DMA1 clock enable /
tushki7	0:60d829a0353a	2827	#define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /!< DMA2 clock enable /
tushki7	0:60d829a0353a	2828
tushki7	0:60d829a0353a	2829	/**************** Bit definition for RCC_APB2ENR register ***************/
tushki7	0:60d829a0353a	2830	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /!< System Configuration SYSCFG clock enable /
tushki7	0:60d829a0353a	2831	#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /!< TIM9 interface clock enable /
tushki7	0:60d829a0353a	2832	#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /!< TIM10 interface clock enable /
tushki7	0:60d829a0353a	2833	#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /!< TIM11 Timer clock enable /
tushki7	0:60d829a0353a	2834	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC1 clock enable /
tushki7	0:60d829a0353a	2835	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
tushki7	0:60d829a0353a	2836	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
tushki7	0:60d829a0353a	2837
tushki7	0:60d829a0353a	2838	/*************** Bit definition for RCC_APB1ENR register ****************/
tushki7	0:60d829a0353a	2839	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
tushki7	0:60d829a0353a	2840	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
tushki7	0:60d829a0353a	2841	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
tushki7	0:60d829a0353a	2842	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /!< Timer 5 clock enable /
tushki7	0:60d829a0353a	2843	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
tushki7	0:60d829a0353a	2844	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
tushki7	0:60d829a0353a	2845	#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /!< LCD clock enable /
tushki7	0:60d829a0353a	2846	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
tushki7	0:60d829a0353a	2847	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
tushki7	0:60d829a0353a	2848	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI 3 clock enable /
tushki7	0:60d829a0353a	2849	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
tushki7	0:60d829a0353a	2850	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
tushki7	0:60d829a0353a	2851	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
tushki7	0:60d829a0353a	2852	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
tushki7	0:60d829a0353a	2853	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
tushki7	0:60d829a0353a	2854	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
tushki7	0:60d829a0353a	2855	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
tushki7	0:60d829a0353a	2856	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
tushki7	0:60d829a0353a	2857	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
tushki7	0:60d829a0353a	2858	#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /!< Comparator interface clock enable /
tushki7	0:60d829a0353a	2859
tushki7	0:60d829a0353a	2860	/**************** Bit definition for RCC_AHBLPENR register **************/
tushki7	0:60d829a0353a	2861	#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /!< GPIO port A clock enabled in sleep mode /
tushki7	0:60d829a0353a	2862	#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /!< GPIO port B clock enabled in sleep mode /
tushki7	0:60d829a0353a	2863	#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /!< GPIO port C clock enabled in sleep mode /
tushki7	0:60d829a0353a	2864	#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /!< GPIO port D clock enabled in sleep mode /
tushki7	0:60d829a0353a	2865	#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /!< GPIO port E clock enabled in sleep mode /
tushki7	0:60d829a0353a	2866	#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /!< GPIO port H clock enabled in sleep mode /
tushki7	0:60d829a0353a	2867	#define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) /!< GPIO port F clock enabled in sleep mode /
tushki7	0:60d829a0353a	2868	#define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) /!< GPIO port G clock enabled in sleep mode /
tushki7	0:60d829a0353a	2869	#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /!< CRC clock enabled in sleep mode /
tushki7	0:60d829a0353a	2870	#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
tushki7	0:60d829a0353a	2871	(has effect only when the Flash memory is
tushki7	0:60d829a0353a	2872	in power down mode) */
tushki7	0:60d829a0353a	2873	#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /!< SRAM clock enabled in sleep mode /
tushki7	0:60d829a0353a	2874	#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /!< DMA1 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2875	#define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /!< DMA2 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2876
tushki7	0:60d829a0353a	2877	/**************** Bit definition for RCC_APB2LPENR register *************/
tushki7	0:60d829a0353a	2878	#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /!< System Configuration SYSCFG clock enabled in sleep mode /
tushki7	0:60d829a0353a	2879	#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /!< TIM9 interface clock enabled in sleep mode /
tushki7	0:60d829a0353a	2880	#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /!< TIM10 interface clock enabled in sleep mode /
tushki7	0:60d829a0353a	2881	#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /!< TIM11 Timer clock enabled in sleep mode /
tushki7	0:60d829a0353a	2882	#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /!< ADC1 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2883	#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /!< SPI1 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2884	#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /!< USART1 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2885
tushki7	0:60d829a0353a	2886	/*************** Bit definition for RCC_APB1LPENR register **************/
tushki7	0:60d829a0353a	2887	#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /!< Timer 2 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2888	#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /!< Timer 3 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2889	#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /!< Timer 4 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2890	#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /!< Timer 5 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2891	#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /!< Timer 6 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2892	#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /!< Timer 7 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2893	#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /!< LCD clock enabled in sleep mode /
tushki7	0:60d829a0353a	2894	#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /!< Window Watchdog clock enabled in sleep mode /
tushki7	0:60d829a0353a	2895	#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /!< SPI 2 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2896	#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /!< SPI 3 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2897	#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /!< USART 2 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2898	#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /!< USART 3 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2899	#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) /!< UART 4 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2900	#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) /!< UART 5 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2901	#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /!< I2C 1 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2902	#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /!< I2C 2 clock enabled in sleep mode /
tushki7	0:60d829a0353a	2903	#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /!< USB clock enabled in sleep mode /
tushki7	0:60d829a0353a	2904	#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /!< Power interface clock enabled in sleep mode /
tushki7	0:60d829a0353a	2905	#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /!< DAC interface clock enabled in sleep mode /
tushki7	0:60d829a0353a	2906	#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /!< Comparator interface clock enabled in sleep mode/
tushki7	0:60d829a0353a	2907
tushki7	0:60d829a0353a	2908	/***************** Bit definition for RCC_CSR register ******************/
tushki7	0:60d829a0353a	2909	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
tushki7	0:60d829a0353a	2910	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
tushki7	0:60d829a0353a	2911
tushki7	0:60d829a0353a	2912	#define RCC_CSR_LSEON ((uint32_t)0x00000100) /!< External Low Speed oscillator enable /
tushki7	0:60d829a0353a	2913	#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /!< External Low Speed oscillator Ready /
tushki7	0:60d829a0353a	2914	#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /!< External Low Speed oscillator Bypass /
tushki7	0:60d829a0353a	2915
tushki7	0:60d829a0353a	2916	#define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /!< External Low Speed oscillator CSS Enable /
tushki7	0:60d829a0353a	2917	#define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /!< External Low Speed oscillator CSS Detected /
tushki7	0:60d829a0353a	2918
tushki7	0:60d829a0353a	2919	#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /!< RTCSEL[1:0] bits (RTC clock source selection) /
tushki7	0:60d829a0353a	2920	#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	2921	#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	2922
tushki7	0:60d829a0353a	2923	/!< RTC congiguration /
tushki7	0:60d829a0353a	2924	#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
tushki7	0:60d829a0353a	2925	#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /!< LSE oscillator clock used as RTC clock /
tushki7	0:60d829a0353a	2926	#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /!< LSI oscillator clock used as RTC clock /
tushki7	0:60d829a0353a	2927	#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock /
tushki7	0:60d829a0353a	2928
tushki7	0:60d829a0353a	2929	#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /!< RTC clock enable /
tushki7	0:60d829a0353a	2930	#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /!< RTC reset /
tushki7	0:60d829a0353a	2931
tushki7	0:60d829a0353a	2932	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
tushki7	0:60d829a0353a	2933	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< Option Bytes Loader reset flag /
tushki7	0:60d829a0353a	2934	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
tushki7	0:60d829a0353a	2935	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
tushki7	0:60d829a0353a	2936	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
tushki7	0:60d829a0353a	2937	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
tushki7	0:60d829a0353a	2938	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
tushki7	0:60d829a0353a	2939	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
tushki7	0:60d829a0353a	2940
tushki7	0:60d829a0353a	2941	/******************************************************************************/
tushki7	0:60d829a0353a	2942	/* */
tushki7	0:60d829a0353a	2943	/* Real-Time Clock (RTC) */
tushki7	0:60d829a0353a	2944	/* */
tushki7	0:60d829a0353a	2945	/******************************************************************************/
tushki7	0:60d829a0353a	2946	/****************** Bits definition for RTC_TR register *****************/
tushki7	0:60d829a0353a	2947	#define RTC_TR_PM ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	2948	#define RTC_TR_HT ((uint32_t)0x00300000)
tushki7	0:60d829a0353a	2949	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	2950	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	2951	#define RTC_TR_HU ((uint32_t)0x000F0000)
tushki7	0:60d829a0353a	2952	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	2953	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	2954	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	2955	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	2956	#define RTC_TR_MNT ((uint32_t)0x00007000)
tushki7	0:60d829a0353a	2957	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2958	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2959	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2960	#define RTC_TR_MNU ((uint32_t)0x00000F00)
tushki7	0:60d829a0353a	2961	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2962	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2963	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2964	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2965	#define RTC_TR_ST ((uint32_t)0x00000070)
tushki7	0:60d829a0353a	2966	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2967	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2968	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	2969	#define RTC_TR_SU ((uint32_t)0x0000000F)
tushki7	0:60d829a0353a	2970	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	2971	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	2972	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	2973	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	2974
tushki7	0:60d829a0353a	2975	/****************** Bits definition for RTC_DR register *****************/
tushki7	0:60d829a0353a	2976	#define RTC_DR_YT ((uint32_t)0x00F00000)
tushki7	0:60d829a0353a	2977	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	2978	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	2979	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	2980	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	2981	#define RTC_DR_YU ((uint32_t)0x000F0000)
tushki7	0:60d829a0353a	2982	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	2983	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	2984	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	2985	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	2986	#define RTC_DR_WDU ((uint32_t)0x0000E000)
tushki7	0:60d829a0353a	2987	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	2988	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	2989	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	2990	#define RTC_DR_MT ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	2991	#define RTC_DR_MU ((uint32_t)0x00000F00)
tushki7	0:60d829a0353a	2992	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	2993	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	2994	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	2995	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	2996	#define RTC_DR_DT ((uint32_t)0x00000030)
tushki7	0:60d829a0353a	2997	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	2998	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	2999	#define RTC_DR_DU ((uint32_t)0x0000000F)
tushki7	0:60d829a0353a	3000	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3001	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3002	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3003	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3004
tushki7	0:60d829a0353a	3005	/****************** Bits definition for RTC_CR register *****************/
tushki7	0:60d829a0353a	3006	#define RTC_CR_COE ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	3007	#define RTC_CR_OSEL ((uint32_t)0x00600000)
tushki7	0:60d829a0353a	3008	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	3009	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	3010	#define RTC_CR_POL ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	3011	#define RTC_CR_COSEL ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	3012	#define RTC_CR_BCK ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	3013	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	3014	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	3015	#define RTC_CR_TSIE ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	3016	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	3017	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	3018	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	3019	#define RTC_CR_TSE ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	3020	#define RTC_CR_WUTE ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	3021	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	3022	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	3023	#define RTC_CR_DCE ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	3024	#define RTC_CR_FMT ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	3025	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	3026	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	3027	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3028	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
tushki7	0:60d829a0353a	3029	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3030	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3031	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3032
tushki7	0:60d829a0353a	3033	/****************** Bits definition for RTC_ISR register ****************/
tushki7	0:60d829a0353a	3034	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	3035	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	3036	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	3037	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	3038	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	3039	#define RTC_ISR_TSF ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	3040	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	3041	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	3042	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	3043	#define RTC_ISR_INIT ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	3044	#define RTC_ISR_INITF ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	3045	#define RTC_ISR_RSF ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	3046	#define RTC_ISR_INITS ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	3047	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3048	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3049	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3050	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3051
tushki7	0:60d829a0353a	3052	/****************** Bits definition for RTC_PRER register ***************/
tushki7	0:60d829a0353a	3053	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
tushki7	0:60d829a0353a	3054	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
tushki7	0:60d829a0353a	3055
tushki7	0:60d829a0353a	3056	/****************** Bits definition for RTC_WUTR register ***************/
tushki7	0:60d829a0353a	3057	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
tushki7	0:60d829a0353a	3058
tushki7	0:60d829a0353a	3059	/****************** Bits definition for RTC_CALIBR register *************/
tushki7	0:60d829a0353a	3060	#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	3061	#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
tushki7	0:60d829a0353a	3062
tushki7	0:60d829a0353a	3063	/****************** Bits definition for RTC_ALRMAR register *************/
tushki7	0:60d829a0353a	3064	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
tushki7	0:60d829a0353a	3065	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
tushki7	0:60d829a0353a	3066	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
tushki7	0:60d829a0353a	3067	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
tushki7	0:60d829a0353a	3068	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
tushki7	0:60d829a0353a	3069	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
tushki7	0:60d829a0353a	3070	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	3071	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	3072	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	3073	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
tushki7	0:60d829a0353a	3074	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	3075	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	3076	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
tushki7	0:60d829a0353a	3077	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	3078	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	3079	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
tushki7	0:60d829a0353a	3080	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	3081	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	3082	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	3083	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	3084	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	3085	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
tushki7	0:60d829a0353a	3086	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	3087	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	3088	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	3089	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
tushki7	0:60d829a0353a	3090	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	3091	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	3092	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	3093	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	3094	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	3095	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
tushki7	0:60d829a0353a	3096	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	3097	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	3098	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	3099	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
tushki7	0:60d829a0353a	3100	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3101	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3102	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3103	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3104
tushki7	0:60d829a0353a	3105	/****************** Bits definition for RTC_ALRMBR register *************/
tushki7	0:60d829a0353a	3106	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
tushki7	0:60d829a0353a	3107	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
tushki7	0:60d829a0353a	3108	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
tushki7	0:60d829a0353a	3109	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
tushki7	0:60d829a0353a	3110	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
tushki7	0:60d829a0353a	3111	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
tushki7	0:60d829a0353a	3112	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	3113	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	3114	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	3115	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
tushki7	0:60d829a0353a	3116	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	3117	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	3118	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
tushki7	0:60d829a0353a	3119	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	3120	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	3121	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
tushki7	0:60d829a0353a	3122	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	3123	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	3124	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	3125	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	3126	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	3127	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
tushki7	0:60d829a0353a	3128	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	3129	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	3130	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	3131	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
tushki7	0:60d829a0353a	3132	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	3133	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	3134	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	3135	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	3136	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	3137	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
tushki7	0:60d829a0353a	3138	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	3139	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	3140	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	3141	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
tushki7	0:60d829a0353a	3142	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3143	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3144	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3145	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3146
tushki7	0:60d829a0353a	3147	/****************** Bits definition for RTC_WPR register ****************/
tushki7	0:60d829a0353a	3148	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
tushki7	0:60d829a0353a	3149
tushki7	0:60d829a0353a	3150	/****************** Bits definition for RTC_SSR register ****************/
tushki7	0:60d829a0353a	3151	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
tushki7	0:60d829a0353a	3152
tushki7	0:60d829a0353a	3153	/****************** Bits definition for RTC_SHIFTR register *************/
tushki7	0:60d829a0353a	3154	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
tushki7	0:60d829a0353a	3155	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
tushki7	0:60d829a0353a	3156
tushki7	0:60d829a0353a	3157	/****************** Bits definition for RTC_TSTR register ***************/
tushki7	0:60d829a0353a	3158	#define RTC_TSTR_PM ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	3159	#define RTC_TSTR_HT ((uint32_t)0x00300000)
tushki7	0:60d829a0353a	3160	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	3161	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	3162	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
tushki7	0:60d829a0353a	3163	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	3164	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	3165	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	3166	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	3167	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
tushki7	0:60d829a0353a	3168	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	3169	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	3170	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	3171	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
tushki7	0:60d829a0353a	3172	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	3173	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	3174	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	3175	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	3176	#define RTC_TSTR_ST ((uint32_t)0x00000070)
tushki7	0:60d829a0353a	3177	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	3178	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	3179	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	3180	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
tushki7	0:60d829a0353a	3181	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3182	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3183	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3184	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3185
tushki7	0:60d829a0353a	3186	/****************** Bits definition for RTC_TSDR register ***************/
tushki7	0:60d829a0353a	3187	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
tushki7	0:60d829a0353a	3188	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	3189	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	3190	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	3191	#define RTC_TSDR_MT ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	3192	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
tushki7	0:60d829a0353a	3193	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	3194	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	3195	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	3196	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	3197	#define RTC_TSDR_DT ((uint32_t)0x00000030)
tushki7	0:60d829a0353a	3198	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	3199	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	3200	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
tushki7	0:60d829a0353a	3201	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3202	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3203	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3204	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3205
tushki7	0:60d829a0353a	3206	/****************** Bits definition for RTC_TSSSR register **************/
tushki7	0:60d829a0353a	3207	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
tushki7	0:60d829a0353a	3208
tushki7	0:60d829a0353a	3209	/****************** Bits definition for RTC_CAL register ***************/
tushki7	0:60d829a0353a	3210	#define RTC_CALR_CALP ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	3211	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	3212	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	3213	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
tushki7	0:60d829a0353a	3214	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3215	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3216	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3217	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3218	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	3219	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	3220	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	3221	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	3222	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	3223
tushki7	0:60d829a0353a	3224	/****************** Bits definition for RTC_TAFCR register **************/
tushki7	0:60d829a0353a	3225	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	3226	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	3227	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
tushki7	0:60d829a0353a	3228	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	3229	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	3230	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
tushki7	0:60d829a0353a	3231	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	3232	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	3233	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
tushki7	0:60d829a0353a	3234	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	3235	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	3236	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	3237	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	3238	#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	3239	#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	3240	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	3241	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	3242	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	3243	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	3244	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	3245
tushki7	0:60d829a0353a	3246	/****************** Bits definition for RTC_ALRMASSR register ***********/
tushki7	0:60d829a0353a	3247	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
tushki7	0:60d829a0353a	3248	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	3249	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	3250	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	3251	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
tushki7	0:60d829a0353a	3252	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
tushki7	0:60d829a0353a	3253
tushki7	0:60d829a0353a	3254	/****************** Bits definition for RTC_ALRMBSSR register ***********/
tushki7	0:60d829a0353a	3255	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
tushki7	0:60d829a0353a	3256	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	3257	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	3258	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	3259	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
tushki7	0:60d829a0353a	3260	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
tushki7	0:60d829a0353a	3261
tushki7	0:60d829a0353a	3262	/****************** Bits definition for RTC_BKP0R register **************/
tushki7	0:60d829a0353a	3263	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3264
tushki7	0:60d829a0353a	3265	/****************** Bits definition for RTC_BKP1R register **************/
tushki7	0:60d829a0353a	3266	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3267
tushki7	0:60d829a0353a	3268	/****************** Bits definition for RTC_BKP2R register **************/
tushki7	0:60d829a0353a	3269	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3270
tushki7	0:60d829a0353a	3271	/****************** Bits definition for RTC_BKP3R register **************/
tushki7	0:60d829a0353a	3272	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3273
tushki7	0:60d829a0353a	3274	/****************** Bits definition for RTC_BKP4R register **************/
tushki7	0:60d829a0353a	3275	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3276
tushki7	0:60d829a0353a	3277	/****************** Bits definition for RTC_BKP5R register **************/
tushki7	0:60d829a0353a	3278	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3279
tushki7	0:60d829a0353a	3280	/****************** Bits definition for RTC_BKP6R register **************/
tushki7	0:60d829a0353a	3281	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3282
tushki7	0:60d829a0353a	3283	/****************** Bits definition for RTC_BKP7R register **************/
tushki7	0:60d829a0353a	3284	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3285
tushki7	0:60d829a0353a	3286	/****************** Bits definition for RTC_BKP8R register **************/
tushki7	0:60d829a0353a	3287	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3288
tushki7	0:60d829a0353a	3289	/****************** Bits definition for RTC_BKP9R register **************/
tushki7	0:60d829a0353a	3290	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3291
tushki7	0:60d829a0353a	3292	/****************** Bits definition for RTC_BKP10R register *************/
tushki7	0:60d829a0353a	3293	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3294
tushki7	0:60d829a0353a	3295	/****************** Bits definition for RTC_BKP11R register *************/
tushki7	0:60d829a0353a	3296	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3297
tushki7	0:60d829a0353a	3298	/****************** Bits definition for RTC_BKP12R register *************/
tushki7	0:60d829a0353a	3299	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3300
tushki7	0:60d829a0353a	3301	/****************** Bits definition for RTC_BKP13R register *************/
tushki7	0:60d829a0353a	3302	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3303
tushki7	0:60d829a0353a	3304	/****************** Bits definition for RTC_BKP14R register *************/
tushki7	0:60d829a0353a	3305	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3306
tushki7	0:60d829a0353a	3307	/****************** Bits definition for RTC_BKP15R register *************/
tushki7	0:60d829a0353a	3308	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3309
tushki7	0:60d829a0353a	3310	/****************** Bits definition for RTC_BKP16R register *************/
tushki7	0:60d829a0353a	3311	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3312
tushki7	0:60d829a0353a	3313	/****************** Bits definition for RTC_BKP17R register *************/
tushki7	0:60d829a0353a	3314	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3315
tushki7	0:60d829a0353a	3316	/****************** Bits definition for RTC_BKP18R register *************/
tushki7	0:60d829a0353a	3317	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3318
tushki7	0:60d829a0353a	3319	/****************** Bits definition for RTC_BKP19R register *************/
tushki7	0:60d829a0353a	3320	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3321
tushki7	0:60d829a0353a	3322	/****************** Bits definition for RTC_BKP20R register *************/
tushki7	0:60d829a0353a	3323	#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3324
tushki7	0:60d829a0353a	3325	/****************** Bits definition for RTC_BKP21R register *************/
tushki7	0:60d829a0353a	3326	#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3327
tushki7	0:60d829a0353a	3328	/****************** Bits definition for RTC_BKP22R register *************/
tushki7	0:60d829a0353a	3329	#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3330
tushki7	0:60d829a0353a	3331	/****************** Bits definition for RTC_BKP23R register *************/
tushki7	0:60d829a0353a	3332	#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3333
tushki7	0:60d829a0353a	3334	/****************** Bits definition for RTC_BKP24R register *************/
tushki7	0:60d829a0353a	3335	#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3336
tushki7	0:60d829a0353a	3337	/****************** Bits definition for RTC_BKP25R register *************/
tushki7	0:60d829a0353a	3338	#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3339
tushki7	0:60d829a0353a	3340	/****************** Bits definition for RTC_BKP26R register *************/
tushki7	0:60d829a0353a	3341	#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3342
tushki7	0:60d829a0353a	3343	/****************** Bits definition for RTC_BKP27R register *************/
tushki7	0:60d829a0353a	3344	#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3345
tushki7	0:60d829a0353a	3346	/****************** Bits definition for RTC_BKP28R register *************/
tushki7	0:60d829a0353a	3347	#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3348
tushki7	0:60d829a0353a	3349	/****************** Bits definition for RTC_BKP29R register *************/
tushki7	0:60d829a0353a	3350	#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3351
tushki7	0:60d829a0353a	3352	/****************** Bits definition for RTC_BKP30R register *************/
tushki7	0:60d829a0353a	3353	#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3354
tushki7	0:60d829a0353a	3355	/****************** Bits definition for RTC_BKP31R register *************/
tushki7	0:60d829a0353a	3356	#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
tushki7	0:60d829a0353a	3357
tushki7	0:60d829a0353a	3358	/****************** Number of backup registers ****************************/
tushki7	0:60d829a0353a	3359	#define RTC_BKP_NUMBER 32
tushki7	0:60d829a0353a	3360
tushki7	0:60d829a0353a	3361	/******************************************************************************/
tushki7	0:60d829a0353a	3362	/* */
tushki7	0:60d829a0353a	3363	/* Serial Peripheral Interface (SPI) */
tushki7	0:60d829a0353a	3364	/* */
tushki7	0:60d829a0353a	3365	/******************************************************************************/
tushki7	0:60d829a0353a	3366
tushki7	0:60d829a0353a	3367	/***************** Bit definition for SPI_CR1 register ******************/
tushki7	0:60d829a0353a	3368	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
tushki7	0:60d829a0353a	3369	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
tushki7	0:60d829a0353a	3370	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
tushki7	0:60d829a0353a	3371
tushki7	0:60d829a0353a	3372	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
tushki7	0:60d829a0353a	3373	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
tushki7	0:60d829a0353a	3374	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
tushki7	0:60d829a0353a	3375	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
tushki7	0:60d829a0353a	3376
tushki7	0:60d829a0353a	3377	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
tushki7	0:60d829a0353a	3378	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
tushki7	0:60d829a0353a	3379	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
tushki7	0:60d829a0353a	3380	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
tushki7	0:60d829a0353a	3381	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
tushki7	0:60d829a0353a	3382	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
tushki7	0:60d829a0353a	3383	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
tushki7	0:60d829a0353a	3384	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
tushki7	0:60d829a0353a	3385	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
tushki7	0:60d829a0353a	3386	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
tushki7	0:60d829a0353a	3387
tushki7	0:60d829a0353a	3388	/***************** Bit definition for SPI_CR2 register ******************/
tushki7	0:60d829a0353a	3389	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
tushki7	0:60d829a0353a	3390	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
tushki7	0:60d829a0353a	3391	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
tushki7	0:60d829a0353a	3392	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame format /
tushki7	0:60d829a0353a	3393	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
tushki7	0:60d829a0353a	3394	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
tushki7	0:60d829a0353a	3395	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
tushki7	0:60d829a0353a	3396
tushki7	0:60d829a0353a	3397	/****************** Bit definition for SPI_SR register ******************/
tushki7	0:60d829a0353a	3398	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
tushki7	0:60d829a0353a	3399	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
tushki7	0:60d829a0353a	3400	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
tushki7	0:60d829a0353a	3401	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
tushki7	0:60d829a0353a	3402	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
tushki7	0:60d829a0353a	3403	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
tushki7	0:60d829a0353a	3404	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
tushki7	0:60d829a0353a	3405	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
tushki7	0:60d829a0353a	3406	#define SPI_SR_FRE ((uint32_t)0x00000100) /!<Frame format error flag /
tushki7	0:60d829a0353a	3407
tushki7	0:60d829a0353a	3408	/****************** Bit definition for SPI_DR register ******************/
tushki7	0:60d829a0353a	3409	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
tushki7	0:60d829a0353a	3410
tushki7	0:60d829a0353a	3411	/***************** Bit definition for SPI_CRCPR register ****************/
tushki7	0:60d829a0353a	3412	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
tushki7	0:60d829a0353a	3413
tushki7	0:60d829a0353a	3414	/**************** Bit definition for SPI_RXCRCR register ****************/
tushki7	0:60d829a0353a	3415	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
tushki7	0:60d829a0353a	3416
tushki7	0:60d829a0353a	3417	/**************** Bit definition for SPI_TXCRCR register ****************/
tushki7	0:60d829a0353a	3418	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
tushki7	0:60d829a0353a	3419
tushki7	0:60d829a0353a	3420	/**************** Bit definition for SPI_I2SCFGR register ***************/
tushki7	0:60d829a0353a	3421	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
tushki7	0:60d829a0353a	3422
tushki7	0:60d829a0353a	3423	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
tushki7	0:60d829a0353a	3424	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
tushki7	0:60d829a0353a	3425	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
tushki7	0:60d829a0353a	3426
tushki7	0:60d829a0353a	3427	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
tushki7	0:60d829a0353a	3428
tushki7	0:60d829a0353a	3429	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
tushki7	0:60d829a0353a	3430	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	3431	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	3432
tushki7	0:60d829a0353a	3433	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
tushki7	0:60d829a0353a	3434
tushki7	0:60d829a0353a	3435	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
tushki7	0:60d829a0353a	3436	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	3437	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	3438
tushki7	0:60d829a0353a	3439	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
tushki7	0:60d829a0353a	3440	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
tushki7	0:60d829a0353a	3441
tushki7	0:60d829a0353a	3442	/**************** Bit definition for SPI_I2SPR register *****************/
tushki7	0:60d829a0353a	3443	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
tushki7	0:60d829a0353a	3444	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
tushki7	0:60d829a0353a	3445	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
tushki7	0:60d829a0353a	3446
tushki7	0:60d829a0353a	3447	/******************************************************************************/
tushki7	0:60d829a0353a	3448	/* */
tushki7	0:60d829a0353a	3449	/* System Configuration (SYSCFG) */
tushki7	0:60d829a0353a	3450	/* */
tushki7	0:60d829a0353a	3451	/******************************************************************************/
tushki7	0:60d829a0353a	3452	/*************** Bit definition for SYSCFG_MEMRMP register **************/
tushki7	0:60d829a0353a	3453	#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
tushki7	0:60d829a0353a	3454	#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3455	#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3456	#define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /!< Boot mode Config /
tushki7	0:60d829a0353a	3457	#define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	3458	#define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	3459
tushki7	0:60d829a0353a	3460	/*************** Bit definition for SYSCFG_PMC register *****************/
tushki7	0:60d829a0353a	3461	#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /!< SYSCFG PMC /
tushki7	0:60d829a0353a	3462
tushki7	0:60d829a0353a	3463	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
tushki7	0:60d829a0353a	3464	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
tushki7	0:60d829a0353a	3465	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
tushki7	0:60d829a0353a	3466	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
tushki7	0:60d829a0353a	3467	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
tushki7	0:60d829a0353a	3468
tushki7	0:60d829a0353a	3469	/**
tushki7	0:60d829a0353a	3470	* @brief EXTI0 configuration
tushki7	0:60d829a0353a	3471	*/
tushki7	0:60d829a0353a	3472	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
tushki7	0:60d829a0353a	3473	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
tushki7	0:60d829a0353a	3474	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
tushki7	0:60d829a0353a	3475	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
tushki7	0:60d829a0353a	3476	#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
tushki7	0:60d829a0353a	3477	#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /!< PH[0] pin /
tushki7	0:60d829a0353a	3478	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000006) /!< PF[0] pin /
tushki7	0:60d829a0353a	3479	#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000007) /!< PG[0] pin /
tushki7	0:60d829a0353a	3480
tushki7	0:60d829a0353a	3481	/**
tushki7	0:60d829a0353a	3482	* @brief EXTI1 configuration
tushki7	0:60d829a0353a	3483	*/
tushki7	0:60d829a0353a	3484	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
tushki7	0:60d829a0353a	3485	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
tushki7	0:60d829a0353a	3486	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
tushki7	0:60d829a0353a	3487	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
tushki7	0:60d829a0353a	3488	#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
tushki7	0:60d829a0353a	3489	#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /!< PH[1] pin /
tushki7	0:60d829a0353a	3490	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000060) /!< PF[1] pin /
tushki7	0:60d829a0353a	3491	#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000070) /!< PG[1] pin /
tushki7	0:60d829a0353a	3492
tushki7	0:60d829a0353a	3493	/**
tushki7	0:60d829a0353a	3494	* @brief EXTI2 configuration
tushki7	0:60d829a0353a	3495	*/
tushki7	0:60d829a0353a	3496	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
tushki7	0:60d829a0353a	3497	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
tushki7	0:60d829a0353a	3498	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
tushki7	0:60d829a0353a	3499	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
tushki7	0:60d829a0353a	3500	#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
tushki7	0:60d829a0353a	3501	#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000500) /!< PH[2] pin /
tushki7	0:60d829a0353a	3502	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000600) /!< PF[2] pin /
tushki7	0:60d829a0353a	3503	#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000700) /!< PG[2] pin /
tushki7	0:60d829a0353a	3504
tushki7	0:60d829a0353a	3505	/**
tushki7	0:60d829a0353a	3506	* @brief EXTI3 configuration
tushki7	0:60d829a0353a	3507	*/
tushki7	0:60d829a0353a	3508	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
tushki7	0:60d829a0353a	3509	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
tushki7	0:60d829a0353a	3510	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
tushki7	0:60d829a0353a	3511	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
tushki7	0:60d829a0353a	3512	#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
tushki7	0:60d829a0353a	3513	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00003000) /!< PF[3] pin /
tushki7	0:60d829a0353a	3514	#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00004000) /!< PG[3] pin /
tushki7	0:60d829a0353a	3515
tushki7	0:60d829a0353a	3516	/*************** Bit definition for SYSCFG_EXTICR2 register ***************/
tushki7	0:60d829a0353a	3517	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
tushki7	0:60d829a0353a	3518	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
tushki7	0:60d829a0353a	3519	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
tushki7	0:60d829a0353a	3520	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
tushki7	0:60d829a0353a	3521
tushki7	0:60d829a0353a	3522	/**
tushki7	0:60d829a0353a	3523	* @brief EXTI4 configuration
tushki7	0:60d829a0353a	3524	*/
tushki7	0:60d829a0353a	3525	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
tushki7	0:60d829a0353a	3526	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
tushki7	0:60d829a0353a	3527	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
tushki7	0:60d829a0353a	3528	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
tushki7	0:60d829a0353a	3529	#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
tushki7	0:60d829a0353a	3530	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000006) /!< PF[4] pin /
tushki7	0:60d829a0353a	3531	#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000007) /!< PG[4] pin /
tushki7	0:60d829a0353a	3532
tushki7	0:60d829a0353a	3533	/**
tushki7	0:60d829a0353a	3534	* @brief EXTI5 configuration
tushki7	0:60d829a0353a	3535	*/
tushki7	0:60d829a0353a	3536	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
tushki7	0:60d829a0353a	3537	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
tushki7	0:60d829a0353a	3538	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
tushki7	0:60d829a0353a	3539	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
tushki7	0:60d829a0353a	3540	#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
tushki7	0:60d829a0353a	3541	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000060) /!< PF[5] pin /
tushki7	0:60d829a0353a	3542	#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000070) /!< PG[5] pin /
tushki7	0:60d829a0353a	3543
tushki7	0:60d829a0353a	3544	/**
tushki7	0:60d829a0353a	3545	* @brief EXTI6 configuration
tushki7	0:60d829a0353a	3546	*/
tushki7	0:60d829a0353a	3547	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
tushki7	0:60d829a0353a	3548	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
tushki7	0:60d829a0353a	3549	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
tushki7	0:60d829a0353a	3550	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
tushki7	0:60d829a0353a	3551	#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
tushki7	0:60d829a0353a	3552	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000600) /!< PF[6] pin /
tushki7	0:60d829a0353a	3553	#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000700) /!< PG[6] pin /
tushki7	0:60d829a0353a	3554
tushki7	0:60d829a0353a	3555	/**
tushki7	0:60d829a0353a	3556	* @brief EXTI7 configuration
tushki7	0:60d829a0353a	3557	*/
tushki7	0:60d829a0353a	3558	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
tushki7	0:60d829a0353a	3559	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
tushki7	0:60d829a0353a	3560	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
tushki7	0:60d829a0353a	3561	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
tushki7	0:60d829a0353a	3562	#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
tushki7	0:60d829a0353a	3563	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00006000) /!< PF[7] pin /
tushki7	0:60d829a0353a	3564	#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00007000) /!< PG[7] pin /
tushki7	0:60d829a0353a	3565
tushki7	0:60d829a0353a	3566	/*************** Bit definition for SYSCFG_EXTICR3 register ***************/
tushki7	0:60d829a0353a	3567	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
tushki7	0:60d829a0353a	3568	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
tushki7	0:60d829a0353a	3569	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
tushki7	0:60d829a0353a	3570	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
tushki7	0:60d829a0353a	3571
tushki7	0:60d829a0353a	3572	/**
tushki7	0:60d829a0353a	3573	* @brief EXTI8 configuration
tushki7	0:60d829a0353a	3574	*/
tushki7	0:60d829a0353a	3575	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
tushki7	0:60d829a0353a	3576	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
tushki7	0:60d829a0353a	3577	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
tushki7	0:60d829a0353a	3578	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
tushki7	0:60d829a0353a	3579	#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
tushki7	0:60d829a0353a	3580	#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000006) /!< PF[8] pin /
tushki7	0:60d829a0353a	3581	#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000007) /!< PG[8] pin /
tushki7	0:60d829a0353a	3582
tushki7	0:60d829a0353a	3583	/**
tushki7	0:60d829a0353a	3584	* @brief EXTI9 configuration
tushki7	0:60d829a0353a	3585	*/
tushki7	0:60d829a0353a	3586	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
tushki7	0:60d829a0353a	3587	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
tushki7	0:60d829a0353a	3588	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
tushki7	0:60d829a0353a	3589	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
tushki7	0:60d829a0353a	3590	#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
tushki7	0:60d829a0353a	3591	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000060) /!< PF[9] pin /
tushki7	0:60d829a0353a	3592	#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000070) /!< PG[9] pin /
tushki7	0:60d829a0353a	3593
tushki7	0:60d829a0353a	3594	/**
tushki7	0:60d829a0353a	3595	* @brief EXTI10 configuration
tushki7	0:60d829a0353a	3596	*/
tushki7	0:60d829a0353a	3597	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
tushki7	0:60d829a0353a	3598	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
tushki7	0:60d829a0353a	3599	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
tushki7	0:60d829a0353a	3600	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
tushki7	0:60d829a0353a	3601	#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
tushki7	0:60d829a0353a	3602	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000600) /!< PF[10] pin /
tushki7	0:60d829a0353a	3603	#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000700) /!< PG[10] pin /
tushki7	0:60d829a0353a	3604
tushki7	0:60d829a0353a	3605	/**
tushki7	0:60d829a0353a	3606	* @brief EXTI11 configuration
tushki7	0:60d829a0353a	3607	*/
tushki7	0:60d829a0353a	3608	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
tushki7	0:60d829a0353a	3609	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
tushki7	0:60d829a0353a	3610	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
tushki7	0:60d829a0353a	3611	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
tushki7	0:60d829a0353a	3612	#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
tushki7	0:60d829a0353a	3613	#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00006000) /!< PF[11] pin /
tushki7	0:60d829a0353a	3614	#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00007000) /!< PG[11] pin /
tushki7	0:60d829a0353a	3615
tushki7	0:60d829a0353a	3616	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
tushki7	0:60d829a0353a	3617	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
tushki7	0:60d829a0353a	3618	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
tushki7	0:60d829a0353a	3619	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
tushki7	0:60d829a0353a	3620	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
tushki7	0:60d829a0353a	3621
tushki7	0:60d829a0353a	3622	/**
tushki7	0:60d829a0353a	3623	* @brief EXTI12 configuration
tushki7	0:60d829a0353a	3624	*/
tushki7	0:60d829a0353a	3625	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
tushki7	0:60d829a0353a	3626	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
tushki7	0:60d829a0353a	3627	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
tushki7	0:60d829a0353a	3628	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
tushki7	0:60d829a0353a	3629	#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
tushki7	0:60d829a0353a	3630	#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000006) /!< PF[12] pin /
tushki7	0:60d829a0353a	3631	#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000007) /!< PG[12] pin /
tushki7	0:60d829a0353a	3632
tushki7	0:60d829a0353a	3633	/**
tushki7	0:60d829a0353a	3634	* @brief EXTI13 configuration
tushki7	0:60d829a0353a	3635	*/
tushki7	0:60d829a0353a	3636	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
tushki7	0:60d829a0353a	3637	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
tushki7	0:60d829a0353a	3638	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
tushki7	0:60d829a0353a	3639	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
tushki7	0:60d829a0353a	3640	#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
tushki7	0:60d829a0353a	3641	#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000060) /!< PF[13] pin /
tushki7	0:60d829a0353a	3642	#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000070) /!< PG[13] pin /
tushki7	0:60d829a0353a	3643
tushki7	0:60d829a0353a	3644	/**
tushki7	0:60d829a0353a	3645	* @brief EXTI14 configuration
tushki7	0:60d829a0353a	3646	*/
tushki7	0:60d829a0353a	3647	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
tushki7	0:60d829a0353a	3648	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
tushki7	0:60d829a0353a	3649	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
tushki7	0:60d829a0353a	3650	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
tushki7	0:60d829a0353a	3651	#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
tushki7	0:60d829a0353a	3652	#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000600) /!< PF[14] pin /
tushki7	0:60d829a0353a	3653	#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000700) /!< PG[14] pin /
tushki7	0:60d829a0353a	3654
tushki7	0:60d829a0353a	3655	/**
tushki7	0:60d829a0353a	3656	* @brief EXTI15 configuration
tushki7	0:60d829a0353a	3657	*/
tushki7	0:60d829a0353a	3658	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
tushki7	0:60d829a0353a	3659	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
tushki7	0:60d829a0353a	3660	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
tushki7	0:60d829a0353a	3661	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
tushki7	0:60d829a0353a	3662	#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
tushki7	0:60d829a0353a	3663	#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00006000) /!< PF[15] pin /
tushki7	0:60d829a0353a	3664	#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00007000) /!< PG[15] pin /
tushki7	0:60d829a0353a	3665
tushki7	0:60d829a0353a	3666	/******************************************************************************/
tushki7	0:60d829a0353a	3667	/* */
tushki7	0:60d829a0353a	3668	/* Routing Interface (RI) */
tushki7	0:60d829a0353a	3669	/* */
tushki7	0:60d829a0353a	3670	/******************************************************************************/
tushki7	0:60d829a0353a	3671
tushki7	0:60d829a0353a	3672	/****************** Bit definition for RI_ICR register ******************/
tushki7	0:60d829a0353a	3673	#define RI_ICR_IC1OS ((uint32_t)0x0000000F) /!< IC1OS[3:0] bits (Input Capture 1 select bits) /
tushki7	0:60d829a0353a	3674	#define RI_ICR_IC1OS_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3675	#define RI_ICR_IC1OS_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3676	#define RI_ICR_IC1OS_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3677	#define RI_ICR_IC1OS_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3678
tushki7	0:60d829a0353a	3679	#define RI_ICR_IC2OS ((uint32_t)0x000000F0) /!< IC2OS[3:0] bits (Input Capture 2 select bits) /
tushki7	0:60d829a0353a	3680	#define RI_ICR_IC2OS_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3681	#define RI_ICR_IC2OS_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3682	#define RI_ICR_IC2OS_2 ((uint32_t)0x00000040) /!< Bit 2 /
tushki7	0:60d829a0353a	3683	#define RI_ICR_IC2OS_3 ((uint32_t)0x00000080) /!< Bit 3 /
tushki7	0:60d829a0353a	3684
tushki7	0:60d829a0353a	3685	#define RI_ICR_IC3OS ((uint32_t)0x00000F00) /!< IC3OS[3:0] bits (Input Capture 3 select bits) /
tushki7	0:60d829a0353a	3686	#define RI_ICR_IC3OS_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	3687	#define RI_ICR_IC3OS_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	3688	#define RI_ICR_IC3OS_2 ((uint32_t)0x00000400) /!< Bit 2 /
tushki7	0:60d829a0353a	3689	#define RI_ICR_IC3OS_3 ((uint32_t)0x00000800) /!< Bit 3 /
tushki7	0:60d829a0353a	3690
tushki7	0:60d829a0353a	3691	#define RI_ICR_IC4OS ((uint32_t)0x0000F000) /!< IC4OS[3:0] bits (Input Capture 4 select bits) /
tushki7	0:60d829a0353a	3692	#define RI_ICR_IC4OS_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3693	#define RI_ICR_IC4OS_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3694	#define RI_ICR_IC4OS_2 ((uint32_t)0x00004000) /!< Bit 2 /
tushki7	0:60d829a0353a	3695	#define RI_ICR_IC4OS_3 ((uint32_t)0x00008000) /!< Bit 3 /
tushki7	0:60d829a0353a	3696
tushki7	0:60d829a0353a	3697	#define RI_ICR_TIM ((uint32_t)0x00030000) /!< TIM[3:0] bits (Timers select bits) /
tushki7	0:60d829a0353a	3698	#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	3699	#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	3700
tushki7	0:60d829a0353a	3701	#define RI_ICR_IC1 ((uint32_t)0x00040000) /!< Input capture 1 /
tushki7	0:60d829a0353a	3702	#define RI_ICR_IC2 ((uint32_t)0x00080000) /!< Input capture 2 /
tushki7	0:60d829a0353a	3703	#define RI_ICR_IC3 ((uint32_t)0x00100000) /!< Input capture 3 /
tushki7	0:60d829a0353a	3704	#define RI_ICR_IC4 ((uint32_t)0x00200000) /!< Input capture 4 /
tushki7	0:60d829a0353a	3705
tushki7	0:60d829a0353a	3706	/****************** Bit definition for RI_ASCR1 register ******************/
tushki7	0:60d829a0353a	3707	#define RI_ASCR1_CH ((uint32_t)0x7BFDFFFF) /!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) /
tushki7	0:60d829a0353a	3708	#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3709	#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3710	#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3711	#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3712	#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3713	#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3714	#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3715	#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3716	#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3717	#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3718	#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3719	#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3720	#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3721	#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3722	#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3723	#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3724	#define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /!< Bit 16 /
tushki7	0:60d829a0353a	3725	#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /!< Bit 18 /
tushki7	0:60d829a0353a	3726	#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /!< Bit 19 /
tushki7	0:60d829a0353a	3727	#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /!< Bit 20 /
tushki7	0:60d829a0353a	3728	#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /!< Bit 21 /
tushki7	0:60d829a0353a	3729	#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /!< Bit 22 /
tushki7	0:60d829a0353a	3730	#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /!< Bit 23 /
tushki7	0:60d829a0353a	3731	#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /!< Bit 24 /
tushki7	0:60d829a0353a	3732	#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /!< Bit 25 /
tushki7	0:60d829a0353a	3733	#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /!< ADC analog switch selection for internal node to COMP1 /
tushki7	0:60d829a0353a	3734	#define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /!< Bit 27 /
tushki7	0:60d829a0353a	3735	#define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /!< Bit 28 /
tushki7	0:60d829a0353a	3736	#define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /!< Bit 29 /
tushki7	0:60d829a0353a	3737	#define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /!< Bit 30 /
tushki7	0:60d829a0353a	3738	#define RI_ASCR1_SCM ((uint32_t)0x80000000) /!< I/O Switch control mode /
tushki7	0:60d829a0353a	3739
tushki7	0:60d829a0353a	3740	/****************** Bit definition for RI_ASCR2 register ******************/
tushki7	0:60d829a0353a	3741	#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /!< GR10-1 selection bit /
tushki7	0:60d829a0353a	3742	#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /!< GR10-2 selection bit /
tushki7	0:60d829a0353a	3743	#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /!< GR10-3 selection bit /
tushki7	0:60d829a0353a	3744	#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /!< GR10-4 selection bit /
tushki7	0:60d829a0353a	3745	#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /!< GR6-1 selection bit /
tushki7	0:60d829a0353a	3746	#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /!< GR6-2 selection bit /
tushki7	0:60d829a0353a	3747	#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /!< GR5-1 selection bit /
tushki7	0:60d829a0353a	3748	#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /!< GR5-2 selection bit /
tushki7	0:60d829a0353a	3749	#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /!< GR5-3 selection bit /
tushki7	0:60d829a0353a	3750	#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /!< GR4-1 selection bit /
tushki7	0:60d829a0353a	3751	#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /!< GR4-2 selection bit /
tushki7	0:60d829a0353a	3752	#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /!< GR4-3 selection bit /
tushki7	0:60d829a0353a	3753	#define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /!< GR4-4 selection bit /
tushki7	0:60d829a0353a	3754	#define RI_ASCR2_CH0b ((uint32_t)0x00010000) /!< CH0b selection bit /
tushki7	0:60d829a0353a	3755	#define RI_ASCR2_CH1b ((uint32_t)0x00020000) /!< CH1b selection bit /
tushki7	0:60d829a0353a	3756	#define RI_ASCR2_CH2b ((uint32_t)0x00040000) /!< CH2b selection bit /
tushki7	0:60d829a0353a	3757	#define RI_ASCR2_CH3b ((uint32_t)0x00080000) /!< CH3b selection bit /
tushki7	0:60d829a0353a	3758	#define RI_ASCR2_CH6b ((uint32_t)0x00100000) /!< CH6b selection bit /
tushki7	0:60d829a0353a	3759	#define RI_ASCR2_CH7b ((uint32_t)0x00200000) /!< CH7b selection bit /
tushki7	0:60d829a0353a	3760	#define RI_ASCR2_CH8b ((uint32_t)0x00400000) /!< CH8b selection bit /
tushki7	0:60d829a0353a	3761	#define RI_ASCR2_CH9b ((uint32_t)0x00800000) /!< CH9b selection bit /
tushki7	0:60d829a0353a	3762	#define RI_ASCR2_CH10b ((uint32_t)0x01000000) /!< CH10b selection bit /
tushki7	0:60d829a0353a	3763	#define RI_ASCR2_CH11b ((uint32_t)0x02000000) /!< CH11b selection bit /
tushki7	0:60d829a0353a	3764	#define RI_ASCR2_CH12b ((uint32_t)0x04000000) /!< CH12b selection bit /
tushki7	0:60d829a0353a	3765	#define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /!< GR6-3 selection bit /
tushki7	0:60d829a0353a	3766	#define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /!< GR6-4 selection bit /
tushki7	0:60d829a0353a	3767
tushki7	0:60d829a0353a	3768	/****************** Bit definition for RI_HYSCR1 register ******************/
tushki7	0:60d829a0353a	3769	#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A Hysteresis selection /
tushki7	0:60d829a0353a	3770	#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3771	#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3772	#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3773	#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3774	#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3775	#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3776	#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3777	#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3778	#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3779	#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3780	#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3781	#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3782	#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3783	#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3784	#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3785	#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3786
tushki7	0:60d829a0353a	3787	#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /!< PB[15:0] Port B Hysteresis selection /
tushki7	0:60d829a0353a	3788	#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	3789	#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	3790	#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /!< Bit 2 /
tushki7	0:60d829a0353a	3791	#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /!< Bit 3 /
tushki7	0:60d829a0353a	3792	#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /!< Bit 4 /
tushki7	0:60d829a0353a	3793	#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /!< Bit 5 /
tushki7	0:60d829a0353a	3794	#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /!< Bit 6 /
tushki7	0:60d829a0353a	3795	#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /!< Bit 7 /
tushki7	0:60d829a0353a	3796	#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /!< Bit 8 /
tushki7	0:60d829a0353a	3797	#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /!< Bit 9 /
tushki7	0:60d829a0353a	3798	#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /!< Bit 10 /
tushki7	0:60d829a0353a	3799	#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /!< Bit 11 /
tushki7	0:60d829a0353a	3800	#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /!< Bit 12 /
tushki7	0:60d829a0353a	3801	#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /!< Bit 13 /
tushki7	0:60d829a0353a	3802	#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /!< Bit 14 /
tushki7	0:60d829a0353a	3803	#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /!< Bit 15 /
tushki7	0:60d829a0353a	3804
tushki7	0:60d829a0353a	3805	/****************** Bit definition for RI_HYSCR2 register ******************/
tushki7	0:60d829a0353a	3806	#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C Hysteresis selection /
tushki7	0:60d829a0353a	3807	#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3808	#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3809	#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3810	#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3811	#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3812	#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3813	#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3814	#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3815	#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3816	#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3817	#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3818	#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3819	#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3820	#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3821	#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3822	#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3823
tushki7	0:60d829a0353a	3824	#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /!< PD[15:0] Port D Hysteresis selection /
tushki7	0:60d829a0353a	3825	#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	3826	#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	3827	#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /!< Bit 2 /
tushki7	0:60d829a0353a	3828	#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /!< Bit 3 /
tushki7	0:60d829a0353a	3829	#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /!< Bit 4 /
tushki7	0:60d829a0353a	3830	#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /!< Bit 5 /
tushki7	0:60d829a0353a	3831	#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /!< Bit 6 /
tushki7	0:60d829a0353a	3832	#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /!< Bit 7 /
tushki7	0:60d829a0353a	3833	#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /!< Bit 8 /
tushki7	0:60d829a0353a	3834	#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /!< Bit 9 /
tushki7	0:60d829a0353a	3835	#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /!< Bit 10 /
tushki7	0:60d829a0353a	3836	#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /!< Bit 11 /
tushki7	0:60d829a0353a	3837	#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /!< Bit 12 /
tushki7	0:60d829a0353a	3838	#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /!< Bit 13 /
tushki7	0:60d829a0353a	3839	#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /!< Bit 14 /
tushki7	0:60d829a0353a	3840	#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /!< Bit 15 /
tushki7	0:60d829a0353a	3841
tushki7	0:60d829a0353a	3842	/****************** Bit definition for RI_HYSCR3 register ******************/
tushki7	0:60d829a0353a	3843	#define RI_HYSCR3_PE ((uint32_t)0x0000FFFF) /!< PE[15:0] Port E Hysteresis selection /
tushki7	0:60d829a0353a	3844	#define RI_HYSCR3_PE_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3845	#define RI_HYSCR3_PE_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3846	#define RI_HYSCR3_PE_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3847	#define RI_HYSCR3_PE_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3848	#define RI_HYSCR3_PE_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3849	#define RI_HYSCR3_PE_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3850	#define RI_HYSCR3_PE_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3851	#define RI_HYSCR3_PE_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3852	#define RI_HYSCR3_PE_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3853	#define RI_HYSCR3_PE_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3854	#define RI_HYSCR3_PE_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3855	#define RI_HYSCR3_PE_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3856	#define RI_HYSCR3_PE_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3857	#define RI_HYSCR3_PE_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3858	#define RI_HYSCR3_PE_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3859	#define RI_HYSCR3_PE_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3860	#define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) /!< PF[15:0] Port F Hysteresis selection /
tushki7	0:60d829a0353a	3861	#define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	3862	#define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	3863	#define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) /!< Bit 2 /
tushki7	0:60d829a0353a	3864	#define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) /!< Bit 3 /
tushki7	0:60d829a0353a	3865	#define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) /!< Bit 4 /
tushki7	0:60d829a0353a	3866	#define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) /!< Bit 5 /
tushki7	0:60d829a0353a	3867	#define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) /!< Bit 6 /
tushki7	0:60d829a0353a	3868	#define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) /!< Bit 7 /
tushki7	0:60d829a0353a	3869	#define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) /!< Bit 8 /
tushki7	0:60d829a0353a	3870	#define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) /!< Bit 9 /
tushki7	0:60d829a0353a	3871	#define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) /!< Bit 10 /
tushki7	0:60d829a0353a	3872	#define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) /!< Bit 11 /
tushki7	0:60d829a0353a	3873	#define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) /!< Bit 12 /
tushki7	0:60d829a0353a	3874	#define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) /!< Bit 13 /
tushki7	0:60d829a0353a	3875	#define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) /!< Bit 14 /
tushki7	0:60d829a0353a	3876	#define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) /!< Bit 15 /
tushki7	0:60d829a0353a	3877
tushki7	0:60d829a0353a	3878	/****************** Bit definition for RI_HYSCR4 register ******************/
tushki7	0:60d829a0353a	3879	#define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) /!< PG[15:0] Port G Hysteresis selection /
tushki7	0:60d829a0353a	3880	#define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3881	#define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3882	#define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3883	#define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3884	#define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3885	#define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3886	#define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3887	#define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3888	#define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3889	#define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3890	#define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3891	#define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3892	#define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3893	#define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3894	#define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3895	#define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3896
tushki7	0:60d829a0353a	3897	/****************** Bit definition for RI_ASMR1 register ******************/
tushki7	0:60d829a0353a	3898	#define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A selection/
tushki7	0:60d829a0353a	3899	#define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3900	#define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3901	#define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3902	#define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3903	#define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3904	#define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3905	#define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3906	#define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3907	#define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3908	#define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3909	#define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3910	#define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3911	#define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3912	#define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3913	#define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3914	#define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3915
tushki7	0:60d829a0353a	3916	/****************** Bit definition for RI_CMR1 register ******************/
tushki7	0:60d829a0353a	3917	#define RI_CMR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A selection/
tushki7	0:60d829a0353a	3918	#define RI_CMR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3919	#define RI_CMR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3920	#define RI_CMR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3921	#define RI_CMR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3922	#define RI_CMR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3923	#define RI_CMR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3924	#define RI_CMR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3925	#define RI_CMR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3926	#define RI_CMR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3927	#define RI_CMR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3928	#define RI_CMR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3929	#define RI_CMR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3930	#define RI_CMR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3931	#define RI_CMR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3932	#define RI_CMR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3933	#define RI_CMR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3934
tushki7	0:60d829a0353a	3935	/****************** Bit definition for RI_CICR1 register ******************/
tushki7	0:60d829a0353a	3936	#define RI_CICR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A selection/
tushki7	0:60d829a0353a	3937	#define RI_CICR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3938	#define RI_CICR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3939	#define RI_CICR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3940	#define RI_CICR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3941	#define RI_CICR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3942	#define RI_CICR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3943	#define RI_CICR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3944	#define RI_CICR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3945	#define RI_CICR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3946	#define RI_CICR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3947	#define RI_CICR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3948	#define RI_CICR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3949	#define RI_CICR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3950	#define RI_CICR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3951	#define RI_CICR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3952	#define RI_CICR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3953
tushki7	0:60d829a0353a	3954	/****************** Bit definition for RI_ASMR2 register ******************/
tushki7	0:60d829a0353a	3955	#define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /!< PB[15:0] Port B selection /
tushki7	0:60d829a0353a	3956	#define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3957	#define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3958	#define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3959	#define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3960	#define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3961	#define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3962	#define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3963	#define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3964	#define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3965	#define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3966	#define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3967	#define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3968	#define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3969	#define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3970	#define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3971	#define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3972
tushki7	0:60d829a0353a	3973	/****************** Bit definition for RI_CMR2 register ******************/
tushki7	0:60d829a0353a	3974	#define RI_CMR2_PB ((uint32_t)0x0000FFFF) /!< PB[15:0] Port B selection /
tushki7	0:60d829a0353a	3975	#define RI_CMR2_PB_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3976	#define RI_CMR2_PB_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3977	#define RI_CMR2_PB_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3978	#define RI_CMR2_PB_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3979	#define RI_CMR2_PB_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3980	#define RI_CMR2_PB_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3981	#define RI_CMR2_PB_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3982	#define RI_CMR2_PB_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	3983	#define RI_CMR2_PB_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	3984	#define RI_CMR2_PB_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	3985	#define RI_CMR2_PB_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	3986	#define RI_CMR2_PB_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	3987	#define RI_CMR2_PB_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	3988	#define RI_CMR2_PB_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	3989	#define RI_CMR2_PB_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	3990	#define RI_CMR2_PB_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	3991
tushki7	0:60d829a0353a	3992	/****************** Bit definition for RI_CICR2 register ******************/
tushki7	0:60d829a0353a	3993	#define RI_CICR2_PB ((uint32_t)0x0000FFFF) /!< PB[15:0] Port B selection /
tushki7	0:60d829a0353a	3994	#define RI_CICR2_PB_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3995	#define RI_CICR2_PB_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3996	#define RI_CICR2_PB_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3997	#define RI_CICR2_PB_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3998	#define RI_CICR2_PB_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3999	#define RI_CICR2_PB_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4000	#define RI_CICR2_PB_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4001	#define RI_CICR2_PB_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4002	#define RI_CICR2_PB_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4003	#define RI_CICR2_PB_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4004	#define RI_CICR2_PB_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4005	#define RI_CICR2_PB_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4006	#define RI_CICR2_PB_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4007	#define RI_CICR2_PB_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4008	#define RI_CICR2_PB_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4009	#define RI_CICR2_PB_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4010
tushki7	0:60d829a0353a	4011	/****************** Bit definition for RI_ASMR3 register ******************/
tushki7	0:60d829a0353a	4012	#define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C selection /
tushki7	0:60d829a0353a	4013	#define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4014	#define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4015	#define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4016	#define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4017	#define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4018	#define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4019	#define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4020	#define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4021	#define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4022	#define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4023	#define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4024	#define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4025	#define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4026	#define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4027	#define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4028	#define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4029
tushki7	0:60d829a0353a	4030	/****************** Bit definition for RI_CMR3 register ******************/
tushki7	0:60d829a0353a	4031	#define RI_CMR3_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C selection /
tushki7	0:60d829a0353a	4032	#define RI_CMR3_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4033	#define RI_CMR3_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4034	#define RI_CMR3_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4035	#define RI_CMR3_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4036	#define RI_CMR3_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4037	#define RI_CMR3_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4038	#define RI_CMR3_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4039	#define RI_CMR3_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4040	#define RI_CMR3_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4041	#define RI_CMR3_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4042	#define RI_CMR3_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4043	#define RI_CMR3_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4044	#define RI_CMR3_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4045	#define RI_CMR3_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4046	#define RI_CMR3_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4047	#define RI_CMR3_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4048
tushki7	0:60d829a0353a	4049	/****************** Bit definition for RI_CICR3 register ******************/
tushki7	0:60d829a0353a	4050	#define RI_CICR3_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C selection /
tushki7	0:60d829a0353a	4051	#define RI_CICR3_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4052	#define RI_CICR3_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4053	#define RI_CICR3_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4054	#define RI_CICR3_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4055	#define RI_CICR3_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4056	#define RI_CICR3_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4057	#define RI_CICR3_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4058	#define RI_CICR3_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4059	#define RI_CICR3_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4060	#define RI_CICR3_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4061	#define RI_CICR3_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4062	#define RI_CICR3_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4063	#define RI_CICR3_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4064	#define RI_CICR3_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4065	#define RI_CICR3_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4066	#define RI_CICR3_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4067
tushki7	0:60d829a0353a	4068	/****************** Bit definition for RI_ASMR4 register ******************/
tushki7	0:60d829a0353a	4069	#define RI_ASMR4_PF ((uint32_t)0x0000FFFF) /!< PF[15:0] Port F selection /
tushki7	0:60d829a0353a	4070	#define RI_ASMR4_PF_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4071	#define RI_ASMR4_PF_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4072	#define RI_ASMR4_PF_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4073	#define RI_ASMR4_PF_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4074	#define RI_ASMR4_PF_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4075	#define RI_ASMR4_PF_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4076	#define RI_ASMR4_PF_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4077	#define RI_ASMR4_PF_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4078	#define RI_ASMR4_PF_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4079	#define RI_ASMR4_PF_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4080	#define RI_ASMR4_PF_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4081	#define RI_ASMR4_PF_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4082	#define RI_ASMR4_PF_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4083	#define RI_ASMR4_PF_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4084	#define RI_ASMR4_PF_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4085	#define RI_ASMR4_PF_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4086
tushki7	0:60d829a0353a	4087	/****************** Bit definition for RI_CMR4 register ******************/
tushki7	0:60d829a0353a	4088	#define RI_CMR4_PF ((uint32_t)0x0000FFFF) /!< PF[15:0] Port F selection /
tushki7	0:60d829a0353a	4089	#define RI_CMR4_PF_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4090	#define RI_CMR4_PF_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4091	#define RI_CMR4_PF_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4092	#define RI_CMR4_PF_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4093	#define RI_CMR4_PF_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4094	#define RI_CMR4_PF_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4095	#define RI_CMR4_PF_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4096	#define RI_CMR4_PF_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4097	#define RI_CMR4_PF_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4098	#define RI_CMR4_PF_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4099	#define RI_CMR4_PF_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4100	#define RI_CMR4_PF_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4101	#define RI_CMR4_PF_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4102	#define RI_CMR4_PF_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4103	#define RI_CMR4_PF_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4104	#define RI_CMR4_PF_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4105
tushki7	0:60d829a0353a	4106	/****************** Bit definition for RI_CICR4 register ******************/
tushki7	0:60d829a0353a	4107	#define RI_CICR4_PF ((uint32_t)0x0000FFFF) /!< PF[15:0] Port F selection /
tushki7	0:60d829a0353a	4108	#define RI_CICR4_PF_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4109	#define RI_CICR4_PF_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4110	#define RI_CICR4_PF_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4111	#define RI_CICR4_PF_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4112	#define RI_CICR4_PF_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4113	#define RI_CICR4_PF_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4114	#define RI_CICR4_PF_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4115	#define RI_CICR4_PF_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4116	#define RI_CICR4_PF_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4117	#define RI_CICR4_PF_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4118	#define RI_CICR4_PF_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4119	#define RI_CICR4_PF_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4120	#define RI_CICR4_PF_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4121	#define RI_CICR4_PF_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4122	#define RI_CICR4_PF_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4123	#define RI_CICR4_PF_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4124
tushki7	0:60d829a0353a	4125	/****************** Bit definition for RI_ASMR5 register ******************/
tushki7	0:60d829a0353a	4126	#define RI_ASMR5_PG ((uint32_t)0x0000FFFF) /!< PG[15:0] Port G selection /
tushki7	0:60d829a0353a	4127	#define RI_ASMR5_PG_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4128	#define RI_ASMR5_PG_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4129	#define RI_ASMR5_PG_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4130	#define RI_ASMR5_PG_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4131	#define RI_ASMR5_PG_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4132	#define RI_ASMR5_PG_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4133	#define RI_ASMR5_PG_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4134	#define RI_ASMR5_PG_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4135	#define RI_ASMR5_PG_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4136	#define RI_ASMR5_PG_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4137	#define RI_ASMR5_PG_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4138	#define RI_ASMR5_PG_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4139	#define RI_ASMR5_PG_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4140	#define RI_ASMR5_PG_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4141	#define RI_ASMR5_PG_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4142	#define RI_ASMR5_PG_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4143
tushki7	0:60d829a0353a	4144	/****************** Bit definition for RI_CMR5 register ******************/
tushki7	0:60d829a0353a	4145	#define RI_CMR5_PG ((uint32_t)0x0000FFFF) /!< PG[15:0] Port G selection /
tushki7	0:60d829a0353a	4146	#define RI_CMR5_PG_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4147	#define RI_CMR5_PG_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4148	#define RI_CMR5_PG_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4149	#define RI_CMR5_PG_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4150	#define RI_CMR5_PG_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4151	#define RI_CMR5_PG_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4152	#define RI_CMR5_PG_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4153	#define RI_CMR5_PG_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4154	#define RI_CMR5_PG_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4155	#define RI_CMR5_PG_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4156	#define RI_CMR5_PG_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4157	#define RI_CMR5_PG_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4158	#define RI_CMR5_PG_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4159	#define RI_CMR5_PG_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4160	#define RI_CMR5_PG_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4161	#define RI_CMR5_PG_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4162
tushki7	0:60d829a0353a	4163	/****************** Bit definition for RI_CICR5 register ******************/
tushki7	0:60d829a0353a	4164	#define RI_CICR5_PG ((uint32_t)0x0000FFFF) /!< PG[15:0] Port G selection /
tushki7	0:60d829a0353a	4165	#define RI_CICR5_PG_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4166	#define RI_CICR5_PG_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4167	#define RI_CICR5_PG_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4168	#define RI_CICR5_PG_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4169	#define RI_CICR5_PG_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4170	#define RI_CICR5_PG_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4171	#define RI_CICR5_PG_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4172	#define RI_CICR5_PG_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4173	#define RI_CICR5_PG_8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	4174	#define RI_CICR5_PG_9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	4175	#define RI_CICR5_PG_10 ((uint32_t)0x00000400) /!< Bit 10 /
tushki7	0:60d829a0353a	4176	#define RI_CICR5_PG_11 ((uint32_t)0x00000800) /!< Bit 11 /
tushki7	0:60d829a0353a	4177	#define RI_CICR5_PG_12 ((uint32_t)0x00001000) /!< Bit 12 /
tushki7	0:60d829a0353a	4178	#define RI_CICR5_PG_13 ((uint32_t)0x00002000) /!< Bit 13 /
tushki7	0:60d829a0353a	4179	#define RI_CICR5_PG_14 ((uint32_t)0x00004000) /!< Bit 14 /
tushki7	0:60d829a0353a	4180	#define RI_CICR5_PG_15 ((uint32_t)0x00008000) /!< Bit 15 /
tushki7	0:60d829a0353a	4181
tushki7	0:60d829a0353a	4182	/******************************************************************************/
tushki7	0:60d829a0353a	4183	/* */
tushki7	0:60d829a0353a	4184	/* Timers (TIM) */
tushki7	0:60d829a0353a	4185	/* */
tushki7	0:60d829a0353a	4186	/******************************************************************************/
tushki7	0:60d829a0353a	4187
tushki7	0:60d829a0353a	4188	/***************** Bit definition for TIM_CR1 register ******************/
tushki7	0:60d829a0353a	4189	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
tushki7	0:60d829a0353a	4190	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
tushki7	0:60d829a0353a	4191	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
tushki7	0:60d829a0353a	4192	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
tushki7	0:60d829a0353a	4193	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
tushki7	0:60d829a0353a	4194
tushki7	0:60d829a0353a	4195	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
tushki7	0:60d829a0353a	4196	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
tushki7	0:60d829a0353a	4197	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
tushki7	0:60d829a0353a	4198
tushki7	0:60d829a0353a	4199	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
tushki7	0:60d829a0353a	4200
tushki7	0:60d829a0353a	4201	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
tushki7	0:60d829a0353a	4202	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	4203	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	4204
tushki7	0:60d829a0353a	4205	/***************** Bit definition for TIM_CR2 register ******************/
tushki7	0:60d829a0353a	4206	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
tushki7	0:60d829a0353a	4207
tushki7	0:60d829a0353a	4208	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
tushki7	0:60d829a0353a	4209	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4210	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4211	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	4212
tushki7	0:60d829a0353a	4213	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
tushki7	0:60d829a0353a	4214
tushki7	0:60d829a0353a	4215	/***************** Bit definition for TIM_SMCR register *****************/
tushki7	0:60d829a0353a	4216	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
tushki7	0:60d829a0353a	4217	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	4218	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	4219	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
tushki7	0:60d829a0353a	4220
tushki7	0:60d829a0353a	4221	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
tushki7	0:60d829a0353a	4222
tushki7	0:60d829a0353a	4223	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
tushki7	0:60d829a0353a	4224	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4225	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4226	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	4227
tushki7	0:60d829a0353a	4228	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
tushki7	0:60d829a0353a	4229
tushki7	0:60d829a0353a	4230	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
tushki7	0:60d829a0353a	4231	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	4232	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	4233	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
tushki7	0:60d829a0353a	4234	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
tushki7	0:60d829a0353a	4235
tushki7	0:60d829a0353a	4236	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
tushki7	0:60d829a0353a	4237	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4238	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4239
tushki7	0:60d829a0353a	4240	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
tushki7	0:60d829a0353a	4241	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
tushki7	0:60d829a0353a	4242
tushki7	0:60d829a0353a	4243	/***************** Bit definition for TIM_DIER register *****************/
tushki7	0:60d829a0353a	4244	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
tushki7	0:60d829a0353a	4245	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
tushki7	0:60d829a0353a	4246	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
tushki7	0:60d829a0353a	4247	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
tushki7	0:60d829a0353a	4248	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
tushki7	0:60d829a0353a	4249	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
tushki7	0:60d829a0353a	4250	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
tushki7	0:60d829a0353a	4251	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
tushki7	0:60d829a0353a	4252	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
tushki7	0:60d829a0353a	4253	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
tushki7	0:60d829a0353a	4254	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
tushki7	0:60d829a0353a	4255	#define TIM_DIER_COMDE ((uint16_t)0x2000) /!<COM DMA request enable /
tushki7	0:60d829a0353a	4256	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
tushki7	0:60d829a0353a	4257
tushki7	0:60d829a0353a	4258	/****************** Bit definition for TIM_SR register ******************/
tushki7	0:60d829a0353a	4259	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
tushki7	0:60d829a0353a	4260	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
tushki7	0:60d829a0353a	4261	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
tushki7	0:60d829a0353a	4262	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
tushki7	0:60d829a0353a	4263	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
tushki7	0:60d829a0353a	4264	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
tushki7	0:60d829a0353a	4265	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
tushki7	0:60d829a0353a	4266	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
tushki7	0:60d829a0353a	4267	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
tushki7	0:60d829a0353a	4268	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
tushki7	0:60d829a0353a	4269
tushki7	0:60d829a0353a	4270	/***************** Bit definition for TIM_EGR register ******************/
tushki7	0:60d829a0353a	4271	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
tushki7	0:60d829a0353a	4272	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
tushki7	0:60d829a0353a	4273	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
tushki7	0:60d829a0353a	4274	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
tushki7	0:60d829a0353a	4275	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
tushki7	0:60d829a0353a	4276	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
tushki7	0:60d829a0353a	4277
tushki7	0:60d829a0353a	4278	/**************** Bit definition for TIM_CCMR1 register *****************/
tushki7	0:60d829a0353a	4279	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
tushki7	0:60d829a0353a	4280	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	4281	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	4282
tushki7	0:60d829a0353a	4283	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
tushki7	0:60d829a0353a	4284	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
tushki7	0:60d829a0353a	4285
tushki7	0:60d829a0353a	4286	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
tushki7	0:60d829a0353a	4287	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4288	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4289	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	4290
tushki7	0:60d829a0353a	4291	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
tushki7	0:60d829a0353a	4292
tushki7	0:60d829a0353a	4293	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
tushki7	0:60d829a0353a	4294	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	4295	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	4296
tushki7	0:60d829a0353a	4297	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
tushki7	0:60d829a0353a	4298	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
tushki7	0:60d829a0353a	4299
tushki7	0:60d829a0353a	4300	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
tushki7	0:60d829a0353a	4301	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4302	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4303	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
tushki7	0:60d829a0353a	4304
tushki7	0:60d829a0353a	4305	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
tushki7	0:60d829a0353a	4306
tushki7	0:60d829a0353a	4307	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4308
tushki7	0:60d829a0353a	4309	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
tushki7	0:60d829a0353a	4310	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
tushki7	0:60d829a0353a	4311	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
tushki7	0:60d829a0353a	4312
tushki7	0:60d829a0353a	4313	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
tushki7	0:60d829a0353a	4314	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4315	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4316	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	4317	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
tushki7	0:60d829a0353a	4318
tushki7	0:60d829a0353a	4319	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
tushki7	0:60d829a0353a	4320	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
tushki7	0:60d829a0353a	4321	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
tushki7	0:60d829a0353a	4322
tushki7	0:60d829a0353a	4323	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
tushki7	0:60d829a0353a	4324	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4325	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4326	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
tushki7	0:60d829a0353a	4327	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
tushki7	0:60d829a0353a	4328
tushki7	0:60d829a0353a	4329	/**************** Bit definition for TIM_CCMR2 register *****************/
tushki7	0:60d829a0353a	4330	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
tushki7	0:60d829a0353a	4331	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	4332	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	4333
tushki7	0:60d829a0353a	4334	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
tushki7	0:60d829a0353a	4335	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
tushki7	0:60d829a0353a	4336
tushki7	0:60d829a0353a	4337	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
tushki7	0:60d829a0353a	4338	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4339	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4340	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	4341
tushki7	0:60d829a0353a	4342	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
tushki7	0:60d829a0353a	4343
tushki7	0:60d829a0353a	4344	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
tushki7	0:60d829a0353a	4345	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	4346	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	4347
tushki7	0:60d829a0353a	4348	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
tushki7	0:60d829a0353a	4349	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
tushki7	0:60d829a0353a	4350
tushki7	0:60d829a0353a	4351	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
tushki7	0:60d829a0353a	4352	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4353	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4354	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
tushki7	0:60d829a0353a	4355
tushki7	0:60d829a0353a	4356	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
tushki7	0:60d829a0353a	4357
tushki7	0:60d829a0353a	4358	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4359
tushki7	0:60d829a0353a	4360	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
tushki7	0:60d829a0353a	4361	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
tushki7	0:60d829a0353a	4362	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
tushki7	0:60d829a0353a	4363
tushki7	0:60d829a0353a	4364	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
tushki7	0:60d829a0353a	4365	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4366	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4367	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	4368	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
tushki7	0:60d829a0353a	4369
tushki7	0:60d829a0353a	4370	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
tushki7	0:60d829a0353a	4371	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
tushki7	0:60d829a0353a	4372	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
tushki7	0:60d829a0353a	4373
tushki7	0:60d829a0353a	4374	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
tushki7	0:60d829a0353a	4375	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4376	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4377	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
tushki7	0:60d829a0353a	4378	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
tushki7	0:60d829a0353a	4379
tushki7	0:60d829a0353a	4380	/***************** Bit definition for TIM_CCER register *****************/
tushki7	0:60d829a0353a	4381	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
tushki7	0:60d829a0353a	4382	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
tushki7	0:60d829a0353a	4383	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
tushki7	0:60d829a0353a	4384	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
tushki7	0:60d829a0353a	4385	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
tushki7	0:60d829a0353a	4386	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
tushki7	0:60d829a0353a	4387	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
tushki7	0:60d829a0353a	4388	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
tushki7	0:60d829a0353a	4389	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
tushki7	0:60d829a0353a	4390	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
tushki7	0:60d829a0353a	4391	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
tushki7	0:60d829a0353a	4392	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
tushki7	0:60d829a0353a	4393
tushki7	0:60d829a0353a	4394	/***************** Bit definition for TIM_CNT register ******************/
tushki7	0:60d829a0353a	4395	#define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /!<Counter Value /
tushki7	0:60d829a0353a	4396
tushki7	0:60d829a0353a	4397	/***************** Bit definition for TIM_PSC register ******************/
tushki7	0:60d829a0353a	4398	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
tushki7	0:60d829a0353a	4399
tushki7	0:60d829a0353a	4400	/***************** Bit definition for TIM_ARR register ******************/
tushki7	0:60d829a0353a	4401	#define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /!<actual auto-reload Value /
tushki7	0:60d829a0353a	4402
tushki7	0:60d829a0353a	4403	/***************** Bit definition for TIM_CCR1 register *****************/
tushki7	0:60d829a0353a	4404	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
tushki7	0:60d829a0353a	4405
tushki7	0:60d829a0353a	4406	/***************** Bit definition for TIM_CCR2 register *****************/
tushki7	0:60d829a0353a	4407	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
tushki7	0:60d829a0353a	4408
tushki7	0:60d829a0353a	4409	/***************** Bit definition for TIM_CCR3 register *****************/
tushki7	0:60d829a0353a	4410	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
tushki7	0:60d829a0353a	4411
tushki7	0:60d829a0353a	4412	/***************** Bit definition for TIM_CCR4 register *****************/
tushki7	0:60d829a0353a	4413	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
tushki7	0:60d829a0353a	4414
tushki7	0:60d829a0353a	4415	/***************** Bit definition for TIM_DCR register ******************/
tushki7	0:60d829a0353a	4416	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
tushki7	0:60d829a0353a	4417	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	4418	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	4419	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
tushki7	0:60d829a0353a	4420	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
tushki7	0:60d829a0353a	4421	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
tushki7	0:60d829a0353a	4422
tushki7	0:60d829a0353a	4423	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
tushki7	0:60d829a0353a	4424	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	4425	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	4426	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
tushki7	0:60d829a0353a	4427	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
tushki7	0:60d829a0353a	4428	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
tushki7	0:60d829a0353a	4429
tushki7	0:60d829a0353a	4430	/***************** Bit definition for TIM_DMAR register *****************/
tushki7	0:60d829a0353a	4431	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
tushki7	0:60d829a0353a	4432
tushki7	0:60d829a0353a	4433	/***************** Bit definition for TIM_OR register *******************/
tushki7	0:60d829a0353a	4434	#define TIM_OR_TI1RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM Input 1 remap) /
tushki7	0:60d829a0353a	4435	#define TIM_OR_TI1RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	4436	#define TIM_OR_TI1RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	4437
tushki7	0:60d829a0353a	4438	#define TIM_OR_ETR_RMP ((uint32_t)0x00000004) /!<ETR_RMP bit (TIM10/11 ETR remap)/
tushki7	0:60d829a0353a	4439	#define TIM_OR_TI1_RMP_RI ((uint32_t)0x00000008) /!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) /
tushki7	0:60d829a0353a	4440
tushki7	0:60d829a0353a	4441	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4442	#define TIM9_OR_ITR1_RMP ((uint32_t)0x00000004) /!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) /
tushki7	0:60d829a0353a	4443
tushki7	0:60d829a0353a	4444	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4445	#define TIM2_OR_ITR1_RMP ((uint32_t)0x00000001) /!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) /
tushki7	0:60d829a0353a	4446
tushki7	0:60d829a0353a	4447	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4448	#define TIM3_OR_ITR2_RMP ((uint32_t)0x00000001) /!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) /
tushki7	0:60d829a0353a	4449
tushki7	0:60d829a0353a	4450	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4451
tushki7	0:60d829a0353a	4452
tushki7	0:60d829a0353a	4453	/******************************************************************************/
tushki7	0:60d829a0353a	4454	/* */
tushki7	0:60d829a0353a	4455	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
tushki7	0:60d829a0353a	4456	/* */
tushki7	0:60d829a0353a	4457	/******************************************************************************/
tushki7	0:60d829a0353a	4458
tushki7	0:60d829a0353a	4459	/***************** Bit definition for USART_SR register *****************/
tushki7	0:60d829a0353a	4460	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
tushki7	0:60d829a0353a	4461	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
tushki7	0:60d829a0353a	4462	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
tushki7	0:60d829a0353a	4463	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
tushki7	0:60d829a0353a	4464	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
tushki7	0:60d829a0353a	4465	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
tushki7	0:60d829a0353a	4466	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
tushki7	0:60d829a0353a	4467	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
tushki7	0:60d829a0353a	4468	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
tushki7	0:60d829a0353a	4469	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
tushki7	0:60d829a0353a	4470
tushki7	0:60d829a0353a	4471	/***************** Bit definition for USART_DR register *****************/
tushki7	0:60d829a0353a	4472	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
tushki7	0:60d829a0353a	4473
tushki7	0:60d829a0353a	4474	/**************** Bit definition for USART_BRR register *****************/
tushki7	0:60d829a0353a	4475	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
tushki7	0:60d829a0353a	4476	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
tushki7	0:60d829a0353a	4477
tushki7	0:60d829a0353a	4478	/**************** Bit definition for USART_CR1 register *****************/
tushki7	0:60d829a0353a	4479	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
tushki7	0:60d829a0353a	4480	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
tushki7	0:60d829a0353a	4481	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
tushki7	0:60d829a0353a	4482	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
tushki7	0:60d829a0353a	4483	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
tushki7	0:60d829a0353a	4484	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
tushki7	0:60d829a0353a	4485	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
tushki7	0:60d829a0353a	4486	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
tushki7	0:60d829a0353a	4487	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
tushki7	0:60d829a0353a	4488	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
tushki7	0:60d829a0353a	4489	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
tushki7	0:60d829a0353a	4490	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
tushki7	0:60d829a0353a	4491	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
tushki7	0:60d829a0353a	4492	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
tushki7	0:60d829a0353a	4493	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit mode /
tushki7	0:60d829a0353a	4494
tushki7	0:60d829a0353a	4495	/**************** Bit definition for USART_CR2 register *****************/
tushki7	0:60d829a0353a	4496	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
tushki7	0:60d829a0353a	4497	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
tushki7	0:60d829a0353a	4498	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
tushki7	0:60d829a0353a	4499	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
tushki7	0:60d829a0353a	4500	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
tushki7	0:60d829a0353a	4501	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
tushki7	0:60d829a0353a	4502	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
tushki7	0:60d829a0353a	4503
tushki7	0:60d829a0353a	4504	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
tushki7	0:60d829a0353a	4505	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	4506	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	4507
tushki7	0:60d829a0353a	4508	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
tushki7	0:60d829a0353a	4509
tushki7	0:60d829a0353a	4510	/**************** Bit definition for USART_CR3 register *****************/
tushki7	0:60d829a0353a	4511	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
tushki7	0:60d829a0353a	4512	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
tushki7	0:60d829a0353a	4513	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
tushki7	0:60d829a0353a	4514	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
tushki7	0:60d829a0353a	4515	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
tushki7	0:60d829a0353a	4516	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
tushki7	0:60d829a0353a	4517	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
tushki7	0:60d829a0353a	4518	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
tushki7	0:60d829a0353a	4519	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
tushki7	0:60d829a0353a	4520	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
tushki7	0:60d829a0353a	4521	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
tushki7	0:60d829a0353a	4522	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
tushki7	0:60d829a0353a	4523
tushki7	0:60d829a0353a	4524	/**************** Bit definition for USART_GTPR register ****************/
tushki7	0:60d829a0353a	4525	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
tushki7	0:60d829a0353a	4526	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	4527	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	4528	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	4529	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	4530	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	4531	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	4532	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	4533	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	4534
tushki7	0:60d829a0353a	4535	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
tushki7	0:60d829a0353a	4536
tushki7	0:60d829a0353a	4537	/******************************************************************************/
tushki7	0:60d829a0353a	4538	/* */
tushki7	0:60d829a0353a	4539	/* Universal Serial Bus (USB) */
tushki7	0:60d829a0353a	4540	/* */
tushki7	0:60d829a0353a	4541	/******************************************************************************/
tushki7	0:60d829a0353a	4542
tushki7	0:60d829a0353a	4543	/!<Endpoint-specific registers /
tushki7	0:60d829a0353a	4544
tushki7	0:60d829a0353a	4545	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
tushki7	0:60d829a0353a	4546	#define USB_EP1R (USB_BASE + 0x00000004) /!< endpoint 1 register address /
tushki7	0:60d829a0353a	4547	#define USB_EP2R (USB_BASE + 0x00000008) /!< endpoint 2 register address /
tushki7	0:60d829a0353a	4548	#define USB_EP3R (USB_BASE + 0x0000000C) /!< endpoint 3 register address /
tushki7	0:60d829a0353a	4549	#define USB_EP4R (USB_BASE + 0x00000010) /!< endpoint 4 register address /
tushki7	0:60d829a0353a	4550	#define USB_EP5R (USB_BASE + 0x00000014) /!< endpoint 5 register address /
tushki7	0:60d829a0353a	4551	#define USB_EP6R (USB_BASE + 0x00000018) /!< endpoint 6 register address /
tushki7	0:60d829a0353a	4552	#define USB_EP7R (USB_BASE + 0x0000001C) /!< endpoint 7 register address /
tushki7	0:60d829a0353a	4553
tushki7	0:60d829a0353a	4554	/* bit positions */
tushki7	0:60d829a0353a	4555	#define USB_EP_CTR_RX ((uint32_t)0x00008000) /!< EndPoint Correct TRansfer RX /
tushki7	0:60d829a0353a	4556	#define USB_EP_DTOG_RX ((uint32_t)0x00004000) /!< EndPoint Data TOGGLE RX /
tushki7	0:60d829a0353a	4557	#define USB_EPRX_STAT ((uint32_t)0x00003000) /!< EndPoint RX STATus bit field /
tushki7	0:60d829a0353a	4558	#define USB_EP_SETUP ((uint32_t)0x00000800) /!< EndPoint SETUP /
tushki7	0:60d829a0353a	4559	#define USB_EP_T_FIELD ((uint32_t)0x00000600) /!< EndPoint TYPE /
tushki7	0:60d829a0353a	4560	#define USB_EP_KIND ((uint32_t)0x00000100) /!< EndPoint KIND /
tushki7	0:60d829a0353a	4561	#define USB_EP_CTR_TX ((uint32_t)0x00000080) /!< EndPoint Correct TRansfer TX /
tushki7	0:60d829a0353a	4562	#define USB_EP_DTOG_TX ((uint32_t)0x00000040) /!< EndPoint Data TOGGLE TX /
tushki7	0:60d829a0353a	4563	#define USB_EPTX_STAT ((uint32_t)0x00000030) /!< EndPoint TX STATus bit field /
tushki7	0:60d829a0353a	4564	#define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /!< EndPoint ADDRess FIELD /
tushki7	0:60d829a0353a	4565
tushki7	0:60d829a0353a	4566	/* EndPoint REGister MASK (no toggle fields) */
tushki7	0:60d829a0353a	4567	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
tushki7	0:60d829a0353a	4568	/!< EP_TYPE[1:0] EndPoint TYPE /
tushki7	0:60d829a0353a	4569	#define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /!< EndPoint TYPE Mask /
tushki7	0:60d829a0353a	4570	#define USB_EP_BULK ((uint32_t)0x00000000) /!< EndPoint BULK /
tushki7	0:60d829a0353a	4571	#define USB_EP_CONTROL ((uint32_t)0x00000200) /!< EndPoint CONTROL /
tushki7	0:60d829a0353a	4572	#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /!< EndPoint ISOCHRONOUS /
tushki7	0:60d829a0353a	4573	#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /!< EndPoint INTERRUPT /
tushki7	0:60d829a0353a	4574	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
tushki7	0:60d829a0353a	4575
tushki7	0:60d829a0353a	4576	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
tushki7	0:60d829a0353a	4577	/!< STAT_TX[1:0] STATus for TX transfer /
tushki7	0:60d829a0353a	4578	#define USB_EP_TX_DIS ((uint32_t)0x00000000) /!< EndPoint TX DISabled /
tushki7	0:60d829a0353a	4579	#define USB_EP_TX_STALL ((uint32_t)0x00000010) /!< EndPoint TX STALLed /
tushki7	0:60d829a0353a	4580	#define USB_EP_TX_NAK ((uint32_t)0x00000020) /!< EndPoint TX NAKed /
tushki7	0:60d829a0353a	4581	#define USB_EP_TX_VALID ((uint32_t)0x00000030) /!< EndPoint TX VALID /
tushki7	0:60d829a0353a	4582	#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /!< EndPoint TX Data TOGgle bit1 /
tushki7	0:60d829a0353a	4583	#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /!< EndPoint TX Data TOGgle bit2 /
tushki7	0:60d829a0353a	4584	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
tushki7	0:60d829a0353a	4585	/!< STAT_RX[1:0] STATus for RX transfer /
tushki7	0:60d829a0353a	4586	#define USB_EP_RX_DIS ((uint32_t)0x00000000) /!< EndPoint RX DISabled /
tushki7	0:60d829a0353a	4587	#define USB_EP_RX_STALL ((uint32_t)0x00001000) /!< EndPoint RX STALLed /
tushki7	0:60d829a0353a	4588	#define USB_EP_RX_NAK ((uint32_t)0x00002000) /!< EndPoint RX NAKed /
tushki7	0:60d829a0353a	4589	#define USB_EP_RX_VALID ((uint32_t)0x00003000) /!< EndPoint RX VALID /
tushki7	0:60d829a0353a	4590	#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /!< EndPoint RX Data TOGgle bit1 /
tushki7	0:60d829a0353a	4591	#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /!< EndPoint RX Data TOGgle bit1 /
tushki7	0:60d829a0353a	4592	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
tushki7	0:60d829a0353a	4593
tushki7	0:60d829a0353a	4594	/***************** Bit definition for USB_EP0R register *****************/
tushki7	0:60d829a0353a	4595	#define USB_EP0R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
tushki7	0:60d829a0353a	4596
tushki7	0:60d829a0353a	4597	#define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	4598	#define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4599	#define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4600
tushki7	0:60d829a0353a	4601	#define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	4602	#define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
tushki7	0:60d829a0353a	4603	#define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
tushki7	0:60d829a0353a	4604
tushki7	0:60d829a0353a	4605	#define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	4606	#define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
tushki7	0:60d829a0353a	4607	#define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
tushki7	0:60d829a0353a	4608
tushki7	0:60d829a0353a	4609	#define USB_EP0R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
tushki7	0:60d829a0353a	4610
tushki7	0:60d829a0353a	4611	#define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	4612	#define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4613	#define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4614
tushki7	0:60d829a0353a	4615	#define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	4616	#define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
tushki7	0:60d829a0353a	4617
tushki7	0:60d829a0353a	4618	/***************** Bit definition for USB_EP1R register *****************/
tushki7	0:60d829a0353a	4619	#define USB_EP1R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
tushki7	0:60d829a0353a	4620
tushki7	0:60d829a0353a	4621	#define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	4622	#define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4623	#define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4624
tushki7	0:60d829a0353a	4625	#define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	4626	#define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
tushki7	0:60d829a0353a	4627	#define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
tushki7	0:60d829a0353a	4628
tushki7	0:60d829a0353a	4629	#define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	4630	#define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
tushki7	0:60d829a0353a	4631	#define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
tushki7	0:60d829a0353a	4632
tushki7	0:60d829a0353a	4633	#define USB_EP1R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
tushki7	0:60d829a0353a	4634
tushki7	0:60d829a0353a	4635	#define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	4636	#define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4637	#define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4638
tushki7	0:60d829a0353a	4639	#define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	4640	#define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
tushki7	0:60d829a0353a	4641
tushki7	0:60d829a0353a	4642	/***************** Bit definition for USB_EP2R register *****************/
tushki7	0:60d829a0353a	4643	#define USB_EP2R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
tushki7	0:60d829a0353a	4644
tushki7	0:60d829a0353a	4645	#define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	4646	#define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4647	#define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4648
tushki7	0:60d829a0353a	4649	#define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	4650	#define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
tushki7	0:60d829a0353a	4651	#define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
tushki7	0:60d829a0353a	4652
tushki7	0:60d829a0353a	4653	#define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	4654	#define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
tushki7	0:60d829a0353a	4655	#define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
tushki7	0:60d829a0353a	4656
tushki7	0:60d829a0353a	4657	#define USB_EP2R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
tushki7	0:60d829a0353a	4658
tushki7	0:60d829a0353a	4659	#define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	4660	#define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4661	#define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4662
tushki7	0:60d829a0353a	4663	#define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	4664	#define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
tushki7	0:60d829a0353a	4665
tushki7	0:60d829a0353a	4666	/***************** Bit definition for USB_EP3R register *****************/
tushki7	0:60d829a0353a	4667	#define USB_EP3R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
tushki7	0:60d829a0353a	4668
tushki7	0:60d829a0353a	4669	#define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	4670	#define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4671	#define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4672
tushki7	0:60d829a0353a	4673	#define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	4674	#define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
tushki7	0:60d829a0353a	4675	#define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
tushki7	0:60d829a0353a	4676
tushki7	0:60d829a0353a	4677	#define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	4678	#define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
tushki7	0:60d829a0353a	4679	#define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
tushki7	0:60d829a0353a	4680
tushki7	0:60d829a0353a	4681	#define USB_EP3R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
tushki7	0:60d829a0353a	4682
tushki7	0:60d829a0353a	4683	#define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	4684	#define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4685	#define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4686
tushki7	0:60d829a0353a	4687	#define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	4688	#define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
tushki7	0:60d829a0353a	4689
tushki7	0:60d829a0353a	4690	/***************** Bit definition for USB_EP4R register *****************/
tushki7	0:60d829a0353a	4691	#define USB_EP4R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
tushki7	0:60d829a0353a	4692
tushki7	0:60d829a0353a	4693	#define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	4694	#define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4695	#define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4696
tushki7	0:60d829a0353a	4697	#define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	4698	#define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
tushki7	0:60d829a0353a	4699	#define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
tushki7	0:60d829a0353a	4700
tushki7	0:60d829a0353a	4701	#define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	4702	#define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
tushki7	0:60d829a0353a	4703	#define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
tushki7	0:60d829a0353a	4704
tushki7	0:60d829a0353a	4705	#define USB_EP4R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
tushki7	0:60d829a0353a	4706
tushki7	0:60d829a0353a	4707	#define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	4708	#define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4709	#define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4710
tushki7	0:60d829a0353a	4711	#define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	4712	#define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
tushki7	0:60d829a0353a	4713
tushki7	0:60d829a0353a	4714	/***************** Bit definition for USB_EP5R register *****************/
tushki7	0:60d829a0353a	4715	#define USB_EP5R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
tushki7	0:60d829a0353a	4716
tushki7	0:60d829a0353a	4717	#define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	4718	#define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4719	#define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4720
tushki7	0:60d829a0353a	4721	#define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	4722	#define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
tushki7	0:60d829a0353a	4723	#define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
tushki7	0:60d829a0353a	4724
tushki7	0:60d829a0353a	4725	#define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	4726	#define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
tushki7	0:60d829a0353a	4727	#define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
tushki7	0:60d829a0353a	4728
tushki7	0:60d829a0353a	4729	#define USB_EP5R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
tushki7	0:60d829a0353a	4730
tushki7	0:60d829a0353a	4731	#define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	4732	#define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4733	#define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4734
tushki7	0:60d829a0353a	4735	#define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	4736	#define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
tushki7	0:60d829a0353a	4737
tushki7	0:60d829a0353a	4738	/***************** Bit definition for USB_EP6R register *****************/
tushki7	0:60d829a0353a	4739	#define USB_EP6R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
tushki7	0:60d829a0353a	4740
tushki7	0:60d829a0353a	4741	#define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	4742	#define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4743	#define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4744
tushki7	0:60d829a0353a	4745	#define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	4746	#define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
tushki7	0:60d829a0353a	4747	#define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
tushki7	0:60d829a0353a	4748
tushki7	0:60d829a0353a	4749	#define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	4750	#define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
tushki7	0:60d829a0353a	4751	#define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
tushki7	0:60d829a0353a	4752
tushki7	0:60d829a0353a	4753	#define USB_EP6R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
tushki7	0:60d829a0353a	4754
tushki7	0:60d829a0353a	4755	#define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	4756	#define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4757	#define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4758
tushki7	0:60d829a0353a	4759	#define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	4760	#define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
tushki7	0:60d829a0353a	4761
tushki7	0:60d829a0353a	4762	/***************** Bit definition for USB_EP7R register *****************/
tushki7	0:60d829a0353a	4763	#define USB_EP7R_EA ((uint32_t)0x0000000F) /!<Endpoint Address /
tushki7	0:60d829a0353a	4764
tushki7	0:60d829a0353a	4765	#define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	4766	#define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	4767	#define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	4768
tushki7	0:60d829a0353a	4769	#define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /!<Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	4770	#define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /!<Correct Transfer for transmission /
tushki7	0:60d829a0353a	4771	#define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /!<Endpoint Kind /
tushki7	0:60d829a0353a	4772
tushki7	0:60d829a0353a	4773	#define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /!<EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	4774	#define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /!<Bit 0 /
tushki7	0:60d829a0353a	4775	#define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /!<Bit 1 /
tushki7	0:60d829a0353a	4776
tushki7	0:60d829a0353a	4777	#define USB_EP7R_SETUP ((uint32_t)0x00000800) /!<Setup transaction completed /
tushki7	0:60d829a0353a	4778
tushki7	0:60d829a0353a	4779	#define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	4780	#define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	4781	#define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	4782
tushki7	0:60d829a0353a	4783	#define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /!<Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	4784	#define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /!<Correct Transfer for reception /
tushki7	0:60d829a0353a	4785
tushki7	0:60d829a0353a	4786	/!<Common registers /
tushki7	0:60d829a0353a	4787
tushki7	0:60d829a0353a	4788	#define USB_CNTR (USB_BASE + 0x00000040) /!< Control register /
tushki7	0:60d829a0353a	4789	#define USB_ISTR (USB_BASE + 0x00000044) /!< Interrupt status register /
tushki7	0:60d829a0353a	4790	#define USB_FNR (USB_BASE + 0x00000048) /!< Frame number register /
tushki7	0:60d829a0353a	4791	#define USB_DADDR (USB_BASE + 0x0000004C) /!< Device address register /
tushki7	0:60d829a0353a	4792	#define USB_BTABLE (USB_BASE + 0x00000050) /!< Buffer Table address register /
tushki7	0:60d829a0353a	4793
tushki7	0:60d829a0353a	4794
tushki7	0:60d829a0353a	4795
tushki7	0:60d829a0353a	4796	/***************** Bit definition for USB_CNTR register *****************/
tushki7	0:60d829a0353a	4797	#define USB_CNTR_FRES ((uint32_t)0x00000001) /!<Force USB Reset /
tushki7	0:60d829a0353a	4798	#define USB_CNTR_PDWN ((uint32_t)0x00000002) /!<Power down /
tushki7	0:60d829a0353a	4799	#define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /!<Low-power mode /
tushki7	0:60d829a0353a	4800	#define USB_CNTR_FSUSP ((uint32_t)0x00000008) /!<Force suspend /
tushki7	0:60d829a0353a	4801	#define USB_CNTR_RESUME ((uint32_t)0x00000010) /!<Resume request /
tushki7	0:60d829a0353a	4802	#define USB_CNTR_ESOFM ((uint32_t)0x00000100) /!<Expected Start Of Frame Interrupt Mask /
tushki7	0:60d829a0353a	4803	#define USB_CNTR_SOFM ((uint32_t)0x00000200) /!<Start Of Frame Interrupt Mask /
tushki7	0:60d829a0353a	4804	#define USB_CNTR_RESETM ((uint32_t)0x00000400) /!<RESET Interrupt Mask /
tushki7	0:60d829a0353a	4805	#define USB_CNTR_SUSPM ((uint32_t)0x00000800) /!<Suspend mode Interrupt Mask /
tushki7	0:60d829a0353a	4806	#define USB_CNTR_WKUPM ((uint32_t)0x00001000) /!<Wakeup Interrupt Mask /
tushki7	0:60d829a0353a	4807	#define USB_CNTR_ERRM ((uint32_t)0x00002000) /!<Error Interrupt Mask /
tushki7	0:60d829a0353a	4808	#define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /!<Packet Memory Area Over / Underrun Interrupt Mask /
tushki7	0:60d829a0353a	4809	#define USB_CNTR_CTRM ((uint32_t)0x00008000) /!<Correct Transfer Interrupt Mask /
tushki7	0:60d829a0353a	4810
tushki7	0:60d829a0353a	4811	/***************** Bit definition for USB_ISTR register *****************/
tushki7	0:60d829a0353a	4812	#define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /!<Endpoint Identifier /
tushki7	0:60d829a0353a	4813	#define USB_ISTR_DIR ((uint32_t)0x00000010) /!<Direction of transaction /
tushki7	0:60d829a0353a	4814	#define USB_ISTR_ESOF ((uint32_t)0x00000100) /!<Expected Start Of Frame /
tushki7	0:60d829a0353a	4815	#define USB_ISTR_SOF ((uint32_t)0x00000200) /!<Start Of Frame /
tushki7	0:60d829a0353a	4816	#define USB_ISTR_RESET ((uint32_t)0x00000400) /!<USB RESET request /
tushki7	0:60d829a0353a	4817	#define USB_ISTR_SUSP ((uint32_t)0x00000800) /!<Suspend mode request /
tushki7	0:60d829a0353a	4818	#define USB_ISTR_WKUP ((uint32_t)0x00001000) /!<Wake up /
tushki7	0:60d829a0353a	4819	#define USB_ISTR_ERR ((uint32_t)0x00002000) /!<Error /
tushki7	0:60d829a0353a	4820	#define USB_ISTR_PMAOVRM ((uint32_t)0x00004000) /!<Packet Memory Area Over / Underrun /
tushki7	0:60d829a0353a	4821	#define USB_ISTR_CTR ((uint32_t)0x00008000) /!<Correct Transfer /
tushki7	0:60d829a0353a	4822
tushki7	0:60d829a0353a	4823	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
tushki7	0:60d829a0353a	4824	#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
tushki7	0:60d829a0353a	4825	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
tushki7	0:60d829a0353a	4826	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
tushki7	0:60d829a0353a	4827	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
tushki7	0:60d829a0353a	4828	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
tushki7	0:60d829a0353a	4829	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
tushki7	0:60d829a0353a	4830	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
tushki7	0:60d829a0353a	4831
tushki7	0:60d829a0353a	4832
tushki7	0:60d829a0353a	4833	/***************** Bit definition for USB_FNR register ******************/
tushki7	0:60d829a0353a	4834	#define USB_FNR_FN ((uint32_t)0x000007FF) /!<Frame Number /
tushki7	0:60d829a0353a	4835	#define USB_FNR_LSOF ((uint32_t)0x00001800) /!<Lost SOF /
tushki7	0:60d829a0353a	4836	#define USB_FNR_LCK ((uint32_t)0x00002000) /!<Locked /
tushki7	0:60d829a0353a	4837	#define USB_FNR_RXDM ((uint32_t)0x00004000) /!<Receive Data - Line Status /
tushki7	0:60d829a0353a	4838	#define USB_FNR_RXDP ((uint32_t)0x00008000) /!<Receive Data + Line Status /
tushki7	0:60d829a0353a	4839
tushki7	0:60d829a0353a	4840	/**************** Bit definition for USB_DADDR register *****************/
tushki7	0:60d829a0353a	4841	#define USB_DADDR_ADD ((uint32_t)0x0000007F) /!<ADD[6:0] bits (Device Address) /
tushki7	0:60d829a0353a	4842	#define USB_DADDR_ADD0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	4843	#define USB_DADDR_ADD1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	4844	#define USB_DADDR_ADD2 ((uint32_t)0x00000004) /!<Bit 2 /
tushki7	0:60d829a0353a	4845	#define USB_DADDR_ADD3 ((uint32_t)0x00000008) /!<Bit 3 /
tushki7	0:60d829a0353a	4846	#define USB_DADDR_ADD4 ((uint32_t)0x00000010) /!<Bit 4 /
tushki7	0:60d829a0353a	4847	#define USB_DADDR_ADD5 ((uint32_t)0x00000020) /!<Bit 5 /
tushki7	0:60d829a0353a	4848	#define USB_DADDR_ADD6 ((uint32_t)0x00000040) /!<Bit 6 /
tushki7	0:60d829a0353a	4849
tushki7	0:60d829a0353a	4850	#define USB_DADDR_EF ((uint32_t)0x00000080) /!<Enable Function /
tushki7	0:60d829a0353a	4851
tushki7	0:60d829a0353a	4852	/**************** Bit definition for USB_BTABLE register ****************/
tushki7	0:60d829a0353a	4853	#define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /!<Buffer Table /
tushki7	0:60d829a0353a	4854
tushki7	0:60d829a0353a	4855	/!< Buffer descriptor table /
tushki7	0:60d829a0353a	4856	/*************** Bit definition for USB_ADDR0_TX register ***************/
tushki7	0:60d829a0353a	4857	#define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 0 /
tushki7	0:60d829a0353a	4858
tushki7	0:60d829a0353a	4859	/*************** Bit definition for USB_ADDR1_TX register ***************/
tushki7	0:60d829a0353a	4860	#define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 1 /
tushki7	0:60d829a0353a	4861
tushki7	0:60d829a0353a	4862	/*************** Bit definition for USB_ADDR2_TX register ***************/
tushki7	0:60d829a0353a	4863	#define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 2 /
tushki7	0:60d829a0353a	4864
tushki7	0:60d829a0353a	4865	/*************** Bit definition for USB_ADDR3_TX register ***************/
tushki7	0:60d829a0353a	4866	#define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 3 /
tushki7	0:60d829a0353a	4867
tushki7	0:60d829a0353a	4868	/*************** Bit definition for USB_ADDR4_TX register ***************/
tushki7	0:60d829a0353a	4869	#define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 4 /
tushki7	0:60d829a0353a	4870
tushki7	0:60d829a0353a	4871	/*************** Bit definition for USB_ADDR5_TX register ***************/
tushki7	0:60d829a0353a	4872	#define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 5 /
tushki7	0:60d829a0353a	4873
tushki7	0:60d829a0353a	4874	/*************** Bit definition for USB_ADDR6_TX register ***************/
tushki7	0:60d829a0353a	4875	#define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 6 /
tushki7	0:60d829a0353a	4876
tushki7	0:60d829a0353a	4877	/*************** Bit definition for USB_ADDR7_TX register ***************/
tushki7	0:60d829a0353a	4878	#define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 7 /
tushki7	0:60d829a0353a	4879
tushki7	0:60d829a0353a	4880	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4881
tushki7	0:60d829a0353a	4882	/*************** Bit definition for USB_COUNT0_TX register **************/
tushki7	0:60d829a0353a	4883	#define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 /
tushki7	0:60d829a0353a	4884
tushki7	0:60d829a0353a	4885	/*************** Bit definition for USB_COUNT1_TX register **************/
tushki7	0:60d829a0353a	4886	#define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 /
tushki7	0:60d829a0353a	4887
tushki7	0:60d829a0353a	4888	/*************** Bit definition for USB_COUNT2_TX register **************/
tushki7	0:60d829a0353a	4889	#define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 /
tushki7	0:60d829a0353a	4890
tushki7	0:60d829a0353a	4891	/*************** Bit definition for USB_COUNT3_TX register **************/
tushki7	0:60d829a0353a	4892	#define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 /
tushki7	0:60d829a0353a	4893
tushki7	0:60d829a0353a	4894	/*************** Bit definition for USB_COUNT4_TX register **************/
tushki7	0:60d829a0353a	4895	#define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 /
tushki7	0:60d829a0353a	4896
tushki7	0:60d829a0353a	4897	/*************** Bit definition for USB_COUNT5_TX register **************/
tushki7	0:60d829a0353a	4898	#define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 /
tushki7	0:60d829a0353a	4899
tushki7	0:60d829a0353a	4900	/*************** Bit definition for USB_COUNT6_TX register **************/
tushki7	0:60d829a0353a	4901	#define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 /
tushki7	0:60d829a0353a	4902
tushki7	0:60d829a0353a	4903	/*************** Bit definition for USB_COUNT7_TX register **************/
tushki7	0:60d829a0353a	4904	#define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 /
tushki7	0:60d829a0353a	4905
tushki7	0:60d829a0353a	4906	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4907
tushki7	0:60d829a0353a	4908	/************** Bit definition for USB_COUNT0_TX_0 register *************/
tushki7	0:60d829a0353a	4909	#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 (low) /
tushki7	0:60d829a0353a	4910
tushki7	0:60d829a0353a	4911	/************** Bit definition for USB_COUNT0_TX_1 register *************/
tushki7	0:60d829a0353a	4912	#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 0 (high) /
tushki7	0:60d829a0353a	4913
tushki7	0:60d829a0353a	4914	/************** Bit definition for USB_COUNT1_TX_0 register *************/
tushki7	0:60d829a0353a	4915	#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 (low) /
tushki7	0:60d829a0353a	4916
tushki7	0:60d829a0353a	4917	/************** Bit definition for USB_COUNT1_TX_1 register *************/
tushki7	0:60d829a0353a	4918	#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 1 (high) /
tushki7	0:60d829a0353a	4919
tushki7	0:60d829a0353a	4920	/************** Bit definition for USB_COUNT2_TX_0 register *************/
tushki7	0:60d829a0353a	4921	#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 (low) /
tushki7	0:60d829a0353a	4922
tushki7	0:60d829a0353a	4923	/************** Bit definition for USB_COUNT2_TX_1 register *************/
tushki7	0:60d829a0353a	4924	#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 2 (high) /
tushki7	0:60d829a0353a	4925
tushki7	0:60d829a0353a	4926	/************** Bit definition for USB_COUNT3_TX_0 register *************/
tushki7	0:60d829a0353a	4927	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x0000000003FF) /!< Transmission Byte Count 3 (low) /
tushki7	0:60d829a0353a	4928
tushki7	0:60d829a0353a	4929	/************** Bit definition for USB_COUNT3_TX_1 register *************/
tushki7	0:60d829a0353a	4930	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FF0000) /!< Transmission Byte Count 3 (high) /
tushki7	0:60d829a0353a	4931
tushki7	0:60d829a0353a	4932	/************** Bit definition for USB_COUNT4_TX_0 register *************/
tushki7	0:60d829a0353a	4933	#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 (low) /
tushki7	0:60d829a0353a	4934
tushki7	0:60d829a0353a	4935	/************** Bit definition for USB_COUNT4_TX_1 register *************/
tushki7	0:60d829a0353a	4936	#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 4 (high) /
tushki7	0:60d829a0353a	4937
tushki7	0:60d829a0353a	4938	/************** Bit definition for USB_COUNT5_TX_0 register *************/
tushki7	0:60d829a0353a	4939	#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 (low) /
tushki7	0:60d829a0353a	4940
tushki7	0:60d829a0353a	4941	/************** Bit definition for USB_COUNT5_TX_1 register *************/
tushki7	0:60d829a0353a	4942	#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 5 (high) /
tushki7	0:60d829a0353a	4943
tushki7	0:60d829a0353a	4944	/************** Bit definition for USB_COUNT6_TX_0 register *************/
tushki7	0:60d829a0353a	4945	#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 (low) /
tushki7	0:60d829a0353a	4946
tushki7	0:60d829a0353a	4947	/************** Bit definition for USB_COUNT6_TX_1 register *************/
tushki7	0:60d829a0353a	4948	#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 6 (high) /
tushki7	0:60d829a0353a	4949
tushki7	0:60d829a0353a	4950	/************** Bit definition for USB_COUNT7_TX_0 register *************/
tushki7	0:60d829a0353a	4951	#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 (low) /
tushki7	0:60d829a0353a	4952
tushki7	0:60d829a0353a	4953	/************** Bit definition for USB_COUNT7_TX_1 register *************/
tushki7	0:60d829a0353a	4954	#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 7 (high) /
tushki7	0:60d829a0353a	4955
tushki7	0:60d829a0353a	4956	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4957
tushki7	0:60d829a0353a	4958	/*************** Bit definition for USB_ADDR0_RX register ***************/
tushki7	0:60d829a0353a	4959	#define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 0 /
tushki7	0:60d829a0353a	4960
tushki7	0:60d829a0353a	4961	/*************** Bit definition for USB_ADDR1_RX register ***************/
tushki7	0:60d829a0353a	4962	#define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 1 /
tushki7	0:60d829a0353a	4963
tushki7	0:60d829a0353a	4964	/*************** Bit definition for USB_ADDR2_RX register ***************/
tushki7	0:60d829a0353a	4965	#define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 2 /
tushki7	0:60d829a0353a	4966
tushki7	0:60d829a0353a	4967	/*************** Bit definition for USB_ADDR3_RX register ***************/
tushki7	0:60d829a0353a	4968	#define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 3 /
tushki7	0:60d829a0353a	4969
tushki7	0:60d829a0353a	4970	/*************** Bit definition for USB_ADDR4_RX register ***************/
tushki7	0:60d829a0353a	4971	#define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 4 /
tushki7	0:60d829a0353a	4972
tushki7	0:60d829a0353a	4973	/*************** Bit definition for USB_ADDR5_RX register ***************/
tushki7	0:60d829a0353a	4974	#define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 5 /
tushki7	0:60d829a0353a	4975
tushki7	0:60d829a0353a	4976	/*************** Bit definition for USB_ADDR6_RX register ***************/
tushki7	0:60d829a0353a	4977	#define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 6 /
tushki7	0:60d829a0353a	4978
tushki7	0:60d829a0353a	4979	/*************** Bit definition for USB_ADDR7_RX register ***************/
tushki7	0:60d829a0353a	4980	#define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 7 /
tushki7	0:60d829a0353a	4981
tushki7	0:60d829a0353a	4982	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	4983
tushki7	0:60d829a0353a	4984	/*************** Bit definition for USB_COUNT0_RX register **************/
tushki7	0:60d829a0353a	4985	#define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	4986
tushki7	0:60d829a0353a	4987	#define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	4988	#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	4989	#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	4990	#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	4991	#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	4992	#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	4993
tushki7	0:60d829a0353a	4994	#define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	4995
tushki7	0:60d829a0353a	4996	/*************** Bit definition for USB_COUNT1_RX register **************/
tushki7	0:60d829a0353a	4997	#define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	4998
tushki7	0:60d829a0353a	4999	#define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	5000	#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5001	#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5002	#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5003	#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5004	#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5005
tushki7	0:60d829a0353a	5006	#define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	5007
tushki7	0:60d829a0353a	5008	/*************** Bit definition for USB_COUNT2_RX register **************/
tushki7	0:60d829a0353a	5009	#define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	5010
tushki7	0:60d829a0353a	5011	#define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	5012	#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5013	#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5014	#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5015	#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5016	#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5017
tushki7	0:60d829a0353a	5018	#define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	5019
tushki7	0:60d829a0353a	5020	/*************** Bit definition for USB_COUNT3_RX register **************/
tushki7	0:60d829a0353a	5021	#define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	5022
tushki7	0:60d829a0353a	5023	#define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	5024	#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5025	#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5026	#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5027	#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5028	#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5029
tushki7	0:60d829a0353a	5030	#define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	5031
tushki7	0:60d829a0353a	5032	/*************** Bit definition for USB_COUNT4_RX register **************/
tushki7	0:60d829a0353a	5033	#define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	5034
tushki7	0:60d829a0353a	5035	#define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	5036	#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5037	#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5038	#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5039	#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5040	#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5041
tushki7	0:60d829a0353a	5042	#define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	5043
tushki7	0:60d829a0353a	5044	/*************** Bit definition for USB_COUNT5_RX register **************/
tushki7	0:60d829a0353a	5045	#define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	5046
tushki7	0:60d829a0353a	5047	#define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	5048	#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5049	#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5050	#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5051	#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5052	#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5053
tushki7	0:60d829a0353a	5054	#define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	5055
tushki7	0:60d829a0353a	5056	/*************** Bit definition for USB_COUNT6_RX register **************/
tushki7	0:60d829a0353a	5057	#define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	5058
tushki7	0:60d829a0353a	5059	#define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	5060	#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5061	#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5062	#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5063	#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5064	#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5065
tushki7	0:60d829a0353a	5066	#define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	5067
tushki7	0:60d829a0353a	5068	/*************** Bit definition for USB_COUNT7_RX register **************/
tushki7	0:60d829a0353a	5069	#define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	5070
tushki7	0:60d829a0353a	5071	#define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	5072	#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5073	#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5074	#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5075	#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5076	#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5077
tushki7	0:60d829a0353a	5078	#define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	5079
tushki7	0:60d829a0353a	5080	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	5081
tushki7	0:60d829a0353a	5082	/************** Bit definition for USB_COUNT0_RX_0 register *************/
tushki7	0:60d829a0353a	5083	#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	5084
tushki7	0:60d829a0353a	5085	#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	5086	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5087	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5088	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5089	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5090	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5091
tushki7	0:60d829a0353a	5092	#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	5093
tushki7	0:60d829a0353a	5094	/************** Bit definition for USB_COUNT0_RX_1 register *************/
tushki7	0:60d829a0353a	5095	#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	5096
tushki7	0:60d829a0353a	5097	#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	5098	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5099	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5100	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	5101	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	5102	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	5103
tushki7	0:60d829a0353a	5104	#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	5105
tushki7	0:60d829a0353a	5106	/************** Bit definition for USB_COUNT1_RX_0 register *************/
tushki7	0:60d829a0353a	5107	#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	5108
tushki7	0:60d829a0353a	5109	#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	5110	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5111	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5112	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5113	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5114	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5115
tushki7	0:60d829a0353a	5116	#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	5117
tushki7	0:60d829a0353a	5118	/************** Bit definition for USB_COUNT1_RX_1 register *************/
tushki7	0:60d829a0353a	5119	#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	5120
tushki7	0:60d829a0353a	5121	#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	5122	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	5123	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5124	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	5125	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	5126	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	5127
tushki7	0:60d829a0353a	5128	#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	5129
tushki7	0:60d829a0353a	5130	/************** Bit definition for USB_COUNT2_RX_0 register *************/
tushki7	0:60d829a0353a	5131	#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	5132
tushki7	0:60d829a0353a	5133	#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	5134	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5135	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5136	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5137	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5138	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5139
tushki7	0:60d829a0353a	5140	#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	5141
tushki7	0:60d829a0353a	5142	/************** Bit definition for USB_COUNT2_RX_1 register *************/
tushki7	0:60d829a0353a	5143	#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	5144
tushki7	0:60d829a0353a	5145	#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	5146	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	5147	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5148	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	5149	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	5150	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	5151
tushki7	0:60d829a0353a	5152	#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	5153
tushki7	0:60d829a0353a	5154	/************** Bit definition for USB_COUNT3_RX_0 register *************/
tushki7	0:60d829a0353a	5155	#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	5156
tushki7	0:60d829a0353a	5157	#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	5158	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5159	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5160	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5161	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5162	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5163
tushki7	0:60d829a0353a	5164	#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	5165
tushki7	0:60d829a0353a	5166	/************** Bit definition for USB_COUNT3_RX_1 register *************/
tushki7	0:60d829a0353a	5167	#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	5168
tushki7	0:60d829a0353a	5169	#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	5170	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	5171	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5172	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	5173	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	5174	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	5175
tushki7	0:60d829a0353a	5176	#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	5177
tushki7	0:60d829a0353a	5178	/************** Bit definition for USB_COUNT4_RX_0 register *************/
tushki7	0:60d829a0353a	5179	#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	5180
tushki7	0:60d829a0353a	5181	#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	5182	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5183	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5184	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5185	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5186	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5187
tushki7	0:60d829a0353a	5188	#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	5189
tushki7	0:60d829a0353a	5190	/************** Bit definition for USB_COUNT4_RX_1 register *************/
tushki7	0:60d829a0353a	5191	#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	5192
tushki7	0:60d829a0353a	5193	#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	5194	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	5195	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5196	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	5197	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	5198	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	5199
tushki7	0:60d829a0353a	5200	#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	5201
tushki7	0:60d829a0353a	5202	/************** Bit definition for USB_COUNT5_RX_0 register *************/
tushki7	0:60d829a0353a	5203	#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	5204
tushki7	0:60d829a0353a	5205	#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	5206	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5207	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5208	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5209	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5210	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5211
tushki7	0:60d829a0353a	5212	#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	5213
tushki7	0:60d829a0353a	5214	/************** Bit definition for USB_COUNT5_RX_1 register *************/
tushki7	0:60d829a0353a	5215	#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	5216
tushki7	0:60d829a0353a	5217	#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	5218	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	5219	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5220	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	5221	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	5222	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	5223
tushki7	0:60d829a0353a	5224	#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	5225
tushki7	0:60d829a0353a	5226	/************* Bit definition for USB_COUNT6_RX_0 register *************/
tushki7	0:60d829a0353a	5227	#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	5228
tushki7	0:60d829a0353a	5229	#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	5230	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5231	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5232	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5233	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5234	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5235
tushki7	0:60d829a0353a	5236	#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	5237
tushki7	0:60d829a0353a	5238	/************** Bit definition for USB_COUNT6_RX_1 register *************/
tushki7	0:60d829a0353a	5239	#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	5240
tushki7	0:60d829a0353a	5241	#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	5242	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	5243	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5244	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	5245	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	5246	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	5247
tushki7	0:60d829a0353a	5248	#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	5249
tushki7	0:60d829a0353a	5250	/************* Bit definition for USB_COUNT7_RX_0 register **************/
tushki7	0:60d829a0353a	5251	#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	5252
tushki7	0:60d829a0353a	5253	#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	5254	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	5255	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	5256	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	5257	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	5258	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	5259
tushki7	0:60d829a0353a	5260	#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	5261
tushki7	0:60d829a0353a	5262	/************* Bit definition for USB_COUNT7_RX_1 register **************/
tushki7	0:60d829a0353a	5263	#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	5264
tushki7	0:60d829a0353a	5265	#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	5266	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	5267	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	5268	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	5269	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	5270	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	5271
tushki7	0:60d829a0353a	5272	#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	5273
tushki7	0:60d829a0353a	5274	/******************************************************************************/
tushki7	0:60d829a0353a	5275	/* */
tushki7	0:60d829a0353a	5276	/* Window WATCHDOG (WWDG) */
tushki7	0:60d829a0353a	5277	/* */
tushki7	0:60d829a0353a	5278	/******************************************************************************/
tushki7	0:60d829a0353a	5279
tushki7	0:60d829a0353a	5280	/***************** Bit definition for WWDG_CR register ******************/
tushki7	0:60d829a0353a	5281	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
tushki7	0:60d829a0353a	5282	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	5283	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	5284	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	5285	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	5286	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	5287	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	5288	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	5289
tushki7	0:60d829a0353a	5290	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
tushki7	0:60d829a0353a	5291
tushki7	0:60d829a0353a	5292	/***************** Bit definition for WWDG_CFR register *****************/
tushki7	0:60d829a0353a	5293	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
tushki7	0:60d829a0353a	5294	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	5295	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	5296	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	5297	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	5298	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	5299	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	5300	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	5301
tushki7	0:60d829a0353a	5302	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
tushki7	0:60d829a0353a	5303	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
tushki7	0:60d829a0353a	5304	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
tushki7	0:60d829a0353a	5305
tushki7	0:60d829a0353a	5306	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
tushki7	0:60d829a0353a	5307
tushki7	0:60d829a0353a	5308	/***************** Bit definition for WWDG_SR register ******************/
tushki7	0:60d829a0353a	5309	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
tushki7	0:60d829a0353a	5310
tushki7	0:60d829a0353a	5311	/******************************************************************************/
tushki7	0:60d829a0353a	5312	/* */
tushki7	0:60d829a0353a	5313	/* SystemTick (SysTick) */
tushki7	0:60d829a0353a	5314	/* */
tushki7	0:60d829a0353a	5315	/******************************************************************************/
tushki7	0:60d829a0353a	5316
tushki7	0:60d829a0353a	5317	/*************** Bit definition for SysTick_CTRL register ***************/
tushki7	0:60d829a0353a	5318	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
tushki7	0:60d829a0353a	5319	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
tushki7	0:60d829a0353a	5320	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
tushki7	0:60d829a0353a	5321	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
tushki7	0:60d829a0353a	5322
tushki7	0:60d829a0353a	5323	/*************** Bit definition for SysTick_LOAD register ***************/
tushki7	0:60d829a0353a	5324	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
tushki7	0:60d829a0353a	5325
tushki7	0:60d829a0353a	5326	/*************** Bit definition for SysTick_VAL register ****************/
tushki7	0:60d829a0353a	5327	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
tushki7	0:60d829a0353a	5328
tushki7	0:60d829a0353a	5329	/*************** Bit definition for SysTick_CALIB register **************/
tushki7	0:60d829a0353a	5330	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
tushki7	0:60d829a0353a	5331	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
tushki7	0:60d829a0353a	5332	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
tushki7	0:60d829a0353a	5333
tushki7	0:60d829a0353a	5334	/******************************************************************************/
tushki7	0:60d829a0353a	5335	/* */
tushki7	0:60d829a0353a	5336	/* Nested Vectored Interrupt Controller (NVIC) */
tushki7	0:60d829a0353a	5337	/* */
tushki7	0:60d829a0353a	5338	/******************************************************************************/
tushki7	0:60d829a0353a	5339
tushki7	0:60d829a0353a	5340	/**************** Bit definition for NVIC_ISER register *****************/
tushki7	0:60d829a0353a	5341	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
tushki7	0:60d829a0353a	5342	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	5343	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	5344	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	5345	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	5346	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	5347	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	5348	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	5349	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	5350	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	5351	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	5352	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	5353	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	5354	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	5355	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	5356	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	5357	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	5358	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	5359	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	5360	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	5361	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	5362	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	5363	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	5364	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	5365	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	5366	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	5367	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	5368	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	5369	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	5370	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	5371	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	5372	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	5373	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	5374
tushki7	0:60d829a0353a	5375	/**************** Bit definition for NVIC_ICER register *****************/
tushki7	0:60d829a0353a	5376	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
tushki7	0:60d829a0353a	5377	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	5378	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	5379	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	5380	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	5381	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	5382	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	5383	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	5384	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	5385	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	5386	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	5387	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	5388	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	5389	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	5390	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	5391	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	5392	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	5393	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	5394	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	5395	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	5396	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	5397	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	5398	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	5399	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	5400	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	5401	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	5402	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	5403	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	5404	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	5405	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	5406	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	5407	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	5408	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	5409
tushki7	0:60d829a0353a	5410	/**************** Bit definition for NVIC_ISPR register *****************/
tushki7	0:60d829a0353a	5411	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
tushki7	0:60d829a0353a	5412	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	5413	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	5414	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	5415	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	5416	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	5417	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	5418	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	5419	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	5420	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	5421	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	5422	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	5423	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	5424	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	5425	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	5426	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	5427	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	5428	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	5429	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	5430	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	5431	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	5432	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	5433	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	5434	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	5435	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	5436	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	5437	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	5438	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	5439	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	5440	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	5441	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	5442	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	5443	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	5444
tushki7	0:60d829a0353a	5445	/**************** Bit definition for NVIC_ICPR register *****************/
tushki7	0:60d829a0353a	5446	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
tushki7	0:60d829a0353a	5447	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	5448	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	5449	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	5450	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	5451	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	5452	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	5453	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	5454	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	5455	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	5456	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	5457	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	5458	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	5459	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	5460	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	5461	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	5462	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	5463	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	5464	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	5465	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	5466	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	5467	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	5468	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	5469	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	5470	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	5471	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	5472	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	5473	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	5474	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	5475	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	5476	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	5477	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	5478	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	5479
tushki7	0:60d829a0353a	5480	/**************** Bit definition for NVIC_IABR register *****************/
tushki7	0:60d829a0353a	5481	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
tushki7	0:60d829a0353a	5482	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	5483	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	5484	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	5485	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	5486	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	5487	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	5488	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	5489	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	5490	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	5491	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	5492	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	5493	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	5494	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	5495	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	5496	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	5497	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	5498	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	5499	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	5500	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	5501	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	5502	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	5503	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	5504	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	5505	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	5506	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	5507	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	5508	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	5509	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	5510	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	5511	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	5512	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	5513	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	5514
tushki7	0:60d829a0353a	5515	/**************** Bit definition for NVIC_PRI0 register *****************/
tushki7	0:60d829a0353a	5516	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
tushki7	0:60d829a0353a	5517	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
tushki7	0:60d829a0353a	5518	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
tushki7	0:60d829a0353a	5519	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
tushki7	0:60d829a0353a	5520
tushki7	0:60d829a0353a	5521	/**************** Bit definition for NVIC_PRI1 register *****************/
tushki7	0:60d829a0353a	5522	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
tushki7	0:60d829a0353a	5523	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
tushki7	0:60d829a0353a	5524	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
tushki7	0:60d829a0353a	5525	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
tushki7	0:60d829a0353a	5526
tushki7	0:60d829a0353a	5527	/**************** Bit definition for NVIC_PRI2 register *****************/
tushki7	0:60d829a0353a	5528	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
tushki7	0:60d829a0353a	5529	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
tushki7	0:60d829a0353a	5530	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
tushki7	0:60d829a0353a	5531	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
tushki7	0:60d829a0353a	5532
tushki7	0:60d829a0353a	5533	/**************** Bit definition for NVIC_PRI3 register *****************/
tushki7	0:60d829a0353a	5534	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
tushki7	0:60d829a0353a	5535	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
tushki7	0:60d829a0353a	5536	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
tushki7	0:60d829a0353a	5537	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
tushki7	0:60d829a0353a	5538
tushki7	0:60d829a0353a	5539	/**************** Bit definition for NVIC_PRI4 register *****************/
tushki7	0:60d829a0353a	5540	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
tushki7	0:60d829a0353a	5541	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
tushki7	0:60d829a0353a	5542	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
tushki7	0:60d829a0353a	5543	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
tushki7	0:60d829a0353a	5544
tushki7	0:60d829a0353a	5545	/**************** Bit definition for NVIC_PRI5 register *****************/
tushki7	0:60d829a0353a	5546	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
tushki7	0:60d829a0353a	5547	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
tushki7	0:60d829a0353a	5548	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
tushki7	0:60d829a0353a	5549	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
tushki7	0:60d829a0353a	5550
tushki7	0:60d829a0353a	5551	/**************** Bit definition for NVIC_PRI6 register *****************/
tushki7	0:60d829a0353a	5552	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
tushki7	0:60d829a0353a	5553	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
tushki7	0:60d829a0353a	5554	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
tushki7	0:60d829a0353a	5555	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
tushki7	0:60d829a0353a	5556
tushki7	0:60d829a0353a	5557	/**************** Bit definition for NVIC_PRI7 register *****************/
tushki7	0:60d829a0353a	5558	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
tushki7	0:60d829a0353a	5559	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
tushki7	0:60d829a0353a	5560	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
tushki7	0:60d829a0353a	5561	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
tushki7	0:60d829a0353a	5562
tushki7	0:60d829a0353a	5563	/**************** Bit definition for SCB_CPUID register *****************/
tushki7	0:60d829a0353a	5564	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
tushki7	0:60d829a0353a	5565	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
tushki7	0:60d829a0353a	5566	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
tushki7	0:60d829a0353a	5567	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
tushki7	0:60d829a0353a	5568	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
tushki7	0:60d829a0353a	5569
tushki7	0:60d829a0353a	5570	/***************** Bit definition for SCB_ICSR register *****************/
tushki7	0:60d829a0353a	5571	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
tushki7	0:60d829a0353a	5572	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
tushki7	0:60d829a0353a	5573	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
tushki7	0:60d829a0353a	5574	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
tushki7	0:60d829a0353a	5575	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
tushki7	0:60d829a0353a	5576	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
tushki7	0:60d829a0353a	5577	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
tushki7	0:60d829a0353a	5578	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
tushki7	0:60d829a0353a	5579	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
tushki7	0:60d829a0353a	5580	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
tushki7	0:60d829a0353a	5581
tushki7	0:60d829a0353a	5582	/***************** Bit definition for SCB_VTOR register *****************/
tushki7	0:60d829a0353a	5583	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
tushki7	0:60d829a0353a	5584	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
tushki7	0:60d829a0353a	5585
tushki7	0:60d829a0353a	5586	/!<************** Bit definition for SCB_AIRCR register *****************/
tushki7	0:60d829a0353a	5587	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
tushki7	0:60d829a0353a	5588	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
tushki7	0:60d829a0353a	5589	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
tushki7	0:60d829a0353a	5590
tushki7	0:60d829a0353a	5591	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
tushki7	0:60d829a0353a	5592	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	5593	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	5594	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
tushki7	0:60d829a0353a	5595
tushki7	0:60d829a0353a	5596	/* prority group configuration */
tushki7	0:60d829a0353a	5597	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
tushki7	0:60d829a0353a	5598	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
tushki7	0:60d829a0353a	5599	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
tushki7	0:60d829a0353a	5600	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
tushki7	0:60d829a0353a	5601	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
tushki7	0:60d829a0353a	5602	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
tushki7	0:60d829a0353a	5603	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
tushki7	0:60d829a0353a	5604	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
tushki7	0:60d829a0353a	5605
tushki7	0:60d829a0353a	5606	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
tushki7	0:60d829a0353a	5607	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
tushki7	0:60d829a0353a	5608
tushki7	0:60d829a0353a	5609	/***************** Bit definition for SCB_SCR register ******************/
tushki7	0:60d829a0353a	5610	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
tushki7	0:60d829a0353a	5611	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
tushki7	0:60d829a0353a	5612	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
tushki7	0:60d829a0353a	5613
tushki7	0:60d829a0353a	5614	/****************** Bit definition for SCB_CCR register *****************/
tushki7	0:60d829a0353a	5615	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
tushki7	0:60d829a0353a	5616	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
tushki7	0:60d829a0353a	5617	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
tushki7	0:60d829a0353a	5618	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
tushki7	0:60d829a0353a	5619	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
tushki7	0:60d829a0353a	5620	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
tushki7	0:60d829a0353a	5621
tushki7	0:60d829a0353a	5622	/***************** Bit definition for SCB_SHPR register ******************/
tushki7	0:60d829a0353a	5623	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
tushki7	0:60d829a0353a	5624	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
tushki7	0:60d829a0353a	5625	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
tushki7	0:60d829a0353a	5626	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
tushki7	0:60d829a0353a	5627
tushki7	0:60d829a0353a	5628	/**************** Bit definition for SCB_SHCSR register *****************/
tushki7	0:60d829a0353a	5629	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
tushki7	0:60d829a0353a	5630	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
tushki7	0:60d829a0353a	5631	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
tushki7	0:60d829a0353a	5632	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
tushki7	0:60d829a0353a	5633	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
tushki7	0:60d829a0353a	5634	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
tushki7	0:60d829a0353a	5635	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
tushki7	0:60d829a0353a	5636	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
tushki7	0:60d829a0353a	5637	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
tushki7	0:60d829a0353a	5638	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
tushki7	0:60d829a0353a	5639	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
tushki7	0:60d829a0353a	5640	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
tushki7	0:60d829a0353a	5641	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
tushki7	0:60d829a0353a	5642	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
tushki7	0:60d829a0353a	5643
tushki7	0:60d829a0353a	5644	/***************** Bit definition for SCB_CFSR register *****************/
tushki7	0:60d829a0353a	5645	/!< MFSR /
tushki7	0:60d829a0353a	5646	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
tushki7	0:60d829a0353a	5647	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
tushki7	0:60d829a0353a	5648	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
tushki7	0:60d829a0353a	5649	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
tushki7	0:60d829a0353a	5650	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
tushki7	0:60d829a0353a	5651	/!< BFSR /
tushki7	0:60d829a0353a	5652	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
tushki7	0:60d829a0353a	5653	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
tushki7	0:60d829a0353a	5654	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
tushki7	0:60d829a0353a	5655	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
tushki7	0:60d829a0353a	5656	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
tushki7	0:60d829a0353a	5657	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
tushki7	0:60d829a0353a	5658	/!< UFSR /
tushki7	0:60d829a0353a	5659	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to excecute an undefined instruction /
tushki7	0:60d829a0353a	5660	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
tushki7	0:60d829a0353a	5661	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
tushki7	0:60d829a0353a	5662	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
tushki7	0:60d829a0353a	5663	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
tushki7	0:60d829a0353a	5664	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
tushki7	0:60d829a0353a	5665
tushki7	0:60d829a0353a	5666	/***************** Bit definition for SCB_HFSR register *****************/
tushki7	0:60d829a0353a	5667	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occures because of vector table read on exception processing /
tushki7	0:60d829a0353a	5668	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
tushki7	0:60d829a0353a	5669	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
tushki7	0:60d829a0353a	5670
tushki7	0:60d829a0353a	5671	/***************** Bit definition for SCB_DFSR register *****************/
tushki7	0:60d829a0353a	5672	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
tushki7	0:60d829a0353a	5673	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
tushki7	0:60d829a0353a	5674	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
tushki7	0:60d829a0353a	5675	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
tushki7	0:60d829a0353a	5676	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
tushki7	0:60d829a0353a	5677
tushki7	0:60d829a0353a	5678	/***************** Bit definition for SCB_MMFAR register ****************/
tushki7	0:60d829a0353a	5679	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
tushki7	0:60d829a0353a	5680
tushki7	0:60d829a0353a	5681	/***************** Bit definition for SCB_BFAR register *****************/
tushki7	0:60d829a0353a	5682	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
tushki7	0:60d829a0353a	5683
tushki7	0:60d829a0353a	5684	/***************** Bit definition for SCB_afsr register *****************/
tushki7	0:60d829a0353a	5685	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
tushki7	0:60d829a0353a	5686	/**
tushki7	0:60d829a0353a	5687	* @}
tushki7	0:60d829a0353a	5688	*/
tushki7	0:60d829a0353a	5689
tushki7	0:60d829a0353a	5690	/**
tushki7	0:60d829a0353a	5691	* @}
tushki7	0:60d829a0353a	5692	*/
tushki7	0:60d829a0353a	5693	/** @addtogroup Exported_macro
tushki7	0:60d829a0353a	5694	* @{
tushki7	0:60d829a0353a	5695	*/
tushki7	0:60d829a0353a	5696
tushki7	0:60d829a0353a	5697	/**************************** ADC Instances *******************************/
tushki7	0:60d829a0353a	5698	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
tushki7	0:60d829a0353a	5699
tushki7	0:60d829a0353a	5700	/****************************** COMP Instances ****************************/
tushki7	0:60d829a0353a	5701	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
tushki7	0:60d829a0353a	5702	((INSTANCE) == COMP2))
tushki7	0:60d829a0353a	5703
tushki7	0:60d829a0353a	5704	/**************************** CRC Instances *******************************/
tushki7	0:60d829a0353a	5705	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
tushki7	0:60d829a0353a	5706
tushki7	0:60d829a0353a	5707	/**************************** DAC Instances *******************************/
tushki7	0:60d829a0353a	5708	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
tushki7	0:60d829a0353a	5709
tushki7	0:60d829a0353a	5710	/**************************** DMA Instances *******************************/
tushki7	0:60d829a0353a	5711	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
tushki7	0:60d829a0353a	5712	((INSTANCE) == DMA1_Channel2) \|\| \
tushki7	0:60d829a0353a	5713	((INSTANCE) == DMA1_Channel3) \|\| \
tushki7	0:60d829a0353a	5714	((INSTANCE) == DMA1_Channel4) \|\| \
tushki7	0:60d829a0353a	5715	((INSTANCE) == DMA1_Channel5) \|\| \
tushki7	0:60d829a0353a	5716	((INSTANCE) == DMA1_Channel6) \|\| \
tushki7	0:60d829a0353a	5717	((INSTANCE) == DMA1_Channel7) \|\| \
tushki7	0:60d829a0353a	5718	((INSTANCE) == DMA2_Channel1) \|\| \
tushki7	0:60d829a0353a	5719	((INSTANCE) == DMA2_Channel2) \|\| \
tushki7	0:60d829a0353a	5720	((INSTANCE) == DMA2_Channel3) \|\| \
tushki7	0:60d829a0353a	5721	((INSTANCE) == DMA2_Channel4) \|\| \
tushki7	0:60d829a0353a	5722	((INSTANCE) == DMA2_Channel5))
tushki7	0:60d829a0353a	5723
tushki7	0:60d829a0353a	5724	/***************************** GPIO Instances *****************************/
tushki7	0:60d829a0353a	5725	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
tushki7	0:60d829a0353a	5726	((INSTANCE) == GPIOB) \|\| \
tushki7	0:60d829a0353a	5727	((INSTANCE) == GPIOC) \|\| \
tushki7	0:60d829a0353a	5728	((INSTANCE) == GPIOD) \|\| \
tushki7	0:60d829a0353a	5729	((INSTANCE) == GPIOE) \|\| \
tushki7	0:60d829a0353a	5730	((INSTANCE) == GPIOF) \|\| \
tushki7	0:60d829a0353a	5731	((INSTANCE) == GPIOG) \|\| \
tushki7	0:60d829a0353a	5732	((INSTANCE) == GPIOH))
tushki7	0:60d829a0353a	5733
tushki7	0:60d829a0353a	5734	/************************** GPIO Lock Instances ***************************/
tushki7	0:60d829a0353a	5735	/* On L1, all GPIO Bank support the Lock mechanism */
tushki7	0:60d829a0353a	5736	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
tushki7	0:60d829a0353a	5737
tushki7	0:60d829a0353a	5738	/****************************** I2C Instances *****************************/
tushki7	0:60d829a0353a	5739	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
tushki7	0:60d829a0353a	5740	((INSTANCE) == I2C2))
tushki7	0:60d829a0353a	5741
tushki7	0:60d829a0353a	5742	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
tushki7	0:60d829a0353a	5743	((INSTANCE) == SPI2) \|\| \
tushki7	0:60d829a0353a	5744	((INSTANCE) == SPI3))
tushki7	0:60d829a0353a	5745	/**************************** IWDG Instances ******************************/
tushki7	0:60d829a0353a	5746	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
tushki7	0:60d829a0353a	5747
tushki7	0:60d829a0353a	5748	/**************************** OPAMP Instances *****************************/
tushki7	0:60d829a0353a	5749	#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) \|\| \
tushki7	0:60d829a0353a	5750	((INSTANCE) == OPAMP2))
tushki7	0:60d829a0353a	5751
tushki7	0:60d829a0353a	5752	/**************************** RTC Instances *******************************/
tushki7	0:60d829a0353a	5753	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
tushki7	0:60d829a0353a	5754
tushki7	0:60d829a0353a	5755	/****************************** SPI Instances *****************************/
tushki7	0:60d829a0353a	5756	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
tushki7	0:60d829a0353a	5757	((INSTANCE) == SPI2) \|\| \
tushki7	0:60d829a0353a	5758	((INSTANCE) == SPI3))
tushki7	0:60d829a0353a	5759
tushki7	0:60d829a0353a	5760	/**************************** TIM Instances *******************************/
tushki7	0:60d829a0353a	5761	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5762	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5763	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5764	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5765	((INSTANCE) == TIM6) \|\| \
tushki7	0:60d829a0353a	5766	((INSTANCE) == TIM7) \|\| \
tushki7	0:60d829a0353a	5767	((INSTANCE) == TIM9) \|\| \
tushki7	0:60d829a0353a	5768	((INSTANCE) == TIM10) \|\| \
tushki7	0:60d829a0353a	5769	((INSTANCE) == TIM11))
tushki7	0:60d829a0353a	5770
tushki7	0:60d829a0353a	5771	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5772	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5773	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5774	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5775	((INSTANCE) == TIM9) \|\| \
tushki7	0:60d829a0353a	5776	((INSTANCE) == TIM10) \|\| \
tushki7	0:60d829a0353a	5777	((INSTANCE) == TIM11))
tushki7	0:60d829a0353a	5778
tushki7	0:60d829a0353a	5779	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5780	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5781	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5782	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5783	((INSTANCE) == TIM9))
tushki7	0:60d829a0353a	5784
tushki7	0:60d829a0353a	5785	#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5786	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5787	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5788	((INSTANCE) == TIM5))
tushki7	0:60d829a0353a	5789
tushki7	0:60d829a0353a	5790	#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5791	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5792	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5793	((INSTANCE) == TIM5))
tushki7	0:60d829a0353a	5794
tushki7	0:60d829a0353a	5795	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5796	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5797	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5798	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5799	((INSTANCE) == TIM9))
tushki7	0:60d829a0353a	5800
tushki7	0:60d829a0353a	5801	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5802	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5803	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5804	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5805	((INSTANCE) == TIM9) \|\| \
tushki7	0:60d829a0353a	5806	((INSTANCE) == TIM10) \|\| \
tushki7	0:60d829a0353a	5807	((INSTANCE) == TIM11))
tushki7	0:60d829a0353a	5808
tushki7	0:60d829a0353a	5809	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5810	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5811	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5812	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5813	((INSTANCE) == TIM9))
tushki7	0:60d829a0353a	5814
tushki7	0:60d829a0353a	5815	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5816	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5817	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5818	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5819	((INSTANCE) == TIM9))
tushki7	0:60d829a0353a	5820
tushki7	0:60d829a0353a	5821	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5822	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5823	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5824
tushki7	0:60d829a0353a	5825	#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5826	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5827	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5828	((INSTANCE) == TIM5))
tushki7	0:60d829a0353a	5829
tushki7	0:60d829a0353a	5830	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5831	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5832	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5833	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5834	((INSTANCE) == TIM6) \|\| \
tushki7	0:60d829a0353a	5835	((INSTANCE) == TIM7) \|\| \
tushki7	0:60d829a0353a	5836	((INSTANCE) == TIM9))
tushki7	0:60d829a0353a	5837
tushki7	0:60d829a0353a	5838	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5839	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5840	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5841	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5842	((INSTANCE) == TIM9))
tushki7	0:60d829a0353a	5843
tushki7	0:60d829a0353a	5844	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
tushki7	0:60d829a0353a	5845
tushki7	0:60d829a0353a	5846	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5847	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5848	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5849	((INSTANCE) == TIM5))
tushki7	0:60d829a0353a	5850
tushki7	0:60d829a0353a	5851	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
tushki7	0:60d829a0353a	5852	((((INSTANCE) == TIM2) && \
tushki7	0:60d829a0353a	5853	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5854	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5855	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	5856	((CHANNEL) == TIM_CHANNEL_4))) \
tushki7	0:60d829a0353a	5857	\|\| \
tushki7	0:60d829a0353a	5858	(((INSTANCE) == TIM3) && \
tushki7	0:60d829a0353a	5859	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5860	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5861	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	5862	((CHANNEL) == TIM_CHANNEL_4))) \
tushki7	0:60d829a0353a	5863	\|\| \
tushki7	0:60d829a0353a	5864	(((INSTANCE) == TIM4) && \
tushki7	0:60d829a0353a	5865	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5866	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5867	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	5868	((CHANNEL) == TIM_CHANNEL_4))) \
tushki7	0:60d829a0353a	5869	\|\| \
tushki7	0:60d829a0353a	5870	(((INSTANCE) == TIM5) && \
tushki7	0:60d829a0353a	5871	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5872	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5873	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	5874	((CHANNEL) == TIM_CHANNEL_4))) \
tushki7	0:60d829a0353a	5875	\|\| \
tushki7	0:60d829a0353a	5876	(((INSTANCE) == TIM9) && \
tushki7	0:60d829a0353a	5877	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5878	((CHANNEL) == TIM_CHANNEL_2))) \
tushki7	0:60d829a0353a	5879	\|\| \
tushki7	0:60d829a0353a	5880	(((INSTANCE) == TIM10) && \
tushki7	0:60d829a0353a	5881	(((CHANNEL) == TIM_CHANNEL_1))) \
tushki7	0:60d829a0353a	5882	\|\| \
tushki7	0:60d829a0353a	5883	(((INSTANCE) == TIM11) && \
tushki7	0:60d829a0353a	5884	(((CHANNEL) == TIM_CHANNEL_1))))
tushki7	0:60d829a0353a	5885
tushki7	0:60d829a0353a	5886	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5887	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5888	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5889	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5890	((INSTANCE) == TIM9) \|\| \
tushki7	0:60d829a0353a	5891	((INSTANCE) == TIM10) \|\| \
tushki7	0:60d829a0353a	5892	((INSTANCE) == TIM11))
tushki7	0:60d829a0353a	5893
tushki7	0:60d829a0353a	5894	#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5895	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5896	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5897	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5898	((INSTANCE) == TIM6) \|\| \
tushki7	0:60d829a0353a	5899	((INSTANCE) == TIM7))
tushki7	0:60d829a0353a	5900
tushki7	0:60d829a0353a	5901	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5902	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5903	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5904	((INSTANCE) == TIM5))
tushki7	0:60d829a0353a	5905
tushki7	0:60d829a0353a	5906	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5907	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5908	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5909	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5910	((INSTANCE) == TIM9))
tushki7	0:60d829a0353a	5911
tushki7	0:60d829a0353a	5912	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5913	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5914	((INSTANCE) == TIM4) \|\| \
tushki7	0:60d829a0353a	5915	((INSTANCE) == TIM5) \|\| \
tushki7	0:60d829a0353a	5916	((INSTANCE) == TIM9))
tushki7	0:60d829a0353a	5917
tushki7	0:60d829a0353a	5918	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5919	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5920	((INSTANCE) == TIM9) \|\| \
tushki7	0:60d829a0353a	5921	((INSTANCE) == TIM10) \|\| \
tushki7	0:60d829a0353a	5922	((INSTANCE) == TIM11))
tushki7	0:60d829a0353a	5923
tushki7	0:60d829a0353a	5924	/****************** USART Instances : Synchronous mode ********************/
tushki7	0:60d829a0353a	5925	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5926	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5927	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5928
tushki7	0:60d829a0353a	5929	/****************** UART Instances : Asynchronous mode ********************/
tushki7	0:60d829a0353a	5930	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5931	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5932	((INSTANCE) == USART3) \|\| \
tushki7	0:60d829a0353a	5933	((INSTANCE) == UART4) \|\| \
tushki7	0:60d829a0353a	5934	((INSTANCE) == UART5))
tushki7	0:60d829a0353a	5935
tushki7	0:60d829a0353a	5936	/****************** UART Instances : Half-Duplex mode ********************/
tushki7	0:60d829a0353a	5937	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5938	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5939	((INSTANCE) == USART3) \|\| \
tushki7	0:60d829a0353a	5940	((INSTANCE) == UART4) \|\| \
tushki7	0:60d829a0353a	5941	((INSTANCE) == UART5))
tushki7	0:60d829a0353a	5942
tushki7	0:60d829a0353a	5943	/****************** UART Instances : LIN mode ********************/
tushki7	0:60d829a0353a	5944	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5945	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5946	((INSTANCE) == USART3) \|\| \
tushki7	0:60d829a0353a	5947	((INSTANCE) == UART4) \|\| \
tushki7	0:60d829a0353a	5948	((INSTANCE) == UART5))
tushki7	0:60d829a0353a	5949
tushki7	0:60d829a0353a	5950	/**************** UART Instances : Hardware Flow control ******************/
tushki7	0:60d829a0353a	5951	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5952	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5953	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5954
tushki7	0:60d829a0353a	5955	/******************* UART Instances : Smard card mode *********************/
tushki7	0:60d829a0353a	5956	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5957	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5958	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5959
tushki7	0:60d829a0353a	5960	/********************* UART Instances : IRDA mode *************************/
tushki7	0:60d829a0353a	5961	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5962	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5963	((INSTANCE) == USART3) \|\| \
tushki7	0:60d829a0353a	5964	((INSTANCE) == UART4) \|\| \
tushki7	0:60d829a0353a	5965	((INSTANCE) == UART5))
tushki7	0:60d829a0353a	5966
tushki7	0:60d829a0353a	5967	/*************** UART Instances : Multi-Processor mode ********************/
tushki7	0:60d829a0353a	5968	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5969	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5970	((INSTANCE) == USART3) \|\| \
tushki7	0:60d829a0353a	5971	((INSTANCE) == UART4) \|\| \
tushki7	0:60d829a0353a	5972	((INSTANCE) == UART5))
tushki7	0:60d829a0353a	5973
tushki7	0:60d829a0353a	5974	/**************************** WWDG Instances ******************************/
tushki7	0:60d829a0353a	5975	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
tushki7	0:60d829a0353a	5976
tushki7	0:60d829a0353a	5977
tushki7	0:60d829a0353a	5978	/**************************** LCD Instances ******************************/
tushki7	0:60d829a0353a	5979	#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
tushki7	0:60d829a0353a	5980
tushki7	0:60d829a0353a	5981	/**************************** USB Instances ******************************/
tushki7	0:60d829a0353a	5982	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
tushki7	0:60d829a0353a	5983
tushki7	0:60d829a0353a	5984	/**
tushki7	0:60d829a0353a	5985	* @}
tushki7	0:60d829a0353a	5986	*/
tushki7	0:60d829a0353a	5987
tushki7	0:60d829a0353a	5988	/******************************************************************************/
tushki7	0:60d829a0353a	5989	/* For a painless codes migration between the STM32L1xx device product */
tushki7	0:60d829a0353a	5990	/* lines, the aliases defined below are put in place to overcome the */
tushki7	0:60d829a0353a	5991	/* differences in the interrupt handlers and IRQn definitions. */
tushki7	0:60d829a0353a	5992	/* No need to update developed interrupt code when moving across */
tushki7	0:60d829a0353a	5993	/* product lines within the same STM32L1 Family */
tushki7	0:60d829a0353a	5994	/******************************************************************************/
tushki7	0:60d829a0353a	5995
tushki7	0:60d829a0353a	5996	/* Aliases for __IRQn */
tushki7	0:60d829a0353a	5997
tushki7	0:60d829a0353a	5998	/* Aliases for __IRQHandler */
tushki7	0:60d829a0353a	5999
tushki7	0:60d829a0353a	6000	/**
tushki7	0:60d829a0353a	6001	* @}
tushki7	0:60d829a0353a	6002	*/
tushki7	0:60d829a0353a	6003
tushki7	0:60d829a0353a	6004	/**
tushki7	0:60d829a0353a	6005	* @}
tushki7	0:60d829a0353a	6006	*/
tushki7	0:60d829a0353a	6007
tushki7	0:60d829a0353a	6008	#ifdef __cplusplus
tushki7	0:60d829a0353a	6009	}
tushki7	0:60d829a0353a	6010	#endif /* __cplusplus */
tushki7	0:60d829a0353a	6011
tushki7	0:60d829a0353a	6012	#endif /* __STM32L152xE_H */
tushki7	0:60d829a0353a	6013
tushki7	0:60d829a0353a	6014
tushki7	0:60d829a0353a	6015
tushki7	0:60d829a0353a	6016	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_NUCLEO_L152RE/stm32l152xe.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

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