FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

Users » tushki7 » Code » FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_NUCLEO_F103RB/stm32f103xb.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1	/**
tushki7	0:60d829a0353a	2	******************************************************************************
tushki7	0:60d829a0353a	3	* @file stm32f103xb.h
tushki7	0:60d829a0353a	4	* @author MCD Application Team
tushki7	0:60d829a0353a	5	* @version V4.0.0
tushki7	0:60d829a0353a	6	* @date 16-December-2014
tushki7	0:60d829a0353a	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
tushki7	0:60d829a0353a	8	* This file contains all the peripheral register's definitions, bits
tushki7	0:60d829a0353a	9	* definitions and memory mapping for STM32F1xx devices.
tushki7	0:60d829a0353a	10	*
tushki7	0:60d829a0353a	11	* This file contains:
tushki7	0:60d829a0353a	12	* - Data structures and the address mapping for all peripherals
tushki7	0:60d829a0353a	13	* - Peripheral's registers declarations and bits definition
tushki7	0:60d829a0353a	14	* - Macros to access peripherals registers hardware
tushki7	0:60d829a0353a	15	*
tushki7	0:60d829a0353a	16	******************************************************************************
tushki7	0:60d829a0353a	17	* @attention
tushki7	0:60d829a0353a	18	*
tushki7	0:60d829a0353a	19	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
tushki7	0:60d829a0353a	20	*
tushki7	0:60d829a0353a	21	* Redistribution and use in source and binary forms, with or without modification,
tushki7	0:60d829a0353a	22	* are permitted provided that the following conditions are met:
tushki7	0:60d829a0353a	23	* 1. Redistributions of source code must retain the above copyright notice,
tushki7	0:60d829a0353a	24	* this list of conditions and the following disclaimer.
tushki7	0:60d829a0353a	25	* 2. Redistributions in binary form must reproduce the above copyright notice,
tushki7	0:60d829a0353a	26	* this list of conditions and the following disclaimer in the documentation
tushki7	0:60d829a0353a	27	* and/or other materials provided with the distribution.
tushki7	0:60d829a0353a	28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
tushki7	0:60d829a0353a	29	* may be used to endorse or promote products derived from this software
tushki7	0:60d829a0353a	30	* without specific prior written permission.
tushki7	0:60d829a0353a	31	*
tushki7	0:60d829a0353a	32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7	0:60d829a0353a	33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7	0:60d829a0353a	34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7	0:60d829a0353a	35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
tushki7	0:60d829a0353a	36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tushki7	0:60d829a0353a	37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
tushki7	0:60d829a0353a	38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
tushki7	0:60d829a0353a	39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
tushki7	0:60d829a0353a	40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
tushki7	0:60d829a0353a	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7	0:60d829a0353a	42	*
tushki7	0:60d829a0353a	43	******************************************************************************
tushki7	0:60d829a0353a	44	*/
tushki7	0:60d829a0353a	45
tushki7	0:60d829a0353a	46
tushki7	0:60d829a0353a	47	/** @addtogroup CMSIS
tushki7	0:60d829a0353a	48	* @{
tushki7	0:60d829a0353a	49	*/
tushki7	0:60d829a0353a	50
tushki7	0:60d829a0353a	51	/** @addtogroup stm32f103xb
tushki7	0:60d829a0353a	52	* @{
tushki7	0:60d829a0353a	53	*/
tushki7	0:60d829a0353a	54
tushki7	0:60d829a0353a	55	#ifndef __STM32F103xB_H
tushki7	0:60d829a0353a	56	#define __STM32F103xB_H
tushki7	0:60d829a0353a	57
tushki7	0:60d829a0353a	58	#ifdef __cplusplus
tushki7	0:60d829a0353a	59	extern "C" {
tushki7	0:60d829a0353a	60	#endif
tushki7	0:60d829a0353a	61
tushki7	0:60d829a0353a	62	/** @addtogroup Configuration_section_for_CMSIS
tushki7	0:60d829a0353a	63	* @{
tushki7	0:60d829a0353a	64	*/
tushki7	0:60d829a0353a	65	/**
tushki7	0:60d829a0353a	66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
tushki7	0:60d829a0353a	67	*/
tushki7	0:60d829a0353a	68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
tushki7	0:60d829a0353a	69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
tushki7	0:60d829a0353a	70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
tushki7	0:60d829a0353a	71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
tushki7	0:60d829a0353a	72
tushki7	0:60d829a0353a	73	/**
tushki7	0:60d829a0353a	74	* @}
tushki7	0:60d829a0353a	75	*/
tushki7	0:60d829a0353a	76
tushki7	0:60d829a0353a	77	/** @addtogroup Peripheral_interrupt_number_definition
tushki7	0:60d829a0353a	78	* @{
tushki7	0:60d829a0353a	79	*/
tushki7	0:60d829a0353a	80
tushki7	0:60d829a0353a	81	/**
tushki7	0:60d829a0353a	82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
tushki7	0:60d829a0353a	83	* in @ref Library_configuration_section
tushki7	0:60d829a0353a	84	*/
tushki7	0:60d829a0353a	85
tushki7	0:60d829a0353a	86	/!< Interrupt Number Definition /
tushki7	0:60d829a0353a	87	typedef enum
tushki7	0:60d829a0353a	88	{
tushki7	0:60d829a0353a	89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
tushki7	0:60d829a0353a	90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
tushki7	0:60d829a0353a	91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
tushki7	0:60d829a0353a	92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
tushki7	0:60d829a0353a	93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
tushki7	0:60d829a0353a	94	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
tushki7	0:60d829a0353a	95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
tushki7	0:60d829a0353a	96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
tushki7	0:60d829a0353a	97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
tushki7	0:60d829a0353a	98
tushki7	0:60d829a0353a	99	/**** STM32 specific Interrupt Numbers *******************************************************/
tushki7	0:60d829a0353a	100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
tushki7	0:60d829a0353a	101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
tushki7	0:60d829a0353a	102	TAMPER_IRQn = 2, /!< Tamper Interrupt /
tushki7	0:60d829a0353a	103	RTC_IRQn = 3, /!< RTC global Interrupt /
tushki7	0:60d829a0353a	104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
tushki7	0:60d829a0353a	105	RCC_IRQn = 5, /!< RCC global Interrupt /
tushki7	0:60d829a0353a	106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
tushki7	0:60d829a0353a	107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
tushki7	0:60d829a0353a	108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
tushki7	0:60d829a0353a	109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
tushki7	0:60d829a0353a	110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
tushki7	0:60d829a0353a	111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
tushki7	0:60d829a0353a	112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
tushki7	0:60d829a0353a	113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
tushki7	0:60d829a0353a	114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
tushki7	0:60d829a0353a	115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
tushki7	0:60d829a0353a	116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
tushki7	0:60d829a0353a	117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
tushki7	0:60d829a0353a	118	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
tushki7	0:60d829a0353a	119	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
tushki7	0:60d829a0353a	120	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
tushki7	0:60d829a0353a	121	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
tushki7	0:60d829a0353a	122	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
tushki7	0:60d829a0353a	123	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
tushki7	0:60d829a0353a	124	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
tushki7	0:60d829a0353a	125	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
tushki7	0:60d829a0353a	126	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
tushki7	0:60d829a0353a	127	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
tushki7	0:60d829a0353a	128	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
tushki7	0:60d829a0353a	129	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
tushki7	0:60d829a0353a	130	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
tushki7	0:60d829a0353a	131	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
tushki7	0:60d829a0353a	132	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
tushki7	0:60d829a0353a	133	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
tushki7	0:60d829a0353a	134	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
tushki7	0:60d829a0353a	135	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
tushki7	0:60d829a0353a	136	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
tushki7	0:60d829a0353a	137	USART1_IRQn = 37, /!< USART1 global Interrupt /
tushki7	0:60d829a0353a	138	USART2_IRQn = 38, /!< USART2 global Interrupt /
tushki7	0:60d829a0353a	139	USART3_IRQn = 39, /!< USART3 global Interrupt /
tushki7	0:60d829a0353a	140	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
tushki7	0:60d829a0353a	141	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
tushki7	0:60d829a0353a	142	USBWakeUp_IRQn = 42, /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
tushki7	0:60d829a0353a	143	} IRQn_Type;
tushki7	0:60d829a0353a	144
tushki7	0:60d829a0353a	145
tushki7	0:60d829a0353a	146	/**
tushki7	0:60d829a0353a	147	* @}
tushki7	0:60d829a0353a	148	*/
tushki7	0:60d829a0353a	149
tushki7	0:60d829a0353a	150	#include "core_cm3.h"
tushki7	0:60d829a0353a	151	#include "system_stm32f1xx.h"
tushki7	0:60d829a0353a	152	#include <stdint.h>
tushki7	0:60d829a0353a	153
tushki7	0:60d829a0353a	154	/** @addtogroup Peripheral_registers_structures
tushki7	0:60d829a0353a	155	* @{
tushki7	0:60d829a0353a	156	*/
tushki7	0:60d829a0353a	157
tushki7	0:60d829a0353a	158	/**
tushki7	0:60d829a0353a	159	* @brief Analog to Digital Converter
tushki7	0:60d829a0353a	160	*/
tushki7	0:60d829a0353a	161
tushki7	0:60d829a0353a	162	typedef struct
tushki7	0:60d829a0353a	163	{
tushki7	0:60d829a0353a	164	__IO uint32_t SR;
tushki7	0:60d829a0353a	165	__IO uint32_t CR1;
tushki7	0:60d829a0353a	166	__IO uint32_t CR2;
tushki7	0:60d829a0353a	167	__IO uint32_t SMPR1;
tushki7	0:60d829a0353a	168	__IO uint32_t SMPR2;
tushki7	0:60d829a0353a	169	__IO uint32_t JOFR1;
tushki7	0:60d829a0353a	170	__IO uint32_t JOFR2;
tushki7	0:60d829a0353a	171	__IO uint32_t JOFR3;
tushki7	0:60d829a0353a	172	__IO uint32_t JOFR4;
tushki7	0:60d829a0353a	173	__IO uint32_t HTR;
tushki7	0:60d829a0353a	174	__IO uint32_t LTR;
tushki7	0:60d829a0353a	175	__IO uint32_t SQR1;
tushki7	0:60d829a0353a	176	__IO uint32_t SQR2;
tushki7	0:60d829a0353a	177	__IO uint32_t SQR3;
tushki7	0:60d829a0353a	178	__IO uint32_t JSQR;
tushki7	0:60d829a0353a	179	__IO uint32_t JDR1;
tushki7	0:60d829a0353a	180	__IO uint32_t JDR2;
tushki7	0:60d829a0353a	181	__IO uint32_t JDR3;
tushki7	0:60d829a0353a	182	__IO uint32_t JDR4;
tushki7	0:60d829a0353a	183	__IO uint32_t DR;
tushki7	0:60d829a0353a	184	} ADC_TypeDef;
tushki7	0:60d829a0353a	185
tushki7	0:60d829a0353a	186	/**
tushki7	0:60d829a0353a	187	* @brief Backup Registers
tushki7	0:60d829a0353a	188	*/
tushki7	0:60d829a0353a	189
tushki7	0:60d829a0353a	190	typedef struct
tushki7	0:60d829a0353a	191	{
tushki7	0:60d829a0353a	192	uint32_t RESERVED0;
tushki7	0:60d829a0353a	193	__IO uint32_t DR1;
tushki7	0:60d829a0353a	194	__IO uint32_t DR2;
tushki7	0:60d829a0353a	195	__IO uint32_t DR3;
tushki7	0:60d829a0353a	196	__IO uint32_t DR4;
tushki7	0:60d829a0353a	197	__IO uint32_t DR5;
tushki7	0:60d829a0353a	198	__IO uint32_t DR6;
tushki7	0:60d829a0353a	199	__IO uint32_t DR7;
tushki7	0:60d829a0353a	200	__IO uint32_t DR8;
tushki7	0:60d829a0353a	201	__IO uint32_t DR9;
tushki7	0:60d829a0353a	202	__IO uint32_t DR10;
tushki7	0:60d829a0353a	203	__IO uint32_t RTCCR;
tushki7	0:60d829a0353a	204	__IO uint32_t CR;
tushki7	0:60d829a0353a	205	__IO uint32_t CSR;
tushki7	0:60d829a0353a	206	} BKP_TypeDef;
tushki7	0:60d829a0353a	207
tushki7	0:60d829a0353a	208	/**
tushki7	0:60d829a0353a	209	* @brief Controller Area Network TxMailBox
tushki7	0:60d829a0353a	210	*/
tushki7	0:60d829a0353a	211
tushki7	0:60d829a0353a	212	typedef struct
tushki7	0:60d829a0353a	213	{
tushki7	0:60d829a0353a	214	__IO uint32_t TIR;
tushki7	0:60d829a0353a	215	__IO uint32_t TDTR;
tushki7	0:60d829a0353a	216	__IO uint32_t TDLR;
tushki7	0:60d829a0353a	217	__IO uint32_t TDHR;
tushki7	0:60d829a0353a	218	} CAN_TxMailBox_TypeDef;
tushki7	0:60d829a0353a	219
tushki7	0:60d829a0353a	220	/**
tushki7	0:60d829a0353a	221	* @brief Controller Area Network FIFOMailBox
tushki7	0:60d829a0353a	222	*/
tushki7	0:60d829a0353a	223
tushki7	0:60d829a0353a	224	typedef struct
tushki7	0:60d829a0353a	225	{
tushki7	0:60d829a0353a	226	__IO uint32_t RIR;
tushki7	0:60d829a0353a	227	__IO uint32_t RDTR;
tushki7	0:60d829a0353a	228	__IO uint32_t RDLR;
tushki7	0:60d829a0353a	229	__IO uint32_t RDHR;
tushki7	0:60d829a0353a	230	} CAN_FIFOMailBox_TypeDef;
tushki7	0:60d829a0353a	231
tushki7	0:60d829a0353a	232	/**
tushki7	0:60d829a0353a	233	* @brief Controller Area Network FilterRegister
tushki7	0:60d829a0353a	234	*/
tushki7	0:60d829a0353a	235
tushki7	0:60d829a0353a	236	typedef struct
tushki7	0:60d829a0353a	237	{
tushki7	0:60d829a0353a	238	__IO uint32_t FR1;
tushki7	0:60d829a0353a	239	__IO uint32_t FR2;
tushki7	0:60d829a0353a	240	} CAN_FilterRegister_TypeDef;
tushki7	0:60d829a0353a	241
tushki7	0:60d829a0353a	242	/**
tushki7	0:60d829a0353a	243	* @brief Controller Area Network
tushki7	0:60d829a0353a	244	*/
tushki7	0:60d829a0353a	245
tushki7	0:60d829a0353a	246	typedef struct
tushki7	0:60d829a0353a	247	{
tushki7	0:60d829a0353a	248	__IO uint32_t MCR;
tushki7	0:60d829a0353a	249	__IO uint32_t MSR;
tushki7	0:60d829a0353a	250	__IO uint32_t TSR;
tushki7	0:60d829a0353a	251	__IO uint32_t RF0R;
tushki7	0:60d829a0353a	252	__IO uint32_t RF1R;
tushki7	0:60d829a0353a	253	__IO uint32_t IER;
tushki7	0:60d829a0353a	254	__IO uint32_t ESR;
tushki7	0:60d829a0353a	255	__IO uint32_t BTR;
tushki7	0:60d829a0353a	256	uint32_t RESERVED0[88];
tushki7	0:60d829a0353a	257	CAN_TxMailBox_TypeDef sTxMailBox[3];
tushki7	0:60d829a0353a	258	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
tushki7	0:60d829a0353a	259	uint32_t RESERVED1[12];
tushki7	0:60d829a0353a	260	__IO uint32_t FMR;
tushki7	0:60d829a0353a	261	__IO uint32_t FM1R;
tushki7	0:60d829a0353a	262	uint32_t RESERVED2;
tushki7	0:60d829a0353a	263	__IO uint32_t FS1R;
tushki7	0:60d829a0353a	264	uint32_t RESERVED3;
tushki7	0:60d829a0353a	265	__IO uint32_t FFA1R;
tushki7	0:60d829a0353a	266	uint32_t RESERVED4;
tushki7	0:60d829a0353a	267	__IO uint32_t FA1R;
tushki7	0:60d829a0353a	268	uint32_t RESERVED5[8];
tushki7	0:60d829a0353a	269	CAN_FilterRegister_TypeDef sFilterRegister[14];
tushki7	0:60d829a0353a	270	} CAN_TypeDef;
tushki7	0:60d829a0353a	271
tushki7	0:60d829a0353a	272	/**
tushki7	0:60d829a0353a	273	* @brief CRC calculation unit
tushki7	0:60d829a0353a	274	*/
tushki7	0:60d829a0353a	275
tushki7	0:60d829a0353a	276	typedef struct
tushki7	0:60d829a0353a	277	{
tushki7	0:60d829a0353a	278	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
tushki7	0:60d829a0353a	279	__IO uint32_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
tushki7	0:60d829a0353a	280	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
tushki7	0:60d829a0353a	281	} CRC_TypeDef;
tushki7	0:60d829a0353a	282
tushki7	0:60d829a0353a	283
tushki7	0:60d829a0353a	284	/**
tushki7	0:60d829a0353a	285	* @brief Debug MCU
tushki7	0:60d829a0353a	286	*/
tushki7	0:60d829a0353a	287
tushki7	0:60d829a0353a	288	typedef struct
tushki7	0:60d829a0353a	289	{
tushki7	0:60d829a0353a	290	__IO uint32_t IDCODE;
tushki7	0:60d829a0353a	291	__IO uint32_t CR;
tushki7	0:60d829a0353a	292	}DBGMCU_TypeDef;
tushki7	0:60d829a0353a	293
tushki7	0:60d829a0353a	294	/**
tushki7	0:60d829a0353a	295	* @brief DMA Controller
tushki7	0:60d829a0353a	296	*/
tushki7	0:60d829a0353a	297
tushki7	0:60d829a0353a	298	typedef struct
tushki7	0:60d829a0353a	299	{
tushki7	0:60d829a0353a	300	__IO uint32_t CCR;
tushki7	0:60d829a0353a	301	__IO uint32_t CNDTR;
tushki7	0:60d829a0353a	302	__IO uint32_t CPAR;
tushki7	0:60d829a0353a	303	__IO uint32_t CMAR;
tushki7	0:60d829a0353a	304	} DMA_Channel_TypeDef;
tushki7	0:60d829a0353a	305
tushki7	0:60d829a0353a	306	typedef struct
tushki7	0:60d829a0353a	307	{
tushki7	0:60d829a0353a	308	__IO uint32_t ISR;
tushki7	0:60d829a0353a	309	__IO uint32_t IFCR;
tushki7	0:60d829a0353a	310	} DMA_TypeDef;
tushki7	0:60d829a0353a	311
tushki7	0:60d829a0353a	312
tushki7	0:60d829a0353a	313
tushki7	0:60d829a0353a	314	/**
tushki7	0:60d829a0353a	315	* @brief External Interrupt/Event Controller
tushki7	0:60d829a0353a	316	*/
tushki7	0:60d829a0353a	317
tushki7	0:60d829a0353a	318	typedef struct
tushki7	0:60d829a0353a	319	{
tushki7	0:60d829a0353a	320	__IO uint32_t IMR;
tushki7	0:60d829a0353a	321	__IO uint32_t EMR;
tushki7	0:60d829a0353a	322	__IO uint32_t RTSR;
tushki7	0:60d829a0353a	323	__IO uint32_t FTSR;
tushki7	0:60d829a0353a	324	__IO uint32_t SWIER;
tushki7	0:60d829a0353a	325	__IO uint32_t PR;
tushki7	0:60d829a0353a	326	} EXTI_TypeDef;
tushki7	0:60d829a0353a	327
tushki7	0:60d829a0353a	328	/**
tushki7	0:60d829a0353a	329	* @brief FLASH Registers
tushki7	0:60d829a0353a	330	*/
tushki7	0:60d829a0353a	331
tushki7	0:60d829a0353a	332	typedef struct
tushki7	0:60d829a0353a	333	{
tushki7	0:60d829a0353a	334	__IO uint32_t ACR;
tushki7	0:60d829a0353a	335	__IO uint32_t KEYR;
tushki7	0:60d829a0353a	336	__IO uint32_t OPTKEYR;
tushki7	0:60d829a0353a	337	__IO uint32_t SR;
tushki7	0:60d829a0353a	338	__IO uint32_t CR;
tushki7	0:60d829a0353a	339	__IO uint32_t AR;
tushki7	0:60d829a0353a	340	__IO uint32_t RESERVED;
tushki7	0:60d829a0353a	341	__IO uint32_t OBR;
tushki7	0:60d829a0353a	342	__IO uint32_t WRPR;
tushki7	0:60d829a0353a	343	} FLASH_TypeDef;
tushki7	0:60d829a0353a	344
tushki7	0:60d829a0353a	345	/**
tushki7	0:60d829a0353a	346	* @brief Option Bytes Registers
tushki7	0:60d829a0353a	347	*/
tushki7	0:60d829a0353a	348
tushki7	0:60d829a0353a	349	typedef struct
tushki7	0:60d829a0353a	350	{
tushki7	0:60d829a0353a	351	__IO uint16_t RDP;
tushki7	0:60d829a0353a	352	__IO uint16_t USER;
tushki7	0:60d829a0353a	353	__IO uint16_t Data0;
tushki7	0:60d829a0353a	354	__IO uint16_t Data1;
tushki7	0:60d829a0353a	355	__IO uint16_t WRP0;
tushki7	0:60d829a0353a	356	__IO uint16_t WRP1;
tushki7	0:60d829a0353a	357	__IO uint16_t WRP2;
tushki7	0:60d829a0353a	358	__IO uint16_t WRP3;
tushki7	0:60d829a0353a	359	} OB_TypeDef;
tushki7	0:60d829a0353a	360
tushki7	0:60d829a0353a	361	/**
tushki7	0:60d829a0353a	362	* @brief General Purpose I/O
tushki7	0:60d829a0353a	363	*/
tushki7	0:60d829a0353a	364
tushki7	0:60d829a0353a	365	typedef struct
tushki7	0:60d829a0353a	366	{
tushki7	0:60d829a0353a	367	__IO uint32_t CRL;
tushki7	0:60d829a0353a	368	__IO uint32_t CRH;
tushki7	0:60d829a0353a	369	__IO uint32_t IDR;
tushki7	0:60d829a0353a	370	__IO uint32_t ODR;
tushki7	0:60d829a0353a	371	__IO uint32_t BSRR;
tushki7	0:60d829a0353a	372	__IO uint32_t BRR;
tushki7	0:60d829a0353a	373	__IO uint32_t LCKR;
tushki7	0:60d829a0353a	374	} GPIO_TypeDef;
tushki7	0:60d829a0353a	375
tushki7	0:60d829a0353a	376	/**
tushki7	0:60d829a0353a	377	* @brief Alternate Function I/O
tushki7	0:60d829a0353a	378	*/
tushki7	0:60d829a0353a	379
tushki7	0:60d829a0353a	380	typedef struct
tushki7	0:60d829a0353a	381	{
tushki7	0:60d829a0353a	382	__IO uint32_t EVCR;
tushki7	0:60d829a0353a	383	__IO uint32_t MAPR;
tushki7	0:60d829a0353a	384	__IO uint32_t EXTICR[4];
tushki7	0:60d829a0353a	385	uint32_t RESERVED0;
tushki7	0:60d829a0353a	386	__IO uint32_t MAPR2;
tushki7	0:60d829a0353a	387	} AFIO_TypeDef;
tushki7	0:60d829a0353a	388	/**
tushki7	0:60d829a0353a	389	* @brief Inter Integrated Circuit Interface
tushki7	0:60d829a0353a	390	*/
tushki7	0:60d829a0353a	391
tushki7	0:60d829a0353a	392	typedef struct
tushki7	0:60d829a0353a	393	{
tushki7	0:60d829a0353a	394	__IO uint32_t CR1;
tushki7	0:60d829a0353a	395	__IO uint32_t CR2;
tushki7	0:60d829a0353a	396	__IO uint32_t OAR1;
tushki7	0:60d829a0353a	397	__IO uint32_t OAR2;
tushki7	0:60d829a0353a	398	__IO uint32_t DR;
tushki7	0:60d829a0353a	399	__IO uint32_t SR1;
tushki7	0:60d829a0353a	400	__IO uint32_t SR2;
tushki7	0:60d829a0353a	401	__IO uint32_t CCR;
tushki7	0:60d829a0353a	402	__IO uint32_t TRISE;
tushki7	0:60d829a0353a	403	} I2C_TypeDef;
tushki7	0:60d829a0353a	404
tushki7	0:60d829a0353a	405	/**
tushki7	0:60d829a0353a	406	* @brief Independent WATCHDOG
tushki7	0:60d829a0353a	407	*/
tushki7	0:60d829a0353a	408
tushki7	0:60d829a0353a	409	typedef struct
tushki7	0:60d829a0353a	410	{
tushki7	0:60d829a0353a	411	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
tushki7	0:60d829a0353a	412	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
tushki7	0:60d829a0353a	413	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
tushki7	0:60d829a0353a	414	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
tushki7	0:60d829a0353a	415	} IWDG_TypeDef;
tushki7	0:60d829a0353a	416
tushki7	0:60d829a0353a	417	/**
tushki7	0:60d829a0353a	418	* @brief Power Control
tushki7	0:60d829a0353a	419	*/
tushki7	0:60d829a0353a	420
tushki7	0:60d829a0353a	421	typedef struct
tushki7	0:60d829a0353a	422	{
tushki7	0:60d829a0353a	423	__IO uint32_t CR;
tushki7	0:60d829a0353a	424	__IO uint32_t CSR;
tushki7	0:60d829a0353a	425	} PWR_TypeDef;
tushki7	0:60d829a0353a	426
tushki7	0:60d829a0353a	427	/**
tushki7	0:60d829a0353a	428	* @brief Reset and Clock Control
tushki7	0:60d829a0353a	429	*/
tushki7	0:60d829a0353a	430
tushki7	0:60d829a0353a	431	typedef struct
tushki7	0:60d829a0353a	432	{
tushki7	0:60d829a0353a	433	__IO uint32_t CR;
tushki7	0:60d829a0353a	434	__IO uint32_t CFGR;
tushki7	0:60d829a0353a	435	__IO uint32_t CIR;
tushki7	0:60d829a0353a	436	__IO uint32_t APB2RSTR;
tushki7	0:60d829a0353a	437	__IO uint32_t APB1RSTR;
tushki7	0:60d829a0353a	438	__IO uint32_t AHBENR;
tushki7	0:60d829a0353a	439	__IO uint32_t APB2ENR;
tushki7	0:60d829a0353a	440	__IO uint32_t APB1ENR;
tushki7	0:60d829a0353a	441	__IO uint32_t BDCR;
tushki7	0:60d829a0353a	442	__IO uint32_t CSR;
tushki7	0:60d829a0353a	443
tushki7	0:60d829a0353a	444
tushki7	0:60d829a0353a	445	} RCC_TypeDef;
tushki7	0:60d829a0353a	446
tushki7	0:60d829a0353a	447	/**
tushki7	0:60d829a0353a	448	* @brief Real-Time Clock
tushki7	0:60d829a0353a	449	*/
tushki7	0:60d829a0353a	450
tushki7	0:60d829a0353a	451	typedef struct
tushki7	0:60d829a0353a	452	{
tushki7	0:60d829a0353a	453	__IO uint32_t CRH;
tushki7	0:60d829a0353a	454	__IO uint32_t CRL;
tushki7	0:60d829a0353a	455	__IO uint32_t PRLH;
tushki7	0:60d829a0353a	456	__IO uint32_t PRLL;
tushki7	0:60d829a0353a	457	__IO uint32_t DIVH;
tushki7	0:60d829a0353a	458	__IO uint32_t DIVL;
tushki7	0:60d829a0353a	459	__IO uint32_t CNTH;
tushki7	0:60d829a0353a	460	__IO uint32_t CNTL;
tushki7	0:60d829a0353a	461	__IO uint32_t ALRH;
tushki7	0:60d829a0353a	462	__IO uint32_t ALRL;
tushki7	0:60d829a0353a	463	} RTC_TypeDef;
tushki7	0:60d829a0353a	464
tushki7	0:60d829a0353a	465	/**
tushki7	0:60d829a0353a	466	* @brief SD host Interface
tushki7	0:60d829a0353a	467	*/
tushki7	0:60d829a0353a	468
tushki7	0:60d829a0353a	469	typedef struct
tushki7	0:60d829a0353a	470	{
tushki7	0:60d829a0353a	471	__IO uint32_t POWER;
tushki7	0:60d829a0353a	472	__IO uint32_t CLKCR;
tushki7	0:60d829a0353a	473	__IO uint32_t ARG;
tushki7	0:60d829a0353a	474	__IO uint32_t CMD;
tushki7	0:60d829a0353a	475	__I uint32_t RESPCMD;
tushki7	0:60d829a0353a	476	__I uint32_t RESP1;
tushki7	0:60d829a0353a	477	__I uint32_t RESP2;
tushki7	0:60d829a0353a	478	__I uint32_t RESP3;
tushki7	0:60d829a0353a	479	__I uint32_t RESP4;
tushki7	0:60d829a0353a	480	__IO uint32_t DTIMER;
tushki7	0:60d829a0353a	481	__IO uint32_t DLEN;
tushki7	0:60d829a0353a	482	__IO uint32_t DCTRL;
tushki7	0:60d829a0353a	483	__I uint32_t DCOUNT;
tushki7	0:60d829a0353a	484	__I uint32_t STA;
tushki7	0:60d829a0353a	485	__IO uint32_t ICR;
tushki7	0:60d829a0353a	486	__IO uint32_t MASK;
tushki7	0:60d829a0353a	487	uint32_t RESERVED0[2];
tushki7	0:60d829a0353a	488	__I uint32_t FIFOCNT;
tushki7	0:60d829a0353a	489	uint32_t RESERVED1[13];
tushki7	0:60d829a0353a	490	__IO uint32_t FIFO;
tushki7	0:60d829a0353a	491	} SDIO_TypeDef;
tushki7	0:60d829a0353a	492
tushki7	0:60d829a0353a	493	/**
tushki7	0:60d829a0353a	494	* @brief Serial Peripheral Interface
tushki7	0:60d829a0353a	495	*/
tushki7	0:60d829a0353a	496
tushki7	0:60d829a0353a	497	typedef struct
tushki7	0:60d829a0353a	498	{
tushki7	0:60d829a0353a	499	__IO uint32_t CR1;
tushki7	0:60d829a0353a	500	__IO uint32_t CR2;
tushki7	0:60d829a0353a	501	__IO uint32_t SR;
tushki7	0:60d829a0353a	502	__IO uint32_t DR;
tushki7	0:60d829a0353a	503	__IO uint32_t CRCPR;
tushki7	0:60d829a0353a	504	__IO uint32_t RXCRCR;
tushki7	0:60d829a0353a	505	__IO uint32_t TXCRCR;
tushki7	0:60d829a0353a	506	__IO uint32_t I2SCFGR;
tushki7	0:60d829a0353a	507	} SPI_TypeDef;
tushki7	0:60d829a0353a	508
tushki7	0:60d829a0353a	509	/**
tushki7	0:60d829a0353a	510	* @brief TIM Timers
tushki7	0:60d829a0353a	511	*/
tushki7	0:60d829a0353a	512	typedef struct
tushki7	0:60d829a0353a	513	{
tushki7	0:60d829a0353a	514	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
tushki7	0:60d829a0353a	515	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
tushki7	0:60d829a0353a	516	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
tushki7	0:60d829a0353a	517	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
tushki7	0:60d829a0353a	518	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
tushki7	0:60d829a0353a	519	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
tushki7	0:60d829a0353a	520	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
tushki7	0:60d829a0353a	521	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
tushki7	0:60d829a0353a	522	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
tushki7	0:60d829a0353a	523	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
tushki7	0:60d829a0353a	524	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
tushki7	0:60d829a0353a	525	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
tushki7	0:60d829a0353a	526	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
tushki7	0:60d829a0353a	527	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
tushki7	0:60d829a0353a	528	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
tushki7	0:60d829a0353a	529	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
tushki7	0:60d829a0353a	530	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
tushki7	0:60d829a0353a	531	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
tushki7	0:60d829a0353a	532	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
tushki7	0:60d829a0353a	533	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
tushki7	0:60d829a0353a	534	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
tushki7	0:60d829a0353a	535	}TIM_TypeDef;
tushki7	0:60d829a0353a	536
tushki7	0:60d829a0353a	537
tushki7	0:60d829a0353a	538	/**
tushki7	0:60d829a0353a	539	* @brief Universal Synchronous Asynchronous Receiver Transmitter
tushki7	0:60d829a0353a	540	*/
tushki7	0:60d829a0353a	541
tushki7	0:60d829a0353a	542	typedef struct
tushki7	0:60d829a0353a	543	{
tushki7	0:60d829a0353a	544	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
tushki7	0:60d829a0353a	545	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
tushki7	0:60d829a0353a	546	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
tushki7	0:60d829a0353a	547	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
tushki7	0:60d829a0353a	548	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
tushki7	0:60d829a0353a	549	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
tushki7	0:60d829a0353a	550	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
tushki7	0:60d829a0353a	551	} USART_TypeDef;
tushki7	0:60d829a0353a	552
tushki7	0:60d829a0353a	553	/**
tushki7	0:60d829a0353a	554	* @brief Universal Serial Bus Full Speed Device
tushki7	0:60d829a0353a	555	*/
tushki7	0:60d829a0353a	556
tushki7	0:60d829a0353a	557	typedef struct
tushki7	0:60d829a0353a	558	{
tushki7	0:60d829a0353a	559	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
tushki7	0:60d829a0353a	560	__IO uint16_t RESERVED0; /!< Reserved /
tushki7	0:60d829a0353a	561	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
tushki7	0:60d829a0353a	562	__IO uint16_t RESERVED1; /!< Reserved /
tushki7	0:60d829a0353a	563	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
tushki7	0:60d829a0353a	564	__IO uint16_t RESERVED2; /!< Reserved /
tushki7	0:60d829a0353a	565	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
tushki7	0:60d829a0353a	566	__IO uint16_t RESERVED3; /!< Reserved /
tushki7	0:60d829a0353a	567	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
tushki7	0:60d829a0353a	568	__IO uint16_t RESERVED4; /!< Reserved /
tushki7	0:60d829a0353a	569	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
tushki7	0:60d829a0353a	570	__IO uint16_t RESERVED5; /!< Reserved /
tushki7	0:60d829a0353a	571	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
tushki7	0:60d829a0353a	572	__IO uint16_t RESERVED6; /!< Reserved /
tushki7	0:60d829a0353a	573	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
tushki7	0:60d829a0353a	574	__IO uint16_t RESERVED7[17]; /!< Reserved /
tushki7	0:60d829a0353a	575	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
tushki7	0:60d829a0353a	576	__IO uint16_t RESERVED8; /!< Reserved /
tushki7	0:60d829a0353a	577	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
tushki7	0:60d829a0353a	578	__IO uint16_t RESERVED9; /!< Reserved /
tushki7	0:60d829a0353a	579	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
tushki7	0:60d829a0353a	580	__IO uint16_t RESERVEDA; /!< Reserved /
tushki7	0:60d829a0353a	581	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
tushki7	0:60d829a0353a	582	__IO uint16_t RESERVEDB; /!< Reserved /
tushki7	0:60d829a0353a	583	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
tushki7	0:60d829a0353a	584	__IO uint16_t RESERVEDC; /!< Reserved /
tushki7	0:60d829a0353a	585	} USB_TypeDef;
tushki7	0:60d829a0353a	586
tushki7	0:60d829a0353a	587
tushki7	0:60d829a0353a	588	/**
tushki7	0:60d829a0353a	589	* @brief Window WATCHDOG
tushki7	0:60d829a0353a	590	*/
tushki7	0:60d829a0353a	591
tushki7	0:60d829a0353a	592	typedef struct
tushki7	0:60d829a0353a	593	{
tushki7	0:60d829a0353a	594	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
tushki7	0:60d829a0353a	595	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
tushki7	0:60d829a0353a	596	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
tushki7	0:60d829a0353a	597	} WWDG_TypeDef;
tushki7	0:60d829a0353a	598
tushki7	0:60d829a0353a	599	/**
tushki7	0:60d829a0353a	600	* @}
tushki7	0:60d829a0353a	601	*/
tushki7	0:60d829a0353a	602
tushki7	0:60d829a0353a	603	/** @addtogroup Peripheral_memory_map
tushki7	0:60d829a0353a	604	* @{
tushki7	0:60d829a0353a	605	*/
tushki7	0:60d829a0353a	606
tushki7	0:60d829a0353a	607
tushki7	0:60d829a0353a	608	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
tushki7	0:60d829a0353a	609	#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /!< FLASH END address of bank1 /
tushki7	0:60d829a0353a	610	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
tushki7	0:60d829a0353a	611	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
tushki7	0:60d829a0353a	612
tushki7	0:60d829a0353a	613	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
tushki7	0:60d829a0353a	614	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
tushki7	0:60d829a0353a	615
tushki7	0:60d829a0353a	616
tushki7	0:60d829a0353a	617	/!< Peripheral memory map /
tushki7	0:60d829a0353a	618	#define APB1PERIPH_BASE PERIPH_BASE
tushki7	0:60d829a0353a	619	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
tushki7	0:60d829a0353a	620	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
tushki7	0:60d829a0353a	621
tushki7	0:60d829a0353a	622	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
tushki7	0:60d829a0353a	623	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
tushki7	0:60d829a0353a	624	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
tushki7	0:60d829a0353a	625	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
tushki7	0:60d829a0353a	626	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
tushki7	0:60d829a0353a	627	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
tushki7	0:60d829a0353a	628	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
tushki7	0:60d829a0353a	629	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
tushki7	0:60d829a0353a	630	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
tushki7	0:60d829a0353a	631	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
tushki7	0:60d829a0353a	632	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
tushki7	0:60d829a0353a	633	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
tushki7	0:60d829a0353a	634	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
tushki7	0:60d829a0353a	635	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
tushki7	0:60d829a0353a	636	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
tushki7	0:60d829a0353a	637	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
tushki7	0:60d829a0353a	638	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
tushki7	0:60d829a0353a	639	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
tushki7	0:60d829a0353a	640	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
tushki7	0:60d829a0353a	641	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
tushki7	0:60d829a0353a	642	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
tushki7	0:60d829a0353a	643	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
tushki7	0:60d829a0353a	644	#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
tushki7	0:60d829a0353a	645	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
tushki7	0:60d829a0353a	646	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
tushki7	0:60d829a0353a	647	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
tushki7	0:60d829a0353a	648
tushki7	0:60d829a0353a	649	#define SDIO_BASE (PERIPH_BASE + 0x18000)
tushki7	0:60d829a0353a	650
tushki7	0:60d829a0353a	651	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
tushki7	0:60d829a0353a	652	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
tushki7	0:60d829a0353a	653	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
tushki7	0:60d829a0353a	654	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
tushki7	0:60d829a0353a	655	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
tushki7	0:60d829a0353a	656	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
tushki7	0:60d829a0353a	657	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
tushki7	0:60d829a0353a	658	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
tushki7	0:60d829a0353a	659	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
tushki7	0:60d829a0353a	660	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
tushki7	0:60d829a0353a	661
tushki7	0:60d829a0353a	662	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
tushki7	0:60d829a0353a	663	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
tushki7	0:60d829a0353a	664
tushki7	0:60d829a0353a	665
tushki7	0:60d829a0353a	666
tushki7	0:60d829a0353a	667	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
tushki7	0:60d829a0353a	668
tushki7	0:60d829a0353a	669	/* USB device FS */
tushki7	0:60d829a0353a	670	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
tushki7	0:60d829a0353a	671	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
tushki7	0:60d829a0353a	672
tushki7	0:60d829a0353a	673
tushki7	0:60d829a0353a	674	/**
tushki7	0:60d829a0353a	675	* @}
tushki7	0:60d829a0353a	676	*/
tushki7	0:60d829a0353a	677
tushki7	0:60d829a0353a	678	/** @addtogroup Peripheral_declaration
tushki7	0:60d829a0353a	679	* @{
tushki7	0:60d829a0353a	680	*/
tushki7	0:60d829a0353a	681
tushki7	0:60d829a0353a	682	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
tushki7	0:60d829a0353a	683	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
tushki7	0:60d829a0353a	684	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
tushki7	0:60d829a0353a	685	#define RTC ((RTC_TypeDef *) RTC_BASE)
tushki7	0:60d829a0353a	686	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
tushki7	0:60d829a0353a	687	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
tushki7	0:60d829a0353a	688	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
tushki7	0:60d829a0353a	689	#define USART2 ((USART_TypeDef *) USART2_BASE)
tushki7	0:60d829a0353a	690	#define USART3 ((USART_TypeDef *) USART3_BASE)
tushki7	0:60d829a0353a	691	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
tushki7	0:60d829a0353a	692	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
tushki7	0:60d829a0353a	693	#define USB ((USB_TypeDef *) USB_BASE)
tushki7	0:60d829a0353a	694	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
tushki7	0:60d829a0353a	695	#define BKP ((BKP_TypeDef *) BKP_BASE)
tushki7	0:60d829a0353a	696	#define PWR ((PWR_TypeDef *) PWR_BASE)
tushki7	0:60d829a0353a	697	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
tushki7	0:60d829a0353a	698	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
tushki7	0:60d829a0353a	699	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
tushki7	0:60d829a0353a	700	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
tushki7	0:60d829a0353a	701	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
tushki7	0:60d829a0353a	702	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
tushki7	0:60d829a0353a	703	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
tushki7	0:60d829a0353a	704	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
tushki7	0:60d829a0353a	705	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
tushki7	0:60d829a0353a	706	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
tushki7	0:60d829a0353a	707	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
tushki7	0:60d829a0353a	708	#define USART1 ((USART_TypeDef *) USART1_BASE)
tushki7	0:60d829a0353a	709	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
tushki7	0:60d829a0353a	710	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
tushki7	0:60d829a0353a	711	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
tushki7	0:60d829a0353a	712	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
tushki7	0:60d829a0353a	713	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
tushki7	0:60d829a0353a	714	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
tushki7	0:60d829a0353a	715	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
tushki7	0:60d829a0353a	716	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
tushki7	0:60d829a0353a	717	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
tushki7	0:60d829a0353a	718	#define RCC ((RCC_TypeDef *) RCC_BASE)
tushki7	0:60d829a0353a	719	#define CRC ((CRC_TypeDef *) CRC_BASE)
tushki7	0:60d829a0353a	720	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
tushki7	0:60d829a0353a	721	#define OB ((OB_TypeDef *) OB_BASE)
tushki7	0:60d829a0353a	722	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
tushki7	0:60d829a0353a	723
tushki7	0:60d829a0353a	724
tushki7	0:60d829a0353a	725	/**
tushki7	0:60d829a0353a	726	* @}
tushki7	0:60d829a0353a	727	*/
tushki7	0:60d829a0353a	728
tushki7	0:60d829a0353a	729	/** @addtogroup Exported_constants
tushki7	0:60d829a0353a	730	* @{
tushki7	0:60d829a0353a	731	*/
tushki7	0:60d829a0353a	732
tushki7	0:60d829a0353a	733	/** @addtogroup Peripheral_Registers_Bits_Definition
tushki7	0:60d829a0353a	734	* @{
tushki7	0:60d829a0353a	735	*/
tushki7	0:60d829a0353a	736
tushki7	0:60d829a0353a	737	/******************************************************************************/
tushki7	0:60d829a0353a	738	/* Peripheral Registers_Bits_Definition */
tushki7	0:60d829a0353a	739	/******************************************************************************/
tushki7	0:60d829a0353a	740
tushki7	0:60d829a0353a	741	/******************************************************************************/
tushki7	0:60d829a0353a	742	/* */
tushki7	0:60d829a0353a	743	/* CRC calculation unit (CRC) */
tushki7	0:60d829a0353a	744	/* */
tushki7	0:60d829a0353a	745	/******************************************************************************/
tushki7	0:60d829a0353a	746
tushki7	0:60d829a0353a	747	/***************** Bit definition for CRC_DR register *******************/
tushki7	0:60d829a0353a	748	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
tushki7	0:60d829a0353a	749
tushki7	0:60d829a0353a	750	/***************** Bit definition for CRC_IDR register ******************/
tushki7	0:60d829a0353a	751	#define CRC_IDR_IDR ((uint32_t)0x000000FF) /!< General-purpose 8-bit data register bits /
tushki7	0:60d829a0353a	752
tushki7	0:60d829a0353a	753	/****************** Bit definition for CRC_CR register ******************/
tushki7	0:60d829a0353a	754	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
tushki7	0:60d829a0353a	755
tushki7	0:60d829a0353a	756	/******************************************************************************/
tushki7	0:60d829a0353a	757	/* */
tushki7	0:60d829a0353a	758	/* Power Control */
tushki7	0:60d829a0353a	759	/* */
tushki7	0:60d829a0353a	760	/******************************************************************************/
tushki7	0:60d829a0353a	761
tushki7	0:60d829a0353a	762	/****************** Bit definition for PWR_CR register ******************/
tushki7	0:60d829a0353a	763	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
tushki7	0:60d829a0353a	764	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
tushki7	0:60d829a0353a	765	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
tushki7	0:60d829a0353a	766	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
tushki7	0:60d829a0353a	767	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
tushki7	0:60d829a0353a	768
tushki7	0:60d829a0353a	769	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
tushki7	0:60d829a0353a	770	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	771	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	772	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	773
tushki7	0:60d829a0353a	774	/!< PVD level configuration /
tushki7	0:60d829a0353a	775	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
tushki7	0:60d829a0353a	776	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
tushki7	0:60d829a0353a	777	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
tushki7	0:60d829a0353a	778	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
tushki7	0:60d829a0353a	779	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
tushki7	0:60d829a0353a	780	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
tushki7	0:60d829a0353a	781	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
tushki7	0:60d829a0353a	782	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
tushki7	0:60d829a0353a	783
tushki7	0:60d829a0353a	784	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
tushki7	0:60d829a0353a	785
tushki7	0:60d829a0353a	786
tushki7	0:60d829a0353a	787	/***************** Bit definition for PWR_CSR register ******************/
tushki7	0:60d829a0353a	788	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
tushki7	0:60d829a0353a	789	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
tushki7	0:60d829a0353a	790	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
tushki7	0:60d829a0353a	791	#define PWR_CSR_EWUP ((uint32_t)0x00000100) /!< Enable WKUP pin /
tushki7	0:60d829a0353a	792
tushki7	0:60d829a0353a	793	/******************************************************************************/
tushki7	0:60d829a0353a	794	/* */
tushki7	0:60d829a0353a	795	/* Backup registers */
tushki7	0:60d829a0353a	796	/* */
tushki7	0:60d829a0353a	797	/******************************************************************************/
tushki7	0:60d829a0353a	798
tushki7	0:60d829a0353a	799	/***************** Bit definition for BKP_DR1 register ******************/
tushki7	0:60d829a0353a	800	#define BKP_DR1_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	801
tushki7	0:60d829a0353a	802	/***************** Bit definition for BKP_DR2 register ******************/
tushki7	0:60d829a0353a	803	#define BKP_DR2_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	804
tushki7	0:60d829a0353a	805	/***************** Bit definition for BKP_DR3 register ******************/
tushki7	0:60d829a0353a	806	#define BKP_DR3_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	807
tushki7	0:60d829a0353a	808	/***************** Bit definition for BKP_DR4 register ******************/
tushki7	0:60d829a0353a	809	#define BKP_DR4_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	810
tushki7	0:60d829a0353a	811	/***************** Bit definition for BKP_DR5 register ******************/
tushki7	0:60d829a0353a	812	#define BKP_DR5_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	813
tushki7	0:60d829a0353a	814	/***************** Bit definition for BKP_DR6 register ******************/
tushki7	0:60d829a0353a	815	#define BKP_DR6_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	816
tushki7	0:60d829a0353a	817	/***************** Bit definition for BKP_DR7 register ******************/
tushki7	0:60d829a0353a	818	#define BKP_DR7_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	819
tushki7	0:60d829a0353a	820	/***************** Bit definition for BKP_DR8 register ******************/
tushki7	0:60d829a0353a	821	#define BKP_DR8_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	822
tushki7	0:60d829a0353a	823	/***************** Bit definition for BKP_DR9 register ******************/
tushki7	0:60d829a0353a	824	#define BKP_DR9_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	825
tushki7	0:60d829a0353a	826	/***************** Bit definition for BKP_DR10 register *****************/
tushki7	0:60d829a0353a	827	#define BKP_DR10_D ((uint32_t)0x0000FFFF) /!< Backup data /
tushki7	0:60d829a0353a	828
tushki7	0:60d829a0353a	829	#define RTC_BKP_NUMBER 10
tushki7	0:60d829a0353a	830
tushki7	0:60d829a0353a	831	/**************** Bit definition for BKP_RTCCR register *****************/
tushki7	0:60d829a0353a	832	#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /!< Calibration value /
tushki7	0:60d829a0353a	833	#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /!< Calibration Clock Output /
tushki7	0:60d829a0353a	834	#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /!< Alarm or Second Output Enable /
tushki7	0:60d829a0353a	835	#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /!< Alarm or Second Output Selection /
tushki7	0:60d829a0353a	836
tushki7	0:60d829a0353a	837	/****************** Bit definition for BKP_CR register ******************/
tushki7	0:60d829a0353a	838	#define BKP_CR_TPE ((uint32_t)0x00000001) /!< TAMPER pin enable /
tushki7	0:60d829a0353a	839	#define BKP_CR_TPAL ((uint32_t)0x00000002) /!< TAMPER pin active level /
tushki7	0:60d829a0353a	840
tushki7	0:60d829a0353a	841	/***************** Bit definition for BKP_CSR register ******************/
tushki7	0:60d829a0353a	842	#define BKP_CSR_CTE ((uint32_t)0x00000001) /!< Clear Tamper event /
tushki7	0:60d829a0353a	843	#define BKP_CSR_CTI ((uint32_t)0x00000002) /!< Clear Tamper Interrupt /
tushki7	0:60d829a0353a	844	#define BKP_CSR_TPIE ((uint32_t)0x00000004) /!< TAMPER Pin interrupt enable /
tushki7	0:60d829a0353a	845	#define BKP_CSR_TEF ((uint32_t)0x00000100) /!< Tamper Event Flag /
tushki7	0:60d829a0353a	846	#define BKP_CSR_TIF ((uint32_t)0x00000200) /!< Tamper Interrupt Flag /
tushki7	0:60d829a0353a	847
tushki7	0:60d829a0353a	848	/******************************************************************************/
tushki7	0:60d829a0353a	849	/* */
tushki7	0:60d829a0353a	850	/* Reset and Clock Control */
tushki7	0:60d829a0353a	851	/* */
tushki7	0:60d829a0353a	852	/******************************************************************************/
tushki7	0:60d829a0353a	853
tushki7	0:60d829a0353a	854	/****************** Bit definition for RCC_CR register ******************/
tushki7	0:60d829a0353a	855	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
tushki7	0:60d829a0353a	856	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
tushki7	0:60d829a0353a	857	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
tushki7	0:60d829a0353a	858	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
tushki7	0:60d829a0353a	859	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
tushki7	0:60d829a0353a	860	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
tushki7	0:60d829a0353a	861	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
tushki7	0:60d829a0353a	862	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
tushki7	0:60d829a0353a	863	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
tushki7	0:60d829a0353a	864	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
tushki7	0:60d829a0353a	865
tushki7	0:60d829a0353a	866
tushki7	0:60d829a0353a	867	/***************** Bit definition for RCC_CFGR register *****************/
tushki7	0:60d829a0353a	868	/!< SW configuration /
tushki7	0:60d829a0353a	869	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
tushki7	0:60d829a0353a	870	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	871	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	872
tushki7	0:60d829a0353a	873	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
tushki7	0:60d829a0353a	874	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
tushki7	0:60d829a0353a	875	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
tushki7	0:60d829a0353a	876
tushki7	0:60d829a0353a	877	/!< SWS configuration /
tushki7	0:60d829a0353a	878	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
tushki7	0:60d829a0353a	879	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
tushki7	0:60d829a0353a	880	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
tushki7	0:60d829a0353a	881
tushki7	0:60d829a0353a	882	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
tushki7	0:60d829a0353a	883	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
tushki7	0:60d829a0353a	884	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
tushki7	0:60d829a0353a	885
tushki7	0:60d829a0353a	886	/!< HPRE configuration /
tushki7	0:60d829a0353a	887	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
tushki7	0:60d829a0353a	888	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	889	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	890	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
tushki7	0:60d829a0353a	891	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
tushki7	0:60d829a0353a	892
tushki7	0:60d829a0353a	893	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
tushki7	0:60d829a0353a	894	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
tushki7	0:60d829a0353a	895	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
tushki7	0:60d829a0353a	896	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
tushki7	0:60d829a0353a	897	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
tushki7	0:60d829a0353a	898	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
tushki7	0:60d829a0353a	899	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
tushki7	0:60d829a0353a	900	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
tushki7	0:60d829a0353a	901	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
tushki7	0:60d829a0353a	902
tushki7	0:60d829a0353a	903	/!< PPRE1 configuration /
tushki7	0:60d829a0353a	904	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
tushki7	0:60d829a0353a	905	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	906	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	907	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
tushki7	0:60d829a0353a	908
tushki7	0:60d829a0353a	909	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
tushki7	0:60d829a0353a	910	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
tushki7	0:60d829a0353a	911	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
tushki7	0:60d829a0353a	912	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
tushki7	0:60d829a0353a	913	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
tushki7	0:60d829a0353a	914
tushki7	0:60d829a0353a	915	/!< PPRE2 configuration /
tushki7	0:60d829a0353a	916	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
tushki7	0:60d829a0353a	917	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
tushki7	0:60d829a0353a	918	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
tushki7	0:60d829a0353a	919	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
tushki7	0:60d829a0353a	920
tushki7	0:60d829a0353a	921	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
tushki7	0:60d829a0353a	922	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
tushki7	0:60d829a0353a	923	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
tushki7	0:60d829a0353a	924	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
tushki7	0:60d829a0353a	925	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
tushki7	0:60d829a0353a	926
tushki7	0:60d829a0353a	927	/!< ADCPPRE configuration /
tushki7	0:60d829a0353a	928	#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /!< ADCPRE[1:0] bits (ADC prescaler) /
tushki7	0:60d829a0353a	929	#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /!< Bit 0 /
tushki7	0:60d829a0353a	930	#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /!< Bit 1 /
tushki7	0:60d829a0353a	931
tushki7	0:60d829a0353a	932	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
tushki7	0:60d829a0353a	933	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
tushki7	0:60d829a0353a	934	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
tushki7	0:60d829a0353a	935	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
tushki7	0:60d829a0353a	936
tushki7	0:60d829a0353a	937	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
tushki7	0:60d829a0353a	938
tushki7	0:60d829a0353a	939	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
tushki7	0:60d829a0353a	940
tushki7	0:60d829a0353a	941	/!< PLLMUL configuration /
tushki7	0:60d829a0353a	942	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
tushki7	0:60d829a0353a	943	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	944	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	945	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
tushki7	0:60d829a0353a	946	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
tushki7	0:60d829a0353a	947
tushki7	0:60d829a0353a	948	#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /!< HSE clock not divided for PLL entry /
tushki7	0:60d829a0353a	949	#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /!< HSE clock divided by 2 for PLL entry /
tushki7	0:60d829a0353a	950
tushki7	0:60d829a0353a	951	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
tushki7	0:60d829a0353a	952	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
tushki7	0:60d829a0353a	953	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
tushki7	0:60d829a0353a	954	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
tushki7	0:60d829a0353a	955	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
tushki7	0:60d829a0353a	956	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
tushki7	0:60d829a0353a	957	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
tushki7	0:60d829a0353a	958	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
tushki7	0:60d829a0353a	959	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
tushki7	0:60d829a0353a	960	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
tushki7	0:60d829a0353a	961	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
tushki7	0:60d829a0353a	962	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
tushki7	0:60d829a0353a	963	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
tushki7	0:60d829a0353a	964	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
tushki7	0:60d829a0353a	965	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
tushki7	0:60d829a0353a	966	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB Device prescaler /
tushki7	0:60d829a0353a	967
tushki7	0:60d829a0353a	968	/!< MCO configuration /
tushki7	0:60d829a0353a	969	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
tushki7	0:60d829a0353a	970	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	971	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	972	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
tushki7	0:60d829a0353a	973
tushki7	0:60d829a0353a	974	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
tushki7	0:60d829a0353a	975	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
tushki7	0:60d829a0353a	976	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
tushki7	0:60d829a0353a	977	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
tushki7	0:60d829a0353a	978	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
tushki7	0:60d829a0353a	979
tushki7	0:60d829a0353a	980	/!<*************** Bit definition for RCC_CIR register ******************/
tushki7	0:60d829a0353a	981	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
tushki7	0:60d829a0353a	982	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
tushki7	0:60d829a0353a	983	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
tushki7	0:60d829a0353a	984	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
tushki7	0:60d829a0353a	985	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
tushki7	0:60d829a0353a	986	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
tushki7	0:60d829a0353a	987	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
tushki7	0:60d829a0353a	988	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
tushki7	0:60d829a0353a	989	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
tushki7	0:60d829a0353a	990	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
tushki7	0:60d829a0353a	991	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
tushki7	0:60d829a0353a	992	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
tushki7	0:60d829a0353a	993	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
tushki7	0:60d829a0353a	994	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
tushki7	0:60d829a0353a	995	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
tushki7	0:60d829a0353a	996	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
tushki7	0:60d829a0353a	997	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
tushki7	0:60d829a0353a	998
tushki7	0:60d829a0353a	999
tushki7	0:60d829a0353a	1000	/*************** Bit definition for RCC_APB2RSTR register ***************/
tushki7	0:60d829a0353a	1001	#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /!< Alternate Function I/O reset /
tushki7	0:60d829a0353a	1002	#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /!< I/O port A reset /
tushki7	0:60d829a0353a	1003	#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /!< I/O port B reset /
tushki7	0:60d829a0353a	1004	#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /!< I/O port C reset /
tushki7	0:60d829a0353a	1005	#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /!< I/O port D reset /
tushki7	0:60d829a0353a	1006	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC 1 interface reset /
tushki7	0:60d829a0353a	1007
tushki7	0:60d829a0353a	1008	#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /!< ADC 2 interface reset /
tushki7	0:60d829a0353a	1009
tushki7	0:60d829a0353a	1010	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 Timer reset /
tushki7	0:60d829a0353a	1011	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI 1 reset /
tushki7	0:60d829a0353a	1012	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
tushki7	0:60d829a0353a	1013
tushki7	0:60d829a0353a	1014
tushki7	0:60d829a0353a	1015	#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /!< I/O port E reset /
tushki7	0:60d829a0353a	1016
tushki7	0:60d829a0353a	1017
tushki7	0:60d829a0353a	1018
tushki7	0:60d829a0353a	1019
tushki7	0:60d829a0353a	1020	/*************** Bit definition for RCC_APB1RSTR register ***************/
tushki7	0:60d829a0353a	1021	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
tushki7	0:60d829a0353a	1022	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
tushki7	0:60d829a0353a	1023	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
tushki7	0:60d829a0353a	1024	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
tushki7	0:60d829a0353a	1025	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
tushki7	0:60d829a0353a	1026
tushki7	0:60d829a0353a	1027	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /!< CAN1 reset /
tushki7	0:60d829a0353a	1028
tushki7	0:60d829a0353a	1029	#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /!< Backup interface reset /
tushki7	0:60d829a0353a	1030	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
tushki7	0:60d829a0353a	1031
tushki7	0:60d829a0353a	1032	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
tushki7	0:60d829a0353a	1033	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
tushki7	0:60d829a0353a	1034	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
tushki7	0:60d829a0353a	1035	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
tushki7	0:60d829a0353a	1036
tushki7	0:60d829a0353a	1037	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB Device reset /
tushki7	0:60d829a0353a	1038
tushki7	0:60d829a0353a	1039
tushki7	0:60d829a0353a	1040
tushki7	0:60d829a0353a	1041
tushki7	0:60d829a0353a	1042
tushki7	0:60d829a0353a	1043
tushki7	0:60d829a0353a	1044	/**************** Bit definition for RCC_AHBENR register ****************/
tushki7	0:60d829a0353a	1045	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
tushki7	0:60d829a0353a	1046	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
tushki7	0:60d829a0353a	1047	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
tushki7	0:60d829a0353a	1048	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
tushki7	0:60d829a0353a	1049
tushki7	0:60d829a0353a	1050
tushki7	0:60d829a0353a	1051
tushki7	0:60d829a0353a	1052
tushki7	0:60d829a0353a	1053	/**************** Bit definition for RCC_APB2ENR register ***************/
tushki7	0:60d829a0353a	1054	#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /!< Alternate Function I/O clock enable /
tushki7	0:60d829a0353a	1055	#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /!< I/O port A clock enable /
tushki7	0:60d829a0353a	1056	#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /!< I/O port B clock enable /
tushki7	0:60d829a0353a	1057	#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /!< I/O port C clock enable /
tushki7	0:60d829a0353a	1058	#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /!< I/O port D clock enable /
tushki7	0:60d829a0353a	1059	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC 1 interface clock enable /
tushki7	0:60d829a0353a	1060
tushki7	0:60d829a0353a	1061	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /!< ADC 2 interface clock enable /
tushki7	0:60d829a0353a	1062
tushki7	0:60d829a0353a	1063	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 Timer clock enable /
tushki7	0:60d829a0353a	1064	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI 1 clock enable /
tushki7	0:60d829a0353a	1065	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
tushki7	0:60d829a0353a	1066
tushki7	0:60d829a0353a	1067
tushki7	0:60d829a0353a	1068	#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /!< I/O port E clock enable /
tushki7	0:60d829a0353a	1069
tushki7	0:60d829a0353a	1070
tushki7	0:60d829a0353a	1071
tushki7	0:60d829a0353a	1072
tushki7	0:60d829a0353a	1073	/*************** Bit definition for RCC_APB1ENR register ****************/
tushki7	0:60d829a0353a	1074	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
tushki7	0:60d829a0353a	1075	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
tushki7	0:60d829a0353a	1076	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
tushki7	0:60d829a0353a	1077	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
tushki7	0:60d829a0353a	1078	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
tushki7	0:60d829a0353a	1079
tushki7	0:60d829a0353a	1080	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /!< CAN1 clock enable /
tushki7	0:60d829a0353a	1081
tushki7	0:60d829a0353a	1082	#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /!< Backup interface clock enable /
tushki7	0:60d829a0353a	1083	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
tushki7	0:60d829a0353a	1084
tushki7	0:60d829a0353a	1085	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
tushki7	0:60d829a0353a	1086	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
tushki7	0:60d829a0353a	1087	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
tushki7	0:60d829a0353a	1088	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
tushki7	0:60d829a0353a	1089
tushki7	0:60d829a0353a	1090	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB Device clock enable /
tushki7	0:60d829a0353a	1091
tushki7	0:60d829a0353a	1092
tushki7	0:60d829a0353a	1093
tushki7	0:60d829a0353a	1094
tushki7	0:60d829a0353a	1095
tushki7	0:60d829a0353a	1096
tushki7	0:60d829a0353a	1097	/***************** Bit definition for RCC_BDCR register *****************/
tushki7	0:60d829a0353a	1098	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
tushki7	0:60d829a0353a	1099	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
tushki7	0:60d829a0353a	1100	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
tushki7	0:60d829a0353a	1101
tushki7	0:60d829a0353a	1102	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
tushki7	0:60d829a0353a	1103	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	1104	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	1105
tushki7	0:60d829a0353a	1106	/!< RTC congiguration /
tushki7	0:60d829a0353a	1107	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
tushki7	0:60d829a0353a	1108	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
tushki7	0:60d829a0353a	1109	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
tushki7	0:60d829a0353a	1110	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
tushki7	0:60d829a0353a	1111
tushki7	0:60d829a0353a	1112	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
tushki7	0:60d829a0353a	1113	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
tushki7	0:60d829a0353a	1114
tushki7	0:60d829a0353a	1115	/***************** Bit definition for RCC_CSR register ******************/
tushki7	0:60d829a0353a	1116	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
tushki7	0:60d829a0353a	1117	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
tushki7	0:60d829a0353a	1118	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
tushki7	0:60d829a0353a	1119	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
tushki7	0:60d829a0353a	1120	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
tushki7	0:60d829a0353a	1121	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
tushki7	0:60d829a0353a	1122	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
tushki7	0:60d829a0353a	1123	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
tushki7	0:60d829a0353a	1124	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
tushki7	0:60d829a0353a	1125
tushki7	0:60d829a0353a	1126
tushki7	0:60d829a0353a	1127
tushki7	0:60d829a0353a	1128	/******************************************************************************/
tushki7	0:60d829a0353a	1129	/* */
tushki7	0:60d829a0353a	1130	/* General Purpose and Alternate Function I/O */
tushki7	0:60d829a0353a	1131	/* */
tushki7	0:60d829a0353a	1132	/******************************************************************************/
tushki7	0:60d829a0353a	1133
tushki7	0:60d829a0353a	1134	/***************** Bit definition for GPIO_CRL register *****************/
tushki7	0:60d829a0353a	1135	#define GPIO_CRL_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
tushki7	0:60d829a0353a	1136
tushki7	0:60d829a0353a	1137	#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
tushki7	0:60d829a0353a	1138	#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1139	#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1140
tushki7	0:60d829a0353a	1141	#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
tushki7	0:60d829a0353a	1142	#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	1143	#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	1144
tushki7	0:60d829a0353a	1145	#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
tushki7	0:60d829a0353a	1146	#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	1147	#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	1148
tushki7	0:60d829a0353a	1149	#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
tushki7	0:60d829a0353a	1150	#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	1151	#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	1152
tushki7	0:60d829a0353a	1153	#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
tushki7	0:60d829a0353a	1154	#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	1155	#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	1156
tushki7	0:60d829a0353a	1157	#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
tushki7	0:60d829a0353a	1158	#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	1159	#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	1160
tushki7	0:60d829a0353a	1161	#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
tushki7	0:60d829a0353a	1162	#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1163	#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1164
tushki7	0:60d829a0353a	1165	#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
tushki7	0:60d829a0353a	1166	#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1167	#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1168
tushki7	0:60d829a0353a	1169	#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
tushki7	0:60d829a0353a	1170
tushki7	0:60d829a0353a	1171	#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
tushki7	0:60d829a0353a	1172	#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /!< Bit 0 /
tushki7	0:60d829a0353a	1173	#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /!< Bit 1 /
tushki7	0:60d829a0353a	1174
tushki7	0:60d829a0353a	1175	#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
tushki7	0:60d829a0353a	1176	#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	1177	#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	1178
tushki7	0:60d829a0353a	1179	#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
tushki7	0:60d829a0353a	1180	#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1181	#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1182
tushki7	0:60d829a0353a	1183	#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
tushki7	0:60d829a0353a	1184	#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /!< Bit 0 /
tushki7	0:60d829a0353a	1185	#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /!< Bit 1 /
tushki7	0:60d829a0353a	1186
tushki7	0:60d829a0353a	1187	#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
tushki7	0:60d829a0353a	1188	#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	1189	#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	1190
tushki7	0:60d829a0353a	1191	#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
tushki7	0:60d829a0353a	1192	#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /!< Bit 0 /
tushki7	0:60d829a0353a	1193	#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /!< Bit 1 /
tushki7	0:60d829a0353a	1194
tushki7	0:60d829a0353a	1195	#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
tushki7	0:60d829a0353a	1196	#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1197	#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1198
tushki7	0:60d829a0353a	1199	#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
tushki7	0:60d829a0353a	1200	#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1201	#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1202
tushki7	0:60d829a0353a	1203	/***************** Bit definition for GPIO_CRH register *****************/
tushki7	0:60d829a0353a	1204	#define GPIO_CRH_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
tushki7	0:60d829a0353a	1205
tushki7	0:60d829a0353a	1206	#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
tushki7	0:60d829a0353a	1207	#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1208	#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1209
tushki7	0:60d829a0353a	1210	#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
tushki7	0:60d829a0353a	1211	#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	1212	#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	1213
tushki7	0:60d829a0353a	1214	#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
tushki7	0:60d829a0353a	1215	#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	1216	#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	1217
tushki7	0:60d829a0353a	1218	#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
tushki7	0:60d829a0353a	1219	#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	1220	#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	1221
tushki7	0:60d829a0353a	1222	#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
tushki7	0:60d829a0353a	1223	#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	1224	#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	1225
tushki7	0:60d829a0353a	1226	#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
tushki7	0:60d829a0353a	1227	#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	1228	#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	1229
tushki7	0:60d829a0353a	1230	#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
tushki7	0:60d829a0353a	1231	#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1232	#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1233
tushki7	0:60d829a0353a	1234	#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
tushki7	0:60d829a0353a	1235	#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1236	#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1237
tushki7	0:60d829a0353a	1238	#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
tushki7	0:60d829a0353a	1239
tushki7	0:60d829a0353a	1240	#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
tushki7	0:60d829a0353a	1241	#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /!< Bit 0 /
tushki7	0:60d829a0353a	1242	#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /!< Bit 1 /
tushki7	0:60d829a0353a	1243
tushki7	0:60d829a0353a	1244	#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
tushki7	0:60d829a0353a	1245	#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	1246	#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	1247
tushki7	0:60d829a0353a	1248	#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
tushki7	0:60d829a0353a	1249	#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1250	#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1251
tushki7	0:60d829a0353a	1252	#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
tushki7	0:60d829a0353a	1253	#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /!< Bit 0 /
tushki7	0:60d829a0353a	1254	#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /!< Bit 1 /
tushki7	0:60d829a0353a	1255
tushki7	0:60d829a0353a	1256	#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
tushki7	0:60d829a0353a	1257	#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	1258	#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	1259
tushki7	0:60d829a0353a	1260	#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
tushki7	0:60d829a0353a	1261	#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /!< Bit 0 /
tushki7	0:60d829a0353a	1262	#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /!< Bit 1 /
tushki7	0:60d829a0353a	1263
tushki7	0:60d829a0353a	1264	#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
tushki7	0:60d829a0353a	1265	#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1266	#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1267
tushki7	0:60d829a0353a	1268	#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
tushki7	0:60d829a0353a	1269	#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1270	#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1271
tushki7	0:60d829a0353a	1272	/!<*************** Bit definition for GPIO_IDR register *****************/
tushki7	0:60d829a0353a	1273	#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /!< Port input data, bit 0 /
tushki7	0:60d829a0353a	1274	#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /!< Port input data, bit 1 /
tushki7	0:60d829a0353a	1275	#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /!< Port input data, bit 2 /
tushki7	0:60d829a0353a	1276	#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /!< Port input data, bit 3 /
tushki7	0:60d829a0353a	1277	#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /!< Port input data, bit 4 /
tushki7	0:60d829a0353a	1278	#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /!< Port input data, bit 5 /
tushki7	0:60d829a0353a	1279	#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /!< Port input data, bit 6 /
tushki7	0:60d829a0353a	1280	#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /!< Port input data, bit 7 /
tushki7	0:60d829a0353a	1281	#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /!< Port input data, bit 8 /
tushki7	0:60d829a0353a	1282	#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /!< Port input data, bit 9 /
tushki7	0:60d829a0353a	1283	#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /!< Port input data, bit 10 /
tushki7	0:60d829a0353a	1284	#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /!< Port input data, bit 11 /
tushki7	0:60d829a0353a	1285	#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /!< Port input data, bit 12 /
tushki7	0:60d829a0353a	1286	#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /!< Port input data, bit 13 /
tushki7	0:60d829a0353a	1287	#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /!< Port input data, bit 14 /
tushki7	0:60d829a0353a	1288	#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /!< Port input data, bit 15 /
tushki7	0:60d829a0353a	1289
tushki7	0:60d829a0353a	1290	/***************** Bit definition for GPIO_ODR register *****************/
tushki7	0:60d829a0353a	1291	#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /!< Port output data, bit 0 /
tushki7	0:60d829a0353a	1292	#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /!< Port output data, bit 1 /
tushki7	0:60d829a0353a	1293	#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /!< Port output data, bit 2 /
tushki7	0:60d829a0353a	1294	#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /!< Port output data, bit 3 /
tushki7	0:60d829a0353a	1295	#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /!< Port output data, bit 4 /
tushki7	0:60d829a0353a	1296	#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /!< Port output data, bit 5 /
tushki7	0:60d829a0353a	1297	#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /!< Port output data, bit 6 /
tushki7	0:60d829a0353a	1298	#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /!< Port output data, bit 7 /
tushki7	0:60d829a0353a	1299	#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /!< Port output data, bit 8 /
tushki7	0:60d829a0353a	1300	#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /!< Port output data, bit 9 /
tushki7	0:60d829a0353a	1301	#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /!< Port output data, bit 10 /
tushki7	0:60d829a0353a	1302	#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /!< Port output data, bit 11 /
tushki7	0:60d829a0353a	1303	#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /!< Port output data, bit 12 /
tushki7	0:60d829a0353a	1304	#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /!< Port output data, bit 13 /
tushki7	0:60d829a0353a	1305	#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /!< Port output data, bit 14 /
tushki7	0:60d829a0353a	1306	#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /!< Port output data, bit 15 /
tushki7	0:60d829a0353a	1307
tushki7	0:60d829a0353a	1308	/**************** Bit definition for GPIO_BSRR register *****************/
tushki7	0:60d829a0353a	1309	#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /!< Port x Set bit 0 /
tushki7	0:60d829a0353a	1310	#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /!< Port x Set bit 1 /
tushki7	0:60d829a0353a	1311	#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /!< Port x Set bit 2 /
tushki7	0:60d829a0353a	1312	#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /!< Port x Set bit 3 /
tushki7	0:60d829a0353a	1313	#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /!< Port x Set bit 4 /
tushki7	0:60d829a0353a	1314	#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /!< Port x Set bit 5 /
tushki7	0:60d829a0353a	1315	#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /!< Port x Set bit 6 /
tushki7	0:60d829a0353a	1316	#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /!< Port x Set bit 7 /
tushki7	0:60d829a0353a	1317	#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /!< Port x Set bit 8 /
tushki7	0:60d829a0353a	1318	#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /!< Port x Set bit 9 /
tushki7	0:60d829a0353a	1319	#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /!< Port x Set bit 10 /
tushki7	0:60d829a0353a	1320	#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /!< Port x Set bit 11 /
tushki7	0:60d829a0353a	1321	#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /!< Port x Set bit 12 /
tushki7	0:60d829a0353a	1322	#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /!< Port x Set bit 13 /
tushki7	0:60d829a0353a	1323	#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /!< Port x Set bit 14 /
tushki7	0:60d829a0353a	1324	#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /!< Port x Set bit 15 /
tushki7	0:60d829a0353a	1325
tushki7	0:60d829a0353a	1326	#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /!< Port x Reset bit 0 /
tushki7	0:60d829a0353a	1327	#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /!< Port x Reset bit 1 /
tushki7	0:60d829a0353a	1328	#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /!< Port x Reset bit 2 /
tushki7	0:60d829a0353a	1329	#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /!< Port x Reset bit 3 /
tushki7	0:60d829a0353a	1330	#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /!< Port x Reset bit 4 /
tushki7	0:60d829a0353a	1331	#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /!< Port x Reset bit 5 /
tushki7	0:60d829a0353a	1332	#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /!< Port x Reset bit 6 /
tushki7	0:60d829a0353a	1333	#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /!< Port x Reset bit 7 /
tushki7	0:60d829a0353a	1334	#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /!< Port x Reset bit 8 /
tushki7	0:60d829a0353a	1335	#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /!< Port x Reset bit 9 /
tushki7	0:60d829a0353a	1336	#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /!< Port x Reset bit 10 /
tushki7	0:60d829a0353a	1337	#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /!< Port x Reset bit 11 /
tushki7	0:60d829a0353a	1338	#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /!< Port x Reset bit 12 /
tushki7	0:60d829a0353a	1339	#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /!< Port x Reset bit 13 /
tushki7	0:60d829a0353a	1340	#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /!< Port x Reset bit 14 /
tushki7	0:60d829a0353a	1341	#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /!< Port x Reset bit 15 /
tushki7	0:60d829a0353a	1342
tushki7	0:60d829a0353a	1343	/***************** Bit definition for GPIO_BRR register *****************/
tushki7	0:60d829a0353a	1344	#define GPIO_BRR_BR0 ((uint32_t)0x0001) /!< Port x Reset bit 0 /
tushki7	0:60d829a0353a	1345	#define GPIO_BRR_BR1 ((uint32_t)0x0002) /!< Port x Reset bit 1 /
tushki7	0:60d829a0353a	1346	#define GPIO_BRR_BR2 ((uint32_t)0x0004) /!< Port x Reset bit 2 /
tushki7	0:60d829a0353a	1347	#define GPIO_BRR_BR3 ((uint32_t)0x0008) /!< Port x Reset bit 3 /
tushki7	0:60d829a0353a	1348	#define GPIO_BRR_BR4 ((uint32_t)0x0010) /!< Port x Reset bit 4 /
tushki7	0:60d829a0353a	1349	#define GPIO_BRR_BR5 ((uint32_t)0x0020) /!< Port x Reset bit 5 /
tushki7	0:60d829a0353a	1350	#define GPIO_BRR_BR6 ((uint32_t)0x0040) /!< Port x Reset bit 6 /
tushki7	0:60d829a0353a	1351	#define GPIO_BRR_BR7 ((uint32_t)0x0080) /!< Port x Reset bit 7 /
tushki7	0:60d829a0353a	1352	#define GPIO_BRR_BR8 ((uint32_t)0x0100) /!< Port x Reset bit 8 /
tushki7	0:60d829a0353a	1353	#define GPIO_BRR_BR9 ((uint32_t)0x0200) /!< Port x Reset bit 9 /
tushki7	0:60d829a0353a	1354	#define GPIO_BRR_BR10 ((uint32_t)0x0400) /!< Port x Reset bit 10 /
tushki7	0:60d829a0353a	1355	#define GPIO_BRR_BR11 ((uint32_t)0x0800) /!< Port x Reset bit 11 /
tushki7	0:60d829a0353a	1356	#define GPIO_BRR_BR12 ((uint32_t)0x1000) /!< Port x Reset bit 12 /
tushki7	0:60d829a0353a	1357	#define GPIO_BRR_BR13 ((uint32_t)0x2000) /!< Port x Reset bit 13 /
tushki7	0:60d829a0353a	1358	#define GPIO_BRR_BR14 ((uint32_t)0x4000) /!< Port x Reset bit 14 /
tushki7	0:60d829a0353a	1359	#define GPIO_BRR_BR15 ((uint32_t)0x8000) /!< Port x Reset bit 15 /
tushki7	0:60d829a0353a	1360
tushki7	0:60d829a0353a	1361	/**************** Bit definition for GPIO_LCKR register *****************/
tushki7	0:60d829a0353a	1362	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /!< Port x Lock bit 0 /
tushki7	0:60d829a0353a	1363	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /!< Port x Lock bit 1 /
tushki7	0:60d829a0353a	1364	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /!< Port x Lock bit 2 /
tushki7	0:60d829a0353a	1365	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /!< Port x Lock bit 3 /
tushki7	0:60d829a0353a	1366	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /!< Port x Lock bit 4 /
tushki7	0:60d829a0353a	1367	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /!< Port x Lock bit 5 /
tushki7	0:60d829a0353a	1368	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /!< Port x Lock bit 6 /
tushki7	0:60d829a0353a	1369	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /!< Port x Lock bit 7 /
tushki7	0:60d829a0353a	1370	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /!< Port x Lock bit 8 /
tushki7	0:60d829a0353a	1371	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /!< Port x Lock bit 9 /
tushki7	0:60d829a0353a	1372	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /!< Port x Lock bit 10 /
tushki7	0:60d829a0353a	1373	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /!< Port x Lock bit 11 /
tushki7	0:60d829a0353a	1374	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /!< Port x Lock bit 12 /
tushki7	0:60d829a0353a	1375	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /!< Port x Lock bit 13 /
tushki7	0:60d829a0353a	1376	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /!< Port x Lock bit 14 /
tushki7	0:60d829a0353a	1377	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /!< Port x Lock bit 15 /
tushki7	0:60d829a0353a	1378	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /!< Lock key /
tushki7	0:60d829a0353a	1379
tushki7	0:60d829a0353a	1380	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	1381
tushki7	0:60d829a0353a	1382	/**************** Bit definition for AFIO_EVCR register *****************/
tushki7	0:60d829a0353a	1383	#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /!< PIN[3:0] bits (Pin selection) /
tushki7	0:60d829a0353a	1384	#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	1385	#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	1386	#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	1387	#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	1388
tushki7	0:60d829a0353a	1389	/!< PIN configuration /
tushki7	0:60d829a0353a	1390	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
tushki7	0:60d829a0353a	1391	#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /!< Pin 1 selected /
tushki7	0:60d829a0353a	1392	#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /!< Pin 2 selected /
tushki7	0:60d829a0353a	1393	#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /!< Pin 3 selected /
tushki7	0:60d829a0353a	1394	#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /!< Pin 4 selected /
tushki7	0:60d829a0353a	1395	#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /!< Pin 5 selected /
tushki7	0:60d829a0353a	1396	#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /!< Pin 6 selected /
tushki7	0:60d829a0353a	1397	#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /!< Pin 7 selected /
tushki7	0:60d829a0353a	1398	#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /!< Pin 8 selected /
tushki7	0:60d829a0353a	1399	#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /!< Pin 9 selected /
tushki7	0:60d829a0353a	1400	#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /!< Pin 10 selected /
tushki7	0:60d829a0353a	1401	#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /!< Pin 11 selected /
tushki7	0:60d829a0353a	1402	#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /!< Pin 12 selected /
tushki7	0:60d829a0353a	1403	#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /!< Pin 13 selected /
tushki7	0:60d829a0353a	1404	#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /!< Pin 14 selected /
tushki7	0:60d829a0353a	1405	#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /!< Pin 15 selected /
tushki7	0:60d829a0353a	1406
tushki7	0:60d829a0353a	1407	#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /!< PORT[2:0] bits (Port selection) /
tushki7	0:60d829a0353a	1408	#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	1409	#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	1410	#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /!< Bit 2 /
tushki7	0:60d829a0353a	1411
tushki7	0:60d829a0353a	1412	/!< PORT configuration /
tushki7	0:60d829a0353a	1413	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
tushki7	0:60d829a0353a	1414	#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /!< Port B selected /
tushki7	0:60d829a0353a	1415	#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /!< Port C selected /
tushki7	0:60d829a0353a	1416	#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /!< Port D selected /
tushki7	0:60d829a0353a	1417	#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /!< Port E selected /
tushki7	0:60d829a0353a	1418
tushki7	0:60d829a0353a	1419	#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /!< Event Output Enable /
tushki7	0:60d829a0353a	1420
tushki7	0:60d829a0353a	1421	/**************** Bit definition for AFIO_MAPR register *****************/
tushki7	0:60d829a0353a	1422	#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /!< SPI1 remapping /
tushki7	0:60d829a0353a	1423	#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /!< I2C1 remapping /
tushki7	0:60d829a0353a	1424	#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /!< USART1 remapping /
tushki7	0:60d829a0353a	1425	#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /!< USART2 remapping /
tushki7	0:60d829a0353a	1426
tushki7	0:60d829a0353a	1427	#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /!< USART3_REMAP[1:0] bits (USART3 remapping) /
tushki7	0:60d829a0353a	1428	#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	1429	#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	1430
tushki7	0:60d829a0353a	1431	/* USART3_REMAP configuration */
tushki7	0:60d829a0353a	1432	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
tushki7	0:60d829a0353a	1433	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
tushki7	0:60d829a0353a	1434	#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
tushki7	0:60d829a0353a	1435
tushki7	0:60d829a0353a	1436	#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
tushki7	0:60d829a0353a	1437	#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	1438	#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	1439
tushki7	0:60d829a0353a	1440	/!< TIM1_REMAP configuration /
tushki7	0:60d829a0353a	1441	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
tushki7	0:60d829a0353a	1442	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
tushki7	0:60d829a0353a	1443	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
tushki7	0:60d829a0353a	1444
tushki7	0:60d829a0353a	1445	#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
tushki7	0:60d829a0353a	1446	#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	1447	#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	1448
tushki7	0:60d829a0353a	1449	/!< TIM2_REMAP configuration /
tushki7	0:60d829a0353a	1450	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
tushki7	0:60d829a0353a	1451	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
tushki7	0:60d829a0353a	1452	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
tushki7	0:60d829a0353a	1453	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
tushki7	0:60d829a0353a	1454
tushki7	0:60d829a0353a	1455	#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
tushki7	0:60d829a0353a	1456	#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	1457	#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	1458
tushki7	0:60d829a0353a	1459	/!< TIM3_REMAP configuration /
tushki7	0:60d829a0353a	1460	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
tushki7	0:60d829a0353a	1461	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
tushki7	0:60d829a0353a	1462	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
tushki7	0:60d829a0353a	1463
tushki7	0:60d829a0353a	1464	#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /!< TIM4_REMAP bit (TIM4 remapping) /
tushki7	0:60d829a0353a	1465
tushki7	0:60d829a0353a	1466	#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) /
tushki7	0:60d829a0353a	1467	#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /!< Bit 0 /
tushki7	0:60d829a0353a	1468	#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /!< Bit 1 /
tushki7	0:60d829a0353a	1469
tushki7	0:60d829a0353a	1470	/!< CAN_REMAP configuration /
tushki7	0:60d829a0353a	1471	#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /!< CANRX mapped to PA11, CANTX mapped to PA12 /
tushki7	0:60d829a0353a	1472	#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /!< CANRX mapped to PB8, CANTX mapped to PB9 /
tushki7	0:60d829a0353a	1473	#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /!< CANRX mapped to PD0, CANTX mapped to PD1 /
tushki7	0:60d829a0353a	1474
tushki7	0:60d829a0353a	1475	#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
tushki7	0:60d829a0353a	1476
tushki7	0:60d829a0353a	1477	/!< SWJ_CFG configuration /
tushki7	0:60d829a0353a	1478	#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
tushki7	0:60d829a0353a	1479	#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	1480	#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	1481	#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /!< Bit 2 /
tushki7	0:60d829a0353a	1482
tushki7	0:60d829a0353a	1483	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
tushki7	0:60d829a0353a	1484	#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
tushki7	0:60d829a0353a	1485	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /!< JTAG-DP Disabled and SW-DP Enabled /
tushki7	0:60d829a0353a	1486	#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /!< JTAG-DP Disabled and SW-DP Disabled /
tushki7	0:60d829a0353a	1487
tushki7	0:60d829a0353a	1488
tushki7	0:60d829a0353a	1489	/*************** Bit definition for AFIO_EXTICR1 register ***************/
tushki7	0:60d829a0353a	1490	#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
tushki7	0:60d829a0353a	1491	#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
tushki7	0:60d829a0353a	1492	#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
tushki7	0:60d829a0353a	1493	#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
tushki7	0:60d829a0353a	1494
tushki7	0:60d829a0353a	1495	/!< EXTI0 configuration /
tushki7	0:60d829a0353a	1496	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
tushki7	0:60d829a0353a	1497	#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
tushki7	0:60d829a0353a	1498	#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
tushki7	0:60d829a0353a	1499	#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
tushki7	0:60d829a0353a	1500	#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
tushki7	0:60d829a0353a	1501	#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
tushki7	0:60d829a0353a	1502	#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!< PG[0] pin /
tushki7	0:60d829a0353a	1503
tushki7	0:60d829a0353a	1504	/!< EXTI1 configuration /
tushki7	0:60d829a0353a	1505	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
tushki7	0:60d829a0353a	1506	#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
tushki7	0:60d829a0353a	1507	#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
tushki7	0:60d829a0353a	1508	#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
tushki7	0:60d829a0353a	1509	#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
tushki7	0:60d829a0353a	1510	#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
tushki7	0:60d829a0353a	1511	#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!< PG[1] pin /
tushki7	0:60d829a0353a	1512
tushki7	0:60d829a0353a	1513	/!< EXTI2 configuration /
tushki7	0:60d829a0353a	1514	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
tushki7	0:60d829a0353a	1515	#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
tushki7	0:60d829a0353a	1516	#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
tushki7	0:60d829a0353a	1517	#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
tushki7	0:60d829a0353a	1518	#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
tushki7	0:60d829a0353a	1519	#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
tushki7	0:60d829a0353a	1520	#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!< PG[2] pin /
tushki7	0:60d829a0353a	1521
tushki7	0:60d829a0353a	1522	/!< EXTI3 configuration /
tushki7	0:60d829a0353a	1523	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
tushki7	0:60d829a0353a	1524	#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
tushki7	0:60d829a0353a	1525	#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
tushki7	0:60d829a0353a	1526	#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
tushki7	0:60d829a0353a	1527	#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
tushki7	0:60d829a0353a	1528	#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
tushki7	0:60d829a0353a	1529	#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!< PG[3] pin /
tushki7	0:60d829a0353a	1530
tushki7	0:60d829a0353a	1531	/*************** Bit definition for AFIO_EXTICR2 register ***************/
tushki7	0:60d829a0353a	1532	#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
tushki7	0:60d829a0353a	1533	#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
tushki7	0:60d829a0353a	1534	#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
tushki7	0:60d829a0353a	1535	#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
tushki7	0:60d829a0353a	1536
tushki7	0:60d829a0353a	1537	/!< EXTI4 configuration /
tushki7	0:60d829a0353a	1538	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
tushki7	0:60d829a0353a	1539	#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
tushki7	0:60d829a0353a	1540	#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
tushki7	0:60d829a0353a	1541	#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
tushki7	0:60d829a0353a	1542	#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
tushki7	0:60d829a0353a	1543	#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
tushki7	0:60d829a0353a	1544	#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!< PG[4] pin /
tushki7	0:60d829a0353a	1545
tushki7	0:60d829a0353a	1546	/* EXTI5 configuration */
tushki7	0:60d829a0353a	1547	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
tushki7	0:60d829a0353a	1548	#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
tushki7	0:60d829a0353a	1549	#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
tushki7	0:60d829a0353a	1550	#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
tushki7	0:60d829a0353a	1551	#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
tushki7	0:60d829a0353a	1552	#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
tushki7	0:60d829a0353a	1553	#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!< PG[5] pin /
tushki7	0:60d829a0353a	1554
tushki7	0:60d829a0353a	1555	/!< EXTI6 configuration /
tushki7	0:60d829a0353a	1556	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
tushki7	0:60d829a0353a	1557	#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
tushki7	0:60d829a0353a	1558	#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
tushki7	0:60d829a0353a	1559	#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
tushki7	0:60d829a0353a	1560	#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
tushki7	0:60d829a0353a	1561	#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
tushki7	0:60d829a0353a	1562	#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!< PG[6] pin /
tushki7	0:60d829a0353a	1563
tushki7	0:60d829a0353a	1564	/!< EXTI7 configuration /
tushki7	0:60d829a0353a	1565	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
tushki7	0:60d829a0353a	1566	#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
tushki7	0:60d829a0353a	1567	#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
tushki7	0:60d829a0353a	1568	#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
tushki7	0:60d829a0353a	1569	#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
tushki7	0:60d829a0353a	1570	#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
tushki7	0:60d829a0353a	1571	#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!< PG[7] pin /
tushki7	0:60d829a0353a	1572
tushki7	0:60d829a0353a	1573	/*************** Bit definition for AFIO_EXTICR3 register ***************/
tushki7	0:60d829a0353a	1574	#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
tushki7	0:60d829a0353a	1575	#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
tushki7	0:60d829a0353a	1576	#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
tushki7	0:60d829a0353a	1577	#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
tushki7	0:60d829a0353a	1578
tushki7	0:60d829a0353a	1579	/!< EXTI8 configuration /
tushki7	0:60d829a0353a	1580	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
tushki7	0:60d829a0353a	1581	#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
tushki7	0:60d829a0353a	1582	#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
tushki7	0:60d829a0353a	1583	#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
tushki7	0:60d829a0353a	1584	#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
tushki7	0:60d829a0353a	1585	#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
tushki7	0:60d829a0353a	1586	#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!< PG[8] pin /
tushki7	0:60d829a0353a	1587
tushki7	0:60d829a0353a	1588	/!< EXTI9 configuration /
tushki7	0:60d829a0353a	1589	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
tushki7	0:60d829a0353a	1590	#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
tushki7	0:60d829a0353a	1591	#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
tushki7	0:60d829a0353a	1592	#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
tushki7	0:60d829a0353a	1593	#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
tushki7	0:60d829a0353a	1594	#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
tushki7	0:60d829a0353a	1595	#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!< PG[9] pin /
tushki7	0:60d829a0353a	1596
tushki7	0:60d829a0353a	1597	/!< EXTI10 configuration /
tushki7	0:60d829a0353a	1598	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
tushki7	0:60d829a0353a	1599	#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
tushki7	0:60d829a0353a	1600	#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
tushki7	0:60d829a0353a	1601	#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
tushki7	0:60d829a0353a	1602	#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
tushki7	0:60d829a0353a	1603	#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
tushki7	0:60d829a0353a	1604	#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!< PG[10] pin /
tushki7	0:60d829a0353a	1605
tushki7	0:60d829a0353a	1606	/!< EXTI11 configuration /
tushki7	0:60d829a0353a	1607	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
tushki7	0:60d829a0353a	1608	#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
tushki7	0:60d829a0353a	1609	#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
tushki7	0:60d829a0353a	1610	#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
tushki7	0:60d829a0353a	1611	#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
tushki7	0:60d829a0353a	1612	#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
tushki7	0:60d829a0353a	1613	#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!< PG[11] pin /
tushki7	0:60d829a0353a	1614
tushki7	0:60d829a0353a	1615	/*************** Bit definition for AFIO_EXTICR4 register ***************/
tushki7	0:60d829a0353a	1616	#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
tushki7	0:60d829a0353a	1617	#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
tushki7	0:60d829a0353a	1618	#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
tushki7	0:60d829a0353a	1619	#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
tushki7	0:60d829a0353a	1620
tushki7	0:60d829a0353a	1621	/* EXTI12 configuration */
tushki7	0:60d829a0353a	1622	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
tushki7	0:60d829a0353a	1623	#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
tushki7	0:60d829a0353a	1624	#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
tushki7	0:60d829a0353a	1625	#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
tushki7	0:60d829a0353a	1626	#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
tushki7	0:60d829a0353a	1627	#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
tushki7	0:60d829a0353a	1628	#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!< PG[12] pin /
tushki7	0:60d829a0353a	1629
tushki7	0:60d829a0353a	1630	/* EXTI13 configuration */
tushki7	0:60d829a0353a	1631	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
tushki7	0:60d829a0353a	1632	#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
tushki7	0:60d829a0353a	1633	#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
tushki7	0:60d829a0353a	1634	#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
tushki7	0:60d829a0353a	1635	#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
tushki7	0:60d829a0353a	1636	#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
tushki7	0:60d829a0353a	1637	#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!< PG[13] pin /
tushki7	0:60d829a0353a	1638
tushki7	0:60d829a0353a	1639	/!< EXTI14 configuration /
tushki7	0:60d829a0353a	1640	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
tushki7	0:60d829a0353a	1641	#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
tushki7	0:60d829a0353a	1642	#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
tushki7	0:60d829a0353a	1643	#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
tushki7	0:60d829a0353a	1644	#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
tushki7	0:60d829a0353a	1645	#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
tushki7	0:60d829a0353a	1646	#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!< PG[14] pin /
tushki7	0:60d829a0353a	1647
tushki7	0:60d829a0353a	1648	/!< EXTI15 configuration /
tushki7	0:60d829a0353a	1649	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
tushki7	0:60d829a0353a	1650	#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
tushki7	0:60d829a0353a	1651	#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
tushki7	0:60d829a0353a	1652	#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
tushki7	0:60d829a0353a	1653	#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
tushki7	0:60d829a0353a	1654	#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
tushki7	0:60d829a0353a	1655	#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!< PG[15] pin /
tushki7	0:60d829a0353a	1656
tushki7	0:60d829a0353a	1657	/**************** Bit definition for AFIO_MAPR2 register ****************/
tushki7	0:60d829a0353a	1658
tushki7	0:60d829a0353a	1659
tushki7	0:60d829a0353a	1660
tushki7	0:60d829a0353a	1661	/******************************************************************************/
tushki7	0:60d829a0353a	1662	/* */
tushki7	0:60d829a0353a	1663	/* SystemTick */
tushki7	0:60d829a0353a	1664	/* */
tushki7	0:60d829a0353a	1665	/******************************************************************************/
tushki7	0:60d829a0353a	1666
tushki7	0:60d829a0353a	1667	/*************** Bit definition for SysTick_CTRL register ***************/
tushki7	0:60d829a0353a	1668	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
tushki7	0:60d829a0353a	1669	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
tushki7	0:60d829a0353a	1670	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
tushki7	0:60d829a0353a	1671	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
tushki7	0:60d829a0353a	1672
tushki7	0:60d829a0353a	1673	/*************** Bit definition for SysTick_LOAD register ***************/
tushki7	0:60d829a0353a	1674	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
tushki7	0:60d829a0353a	1675
tushki7	0:60d829a0353a	1676	/*************** Bit definition for SysTick_VAL register ****************/
tushki7	0:60d829a0353a	1677	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
tushki7	0:60d829a0353a	1678
tushki7	0:60d829a0353a	1679	/*************** Bit definition for SysTick_CALIB register **************/
tushki7	0:60d829a0353a	1680	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
tushki7	0:60d829a0353a	1681	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
tushki7	0:60d829a0353a	1682	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
tushki7	0:60d829a0353a	1683
tushki7	0:60d829a0353a	1684	/******************************************************************************/
tushki7	0:60d829a0353a	1685	/* */
tushki7	0:60d829a0353a	1686	/* Nested Vectored Interrupt Controller */
tushki7	0:60d829a0353a	1687	/* */
tushki7	0:60d829a0353a	1688	/******************************************************************************/
tushki7	0:60d829a0353a	1689
tushki7	0:60d829a0353a	1690	/**************** Bit definition for NVIC_ISER register *****************/
tushki7	0:60d829a0353a	1691	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
tushki7	0:60d829a0353a	1692	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	1693	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	1694	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	1695	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	1696	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	1697	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	1698	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	1699	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	1700	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	1701	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	1702	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	1703	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	1704	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	1705	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	1706	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	1707	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	1708	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	1709	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	1710	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	1711	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	1712	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	1713	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	1714	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	1715	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	1716	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	1717	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	1718	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	1719	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	1720	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	1721	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	1722	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	1723	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	1724
tushki7	0:60d829a0353a	1725	/**************** Bit definition for NVIC_ICER register *****************/
tushki7	0:60d829a0353a	1726	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
tushki7	0:60d829a0353a	1727	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	1728	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	1729	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	1730	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	1731	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	1732	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	1733	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	1734	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	1735	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	1736	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	1737	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	1738	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	1739	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	1740	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	1741	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	1742	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	1743	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	1744	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	1745	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	1746	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	1747	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	1748	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	1749	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	1750	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	1751	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	1752	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	1753	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	1754	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	1755	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	1756	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	1757	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	1758	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	1759
tushki7	0:60d829a0353a	1760	/**************** Bit definition for NVIC_ISPR register *****************/
tushki7	0:60d829a0353a	1761	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
tushki7	0:60d829a0353a	1762	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	1763	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	1764	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	1765	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	1766	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	1767	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	1768	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	1769	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	1770	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	1771	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	1772	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	1773	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	1774	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	1775	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	1776	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	1777	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	1778	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	1779	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	1780	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	1781	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	1782	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	1783	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	1784	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	1785	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	1786	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	1787	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	1788	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	1789	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	1790	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	1791	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	1792	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	1793	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	1794
tushki7	0:60d829a0353a	1795	/**************** Bit definition for NVIC_ICPR register *****************/
tushki7	0:60d829a0353a	1796	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
tushki7	0:60d829a0353a	1797	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	1798	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	1799	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	1800	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	1801	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	1802	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	1803	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	1804	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	1805	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	1806	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	1807	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	1808	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	1809	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	1810	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	1811	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	1812	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	1813	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	1814	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	1815	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	1816	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	1817	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	1818	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	1819	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	1820	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	1821	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	1822	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	1823	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	1824	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	1825	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	1826	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	1827	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	1828	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	1829
tushki7	0:60d829a0353a	1830	/**************** Bit definition for NVIC_IABR register *****************/
tushki7	0:60d829a0353a	1831	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
tushki7	0:60d829a0353a	1832	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
tushki7	0:60d829a0353a	1833	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
tushki7	0:60d829a0353a	1834	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
tushki7	0:60d829a0353a	1835	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
tushki7	0:60d829a0353a	1836	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
tushki7	0:60d829a0353a	1837	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
tushki7	0:60d829a0353a	1838	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
tushki7	0:60d829a0353a	1839	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
tushki7	0:60d829a0353a	1840	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
tushki7	0:60d829a0353a	1841	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
tushki7	0:60d829a0353a	1842	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
tushki7	0:60d829a0353a	1843	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
tushki7	0:60d829a0353a	1844	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
tushki7	0:60d829a0353a	1845	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
tushki7	0:60d829a0353a	1846	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
tushki7	0:60d829a0353a	1847	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
tushki7	0:60d829a0353a	1848	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
tushki7	0:60d829a0353a	1849	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
tushki7	0:60d829a0353a	1850	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
tushki7	0:60d829a0353a	1851	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
tushki7	0:60d829a0353a	1852	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
tushki7	0:60d829a0353a	1853	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
tushki7	0:60d829a0353a	1854	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
tushki7	0:60d829a0353a	1855	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
tushki7	0:60d829a0353a	1856	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
tushki7	0:60d829a0353a	1857	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
tushki7	0:60d829a0353a	1858	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
tushki7	0:60d829a0353a	1859	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
tushki7	0:60d829a0353a	1860	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
tushki7	0:60d829a0353a	1861	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
tushki7	0:60d829a0353a	1862	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
tushki7	0:60d829a0353a	1863	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
tushki7	0:60d829a0353a	1864
tushki7	0:60d829a0353a	1865	/**************** Bit definition for NVIC_PRI0 register *****************/
tushki7	0:60d829a0353a	1866	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
tushki7	0:60d829a0353a	1867	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
tushki7	0:60d829a0353a	1868	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
tushki7	0:60d829a0353a	1869	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
tushki7	0:60d829a0353a	1870
tushki7	0:60d829a0353a	1871	/**************** Bit definition for NVIC_PRI1 register *****************/
tushki7	0:60d829a0353a	1872	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
tushki7	0:60d829a0353a	1873	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
tushki7	0:60d829a0353a	1874	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
tushki7	0:60d829a0353a	1875	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
tushki7	0:60d829a0353a	1876
tushki7	0:60d829a0353a	1877	/**************** Bit definition for NVIC_PRI2 register *****************/
tushki7	0:60d829a0353a	1878	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
tushki7	0:60d829a0353a	1879	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
tushki7	0:60d829a0353a	1880	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
tushki7	0:60d829a0353a	1881	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
tushki7	0:60d829a0353a	1882
tushki7	0:60d829a0353a	1883	/**************** Bit definition for NVIC_PRI3 register *****************/
tushki7	0:60d829a0353a	1884	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
tushki7	0:60d829a0353a	1885	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
tushki7	0:60d829a0353a	1886	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
tushki7	0:60d829a0353a	1887	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
tushki7	0:60d829a0353a	1888
tushki7	0:60d829a0353a	1889	/**************** Bit definition for NVIC_PRI4 register *****************/
tushki7	0:60d829a0353a	1890	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
tushki7	0:60d829a0353a	1891	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
tushki7	0:60d829a0353a	1892	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
tushki7	0:60d829a0353a	1893	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
tushki7	0:60d829a0353a	1894
tushki7	0:60d829a0353a	1895	/**************** Bit definition for NVIC_PRI5 register *****************/
tushki7	0:60d829a0353a	1896	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
tushki7	0:60d829a0353a	1897	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
tushki7	0:60d829a0353a	1898	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
tushki7	0:60d829a0353a	1899	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
tushki7	0:60d829a0353a	1900
tushki7	0:60d829a0353a	1901	/**************** Bit definition for NVIC_PRI6 register *****************/
tushki7	0:60d829a0353a	1902	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
tushki7	0:60d829a0353a	1903	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
tushki7	0:60d829a0353a	1904	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
tushki7	0:60d829a0353a	1905	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
tushki7	0:60d829a0353a	1906
tushki7	0:60d829a0353a	1907	/**************** Bit definition for NVIC_PRI7 register *****************/
tushki7	0:60d829a0353a	1908	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
tushki7	0:60d829a0353a	1909	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
tushki7	0:60d829a0353a	1910	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
tushki7	0:60d829a0353a	1911	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
tushki7	0:60d829a0353a	1912
tushki7	0:60d829a0353a	1913	/**************** Bit definition for SCB_CPUID register *****************/
tushki7	0:60d829a0353a	1914	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
tushki7	0:60d829a0353a	1915	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
tushki7	0:60d829a0353a	1916	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
tushki7	0:60d829a0353a	1917	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
tushki7	0:60d829a0353a	1918	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
tushki7	0:60d829a0353a	1919
tushki7	0:60d829a0353a	1920	/***************** Bit definition for SCB_ICSR register *****************/
tushki7	0:60d829a0353a	1921	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
tushki7	0:60d829a0353a	1922	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
tushki7	0:60d829a0353a	1923	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
tushki7	0:60d829a0353a	1924	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
tushki7	0:60d829a0353a	1925	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
tushki7	0:60d829a0353a	1926	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
tushki7	0:60d829a0353a	1927	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
tushki7	0:60d829a0353a	1928	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
tushki7	0:60d829a0353a	1929	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
tushki7	0:60d829a0353a	1930	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
tushki7	0:60d829a0353a	1931
tushki7	0:60d829a0353a	1932	/***************** Bit definition for SCB_VTOR register *****************/
tushki7	0:60d829a0353a	1933	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
tushki7	0:60d829a0353a	1934	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
tushki7	0:60d829a0353a	1935
tushki7	0:60d829a0353a	1936	/!<************** Bit definition for SCB_AIRCR register *****************/
tushki7	0:60d829a0353a	1937	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
tushki7	0:60d829a0353a	1938	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
tushki7	0:60d829a0353a	1939	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
tushki7	0:60d829a0353a	1940
tushki7	0:60d829a0353a	1941	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
tushki7	0:60d829a0353a	1942	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	1943	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	1944	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
tushki7	0:60d829a0353a	1945
tushki7	0:60d829a0353a	1946	/* prority group configuration */
tushki7	0:60d829a0353a	1947	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
tushki7	0:60d829a0353a	1948	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
tushki7	0:60d829a0353a	1949	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
tushki7	0:60d829a0353a	1950	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
tushki7	0:60d829a0353a	1951	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
tushki7	0:60d829a0353a	1952	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
tushki7	0:60d829a0353a	1953	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
tushki7	0:60d829a0353a	1954	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
tushki7	0:60d829a0353a	1955
tushki7	0:60d829a0353a	1956	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
tushki7	0:60d829a0353a	1957	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
tushki7	0:60d829a0353a	1958
tushki7	0:60d829a0353a	1959	/***************** Bit definition for SCB_SCR register ******************/
tushki7	0:60d829a0353a	1960	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
tushki7	0:60d829a0353a	1961	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
tushki7	0:60d829a0353a	1962	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
tushki7	0:60d829a0353a	1963
tushki7	0:60d829a0353a	1964	/****************** Bit definition for SCB_CCR register *****************/
tushki7	0:60d829a0353a	1965	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
tushki7	0:60d829a0353a	1966	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
tushki7	0:60d829a0353a	1967	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
tushki7	0:60d829a0353a	1968	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
tushki7	0:60d829a0353a	1969	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
tushki7	0:60d829a0353a	1970	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
tushki7	0:60d829a0353a	1971
tushki7	0:60d829a0353a	1972	/***************** Bit definition for SCB_SHPR register ******************/
tushki7	0:60d829a0353a	1973	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
tushki7	0:60d829a0353a	1974	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
tushki7	0:60d829a0353a	1975	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
tushki7	0:60d829a0353a	1976	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
tushki7	0:60d829a0353a	1977
tushki7	0:60d829a0353a	1978	/**************** Bit definition for SCB_SHCSR register *****************/
tushki7	0:60d829a0353a	1979	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
tushki7	0:60d829a0353a	1980	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
tushki7	0:60d829a0353a	1981	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
tushki7	0:60d829a0353a	1982	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
tushki7	0:60d829a0353a	1983	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
tushki7	0:60d829a0353a	1984	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
tushki7	0:60d829a0353a	1985	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
tushki7	0:60d829a0353a	1986	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
tushki7	0:60d829a0353a	1987	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
tushki7	0:60d829a0353a	1988	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
tushki7	0:60d829a0353a	1989	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
tushki7	0:60d829a0353a	1990	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
tushki7	0:60d829a0353a	1991	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
tushki7	0:60d829a0353a	1992	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
tushki7	0:60d829a0353a	1993
tushki7	0:60d829a0353a	1994	/***************** Bit definition for SCB_CFSR register *****************/
tushki7	0:60d829a0353a	1995	/!< MFSR /
tushki7	0:60d829a0353a	1996	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
tushki7	0:60d829a0353a	1997	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
tushki7	0:60d829a0353a	1998	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
tushki7	0:60d829a0353a	1999	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
tushki7	0:60d829a0353a	2000	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
tushki7	0:60d829a0353a	2001	/!< BFSR /
tushki7	0:60d829a0353a	2002	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
tushki7	0:60d829a0353a	2003	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
tushki7	0:60d829a0353a	2004	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
tushki7	0:60d829a0353a	2005	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
tushki7	0:60d829a0353a	2006	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
tushki7	0:60d829a0353a	2007	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
tushki7	0:60d829a0353a	2008	/!< UFSR /
tushki7	0:60d829a0353a	2009	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to execute an undefined instruction /
tushki7	0:60d829a0353a	2010	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
tushki7	0:60d829a0353a	2011	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
tushki7	0:60d829a0353a	2012	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
tushki7	0:60d829a0353a	2013	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
tushki7	0:60d829a0353a	2014	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
tushki7	0:60d829a0353a	2015
tushki7	0:60d829a0353a	2016	/***************** Bit definition for SCB_HFSR register *****************/
tushki7	0:60d829a0353a	2017	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
tushki7	0:60d829a0353a	2018	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
tushki7	0:60d829a0353a	2019	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
tushki7	0:60d829a0353a	2020
tushki7	0:60d829a0353a	2021	/***************** Bit definition for SCB_DFSR register *****************/
tushki7	0:60d829a0353a	2022	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
tushki7	0:60d829a0353a	2023	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
tushki7	0:60d829a0353a	2024	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
tushki7	0:60d829a0353a	2025	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
tushki7	0:60d829a0353a	2026	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
tushki7	0:60d829a0353a	2027
tushki7	0:60d829a0353a	2028	/***************** Bit definition for SCB_MMFAR register ****************/
tushki7	0:60d829a0353a	2029	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
tushki7	0:60d829a0353a	2030
tushki7	0:60d829a0353a	2031	/***************** Bit definition for SCB_BFAR register *****************/
tushki7	0:60d829a0353a	2032	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
tushki7	0:60d829a0353a	2033
tushki7	0:60d829a0353a	2034	/***************** Bit definition for SCB_afsr register *****************/
tushki7	0:60d829a0353a	2035	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
tushki7	0:60d829a0353a	2036
tushki7	0:60d829a0353a	2037	/******************************************************************************/
tushki7	0:60d829a0353a	2038	/* */
tushki7	0:60d829a0353a	2039	/* External Interrupt/Event Controller */
tushki7	0:60d829a0353a	2040	/* */
tushki7	0:60d829a0353a	2041	/******************************************************************************/
tushki7	0:60d829a0353a	2042
tushki7	0:60d829a0353a	2043	/***************** Bit definition for EXTI_IMR register *****************/
tushki7	0:60d829a0353a	2044	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
tushki7	0:60d829a0353a	2045	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
tushki7	0:60d829a0353a	2046	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
tushki7	0:60d829a0353a	2047	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
tushki7	0:60d829a0353a	2048	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
tushki7	0:60d829a0353a	2049	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
tushki7	0:60d829a0353a	2050	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
tushki7	0:60d829a0353a	2051	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
tushki7	0:60d829a0353a	2052	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
tushki7	0:60d829a0353a	2053	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
tushki7	0:60d829a0353a	2054	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
tushki7	0:60d829a0353a	2055	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
tushki7	0:60d829a0353a	2056	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
tushki7	0:60d829a0353a	2057	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
tushki7	0:60d829a0353a	2058	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
tushki7	0:60d829a0353a	2059	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
tushki7	0:60d829a0353a	2060	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
tushki7	0:60d829a0353a	2061	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
tushki7	0:60d829a0353a	2062	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
tushki7	0:60d829a0353a	2063	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
tushki7	0:60d829a0353a	2064
tushki7	0:60d829a0353a	2065	/***************** Bit definition for EXTI_EMR register *****************/
tushki7	0:60d829a0353a	2066	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
tushki7	0:60d829a0353a	2067	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
tushki7	0:60d829a0353a	2068	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
tushki7	0:60d829a0353a	2069	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
tushki7	0:60d829a0353a	2070	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
tushki7	0:60d829a0353a	2071	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
tushki7	0:60d829a0353a	2072	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
tushki7	0:60d829a0353a	2073	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
tushki7	0:60d829a0353a	2074	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
tushki7	0:60d829a0353a	2075	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
tushki7	0:60d829a0353a	2076	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
tushki7	0:60d829a0353a	2077	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
tushki7	0:60d829a0353a	2078	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
tushki7	0:60d829a0353a	2079	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
tushki7	0:60d829a0353a	2080	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
tushki7	0:60d829a0353a	2081	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
tushki7	0:60d829a0353a	2082	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
tushki7	0:60d829a0353a	2083	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
tushki7	0:60d829a0353a	2084	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
tushki7	0:60d829a0353a	2085	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
tushki7	0:60d829a0353a	2086
tushki7	0:60d829a0353a	2087	/**************** Bit definition for EXTI_RTSR register *****************/
tushki7	0:60d829a0353a	2088	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
tushki7	0:60d829a0353a	2089	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
tushki7	0:60d829a0353a	2090	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
tushki7	0:60d829a0353a	2091	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
tushki7	0:60d829a0353a	2092	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
tushki7	0:60d829a0353a	2093	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
tushki7	0:60d829a0353a	2094	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
tushki7	0:60d829a0353a	2095	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
tushki7	0:60d829a0353a	2096	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
tushki7	0:60d829a0353a	2097	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
tushki7	0:60d829a0353a	2098	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
tushki7	0:60d829a0353a	2099	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
tushki7	0:60d829a0353a	2100	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
tushki7	0:60d829a0353a	2101	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
tushki7	0:60d829a0353a	2102	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
tushki7	0:60d829a0353a	2103	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
tushki7	0:60d829a0353a	2104	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
tushki7	0:60d829a0353a	2105	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
tushki7	0:60d829a0353a	2106	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
tushki7	0:60d829a0353a	2107	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
tushki7	0:60d829a0353a	2108
tushki7	0:60d829a0353a	2109	/**************** Bit definition for EXTI_FTSR register *****************/
tushki7	0:60d829a0353a	2110	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
tushki7	0:60d829a0353a	2111	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
tushki7	0:60d829a0353a	2112	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
tushki7	0:60d829a0353a	2113	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
tushki7	0:60d829a0353a	2114	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
tushki7	0:60d829a0353a	2115	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
tushki7	0:60d829a0353a	2116	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
tushki7	0:60d829a0353a	2117	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
tushki7	0:60d829a0353a	2118	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
tushki7	0:60d829a0353a	2119	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
tushki7	0:60d829a0353a	2120	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
tushki7	0:60d829a0353a	2121	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
tushki7	0:60d829a0353a	2122	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
tushki7	0:60d829a0353a	2123	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
tushki7	0:60d829a0353a	2124	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
tushki7	0:60d829a0353a	2125	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
tushki7	0:60d829a0353a	2126	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
tushki7	0:60d829a0353a	2127	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
tushki7	0:60d829a0353a	2128	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
tushki7	0:60d829a0353a	2129	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
tushki7	0:60d829a0353a	2130
tushki7	0:60d829a0353a	2131	/**************** Bit definition for EXTI_SWIER register ****************/
tushki7	0:60d829a0353a	2132	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
tushki7	0:60d829a0353a	2133	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
tushki7	0:60d829a0353a	2134	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
tushki7	0:60d829a0353a	2135	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
tushki7	0:60d829a0353a	2136	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
tushki7	0:60d829a0353a	2137	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
tushki7	0:60d829a0353a	2138	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
tushki7	0:60d829a0353a	2139	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
tushki7	0:60d829a0353a	2140	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
tushki7	0:60d829a0353a	2141	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
tushki7	0:60d829a0353a	2142	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
tushki7	0:60d829a0353a	2143	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
tushki7	0:60d829a0353a	2144	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
tushki7	0:60d829a0353a	2145	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
tushki7	0:60d829a0353a	2146	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
tushki7	0:60d829a0353a	2147	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
tushki7	0:60d829a0353a	2148	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
tushki7	0:60d829a0353a	2149	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
tushki7	0:60d829a0353a	2150	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
tushki7	0:60d829a0353a	2151	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
tushki7	0:60d829a0353a	2152
tushki7	0:60d829a0353a	2153	/***************** Bit definition for EXTI_PR register ******************/
tushki7	0:60d829a0353a	2154	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
tushki7	0:60d829a0353a	2155	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
tushki7	0:60d829a0353a	2156	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
tushki7	0:60d829a0353a	2157	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
tushki7	0:60d829a0353a	2158	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
tushki7	0:60d829a0353a	2159	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
tushki7	0:60d829a0353a	2160	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
tushki7	0:60d829a0353a	2161	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
tushki7	0:60d829a0353a	2162	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
tushki7	0:60d829a0353a	2163	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
tushki7	0:60d829a0353a	2164	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
tushki7	0:60d829a0353a	2165	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
tushki7	0:60d829a0353a	2166	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
tushki7	0:60d829a0353a	2167	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
tushki7	0:60d829a0353a	2168	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
tushki7	0:60d829a0353a	2169	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
tushki7	0:60d829a0353a	2170	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
tushki7	0:60d829a0353a	2171	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
tushki7	0:60d829a0353a	2172	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
tushki7	0:60d829a0353a	2173	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
tushki7	0:60d829a0353a	2174
tushki7	0:60d829a0353a	2175	/******************************************************************************/
tushki7	0:60d829a0353a	2176	/* */
tushki7	0:60d829a0353a	2177	/* DMA Controller */
tushki7	0:60d829a0353a	2178	/* */
tushki7	0:60d829a0353a	2179	/******************************************************************************/
tushki7	0:60d829a0353a	2180
tushki7	0:60d829a0353a	2181	/***************** Bit definition for DMA_ISR register ******************/
tushki7	0:60d829a0353a	2182	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
tushki7	0:60d829a0353a	2183	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
tushki7	0:60d829a0353a	2184	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
tushki7	0:60d829a0353a	2185	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
tushki7	0:60d829a0353a	2186	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
tushki7	0:60d829a0353a	2187	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
tushki7	0:60d829a0353a	2188	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
tushki7	0:60d829a0353a	2189	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
tushki7	0:60d829a0353a	2190	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
tushki7	0:60d829a0353a	2191	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
tushki7	0:60d829a0353a	2192	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
tushki7	0:60d829a0353a	2193	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
tushki7	0:60d829a0353a	2194	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
tushki7	0:60d829a0353a	2195	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
tushki7	0:60d829a0353a	2196	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
tushki7	0:60d829a0353a	2197	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
tushki7	0:60d829a0353a	2198	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
tushki7	0:60d829a0353a	2199	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
tushki7	0:60d829a0353a	2200	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
tushki7	0:60d829a0353a	2201	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
tushki7	0:60d829a0353a	2202	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
tushki7	0:60d829a0353a	2203	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
tushki7	0:60d829a0353a	2204	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
tushki7	0:60d829a0353a	2205	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
tushki7	0:60d829a0353a	2206	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
tushki7	0:60d829a0353a	2207	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
tushki7	0:60d829a0353a	2208	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
tushki7	0:60d829a0353a	2209	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
tushki7	0:60d829a0353a	2210
tushki7	0:60d829a0353a	2211	/***************** Bit definition for DMA_IFCR register *****************/
tushki7	0:60d829a0353a	2212	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
tushki7	0:60d829a0353a	2213	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
tushki7	0:60d829a0353a	2214	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
tushki7	0:60d829a0353a	2215	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
tushki7	0:60d829a0353a	2216	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
tushki7	0:60d829a0353a	2217	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
tushki7	0:60d829a0353a	2218	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
tushki7	0:60d829a0353a	2219	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
tushki7	0:60d829a0353a	2220	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
tushki7	0:60d829a0353a	2221	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
tushki7	0:60d829a0353a	2222	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
tushki7	0:60d829a0353a	2223	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
tushki7	0:60d829a0353a	2224	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
tushki7	0:60d829a0353a	2225	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
tushki7	0:60d829a0353a	2226	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
tushki7	0:60d829a0353a	2227	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
tushki7	0:60d829a0353a	2228	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
tushki7	0:60d829a0353a	2229	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
tushki7	0:60d829a0353a	2230	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
tushki7	0:60d829a0353a	2231	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
tushki7	0:60d829a0353a	2232	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
tushki7	0:60d829a0353a	2233	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
tushki7	0:60d829a0353a	2234	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
tushki7	0:60d829a0353a	2235	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
tushki7	0:60d829a0353a	2236	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
tushki7	0:60d829a0353a	2237	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
tushki7	0:60d829a0353a	2238	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
tushki7	0:60d829a0353a	2239	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
tushki7	0:60d829a0353a	2240
tushki7	0:60d829a0353a	2241	/***************** Bit definition for DMA_CCR register *****************/
tushki7	0:60d829a0353a	2242	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
tushki7	0:60d829a0353a	2243	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
tushki7	0:60d829a0353a	2244	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
tushki7	0:60d829a0353a	2245	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
tushki7	0:60d829a0353a	2246	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
tushki7	0:60d829a0353a	2247	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
tushki7	0:60d829a0353a	2248	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
tushki7	0:60d829a0353a	2249	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
tushki7	0:60d829a0353a	2250
tushki7	0:60d829a0353a	2251	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
tushki7	0:60d829a0353a	2252	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
tushki7	0:60d829a0353a	2253	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
tushki7	0:60d829a0353a	2254
tushki7	0:60d829a0353a	2255	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
tushki7	0:60d829a0353a	2256	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	2257	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	2258
tushki7	0:60d829a0353a	2259	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
tushki7	0:60d829a0353a	2260	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	2261	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	2262
tushki7	0:60d829a0353a	2263	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
tushki7	0:60d829a0353a	2264
tushki7	0:60d829a0353a	2265	/**************** Bit definition for DMA_CNDTR register ****************/
tushki7	0:60d829a0353a	2266	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
tushki7	0:60d829a0353a	2267
tushki7	0:60d829a0353a	2268	/**************** Bit definition for DMA_CPAR register *****************/
tushki7	0:60d829a0353a	2269	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
tushki7	0:60d829a0353a	2270
tushki7	0:60d829a0353a	2271	/**************** Bit definition for DMA_CMAR register *****************/
tushki7	0:60d829a0353a	2272	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
tushki7	0:60d829a0353a	2273
tushki7	0:60d829a0353a	2274	/******************************************************************************/
tushki7	0:60d829a0353a	2275	/* */
tushki7	0:60d829a0353a	2276	/* Analog to Digital Converter */
tushki7	0:60d829a0353a	2277	/* */
tushki7	0:60d829a0353a	2278	/******************************************************************************/
tushki7	0:60d829a0353a	2279
tushki7	0:60d829a0353a	2280	/****************** Bit definition for ADC_SR register ******************/
tushki7	0:60d829a0353a	2281	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
tushki7	0:60d829a0353a	2282	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
tushki7	0:60d829a0353a	2283	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
tushki7	0:60d829a0353a	2284	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
tushki7	0:60d829a0353a	2285	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
tushki7	0:60d829a0353a	2286
tushki7	0:60d829a0353a	2287	/***************** Bit definition for ADC_CR1 register ******************/
tushki7	0:60d829a0353a	2288	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
tushki7	0:60d829a0353a	2289	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2290	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2291	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2292	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	2293	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	2294
tushki7	0:60d829a0353a	2295	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
tushki7	0:60d829a0353a	2296	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
tushki7	0:60d829a0353a	2297	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
tushki7	0:60d829a0353a	2298	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
tushki7	0:60d829a0353a	2299	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
tushki7	0:60d829a0353a	2300	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
tushki7	0:60d829a0353a	2301	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
tushki7	0:60d829a0353a	2302	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
tushki7	0:60d829a0353a	2303
tushki7	0:60d829a0353a	2304	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
tushki7	0:60d829a0353a	2305	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
tushki7	0:60d829a0353a	2306	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
tushki7	0:60d829a0353a	2307	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
tushki7	0:60d829a0353a	2308
tushki7	0:60d829a0353a	2309	#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /!< DUALMOD[3:0] bits (Dual mode selection) /
tushki7	0:60d829a0353a	2310	#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	2311	#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	2312	#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /!< Bit 2 /
tushki7	0:60d829a0353a	2313	#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /!< Bit 3 /
tushki7	0:60d829a0353a	2314
tushki7	0:60d829a0353a	2315	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
tushki7	0:60d829a0353a	2316	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
tushki7	0:60d829a0353a	2317
tushki7	0:60d829a0353a	2318
tushki7	0:60d829a0353a	2319	/***************** Bit definition for ADC_CR2 register ******************/
tushki7	0:60d829a0353a	2320	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
tushki7	0:60d829a0353a	2321	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
tushki7	0:60d829a0353a	2322	#define ADC_CR2_CAL ((uint32_t)0x00000004) /!< A/D Calibration /
tushki7	0:60d829a0353a	2323	#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /!< Reset Calibration /
tushki7	0:60d829a0353a	2324	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
tushki7	0:60d829a0353a	2325	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
tushki7	0:60d829a0353a	2326
tushki7	0:60d829a0353a	2327	#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /!< JEXTSEL[2:0] bits (External event select for injected group) /
tushki7	0:60d829a0353a	2328	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	2329	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	2330	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /!< Bit 2 /
tushki7	0:60d829a0353a	2331
tushki7	0:60d829a0353a	2332	#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /!< External Trigger Conversion mode for injected channels /
tushki7	0:60d829a0353a	2333
tushki7	0:60d829a0353a	2334	#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
tushki7	0:60d829a0353a	2335	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /!< Bit 0 /
tushki7	0:60d829a0353a	2336	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /!< Bit 1 /
tushki7	0:60d829a0353a	2337	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /!< Bit 2 /
tushki7	0:60d829a0353a	2338
tushki7	0:60d829a0353a	2339	#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /!< External Trigger Conversion mode for regular channels /
tushki7	0:60d829a0353a	2340	#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /!< Start Conversion of injected channels /
tushki7	0:60d829a0353a	2341	#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /!< Start Conversion of regular channels /
tushki7	0:60d829a0353a	2342	#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
tushki7	0:60d829a0353a	2343
tushki7	0:60d829a0353a	2344	/**************** Bit definition for ADC_SMPR1 register *****************/
tushki7	0:60d829a0353a	2345	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
tushki7	0:60d829a0353a	2346	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2347	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2348	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2349
tushki7	0:60d829a0353a	2350	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
tushki7	0:60d829a0353a	2351	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
tushki7	0:60d829a0353a	2352	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
tushki7	0:60d829a0353a	2353	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
tushki7	0:60d829a0353a	2354
tushki7	0:60d829a0353a	2355	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
tushki7	0:60d829a0353a	2356	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	2357	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	2358	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
tushki7	0:60d829a0353a	2359
tushki7	0:60d829a0353a	2360	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
tushki7	0:60d829a0353a	2361	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	2362	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	2363	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
tushki7	0:60d829a0353a	2364
tushki7	0:60d829a0353a	2365	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
tushki7	0:60d829a0353a	2366	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	2367	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	2368	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
tushki7	0:60d829a0353a	2369
tushki7	0:60d829a0353a	2370	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 15 Sample time selection) /
tushki7	0:60d829a0353a	2371	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	2372	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	2373	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	2374
tushki7	0:60d829a0353a	2375	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
tushki7	0:60d829a0353a	2376	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	2377	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	2378	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
tushki7	0:60d829a0353a	2379
tushki7	0:60d829a0353a	2380	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
tushki7	0:60d829a0353a	2381	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
tushki7	0:60d829a0353a	2382	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
tushki7	0:60d829a0353a	2383	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
tushki7	0:60d829a0353a	2384
tushki7	0:60d829a0353a	2385	/**************** Bit definition for ADC_SMPR2 register *****************/
tushki7	0:60d829a0353a	2386	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
tushki7	0:60d829a0353a	2387	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2388	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2389	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2390
tushki7	0:60d829a0353a	2391	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
tushki7	0:60d829a0353a	2392	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
tushki7	0:60d829a0353a	2393	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
tushki7	0:60d829a0353a	2394	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
tushki7	0:60d829a0353a	2395
tushki7	0:60d829a0353a	2396	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
tushki7	0:60d829a0353a	2397	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	2398	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	2399	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
tushki7	0:60d829a0353a	2400
tushki7	0:60d829a0353a	2401	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
tushki7	0:60d829a0353a	2402	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	2403	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	2404	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
tushki7	0:60d829a0353a	2405
tushki7	0:60d829a0353a	2406	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
tushki7	0:60d829a0353a	2407	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	2408	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	2409	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
tushki7	0:60d829a0353a	2410
tushki7	0:60d829a0353a	2411	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
tushki7	0:60d829a0353a	2412	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	2413	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	2414	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	2415
tushki7	0:60d829a0353a	2416	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
tushki7	0:60d829a0353a	2417	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
tushki7	0:60d829a0353a	2418	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
tushki7	0:60d829a0353a	2419	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
tushki7	0:60d829a0353a	2420
tushki7	0:60d829a0353a	2421	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
tushki7	0:60d829a0353a	2422	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
tushki7	0:60d829a0353a	2423	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
tushki7	0:60d829a0353a	2424	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
tushki7	0:60d829a0353a	2425
tushki7	0:60d829a0353a	2426	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
tushki7	0:60d829a0353a	2427	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
tushki7	0:60d829a0353a	2428	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
tushki7	0:60d829a0353a	2429	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
tushki7	0:60d829a0353a	2430
tushki7	0:60d829a0353a	2431	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
tushki7	0:60d829a0353a	2432	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
tushki7	0:60d829a0353a	2433	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
tushki7	0:60d829a0353a	2434	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
tushki7	0:60d829a0353a	2435
tushki7	0:60d829a0353a	2436	/**************** Bit definition for ADC_JOFR1 register *****************/
tushki7	0:60d829a0353a	2437	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
tushki7	0:60d829a0353a	2438
tushki7	0:60d829a0353a	2439	/**************** Bit definition for ADC_JOFR2 register *****************/
tushki7	0:60d829a0353a	2440	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
tushki7	0:60d829a0353a	2441
tushki7	0:60d829a0353a	2442	/**************** Bit definition for ADC_JOFR3 register *****************/
tushki7	0:60d829a0353a	2443	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
tushki7	0:60d829a0353a	2444
tushki7	0:60d829a0353a	2445	/**************** Bit definition for ADC_JOFR4 register *****************/
tushki7	0:60d829a0353a	2446	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
tushki7	0:60d829a0353a	2447
tushki7	0:60d829a0353a	2448	/***************** Bit definition for ADC_HTR register ******************/
tushki7	0:60d829a0353a	2449	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
tushki7	0:60d829a0353a	2450
tushki7	0:60d829a0353a	2451	/***************** Bit definition for ADC_LTR register ******************/
tushki7	0:60d829a0353a	2452	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
tushki7	0:60d829a0353a	2453
tushki7	0:60d829a0353a	2454	/***************** Bit definition for ADC_SQR1 register *****************/
tushki7	0:60d829a0353a	2455	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
tushki7	0:60d829a0353a	2456	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2457	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2458	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2459	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	2460	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	2461
tushki7	0:60d829a0353a	2462	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
tushki7	0:60d829a0353a	2463	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	2464	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	2465	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	2466	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	2467	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	2468
tushki7	0:60d829a0353a	2469	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
tushki7	0:60d829a0353a	2470	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	2471	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	2472	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	2473	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	2474	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	2475
tushki7	0:60d829a0353a	2476	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
tushki7	0:60d829a0353a	2477	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	2478	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	2479	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	2480	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	2481	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	2482
tushki7	0:60d829a0353a	2483	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
tushki7	0:60d829a0353a	2484	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	2485	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	2486	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
tushki7	0:60d829a0353a	2487	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
tushki7	0:60d829a0353a	2488
tushki7	0:60d829a0353a	2489	/***************** Bit definition for ADC_SQR2 register *****************/
tushki7	0:60d829a0353a	2490	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
tushki7	0:60d829a0353a	2491	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2492	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2493	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2494	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	2495	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	2496
tushki7	0:60d829a0353a	2497	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
tushki7	0:60d829a0353a	2498	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	2499	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	2500	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	2501	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	2502	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	2503
tushki7	0:60d829a0353a	2504	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
tushki7	0:60d829a0353a	2505	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	2506	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	2507	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	2508	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	2509	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	2510
tushki7	0:60d829a0353a	2511	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
tushki7	0:60d829a0353a	2512	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	2513	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	2514	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	2515	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	2516	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	2517
tushki7	0:60d829a0353a	2518	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
tushki7	0:60d829a0353a	2519	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	2520	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	2521	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
tushki7	0:60d829a0353a	2522	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
tushki7	0:60d829a0353a	2523	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
tushki7	0:60d829a0353a	2524
tushki7	0:60d829a0353a	2525	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
tushki7	0:60d829a0353a	2526	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
tushki7	0:60d829a0353a	2527	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
tushki7	0:60d829a0353a	2528	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
tushki7	0:60d829a0353a	2529	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
tushki7	0:60d829a0353a	2530	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
tushki7	0:60d829a0353a	2531
tushki7	0:60d829a0353a	2532	/***************** Bit definition for ADC_SQR3 register *****************/
tushki7	0:60d829a0353a	2533	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
tushki7	0:60d829a0353a	2534	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2535	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2536	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2537	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	2538	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	2539
tushki7	0:60d829a0353a	2540	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
tushki7	0:60d829a0353a	2541	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	2542	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	2543	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	2544	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	2545	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	2546
tushki7	0:60d829a0353a	2547	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
tushki7	0:60d829a0353a	2548	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	2549	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	2550	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	2551	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	2552	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	2553
tushki7	0:60d829a0353a	2554	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
tushki7	0:60d829a0353a	2555	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	2556	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	2557	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	2558	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	2559	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	2560
tushki7	0:60d829a0353a	2561	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
tushki7	0:60d829a0353a	2562	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	2563	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	2564	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
tushki7	0:60d829a0353a	2565	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
tushki7	0:60d829a0353a	2566	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
tushki7	0:60d829a0353a	2567
tushki7	0:60d829a0353a	2568	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
tushki7	0:60d829a0353a	2569	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
tushki7	0:60d829a0353a	2570	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
tushki7	0:60d829a0353a	2571	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
tushki7	0:60d829a0353a	2572	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
tushki7	0:60d829a0353a	2573	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
tushki7	0:60d829a0353a	2574
tushki7	0:60d829a0353a	2575	/***************** Bit definition for ADC_JSQR register *****************/
tushki7	0:60d829a0353a	2576	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
tushki7	0:60d829a0353a	2577	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2578	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2579	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2580	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	2581	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	2582
tushki7	0:60d829a0353a	2583	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
tushki7	0:60d829a0353a	2584	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
tushki7	0:60d829a0353a	2585	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
tushki7	0:60d829a0353a	2586	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
tushki7	0:60d829a0353a	2587	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
tushki7	0:60d829a0353a	2588	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
tushki7	0:60d829a0353a	2589
tushki7	0:60d829a0353a	2590	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
tushki7	0:60d829a0353a	2591	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	2592	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	2593	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	2594	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	2595	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	2596
tushki7	0:60d829a0353a	2597	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
tushki7	0:60d829a0353a	2598	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
tushki7	0:60d829a0353a	2599	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
tushki7	0:60d829a0353a	2600	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
tushki7	0:60d829a0353a	2601	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
tushki7	0:60d829a0353a	2602	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
tushki7	0:60d829a0353a	2603
tushki7	0:60d829a0353a	2604	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
tushki7	0:60d829a0353a	2605	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
tushki7	0:60d829a0353a	2606	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
tushki7	0:60d829a0353a	2607
tushki7	0:60d829a0353a	2608	/***************** Bit definition for ADC_JDR1 register *****************/
tushki7	0:60d829a0353a	2609	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
tushki7	0:60d829a0353a	2610
tushki7	0:60d829a0353a	2611	/***************** Bit definition for ADC_JDR2 register *****************/
tushki7	0:60d829a0353a	2612	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
tushki7	0:60d829a0353a	2613
tushki7	0:60d829a0353a	2614	/***************** Bit definition for ADC_JDR3 register *****************/
tushki7	0:60d829a0353a	2615	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
tushki7	0:60d829a0353a	2616
tushki7	0:60d829a0353a	2617	/***************** Bit definition for ADC_JDR4 register *****************/
tushki7	0:60d829a0353a	2618	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
tushki7	0:60d829a0353a	2619
tushki7	0:60d829a0353a	2620	/****************** Bit definition for ADC_DR register ******************/
tushki7	0:60d829a0353a	2621	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
tushki7	0:60d829a0353a	2622	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!< ADC2 data /
tushki7	0:60d829a0353a	2623
tushki7	0:60d829a0353a	2624
tushki7	0:60d829a0353a	2625	/*****************************************************************************/
tushki7	0:60d829a0353a	2626	/* */
tushki7	0:60d829a0353a	2627	/* Timers (TIM) */
tushki7	0:60d829a0353a	2628	/* */
tushki7	0:60d829a0353a	2629	/*****************************************************************************/
tushki7	0:60d829a0353a	2630	/***************** Bit definition for TIM_CR1 register *****************/
tushki7	0:60d829a0353a	2631	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
tushki7	0:60d829a0353a	2632	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
tushki7	0:60d829a0353a	2633	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
tushki7	0:60d829a0353a	2634	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
tushki7	0:60d829a0353a	2635	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
tushki7	0:60d829a0353a	2636
tushki7	0:60d829a0353a	2637	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
tushki7	0:60d829a0353a	2638	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
tushki7	0:60d829a0353a	2639	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
tushki7	0:60d829a0353a	2640
tushki7	0:60d829a0353a	2641	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
tushki7	0:60d829a0353a	2642
tushki7	0:60d829a0353a	2643	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
tushki7	0:60d829a0353a	2644	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	2645	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	2646
tushki7	0:60d829a0353a	2647	/***************** Bit definition for TIM_CR2 register *****************/
tushki7	0:60d829a0353a	2648	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
tushki7	0:60d829a0353a	2649	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
tushki7	0:60d829a0353a	2650	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
tushki7	0:60d829a0353a	2651
tushki7	0:60d829a0353a	2652	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
tushki7	0:60d829a0353a	2653	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	2654	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	2655	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	2656
tushki7	0:60d829a0353a	2657	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
tushki7	0:60d829a0353a	2658	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
tushki7	0:60d829a0353a	2659	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
tushki7	0:60d829a0353a	2660	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
tushki7	0:60d829a0353a	2661	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
tushki7	0:60d829a0353a	2662	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
tushki7	0:60d829a0353a	2663	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
tushki7	0:60d829a0353a	2664	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
tushki7	0:60d829a0353a	2665
tushki7	0:60d829a0353a	2666	/***************** Bit definition for TIM_SMCR register ****************/
tushki7	0:60d829a0353a	2667	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
tushki7	0:60d829a0353a	2668	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	2669	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	2670	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
tushki7	0:60d829a0353a	2671
tushki7	0:60d829a0353a	2672	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
tushki7	0:60d829a0353a	2673
tushki7	0:60d829a0353a	2674	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
tushki7	0:60d829a0353a	2675	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	2676	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	2677	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	2678
tushki7	0:60d829a0353a	2679	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
tushki7	0:60d829a0353a	2680
tushki7	0:60d829a0353a	2681	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
tushki7	0:60d829a0353a	2682	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	2683	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	2684	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
tushki7	0:60d829a0353a	2685	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
tushki7	0:60d829a0353a	2686
tushki7	0:60d829a0353a	2687	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
tushki7	0:60d829a0353a	2688	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	2689	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	2690
tushki7	0:60d829a0353a	2691	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
tushki7	0:60d829a0353a	2692	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
tushki7	0:60d829a0353a	2693
tushki7	0:60d829a0353a	2694	/***************** Bit definition for TIM_DIER register ****************/
tushki7	0:60d829a0353a	2695	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
tushki7	0:60d829a0353a	2696	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
tushki7	0:60d829a0353a	2697	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
tushki7	0:60d829a0353a	2698	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
tushki7	0:60d829a0353a	2699	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
tushki7	0:60d829a0353a	2700	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
tushki7	0:60d829a0353a	2701	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
tushki7	0:60d829a0353a	2702	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
tushki7	0:60d829a0353a	2703	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
tushki7	0:60d829a0353a	2704	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
tushki7	0:60d829a0353a	2705	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
tushki7	0:60d829a0353a	2706	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
tushki7	0:60d829a0353a	2707	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
tushki7	0:60d829a0353a	2708	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
tushki7	0:60d829a0353a	2709	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
tushki7	0:60d829a0353a	2710
tushki7	0:60d829a0353a	2711	/****************** Bit definition for TIM_SR register *****************/
tushki7	0:60d829a0353a	2712	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
tushki7	0:60d829a0353a	2713	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
tushki7	0:60d829a0353a	2714	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
tushki7	0:60d829a0353a	2715	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
tushki7	0:60d829a0353a	2716	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
tushki7	0:60d829a0353a	2717	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
tushki7	0:60d829a0353a	2718	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
tushki7	0:60d829a0353a	2719	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
tushki7	0:60d829a0353a	2720	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
tushki7	0:60d829a0353a	2721	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
tushki7	0:60d829a0353a	2722	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
tushki7	0:60d829a0353a	2723	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
tushki7	0:60d829a0353a	2724
tushki7	0:60d829a0353a	2725	/***************** Bit definition for TIM_EGR register *****************/
tushki7	0:60d829a0353a	2726	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
tushki7	0:60d829a0353a	2727	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
tushki7	0:60d829a0353a	2728	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
tushki7	0:60d829a0353a	2729	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
tushki7	0:60d829a0353a	2730	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
tushki7	0:60d829a0353a	2731	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
tushki7	0:60d829a0353a	2732	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
tushki7	0:60d829a0353a	2733	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
tushki7	0:60d829a0353a	2734
tushki7	0:60d829a0353a	2735	/**************** Bit definition for TIM_CCMR1 register ****************/
tushki7	0:60d829a0353a	2736	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
tushki7	0:60d829a0353a	2737	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	2738	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	2739
tushki7	0:60d829a0353a	2740	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
tushki7	0:60d829a0353a	2741	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
tushki7	0:60d829a0353a	2742
tushki7	0:60d829a0353a	2743	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
tushki7	0:60d829a0353a	2744	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	2745	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	2746	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	2747
tushki7	0:60d829a0353a	2748	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
tushki7	0:60d829a0353a	2749
tushki7	0:60d829a0353a	2750	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
tushki7	0:60d829a0353a	2751	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	2752	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	2753
tushki7	0:60d829a0353a	2754	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
tushki7	0:60d829a0353a	2755	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
tushki7	0:60d829a0353a	2756
tushki7	0:60d829a0353a	2757	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
tushki7	0:60d829a0353a	2758	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	2759	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	2760	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
tushki7	0:60d829a0353a	2761
tushki7	0:60d829a0353a	2762	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
tushki7	0:60d829a0353a	2763
tushki7	0:60d829a0353a	2764	/---------------------------------------------------------------------------/
tushki7	0:60d829a0353a	2765
tushki7	0:60d829a0353a	2766	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
tushki7	0:60d829a0353a	2767	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
tushki7	0:60d829a0353a	2768	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
tushki7	0:60d829a0353a	2769
tushki7	0:60d829a0353a	2770	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
tushki7	0:60d829a0353a	2771	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	2772	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	2773	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	2774	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
tushki7	0:60d829a0353a	2775
tushki7	0:60d829a0353a	2776	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
tushki7	0:60d829a0353a	2777	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
tushki7	0:60d829a0353a	2778	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
tushki7	0:60d829a0353a	2779
tushki7	0:60d829a0353a	2780	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
tushki7	0:60d829a0353a	2781	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	2782	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	2783	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
tushki7	0:60d829a0353a	2784	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
tushki7	0:60d829a0353a	2785
tushki7	0:60d829a0353a	2786	/**************** Bit definition for TIM_CCMR2 register ****************/
tushki7	0:60d829a0353a	2787	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
tushki7	0:60d829a0353a	2788	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	2789	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	2790
tushki7	0:60d829a0353a	2791	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
tushki7	0:60d829a0353a	2792	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
tushki7	0:60d829a0353a	2793
tushki7	0:60d829a0353a	2794	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
tushki7	0:60d829a0353a	2795	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	2796	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	2797	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	2798
tushki7	0:60d829a0353a	2799	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
tushki7	0:60d829a0353a	2800
tushki7	0:60d829a0353a	2801	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
tushki7	0:60d829a0353a	2802	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	2803	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	2804
tushki7	0:60d829a0353a	2805	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
tushki7	0:60d829a0353a	2806	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
tushki7	0:60d829a0353a	2807
tushki7	0:60d829a0353a	2808	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
tushki7	0:60d829a0353a	2809	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	2810	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	2811	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
tushki7	0:60d829a0353a	2812
tushki7	0:60d829a0353a	2813	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
tushki7	0:60d829a0353a	2814
tushki7	0:60d829a0353a	2815	/---------------------------------------------------------------------------/
tushki7	0:60d829a0353a	2816
tushki7	0:60d829a0353a	2817	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
tushki7	0:60d829a0353a	2818	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
tushki7	0:60d829a0353a	2819	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
tushki7	0:60d829a0353a	2820
tushki7	0:60d829a0353a	2821	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
tushki7	0:60d829a0353a	2822	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
tushki7	0:60d829a0353a	2823	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
tushki7	0:60d829a0353a	2824	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
tushki7	0:60d829a0353a	2825	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
tushki7	0:60d829a0353a	2826
tushki7	0:60d829a0353a	2827	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
tushki7	0:60d829a0353a	2828	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
tushki7	0:60d829a0353a	2829	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
tushki7	0:60d829a0353a	2830
tushki7	0:60d829a0353a	2831	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
tushki7	0:60d829a0353a	2832	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
tushki7	0:60d829a0353a	2833	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
tushki7	0:60d829a0353a	2834	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
tushki7	0:60d829a0353a	2835	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
tushki7	0:60d829a0353a	2836
tushki7	0:60d829a0353a	2837	/***************** Bit definition for TIM_CCER register ****************/
tushki7	0:60d829a0353a	2838	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
tushki7	0:60d829a0353a	2839	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
tushki7	0:60d829a0353a	2840	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
tushki7	0:60d829a0353a	2841	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
tushki7	0:60d829a0353a	2842	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
tushki7	0:60d829a0353a	2843	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
tushki7	0:60d829a0353a	2844	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
tushki7	0:60d829a0353a	2845	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
tushki7	0:60d829a0353a	2846	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
tushki7	0:60d829a0353a	2847	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
tushki7	0:60d829a0353a	2848	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
tushki7	0:60d829a0353a	2849	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
tushki7	0:60d829a0353a	2850	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
tushki7	0:60d829a0353a	2851	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
tushki7	0:60d829a0353a	2852	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
tushki7	0:60d829a0353a	2853
tushki7	0:60d829a0353a	2854	/***************** Bit definition for TIM_CNT register *****************/
tushki7	0:60d829a0353a	2855	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
tushki7	0:60d829a0353a	2856
tushki7	0:60d829a0353a	2857	/***************** Bit definition for TIM_PSC register *****************/
tushki7	0:60d829a0353a	2858	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
tushki7	0:60d829a0353a	2859
tushki7	0:60d829a0353a	2860	/***************** Bit definition for TIM_ARR register *****************/
tushki7	0:60d829a0353a	2861	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
tushki7	0:60d829a0353a	2862
tushki7	0:60d829a0353a	2863	/***************** Bit definition for TIM_RCR register *****************/
tushki7	0:60d829a0353a	2864	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
tushki7	0:60d829a0353a	2865
tushki7	0:60d829a0353a	2866	/***************** Bit definition for TIM_CCR1 register ****************/
tushki7	0:60d829a0353a	2867	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
tushki7	0:60d829a0353a	2868
tushki7	0:60d829a0353a	2869	/***************** Bit definition for TIM_CCR2 register ****************/
tushki7	0:60d829a0353a	2870	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
tushki7	0:60d829a0353a	2871
tushki7	0:60d829a0353a	2872	/***************** Bit definition for TIM_CCR3 register ****************/
tushki7	0:60d829a0353a	2873	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
tushki7	0:60d829a0353a	2874
tushki7	0:60d829a0353a	2875	/***************** Bit definition for TIM_CCR4 register ****************/
tushki7	0:60d829a0353a	2876	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
tushki7	0:60d829a0353a	2877
tushki7	0:60d829a0353a	2878	/***************** Bit definition for TIM_BDTR register ****************/
tushki7	0:60d829a0353a	2879	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
tushki7	0:60d829a0353a	2880	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	2881	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	2882	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
tushki7	0:60d829a0353a	2883	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
tushki7	0:60d829a0353a	2884	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
tushki7	0:60d829a0353a	2885	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
tushki7	0:60d829a0353a	2886	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
tushki7	0:60d829a0353a	2887	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
tushki7	0:60d829a0353a	2888
tushki7	0:60d829a0353a	2889	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
tushki7	0:60d829a0353a	2890	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	2891	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	2892
tushki7	0:60d829a0353a	2893	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
tushki7	0:60d829a0353a	2894	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
tushki7	0:60d829a0353a	2895	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
tushki7	0:60d829a0353a	2896	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
tushki7	0:60d829a0353a	2897	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
tushki7	0:60d829a0353a	2898	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
tushki7	0:60d829a0353a	2899
tushki7	0:60d829a0353a	2900	/***************** Bit definition for TIM_DCR register *****************/
tushki7	0:60d829a0353a	2901	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
tushki7	0:60d829a0353a	2902	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
tushki7	0:60d829a0353a	2903	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
tushki7	0:60d829a0353a	2904	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
tushki7	0:60d829a0353a	2905	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
tushki7	0:60d829a0353a	2906	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
tushki7	0:60d829a0353a	2907
tushki7	0:60d829a0353a	2908	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
tushki7	0:60d829a0353a	2909	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
tushki7	0:60d829a0353a	2910	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
tushki7	0:60d829a0353a	2911	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
tushki7	0:60d829a0353a	2912	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
tushki7	0:60d829a0353a	2913	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
tushki7	0:60d829a0353a	2914
tushki7	0:60d829a0353a	2915	/***************** Bit definition for TIM_DMAR register ****************/
tushki7	0:60d829a0353a	2916	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
tushki7	0:60d829a0353a	2917
tushki7	0:60d829a0353a	2918	/***************** Bit definition for TIM_OR register ******************/
tushki7	0:60d829a0353a	2919
tushki7	0:60d829a0353a	2920	/******************************************************************************/
tushki7	0:60d829a0353a	2921	/* */
tushki7	0:60d829a0353a	2922	/* Real-Time Clock */
tushki7	0:60d829a0353a	2923	/* */
tushki7	0:60d829a0353a	2924	/******************************************************************************/
tushki7	0:60d829a0353a	2925
tushki7	0:60d829a0353a	2926	/***************** Bit definition for RTC_CRH register ******************/
tushki7	0:60d829a0353a	2927	#define RTC_CRH_SECIE ((uint32_t)0x00000001) /!< Second Interrupt Enable /
tushki7	0:60d829a0353a	2928	#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /!< Alarm Interrupt Enable /
tushki7	0:60d829a0353a	2929	#define RTC_CRH_OWIE ((uint32_t)0x00000004) /!< OverfloW Interrupt Enable /
tushki7	0:60d829a0353a	2930
tushki7	0:60d829a0353a	2931	/***************** Bit definition for RTC_CRL register ******************/
tushki7	0:60d829a0353a	2932	#define RTC_CRL_SECF ((uint32_t)0x00000001) /!< Second Flag /
tushki7	0:60d829a0353a	2933	#define RTC_CRL_ALRF ((uint32_t)0x00000002) /!< Alarm Flag /
tushki7	0:60d829a0353a	2934	#define RTC_CRL_OWF ((uint32_t)0x00000004) /!< OverfloW Flag /
tushki7	0:60d829a0353a	2935	#define RTC_CRL_RSF ((uint32_t)0x00000008) /!< Registers Synchronized Flag /
tushki7	0:60d829a0353a	2936	#define RTC_CRL_CNF ((uint32_t)0x00000010) /!< Configuration Flag /
tushki7	0:60d829a0353a	2937	#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /!< RTC operation OFF /
tushki7	0:60d829a0353a	2938
tushki7	0:60d829a0353a	2939	/***************** Bit definition for RTC_PRLH register *****************/
tushki7	0:60d829a0353a	2940	#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /!< RTC Prescaler Reload Value High /
tushki7	0:60d829a0353a	2941
tushki7	0:60d829a0353a	2942	/***************** Bit definition for RTC_PRLL register *****************/
tushki7	0:60d829a0353a	2943	#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /!< RTC Prescaler Reload Value Low /
tushki7	0:60d829a0353a	2944
tushki7	0:60d829a0353a	2945	/***************** Bit definition for RTC_DIVH register *****************/
tushki7	0:60d829a0353a	2946	#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /!< RTC Clock Divider High /
tushki7	0:60d829a0353a	2947
tushki7	0:60d829a0353a	2948	/***************** Bit definition for RTC_DIVL register *****************/
tushki7	0:60d829a0353a	2949	#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /!< RTC Clock Divider Low /
tushki7	0:60d829a0353a	2950
tushki7	0:60d829a0353a	2951	/***************** Bit definition for RTC_CNTH register *****************/
tushki7	0:60d829a0353a	2952	#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter High /
tushki7	0:60d829a0353a	2953
tushki7	0:60d829a0353a	2954	/***************** Bit definition for RTC_CNTL register *****************/
tushki7	0:60d829a0353a	2955	#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter Low /
tushki7	0:60d829a0353a	2956
tushki7	0:60d829a0353a	2957	/***************** Bit definition for RTC_ALRH register *****************/
tushki7	0:60d829a0353a	2958	#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm High /
tushki7	0:60d829a0353a	2959
tushki7	0:60d829a0353a	2960	/***************** Bit definition for RTC_ALRL register *****************/
tushki7	0:60d829a0353a	2961	#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm Low /
tushki7	0:60d829a0353a	2962
tushki7	0:60d829a0353a	2963	/******************************************************************************/
tushki7	0:60d829a0353a	2964	/* */
tushki7	0:60d829a0353a	2965	/* Independent WATCHDOG (IWDG) */
tushki7	0:60d829a0353a	2966	/* */
tushki7	0:60d829a0353a	2967	/******************************************************************************/
tushki7	0:60d829a0353a	2968
tushki7	0:60d829a0353a	2969	/***************** Bit definition for IWDG_KR register ******************/
tushki7	0:60d829a0353a	2970	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
tushki7	0:60d829a0353a	2971
tushki7	0:60d829a0353a	2972	/***************** Bit definition for IWDG_PR register ******************/
tushki7	0:60d829a0353a	2973	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
tushki7	0:60d829a0353a	2974	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2975	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2976	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2977
tushki7	0:60d829a0353a	2978	/***************** Bit definition for IWDG_RLR register *****************/
tushki7	0:60d829a0353a	2979	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
tushki7	0:60d829a0353a	2980
tushki7	0:60d829a0353a	2981	/***************** Bit definition for IWDG_SR register ******************/
tushki7	0:60d829a0353a	2982	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
tushki7	0:60d829a0353a	2983	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
tushki7	0:60d829a0353a	2984
tushki7	0:60d829a0353a	2985	/******************************************************************************/
tushki7	0:60d829a0353a	2986	/* */
tushki7	0:60d829a0353a	2987	/* Window WATCHDOG */
tushki7	0:60d829a0353a	2988	/* */
tushki7	0:60d829a0353a	2989	/******************************************************************************/
tushki7	0:60d829a0353a	2990
tushki7	0:60d829a0353a	2991	/***************** Bit definition for WWDG_CR register ******************/
tushki7	0:60d829a0353a	2992	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
tushki7	0:60d829a0353a	2993	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	2994	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	2995	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	2996	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	2997	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	2998	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	2999	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3000
tushki7	0:60d829a0353a	3001	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
tushki7	0:60d829a0353a	3002
tushki7	0:60d829a0353a	3003	/***************** Bit definition for WWDG_CFR register *****************/
tushki7	0:60d829a0353a	3004	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
tushki7	0:60d829a0353a	3005	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3006	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3007	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3008	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3009	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3010	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3011	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3012
tushki7	0:60d829a0353a	3013	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
tushki7	0:60d829a0353a	3014	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
tushki7	0:60d829a0353a	3015	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
tushki7	0:60d829a0353a	3016
tushki7	0:60d829a0353a	3017	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
tushki7	0:60d829a0353a	3018
tushki7	0:60d829a0353a	3019	/***************** Bit definition for WWDG_SR register ******************/
tushki7	0:60d829a0353a	3020	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
tushki7	0:60d829a0353a	3021
tushki7	0:60d829a0353a	3022
tushki7	0:60d829a0353a	3023	/******************************************************************************/
tushki7	0:60d829a0353a	3024	/* */
tushki7	0:60d829a0353a	3025	/* SD host Interface */
tushki7	0:60d829a0353a	3026	/* */
tushki7	0:60d829a0353a	3027	/******************************************************************************/
tushki7	0:60d829a0353a	3028
tushki7	0:60d829a0353a	3029	/**************** Bit definition for SDIO_POWER register ****************/
tushki7	0:60d829a0353a	3030	#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
tushki7	0:60d829a0353a	3031	#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /!< Bit 0 /
tushki7	0:60d829a0353a	3032	#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /!< Bit 1 /
tushki7	0:60d829a0353a	3033
tushki7	0:60d829a0353a	3034	/**************** Bit definition for SDIO_CLKCR register ****************/
tushki7	0:60d829a0353a	3035	#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /!< Clock divide factor /
tushki7	0:60d829a0353a	3036	#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /!< Clock enable bit /
tushki7	0:60d829a0353a	3037	#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /!< Power saving configuration bit /
tushki7	0:60d829a0353a	3038	#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /!< Clock divider bypass enable bit /
tushki7	0:60d829a0353a	3039
tushki7	0:60d829a0353a	3040	#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
tushki7	0:60d829a0353a	3041	#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!< Bit 0 /
tushki7	0:60d829a0353a	3042	#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!< Bit 1 /
tushki7	0:60d829a0353a	3043
tushki7	0:60d829a0353a	3044	#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /!< SDIO_CK dephasing selection bit /
tushki7	0:60d829a0353a	3045	#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /!< HW Flow Control enable /
tushki7	0:60d829a0353a	3046
tushki7	0:60d829a0353a	3047	/***************** Bit definition for SDIO_ARG register *****************/
tushki7	0:60d829a0353a	3048	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
tushki7	0:60d829a0353a	3049
tushki7	0:60d829a0353a	3050	/***************** Bit definition for SDIO_CMD register *****************/
tushki7	0:60d829a0353a	3051	#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /!< Command Index /
tushki7	0:60d829a0353a	3052
tushki7	0:60d829a0353a	3053	#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
tushki7	0:60d829a0353a	3054	#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
tushki7	0:60d829a0353a	3055	#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
tushki7	0:60d829a0353a	3056
tushki7	0:60d829a0353a	3057	#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /!< CPSM Waits for Interrupt Request /
tushki7	0:60d829a0353a	3058	#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
tushki7	0:60d829a0353a	3059	#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
tushki7	0:60d829a0353a	3060	#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!< SD I/O suspend command /
tushki7	0:60d829a0353a	3061	#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /!< Enable CMD completion /
tushki7	0:60d829a0353a	3062	#define SDIO_CMD_NIEN ((uint32_t)0x2000) /!< Not Interrupt Enable /
tushki7	0:60d829a0353a	3063	#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /!< CE-ATA command /
tushki7	0:60d829a0353a	3064
tushki7	0:60d829a0353a	3065	/*************** Bit definition for SDIO_RESPCMD register ***************/
tushki7	0:60d829a0353a	3066	#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /!< Response command index /
tushki7	0:60d829a0353a	3067
tushki7	0:60d829a0353a	3068	/**************** Bit definition for SDIO_RESP0 register ****************/
tushki7	0:60d829a0353a	3069	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
tushki7	0:60d829a0353a	3070
tushki7	0:60d829a0353a	3071	/**************** Bit definition for SDIO_RESP1 register ****************/
tushki7	0:60d829a0353a	3072	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
tushki7	0:60d829a0353a	3073
tushki7	0:60d829a0353a	3074	/**************** Bit definition for SDIO_RESP2 register ****************/
tushki7	0:60d829a0353a	3075	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
tushki7	0:60d829a0353a	3076
tushki7	0:60d829a0353a	3077	/**************** Bit definition for SDIO_RESP3 register ****************/
tushki7	0:60d829a0353a	3078	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
tushki7	0:60d829a0353a	3079
tushki7	0:60d829a0353a	3080	/**************** Bit definition for SDIO_RESP4 register ****************/
tushki7	0:60d829a0353a	3081	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
tushki7	0:60d829a0353a	3082
tushki7	0:60d829a0353a	3083	/**************** Bit definition for SDIO_DTIMER register ***************/
tushki7	0:60d829a0353a	3084	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
tushki7	0:60d829a0353a	3085
tushki7	0:60d829a0353a	3086	/**************** Bit definition for SDIO_DLEN register *****************/
tushki7	0:60d829a0353a	3087	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
tushki7	0:60d829a0353a	3088
tushki7	0:60d829a0353a	3089	/**************** Bit definition for SDIO_DCTRL register ****************/
tushki7	0:60d829a0353a	3090	#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /!< Data transfer enabled bit /
tushki7	0:60d829a0353a	3091	#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /!< Data transfer direction selection /
tushki7	0:60d829a0353a	3092	#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /!< Data transfer mode selection /
tushki7	0:60d829a0353a	3093	#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /!< DMA enabled bit /
tushki7	0:60d829a0353a	3094
tushki7	0:60d829a0353a	3095	#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
tushki7	0:60d829a0353a	3096	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!< Bit 0 /
tushki7	0:60d829a0353a	3097	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!< Bit 1 /
tushki7	0:60d829a0353a	3098	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!< Bit 2 /
tushki7	0:60d829a0353a	3099	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!< Bit 3 /
tushki7	0:60d829a0353a	3100
tushki7	0:60d829a0353a	3101	#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /!< Read wait start /
tushki7	0:60d829a0353a	3102	#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /!< Read wait stop /
tushki7	0:60d829a0353a	3103	#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /!< Read wait mode /
tushki7	0:60d829a0353a	3104	#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /!< SD I/O enable functions /
tushki7	0:60d829a0353a	3105
tushki7	0:60d829a0353a	3106	/**************** Bit definition for SDIO_DCOUNT register ***************/
tushki7	0:60d829a0353a	3107	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
tushki7	0:60d829a0353a	3108
tushki7	0:60d829a0353a	3109	/**************** Bit definition for SDIO_STA register ******************/
tushki7	0:60d829a0353a	3110	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
tushki7	0:60d829a0353a	3111	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
tushki7	0:60d829a0353a	3112	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
tushki7	0:60d829a0353a	3113	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
tushki7	0:60d829a0353a	3114	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
tushki7	0:60d829a0353a	3115	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
tushki7	0:60d829a0353a	3116	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
tushki7	0:60d829a0353a	3117	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
tushki7	0:60d829a0353a	3118	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
tushki7	0:60d829a0353a	3119	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
tushki7	0:60d829a0353a	3120	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
tushki7	0:60d829a0353a	3121	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
tushki7	0:60d829a0353a	3122	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
tushki7	0:60d829a0353a	3123	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
tushki7	0:60d829a0353a	3124	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
tushki7	0:60d829a0353a	3125	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
tushki7	0:60d829a0353a	3126	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
tushki7	0:60d829a0353a	3127	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
tushki7	0:60d829a0353a	3128	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
tushki7	0:60d829a0353a	3129	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
tushki7	0:60d829a0353a	3130	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
tushki7	0:60d829a0353a	3131	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
tushki7	0:60d829a0353a	3132	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
tushki7	0:60d829a0353a	3133	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
tushki7	0:60d829a0353a	3134
tushki7	0:60d829a0353a	3135	/***************** Bit definition for SDIO_ICR register *****************/
tushki7	0:60d829a0353a	3136	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
tushki7	0:60d829a0353a	3137	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
tushki7	0:60d829a0353a	3138	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
tushki7	0:60d829a0353a	3139	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
tushki7	0:60d829a0353a	3140	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
tushki7	0:60d829a0353a	3141	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
tushki7	0:60d829a0353a	3142	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
tushki7	0:60d829a0353a	3143	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
tushki7	0:60d829a0353a	3144	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
tushki7	0:60d829a0353a	3145	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
tushki7	0:60d829a0353a	3146	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
tushki7	0:60d829a0353a	3147	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
tushki7	0:60d829a0353a	3148	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
tushki7	0:60d829a0353a	3149
tushki7	0:60d829a0353a	3150	/**************** Bit definition for SDIO_MASK register *****************/
tushki7	0:60d829a0353a	3151	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
tushki7	0:60d829a0353a	3152	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
tushki7	0:60d829a0353a	3153	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
tushki7	0:60d829a0353a	3154	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
tushki7	0:60d829a0353a	3155	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
tushki7	0:60d829a0353a	3156	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
tushki7	0:60d829a0353a	3157	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
tushki7	0:60d829a0353a	3158	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
tushki7	0:60d829a0353a	3159	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
tushki7	0:60d829a0353a	3160	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
tushki7	0:60d829a0353a	3161	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
tushki7	0:60d829a0353a	3162	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
tushki7	0:60d829a0353a	3163	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
tushki7	0:60d829a0353a	3164	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
tushki7	0:60d829a0353a	3165	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
tushki7	0:60d829a0353a	3166	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
tushki7	0:60d829a0353a	3167	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
tushki7	0:60d829a0353a	3168	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
tushki7	0:60d829a0353a	3169	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
tushki7	0:60d829a0353a	3170	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
tushki7	0:60d829a0353a	3171	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
tushki7	0:60d829a0353a	3172	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
tushki7	0:60d829a0353a	3173	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
tushki7	0:60d829a0353a	3174	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
tushki7	0:60d829a0353a	3175
tushki7	0:60d829a0353a	3176	/*************** Bit definition for SDIO_FIFOCNT register ***************/
tushki7	0:60d829a0353a	3177	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
tushki7	0:60d829a0353a	3178
tushki7	0:60d829a0353a	3179	/**************** Bit definition for SDIO_FIFO register *****************/
tushki7	0:60d829a0353a	3180	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
tushki7	0:60d829a0353a	3181
tushki7	0:60d829a0353a	3182	/******************************************************************************/
tushki7	0:60d829a0353a	3183	/* */
tushki7	0:60d829a0353a	3184	/* USB Device FS */
tushki7	0:60d829a0353a	3185	/* */
tushki7	0:60d829a0353a	3186	/******************************************************************************/
tushki7	0:60d829a0353a	3187
tushki7	0:60d829a0353a	3188	/!< Endpoint-specific registers /
tushki7	0:60d829a0353a	3189	#define USB_EP0R USB_BASE /!< Endpoint 0 register address /
tushki7	0:60d829a0353a	3190	#define USB_EP1R (USB_BASE + 0x00000004) /!< Endpoint 1 register address /
tushki7	0:60d829a0353a	3191	#define USB_EP2R (USB_BASE + 0x00000008) /!< Endpoint 2 register address /
tushki7	0:60d829a0353a	3192	#define USB_EP3R (USB_BASE + 0x0000000C) /!< Endpoint 3 register address /
tushki7	0:60d829a0353a	3193	#define USB_EP4R (USB_BASE + 0x00000010) /!< Endpoint 4 register address /
tushki7	0:60d829a0353a	3194	#define USB_EP5R (USB_BASE + 0x00000014) /!< Endpoint 5 register address /
tushki7	0:60d829a0353a	3195	#define USB_EP6R (USB_BASE + 0x00000018) /!< Endpoint 6 register address /
tushki7	0:60d829a0353a	3196	#define USB_EP7R (USB_BASE + 0x0000001C) /!< Endpoint 7 register address /
tushki7	0:60d829a0353a	3197
tushki7	0:60d829a0353a	3198	/* bit positions */
tushki7	0:60d829a0353a	3199	#define USB_EP_CTR_RX ((uint32_t)0x00008000) /!< EndPoint Correct TRansfer RX /
tushki7	0:60d829a0353a	3200	#define USB_EP_DTOG_RX ((uint32_t)0x00004000) /!< EndPoint Data TOGGLE RX /
tushki7	0:60d829a0353a	3201	#define USB_EPRX_STAT ((uint32_t)0x00003000) /!< EndPoint RX STATus bit field /
tushki7	0:60d829a0353a	3202	#define USB_EP_SETUP ((uint32_t)0x00000800) /!< EndPoint SETUP /
tushki7	0:60d829a0353a	3203	#define USB_EP_T_FIELD ((uint32_t)0x00000600) /!< EndPoint TYPE /
tushki7	0:60d829a0353a	3204	#define USB_EP_KIND ((uint32_t)0x00000100) /!< EndPoint KIND /
tushki7	0:60d829a0353a	3205	#define USB_EP_CTR_TX ((uint32_t)0x00000080) /!< EndPoint Correct TRansfer TX /
tushki7	0:60d829a0353a	3206	#define USB_EP_DTOG_TX ((uint32_t)0x00000040) /!< EndPoint Data TOGGLE TX /
tushki7	0:60d829a0353a	3207	#define USB_EPTX_STAT ((uint32_t)0x00000030) /!< EndPoint TX STATus bit field /
tushki7	0:60d829a0353a	3208	#define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /!< EndPoint ADDRess FIELD /
tushki7	0:60d829a0353a	3209
tushki7	0:60d829a0353a	3210	/* EndPoint REGister MASK (no toggle fields) */
tushki7	0:60d829a0353a	3211	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
tushki7	0:60d829a0353a	3212	/!< EP_TYPE[1:0] EndPoint TYPE /
tushki7	0:60d829a0353a	3213	#define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /!< EndPoint TYPE Mask /
tushki7	0:60d829a0353a	3214	#define USB_EP_BULK ((uint32_t)0x00000000) /!< EndPoint BULK /
tushki7	0:60d829a0353a	3215	#define USB_EP_CONTROL ((uint32_t)0x00000200) /!< EndPoint CONTROL /
tushki7	0:60d829a0353a	3216	#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /!< EndPoint ISOCHRONOUS /
tushki7	0:60d829a0353a	3217	#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /!< EndPoint INTERRUPT /
tushki7	0:60d829a0353a	3218	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
tushki7	0:60d829a0353a	3219
tushki7	0:60d829a0353a	3220	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
tushki7	0:60d829a0353a	3221	/!< STAT_TX[1:0] STATus for TX transfer /
tushki7	0:60d829a0353a	3222	#define USB_EP_TX_DIS ((uint32_t)0x00000000) /!< EndPoint TX DISabled /
tushki7	0:60d829a0353a	3223	#define USB_EP_TX_STALL ((uint32_t)0x00000010) /!< EndPoint TX STALLed /
tushki7	0:60d829a0353a	3224	#define USB_EP_TX_NAK ((uint32_t)0x00000020) /!< EndPoint TX NAKed /
tushki7	0:60d829a0353a	3225	#define USB_EP_TX_VALID ((uint32_t)0x00000030) /!< EndPoint TX VALID /
tushki7	0:60d829a0353a	3226	#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /!< EndPoint TX Data TOGgle bit1 /
tushki7	0:60d829a0353a	3227	#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /!< EndPoint TX Data TOGgle bit2 /
tushki7	0:60d829a0353a	3228	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
tushki7	0:60d829a0353a	3229	/!< STAT_RX[1:0] STATus for RX transfer /
tushki7	0:60d829a0353a	3230	#define USB_EP_RX_DIS ((uint32_t)0x00000000) /!< EndPoint RX DISabled /
tushki7	0:60d829a0353a	3231	#define USB_EP_RX_STALL ((uint32_t)0x00001000) /!< EndPoint RX STALLed /
tushki7	0:60d829a0353a	3232	#define USB_EP_RX_NAK ((uint32_t)0x00002000) /!< EndPoint RX NAKed /
tushki7	0:60d829a0353a	3233	#define USB_EP_RX_VALID ((uint32_t)0x00003000) /!< EndPoint RX VALID /
tushki7	0:60d829a0353a	3234	#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /!< EndPoint RX Data TOGgle bit1 /
tushki7	0:60d829a0353a	3235	#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /!< EndPoint RX Data TOGgle bit1 /
tushki7	0:60d829a0353a	3236	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
tushki7	0:60d829a0353a	3237
tushki7	0:60d829a0353a	3238	/***************** Bit definition for USB_EP0R register *****************/
tushki7	0:60d829a0353a	3239	#define USB_EP0R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
tushki7	0:60d829a0353a	3240
tushki7	0:60d829a0353a	3241	#define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	3242	#define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3243	#define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3244
tushki7	0:60d829a0353a	3245	#define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	3246	#define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
tushki7	0:60d829a0353a	3247	#define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
tushki7	0:60d829a0353a	3248
tushki7	0:60d829a0353a	3249	#define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	3250	#define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	3251	#define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	3252
tushki7	0:60d829a0353a	3253	#define USB_EP0R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
tushki7	0:60d829a0353a	3254
tushki7	0:60d829a0353a	3255	#define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	3256	#define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3257	#define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3258
tushki7	0:60d829a0353a	3259	#define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	3260	#define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
tushki7	0:60d829a0353a	3261
tushki7	0:60d829a0353a	3262	/***************** Bit definition for USB_EP1R register *****************/
tushki7	0:60d829a0353a	3263	#define USB_EP1R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
tushki7	0:60d829a0353a	3264
tushki7	0:60d829a0353a	3265	#define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	3266	#define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3267	#define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3268
tushki7	0:60d829a0353a	3269	#define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	3270	#define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
tushki7	0:60d829a0353a	3271	#define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
tushki7	0:60d829a0353a	3272
tushki7	0:60d829a0353a	3273	#define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	3274	#define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	3275	#define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	3276
tushki7	0:60d829a0353a	3277	#define USB_EP1R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
tushki7	0:60d829a0353a	3278
tushki7	0:60d829a0353a	3279	#define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	3280	#define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3281	#define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3282
tushki7	0:60d829a0353a	3283	#define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	3284	#define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
tushki7	0:60d829a0353a	3285
tushki7	0:60d829a0353a	3286	/***************** Bit definition for USB_EP2R register *****************/
tushki7	0:60d829a0353a	3287	#define USB_EP2R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
tushki7	0:60d829a0353a	3288
tushki7	0:60d829a0353a	3289	#define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	3290	#define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3291	#define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3292
tushki7	0:60d829a0353a	3293	#define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	3294	#define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
tushki7	0:60d829a0353a	3295	#define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
tushki7	0:60d829a0353a	3296
tushki7	0:60d829a0353a	3297	#define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	3298	#define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	3299	#define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	3300
tushki7	0:60d829a0353a	3301	#define USB_EP2R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
tushki7	0:60d829a0353a	3302
tushki7	0:60d829a0353a	3303	#define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	3304	#define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3305	#define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3306
tushki7	0:60d829a0353a	3307	#define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	3308	#define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
tushki7	0:60d829a0353a	3309
tushki7	0:60d829a0353a	3310	/***************** Bit definition for USB_EP3R register *****************/
tushki7	0:60d829a0353a	3311	#define USB_EP3R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
tushki7	0:60d829a0353a	3312
tushki7	0:60d829a0353a	3313	#define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	3314	#define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3315	#define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3316
tushki7	0:60d829a0353a	3317	#define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	3318	#define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
tushki7	0:60d829a0353a	3319	#define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
tushki7	0:60d829a0353a	3320
tushki7	0:60d829a0353a	3321	#define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	3322	#define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	3323	#define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	3324
tushki7	0:60d829a0353a	3325	#define USB_EP3R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
tushki7	0:60d829a0353a	3326
tushki7	0:60d829a0353a	3327	#define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	3328	#define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3329	#define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3330
tushki7	0:60d829a0353a	3331	#define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	3332	#define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
tushki7	0:60d829a0353a	3333
tushki7	0:60d829a0353a	3334	/***************** Bit definition for USB_EP4R register *****************/
tushki7	0:60d829a0353a	3335	#define USB_EP4R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
tushki7	0:60d829a0353a	3336
tushki7	0:60d829a0353a	3337	#define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	3338	#define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3339	#define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3340
tushki7	0:60d829a0353a	3341	#define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	3342	#define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
tushki7	0:60d829a0353a	3343	#define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
tushki7	0:60d829a0353a	3344
tushki7	0:60d829a0353a	3345	#define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	3346	#define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	3347	#define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	3348
tushki7	0:60d829a0353a	3349	#define USB_EP4R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
tushki7	0:60d829a0353a	3350
tushki7	0:60d829a0353a	3351	#define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	3352	#define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3353	#define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3354
tushki7	0:60d829a0353a	3355	#define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	3356	#define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
tushki7	0:60d829a0353a	3357
tushki7	0:60d829a0353a	3358	/***************** Bit definition for USB_EP5R register *****************/
tushki7	0:60d829a0353a	3359	#define USB_EP5R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
tushki7	0:60d829a0353a	3360
tushki7	0:60d829a0353a	3361	#define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	3362	#define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3363	#define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3364
tushki7	0:60d829a0353a	3365	#define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	3366	#define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
tushki7	0:60d829a0353a	3367	#define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
tushki7	0:60d829a0353a	3368
tushki7	0:60d829a0353a	3369	#define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	3370	#define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	3371	#define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	3372
tushki7	0:60d829a0353a	3373	#define USB_EP5R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
tushki7	0:60d829a0353a	3374
tushki7	0:60d829a0353a	3375	#define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	3376	#define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3377	#define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3378
tushki7	0:60d829a0353a	3379	#define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	3380	#define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
tushki7	0:60d829a0353a	3381
tushki7	0:60d829a0353a	3382	/***************** Bit definition for USB_EP6R register *****************/
tushki7	0:60d829a0353a	3383	#define USB_EP6R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
tushki7	0:60d829a0353a	3384
tushki7	0:60d829a0353a	3385	#define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	3386	#define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3387	#define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3388
tushki7	0:60d829a0353a	3389	#define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	3390	#define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
tushki7	0:60d829a0353a	3391	#define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
tushki7	0:60d829a0353a	3392
tushki7	0:60d829a0353a	3393	#define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	3394	#define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	3395	#define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	3396
tushki7	0:60d829a0353a	3397	#define USB_EP6R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
tushki7	0:60d829a0353a	3398
tushki7	0:60d829a0353a	3399	#define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	3400	#define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3401	#define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3402
tushki7	0:60d829a0353a	3403	#define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	3404	#define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
tushki7	0:60d829a0353a	3405
tushki7	0:60d829a0353a	3406	/***************** Bit definition for USB_EP7R register *****************/
tushki7	0:60d829a0353a	3407	#define USB_EP7R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
tushki7	0:60d829a0353a	3408
tushki7	0:60d829a0353a	3409	#define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
tushki7	0:60d829a0353a	3410	#define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3411	#define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3412
tushki7	0:60d829a0353a	3413	#define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
tushki7	0:60d829a0353a	3414	#define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
tushki7	0:60d829a0353a	3415	#define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
tushki7	0:60d829a0353a	3416
tushki7	0:60d829a0353a	3417	#define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
tushki7	0:60d829a0353a	3418	#define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
tushki7	0:60d829a0353a	3419	#define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
tushki7	0:60d829a0353a	3420
tushki7	0:60d829a0353a	3421	#define USB_EP7R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
tushki7	0:60d829a0353a	3422
tushki7	0:60d829a0353a	3423	#define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
tushki7	0:60d829a0353a	3424	#define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	3425	#define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	3426
tushki7	0:60d829a0353a	3427	#define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
tushki7	0:60d829a0353a	3428	#define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
tushki7	0:60d829a0353a	3429
tushki7	0:60d829a0353a	3430	/!< Common registers /
tushki7	0:60d829a0353a	3431	/***************** Bit definition for USB_CNTR register *****************/
tushki7	0:60d829a0353a	3432	#define USB_CNTR_FRES ((uint32_t)0x00000001) /!< Force USB Reset /
tushki7	0:60d829a0353a	3433	#define USB_CNTR_PDWN ((uint32_t)0x00000002) /!< Power down /
tushki7	0:60d829a0353a	3434	#define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /!< Low-power mode /
tushki7	0:60d829a0353a	3435	#define USB_CNTR_FSUSP ((uint32_t)0x00000008) /!< Force suspend /
tushki7	0:60d829a0353a	3436	#define USB_CNTR_RESUME ((uint32_t)0x00000010) /!< Resume request /
tushki7	0:60d829a0353a	3437	#define USB_CNTR_ESOFM ((uint32_t)0x00000100) /!< Expected Start Of Frame Interrupt Mask /
tushki7	0:60d829a0353a	3438	#define USB_CNTR_SOFM ((uint32_t)0x00000200) /!< Start Of Frame Interrupt Mask /
tushki7	0:60d829a0353a	3439	#define USB_CNTR_RESETM ((uint32_t)0x00000400) /!< RESET Interrupt Mask /
tushki7	0:60d829a0353a	3440	#define USB_CNTR_SUSPM ((uint32_t)0x00000800) /!< Suspend mode Interrupt Mask /
tushki7	0:60d829a0353a	3441	#define USB_CNTR_WKUPM ((uint32_t)0x00001000) /!< Wakeup Interrupt Mask /
tushki7	0:60d829a0353a	3442	#define USB_CNTR_ERRM ((uint32_t)0x00002000) /!< Error Interrupt Mask /
tushki7	0:60d829a0353a	3443	#define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /!< Packet Memory Area Over / Underrun Interrupt Mask /
tushki7	0:60d829a0353a	3444	#define USB_CNTR_CTRM ((uint32_t)0x00008000) /!< Correct Transfer Interrupt Mask /
tushki7	0:60d829a0353a	3445
tushki7	0:60d829a0353a	3446	/***************** Bit definition for USB_ISTR register *****************/
tushki7	0:60d829a0353a	3447	#define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /!< Endpoint Identifier /
tushki7	0:60d829a0353a	3448	#define USB_ISTR_DIR ((uint32_t)0x00000010) /!< Direction of transaction /
tushki7	0:60d829a0353a	3449	#define USB_ISTR_ESOF ((uint32_t)0x00000100) /!< Expected Start Of Frame /
tushki7	0:60d829a0353a	3450	#define USB_ISTR_SOF ((uint32_t)0x00000200) /!< Start Of Frame /
tushki7	0:60d829a0353a	3451	#define USB_ISTR_RESET ((uint32_t)0x00000400) /!< USB RESET request /
tushki7	0:60d829a0353a	3452	#define USB_ISTR_SUSP ((uint32_t)0x00000800) /!< Suspend mode request /
tushki7	0:60d829a0353a	3453	#define USB_ISTR_WKUP ((uint32_t)0x00001000) /!< Wake up /
tushki7	0:60d829a0353a	3454	#define USB_ISTR_ERR ((uint32_t)0x00002000) /!< Error /
tushki7	0:60d829a0353a	3455	#define USB_ISTR_PMAOVR ((uint32_t)0x00004000) /!< Packet Memory Area Over / Underrun /
tushki7	0:60d829a0353a	3456	#define USB_ISTR_CTR ((uint32_t)0x00008000) /!< Correct Transfer /
tushki7	0:60d829a0353a	3457
tushki7	0:60d829a0353a	3458	/***************** Bit definition for USB_FNR register ******************/
tushki7	0:60d829a0353a	3459	#define USB_FNR_FN ((uint32_t)0x000007FF) /!< Frame Number /
tushki7	0:60d829a0353a	3460	#define USB_FNR_LSOF ((uint32_t)0x00001800) /!< Lost SOF /
tushki7	0:60d829a0353a	3461	#define USB_FNR_LCK ((uint32_t)0x00002000) /!< Locked /
tushki7	0:60d829a0353a	3462	#define USB_FNR_RXDM ((uint32_t)0x00004000) /!< Receive Data - Line Status /
tushki7	0:60d829a0353a	3463	#define USB_FNR_RXDP ((uint32_t)0x00008000) /!< Receive Data + Line Status /
tushki7	0:60d829a0353a	3464
tushki7	0:60d829a0353a	3465	/**************** Bit definition for USB_DADDR register *****************/
tushki7	0:60d829a0353a	3466	#define USB_DADDR_ADD ((uint32_t)0x0000007F) /!< ADD[6:0] bits (Device Address) /
tushki7	0:60d829a0353a	3467	#define USB_DADDR_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	3468	#define USB_DADDR_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	3469	#define USB_DADDR_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	3470	#define USB_DADDR_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	3471	#define USB_DADDR_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	3472	#define USB_DADDR_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	3473	#define USB_DADDR_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	3474
tushki7	0:60d829a0353a	3475	#define USB_DADDR_EF ((uint32_t)0x00000080) /!< Enable Function /
tushki7	0:60d829a0353a	3476
tushki7	0:60d829a0353a	3477	/**************** Bit definition for USB_BTABLE register ****************/
tushki7	0:60d829a0353a	3478	#define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /!< Buffer Table /
tushki7	0:60d829a0353a	3479
tushki7	0:60d829a0353a	3480	/!< Buffer descriptor table /
tushki7	0:60d829a0353a	3481	/*************** Bit definition for USB_ADDR0_TX register ***************/
tushki7	0:60d829a0353a	3482	#define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 0 /
tushki7	0:60d829a0353a	3483
tushki7	0:60d829a0353a	3484	/*************** Bit definition for USB_ADDR1_TX register ***************/
tushki7	0:60d829a0353a	3485	#define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 1 /
tushki7	0:60d829a0353a	3486
tushki7	0:60d829a0353a	3487	/*************** Bit definition for USB_ADDR2_TX register ***************/
tushki7	0:60d829a0353a	3488	#define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 2 /
tushki7	0:60d829a0353a	3489
tushki7	0:60d829a0353a	3490	/*************** Bit definition for USB_ADDR3_TX register ***************/
tushki7	0:60d829a0353a	3491	#define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 3 /
tushki7	0:60d829a0353a	3492
tushki7	0:60d829a0353a	3493	/*************** Bit definition for USB_ADDR4_TX register ***************/
tushki7	0:60d829a0353a	3494	#define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 4 /
tushki7	0:60d829a0353a	3495
tushki7	0:60d829a0353a	3496	/*************** Bit definition for USB_ADDR5_TX register ***************/
tushki7	0:60d829a0353a	3497	#define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 5 /
tushki7	0:60d829a0353a	3498
tushki7	0:60d829a0353a	3499	/*************** Bit definition for USB_ADDR6_TX register ***************/
tushki7	0:60d829a0353a	3500	#define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 6 /
tushki7	0:60d829a0353a	3501
tushki7	0:60d829a0353a	3502	/*************** Bit definition for USB_ADDR7_TX register ***************/
tushki7	0:60d829a0353a	3503	#define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 7 /
tushki7	0:60d829a0353a	3504
tushki7	0:60d829a0353a	3505	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	3506
tushki7	0:60d829a0353a	3507	/*************** Bit definition for USB_COUNT0_TX register **************/
tushki7	0:60d829a0353a	3508	#define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 /
tushki7	0:60d829a0353a	3509
tushki7	0:60d829a0353a	3510	/*************** Bit definition for USB_COUNT1_TX register **************/
tushki7	0:60d829a0353a	3511	#define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 /
tushki7	0:60d829a0353a	3512
tushki7	0:60d829a0353a	3513	/*************** Bit definition for USB_COUNT2_TX register **************/
tushki7	0:60d829a0353a	3514	#define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 /
tushki7	0:60d829a0353a	3515
tushki7	0:60d829a0353a	3516	/*************** Bit definition for USB_COUNT3_TX register **************/
tushki7	0:60d829a0353a	3517	#define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 /
tushki7	0:60d829a0353a	3518
tushki7	0:60d829a0353a	3519	/*************** Bit definition for USB_COUNT4_TX register **************/
tushki7	0:60d829a0353a	3520	#define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 /
tushki7	0:60d829a0353a	3521
tushki7	0:60d829a0353a	3522	/*************** Bit definition for USB_COUNT5_TX register **************/
tushki7	0:60d829a0353a	3523	#define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 /
tushki7	0:60d829a0353a	3524
tushki7	0:60d829a0353a	3525	/*************** Bit definition for USB_COUNT6_TX register **************/
tushki7	0:60d829a0353a	3526	#define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 /
tushki7	0:60d829a0353a	3527
tushki7	0:60d829a0353a	3528	/*************** Bit definition for USB_COUNT7_TX register **************/
tushki7	0:60d829a0353a	3529	#define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 /
tushki7	0:60d829a0353a	3530
tushki7	0:60d829a0353a	3531	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	3532
tushki7	0:60d829a0353a	3533	/************** Bit definition for USB_COUNT0_TX_0 register *************/
tushki7	0:60d829a0353a	3534	#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 (low) /
tushki7	0:60d829a0353a	3535
tushki7	0:60d829a0353a	3536	/************** Bit definition for USB_COUNT0_TX_1 register *************/
tushki7	0:60d829a0353a	3537	#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 0 (high) /
tushki7	0:60d829a0353a	3538
tushki7	0:60d829a0353a	3539	/************** Bit definition for USB_COUNT1_TX_0 register *************/
tushki7	0:60d829a0353a	3540	#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 (low) /
tushki7	0:60d829a0353a	3541
tushki7	0:60d829a0353a	3542	/************** Bit definition for USB_COUNT1_TX_1 register *************/
tushki7	0:60d829a0353a	3543	#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 1 (high) /
tushki7	0:60d829a0353a	3544
tushki7	0:60d829a0353a	3545	/************** Bit definition for USB_COUNT2_TX_0 register *************/
tushki7	0:60d829a0353a	3546	#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 (low) /
tushki7	0:60d829a0353a	3547
tushki7	0:60d829a0353a	3548	/************** Bit definition for USB_COUNT2_TX_1 register *************/
tushki7	0:60d829a0353a	3549	#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 2 (high) /
tushki7	0:60d829a0353a	3550
tushki7	0:60d829a0353a	3551	/************** Bit definition for USB_COUNT3_TX_0 register *************/
tushki7	0:60d829a0353a	3552	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 (low) /
tushki7	0:60d829a0353a	3553
tushki7	0:60d829a0353a	3554	/************** Bit definition for USB_COUNT3_TX_1 register *************/
tushki7	0:60d829a0353a	3555	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 3 (high) /
tushki7	0:60d829a0353a	3556
tushki7	0:60d829a0353a	3557	/************** Bit definition for USB_COUNT4_TX_0 register *************/
tushki7	0:60d829a0353a	3558	#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 (low) /
tushki7	0:60d829a0353a	3559
tushki7	0:60d829a0353a	3560	/************** Bit definition for USB_COUNT4_TX_1 register *************/
tushki7	0:60d829a0353a	3561	#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 4 (high) /
tushki7	0:60d829a0353a	3562
tushki7	0:60d829a0353a	3563	/************** Bit definition for USB_COUNT5_TX_0 register *************/
tushki7	0:60d829a0353a	3564	#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 (low) /
tushki7	0:60d829a0353a	3565
tushki7	0:60d829a0353a	3566	/************** Bit definition for USB_COUNT5_TX_1 register *************/
tushki7	0:60d829a0353a	3567	#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 5 (high) /
tushki7	0:60d829a0353a	3568
tushki7	0:60d829a0353a	3569	/************** Bit definition for USB_COUNT6_TX_0 register *************/
tushki7	0:60d829a0353a	3570	#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 (low) /
tushki7	0:60d829a0353a	3571
tushki7	0:60d829a0353a	3572	/************** Bit definition for USB_COUNT6_TX_1 register *************/
tushki7	0:60d829a0353a	3573	#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 6 (high) /
tushki7	0:60d829a0353a	3574
tushki7	0:60d829a0353a	3575	/************** Bit definition for USB_COUNT7_TX_0 register *************/
tushki7	0:60d829a0353a	3576	#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 (low) /
tushki7	0:60d829a0353a	3577
tushki7	0:60d829a0353a	3578	/************** Bit definition for USB_COUNT7_TX_1 register *************/
tushki7	0:60d829a0353a	3579	#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 7 (high) /
tushki7	0:60d829a0353a	3580
tushki7	0:60d829a0353a	3581	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	3582
tushki7	0:60d829a0353a	3583	/*************** Bit definition for USB_ADDR0_RX register ***************/
tushki7	0:60d829a0353a	3584	#define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 0 /
tushki7	0:60d829a0353a	3585
tushki7	0:60d829a0353a	3586	/*************** Bit definition for USB_ADDR1_RX register ***************/
tushki7	0:60d829a0353a	3587	#define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 1 /
tushki7	0:60d829a0353a	3588
tushki7	0:60d829a0353a	3589	/*************** Bit definition for USB_ADDR2_RX register ***************/
tushki7	0:60d829a0353a	3590	#define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 2 /
tushki7	0:60d829a0353a	3591
tushki7	0:60d829a0353a	3592	/*************** Bit definition for USB_ADDR3_RX register ***************/
tushki7	0:60d829a0353a	3593	#define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 3 /
tushki7	0:60d829a0353a	3594
tushki7	0:60d829a0353a	3595	/*************** Bit definition for USB_ADDR4_RX register ***************/
tushki7	0:60d829a0353a	3596	#define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 4 /
tushki7	0:60d829a0353a	3597
tushki7	0:60d829a0353a	3598	/*************** Bit definition for USB_ADDR5_RX register ***************/
tushki7	0:60d829a0353a	3599	#define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 5 /
tushki7	0:60d829a0353a	3600
tushki7	0:60d829a0353a	3601	/*************** Bit definition for USB_ADDR6_RX register ***************/
tushki7	0:60d829a0353a	3602	#define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 6 /
tushki7	0:60d829a0353a	3603
tushki7	0:60d829a0353a	3604	/*************** Bit definition for USB_ADDR7_RX register ***************/
tushki7	0:60d829a0353a	3605	#define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 7 /
tushki7	0:60d829a0353a	3606
tushki7	0:60d829a0353a	3607	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	3608
tushki7	0:60d829a0353a	3609	/*************** Bit definition for USB_COUNT0_RX register **************/
tushki7	0:60d829a0353a	3610	#define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	3611
tushki7	0:60d829a0353a	3612	#define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	3613	#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3614	#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3615	#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3616	#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3617	#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3618
tushki7	0:60d829a0353a	3619	#define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	3620
tushki7	0:60d829a0353a	3621	/*************** Bit definition for USB_COUNT1_RX register **************/
tushki7	0:60d829a0353a	3622	#define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	3623
tushki7	0:60d829a0353a	3624	#define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	3625	#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3626	#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3627	#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3628	#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3629	#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3630
tushki7	0:60d829a0353a	3631	#define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	3632
tushki7	0:60d829a0353a	3633	/*************** Bit definition for USB_COUNT2_RX register **************/
tushki7	0:60d829a0353a	3634	#define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	3635
tushki7	0:60d829a0353a	3636	#define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	3637	#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3638	#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3639	#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3640	#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3641	#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3642
tushki7	0:60d829a0353a	3643	#define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	3644
tushki7	0:60d829a0353a	3645	/*************** Bit definition for USB_COUNT3_RX register **************/
tushki7	0:60d829a0353a	3646	#define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	3647
tushki7	0:60d829a0353a	3648	#define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	3649	#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3650	#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3651	#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3652	#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3653	#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3654
tushki7	0:60d829a0353a	3655	#define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	3656
tushki7	0:60d829a0353a	3657	/*************** Bit definition for USB_COUNT4_RX register **************/
tushki7	0:60d829a0353a	3658	#define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	3659
tushki7	0:60d829a0353a	3660	#define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	3661	#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3662	#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3663	#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3664	#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3665	#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3666
tushki7	0:60d829a0353a	3667	#define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	3668
tushki7	0:60d829a0353a	3669	/*************** Bit definition for USB_COUNT5_RX register **************/
tushki7	0:60d829a0353a	3670	#define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	3671
tushki7	0:60d829a0353a	3672	#define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	3673	#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3674	#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3675	#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3676	#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3677	#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3678
tushki7	0:60d829a0353a	3679	#define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	3680
tushki7	0:60d829a0353a	3681	/*************** Bit definition for USB_COUNT6_RX register **************/
tushki7	0:60d829a0353a	3682	#define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	3683
tushki7	0:60d829a0353a	3684	#define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	3685	#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3686	#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3687	#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3688	#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3689	#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3690
tushki7	0:60d829a0353a	3691	#define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	3692
tushki7	0:60d829a0353a	3693	/*************** Bit definition for USB_COUNT7_RX register **************/
tushki7	0:60d829a0353a	3694	#define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
tushki7	0:60d829a0353a	3695
tushki7	0:60d829a0353a	3696	#define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
tushki7	0:60d829a0353a	3697	#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3698	#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3699	#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3700	#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3701	#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3702
tushki7	0:60d829a0353a	3703	#define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
tushki7	0:60d829a0353a	3704
tushki7	0:60d829a0353a	3705	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	3706
tushki7	0:60d829a0353a	3707	/************** Bit definition for USB_COUNT0_RX_0 register *************/
tushki7	0:60d829a0353a	3708	#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	3709
tushki7	0:60d829a0353a	3710	#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	3711	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3712	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3713	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3714	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3715	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3716
tushki7	0:60d829a0353a	3717	#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	3718
tushki7	0:60d829a0353a	3719	/************** Bit definition for USB_COUNT0_RX_1 register *************/
tushki7	0:60d829a0353a	3720	#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	3721
tushki7	0:60d829a0353a	3722	#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	3723	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3724	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3725	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	3726	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	3727	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	3728
tushki7	0:60d829a0353a	3729	#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	3730
tushki7	0:60d829a0353a	3731	/************** Bit definition for USB_COUNT1_RX_0 register *************/
tushki7	0:60d829a0353a	3732	#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	3733
tushki7	0:60d829a0353a	3734	#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	3735	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3736	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3737	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3738	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3739	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3740
tushki7	0:60d829a0353a	3741	#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	3742
tushki7	0:60d829a0353a	3743	/************** Bit definition for USB_COUNT1_RX_1 register *************/
tushki7	0:60d829a0353a	3744	#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	3745
tushki7	0:60d829a0353a	3746	#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	3747	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	3748	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3749	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	3750	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	3751	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	3752
tushki7	0:60d829a0353a	3753	#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	3754
tushki7	0:60d829a0353a	3755	/************** Bit definition for USB_COUNT2_RX_0 register *************/
tushki7	0:60d829a0353a	3756	#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	3757
tushki7	0:60d829a0353a	3758	#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	3759	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3760	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3761	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3762	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3763	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3764
tushki7	0:60d829a0353a	3765	#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	3766
tushki7	0:60d829a0353a	3767	/************** Bit definition for USB_COUNT2_RX_1 register *************/
tushki7	0:60d829a0353a	3768	#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	3769
tushki7	0:60d829a0353a	3770	#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	3771	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	3772	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3773	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	3774	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	3775	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	3776
tushki7	0:60d829a0353a	3777	#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	3778
tushki7	0:60d829a0353a	3779	/************** Bit definition for USB_COUNT3_RX_0 register *************/
tushki7	0:60d829a0353a	3780	#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	3781
tushki7	0:60d829a0353a	3782	#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	3783	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3784	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3785	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3786	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3787	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3788
tushki7	0:60d829a0353a	3789	#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	3790
tushki7	0:60d829a0353a	3791	/************** Bit definition for USB_COUNT3_RX_1 register *************/
tushki7	0:60d829a0353a	3792	#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	3793
tushki7	0:60d829a0353a	3794	#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	3795	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	3796	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3797	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	3798	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	3799	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	3800
tushki7	0:60d829a0353a	3801	#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	3802
tushki7	0:60d829a0353a	3803	/************** Bit definition for USB_COUNT4_RX_0 register *************/
tushki7	0:60d829a0353a	3804	#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	3805
tushki7	0:60d829a0353a	3806	#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	3807	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3808	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3809	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3810	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3811	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3812
tushki7	0:60d829a0353a	3813	#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	3814
tushki7	0:60d829a0353a	3815	/************** Bit definition for USB_COUNT4_RX_1 register *************/
tushki7	0:60d829a0353a	3816	#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	3817
tushki7	0:60d829a0353a	3818	#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	3819	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	3820	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3821	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	3822	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	3823	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	3824
tushki7	0:60d829a0353a	3825	#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	3826
tushki7	0:60d829a0353a	3827	/************** Bit definition for USB_COUNT5_RX_0 register *************/
tushki7	0:60d829a0353a	3828	#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	3829
tushki7	0:60d829a0353a	3830	#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	3831	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3832	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3833	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3834	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3835	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3836
tushki7	0:60d829a0353a	3837	#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	3838
tushki7	0:60d829a0353a	3839	/************** Bit definition for USB_COUNT5_RX_1 register *************/
tushki7	0:60d829a0353a	3840	#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	3841
tushki7	0:60d829a0353a	3842	#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	3843	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	3844	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3845	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	3846	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	3847	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	3848
tushki7	0:60d829a0353a	3849	#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	3850
tushki7	0:60d829a0353a	3851	/************* Bit definition for USB_COUNT6_RX_0 register *************/
tushki7	0:60d829a0353a	3852	#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	3853
tushki7	0:60d829a0353a	3854	#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	3855	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3856	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3857	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3858	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3859	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3860
tushki7	0:60d829a0353a	3861	#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	3862
tushki7	0:60d829a0353a	3863	/************** Bit definition for USB_COUNT6_RX_1 register *************/
tushki7	0:60d829a0353a	3864	#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	3865
tushki7	0:60d829a0353a	3866	#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	3867	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	3868	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3869	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	3870	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	3871	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	3872
tushki7	0:60d829a0353a	3873	#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	3874
tushki7	0:60d829a0353a	3875	/************* Bit definition for USB_COUNT7_RX_0 register **************/
tushki7	0:60d829a0353a	3876	#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
tushki7	0:60d829a0353a	3877
tushki7	0:60d829a0353a	3878	#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
tushki7	0:60d829a0353a	3879	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
tushki7	0:60d829a0353a	3880	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
tushki7	0:60d829a0353a	3881	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
tushki7	0:60d829a0353a	3882	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
tushki7	0:60d829a0353a	3883	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
tushki7	0:60d829a0353a	3884
tushki7	0:60d829a0353a	3885	#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
tushki7	0:60d829a0353a	3886
tushki7	0:60d829a0353a	3887	/************* Bit definition for USB_COUNT7_RX_1 register **************/
tushki7	0:60d829a0353a	3888	#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
tushki7	0:60d829a0353a	3889
tushki7	0:60d829a0353a	3890	#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
tushki7	0:60d829a0353a	3891	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
tushki7	0:60d829a0353a	3892	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
tushki7	0:60d829a0353a	3893	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
tushki7	0:60d829a0353a	3894	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
tushki7	0:60d829a0353a	3895	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
tushki7	0:60d829a0353a	3896
tushki7	0:60d829a0353a	3897	#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
tushki7	0:60d829a0353a	3898
tushki7	0:60d829a0353a	3899	/******************************************************************************/
tushki7	0:60d829a0353a	3900	/* */
tushki7	0:60d829a0353a	3901	/* Controller Area Network */
tushki7	0:60d829a0353a	3902	/* */
tushki7	0:60d829a0353a	3903	/******************************************************************************/
tushki7	0:60d829a0353a	3904
tushki7	0:60d829a0353a	3905	/!< CAN control and status registers /
tushki7	0:60d829a0353a	3906	/***************** Bit definition for CAN_MCR register ******************/
tushki7	0:60d829a0353a	3907	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!< Initialization Request /
tushki7	0:60d829a0353a	3908	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!< Sleep Mode Request /
tushki7	0:60d829a0353a	3909	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!< Transmit FIFO Priority /
tushki7	0:60d829a0353a	3910	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!< Receive FIFO Locked Mode /
tushki7	0:60d829a0353a	3911	#define CAN_MCR_NART ((uint32_t)0x00000010) /!< No Automatic Retransmission /
tushki7	0:60d829a0353a	3912	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!< Automatic Wakeup Mode /
tushki7	0:60d829a0353a	3913	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!< Automatic Bus-Off Management /
tushki7	0:60d829a0353a	3914	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!< Time Triggered Communication Mode /
tushki7	0:60d829a0353a	3915	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!< CAN software master reset /
tushki7	0:60d829a0353a	3916	#define CAN_MCR_DBF ((uint32_t)0x00010000) /!< CAN Debug freeze /
tushki7	0:60d829a0353a	3917
tushki7	0:60d829a0353a	3918	/***************** Bit definition for CAN_MSR register ******************/
tushki7	0:60d829a0353a	3919	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!< Initialization Acknowledge /
tushki7	0:60d829a0353a	3920	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!< Sleep Acknowledge /
tushki7	0:60d829a0353a	3921	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!< Error Interrupt /
tushki7	0:60d829a0353a	3922	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!< Wakeup Interrupt /
tushki7	0:60d829a0353a	3923	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!< Sleep Acknowledge Interrupt /
tushki7	0:60d829a0353a	3924	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!< Transmit Mode /
tushki7	0:60d829a0353a	3925	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!< Receive Mode /
tushki7	0:60d829a0353a	3926	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!< Last Sample Point /
tushki7	0:60d829a0353a	3927	#define CAN_MSR_RX ((uint32_t)0x00000800) /!< CAN Rx Signal /
tushki7	0:60d829a0353a	3928
tushki7	0:60d829a0353a	3929	/***************** Bit definition for CAN_TSR register ******************/
tushki7	0:60d829a0353a	3930	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!< Request Completed Mailbox0 /
tushki7	0:60d829a0353a	3931	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!< Transmission OK of Mailbox0 /
tushki7	0:60d829a0353a	3932	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!< Arbitration Lost for Mailbox0 /
tushki7	0:60d829a0353a	3933	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!< Transmission Error of Mailbox0 /
tushki7	0:60d829a0353a	3934	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!< Abort Request for Mailbox0 /
tushki7	0:60d829a0353a	3935	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!< Request Completed Mailbox1 /
tushki7	0:60d829a0353a	3936	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!< Transmission OK of Mailbox1 /
tushki7	0:60d829a0353a	3937	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!< Arbitration Lost for Mailbox1 /
tushki7	0:60d829a0353a	3938	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!< Transmission Error of Mailbox1 /
tushki7	0:60d829a0353a	3939	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!< Abort Request for Mailbox 1 /
tushki7	0:60d829a0353a	3940	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!< Request Completed Mailbox2 /
tushki7	0:60d829a0353a	3941	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!< Transmission OK of Mailbox 2 /
tushki7	0:60d829a0353a	3942	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!< Arbitration Lost for mailbox 2 /
tushki7	0:60d829a0353a	3943	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!< Transmission Error of Mailbox 2 /
tushki7	0:60d829a0353a	3944	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!< Abort Request for Mailbox 2 /
tushki7	0:60d829a0353a	3945	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!< Mailbox Code /
tushki7	0:60d829a0353a	3946
tushki7	0:60d829a0353a	3947	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!< TME[2:0] bits /
tushki7	0:60d829a0353a	3948	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!< Transmit Mailbox 0 Empty /
tushki7	0:60d829a0353a	3949	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!< Transmit Mailbox 1 Empty /
tushki7	0:60d829a0353a	3950	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!< Transmit Mailbox 2 Empty /
tushki7	0:60d829a0353a	3951
tushki7	0:60d829a0353a	3952	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!< LOW[2:0] bits /
tushki7	0:60d829a0353a	3953	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!< Lowest Priority Flag for Mailbox 0 /
tushki7	0:60d829a0353a	3954	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!< Lowest Priority Flag for Mailbox 1 /
tushki7	0:60d829a0353a	3955	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!< Lowest Priority Flag for Mailbox 2 /
tushki7	0:60d829a0353a	3956
tushki7	0:60d829a0353a	3957	/***************** Bit definition for CAN_RF0R register *****************/
tushki7	0:60d829a0353a	3958	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!< FIFO 0 Message Pending /
tushki7	0:60d829a0353a	3959	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!< FIFO 0 Full /
tushki7	0:60d829a0353a	3960	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!< FIFO 0 Overrun /
tushki7	0:60d829a0353a	3961	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!< Release FIFO 0 Output Mailbox /
tushki7	0:60d829a0353a	3962
tushki7	0:60d829a0353a	3963	/***************** Bit definition for CAN_RF1R register *****************/
tushki7	0:60d829a0353a	3964	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!< FIFO 1 Message Pending /
tushki7	0:60d829a0353a	3965	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!< FIFO 1 Full /
tushki7	0:60d829a0353a	3966	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!< FIFO 1 Overrun /
tushki7	0:60d829a0353a	3967	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!< Release FIFO 1 Output Mailbox /
tushki7	0:60d829a0353a	3968
tushki7	0:60d829a0353a	3969	/****************** Bit definition for CAN_IER register *****************/
tushki7	0:60d829a0353a	3970	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!< Transmit Mailbox Empty Interrupt Enable /
tushki7	0:60d829a0353a	3971	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!< FIFO Message Pending Interrupt Enable /
tushki7	0:60d829a0353a	3972	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!< FIFO Full Interrupt Enable /
tushki7	0:60d829a0353a	3973	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!< FIFO Overrun Interrupt Enable /
tushki7	0:60d829a0353a	3974	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!< FIFO Message Pending Interrupt Enable /
tushki7	0:60d829a0353a	3975	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!< FIFO Full Interrupt Enable /
tushki7	0:60d829a0353a	3976	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!< FIFO Overrun Interrupt Enable /
tushki7	0:60d829a0353a	3977	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!< Error Warning Interrupt Enable /
tushki7	0:60d829a0353a	3978	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!< Error Passive Interrupt Enable /
tushki7	0:60d829a0353a	3979	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!< Bus-Off Interrupt Enable /
tushki7	0:60d829a0353a	3980	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!< Last Error Code Interrupt Enable /
tushki7	0:60d829a0353a	3981	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!< Error Interrupt Enable /
tushki7	0:60d829a0353a	3982	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!< Wakeup Interrupt Enable /
tushki7	0:60d829a0353a	3983	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!< Sleep Interrupt Enable /
tushki7	0:60d829a0353a	3984
tushki7	0:60d829a0353a	3985	/****************** Bit definition for CAN_ESR register *****************/
tushki7	0:60d829a0353a	3986	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!< Error Warning Flag /
tushki7	0:60d829a0353a	3987	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!< Error Passive Flag /
tushki7	0:60d829a0353a	3988	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!< Bus-Off Flag /
tushki7	0:60d829a0353a	3989
tushki7	0:60d829a0353a	3990	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!< LEC[2:0] bits (Last Error Code) /
tushki7	0:60d829a0353a	3991	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!< Bit 0 /
tushki7	0:60d829a0353a	3992	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!< Bit 1 /
tushki7	0:60d829a0353a	3993	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!< Bit 2 /
tushki7	0:60d829a0353a	3994
tushki7	0:60d829a0353a	3995	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!< Least significant byte of the 9-bit Transmit Error Counter /
tushki7	0:60d829a0353a	3996	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!< Receive Error Counter /
tushki7	0:60d829a0353a	3997
tushki7	0:60d829a0353a	3998	/***************** Bit definition for CAN_BTR register ******************/
tushki7	0:60d829a0353a	3999	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
tushki7	0:60d829a0353a	4000	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
tushki7	0:60d829a0353a	4001	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
tushki7	0:60d829a0353a	4002	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
tushki7	0:60d829a0353a	4003	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
tushki7	0:60d829a0353a	4004	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
tushki7	0:60d829a0353a	4005	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
tushki7	0:60d829a0353a	4006	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
tushki7	0:60d829a0353a	4007	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
tushki7	0:60d829a0353a	4008	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
tushki7	0:60d829a0353a	4009	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
tushki7	0:60d829a0353a	4010	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
tushki7	0:60d829a0353a	4011	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
tushki7	0:60d829a0353a	4012	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
tushki7	0:60d829a0353a	4013	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
tushki7	0:60d829a0353a	4014
tushki7	0:60d829a0353a	4015	/!< Mailbox registers /
tushki7	0:60d829a0353a	4016	/**************** Bit definition for CAN_TI0R register ******************/
tushki7	0:60d829a0353a	4017	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
tushki7	0:60d829a0353a	4018	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
tushki7	0:60d829a0353a	4019	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
tushki7	0:60d829a0353a	4020	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
tushki7	0:60d829a0353a	4021	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
tushki7	0:60d829a0353a	4022
tushki7	0:60d829a0353a	4023	/**************** Bit definition for CAN_TDT0R register *****************/
tushki7	0:60d829a0353a	4024	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
tushki7	0:60d829a0353a	4025	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
tushki7	0:60d829a0353a	4026	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
tushki7	0:60d829a0353a	4027
tushki7	0:60d829a0353a	4028	/**************** Bit definition for CAN_TDL0R register *****************/
tushki7	0:60d829a0353a	4029	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
tushki7	0:60d829a0353a	4030	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
tushki7	0:60d829a0353a	4031	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
tushki7	0:60d829a0353a	4032	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
tushki7	0:60d829a0353a	4033
tushki7	0:60d829a0353a	4034	/**************** Bit definition for CAN_TDH0R register *****************/
tushki7	0:60d829a0353a	4035	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
tushki7	0:60d829a0353a	4036	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
tushki7	0:60d829a0353a	4037	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
tushki7	0:60d829a0353a	4038	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
tushki7	0:60d829a0353a	4039
tushki7	0:60d829a0353a	4040	/***************** Bit definition for CAN_TI1R register *****************/
tushki7	0:60d829a0353a	4041	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
tushki7	0:60d829a0353a	4042	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
tushki7	0:60d829a0353a	4043	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
tushki7	0:60d829a0353a	4044	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
tushki7	0:60d829a0353a	4045	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
tushki7	0:60d829a0353a	4046
tushki7	0:60d829a0353a	4047	/***************** Bit definition for CAN_TDT1R register ****************/
tushki7	0:60d829a0353a	4048	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
tushki7	0:60d829a0353a	4049	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
tushki7	0:60d829a0353a	4050	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
tushki7	0:60d829a0353a	4051
tushki7	0:60d829a0353a	4052	/***************** Bit definition for CAN_TDL1R register ****************/
tushki7	0:60d829a0353a	4053	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
tushki7	0:60d829a0353a	4054	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
tushki7	0:60d829a0353a	4055	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
tushki7	0:60d829a0353a	4056	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
tushki7	0:60d829a0353a	4057
tushki7	0:60d829a0353a	4058	/***************** Bit definition for CAN_TDH1R register ****************/
tushki7	0:60d829a0353a	4059	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
tushki7	0:60d829a0353a	4060	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
tushki7	0:60d829a0353a	4061	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
tushki7	0:60d829a0353a	4062	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
tushki7	0:60d829a0353a	4063
tushki7	0:60d829a0353a	4064	/***************** Bit definition for CAN_TI2R register *****************/
tushki7	0:60d829a0353a	4065	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
tushki7	0:60d829a0353a	4066	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
tushki7	0:60d829a0353a	4067	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
tushki7	0:60d829a0353a	4068	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
tushki7	0:60d829a0353a	4069	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
tushki7	0:60d829a0353a	4070
tushki7	0:60d829a0353a	4071	/***************** Bit definition for CAN_TDT2R register ****************/
tushki7	0:60d829a0353a	4072	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
tushki7	0:60d829a0353a	4073	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
tushki7	0:60d829a0353a	4074	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
tushki7	0:60d829a0353a	4075
tushki7	0:60d829a0353a	4076	/***************** Bit definition for CAN_TDL2R register ****************/
tushki7	0:60d829a0353a	4077	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
tushki7	0:60d829a0353a	4078	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
tushki7	0:60d829a0353a	4079	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
tushki7	0:60d829a0353a	4080	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
tushki7	0:60d829a0353a	4081
tushki7	0:60d829a0353a	4082	/***************** Bit definition for CAN_TDH2R register ****************/
tushki7	0:60d829a0353a	4083	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
tushki7	0:60d829a0353a	4084	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
tushki7	0:60d829a0353a	4085	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
tushki7	0:60d829a0353a	4086	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
tushki7	0:60d829a0353a	4087
tushki7	0:60d829a0353a	4088	/***************** Bit definition for CAN_RI0R register *****************/
tushki7	0:60d829a0353a	4089	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
tushki7	0:60d829a0353a	4090	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
tushki7	0:60d829a0353a	4091	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
tushki7	0:60d829a0353a	4092	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
tushki7	0:60d829a0353a	4093
tushki7	0:60d829a0353a	4094	/***************** Bit definition for CAN_RDT0R register ****************/
tushki7	0:60d829a0353a	4095	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
tushki7	0:60d829a0353a	4096	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
tushki7	0:60d829a0353a	4097	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
tushki7	0:60d829a0353a	4098
tushki7	0:60d829a0353a	4099	/***************** Bit definition for CAN_RDL0R register ****************/
tushki7	0:60d829a0353a	4100	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
tushki7	0:60d829a0353a	4101	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
tushki7	0:60d829a0353a	4102	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
tushki7	0:60d829a0353a	4103	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
tushki7	0:60d829a0353a	4104
tushki7	0:60d829a0353a	4105	/***************** Bit definition for CAN_RDH0R register ****************/
tushki7	0:60d829a0353a	4106	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
tushki7	0:60d829a0353a	4107	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
tushki7	0:60d829a0353a	4108	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
tushki7	0:60d829a0353a	4109	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
tushki7	0:60d829a0353a	4110
tushki7	0:60d829a0353a	4111	/***************** Bit definition for CAN_RI1R register *****************/
tushki7	0:60d829a0353a	4112	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
tushki7	0:60d829a0353a	4113	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
tushki7	0:60d829a0353a	4114	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
tushki7	0:60d829a0353a	4115	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
tushki7	0:60d829a0353a	4116
tushki7	0:60d829a0353a	4117	/***************** Bit definition for CAN_RDT1R register ****************/
tushki7	0:60d829a0353a	4118	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
tushki7	0:60d829a0353a	4119	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
tushki7	0:60d829a0353a	4120	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
tushki7	0:60d829a0353a	4121
tushki7	0:60d829a0353a	4122	/***************** Bit definition for CAN_RDL1R register ****************/
tushki7	0:60d829a0353a	4123	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
tushki7	0:60d829a0353a	4124	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
tushki7	0:60d829a0353a	4125	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
tushki7	0:60d829a0353a	4126	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
tushki7	0:60d829a0353a	4127
tushki7	0:60d829a0353a	4128	/***************** Bit definition for CAN_RDH1R register ****************/
tushki7	0:60d829a0353a	4129	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
tushki7	0:60d829a0353a	4130	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
tushki7	0:60d829a0353a	4131	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
tushki7	0:60d829a0353a	4132	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
tushki7	0:60d829a0353a	4133
tushki7	0:60d829a0353a	4134	/!< CAN filter registers /
tushki7	0:60d829a0353a	4135	/***************** Bit definition for CAN_FMR register ******************/
tushki7	0:60d829a0353a	4136	#define CAN_FMR_FINIT ((uint32_t)0x00000001) /!< Filter Init Mode /
tushki7	0:60d829a0353a	4137	#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /!< CAN2 start bank /
tushki7	0:60d829a0353a	4138
tushki7	0:60d829a0353a	4139	/***************** Bit definition for CAN_FM1R register *****************/
tushki7	0:60d829a0353a	4140	#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /!< Filter Mode /
tushki7	0:60d829a0353a	4141	#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /!< Filter Init Mode for filter 0 /
tushki7	0:60d829a0353a	4142	#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /!< Filter Init Mode for filter 1 /
tushki7	0:60d829a0353a	4143	#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /!< Filter Init Mode for filter 2 /
tushki7	0:60d829a0353a	4144	#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /!< Filter Init Mode for filter 3 /
tushki7	0:60d829a0353a	4145	#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /!< Filter Init Mode for filter 4 /
tushki7	0:60d829a0353a	4146	#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /!< Filter Init Mode for filter 5 /
tushki7	0:60d829a0353a	4147	#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /!< Filter Init Mode for filter 6 /
tushki7	0:60d829a0353a	4148	#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /!< Filter Init Mode for filter 7 /
tushki7	0:60d829a0353a	4149	#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /!< Filter Init Mode for filter 8 /
tushki7	0:60d829a0353a	4150	#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /!< Filter Init Mode for filter 9 /
tushki7	0:60d829a0353a	4151	#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /!< Filter Init Mode for filter 10 /
tushki7	0:60d829a0353a	4152	#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /!< Filter Init Mode for filter 11 /
tushki7	0:60d829a0353a	4153	#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /!< Filter Init Mode for filter 12 /
tushki7	0:60d829a0353a	4154	#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /!< Filter Init Mode for filter 13 /
tushki7	0:60d829a0353a	4155
tushki7	0:60d829a0353a	4156	/***************** Bit definition for CAN_FS1R register *****************/
tushki7	0:60d829a0353a	4157	#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /!< Filter Scale Configuration /
tushki7	0:60d829a0353a	4158	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!< Filter Scale Configuration for filter 0 /
tushki7	0:60d829a0353a	4159	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!< Filter Scale Configuration for filter 1 /
tushki7	0:60d829a0353a	4160	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!< Filter Scale Configuration for filter 2 /
tushki7	0:60d829a0353a	4161	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!< Filter Scale Configuration for filter 3 /
tushki7	0:60d829a0353a	4162	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!< Filter Scale Configuration for filter 4 /
tushki7	0:60d829a0353a	4163	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!< Filter Scale Configuration for filter 5 /
tushki7	0:60d829a0353a	4164	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!< Filter Scale Configuration for filter 6 /
tushki7	0:60d829a0353a	4165	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!< Filter Scale Configuration for filter 7 /
tushki7	0:60d829a0353a	4166	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!< Filter Scale Configuration for filter 8 /
tushki7	0:60d829a0353a	4167	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!< Filter Scale Configuration for filter 9 /
tushki7	0:60d829a0353a	4168	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!< Filter Scale Configuration for filter 10 /
tushki7	0:60d829a0353a	4169	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!< Filter Scale Configuration for filter 11 /
tushki7	0:60d829a0353a	4170	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!< Filter Scale Configuration for filter 12 /
tushki7	0:60d829a0353a	4171	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!< Filter Scale Configuration for filter 13 /
tushki7	0:60d829a0353a	4172
tushki7	0:60d829a0353a	4173	/**************** Bit definition for CAN_FFA1R register *****************/
tushki7	0:60d829a0353a	4174	#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /!< Filter FIFO Assignment /
tushki7	0:60d829a0353a	4175	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!< Filter FIFO Assignment for filter 0 /
tushki7	0:60d829a0353a	4176	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!< Filter FIFO Assignment for filter 1 /
tushki7	0:60d829a0353a	4177	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!< Filter FIFO Assignment for filter 2 /
tushki7	0:60d829a0353a	4178	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!< Filter FIFO Assignment for filter 3 /
tushki7	0:60d829a0353a	4179	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!< Filter FIFO Assignment for filter 4 /
tushki7	0:60d829a0353a	4180	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!< Filter FIFO Assignment for filter 5 /
tushki7	0:60d829a0353a	4181	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!< Filter FIFO Assignment for filter 6 /
tushki7	0:60d829a0353a	4182	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!< Filter FIFO Assignment for filter 7 /
tushki7	0:60d829a0353a	4183	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!< Filter FIFO Assignment for filter 8 /
tushki7	0:60d829a0353a	4184	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!< Filter FIFO Assignment for filter 9 /
tushki7	0:60d829a0353a	4185	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!< Filter FIFO Assignment for filter 10 /
tushki7	0:60d829a0353a	4186	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!< Filter FIFO Assignment for filter 11 /
tushki7	0:60d829a0353a	4187	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!< Filter FIFO Assignment for filter 12 /
tushki7	0:60d829a0353a	4188	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!< Filter FIFO Assignment for filter 13 /
tushki7	0:60d829a0353a	4189
tushki7	0:60d829a0353a	4190	/***************** Bit definition for CAN_FA1R register *****************/
tushki7	0:60d829a0353a	4191	#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /!< Filter Active /
tushki7	0:60d829a0353a	4192	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!< Filter 0 Active /
tushki7	0:60d829a0353a	4193	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!< Filter 1 Active /
tushki7	0:60d829a0353a	4194	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!< Filter 2 Active /
tushki7	0:60d829a0353a	4195	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!< Filter 3 Active /
tushki7	0:60d829a0353a	4196	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!< Filter 4 Active /
tushki7	0:60d829a0353a	4197	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!< Filter 5 Active /
tushki7	0:60d829a0353a	4198	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!< Filter 6 Active /
tushki7	0:60d829a0353a	4199	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!< Filter 7 Active /
tushki7	0:60d829a0353a	4200	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!< Filter 8 Active /
tushki7	0:60d829a0353a	4201	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!< Filter 9 Active /
tushki7	0:60d829a0353a	4202	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!< Filter 10 Active /
tushki7	0:60d829a0353a	4203	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!< Filter 11 Active /
tushki7	0:60d829a0353a	4204	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!< Filter 12 Active /
tushki7	0:60d829a0353a	4205	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!< Filter 13 Active /
tushki7	0:60d829a0353a	4206
tushki7	0:60d829a0353a	4207	/***************** Bit definition for CAN_F0R1 register *****************/
tushki7	0:60d829a0353a	4208	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4209	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4210	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4211	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4212	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4213	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4214	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4215	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4216	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4217	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4218	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4219	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4220	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4221	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4222	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4223	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4224	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4225	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4226	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4227	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4228	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4229	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4230	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4231	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4232	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4233	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4234	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4235	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4236	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4237	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4238	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4239	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4240
tushki7	0:60d829a0353a	4241	/***************** Bit definition for CAN_F1R1 register *****************/
tushki7	0:60d829a0353a	4242	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4243	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4244	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4245	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4246	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4247	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4248	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4249	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4250	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4251	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4252	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4253	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4254	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4255	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4256	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4257	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4258	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4259	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4260	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4261	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4262	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4263	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4264	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4265	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4266	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4267	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4268	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4269	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4270	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4271	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4272	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4273	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4274
tushki7	0:60d829a0353a	4275	/***************** Bit definition for CAN_F2R1 register *****************/
tushki7	0:60d829a0353a	4276	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4277	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4278	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4279	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4280	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4281	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4282	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4283	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4284	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4285	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4286	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4287	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4288	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4289	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4290	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4291	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4292	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4293	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4294	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4295	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4296	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4297	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4298	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4299	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4300	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4301	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4302	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4303	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4304	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4305	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4306	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4307	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4308
tushki7	0:60d829a0353a	4309	/***************** Bit definition for CAN_F3R1 register *****************/
tushki7	0:60d829a0353a	4310	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4311	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4312	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4313	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4314	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4315	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4316	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4317	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4318	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4319	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4320	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4321	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4322	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4323	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4324	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4325	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4326	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4327	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4328	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4329	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4330	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4331	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4332	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4333	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4334	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4335	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4336	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4337	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4338	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4339	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4340	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4341	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4342
tushki7	0:60d829a0353a	4343	/***************** Bit definition for CAN_F4R1 register *****************/
tushki7	0:60d829a0353a	4344	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4345	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4346	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4347	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4348	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4349	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4350	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4351	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4352	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4353	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4354	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4355	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4356	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4357	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4358	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4359	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4360	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4361	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4362	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4363	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4364	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4365	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4366	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4367	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4368	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4369	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4370	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4371	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4372	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4373	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4374	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4375	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4376
tushki7	0:60d829a0353a	4377	/***************** Bit definition for CAN_F5R1 register *****************/
tushki7	0:60d829a0353a	4378	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4379	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4380	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4381	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4382	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4383	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4384	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4385	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4386	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4387	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4388	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4389	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4390	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4391	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4392	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4393	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4394	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4395	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4396	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4397	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4398	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4399	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4400	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4401	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4402	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4403	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4404	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4405	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4406	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4407	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4408	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4409	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4410
tushki7	0:60d829a0353a	4411	/***************** Bit definition for CAN_F6R1 register *****************/
tushki7	0:60d829a0353a	4412	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4413	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4414	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4415	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4416	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4417	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4418	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4419	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4420	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4421	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4422	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4423	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4424	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4425	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4426	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4427	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4428	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4429	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4430	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4431	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4432	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4433	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4434	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4435	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4436	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4437	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4438	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4439	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4440	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4441	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4442	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4443	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4444
tushki7	0:60d829a0353a	4445	/***************** Bit definition for CAN_F7R1 register *****************/
tushki7	0:60d829a0353a	4446	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4447	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4448	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4449	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4450	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4451	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4452	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4453	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4454	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4455	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4456	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4457	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4458	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4459	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4460	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4461	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4462	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4463	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4464	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4465	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4466	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4467	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4468	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4469	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4470	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4471	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4472	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4473	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4474	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4475	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4476	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4477	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4478
tushki7	0:60d829a0353a	4479	/***************** Bit definition for CAN_F8R1 register *****************/
tushki7	0:60d829a0353a	4480	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4481	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4482	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4483	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4484	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4485	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4486	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4487	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4488	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4489	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4490	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4491	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4492	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4493	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4494	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4495	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4496	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4497	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4498	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4499	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4500	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4501	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4502	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4503	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4504	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4505	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4506	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4507	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4508	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4509	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4510	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4511	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4512
tushki7	0:60d829a0353a	4513	/***************** Bit definition for CAN_F9R1 register *****************/
tushki7	0:60d829a0353a	4514	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4515	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4516	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4517	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4518	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4519	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4520	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4521	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4522	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4523	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4524	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4525	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4526	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4527	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4528	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4529	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4530	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4531	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4532	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4533	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4534	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4535	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4536	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4537	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4538	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4539	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4540	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4541	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4542	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4543	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4544	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4545	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4546
tushki7	0:60d829a0353a	4547	/***************** Bit definition for CAN_F10R1 register ****************/
tushki7	0:60d829a0353a	4548	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4549	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4550	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4551	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4552	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4553	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4554	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4555	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4556	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4557	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4558	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4559	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4560	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4561	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4562	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4563	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4564	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4565	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4566	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4567	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4568	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4569	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4570	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4571	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4572	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4573	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4574	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4575	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4576	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4577	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4578	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4579	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4580
tushki7	0:60d829a0353a	4581	/***************** Bit definition for CAN_F11R1 register ****************/
tushki7	0:60d829a0353a	4582	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4583	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4584	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4585	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4586	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4587	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4588	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4589	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4590	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4591	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4592	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4593	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4594	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4595	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4596	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4597	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4598	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4599	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4600	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4601	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4602	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4603	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4604	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4605	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4606	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4607	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4608	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4609	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4610	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4611	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4612	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4613	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4614
tushki7	0:60d829a0353a	4615	/***************** Bit definition for CAN_F12R1 register ****************/
tushki7	0:60d829a0353a	4616	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4617	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4618	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4619	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4620	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4621	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4622	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4623	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4624	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4625	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4626	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4627	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4628	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4629	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4630	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4631	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4632	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4633	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4634	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4635	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4636	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4637	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4638	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4639	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4640	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4641	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4642	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4643	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4644	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4645	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4646	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4647	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4648
tushki7	0:60d829a0353a	4649	/***************** Bit definition for CAN_F13R1 register ****************/
tushki7	0:60d829a0353a	4650	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4651	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4652	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4653	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4654	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4655	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4656	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4657	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4658	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4659	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4660	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4661	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4662	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4663	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4664	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4665	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4666	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4667	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4668	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4669	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4670	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4671	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4672	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4673	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4674	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4675	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4676	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4677	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4678	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4679	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4680	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4681	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4682
tushki7	0:60d829a0353a	4683	/***************** Bit definition for CAN_F0R2 register *****************/
tushki7	0:60d829a0353a	4684	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4685	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4686	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4687	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4688	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4689	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4690	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4691	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4692	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4693	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4694	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4695	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4696	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4697	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4698	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4699	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4700	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4701	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4702	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4703	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4704	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4705	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4706	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4707	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4708	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4709	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4710	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4711	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4712	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4713	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4714	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4715	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4716
tushki7	0:60d829a0353a	4717	/***************** Bit definition for CAN_F1R2 register *****************/
tushki7	0:60d829a0353a	4718	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4719	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4720	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4721	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4722	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4723	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4724	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4725	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4726	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4727	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4728	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4729	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4730	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4731	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4732	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4733	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4734	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4735	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4736	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4737	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4738	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4739	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4740	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4741	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4742	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4743	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4744	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4745	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4746	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4747	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4748	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4749	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4750
tushki7	0:60d829a0353a	4751	/***************** Bit definition for CAN_F2R2 register *****************/
tushki7	0:60d829a0353a	4752	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4753	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4754	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4755	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4756	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4757	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4758	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4759	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4760	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4761	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4762	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4763	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4764	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4765	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4766	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4767	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4768	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4769	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4770	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4771	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4772	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4773	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4774	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4775	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4776	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4777	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4778	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4779	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4780	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4781	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4782	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4783	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4784
tushki7	0:60d829a0353a	4785	/***************** Bit definition for CAN_F3R2 register *****************/
tushki7	0:60d829a0353a	4786	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4787	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4788	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4789	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4790	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4791	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4792	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4793	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4794	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4795	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4796	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4797	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4798	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4799	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4800	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4801	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4802	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4803	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4804	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4805	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4806	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4807	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4808	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4809	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4810	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4811	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4812	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4813	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4814	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4815	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4816	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4817	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4818
tushki7	0:60d829a0353a	4819	/***************** Bit definition for CAN_F4R2 register *****************/
tushki7	0:60d829a0353a	4820	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4821	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4822	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4823	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4824	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4825	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4826	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4827	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4828	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4829	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4830	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4831	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4832	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4833	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4834	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4835	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4836	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4837	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4838	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4839	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4840	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4841	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4842	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4843	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4844	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4845	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4846	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4847	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4848	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4849	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4850	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4851	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4852
tushki7	0:60d829a0353a	4853	/***************** Bit definition for CAN_F5R2 register *****************/
tushki7	0:60d829a0353a	4854	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4855	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4856	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4857	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4858	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4859	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4860	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4861	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4862	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4863	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4864	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4865	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4866	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4867	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4868	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4869	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4870	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4871	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4872	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4873	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4874	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4875	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4876	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4877	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4878	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4879	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4880	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4881	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4882	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4883	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4884	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4885	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4886
tushki7	0:60d829a0353a	4887	/***************** Bit definition for CAN_F6R2 register *****************/
tushki7	0:60d829a0353a	4888	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4889	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4890	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4891	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4892	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4893	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4894	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4895	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4896	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4897	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4898	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4899	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4900	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4901	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4902	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4903	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4904	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4905	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4906	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4907	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4908	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4909	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4910	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4911	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4912	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4913	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4914	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4915	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4916	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4917	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4918	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4919	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4920
tushki7	0:60d829a0353a	4921	/***************** Bit definition for CAN_F7R2 register *****************/
tushki7	0:60d829a0353a	4922	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4923	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4924	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4925	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4926	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4927	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4928	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4929	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4930	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4931	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4932	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4933	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4934	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4935	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4936	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4937	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4938	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4939	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4940	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4941	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4942	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4943	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4944	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4945	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4946	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4947	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4948	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4949	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4950	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4951	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4952	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4953	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4954
tushki7	0:60d829a0353a	4955	/***************** Bit definition for CAN_F8R2 register *****************/
tushki7	0:60d829a0353a	4956	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4957	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4958	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4959	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4960	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4961	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4962	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4963	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4964	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4965	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	4966	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	4967	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	4968	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	4969	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	4970	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	4971	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	4972	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	4973	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	4974	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	4975	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	4976	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	4977	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	4978	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	4979	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	4980	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	4981	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	4982	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	4983	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	4984	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	4985	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	4986	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	4987	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	4988
tushki7	0:60d829a0353a	4989	/***************** Bit definition for CAN_F9R2 register *****************/
tushki7	0:60d829a0353a	4990	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	4991	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	4992	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	4993	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	4994	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	4995	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	4996	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	4997	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	4998	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	4999	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	5000	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	5001	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	5002	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	5003	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	5004	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	5005	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	5006	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	5007	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	5008	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	5009	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	5010	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	5011	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	5012	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	5013	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	5014	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	5015	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	5016	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	5017	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	5018	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	5019	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	5020	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	5021	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	5022
tushki7	0:60d829a0353a	5023	/***************** Bit definition for CAN_F10R2 register ****************/
tushki7	0:60d829a0353a	5024	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	5025	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	5026	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	5027	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	5028	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	5029	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	5030	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	5031	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	5032	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	5033	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	5034	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	5035	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	5036	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	5037	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	5038	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	5039	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	5040	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	5041	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	5042	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	5043	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	5044	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	5045	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	5046	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	5047	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	5048	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	5049	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	5050	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	5051	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	5052	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	5053	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	5054	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	5055	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	5056
tushki7	0:60d829a0353a	5057	/***************** Bit definition for CAN_F11R2 register ****************/
tushki7	0:60d829a0353a	5058	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	5059	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	5060	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	5061	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	5062	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	5063	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	5064	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	5065	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	5066	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	5067	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	5068	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	5069	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	5070	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	5071	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	5072	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	5073	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	5074	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	5075	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	5076	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	5077	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	5078	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	5079	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	5080	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	5081	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	5082	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	5083	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	5084	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	5085	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	5086	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	5087	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	5088	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	5089	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	5090
tushki7	0:60d829a0353a	5091	/***************** Bit definition for CAN_F12R2 register ****************/
tushki7	0:60d829a0353a	5092	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	5093	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	5094	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	5095	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	5096	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	5097	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	5098	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	5099	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	5100	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	5101	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	5102	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	5103	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	5104	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	5105	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	5106	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	5107	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	5108	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	5109	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	5110	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	5111	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	5112	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	5113	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	5114	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	5115	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	5116	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	5117	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	5118	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	5119	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	5120	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	5121	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	5122	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	5123	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	5124
tushki7	0:60d829a0353a	5125	/***************** Bit definition for CAN_F13R2 register ****************/
tushki7	0:60d829a0353a	5126	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
tushki7	0:60d829a0353a	5127	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
tushki7	0:60d829a0353a	5128	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
tushki7	0:60d829a0353a	5129	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
tushki7	0:60d829a0353a	5130	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
tushki7	0:60d829a0353a	5131	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
tushki7	0:60d829a0353a	5132	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
tushki7	0:60d829a0353a	5133	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
tushki7	0:60d829a0353a	5134	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
tushki7	0:60d829a0353a	5135	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
tushki7	0:60d829a0353a	5136	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
tushki7	0:60d829a0353a	5137	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
tushki7	0:60d829a0353a	5138	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
tushki7	0:60d829a0353a	5139	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
tushki7	0:60d829a0353a	5140	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
tushki7	0:60d829a0353a	5141	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
tushki7	0:60d829a0353a	5142	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
tushki7	0:60d829a0353a	5143	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
tushki7	0:60d829a0353a	5144	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
tushki7	0:60d829a0353a	5145	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
tushki7	0:60d829a0353a	5146	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
tushki7	0:60d829a0353a	5147	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
tushki7	0:60d829a0353a	5148	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
tushki7	0:60d829a0353a	5149	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
tushki7	0:60d829a0353a	5150	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
tushki7	0:60d829a0353a	5151	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
tushki7	0:60d829a0353a	5152	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
tushki7	0:60d829a0353a	5153	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
tushki7	0:60d829a0353a	5154	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
tushki7	0:60d829a0353a	5155	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
tushki7	0:60d829a0353a	5156	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
tushki7	0:60d829a0353a	5157	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
tushki7	0:60d829a0353a	5158
tushki7	0:60d829a0353a	5159	/******************************************************************************/
tushki7	0:60d829a0353a	5160	/* */
tushki7	0:60d829a0353a	5161	/* Serial Peripheral Interface */
tushki7	0:60d829a0353a	5162	/* */
tushki7	0:60d829a0353a	5163	/******************************************************************************/
tushki7	0:60d829a0353a	5164
tushki7	0:60d829a0353a	5165	/***************** Bit definition for SPI_CR1 register ******************/
tushki7	0:60d829a0353a	5166	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
tushki7	0:60d829a0353a	5167	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
tushki7	0:60d829a0353a	5168	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
tushki7	0:60d829a0353a	5169
tushki7	0:60d829a0353a	5170	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
tushki7	0:60d829a0353a	5171	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
tushki7	0:60d829a0353a	5172	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
tushki7	0:60d829a0353a	5173	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
tushki7	0:60d829a0353a	5174
tushki7	0:60d829a0353a	5175	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
tushki7	0:60d829a0353a	5176	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
tushki7	0:60d829a0353a	5177	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
tushki7	0:60d829a0353a	5178	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
tushki7	0:60d829a0353a	5179	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
tushki7	0:60d829a0353a	5180	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
tushki7	0:60d829a0353a	5181	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
tushki7	0:60d829a0353a	5182	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
tushki7	0:60d829a0353a	5183	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
tushki7	0:60d829a0353a	5184	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
tushki7	0:60d829a0353a	5185
tushki7	0:60d829a0353a	5186	/***************** Bit definition for SPI_CR2 register ******************/
tushki7	0:60d829a0353a	5187	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
tushki7	0:60d829a0353a	5188	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
tushki7	0:60d829a0353a	5189	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
tushki7	0:60d829a0353a	5190	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
tushki7	0:60d829a0353a	5191	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
tushki7	0:60d829a0353a	5192	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
tushki7	0:60d829a0353a	5193
tushki7	0:60d829a0353a	5194	/****************** Bit definition for SPI_SR register ******************/
tushki7	0:60d829a0353a	5195	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
tushki7	0:60d829a0353a	5196	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
tushki7	0:60d829a0353a	5197	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
tushki7	0:60d829a0353a	5198	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
tushki7	0:60d829a0353a	5199	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
tushki7	0:60d829a0353a	5200	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
tushki7	0:60d829a0353a	5201	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
tushki7	0:60d829a0353a	5202	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
tushki7	0:60d829a0353a	5203
tushki7	0:60d829a0353a	5204	/****************** Bit definition for SPI_DR register ******************/
tushki7	0:60d829a0353a	5205	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
tushki7	0:60d829a0353a	5206
tushki7	0:60d829a0353a	5207	/***************** Bit definition for SPI_CRCPR register ****************/
tushki7	0:60d829a0353a	5208	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
tushki7	0:60d829a0353a	5209
tushki7	0:60d829a0353a	5210	/**************** Bit definition for SPI_RXCRCR register ****************/
tushki7	0:60d829a0353a	5211	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
tushki7	0:60d829a0353a	5212
tushki7	0:60d829a0353a	5213	/**************** Bit definition for SPI_TXCRCR register ****************/
tushki7	0:60d829a0353a	5214	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
tushki7	0:60d829a0353a	5215
tushki7	0:60d829a0353a	5216	/**************** Bit definition for SPI_I2SCFGR register ***************/
tushki7	0:60d829a0353a	5217	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!< I2S mode selection /
tushki7	0:60d829a0353a	5218
tushki7	0:60d829a0353a	5219
tushki7	0:60d829a0353a	5220	/******************************************************************************/
tushki7	0:60d829a0353a	5221	/* */
tushki7	0:60d829a0353a	5222	/* Inter-integrated Circuit Interface */
tushki7	0:60d829a0353a	5223	/* */
tushki7	0:60d829a0353a	5224	/******************************************************************************/
tushki7	0:60d829a0353a	5225
tushki7	0:60d829a0353a	5226	/***************** Bit definition for I2C_CR1 register ******************/
tushki7	0:60d829a0353a	5227	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
tushki7	0:60d829a0353a	5228	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
tushki7	0:60d829a0353a	5229	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
tushki7	0:60d829a0353a	5230	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
tushki7	0:60d829a0353a	5231	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
tushki7	0:60d829a0353a	5232	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
tushki7	0:60d829a0353a	5233	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
tushki7	0:60d829a0353a	5234	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
tushki7	0:60d829a0353a	5235	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
tushki7	0:60d829a0353a	5236	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
tushki7	0:60d829a0353a	5237	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
tushki7	0:60d829a0353a	5238	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
tushki7	0:60d829a0353a	5239	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
tushki7	0:60d829a0353a	5240	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
tushki7	0:60d829a0353a	5241
tushki7	0:60d829a0353a	5242	/***************** Bit definition for I2C_CR2 register ******************/
tushki7	0:60d829a0353a	5243	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
tushki7	0:60d829a0353a	5244	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	5245	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	5246	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	5247	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	5248	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	5249	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	5250
tushki7	0:60d829a0353a	5251	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
tushki7	0:60d829a0353a	5252	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
tushki7	0:60d829a0353a	5253	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
tushki7	0:60d829a0353a	5254	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
tushki7	0:60d829a0353a	5255	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
tushki7	0:60d829a0353a	5256
tushki7	0:60d829a0353a	5257	/***************** Bit definition for I2C_OAR1 register *****************/
tushki7	0:60d829a0353a	5258	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
tushki7	0:60d829a0353a	5259	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
tushki7	0:60d829a0353a	5260
tushki7	0:60d829a0353a	5261	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	5262	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	5263	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	5264	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	5265	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	5266	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	5267	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	5268	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	5269	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
tushki7	0:60d829a0353a	5270	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
tushki7	0:60d829a0353a	5271
tushki7	0:60d829a0353a	5272	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
tushki7	0:60d829a0353a	5273
tushki7	0:60d829a0353a	5274	/***************** Bit definition for I2C_OAR2 register *****************/
tushki7	0:60d829a0353a	5275	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
tushki7	0:60d829a0353a	5276	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
tushki7	0:60d829a0353a	5277
tushki7	0:60d829a0353a	5278	/***************** Bit definition for I2C_SR1 register ******************/
tushki7	0:60d829a0353a	5279	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
tushki7	0:60d829a0353a	5280	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
tushki7	0:60d829a0353a	5281	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
tushki7	0:60d829a0353a	5282	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
tushki7	0:60d829a0353a	5283	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
tushki7	0:60d829a0353a	5284	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
tushki7	0:60d829a0353a	5285	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
tushki7	0:60d829a0353a	5286	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
tushki7	0:60d829a0353a	5287	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
tushki7	0:60d829a0353a	5288	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
tushki7	0:60d829a0353a	5289	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
tushki7	0:60d829a0353a	5290	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
tushki7	0:60d829a0353a	5291	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
tushki7	0:60d829a0353a	5292	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
tushki7	0:60d829a0353a	5293
tushki7	0:60d829a0353a	5294	/***************** Bit definition for I2C_SR2 register ******************/
tushki7	0:60d829a0353a	5295	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
tushki7	0:60d829a0353a	5296	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
tushki7	0:60d829a0353a	5297	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
tushki7	0:60d829a0353a	5298	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
tushki7	0:60d829a0353a	5299	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
tushki7	0:60d829a0353a	5300	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
tushki7	0:60d829a0353a	5301	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
tushki7	0:60d829a0353a	5302	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
tushki7	0:60d829a0353a	5303
tushki7	0:60d829a0353a	5304	/***************** Bit definition for I2C_CCR register ******************/
tushki7	0:60d829a0353a	5305	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
tushki7	0:60d829a0353a	5306	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
tushki7	0:60d829a0353a	5307	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
tushki7	0:60d829a0353a	5308
tushki7	0:60d829a0353a	5309	/**************** Bit definition for I2C_TRISE register *****************/
tushki7	0:60d829a0353a	5310	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
tushki7	0:60d829a0353a	5311
tushki7	0:60d829a0353a	5312	/******************************************************************************/
tushki7	0:60d829a0353a	5313	/* */
tushki7	0:60d829a0353a	5314	/* Universal Synchronous Asynchronous Receiver Transmitter */
tushki7	0:60d829a0353a	5315	/* */
tushki7	0:60d829a0353a	5316	/******************************************************************************/
tushki7	0:60d829a0353a	5317
tushki7	0:60d829a0353a	5318	/***************** Bit definition for USART_SR register *****************/
tushki7	0:60d829a0353a	5319	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
tushki7	0:60d829a0353a	5320	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
tushki7	0:60d829a0353a	5321	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
tushki7	0:60d829a0353a	5322	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
tushki7	0:60d829a0353a	5323	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
tushki7	0:60d829a0353a	5324	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
tushki7	0:60d829a0353a	5325	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
tushki7	0:60d829a0353a	5326	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
tushki7	0:60d829a0353a	5327	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
tushki7	0:60d829a0353a	5328	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
tushki7	0:60d829a0353a	5329
tushki7	0:60d829a0353a	5330	/***************** Bit definition for USART_DR register *****************/
tushki7	0:60d829a0353a	5331	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
tushki7	0:60d829a0353a	5332
tushki7	0:60d829a0353a	5333	/**************** Bit definition for USART_BRR register *****************/
tushki7	0:60d829a0353a	5334	#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
tushki7	0:60d829a0353a	5335	#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
tushki7	0:60d829a0353a	5336
tushki7	0:60d829a0353a	5337	/**************** Bit definition for USART_CR1 register *****************/
tushki7	0:60d829a0353a	5338	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
tushki7	0:60d829a0353a	5339	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
tushki7	0:60d829a0353a	5340	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
tushki7	0:60d829a0353a	5341	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
tushki7	0:60d829a0353a	5342	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
tushki7	0:60d829a0353a	5343	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
tushki7	0:60d829a0353a	5344	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
tushki7	0:60d829a0353a	5345	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
tushki7	0:60d829a0353a	5346	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
tushki7	0:60d829a0353a	5347	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
tushki7	0:60d829a0353a	5348	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
tushki7	0:60d829a0353a	5349	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
tushki7	0:60d829a0353a	5350	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
tushki7	0:60d829a0353a	5351	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
tushki7	0:60d829a0353a	5352
tushki7	0:60d829a0353a	5353	/**************** Bit definition for USART_CR2 register *****************/
tushki7	0:60d829a0353a	5354	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
tushki7	0:60d829a0353a	5355	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
tushki7	0:60d829a0353a	5356	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
tushki7	0:60d829a0353a	5357	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
tushki7	0:60d829a0353a	5358	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
tushki7	0:60d829a0353a	5359	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
tushki7	0:60d829a0353a	5360	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
tushki7	0:60d829a0353a	5361
tushki7	0:60d829a0353a	5362	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
tushki7	0:60d829a0353a	5363	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
tushki7	0:60d829a0353a	5364	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
tushki7	0:60d829a0353a	5365
tushki7	0:60d829a0353a	5366	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
tushki7	0:60d829a0353a	5367
tushki7	0:60d829a0353a	5368	/**************** Bit definition for USART_CR3 register *****************/
tushki7	0:60d829a0353a	5369	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
tushki7	0:60d829a0353a	5370	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
tushki7	0:60d829a0353a	5371	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
tushki7	0:60d829a0353a	5372	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
tushki7	0:60d829a0353a	5373	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
tushki7	0:60d829a0353a	5374	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
tushki7	0:60d829a0353a	5375	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
tushki7	0:60d829a0353a	5376	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
tushki7	0:60d829a0353a	5377	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
tushki7	0:60d829a0353a	5378	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
tushki7	0:60d829a0353a	5379	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
tushki7	0:60d829a0353a	5380
tushki7	0:60d829a0353a	5381	/**************** Bit definition for USART_GTPR register ****************/
tushki7	0:60d829a0353a	5382	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
tushki7	0:60d829a0353a	5383	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	5384	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	5385	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	5386	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
tushki7	0:60d829a0353a	5387	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
tushki7	0:60d829a0353a	5388	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
tushki7	0:60d829a0353a	5389	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
tushki7	0:60d829a0353a	5390	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
tushki7	0:60d829a0353a	5391
tushki7	0:60d829a0353a	5392	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
tushki7	0:60d829a0353a	5393
tushki7	0:60d829a0353a	5394	/******************************************************************************/
tushki7	0:60d829a0353a	5395	/* */
tushki7	0:60d829a0353a	5396	/* Debug MCU */
tushki7	0:60d829a0353a	5397	/* */
tushki7	0:60d829a0353a	5398	/******************************************************************************/
tushki7	0:60d829a0353a	5399
tushki7	0:60d829a0353a	5400	/************** Bit definition for DBGMCU_IDCODE register ***************/
tushki7	0:60d829a0353a	5401	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
tushki7	0:60d829a0353a	5402
tushki7	0:60d829a0353a	5403	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
tushki7	0:60d829a0353a	5404	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
tushki7	0:60d829a0353a	5405	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
tushki7	0:60d829a0353a	5406	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
tushki7	0:60d829a0353a	5407	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
tushki7	0:60d829a0353a	5408	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
tushki7	0:60d829a0353a	5409	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
tushki7	0:60d829a0353a	5410	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
tushki7	0:60d829a0353a	5411	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
tushki7	0:60d829a0353a	5412	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
tushki7	0:60d829a0353a	5413	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
tushki7	0:60d829a0353a	5414	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
tushki7	0:60d829a0353a	5415	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
tushki7	0:60d829a0353a	5416	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
tushki7	0:60d829a0353a	5417	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
tushki7	0:60d829a0353a	5418	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
tushki7	0:60d829a0353a	5419	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
tushki7	0:60d829a0353a	5420
tushki7	0:60d829a0353a	5421	/**************** Bit definition for DBGMCU_CR register *****************/
tushki7	0:60d829a0353a	5422	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
tushki7	0:60d829a0353a	5423	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
tushki7	0:60d829a0353a	5424	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
tushki7	0:60d829a0353a	5425	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
tushki7	0:60d829a0353a	5426
tushki7	0:60d829a0353a	5427	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
tushki7	0:60d829a0353a	5428	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
tushki7	0:60d829a0353a	5429	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
tushki7	0:60d829a0353a	5430
tushki7	0:60d829a0353a	5431	#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /!< Debug Independent Watchdog stopped when Core is halted /
tushki7	0:60d829a0353a	5432	#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /!< Debug Window Watchdog stopped when Core is halted /
tushki7	0:60d829a0353a	5433	#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /!< TIM1 counter stopped when core is halted /
tushki7	0:60d829a0353a	5434	#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /!< TIM2 counter stopped when core is halted /
tushki7	0:60d829a0353a	5435	#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /!< TIM3 counter stopped when core is halted /
tushki7	0:60d829a0353a	5436	#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /!< TIM4 counter stopped when core is halted /
tushki7	0:60d829a0353a	5437	#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /!< Debug CAN1 stopped when Core is halted /
tushki7	0:60d829a0353a	5438	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /!< SMBUS timeout mode stopped when Core is halted /
tushki7	0:60d829a0353a	5439	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /!< SMBUS timeout mode stopped when Core is halted /
tushki7	0:60d829a0353a	5440
tushki7	0:60d829a0353a	5441	/******************************************************************************/
tushki7	0:60d829a0353a	5442	/* */
tushki7	0:60d829a0353a	5443	/* FLASH and Option Bytes Registers */
tushki7	0:60d829a0353a	5444	/* */
tushki7	0:60d829a0353a	5445	/******************************************************************************/
tushki7	0:60d829a0353a	5446	/***************** Bit definition for FLASH_ACR register ****************/
tushki7	0:60d829a0353a	5447	#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /!< LATENCY[2:0] bits (Latency) /
tushki7	0:60d829a0353a	5448	#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /!< Bit 0 /
tushki7	0:60d829a0353a	5449	#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /!< Bit 1 /
tushki7	0:60d829a0353a	5450	#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /!< Bit 2 /
tushki7	0:60d829a0353a	5451
tushki7	0:60d829a0353a	5452	#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /!< Flash Half Cycle Access Enable /
tushki7	0:60d829a0353a	5453	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
tushki7	0:60d829a0353a	5454	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
tushki7	0:60d829a0353a	5455
tushki7	0:60d829a0353a	5456	/**************** Bit definition for FLASH_KEYR register ****************/
tushki7	0:60d829a0353a	5457	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
tushki7	0:60d829a0353a	5458
tushki7	0:60d829a0353a	5459	#define RDP_KEY ((uint32_t)0x000000A5) /!< RDP Key /
tushki7	0:60d829a0353a	5460	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
tushki7	0:60d829a0353a	5461	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
tushki7	0:60d829a0353a	5462
tushki7	0:60d829a0353a	5463	/*************** Bit definition for FLASH_OPTKEYR register **************/
tushki7	0:60d829a0353a	5464	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
tushki7	0:60d829a0353a	5465
tushki7	0:60d829a0353a	5466	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
tushki7	0:60d829a0353a	5467	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
tushki7	0:60d829a0353a	5468
tushki7	0:60d829a0353a	5469	/**************** Bit definition for FLASH_SR register ******************/
tushki7	0:60d829a0353a	5470	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
tushki7	0:60d829a0353a	5471	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
tushki7	0:60d829a0353a	5472	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
tushki7	0:60d829a0353a	5473	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
tushki7	0:60d829a0353a	5474
tushki7	0:60d829a0353a	5475	/***************** Bit definition for FLASH_CR register *****************/
tushki7	0:60d829a0353a	5476	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
tushki7	0:60d829a0353a	5477	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
tushki7	0:60d829a0353a	5478	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
tushki7	0:60d829a0353a	5479	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
tushki7	0:60d829a0353a	5480	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
tushki7	0:60d829a0353a	5481	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
tushki7	0:60d829a0353a	5482	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
tushki7	0:60d829a0353a	5483	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
tushki7	0:60d829a0353a	5484	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
tushki7	0:60d829a0353a	5485	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
tushki7	0:60d829a0353a	5486
tushki7	0:60d829a0353a	5487	/***************** Bit definition for FLASH_AR register *****************/
tushki7	0:60d829a0353a	5488	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
tushki7	0:60d829a0353a	5489
tushki7	0:60d829a0353a	5490	/**************** Bit definition for FLASH_OBR register *****************/
tushki7	0:60d829a0353a	5491	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
tushki7	0:60d829a0353a	5492	#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /!< Read protection /
tushki7	0:60d829a0353a	5493
tushki7	0:60d829a0353a	5494	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /!< IWDG SW /
tushki7	0:60d829a0353a	5495	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /!< nRST_STOP /
tushki7	0:60d829a0353a	5496	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /!< nRST_STDBY /
tushki7	0:60d829a0353a	5497	#define FLASH_OBR_USER ((uint32_t)0x0000001C) /!< User Option Bytes /
tushki7	0:60d829a0353a	5498
tushki7	0:60d829a0353a	5499	/**************** Bit definition for FLASH_WRPR register ****************/
tushki7	0:60d829a0353a	5500	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
tushki7	0:60d829a0353a	5501
tushki7	0:60d829a0353a	5502	/----------------------------------------------------------------------------/
tushki7	0:60d829a0353a	5503
tushki7	0:60d829a0353a	5504	/**************** Bit definition for FLASH_RDP register *****************/
tushki7	0:60d829a0353a	5505	#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
tushki7	0:60d829a0353a	5506	#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
tushki7	0:60d829a0353a	5507
tushki7	0:60d829a0353a	5508	/**************** Bit definition for FLASH_USER register ****************/
tushki7	0:60d829a0353a	5509	#define FLASH_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
tushki7	0:60d829a0353a	5510	#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
tushki7	0:60d829a0353a	5511
tushki7	0:60d829a0353a	5512	/**************** Bit definition for FLASH_Data0 register ***************/
tushki7	0:60d829a0353a	5513	#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /!< User data storage option byte /
tushki7	0:60d829a0353a	5514	#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /!< User data storage complemented option byte /
tushki7	0:60d829a0353a	5515
tushki7	0:60d829a0353a	5516	/**************** Bit definition for FLASH_Data1 register ***************/
tushki7	0:60d829a0353a	5517	#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /!< User data storage option byte /
tushki7	0:60d829a0353a	5518	#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /!< User data storage complemented option byte /
tushki7	0:60d829a0353a	5519
tushki7	0:60d829a0353a	5520	/**************** Bit definition for FLASH_WRP0 register ****************/
tushki7	0:60d829a0353a	5521	#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
tushki7	0:60d829a0353a	5522	#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
tushki7	0:60d829a0353a	5523
tushki7	0:60d829a0353a	5524	/**************** Bit definition for FLASH_WRP1 register ****************/
tushki7	0:60d829a0353a	5525	#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
tushki7	0:60d829a0353a	5526	#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
tushki7	0:60d829a0353a	5527
tushki7	0:60d829a0353a	5528	/**************** Bit definition for FLASH_WRP2 register ****************/
tushki7	0:60d829a0353a	5529	#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
tushki7	0:60d829a0353a	5530	#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
tushki7	0:60d829a0353a	5531
tushki7	0:60d829a0353a	5532	/**************** Bit definition for FLASH_WRP3 register ****************/
tushki7	0:60d829a0353a	5533	#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
tushki7	0:60d829a0353a	5534	#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
tushki7	0:60d829a0353a	5535
tushki7	0:60d829a0353a	5536
tushki7	0:60d829a0353a	5537
tushki7	0:60d829a0353a	5538	/**
tushki7	0:60d829a0353a	5539	* @}
tushki7	0:60d829a0353a	5540	*/
tushki7	0:60d829a0353a	5541
tushki7	0:60d829a0353a	5542	/**
tushki7	0:60d829a0353a	5543	* @}
tushki7	0:60d829a0353a	5544	*/
tushki7	0:60d829a0353a	5545
tushki7	0:60d829a0353a	5546	/** @addtogroup Exported_macro
tushki7	0:60d829a0353a	5547	* @{
tushki7	0:60d829a0353a	5548	*/
tushki7	0:60d829a0353a	5549
tushki7	0:60d829a0353a	5550	/**************************** ADC Instances *******************************/
tushki7	0:60d829a0353a	5551	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
tushki7	0:60d829a0353a	5552	((INSTANCE) == ADC2))
tushki7	0:60d829a0353a	5553
tushki7	0:60d829a0353a	5554	#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
tushki7	0:60d829a0353a	5555
tushki7	0:60d829a0353a	5556	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
tushki7	0:60d829a0353a	5557
tushki7	0:60d829a0353a	5558
tushki7	0:60d829a0353a	5559	/**************************** CAN Instances *******************************/
tushki7	0:60d829a0353a	5560	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
tushki7	0:60d829a0353a	5561
tushki7	0:60d829a0353a	5562	/**************************** CRC Instances *******************************/
tushki7	0:60d829a0353a	5563	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
tushki7	0:60d829a0353a	5564
tushki7	0:60d829a0353a	5565	/**************************** DAC Instances *******************************/
tushki7	0:60d829a0353a	5566
tushki7	0:60d829a0353a	5567	/**************************** DMA Instances *******************************/
tushki7	0:60d829a0353a	5568	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
tushki7	0:60d829a0353a	5569	((INSTANCE) == DMA1_Channel2) \|\| \
tushki7	0:60d829a0353a	5570	((INSTANCE) == DMA1_Channel3) \|\| \
tushki7	0:60d829a0353a	5571	((INSTANCE) == DMA1_Channel4) \|\| \
tushki7	0:60d829a0353a	5572	((INSTANCE) == DMA1_Channel5) \|\| \
tushki7	0:60d829a0353a	5573	((INSTANCE) == DMA1_Channel6) \|\| \
tushki7	0:60d829a0353a	5574	((INSTANCE) == DMA1_Channel7))
tushki7	0:60d829a0353a	5575
tushki7	0:60d829a0353a	5576	/***************************** GPIO Instances *****************************/
tushki7	0:60d829a0353a	5577	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
tushki7	0:60d829a0353a	5578	((INSTANCE) == GPIOB) \|\| \
tushki7	0:60d829a0353a	5579	((INSTANCE) == GPIOC) \|\| \
tushki7	0:60d829a0353a	5580	((INSTANCE) == GPIOD) \|\| \
tushki7	0:60d829a0353a	5581	((INSTANCE) == GPIOE))
tushki7	0:60d829a0353a	5582
tushki7	0:60d829a0353a	5583	/************************** GPIO Alternate Function Instances *************/
tushki7	0:60d829a0353a	5584	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
tushki7	0:60d829a0353a	5585
tushki7	0:60d829a0353a	5586	/************************** GPIO Lock Instances ***************************/
tushki7	0:60d829a0353a	5587	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
tushki7	0:60d829a0353a	5588
tushki7	0:60d829a0353a	5589	/****************************** I2C Instances *****************************/
tushki7	0:60d829a0353a	5590	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
tushki7	0:60d829a0353a	5591	((INSTANCE) == I2C2))
tushki7	0:60d829a0353a	5592
tushki7	0:60d829a0353a	5593	/**************************** IWDG Instances ******************************/
tushki7	0:60d829a0353a	5594	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
tushki7	0:60d829a0353a	5595
tushki7	0:60d829a0353a	5596	/****************************** SPI Instances *****************************/
tushki7	0:60d829a0353a	5597	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
tushki7	0:60d829a0353a	5598	((INSTANCE) == SPI2))
tushki7	0:60d829a0353a	5599
tushki7	0:60d829a0353a	5600	/**************************** START TIM Instances *************************/
tushki7	0:60d829a0353a	5601	/**************************** TIM Instances *******************************/
tushki7	0:60d829a0353a	5602	#define IS_TIM_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5603	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5604	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5605	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5606	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5607
tushki7	0:60d829a0353a	5608	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5609	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5610	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5611	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5612	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5613
tushki7	0:60d829a0353a	5614	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5615	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5616	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5617	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5618	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5619
tushki7	0:60d829a0353a	5620	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5621	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5622	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5623	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5624	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5625
tushki7	0:60d829a0353a	5626	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5627	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5628	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5629	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5630	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5631
tushki7	0:60d829a0353a	5632	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5633	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5634	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5635	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5636	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5637
tushki7	0:60d829a0353a	5638	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5639	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5640	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5641	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5642	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5643
tushki7	0:60d829a0353a	5644	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5645	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5646	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5647	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5648	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5649
tushki7	0:60d829a0353a	5650	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5651	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5652	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5653	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5654	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5655
tushki7	0:60d829a0353a	5656	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5657	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5658	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5659	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5660	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5661
tushki7	0:60d829a0353a	5662	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5663	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5664	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5665	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5666	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5667
tushki7	0:60d829a0353a	5668	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5669	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5670	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5671	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5672	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5673
tushki7	0:60d829a0353a	5674	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5675	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5676	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5677	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5678	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5679
tushki7	0:60d829a0353a	5680	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5681	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5682	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5683	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5684	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5685
tushki7	0:60d829a0353a	5686	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5687	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5688	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5689	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5690	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5691
tushki7	0:60d829a0353a	5692	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5693	((INSTANCE) == TIM1)
tushki7	0:60d829a0353a	5694
tushki7	0:60d829a0353a	5695	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
tushki7	0:60d829a0353a	5696	((((INSTANCE) == TIM1) && \
tushki7	0:60d829a0353a	5697	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5698	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5699	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	5700	((CHANNEL) == TIM_CHANNEL_4))) \
tushki7	0:60d829a0353a	5701	\|\| \
tushki7	0:60d829a0353a	5702	(((INSTANCE) == TIM2) && \
tushki7	0:60d829a0353a	5703	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5704	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5705	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	5706	((CHANNEL) == TIM_CHANNEL_4))) \
tushki7	0:60d829a0353a	5707	\|\| \
tushki7	0:60d829a0353a	5708	(((INSTANCE) == TIM3) && \
tushki7	0:60d829a0353a	5709	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5710	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5711	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	5712	((CHANNEL) == TIM_CHANNEL_4))) \
tushki7	0:60d829a0353a	5713	\|\| \
tushki7	0:60d829a0353a	5714	(((INSTANCE) == TIM4) && \
tushki7	0:60d829a0353a	5715	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5716	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5717	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	5718	((CHANNEL) == TIM_CHANNEL_4))))
tushki7	0:60d829a0353a	5719
tushki7	0:60d829a0353a	5720	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
tushki7	0:60d829a0353a	5721	(((INSTANCE) == TIM1) && \
tushki7	0:60d829a0353a	5722	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	5723	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	5724	((CHANNEL) == TIM_CHANNEL_3)))
tushki7	0:60d829a0353a	5725
tushki7	0:60d829a0353a	5726	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5727	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5728	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5729	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5730	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5731
tushki7	0:60d829a0353a	5732	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5733	((INSTANCE) == TIM1)
tushki7	0:60d829a0353a	5734
tushki7	0:60d829a0353a	5735	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5736	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5737	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5738	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5739	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5740
tushki7	0:60d829a0353a	5741	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5742	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5743	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5744	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5745	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5746
tushki7	0:60d829a0353a	5747	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5748	(((INSTANCE) == TIM1) \|\| \
tushki7	0:60d829a0353a	5749	((INSTANCE) == TIM2) \|\| \
tushki7	0:60d829a0353a	5750	((INSTANCE) == TIM3) \|\| \
tushki7	0:60d829a0353a	5751	((INSTANCE) == TIM4))
tushki7	0:60d829a0353a	5752
tushki7	0:60d829a0353a	5753	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
tushki7	0:60d829a0353a	5754	((INSTANCE) == TIM1)
tushki7	0:60d829a0353a	5755
tushki7	0:60d829a0353a	5756	/**************************** END TIM Instances ***************************/
tushki7	0:60d829a0353a	5757
tushki7	0:60d829a0353a	5758
tushki7	0:60d829a0353a	5759	/****************** USART Instances : Synchronous mode ********************/
tushki7	0:60d829a0353a	5760	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5761	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5762	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5763
tushki7	0:60d829a0353a	5764	/****************** UART Instances : Asynchronous mode ********************/
tushki7	0:60d829a0353a	5765	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5766	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5767	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5768
tushki7	0:60d829a0353a	5769	/****************** UART Instances : Half-Duplex mode ********************/
tushki7	0:60d829a0353a	5770	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5771	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5772	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5773
tushki7	0:60d829a0353a	5774	/****************** UART Instances : LIN mode ********************/
tushki7	0:60d829a0353a	5775	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5776	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5777	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5778
tushki7	0:60d829a0353a	5779	/**************** UART Instances : Hardware Flow control ******************/
tushki7	0:60d829a0353a	5780	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5781	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5782	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5783
tushki7	0:60d829a0353a	5784	/******************* UART Instances : Smard card mode *********************/
tushki7	0:60d829a0353a	5785	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5786	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5787	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5788
tushki7	0:60d829a0353a	5789	/********************* UART Instances : IRDA mode *************************/
tushki7	0:60d829a0353a	5790	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5791	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5792	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5793
tushki7	0:60d829a0353a	5794	/*************** UART Instances : Multi-Processor mode ********************/
tushki7	0:60d829a0353a	5795	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5796	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5797	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5798
tushki7	0:60d829a0353a	5799	/*************** UART Instances : DMA mode available ********************/
tushki7	0:60d829a0353a	5800	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
tushki7	0:60d829a0353a	5801	((INSTANCE) == USART2) \|\| \
tushki7	0:60d829a0353a	5802	((INSTANCE) == USART3))
tushki7	0:60d829a0353a	5803
tushki7	0:60d829a0353a	5804	/**************************** RTC Instances *******************************/
tushki7	0:60d829a0353a	5805	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
tushki7	0:60d829a0353a	5806
tushki7	0:60d829a0353a	5807	/************************** WWDG Instances ***************************/
tushki7	0:60d829a0353a	5808	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
tushki7	0:60d829a0353a	5809
tushki7	0:60d829a0353a	5810	/**************************** USB Instances ******************************/
tushki7	0:60d829a0353a	5811	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
tushki7	0:60d829a0353a	5812
tushki7	0:60d829a0353a	5813
tushki7	0:60d829a0353a	5814
tushki7	0:60d829a0353a	5815
tushki7	0:60d829a0353a	5816	/**
tushki7	0:60d829a0353a	5817	* @}
tushki7	0:60d829a0353a	5818	*/
tushki7	0:60d829a0353a	5819	/******************************************************************************/
tushki7	0:60d829a0353a	5820	/* For a painless codes migration between the STM32F1xx device product */
tushki7	0:60d829a0353a	5821	/* lines, the aliases defined below are put in place to overcome the */
tushki7	0:60d829a0353a	5822	/* differences in the interrupt handlers and IRQn definitions. */
tushki7	0:60d829a0353a	5823	/* No need to update developed interrupt code when moving across */
tushki7	0:60d829a0353a	5824	/* product lines within the same STM32F1 Family */
tushki7	0:60d829a0353a	5825	/******************************************************************************/
tushki7	0:60d829a0353a	5826
tushki7	0:60d829a0353a	5827	/* Aliases for __IRQn */
tushki7	0:60d829a0353a	5828	#define ADC1_IRQn ADC1_2_IRQn
tushki7	0:60d829a0353a	5829
tushki7	0:60d829a0353a	5830
tushki7	0:60d829a0353a	5831
tushki7	0:60d829a0353a	5832	#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
tushki7	0:60d829a0353a	5833	#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
tushki7	0:60d829a0353a	5834
tushki7	0:60d829a0353a	5835	#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
tushki7	0:60d829a0353a	5836	#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
tushki7	0:60d829a0353a	5837
tushki7	0:60d829a0353a	5838
tushki7	0:60d829a0353a	5839
tushki7	0:60d829a0353a	5840	#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
tushki7	0:60d829a0353a	5841	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
tushki7	0:60d829a0353a	5842	#define TIM9_IRQn TIM1_BRK_IRQn
tushki7	0:60d829a0353a	5843
tushki7	0:60d829a0353a	5844	#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
tushki7	0:60d829a0353a	5845	#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
tushki7	0:60d829a0353a	5846	#define TIM10_IRQn TIM1_UP_IRQn
tushki7	0:60d829a0353a	5847
tushki7	0:60d829a0353a	5848	#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
tushki7	0:60d829a0353a	5849	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
tushki7	0:60d829a0353a	5850	#define TIM11_IRQn TIM1_TRG_COM_IRQn
tushki7	0:60d829a0353a	5851
tushki7	0:60d829a0353a	5852	#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
tushki7	0:60d829a0353a	5853	#define CEC_IRQn USBWakeUp_IRQn
tushki7	0:60d829a0353a	5854
tushki7	0:60d829a0353a	5855
tushki7	0:60d829a0353a	5856
tushki7	0:60d829a0353a	5857
tushki7	0:60d829a0353a	5858	/* Aliases for __IRQHandler */
tushki7	0:60d829a0353a	5859	#define ADC1_IRQHandler ADC1_2_IRQHandler
tushki7	0:60d829a0353a	5860
tushki7	0:60d829a0353a	5861
tushki7	0:60d829a0353a	5862
tushki7	0:60d829a0353a	5863	#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
tushki7	0:60d829a0353a	5864	#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
tushki7	0:60d829a0353a	5865
tushki7	0:60d829a0353a	5866	#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
tushki7	0:60d829a0353a	5867	#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
tushki7	0:60d829a0353a	5868
tushki7	0:60d829a0353a	5869
tushki7	0:60d829a0353a	5870
tushki7	0:60d829a0353a	5871	#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
tushki7	0:60d829a0353a	5872	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
tushki7	0:60d829a0353a	5873	#define TIM9_IRQHandler TIM1_BRK_IRQHandler
tushki7	0:60d829a0353a	5874
tushki7	0:60d829a0353a	5875	#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
tushki7	0:60d829a0353a	5876	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
tushki7	0:60d829a0353a	5877	#define TIM10_IRQHandler TIM1_UP_IRQHandler
tushki7	0:60d829a0353a	5878
tushki7	0:60d829a0353a	5879	#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
tushki7	0:60d829a0353a	5880	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
tushki7	0:60d829a0353a	5881	#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
tushki7	0:60d829a0353a	5882
tushki7	0:60d829a0353a	5883	#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
tushki7	0:60d829a0353a	5884	#define CEC_IRQHandler USBWakeUp_IRQHandler
tushki7	0:60d829a0353a	5885
tushki7	0:60d829a0353a	5886
tushki7	0:60d829a0353a	5887
tushki7	0:60d829a0353a	5888
tushki7	0:60d829a0353a	5889	/**
tushki7	0:60d829a0353a	5890	* @}
tushki7	0:60d829a0353a	5891	*/
tushki7	0:60d829a0353a	5892
tushki7	0:60d829a0353a	5893	/**
tushki7	0:60d829a0353a	5894	* @}
tushki7	0:60d829a0353a	5895	*/
tushki7	0:60d829a0353a	5896
tushki7	0:60d829a0353a	5897
tushki7	0:60d829a0353a	5898	#ifdef __cplusplus
tushki7	0:60d829a0353a	5899	}
tushki7	0:60d829a0353a	5900	#endif /* __cplusplus */
tushki7	0:60d829a0353a	5901
tushki7	0:60d829a0353a	5902	#endif /* __STM32F103xB_H */
tushki7	0:60d829a0353a	5903
tushki7	0:60d829a0353a	5904
tushki7	0:60d829a0353a	5905
tushki7	0:60d829a0353a	5906	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_NUCLEO_F103RB/stm32f103xb.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

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