FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

Users » tushki7 » Code » FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_LPC4337/LPC43xx.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1	/*
tushki7	0:60d829a0353a	2	* LPC43xx/LPC18xx MCU header
tushki7	0:60d829a0353a	3	*
tushki7	0:60d829a0353a	4	* Copyright(C) NXP Semiconductors, 2012
tushki7	0:60d829a0353a	5	* All rights reserved.
tushki7	0:60d829a0353a	6	*
tushki7	0:60d829a0353a	7	* Software that is described herein is for illustrative purposes only
tushki7	0:60d829a0353a	8	* which provides customers with programming information regarding the
tushki7	0:60d829a0353a	9	* LPC products. This software is supplied "AS IS" without any warranties of
tushki7	0:60d829a0353a	10	* any kind, and NXP Semiconductors and its licensor disclaim any and
tushki7	0:60d829a0353a	11	* all warranties, express or implied, including all implied warranties of
tushki7	0:60d829a0353a	12	* merchantability, fitness for a particular purpose and non-infringement of
tushki7	0:60d829a0353a	13	* intellectual property rights. NXP Semiconductors assumes no responsibility
tushki7	0:60d829a0353a	14	* or liability for the use of the software, conveys no license or rights under any
tushki7	0:60d829a0353a	15	* patent, copyright, mask work right, or any other intellectual property rights in
tushki7	0:60d829a0353a	16	* or to any products. NXP Semiconductors reserves the right to make changes
tushki7	0:60d829a0353a	17	* in the software without notification. NXP Semiconductors also makes no
tushki7	0:60d829a0353a	18	* representation or warranty that such application will be suitable for the
tushki7	0:60d829a0353a	19	* specified use without further testing or modification.
tushki7	0:60d829a0353a	20	*
tushki7	0:60d829a0353a	21	* Permission to use, copy, modify, and distribute this software and its
tushki7	0:60d829a0353a	22	* documentation is hereby granted, under NXP Semiconductors' and its
tushki7	0:60d829a0353a	23	* licensor's relevant copyrights in the software, without fee, provided that it
tushki7	0:60d829a0353a	24	* is used in conjunction with NXP Semiconductors microcontrollers. This
tushki7	0:60d829a0353a	25	* copyright, permission, and disclaimer notice must appear in all copies of
tushki7	0:60d829a0353a	26	* this code.
tushki7	0:60d829a0353a	27	*
tushki7	0:60d829a0353a	28	* Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
tushki7	0:60d829a0353a	29	* 05/15/13 Micromint USA <support@micromint.com>
tushki7	0:60d829a0353a	30	*/
tushki7	0:60d829a0353a	31
tushki7	0:60d829a0353a	32	#ifndef __LPC43XX_H
tushki7	0:60d829a0353a	33	#define __LPC43XX_H
tushki7	0:60d829a0353a	34
tushki7	0:60d829a0353a	35	#ifdef __cplusplus
tushki7	0:60d829a0353a	36	extern "C" {
tushki7	0:60d829a0353a	37	#endif
tushki7	0:60d829a0353a	38
tushki7	0:60d829a0353a	39	/* Treat __CORE_Mx as CORE_Mx */
tushki7	0:60d829a0353a	40	#if defined(__CORTEX_M0) && !defined(CORE_M0)
tushki7	0:60d829a0353a	41	#define CORE_M0
tushki7	0:60d829a0353a	42	#endif
tushki7	0:60d829a0353a	43	#if defined(__CORTEX_M3) && !defined(CORE_M3)
tushki7	0:60d829a0353a	44	#define CORE_M3
tushki7	0:60d829a0353a	45	#endif
tushki7	0:60d829a0353a	46	/* Default to M4 core if no core explicitly declared */
tushki7	0:60d829a0353a	47	#if !defined(CORE_M0) && !defined(CORE_M3)
tushki7	0:60d829a0353a	48	#define CORE_M4
tushki7	0:60d829a0353a	49	#endif
tushki7	0:60d829a0353a	50
tushki7	0:60d829a0353a	51	/* Define LPC18XX or LPC43XX according to core type */
tushki7	0:60d829a0353a	52	#if (defined(CORE_M4) \|\| defined(CORE_M0)) && !defined(__LPC43XX__)
tushki7	0:60d829a0353a	53	#define __LPC43XX__
tushki7	0:60d829a0353a	54	#endif
tushki7	0:60d829a0353a	55	#if defined(CORE_M3) && !defined(__LPC18XX__)
tushki7	0:60d829a0353a	56	#define __LPC18XX__
tushki7	0:60d829a0353a	57	#endif
tushki7	0:60d829a0353a	58
tushki7	0:60d829a0353a	59	/* Start of section using anonymous unions */
tushki7	0:60d829a0353a	60	#if defined(__ARMCC_VERSION)
tushki7	0:60d829a0353a	61	// Kill warning "#pragma push with no matching #pragma pop"
tushki7	0:60d829a0353a	62	#pragma diag_suppress 2525
tushki7	0:60d829a0353a	63	#pragma push
tushki7	0:60d829a0353a	64	#pragma anon_unions
tushki7	0:60d829a0353a	65	#elif defined(__CWCC__)
tushki7	0:60d829a0353a	66	#pragma push
tushki7	0:60d829a0353a	67	#pragma cpp_extensions on
tushki7	0:60d829a0353a	68	#elif defined(__IAR_SYSTEMS_ICC__)
tushki7	0:60d829a0353a	69	//#pragma push // FIXME not usable for IAR
tushki7	0:60d829a0353a	70	#pragma language=extended
tushki7	0:60d829a0353a	71	#else /* defined(__GNUC__) and others */
tushki7	0:60d829a0353a	72	/* Assume anonymous unions are enabled by default */
tushki7	0:60d829a0353a	73	#endif
tushki7	0:60d829a0353a	74
tushki7	0:60d829a0353a	75	#if defined(CORE_M4)
tushki7	0:60d829a0353a	76	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	77	* LPC43xx (M4 Core) Cortex CMSIS definitions
tushki7	0:60d829a0353a	78	*/
tushki7	0:60d829a0353a	79
tushki7	0:60d829a0353a	80	#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
tushki7	0:60d829a0353a	81	#define __MPU_PRESENT 1 /* MPU present or not */
tushki7	0:60d829a0353a	82	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
tushki7	0:60d829a0353a	83	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
tushki7	0:60d829a0353a	84	#define __FPU_PRESENT 1 /* FPU present or not */
tushki7	0:60d829a0353a	85	#define CHIP_LPC43XX /* LPCOPEN compatibility */
tushki7	0:60d829a0353a	86
tushki7	0:60d829a0353a	87	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	88	* LPC43xx peripheral interrupt numbers
tushki7	0:60d829a0353a	89	*/
tushki7	0:60d829a0353a	90
tushki7	0:60d829a0353a	91	typedef enum {
tushki7	0:60d829a0353a	92	/* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
tushki7	0:60d829a0353a	93	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
tushki7	0:60d829a0353a	94	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
tushki7	0:60d829a0353a	95	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
tushki7	0:60d829a0353a	96	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
tushki7	0:60d829a0353a	97	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
tushki7	0:60d829a0353a	98	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
tushki7	0:60d829a0353a	99	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
tushki7	0:60d829a0353a	100	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
tushki7	0:60d829a0353a	101	PendSV_IRQn = -2,/* 14 Pendable request for system service */
tushki7	0:60d829a0353a	102	SysTick_IRQn = -1,/* 15 System Tick Timer */
tushki7	0:60d829a0353a	103
tushki7	0:60d829a0353a	104	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
tushki7	0:60d829a0353a	105	DAC_IRQn = 0,/* 0 DAC */
tushki7	0:60d829a0353a	106	M0CORE_IRQn = 1,/* 1 M0a */
tushki7	0:60d829a0353a	107	DMA_IRQn = 2,/* 2 DMA */
tushki7	0:60d829a0353a	108	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
tushki7	0:60d829a0353a	109	RESERVED2_IRQn = 4,
tushki7	0:60d829a0353a	110	ETHERNET_IRQn = 5,/* 5 ETHERNET */
tushki7	0:60d829a0353a	111	SDIO_IRQn = 6,/* 6 SDIO */
tushki7	0:60d829a0353a	112	LCD_IRQn = 7,/* 7 LCD */
tushki7	0:60d829a0353a	113	USB0_IRQn = 8,/* 8 USB0 */
tushki7	0:60d829a0353a	114	USB1_IRQn = 9,/* 9 USB1 */
tushki7	0:60d829a0353a	115	SCT_IRQn = 10,/* 10 SCT */
tushki7	0:60d829a0353a	116	RITIMER_IRQn = 11,/* 11 RITIMER */
tushki7	0:60d829a0353a	117	TIMER0_IRQn = 12,/* 12 TIMER0 */
tushki7	0:60d829a0353a	118	TIMER1_IRQn = 13,/* 13 TIMER1 */
tushki7	0:60d829a0353a	119	TIMER2_IRQn = 14,/* 14 TIMER2 */
tushki7	0:60d829a0353a	120	TIMER3_IRQn = 15,/* 15 TIMER3 */
tushki7	0:60d829a0353a	121	MCPWM_IRQn = 16,/* 16 MCPWM */
tushki7	0:60d829a0353a	122	ADC0_IRQn = 17,/* 17 ADC0 */
tushki7	0:60d829a0353a	123	I2C0_IRQn = 18,/* 18 I2C0 */
tushki7	0:60d829a0353a	124	I2C1_IRQn = 19,/* 19 I2C1 */
tushki7	0:60d829a0353a	125	SPI_INT_IRQn = 20,/* 20 SPI_INT */
tushki7	0:60d829a0353a	126	ADC1_IRQn = 21,/* 21 ADC1 */
tushki7	0:60d829a0353a	127	SSP0_IRQn = 22,/* 22 SSP0 */
tushki7	0:60d829a0353a	128	SSP1_IRQn = 23,/* 23 SSP1 */
tushki7	0:60d829a0353a	129	USART0_IRQn = 24,/* 24 USART0 */
tushki7	0:60d829a0353a	130	UART1_IRQn = 25,/* 25 UART1 */
tushki7	0:60d829a0353a	131	USART2_IRQn = 26,/* 26 USART2 */
tushki7	0:60d829a0353a	132	USART3_IRQn = 27,/* 27 USART3 */
tushki7	0:60d829a0353a	133	I2S0_IRQn = 28,/* 28 I2S0 */
tushki7	0:60d829a0353a	134	I2S1_IRQn = 29,/* 29 I2S1 */
tushki7	0:60d829a0353a	135	RESERVED4_IRQn = 30,
tushki7	0:60d829a0353a	136	SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
tushki7	0:60d829a0353a	137	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
tushki7	0:60d829a0353a	138	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
tushki7	0:60d829a0353a	139	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
tushki7	0:60d829a0353a	140	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
tushki7	0:60d829a0353a	141	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
tushki7	0:60d829a0353a	142	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
tushki7	0:60d829a0353a	143	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
tushki7	0:60d829a0353a	144	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
tushki7	0:60d829a0353a	145	GINT0_IRQn = 40,/* 40 GINT0 */
tushki7	0:60d829a0353a	146	GINT1_IRQn = 41,/* 41 GINT1 */
tushki7	0:60d829a0353a	147	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
tushki7	0:60d829a0353a	148	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
tushki7	0:60d829a0353a	149	RESERVED6_IRQn = 44,
tushki7	0:60d829a0353a	150	RESERVED7_IRQn = 45,/* 45 VADC */
tushki7	0:60d829a0353a	151	ATIMER_IRQn = 46,/* 46 ATIMER */
tushki7	0:60d829a0353a	152	RTC_IRQn = 47,/* 47 RTC */
tushki7	0:60d829a0353a	153	RESERVED8_IRQn = 48,
tushki7	0:60d829a0353a	154	WWDT_IRQn = 49,/* 49 WWDT */
tushki7	0:60d829a0353a	155	RESERVED9_IRQn = 50,
tushki7	0:60d829a0353a	156	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
tushki7	0:60d829a0353a	157	QEI_IRQn = 52,/* 52 QEI */
tushki7	0:60d829a0353a	158	} IRQn_Type;
tushki7	0:60d829a0353a	159
tushki7	0:60d829a0353a	160	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
tushki7	0:60d829a0353a	161
tushki7	0:60d829a0353a	162	#elif defined(CORE_M3)
tushki7	0:60d829a0353a	163	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	164	* LPC18xx (M3 Core) Cortex CMSIS definitions
tushki7	0:60d829a0353a	165	*/
tushki7	0:60d829a0353a	166	#define __MPU_PRESENT 1 /* MPU present or not */
tushki7	0:60d829a0353a	167	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
tushki7	0:60d829a0353a	168	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
tushki7	0:60d829a0353a	169	#define __FPU_PRESENT 0 /* FPU present or not */
tushki7	0:60d829a0353a	170	#define CHIP_LPC18XX /* LPCOPEN compatibility */
tushki7	0:60d829a0353a	171
tushki7	0:60d829a0353a	172	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	173	* LPC18xx peripheral interrupt numbers
tushki7	0:60d829a0353a	174	*/
tushki7	0:60d829a0353a	175
tushki7	0:60d829a0353a	176	typedef enum {
tushki7	0:60d829a0353a	177	/* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
tushki7	0:60d829a0353a	178	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
tushki7	0:60d829a0353a	179	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
tushki7	0:60d829a0353a	180	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
tushki7	0:60d829a0353a	181	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
tushki7	0:60d829a0353a	182	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
tushki7	0:60d829a0353a	183	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
tushki7	0:60d829a0353a	184	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
tushki7	0:60d829a0353a	185	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
tushki7	0:60d829a0353a	186	PendSV_IRQn = -2,/* 14 Pendable request for system service */
tushki7	0:60d829a0353a	187	SysTick_IRQn = -1,/* 15 System Tick Timer */
tushki7	0:60d829a0353a	188
tushki7	0:60d829a0353a	189	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
tushki7	0:60d829a0353a	190	DAC_IRQn = 0,/* 0 DAC */
tushki7	0:60d829a0353a	191	RESERVED0_IRQn = 1,
tushki7	0:60d829a0353a	192	DMA_IRQn = 2,/* 2 DMA */
tushki7	0:60d829a0353a	193	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
tushki7	0:60d829a0353a	194	RESERVED2_IRQn = 4,
tushki7	0:60d829a0353a	195	ETHERNET_IRQn = 5,/* 5 ETHERNET */
tushki7	0:60d829a0353a	196	SDIO_IRQn = 6,/* 6 SDIO */
tushki7	0:60d829a0353a	197	LCD_IRQn = 7,/* 7 LCD */
tushki7	0:60d829a0353a	198	USB0_IRQn = 8,/* 8 USB0 */
tushki7	0:60d829a0353a	199	USB1_IRQn = 9,/* 9 USB1 */
tushki7	0:60d829a0353a	200	SCT_IRQn = 10,/* 10 SCT */
tushki7	0:60d829a0353a	201	RITIMER_IRQn = 11,/* 11 RITIMER */
tushki7	0:60d829a0353a	202	TIMER0_IRQn = 12,/* 12 TIMER0 */
tushki7	0:60d829a0353a	203	TIMER1_IRQn = 13,/* 13 TIMER1 */
tushki7	0:60d829a0353a	204	TIMER2_IRQn = 14,/* 14 TIMER2 */
tushki7	0:60d829a0353a	205	TIMER3_IRQn = 15,/* 15 TIMER3 */
tushki7	0:60d829a0353a	206	MCPWM_IRQn = 16,/* 16 MCPWM */
tushki7	0:60d829a0353a	207	ADC0_IRQn = 17,/* 17 ADC0 */
tushki7	0:60d829a0353a	208	I2C0_IRQn = 18,/* 18 I2C0 */
tushki7	0:60d829a0353a	209	I2C1_IRQn = 19,/* 19 I2C1 */
tushki7	0:60d829a0353a	210	RESERVED3_IRQn = 20,
tushki7	0:60d829a0353a	211	ADC1_IRQn = 21,/* 21 ADC1 */
tushki7	0:60d829a0353a	212	SSP0_IRQn = 22,/* 22 SSP0 */
tushki7	0:60d829a0353a	213	SSP1_IRQn = 23,/* 23 SSP1 */
tushki7	0:60d829a0353a	214	USART0_IRQn = 24,/* 24 USART0 */
tushki7	0:60d829a0353a	215	UART1_IRQn = 25,/* 25 UART1 */
tushki7	0:60d829a0353a	216	USART2_IRQn = 26,/* 26 USART2 */
tushki7	0:60d829a0353a	217	USART3_IRQn = 27,/* 27 USART3 */
tushki7	0:60d829a0353a	218	I2S0_IRQn = 28,/* 28 I2S0 */
tushki7	0:60d829a0353a	219	I2S1_IRQn = 29,/* 29 I2S1 */
tushki7	0:60d829a0353a	220	RESERVED4_IRQn = 30,
tushki7	0:60d829a0353a	221	RESERVED5_IRQn = 31,
tushki7	0:60d829a0353a	222	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
tushki7	0:60d829a0353a	223	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
tushki7	0:60d829a0353a	224	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
tushki7	0:60d829a0353a	225	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
tushki7	0:60d829a0353a	226	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
tushki7	0:60d829a0353a	227	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
tushki7	0:60d829a0353a	228	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
tushki7	0:60d829a0353a	229	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
tushki7	0:60d829a0353a	230	GINT0_IRQn = 40,/* 40 GINT0 */
tushki7	0:60d829a0353a	231	GINT1_IRQn = 41,/* 41 GINT1 */
tushki7	0:60d829a0353a	232	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
tushki7	0:60d829a0353a	233	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
tushki7	0:60d829a0353a	234	RESERVED6_IRQn = 44,
tushki7	0:60d829a0353a	235	RESERVED7_IRQn = 45,/* 45 VADC */
tushki7	0:60d829a0353a	236	ATIMER_IRQn = 46,/* 46 ATIMER */
tushki7	0:60d829a0353a	237	RTC_IRQn = 47,/* 47 RTC */
tushki7	0:60d829a0353a	238	RESERVED8_IRQn = 48,
tushki7	0:60d829a0353a	239	WWDT_IRQn = 49,/* 49 WWDT */
tushki7	0:60d829a0353a	240	RESERVED9_IRQn = 50,
tushki7	0:60d829a0353a	241	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
tushki7	0:60d829a0353a	242	QEI_IRQn = 52,/* 52 QEI */
tushki7	0:60d829a0353a	243	} IRQn_Type;
tushki7	0:60d829a0353a	244
tushki7	0:60d829a0353a	245	#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
tushki7	0:60d829a0353a	246
tushki7	0:60d829a0353a	247	#elif defined(CORE_M0)
tushki7	0:60d829a0353a	248	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	249	* LPC43xx (M0 Core) Cortex CMSIS definitions
tushki7	0:60d829a0353a	250	*/
tushki7	0:60d829a0353a	251
tushki7	0:60d829a0353a	252	#define __MPU_PRESENT 0 /* MPU present or not */
tushki7	0:60d829a0353a	253	#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
tushki7	0:60d829a0353a	254	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
tushki7	0:60d829a0353a	255	#define __FPU_PRESENT 0 /* FPU present or not */
tushki7	0:60d829a0353a	256	#define CHIP_LPC43XX /* LPCOPEN compatibility */
tushki7	0:60d829a0353a	257
tushki7	0:60d829a0353a	258	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	259	* LPC43xx (M0 Core) peripheral interrupt numbers
tushki7	0:60d829a0353a	260	*/
tushki7	0:60d829a0353a	261
tushki7	0:60d829a0353a	262	typedef enum {
tushki7	0:60d829a0353a	263	/* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
tushki7	0:60d829a0353a	264	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
tushki7	0:60d829a0353a	265	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
tushki7	0:60d829a0353a	266	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
tushki7	0:60d829a0353a	267	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
tushki7	0:60d829a0353a	268	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
tushki7	0:60d829a0353a	269	PendSV_IRQn = -2,/* 14 Pendable request for system service */
tushki7	0:60d829a0353a	270	SysTick_IRQn = -1,/* 15 System Tick Timer */
tushki7	0:60d829a0353a	271
tushki7	0:60d829a0353a	272	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
tushki7	0:60d829a0353a	273	DAC_IRQn = 0,/* 0 DAC */
tushki7	0:60d829a0353a	274	M0_M4CORE_IRQn = 1,/* 1 M0a */
tushki7	0:60d829a0353a	275	DMA_IRQn = 2,/* 2 DMA r */
tushki7	0:60d829a0353a	276	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
tushki7	0:60d829a0353a	277	FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
tushki7	0:60d829a0353a	278	ETHERNET_IRQn = 5,/* 5 ETHERNET */
tushki7	0:60d829a0353a	279	SDIO_IRQn = 6,/* 6 SDIO */
tushki7	0:60d829a0353a	280	LCD_IRQn = 7,/* 7 LCD */
tushki7	0:60d829a0353a	281	USB0_IRQn = 8,/* 8 USB0 */
tushki7	0:60d829a0353a	282	USB1_IRQn = 9,/* 9 USB1 */
tushki7	0:60d829a0353a	283	SCT_IRQn = 10,/* 10 SCT */
tushki7	0:60d829a0353a	284	RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
tushki7	0:60d829a0353a	285	TIMER0_IRQn = 12,/* 12 TIMER0 */
tushki7	0:60d829a0353a	286	GINT1_IRQn = 13,/* 13 GINT1 */
tushki7	0:60d829a0353a	287	PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
tushki7	0:60d829a0353a	288	TIMER3_IRQn = 15,/* 15 TIMER3 */
tushki7	0:60d829a0353a	289	MCPWM_IRQn = 16,/* 16 MCPWM */
tushki7	0:60d829a0353a	290	ADC0_IRQn = 17,/* 17 ADC0 */
tushki7	0:60d829a0353a	291	I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
tushki7	0:60d829a0353a	292	SGPIO_INT_IRQn = 19,/* 19 SGPIO */
tushki7	0:60d829a0353a	293	SPI_INT_IRQn = 20,/* 20 SPI_INT */
tushki7	0:60d829a0353a	294	ADC1_IRQn = 21,/* 21 ADC1 */
tushki7	0:60d829a0353a	295	SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
tushki7	0:60d829a0353a	296	EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
tushki7	0:60d829a0353a	297	USART0_IRQn = 24,/* 24 USART0 */
tushki7	0:60d829a0353a	298	UART1_IRQn = 25,/* 25 UART1 */
tushki7	0:60d829a0353a	299	USART2_IRQn = 26,/* 26 USART2 */
tushki7	0:60d829a0353a	300	USART3_IRQn = 27,/* 27 USART3 */
tushki7	0:60d829a0353a	301	I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
tushki7	0:60d829a0353a	302	C_CAN0_IRQn = 29,/* 29 C_CAN0 */
tushki7	0:60d829a0353a	303	I2S1_IRQn = 29,/* 29 I2S1 */
tushki7	0:60d829a0353a	304	RESERVED2_IRQn = 30,
tushki7	0:60d829a0353a	305	RESERVED3_IRQn = 31,
tushki7	0:60d829a0353a	306	} IRQn_Type;
tushki7	0:60d829a0353a	307
tushki7	0:60d829a0353a	308	#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
tushki7	0:60d829a0353a	309	#else
tushki7	0:60d829a0353a	310	#error Please #define CORE_M0, CORE_M3 or CORE_M4
tushki7	0:60d829a0353a	311	#endif
tushki7	0:60d829a0353a	312
tushki7	0:60d829a0353a	313	#include "system_LPC43xx.h"
tushki7	0:60d829a0353a	314
tushki7	0:60d829a0353a	315	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	316	* State Configurable Timer register block structure
tushki7	0:60d829a0353a	317	*/
tushki7	0:60d829a0353a	318	#define LPC_SCT_BASE 0x40000000
tushki7	0:60d829a0353a	319	#define CONFIG_SCT_nEV (16) /* Number of events */
tushki7	0:60d829a0353a	320	#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
tushki7	0:60d829a0353a	321	#define CONFIG_SCT_nOU (16) /* Number of outputs */
tushki7	0:60d829a0353a	322
tushki7	0:60d829a0353a	323	typedef struct {
tushki7	0:60d829a0353a	324	__IO uint32_t CONFIG; /* Configuration Register */
tushki7	0:60d829a0353a	325	union {
tushki7	0:60d829a0353a	326	__IO uint32_t CTRL_U; /* Control Register */
tushki7	0:60d829a0353a	327	struct {
tushki7	0:60d829a0353a	328	__IO uint16_t CTRL_L; /* Low control register */
tushki7	0:60d829a0353a	329	__IO uint16_t CTRL_H; /* High control register */
tushki7	0:60d829a0353a	330	};
tushki7	0:60d829a0353a	331
tushki7	0:60d829a0353a	332	};
tushki7	0:60d829a0353a	333
tushki7	0:60d829a0353a	334	__IO uint16_t LIMIT_L; /* limit register for counter L */
tushki7	0:60d829a0353a	335	__IO uint16_t LIMIT_H; /* limit register for counter H */
tushki7	0:60d829a0353a	336	__IO uint16_t HALT_L; /* halt register for counter L */
tushki7	0:60d829a0353a	337	__IO uint16_t HALT_H; /* halt register for counter H */
tushki7	0:60d829a0353a	338	__IO uint16_t STOP_L; /* stop register for counter L */
tushki7	0:60d829a0353a	339	__IO uint16_t STOP_H; /* stop register for counter H */
tushki7	0:60d829a0353a	340	__IO uint16_t START_L; /* start register for counter L */
tushki7	0:60d829a0353a	341	__IO uint16_t START_H; /* start register for counter H */
tushki7	0:60d829a0353a	342	uint32_t RESERVED1[10]; /* 0x03C reserved */
tushki7	0:60d829a0353a	343	union {
tushki7	0:60d829a0353a	344	__IO uint32_t COUNT_U; /* counter register */
tushki7	0:60d829a0353a	345	struct {
tushki7	0:60d829a0353a	346	__IO uint16_t COUNT_L; /* counter register for counter L */
tushki7	0:60d829a0353a	347	__IO uint16_t COUNT_H; /* counter register for counter H */
tushki7	0:60d829a0353a	348	};
tushki7	0:60d829a0353a	349
tushki7	0:60d829a0353a	350	};
tushki7	0:60d829a0353a	351
tushki7	0:60d829a0353a	352	__IO uint16_t STATE_L; /* state register for counter L */
tushki7	0:60d829a0353a	353	__IO uint16_t STATE_H; /* state register for counter H */
tushki7	0:60d829a0353a	354	__I uint32_t INPUT; /* input register */
tushki7	0:60d829a0353a	355	__IO uint16_t REGMODE_L; /* match - capture registers mode register L */
tushki7	0:60d829a0353a	356	__IO uint16_t REGMODE_H; /* match - capture registers mode register H */
tushki7	0:60d829a0353a	357	__IO uint32_t OUTPUT; /* output register */
tushki7	0:60d829a0353a	358	__IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
tushki7	0:60d829a0353a	359	__IO uint32_t RES; /* conflict resolution register */
tushki7	0:60d829a0353a	360	__IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
tushki7	0:60d829a0353a	361	__IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
tushki7	0:60d829a0353a	362	uint32_t RESERVED2[35];
tushki7	0:60d829a0353a	363	__IO uint32_t EVEN; /* event enable register */
tushki7	0:60d829a0353a	364	__IO uint32_t EVFLAG; /* event flag register */
tushki7	0:60d829a0353a	365	__IO uint32_t CONEN; /* conflict enable register */
tushki7	0:60d829a0353a	366	__IO uint32_t CONFLAG; /* conflict flag register */
tushki7	0:60d829a0353a	367	union {
tushki7	0:60d829a0353a	368	__IO union { /* ... Match / Capture value */
tushki7	0:60d829a0353a	369	uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
tushki7	0:60d829a0353a	370	struct {
tushki7	0:60d829a0353a	371	uint16_t L; /* SCTMATCH[i].L Access to L value */
tushki7	0:60d829a0353a	372	uint16_t H; /* SCTMATCH[i].H Access to H value */
tushki7	0:60d829a0353a	373	};
tushki7	0:60d829a0353a	374
tushki7	0:60d829a0353a	375	} MATCH[CONFIG_SCT_nRG];
tushki7	0:60d829a0353a	376
tushki7	0:60d829a0353a	377	__I union {
tushki7	0:60d829a0353a	378	uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
tushki7	0:60d829a0353a	379	struct {
tushki7	0:60d829a0353a	380	uint16_t L; /* SCTCAP[i].L Access to L value */
tushki7	0:60d829a0353a	381	uint16_t H; /* SCTCAP[i].H Access to H value */
tushki7	0:60d829a0353a	382	};
tushki7	0:60d829a0353a	383
tushki7	0:60d829a0353a	384	} CAP[CONFIG_SCT_nRG];
tushki7	0:60d829a0353a	385
tushki7	0:60d829a0353a	386	};
tushki7	0:60d829a0353a	387
tushki7	0:60d829a0353a	388	uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
tushki7	0:60d829a0353a	389	union {
tushki7	0:60d829a0353a	390	__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
tushki7	0:60d829a0353a	391	__I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
tushki7	0:60d829a0353a	392	};
tushki7	0:60d829a0353a	393
tushki7	0:60d829a0353a	394	uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
tushki7	0:60d829a0353a	395	union {
tushki7	0:60d829a0353a	396	__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
tushki7	0:60d829a0353a	397	__I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
tushki7	0:60d829a0353a	398	};
tushki7	0:60d829a0353a	399
tushki7	0:60d829a0353a	400	uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
tushki7	0:60d829a0353a	401	union {
tushki7	0:60d829a0353a	402	__IO union { /* 0x200-... Match Reload / Capture Control value */
tushki7	0:60d829a0353a	403	uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
tushki7	0:60d829a0353a	404	struct {
tushki7	0:60d829a0353a	405	uint16_t L; /* SCTMATCHREL[i].L Access to L value */
tushki7	0:60d829a0353a	406	uint16_t H; /* SCTMATCHREL[i].H Access to H value */
tushki7	0:60d829a0353a	407	};
tushki7	0:60d829a0353a	408
tushki7	0:60d829a0353a	409	} MATCHREL[CONFIG_SCT_nRG];
tushki7	0:60d829a0353a	410
tushki7	0:60d829a0353a	411	__IO union {
tushki7	0:60d829a0353a	412	uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
tushki7	0:60d829a0353a	413	struct {
tushki7	0:60d829a0353a	414	uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
tushki7	0:60d829a0353a	415	uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
tushki7	0:60d829a0353a	416	};
tushki7	0:60d829a0353a	417
tushki7	0:60d829a0353a	418	} CAPCTRL[CONFIG_SCT_nRG];
tushki7	0:60d829a0353a	419
tushki7	0:60d829a0353a	420	};
tushki7	0:60d829a0353a	421
tushki7	0:60d829a0353a	422	uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
tushki7	0:60d829a0353a	423	union {
tushki7	0:60d829a0353a	424	__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
tushki7	0:60d829a0353a	425	__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
tushki7	0:60d829a0353a	426	};
tushki7	0:60d829a0353a	427
tushki7	0:60d829a0353a	428	uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
tushki7	0:60d829a0353a	429	union {
tushki7	0:60d829a0353a	430	__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
tushki7	0:60d829a0353a	431	__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
tushki7	0:60d829a0353a	432	};
tushki7	0:60d829a0353a	433
tushki7	0:60d829a0353a	434	uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
tushki7	0:60d829a0353a	435	__IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
tushki7	0:60d829a0353a	436	uint32_t STATE; /* Event State Register */
tushki7	0:60d829a0353a	437	uint32_t CTRL; /* Event Control Register */
tushki7	0:60d829a0353a	438	} EVENT[CONFIG_SCT_nEV];
tushki7	0:60d829a0353a	439
tushki7	0:60d829a0353a	440	uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
tushki7	0:60d829a0353a	441	__IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
tushki7	0:60d829a0353a	442	uint32_t SET; /* Output n Set Register */
tushki7	0:60d829a0353a	443	uint32_t CLR; /* Output n Clear Register */
tushki7	0:60d829a0353a	444	} OUT[CONFIG_SCT_nOU];
tushki7	0:60d829a0353a	445
tushki7	0:60d829a0353a	446	uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
tushki7	0:60d829a0353a	447	__I uint32_t MODULECONTENT; /* 0x7FC Module Content */
tushki7	0:60d829a0353a	448	} LPC_SCT_T;
tushki7	0:60d829a0353a	449
tushki7	0:60d829a0353a	450	/* Macro defines for SCT configuration register */
tushki7	0:60d829a0353a	451	#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
tushki7	0:60d829a0353a	452	#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
tushki7	0:60d829a0353a	453
tushki7	0:60d829a0353a	454	#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
tushki7	0:60d829a0353a	455	#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
tushki7	0:60d829a0353a	456	#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
tushki7	0:60d829a0353a	457	#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
tushki7	0:60d829a0353a	458
tushki7	0:60d829a0353a	459	#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
tushki7	0:60d829a0353a	460	#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
tushki7	0:60d829a0353a	461
tushki7	0:60d829a0353a	462	/* Macro defines for SCT control register */
tushki7	0:60d829a0353a	463	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
tushki7	0:60d829a0353a	464	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
tushki7	0:60d829a0353a	465
tushki7	0:60d829a0353a	466	#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
tushki7	0:60d829a0353a	467	#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
tushki7	0:60d829a0353a	468	#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
tushki7	0:60d829a0353a	469	#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
tushki7	0:60d829a0353a	470	#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
tushki7	0:60d829a0353a	471
tushki7	0:60d829a0353a	472	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
tushki7	0:60d829a0353a	473	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
tushki7	0:60d829a0353a	474	#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
tushki7	0:60d829a0353a	475	#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
tushki7	0:60d829a0353a	476	#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
tushki7	0:60d829a0353a	477	#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
tushki7	0:60d829a0353a	478	#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
tushki7	0:60d829a0353a	479
tushki7	0:60d829a0353a	480	/* Macro defines for SCT Conflict resolution register */
tushki7	0:60d829a0353a	481	#define SCT_RES_NOCHANGE (0)
tushki7	0:60d829a0353a	482	#define SCT_RES_SET_OUTPUT (1)
tushki7	0:60d829a0353a	483	#define SCT_RES_CLEAR_OUTPUT (2)
tushki7	0:60d829a0353a	484	#define SCT_RES_TOGGLE_OUTPUT (3)
tushki7	0:60d829a0353a	485
tushki7	0:60d829a0353a	486	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	487	* GPDMA Channel register block structure
tushki7	0:60d829a0353a	488	*/
tushki7	0:60d829a0353a	489	#define LPC_GPDMA_BASE 0x40002000
tushki7	0:60d829a0353a	490
tushki7	0:60d829a0353a	491	typedef struct {
tushki7	0:60d829a0353a	492	__IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
tushki7	0:60d829a0353a	493	__IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
tushki7	0:60d829a0353a	494	__IO uint32_t LLI; /* DMA Channel Linked List Item Register */
tushki7	0:60d829a0353a	495	__IO uint32_t CONTROL; /* DMA Channel Control Register */
tushki7	0:60d829a0353a	496	__IO uint32_t CONFIG; /* DMA Channel Configuration Register */
tushki7	0:60d829a0353a	497	__I uint32_t RESERVED1[3];
tushki7	0:60d829a0353a	498	} LPC_GPDMA_CH_T;
tushki7	0:60d829a0353a	499
tushki7	0:60d829a0353a	500	#define GPDMA_CHANNELS 8
tushki7	0:60d829a0353a	501
tushki7	0:60d829a0353a	502	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	503	* GPDMA register block
tushki7	0:60d829a0353a	504	*/
tushki7	0:60d829a0353a	505	typedef struct { /* GPDMA Structure */
tushki7	0:60d829a0353a	506	__I uint32_t INTSTAT; /* DMA Interrupt Status Register */
tushki7	0:60d829a0353a	507	__I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
tushki7	0:60d829a0353a	508	__O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
tushki7	0:60d829a0353a	509	__I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
tushki7	0:60d829a0353a	510	__O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
tushki7	0:60d829a0353a	511	__I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
tushki7	0:60d829a0353a	512	__I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
tushki7	0:60d829a0353a	513	__I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
tushki7	0:60d829a0353a	514	__IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
tushki7	0:60d829a0353a	515	__IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
tushki7	0:60d829a0353a	516	__IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
tushki7	0:60d829a0353a	517	__IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
tushki7	0:60d829a0353a	518	__IO uint32_t CONFIG; /* DMA Configuration Register */
tushki7	0:60d829a0353a	519	__IO uint32_t SYNC; /* DMA Synchronization Register */
tushki7	0:60d829a0353a	520	__I uint32_t RESERVED0[50];
tushki7	0:60d829a0353a	521	LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
tushki7	0:60d829a0353a	522	} LPC_GPDMA_T;
tushki7	0:60d829a0353a	523
tushki7	0:60d829a0353a	524	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	525	* SPIFI register block structure
tushki7	0:60d829a0353a	526	*/
tushki7	0:60d829a0353a	527	#define LPC_SPIFI_BASE 0x40003000
tushki7	0:60d829a0353a	528
tushki7	0:60d829a0353a	529	typedef struct { /* SPIFI Structure */
tushki7	0:60d829a0353a	530	__IO uint32_t CTRL; /* Control register */
tushki7	0:60d829a0353a	531	__IO uint32_t CMD; /* Command register */
tushki7	0:60d829a0353a	532	__IO uint32_t ADDR; /* Address register */
tushki7	0:60d829a0353a	533	__IO uint32_t IDATA; /* Intermediate data register */
tushki7	0:60d829a0353a	534	__IO uint32_t CLIMIT; /* Cache limit register */
tushki7	0:60d829a0353a	535	union {
tushki7	0:60d829a0353a	536	__IO uint32_t DATA;
tushki7	0:60d829a0353a	537	__IO uint16_t DATA_HWORD;
tushki7	0:60d829a0353a	538	__IO uint8_t DATA_BYTE;
tushki7	0:60d829a0353a	539	}; /* Data register */
tushki7	0:60d829a0353a	540	__IO uint32_t MCMD; /* Memory command register */
tushki7	0:60d829a0353a	541	__IO uint32_t STAT; /* Status register */
tushki7	0:60d829a0353a	542	} LPC_SPIFI_T;
tushki7	0:60d829a0353a	543
tushki7	0:60d829a0353a	544	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	545	* SD/MMC & SDIO register block structure
tushki7	0:60d829a0353a	546	*/
tushki7	0:60d829a0353a	547	#define LPC_SDMMC_BASE 0x40004000
tushki7	0:60d829a0353a	548
tushki7	0:60d829a0353a	549	typedef struct { /* SDMMC Structure */
tushki7	0:60d829a0353a	550	__IO uint32_t CTRL; /* Control Register */
tushki7	0:60d829a0353a	551	__IO uint32_t PWREN; /* Power Enable Register */
tushki7	0:60d829a0353a	552	__IO uint32_t CLKDIV; /* Clock Divider Register */
tushki7	0:60d829a0353a	553	__IO uint32_t CLKSRC; /* SD Clock Source Register */
tushki7	0:60d829a0353a	554	__IO uint32_t CLKENA; /* Clock Enable Register */
tushki7	0:60d829a0353a	555	__IO uint32_t TMOUT; /* Timeout Register */
tushki7	0:60d829a0353a	556	__IO uint32_t CTYPE; /* Card Type Register */
tushki7	0:60d829a0353a	557	__IO uint32_t BLKSIZ; /* Block Size Register */
tushki7	0:60d829a0353a	558	__IO uint32_t BYTCNT; /* Byte Count Register */
tushki7	0:60d829a0353a	559	__IO uint32_t INTMASK; /* Interrupt Mask Register */
tushki7	0:60d829a0353a	560	__IO uint32_t CMDARG; /* Command Argument Register */
tushki7	0:60d829a0353a	561	__IO uint32_t CMD; /* Command Register */
tushki7	0:60d829a0353a	562	__I uint32_t RESP0; /* Response Register 0 */
tushki7	0:60d829a0353a	563	__I uint32_t RESP1; /* Response Register 1 */
tushki7	0:60d829a0353a	564	__I uint32_t RESP2; /* Response Register 2 */
tushki7	0:60d829a0353a	565	__I uint32_t RESP3; /* Response Register 3 */
tushki7	0:60d829a0353a	566	__I uint32_t MINTSTS; /* Masked Interrupt Status Register */
tushki7	0:60d829a0353a	567	__IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
tushki7	0:60d829a0353a	568	__I uint32_t STATUS; /* Status Register */
tushki7	0:60d829a0353a	569	__IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
tushki7	0:60d829a0353a	570	__I uint32_t CDETECT; /* Card Detect Register */
tushki7	0:60d829a0353a	571	__I uint32_t WRTPRT; /* Write Protect Register */
tushki7	0:60d829a0353a	572	__IO uint32_t GPIO; /* General Purpose Input/Output Register */
tushki7	0:60d829a0353a	573	__I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
tushki7	0:60d829a0353a	574	__I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
tushki7	0:60d829a0353a	575	__IO uint32_t DEBNCE; /* Debounce Count Register */
tushki7	0:60d829a0353a	576	__IO uint32_t USRID; /* User ID Register */
tushki7	0:60d829a0353a	577	__I uint32_t VERID; /* Version ID Register */
tushki7	0:60d829a0353a	578	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	579	__IO uint32_t UHS_REG; /* UHS-1 Register */
tushki7	0:60d829a0353a	580	__IO uint32_t RST_N; /* Hardware Reset */
tushki7	0:60d829a0353a	581	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	582	__IO uint32_t BMOD; /* Bus Mode Register */
tushki7	0:60d829a0353a	583	__O uint32_t PLDMND; /* Poll Demand Register */
tushki7	0:60d829a0353a	584	__IO uint32_t DBADDR; /* Descriptor List Base Address Register */
tushki7	0:60d829a0353a	585	__IO uint32_t IDSTS; /* Internal DMAC Status Register */
tushki7	0:60d829a0353a	586	__IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
tushki7	0:60d829a0353a	587	__I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
tushki7	0:60d829a0353a	588	__I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
tushki7	0:60d829a0353a	589	} LPC_SDMMC_T;
tushki7	0:60d829a0353a	590
tushki7	0:60d829a0353a	591	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	592	* External Memory Controller (EMC) register block structure
tushki7	0:60d829a0353a	593	*/
tushki7	0:60d829a0353a	594	#define LPC_EMC_BASE 0x40005000
tushki7	0:60d829a0353a	595
tushki7	0:60d829a0353a	596	typedef struct { /* EMC Structure */
tushki7	0:60d829a0353a	597	__IO uint32_t CONTROL; /* Controls operation of the memory controller. */
tushki7	0:60d829a0353a	598	__I uint32_t STATUS; /* Provides EMC status information. */
tushki7	0:60d829a0353a	599	__IO uint32_t CONFIG; /* Configures operation of the memory controller. */
tushki7	0:60d829a0353a	600	__I uint32_t RESERVED0[5];
tushki7	0:60d829a0353a	601	__IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
tushki7	0:60d829a0353a	602	__IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
tushki7	0:60d829a0353a	603	__IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
tushki7	0:60d829a0353a	604	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	605	__IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
tushki7	0:60d829a0353a	606	__IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
tushki7	0:60d829a0353a	607	__IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
tushki7	0:60d829a0353a	608	__IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
tushki7	0:60d829a0353a	609	__IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
tushki7	0:60d829a0353a	610	__IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
tushki7	0:60d829a0353a	611	__IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
tushki7	0:60d829a0353a	612	__IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
tushki7	0:60d829a0353a	613	__IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
tushki7	0:60d829a0353a	614	__IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
tushki7	0:60d829a0353a	615	__IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
tushki7	0:60d829a0353a	616	__I uint32_t RESERVED2[9];
tushki7	0:60d829a0353a	617	__IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
tushki7	0:60d829a0353a	618	__I uint32_t RESERVED3[31];
tushki7	0:60d829a0353a	619	__IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
tushki7	0:60d829a0353a	620	__IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
tushki7	0:60d829a0353a	621	__I uint32_t RESERVED4[6];
tushki7	0:60d829a0353a	622	__IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
tushki7	0:60d829a0353a	623	__IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
tushki7	0:60d829a0353a	624	__I uint32_t RESERVED5[6];
tushki7	0:60d829a0353a	625	__IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
tushki7	0:60d829a0353a	626	__IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
tushki7	0:60d829a0353a	627	__I uint32_t RESERVED6[6];
tushki7	0:60d829a0353a	628	__IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
tushki7	0:60d829a0353a	629	__IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
tushki7	0:60d829a0353a	630	__I uint32_t RESERVED7[38];
tushki7	0:60d829a0353a	631	__IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
tushki7	0:60d829a0353a	632	__IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
tushki7	0:60d829a0353a	633	__IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
tushki7	0:60d829a0353a	634	__IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
tushki7	0:60d829a0353a	635	__IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
tushki7	0:60d829a0353a	636	__IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
tushki7	0:60d829a0353a	637	__IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
tushki7	0:60d829a0353a	638	__I uint32_t RESERVED8;
tushki7	0:60d829a0353a	639	__IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
tushki7	0:60d829a0353a	640	__IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
tushki7	0:60d829a0353a	641	__IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
tushki7	0:60d829a0353a	642	__IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
tushki7	0:60d829a0353a	643	__IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
tushki7	0:60d829a0353a	644	__IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
tushki7	0:60d829a0353a	645	__IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
tushki7	0:60d829a0353a	646	__I uint32_t RESERVED9;
tushki7	0:60d829a0353a	647	__IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
tushki7	0:60d829a0353a	648	__IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
tushki7	0:60d829a0353a	649	__IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
tushki7	0:60d829a0353a	650	__IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
tushki7	0:60d829a0353a	651	__IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
tushki7	0:60d829a0353a	652	__IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
tushki7	0:60d829a0353a	653	__IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
tushki7	0:60d829a0353a	654	__I uint32_t RESERVED10;
tushki7	0:60d829a0353a	655	__IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
tushki7	0:60d829a0353a	656	__IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
tushki7	0:60d829a0353a	657	__IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
tushki7	0:60d829a0353a	658	__IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
tushki7	0:60d829a0353a	659	__IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
tushki7	0:60d829a0353a	660	__IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
tushki7	0:60d829a0353a	661	__IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
tushki7	0:60d829a0353a	662	} LPC_EMC_T;
tushki7	0:60d829a0353a	663
tushki7	0:60d829a0353a	664	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	665	* USB High-Speed register block structure
tushki7	0:60d829a0353a	666	*/
tushki7	0:60d829a0353a	667	#define LPC_USB0_BASE 0x40006000
tushki7	0:60d829a0353a	668	#define LPC_USB1_BASE 0x40007000
tushki7	0:60d829a0353a	669
tushki7	0:60d829a0353a	670	typedef struct { /* USB Structure */
tushki7	0:60d829a0353a	671	__I uint32_t RESERVED0[64];
tushki7	0:60d829a0353a	672	__I uint32_t CAPLENGTH; /* Capability register length */
tushki7	0:60d829a0353a	673	__I uint32_t HCSPARAMS; /* Host controller structural parameters */
tushki7	0:60d829a0353a	674	__I uint32_t HCCPARAMS; /* Host controller capability parameters */
tushki7	0:60d829a0353a	675	__I uint32_t RESERVED1[5];
tushki7	0:60d829a0353a	676	__I uint32_t DCIVERSION; /* Device interface version number */
tushki7	0:60d829a0353a	677	__I uint32_t RESERVED2[7];
tushki7	0:60d829a0353a	678	union {
tushki7	0:60d829a0353a	679	__IO uint32_t USBCMD_H; /* USB command (host mode) */
tushki7	0:60d829a0353a	680	__IO uint32_t USBCMD_D; /* USB command (device mode) */
tushki7	0:60d829a0353a	681	};
tushki7	0:60d829a0353a	682
tushki7	0:60d829a0353a	683	union {
tushki7	0:60d829a0353a	684	__IO uint32_t USBSTS_H; /* USB status (host mode) */
tushki7	0:60d829a0353a	685	__IO uint32_t USBSTS_D; /* USB status (device mode) */
tushki7	0:60d829a0353a	686	};
tushki7	0:60d829a0353a	687
tushki7	0:60d829a0353a	688	union {
tushki7	0:60d829a0353a	689	__IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
tushki7	0:60d829a0353a	690	__IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
tushki7	0:60d829a0353a	691	};
tushki7	0:60d829a0353a	692
tushki7	0:60d829a0353a	693	union {
tushki7	0:60d829a0353a	694	__IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
tushki7	0:60d829a0353a	695	__I uint32_t FRINDEX_D; /* USB frame index (device mode) */
tushki7	0:60d829a0353a	696	};
tushki7	0:60d829a0353a	697
tushki7	0:60d829a0353a	698	__I uint32_t RESERVED3;
tushki7	0:60d829a0353a	699	union {
tushki7	0:60d829a0353a	700	__IO uint32_t PERIODICLISTBASE; /* Frame list base address */
tushki7	0:60d829a0353a	701	__IO uint32_t DEVICEADDR; /* USB device address */
tushki7	0:60d829a0353a	702	};
tushki7	0:60d829a0353a	703
tushki7	0:60d829a0353a	704	union {
tushki7	0:60d829a0353a	705	__IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
tushki7	0:60d829a0353a	706	__IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
tushki7	0:60d829a0353a	707	};
tushki7	0:60d829a0353a	708
tushki7	0:60d829a0353a	709	__IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
tushki7	0:60d829a0353a	710	__IO uint32_t BURSTSIZE; /* Programmable burst size */
tushki7	0:60d829a0353a	711	__IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
tushki7	0:60d829a0353a	712	__I uint32_t RESERVED4[2];
tushki7	0:60d829a0353a	713	__IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
tushki7	0:60d829a0353a	714	__IO uint32_t BINTERVAL; /* Length of virtual frame */
tushki7	0:60d829a0353a	715	__IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
tushki7	0:60d829a0353a	716	__IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
tushki7	0:60d829a0353a	717	__I uint32_t RESERVED5;
tushki7	0:60d829a0353a	718	union {
tushki7	0:60d829a0353a	719	__IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
tushki7	0:60d829a0353a	720	__IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
tushki7	0:60d829a0353a	721	};
tushki7	0:60d829a0353a	722
tushki7	0:60d829a0353a	723	__I uint32_t RESERVED6[7];
tushki7	0:60d829a0353a	724	__IO uint32_t OTGSC; /* OTG status and control */
tushki7	0:60d829a0353a	725	union {
tushki7	0:60d829a0353a	726	__IO uint32_t USBMODE_H; /* USB mode (host mode) */
tushki7	0:60d829a0353a	727	__IO uint32_t USBMODE_D; /* USB mode (device mode) */
tushki7	0:60d829a0353a	728	};
tushki7	0:60d829a0353a	729
tushki7	0:60d829a0353a	730	__IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
tushki7	0:60d829a0353a	731	__IO uint32_t ENDPTPRIME; /* Endpoint initialization */
tushki7	0:60d829a0353a	732	__IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
tushki7	0:60d829a0353a	733	__I uint32_t ENDPTSTAT; /* Endpoint status */
tushki7	0:60d829a0353a	734	__IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
tushki7	0:60d829a0353a	735	__IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
tushki7	0:60d829a0353a	736	} LPC_USBHS_T;
tushki7	0:60d829a0353a	737
tushki7	0:60d829a0353a	738	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	739	* LCD Controller register block structure
tushki7	0:60d829a0353a	740	*/
tushki7	0:60d829a0353a	741	#define LPC_LCD_BASE 0x40008000
tushki7	0:60d829a0353a	742
tushki7	0:60d829a0353a	743	typedef struct { /* LCD Structure */
tushki7	0:60d829a0353a	744	__IO uint32_t TIMH; /* Horizontal Timing Control register */
tushki7	0:60d829a0353a	745	__IO uint32_t TIMV; /* Vertical Timing Control register */
tushki7	0:60d829a0353a	746	__IO uint32_t POL; /* Clock and Signal Polarity Control register */
tushki7	0:60d829a0353a	747	__IO uint32_t LE; /* Line End Control register */
tushki7	0:60d829a0353a	748	__IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
tushki7	0:60d829a0353a	749	__IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
tushki7	0:60d829a0353a	750	__IO uint32_t CTRL; /* LCD Control register */
tushki7	0:60d829a0353a	751	__IO uint32_t INTMSK; /* Interrupt Mask register */
tushki7	0:60d829a0353a	752	__I uint32_t INTRAW; /* Raw Interrupt Status register */
tushki7	0:60d829a0353a	753	__I uint32_t INTSTAT; /* Masked Interrupt Status register */
tushki7	0:60d829a0353a	754	__O uint32_t INTCLR; /* Interrupt Clear register */
tushki7	0:60d829a0353a	755	__I uint32_t UPCURR; /* Upper Panel Current Address Value register */
tushki7	0:60d829a0353a	756	__I uint32_t LPCURR; /* Lower Panel Current Address Value register */
tushki7	0:60d829a0353a	757	__I uint32_t RESERVED0[115];
tushki7	0:60d829a0353a	758	__IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
tushki7	0:60d829a0353a	759	__I uint32_t RESERVED1[256];
tushki7	0:60d829a0353a	760	__IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
tushki7	0:60d829a0353a	761	__IO uint32_t CRSR_CTRL; /* Cursor Control register */
tushki7	0:60d829a0353a	762	__IO uint32_t CRSR_CFG; /* Cursor Configuration register */
tushki7	0:60d829a0353a	763	__IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
tushki7	0:60d829a0353a	764	__IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
tushki7	0:60d829a0353a	765	__IO uint32_t CRSR_XY; /* Cursor XY Position register */
tushki7	0:60d829a0353a	766	__IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
tushki7	0:60d829a0353a	767	__I uint32_t RESERVED2[2];
tushki7	0:60d829a0353a	768	__IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
tushki7	0:60d829a0353a	769	__O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
tushki7	0:60d829a0353a	770	__I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
tushki7	0:60d829a0353a	771	__I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
tushki7	0:60d829a0353a	772	} LPC_LCD_T;
tushki7	0:60d829a0353a	773
tushki7	0:60d829a0353a	774	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	775	* EEPROM register block structure
tushki7	0:60d829a0353a	776	*/
tushki7	0:60d829a0353a	777	#define LPC_EEPROM_BASE 0x4000E000
tushki7	0:60d829a0353a	778
tushki7	0:60d829a0353a	779	typedef struct { /* EEPROM Structure */
tushki7	0:60d829a0353a	780	__IO uint32_t CMD; /* EEPROM command register */
tushki7	0:60d829a0353a	781	uint32_t RESERVED0;
tushki7	0:60d829a0353a	782	__IO uint32_t RWSTATE; /* EEPROM read wait state register */
tushki7	0:60d829a0353a	783	__IO uint32_t AUTOPROG; /* EEPROM auto programming register */
tushki7	0:60d829a0353a	784	__IO uint32_t WSTATE; /* EEPROM wait state register */
tushki7	0:60d829a0353a	785	__IO uint32_t CLKDIV; /* EEPROM clock divider register */
tushki7	0:60d829a0353a	786	__IO uint32_t PWRDWN; /* EEPROM power-down register */
tushki7	0:60d829a0353a	787	uint32_t RESERVED2[1007];
tushki7	0:60d829a0353a	788	__O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
tushki7	0:60d829a0353a	789	__O uint32_t INTENSET; /* EEPROM interrupt enable set */
tushki7	0:60d829a0353a	790	__I uint32_t INTSTAT; /* EEPROM interrupt status */
tushki7	0:60d829a0353a	791	__I uint32_t INTEN; /* EEPROM interrupt enable */
tushki7	0:60d829a0353a	792	__O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
tushki7	0:60d829a0353a	793	__O uint32_t INTSTATSET; /* EEPROM interrupt status set */
tushki7	0:60d829a0353a	794	} LPC_EEPROM_T;
tushki7	0:60d829a0353a	795
tushki7	0:60d829a0353a	796	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	797	* 10/100 MII & RMII Ethernet with timestamping register block structure
tushki7	0:60d829a0353a	798	*/
tushki7	0:60d829a0353a	799	#define LPC_ETHERNET_BASE 0x40010000
tushki7	0:60d829a0353a	800
tushki7	0:60d829a0353a	801	typedef struct { /* ETHERNET Structure */
tushki7	0:60d829a0353a	802	__IO uint32_t MAC_CONFIG; /* MAC configuration register */
tushki7	0:60d829a0353a	803	__IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
tushki7	0:60d829a0353a	804	__IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
tushki7	0:60d829a0353a	805	__IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
tushki7	0:60d829a0353a	806	__IO uint32_t MAC_MII_ADDR; /* MII address register */
tushki7	0:60d829a0353a	807	__IO uint32_t MAC_MII_DATA; /* MII data register */
tushki7	0:60d829a0353a	808	__IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
tushki7	0:60d829a0353a	809	__IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
tushki7	0:60d829a0353a	810	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	811	__I uint32_t MAC_DEBUG; /* Debug register */
tushki7	0:60d829a0353a	812	__IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
tushki7	0:60d829a0353a	813	__IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
tushki7	0:60d829a0353a	814	__I uint32_t RESERVED1[2];
tushki7	0:60d829a0353a	815	__I uint32_t MAC_INTR; /* Interrupt status register */
tushki7	0:60d829a0353a	816	__IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
tushki7	0:60d829a0353a	817	__IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
tushki7	0:60d829a0353a	818	__IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
tushki7	0:60d829a0353a	819	__I uint32_t RESERVED2[430];
tushki7	0:60d829a0353a	820	__IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
tushki7	0:60d829a0353a	821	__IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
tushki7	0:60d829a0353a	822	__I uint32_t SECONDS; /* System time seconds register */
tushki7	0:60d829a0353a	823	__I uint32_t NANOSECONDS; /* System time nanoseconds register */
tushki7	0:60d829a0353a	824	__IO uint32_t SECONDSUPDATE; /* System time seconds update register */
tushki7	0:60d829a0353a	825	__IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
tushki7	0:60d829a0353a	826	__IO uint32_t ADDEND; /* Time stamp addend register */
tushki7	0:60d829a0353a	827	__IO uint32_t TARGETSECONDS; /* Target time seconds register */
tushki7	0:60d829a0353a	828	__IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
tushki7	0:60d829a0353a	829	__IO uint32_t HIGHWORD; /* System time higher word seconds register */
tushki7	0:60d829a0353a	830	__I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
tushki7	0:60d829a0353a	831	__IO uint32_t PPSCTRL; /* PPS control register */
tushki7	0:60d829a0353a	832	__I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
tushki7	0:60d829a0353a	833	__I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
tushki7	0:60d829a0353a	834	__I uint32_t RESERVED3[562];
tushki7	0:60d829a0353a	835	__IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
tushki7	0:60d829a0353a	836	__IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
tushki7	0:60d829a0353a	837	__IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
tushki7	0:60d829a0353a	838	__IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
tushki7	0:60d829a0353a	839	__IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
tushki7	0:60d829a0353a	840	__IO uint32_t DMA_STAT; /* Status register */
tushki7	0:60d829a0353a	841	__IO uint32_t DMA_OP_MODE; /* Operation mode register */
tushki7	0:60d829a0353a	842	__IO uint32_t DMA_INT_EN; /* Interrupt enable register */
tushki7	0:60d829a0353a	843	__I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
tushki7	0:60d829a0353a	844	__IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
tushki7	0:60d829a0353a	845	__I uint32_t RESERVED4[8];
tushki7	0:60d829a0353a	846	__I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
tushki7	0:60d829a0353a	847	__I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
tushki7	0:60d829a0353a	848	__I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
tushki7	0:60d829a0353a	849	__I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
tushki7	0:60d829a0353a	850	} LPC_ENET_T;
tushki7	0:60d829a0353a	851
tushki7	0:60d829a0353a	852	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	853	* Alarm Timer register block structure
tushki7	0:60d829a0353a	854	*/
tushki7	0:60d829a0353a	855	#define LPC_ATIMER_BASE 0x40040000
tushki7	0:60d829a0353a	856
tushki7	0:60d829a0353a	857	typedef struct { /* ATIMER Structure */
tushki7	0:60d829a0353a	858	__IO uint32_t DOWNCOUNTER; /* Downcounter register */
tushki7	0:60d829a0353a	859	__IO uint32_t PRESET; /* Preset value register */
tushki7	0:60d829a0353a	860	__I uint32_t RESERVED0[1012];
tushki7	0:60d829a0353a	861	__O uint32_t CLR_EN; /* Interrupt clear enable register */
tushki7	0:60d829a0353a	862	__O uint32_t SET_EN; /* Interrupt set enable register */
tushki7	0:60d829a0353a	863	__I uint32_t STATUS; /* Status register */
tushki7	0:60d829a0353a	864	__I uint32_t ENABLE; /* Enable register */
tushki7	0:60d829a0353a	865	__O uint32_t CLR_STAT; /* Clear register */
tushki7	0:60d829a0353a	866	__O uint32_t SET_STAT; /* Set register */
tushki7	0:60d829a0353a	867	} LPC_ATIMER_T;
tushki7	0:60d829a0353a	868
tushki7	0:60d829a0353a	869	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	870	* Register File register block structure
tushki7	0:60d829a0353a	871	*/
tushki7	0:60d829a0353a	872	#define LPC_REGFILE_BASE 0x40041000
tushki7	0:60d829a0353a	873
tushki7	0:60d829a0353a	874	typedef struct {
tushki7	0:60d829a0353a	875	__IO uint32_t REGFILE[64]; /* General purpose storage register */
tushki7	0:60d829a0353a	876	} LPC_REGFILE_T;
tushki7	0:60d829a0353a	877
tushki7	0:60d829a0353a	878	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	879	* Power Management Controller register block structure
tushki7	0:60d829a0353a	880	*/
tushki7	0:60d829a0353a	881	#define LPC_PMC_BASE 0x40042000
tushki7	0:60d829a0353a	882
tushki7	0:60d829a0353a	883	typedef struct { /* PMC Structure */
tushki7	0:60d829a0353a	884	__IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
tushki7	0:60d829a0353a	885	__I uint32_t RESERVED0[6];
tushki7	0:60d829a0353a	886	__IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
tushki7	0:60d829a0353a	887	} LPC_PMC_T;
tushki7	0:60d829a0353a	888
tushki7	0:60d829a0353a	889	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	890	* CREG Register Block
tushki7	0:60d829a0353a	891	*/
tushki7	0:60d829a0353a	892	#define LPC_CREG_BASE 0x40043000
tushki7	0:60d829a0353a	893
tushki7	0:60d829a0353a	894	typedef struct { /* CREG Structure */
tushki7	0:60d829a0353a	895	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	896	__IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
tushki7	0:60d829a0353a	897	__I uint32_t RESERVED1[62];
tushki7	0:60d829a0353a	898	__IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
tushki7	0:60d829a0353a	899	#if defined(CHIP_LPC18XX)
tushki7	0:60d829a0353a	900	__I uint32_t RESERVED2[5];
tushki7	0:60d829a0353a	901	#else
tushki7	0:60d829a0353a	902	__I uint32_t RESERVED2;
tushki7	0:60d829a0353a	903	__I uint32_t CREG1; /* Configuration Register 1 */
tushki7	0:60d829a0353a	904	__I uint32_t CREG2; /* Configuration Register 2 */
tushki7	0:60d829a0353a	905	__I uint32_t CREG3; /* Configuration Register 3 */
tushki7	0:60d829a0353a	906	__I uint32_t CREG4; /* Configuration Register 4 */
tushki7	0:60d829a0353a	907	#endif
tushki7	0:60d829a0353a	908	__IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
tushki7	0:60d829a0353a	909	__IO uint32_t DMAMUX; /* DMA muxing control */
tushki7	0:60d829a0353a	910	__IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
tushki7	0:60d829a0353a	911	__IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
tushki7	0:60d829a0353a	912	__IO uint32_t ETBCFG; /* ETB RAM configuration */
tushki7	0:60d829a0353a	913	__IO uint32_t CREG6; /* Chip configuration register 6. */
tushki7	0:60d829a0353a	914	#if defined(CHIP_LPC18XX)
tushki7	0:60d829a0353a	915	__I uint32_t RESERVED4[52];
tushki7	0:60d829a0353a	916	#else
tushki7	0:60d829a0353a	917	__IO uint32_t M4TXEVENT; /* M4 IPC event register */
tushki7	0:60d829a0353a	918	__I uint32_t RESERVED4[51];
tushki7	0:60d829a0353a	919	#endif
tushki7	0:60d829a0353a	920	__I uint32_t CHIPID; /* Part ID */
tushki7	0:60d829a0353a	921	#if defined(CHIP_LPC18XX)
tushki7	0:60d829a0353a	922	__I uint32_t RESERVED5[191];
tushki7	0:60d829a0353a	923	#else
tushki7	0:60d829a0353a	924	__I uint32_t RESERVED5[127];
tushki7	0:60d829a0353a	925	__IO uint32_t M0TXEVENT; /* M0 IPC Event register */
tushki7	0:60d829a0353a	926	__IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
tushki7	0:60d829a0353a	927	__I uint32_t RESERVED6[62];
tushki7	0:60d829a0353a	928	#endif
tushki7	0:60d829a0353a	929	__IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
tushki7	0:60d829a0353a	930	__I uint32_t RESERVED7[63];
tushki7	0:60d829a0353a	931	__IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
tushki7	0:60d829a0353a	932	} LPC_CREG_T;
tushki7	0:60d829a0353a	933
tushki7	0:60d829a0353a	934	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	935	* Event Router register structure
tushki7	0:60d829a0353a	936	*/
tushki7	0:60d829a0353a	937	#define LPC_EVRT_BASE 0x40044000
tushki7	0:60d829a0353a	938
tushki7	0:60d829a0353a	939	typedef struct { /* EVENTROUTER Structure */
tushki7	0:60d829a0353a	940	__IO uint32_t HILO; /* Level configuration register */
tushki7	0:60d829a0353a	941	__IO uint32_t EDGE; /* Edge configuration */
tushki7	0:60d829a0353a	942	__I uint32_t RESERVED0[1012];
tushki7	0:60d829a0353a	943	__O uint32_t CLR_EN; /* Event clear enable register */
tushki7	0:60d829a0353a	944	__O uint32_t SET_EN; /* Event set enable register */
tushki7	0:60d829a0353a	945	__I uint32_t STATUS; /* Status register */
tushki7	0:60d829a0353a	946	__I uint32_t ENABLE; /* Enable register */
tushki7	0:60d829a0353a	947	__O uint32_t CLR_STAT; /* Clear register */
tushki7	0:60d829a0353a	948	__O uint32_t SET_STAT; /* Set register */
tushki7	0:60d829a0353a	949	} LPC_EVRT_T;
tushki7	0:60d829a0353a	950
tushki7	0:60d829a0353a	951	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	952	* Real Time Clock register block structure
tushki7	0:60d829a0353a	953	*/
tushki7	0:60d829a0353a	954	#define LPC_RTC_BASE 0x40046000
tushki7	0:60d829a0353a	955	#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
tushki7	0:60d829a0353a	956
tushki7	0:60d829a0353a	957	typedef enum RTC_TIMEINDEX {
tushki7	0:60d829a0353a	958	RTC_TIMETYPE_SECOND, /* Second */
tushki7	0:60d829a0353a	959	RTC_TIMETYPE_MINUTE, /* Month */
tushki7	0:60d829a0353a	960	RTC_TIMETYPE_HOUR, /* Hour */
tushki7	0:60d829a0353a	961	RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
tushki7	0:60d829a0353a	962	RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
tushki7	0:60d829a0353a	963	RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
tushki7	0:60d829a0353a	964	RTC_TIMETYPE_MONTH, /* Month */
tushki7	0:60d829a0353a	965	RTC_TIMETYPE_YEAR, /* Year */
tushki7	0:60d829a0353a	966	RTC_TIMETYPE_LAST
tushki7	0:60d829a0353a	967	} RTC_TIMEINDEX_T;
tushki7	0:60d829a0353a	968
tushki7	0:60d829a0353a	969	#if RTC_EV_SUPPORT
tushki7	0:60d829a0353a	970	typedef enum LPC_RTC_EV_CHANNEL {
tushki7	0:60d829a0353a	971	RTC_EV_CHANNEL_1 = 0,
tushki7	0:60d829a0353a	972	RTC_EV_CHANNEL_2,
tushki7	0:60d829a0353a	973	RTC_EV_CHANNEL_3,
tushki7	0:60d829a0353a	974	RTC_EV_CHANNEL_NUM,
tushki7	0:60d829a0353a	975	} LPC_RTC_EV_CHANNEL_T;
tushki7	0:60d829a0353a	976	#endif /RTC_EV_SUPPORT/
tushki7	0:60d829a0353a	977
tushki7	0:60d829a0353a	978	typedef struct { /* RTC Structure */
tushki7	0:60d829a0353a	979	__IO uint32_t ILR; /* Interrupt Location Register */
tushki7	0:60d829a0353a	980	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	981	__IO uint32_t CCR; /* Clock Control Register */
tushki7	0:60d829a0353a	982	__IO uint32_t CIIR; /* Counter Increment Interrupt Register */
tushki7	0:60d829a0353a	983	__IO uint32_t AMR; /* Alarm Mask Register */
tushki7	0:60d829a0353a	984	__I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
tushki7	0:60d829a0353a	985	__IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
tushki7	0:60d829a0353a	986	__IO uint32_t CALIBRATION; /* Calibration Value Register */
tushki7	0:60d829a0353a	987	__I uint32_t RESERVED1[7];
tushki7	0:60d829a0353a	988	__IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
tushki7	0:60d829a0353a	989	#if RTC_EV_SUPPORT
tushki7	0:60d829a0353a	990	__IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
tushki7	0:60d829a0353a	991	__IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
tushki7	0:60d829a0353a	992	__I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
tushki7	0:60d829a0353a	993	__I uint32_t RESERVED2;
tushki7	0:60d829a0353a	994	__I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
tushki7	0:60d829a0353a	995	__I uint32_t RESERVED3;
tushki7	0:60d829a0353a	996	__I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
tushki7	0:60d829a0353a	997	#endif /RTC_EV_SUPPORT/
tushki7	0:60d829a0353a	998	} LPC_RTC_T;
tushki7	0:60d829a0353a	999
tushki7	0:60d829a0353a	1000	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1001	* LPC18XX/43XX CGU register block structure
tushki7	0:60d829a0353a	1002	*/
tushki7	0:60d829a0353a	1003	#define LPC_CGU_BASE 0x40050000
tushki7	0:60d829a0353a	1004	#define LPC_CCU1_BASE 0x40051000
tushki7	0:60d829a0353a	1005	#define LPC_CCU2_BASE 0x40052000
tushki7	0:60d829a0353a	1006	/*
tushki7	0:60d829a0353a	1007	* Input clocks for the CGU and can come from both external (crystal) and
tushki7	0:60d829a0353a	1008	* internal (PLL) sources. Can be routed to the base clocks.
tushki7	0:60d829a0353a	1009	*/
tushki7	0:60d829a0353a	1010	typedef enum CGU_CLKIN {
tushki7	0:60d829a0353a	1011	CLKIN_32K, /* External 32KHz input */
tushki7	0:60d829a0353a	1012	CLKIN_IRC, /* Internal IRC (12MHz) input */
tushki7	0:60d829a0353a	1013	CLKIN_ENET_RX, /* External ENET_RX pin input */
tushki7	0:60d829a0353a	1014	CLKIN_ENET_TX, /* External ENET_TX pin input */
tushki7	0:60d829a0353a	1015	CLKIN_CLKIN, /* External GPCLKIN pin input */
tushki7	0:60d829a0353a	1016	CLKIN_RESERVED1,
tushki7	0:60d829a0353a	1017	CLKIN_CRYSTAL, /* External (main) crystal pin input */
tushki7	0:60d829a0353a	1018	CLKIN_USBPLL, /* Internal USB PLL input */
tushki7	0:60d829a0353a	1019	CLKIN_AUDIOPLL, /* Internal Audio PLL input */
tushki7	0:60d829a0353a	1020	CLKIN_MAINPLL, /* Internal Main PLL input */
tushki7	0:60d829a0353a	1021	CLKIN_RESERVED2,
tushki7	0:60d829a0353a	1022	CLKIN_RESERVED3,
tushki7	0:60d829a0353a	1023	CLKIN_IDIVA, /* Internal divider A input */
tushki7	0:60d829a0353a	1024	CLKIN_IDIVB, /* Internal divider B input */
tushki7	0:60d829a0353a	1025	CLKIN_IDIVC, /* Internal divider C input */
tushki7	0:60d829a0353a	1026	CLKIN_IDIVD, /* Internal divider D input */
tushki7	0:60d829a0353a	1027	CLKIN_IDIVE, /* Internal divider E input */
tushki7	0:60d829a0353a	1028	CLKINPUT_PD /* External 32KHz input */
tushki7	0:60d829a0353a	1029	} CGU_CLKIN_T;
tushki7	0:60d829a0353a	1030
tushki7	0:60d829a0353a	1031	#define CLKIN_PLL0USB CLKIN_USBPLL
tushki7	0:60d829a0353a	1032	#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
tushki7	0:60d829a0353a	1033	#define CLKIN_PLL1 CLKIN_MAINPLL
tushki7	0:60d829a0353a	1034
tushki7	0:60d829a0353a	1035	/*
tushki7	0:60d829a0353a	1036	* CGU base clocks are clocks that are associated with a single input clock
tushki7	0:60d829a0353a	1037	* and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
tushki7	0:60d829a0353a	1038	* clock can be configured to use the CLKIN_MAINPLL input clock, which will in
tushki7	0:60d829a0353a	1039	* turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
tushki7	0:60d829a0353a	1040	* CLK_PERIPH_SGPIO periphral clocks.
tushki7	0:60d829a0353a	1041	*/
tushki7	0:60d829a0353a	1042	typedef enum CGU_BASE_CLK {
tushki7	0:60d829a0353a	1043	CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
tushki7	0:60d829a0353a	1044	CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
tushki7	0:60d829a0353a	1045	#if defined(CHIP_LPC43XX)
tushki7	0:60d829a0353a	1046	CLK_BASE_PERIPH, /* Base clock for SGPIO */
tushki7	0:60d829a0353a	1047	#else
tushki7	0:60d829a0353a	1048	CLK_BASE_RESERVED1,
tushki7	0:60d829a0353a	1049	#endif
tushki7	0:60d829a0353a	1050	CLK_BASE_USB1, /* Base USB clock for USB1 */
tushki7	0:60d829a0353a	1051	CLK_BASE_MX, /* Base clock for CPU core */
tushki7	0:60d829a0353a	1052	CLK_BASE_SPIFI, /* Base clock for SPIFI */
tushki7	0:60d829a0353a	1053	#if defined(CHIP_LPC43XX)
tushki7	0:60d829a0353a	1054	CLK_BASE_SPI, /* Base clock for SPI */
tushki7	0:60d829a0353a	1055	#else
tushki7	0:60d829a0353a	1056	CLK_BASE_RESERVED2,
tushki7	0:60d829a0353a	1057	#endif
tushki7	0:60d829a0353a	1058	CLK_BASE_PHY_RX, /* Base clock for PHY RX */
tushki7	0:60d829a0353a	1059	CLK_BASE_PHY_TX, /* Base clock for PHY TX */
tushki7	0:60d829a0353a	1060	CLK_BASE_APB1, /* Base clock for APB1 group */
tushki7	0:60d829a0353a	1061	CLK_BASE_APB3, /* Base clock for APB3 group */
tushki7	0:60d829a0353a	1062	CLK_BASE_LCD, /* Base clock for LCD pixel clock */
tushki7	0:60d829a0353a	1063	#if defined(CHIP_LPC43XX)
tushki7	0:60d829a0353a	1064	CLK_BASE_VADC, /* Base clock for VADC */
tushki7	0:60d829a0353a	1065	#else
tushki7	0:60d829a0353a	1066	CLK_BASE_RESERVED3,
tushki7	0:60d829a0353a	1067	#endif
tushki7	0:60d829a0353a	1068	CLK_BASE_SDIO, /* Base clock for SDIO */
tushki7	0:60d829a0353a	1069	CLK_BASE_SSP0, /* Base clock for SSP0 */
tushki7	0:60d829a0353a	1070	CLK_BASE_SSP1, /* Base clock for SSP1 */
tushki7	0:60d829a0353a	1071	CLK_BASE_UART0, /* Base clock for UART0 */
tushki7	0:60d829a0353a	1072	CLK_BASE_UART1, /* Base clock for UART1 */
tushki7	0:60d829a0353a	1073	CLK_BASE_UART2, /* Base clock for UART2 */
tushki7	0:60d829a0353a	1074	CLK_BASE_UART3, /* Base clock for UART3 */
tushki7	0:60d829a0353a	1075	CLK_BASE_OUT, /* Base clock for CLKOUT pin */
tushki7	0:60d829a0353a	1076	CLK_BASE_RESERVED4,
tushki7	0:60d829a0353a	1077	CLK_BASE_RESERVED5,
tushki7	0:60d829a0353a	1078	CLK_BASE_RESERVED6,
tushki7	0:60d829a0353a	1079	CLK_BASE_RESERVED7,
tushki7	0:60d829a0353a	1080	CLK_BASE_APLL, /* Base clock for audio PLL */
tushki7	0:60d829a0353a	1081	CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
tushki7	0:60d829a0353a	1082	CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
tushki7	0:60d829a0353a	1083	CLK_BASE_LAST,
tushki7	0:60d829a0353a	1084	CLK_BASE_NONE = CLK_BASE_LAST
tushki7	0:60d829a0353a	1085	} CGU_BASE_CLK_T;
tushki7	0:60d829a0353a	1086
tushki7	0:60d829a0353a	1087	/*
tushki7	0:60d829a0353a	1088	* CGU dividers provide an extra clock state where a specific clock can be
tushki7	0:60d829a0353a	1089	* divided before being routed to a peripheral group. A divider accepts an
tushki7	0:60d829a0353a	1090	* input clock and then divides it. To use the divided clock for a base clock
tushki7	0:60d829a0353a	1091	* group, use the divider as the input clock for the base clock (for example,
tushki7	0:60d829a0353a	1092	* use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
tushki7	0:60d829a0353a	1093	*/
tushki7	0:60d829a0353a	1094	typedef enum CGU_IDIV {
tushki7	0:60d829a0353a	1095	CLK_IDIV_A, /* CGU clock divider A */
tushki7	0:60d829a0353a	1096	CLK_IDIV_B, /* CGU clock divider B */
tushki7	0:60d829a0353a	1097	CLK_IDIV_C, /* CGU clock divider A */
tushki7	0:60d829a0353a	1098	CLK_IDIV_D, /* CGU clock divider D */
tushki7	0:60d829a0353a	1099	CLK_IDIV_E, /* CGU clock divider E */
tushki7	0:60d829a0353a	1100	CLK_IDIV_LAST
tushki7	0:60d829a0353a	1101	} CGU_IDIV_T;
tushki7	0:60d829a0353a	1102
tushki7	0:60d829a0353a	1103	/*
tushki7	0:60d829a0353a	1104	* Peripheral clocks are individual clocks routed to peripherals. Although
tushki7	0:60d829a0353a	1105	* multiple peripherals may share a same base clock, each peripheral's clock
tushki7	0:60d829a0353a	1106	* can be enabled or disabled individually. Some peripheral clocks also have
tushki7	0:60d829a0353a	1107	* additional dividers associated with them.
tushki7	0:60d829a0353a	1108	*/
tushki7	0:60d829a0353a	1109	typedef enum CCU_CLK {
tushki7	0:60d829a0353a	1110	/* CCU1 clocks */
tushki7	0:60d829a0353a	1111	CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
tushki7	0:60d829a0353a	1112	CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
tushki7	0:60d829a0353a	1113	CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
tushki7	0:60d829a0353a	1114	CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
tushki7	0:60d829a0353a	1115	CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
tushki7	0:60d829a0353a	1116	CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
tushki7	0:60d829a0353a	1117	CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
tushki7	0:60d829a0353a	1118	CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
tushki7	0:60d829a0353a	1119	CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
tushki7	0:60d829a0353a	1120	CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
tushki7	0:60d829a0353a	1121	CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
tushki7	0:60d829a0353a	1122	CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
tushki7	0:60d829a0353a	1123	CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1124	CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1125	CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1126	CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1127	CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1128	CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1129	CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1130	CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1131	CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1132	CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1133	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
tushki7	0:60d829a0353a	1134	CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1135	CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1136	CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1137	CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1138	CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1139	#if defined(CHIP_LPC43XX)
tushki7	0:60d829a0353a	1140	CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1141	CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1142	#else
tushki7	0:60d829a0353a	1143	CLK_RESERVED1,
tushki7	0:60d829a0353a	1144	CLK_RESERVED2,
tushki7	0:60d829a0353a	1145	#endif
tushki7	0:60d829a0353a	1146	CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1147	CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1148	CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1149	CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1150	CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1151	CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1152	CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1153	CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1154	CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1155	CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1156	CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1157	CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1158	CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1159	CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1160	CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1161	CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
tushki7	0:60d829a0353a	1162	#if defined(CHIP_LPC43XX)
tushki7	0:60d829a0353a	1163	CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
tushki7	0:60d829a0353a	1164	CLK_RESERVED3,
tushki7	0:60d829a0353a	1165	CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
tushki7	0:60d829a0353a	1166	CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
tushki7	0:60d829a0353a	1167	#else
tushki7	0:60d829a0353a	1168	CLK_RESERVED3 = 192,
tushki7	0:60d829a0353a	1169	CLK_RESERVED3A,
tushki7	0:60d829a0353a	1170	CLK_RESERVED4,
tushki7	0:60d829a0353a	1171	CLK_RESERVED5,
tushki7	0:60d829a0353a	1172	#endif
tushki7	0:60d829a0353a	1173	CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
tushki7	0:60d829a0353a	1174	CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
tushki7	0:60d829a0353a	1175	#if defined(CHIP_LPC43XX)
tushki7	0:60d829a0353a	1176	CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
tushki7	0:60d829a0353a	1177	CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
tushki7	0:60d829a0353a	1178	#else
tushki7	0:60d829a0353a	1179	CLK_RESERVED7 = 320,
tushki7	0:60d829a0353a	1180	CLK_RESERVED8,
tushki7	0:60d829a0353a	1181	#endif
tushki7	0:60d829a0353a	1182	CLK_CCU1_LAST,
tushki7	0:60d829a0353a	1183
tushki7	0:60d829a0353a	1184	/* CCU2 clocks */
tushki7	0:60d829a0353a	1185	CLK_CCU2_START,
tushki7	0:60d829a0353a	1186	CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
tushki7	0:60d829a0353a	1187	RESERVED_ALIGNB = CLK_CCU2_START + 31,
tushki7	0:60d829a0353a	1188	CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
tushki7	0:60d829a0353a	1189	RESERVED_ALIGNC = CLK_CCU2_START + 63,
tushki7	0:60d829a0353a	1190	CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
tushki7	0:60d829a0353a	1191	RESERVED_ALIGND = CLK_CCU2_START + 95,
tushki7	0:60d829a0353a	1192	CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
tushki7	0:60d829a0353a	1193	RESERVED_ALIGNE = CLK_CCU2_START + 127,
tushki7	0:60d829a0353a	1194	CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
tushki7	0:60d829a0353a	1195	RESERVED_ALIGNF = CLK_CCU2_START + 159,
tushki7	0:60d829a0353a	1196	CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
tushki7	0:60d829a0353a	1197	RESERVED_ALIGNG = CLK_CCU2_START + 191,
tushki7	0:60d829a0353a	1198	CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
tushki7	0:60d829a0353a	1199	RESERVED_ALIGNH = CLK_CCU2_START + 223,
tushki7	0:60d829a0353a	1200	CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
tushki7	0:60d829a0353a	1201	CLK_CCU2_LAST
tushki7	0:60d829a0353a	1202	} CCU_CLK_T;
tushki7	0:60d829a0353a	1203
tushki7	0:60d829a0353a	1204	/*
tushki7	0:60d829a0353a	1205	* Audio or USB PLL selection
tushki7	0:60d829a0353a	1206	*/
tushki7	0:60d829a0353a	1207	typedef enum CGU_USB_AUDIO_PLL {
tushki7	0:60d829a0353a	1208	CGU_USB_PLL,
tushki7	0:60d829a0353a	1209	CGU_AUDIO_PLL
tushki7	0:60d829a0353a	1210	} CGU_USB_AUDIO_PLL_T;
tushki7	0:60d829a0353a	1211
tushki7	0:60d829a0353a	1212	/*
tushki7	0:60d829a0353a	1213	* PLL register block
tushki7	0:60d829a0353a	1214	*/
tushki7	0:60d829a0353a	1215	typedef struct {
tushki7	0:60d829a0353a	1216	__I uint32_t PLL_STAT; /* PLL status register */
tushki7	0:60d829a0353a	1217	__IO uint32_t PLL_CTRL; /* PLL control register */
tushki7	0:60d829a0353a	1218	__IO uint32_t PLL_MDIV; /* PLL M-divider register */
tushki7	0:60d829a0353a	1219	__IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
tushki7	0:60d829a0353a	1220	} CGU_PLL_REG_T;
tushki7	0:60d829a0353a	1221
tushki7	0:60d829a0353a	1222	typedef struct { /* (@ 0x40050000) CGU Structure */
tushki7	0:60d829a0353a	1223	__I uint32_t RESERVED0[5];
tushki7	0:60d829a0353a	1224	__IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
tushki7	0:60d829a0353a	1225	__IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
tushki7	0:60d829a0353a	1226	CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
tushki7	0:60d829a0353a	1227	__IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
tushki7	0:60d829a0353a	1228	__I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
tushki7	0:60d829a0353a	1229	__IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
tushki7	0:60d829a0353a	1230	__IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
tushki7	0:60d829a0353a	1231	__IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
tushki7	0:60d829a0353a	1232	} LPC_CGU_T;
tushki7	0:60d829a0353a	1233
tushki7	0:60d829a0353a	1234	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1235	* CCU clock config/status register pair
tushki7	0:60d829a0353a	1236	*/
tushki7	0:60d829a0353a	1237	typedef struct {
tushki7	0:60d829a0353a	1238	__IO uint32_t CFG; /* CCU clock configuration register */
tushki7	0:60d829a0353a	1239	__I uint32_t STAT; /* CCU clock status register */
tushki7	0:60d829a0353a	1240	} CCU_CFGSTAT_T;
tushki7	0:60d829a0353a	1241
tushki7	0:60d829a0353a	1242	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1243	* CCU1 register block structure
tushki7	0:60d829a0353a	1244	*/
tushki7	0:60d829a0353a	1245	typedef struct { /* (@ 0x40051000) CCU1 Structure */
tushki7	0:60d829a0353a	1246	__IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
tushki7	0:60d829a0353a	1247	__I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
tushki7	0:60d829a0353a	1248	__I uint32_t RESERVED0[62];
tushki7	0:60d829a0353a	1249	CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
tushki7	0:60d829a0353a	1250	} LPC_CCU1_T;
tushki7	0:60d829a0353a	1251
tushki7	0:60d829a0353a	1252	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1253	* CCU2 register block structure
tushki7	0:60d829a0353a	1254	*/
tushki7	0:60d829a0353a	1255	typedef struct { /* (@ 0x40052000) CCU2 Structure */
tushki7	0:60d829a0353a	1256	__IO uint32_t PM; /* (@ 0x40052000) Power mode register */
tushki7	0:60d829a0353a	1257	__I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
tushki7	0:60d829a0353a	1258	__I uint32_t RESERVED0[62];
tushki7	0:60d829a0353a	1259	CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
tushki7	0:60d829a0353a	1260	} LPC_CCU2_T;
tushki7	0:60d829a0353a	1261
tushki7	0:60d829a0353a	1262	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1263	* RGU register structure
tushki7	0:60d829a0353a	1264	*/
tushki7	0:60d829a0353a	1265	#define LPC_RGU_BASE 0x40053000
tushki7	0:60d829a0353a	1266
tushki7	0:60d829a0353a	1267	typedef enum RGU_RST {
tushki7	0:60d829a0353a	1268	RGU_CORE_RST,
tushki7	0:60d829a0353a	1269	RGU_PERIPH_RST,
tushki7	0:60d829a0353a	1270	RGU_MASTER_RST,
tushki7	0:60d829a0353a	1271	RGU_WWDT_RST = 4,
tushki7	0:60d829a0353a	1272	RGU_CREG_RST,
tushki7	0:60d829a0353a	1273	RGU_BUS_RST = 8,
tushki7	0:60d829a0353a	1274	RGU_SCU_RST,
tushki7	0:60d829a0353a	1275	RGU_M3_RST = 13,
tushki7	0:60d829a0353a	1276	RGU_LCD_RST = 16,
tushki7	0:60d829a0353a	1277	RGU_USB0_RST,
tushki7	0:60d829a0353a	1278	RGU_USB1_RST,
tushki7	0:60d829a0353a	1279	RGU_DMA_RST,
tushki7	0:60d829a0353a	1280	RGU_SDIO_RST,
tushki7	0:60d829a0353a	1281	RGU_EMC_RST,
tushki7	0:60d829a0353a	1282	RGU_ETHERNET_RST,
tushki7	0:60d829a0353a	1283	RGU_FLASHA_RST = 25,
tushki7	0:60d829a0353a	1284	RGU_EEPROM_RST = 27,
tushki7	0:60d829a0353a	1285	RGU_GPIO_RST,
tushki7	0:60d829a0353a	1286	RGU_FLASHB_RST,
tushki7	0:60d829a0353a	1287	RGU_TIMER0_RST = 32,
tushki7	0:60d829a0353a	1288	RGU_TIMER1_RST,
tushki7	0:60d829a0353a	1289	RGU_TIMER2_RST,
tushki7	0:60d829a0353a	1290	RGU_TIMER3_RST,
tushki7	0:60d829a0353a	1291	RGU_RITIMER_RST,
tushki7	0:60d829a0353a	1292	RGU_SCT_RST,
tushki7	0:60d829a0353a	1293	RGU_MOTOCONPWM_RST,
tushki7	0:60d829a0353a	1294	RGU_QEI_RST,
tushki7	0:60d829a0353a	1295	RGU_ADC0_RST,
tushki7	0:60d829a0353a	1296	RGU_ADC1_RST,
tushki7	0:60d829a0353a	1297	RGU_DAC_RST,
tushki7	0:60d829a0353a	1298	RGU_UART0_RST = 44,
tushki7	0:60d829a0353a	1299	RGU_UART1_RST,
tushki7	0:60d829a0353a	1300	RGU_UART2_RST,
tushki7	0:60d829a0353a	1301	RGU_UART3_RST,
tushki7	0:60d829a0353a	1302	RGU_I2C0_RST,
tushki7	0:60d829a0353a	1303	RGU_I2C1_RST,
tushki7	0:60d829a0353a	1304	RGU_SSP0_RST,
tushki7	0:60d829a0353a	1305	RGU_SSP1_RST,
tushki7	0:60d829a0353a	1306	RGU_I2S_RST,
tushki7	0:60d829a0353a	1307	RGU_SPIFI_RST,
tushki7	0:60d829a0353a	1308	RGU_CAN1_RST,
tushki7	0:60d829a0353a	1309	RGU_CAN0_RST,
tushki7	0:60d829a0353a	1310	#ifdef CHIP_LPC43XX
tushki7	0:60d829a0353a	1311	RGU_M0APP_RST,
tushki7	0:60d829a0353a	1312	RGU_SGPIO_RST,
tushki7	0:60d829a0353a	1313	RGU_SPI_RST,
tushki7	0:60d829a0353a	1314	#endif
tushki7	0:60d829a0353a	1315	RGU_LAST_RST = 63,
tushki7	0:60d829a0353a	1316	} RGU_RST_T;
tushki7	0:60d829a0353a	1317
tushki7	0:60d829a0353a	1318	typedef struct { /* RGU Structure */
tushki7	0:60d829a0353a	1319	__I uint32_t RESERVED0[64];
tushki7	0:60d829a0353a	1320	__O uint32_t RESET_CTRL0; /* Reset control register 0 */
tushki7	0:60d829a0353a	1321	__O uint32_t RESET_CTRL1; /* Reset control register 1 */
tushki7	0:60d829a0353a	1322	__I uint32_t RESERVED1[2];
tushki7	0:60d829a0353a	1323	__IO uint32_t RESET_STATUS0; /* Reset status register 0 */
tushki7	0:60d829a0353a	1324	__IO uint32_t RESET_STATUS1; /* Reset status register 1 */
tushki7	0:60d829a0353a	1325	__IO uint32_t RESET_STATUS2; /* Reset status register 2 */
tushki7	0:60d829a0353a	1326	__IO uint32_t RESET_STATUS3; /* Reset status register 3 */
tushki7	0:60d829a0353a	1327	__I uint32_t RESERVED2[12];
tushki7	0:60d829a0353a	1328	__I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
tushki7	0:60d829a0353a	1329	__I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
tushki7	0:60d829a0353a	1330	__I uint32_t RESERVED3[170];
tushki7	0:60d829a0353a	1331	__IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
tushki7	0:60d829a0353a	1332	} LPC_RGU_T;
tushki7	0:60d829a0353a	1333
tushki7	0:60d829a0353a	1334	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1335	* Windowed Watchdog register block structure
tushki7	0:60d829a0353a	1336	*/
tushki7	0:60d829a0353a	1337	#define LPC_WWDT_BASE 0x40080000
tushki7	0:60d829a0353a	1338
tushki7	0:60d829a0353a	1339	typedef struct { /* WWDT Structure */
tushki7	0:60d829a0353a	1340	__IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
tushki7	0:60d829a0353a	1341	__IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
tushki7	0:60d829a0353a	1342	__O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
tushki7	0:60d829a0353a	1343	__I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
tushki7	0:60d829a0353a	1344	#ifdef WATCHDOG_CLKSEL_SUPPORT
tushki7	0:60d829a0353a	1345	__IO uint32_t CLKSEL; /* Watchdog clock select register. */
tushki7	0:60d829a0353a	1346	#else
tushki7	0:60d829a0353a	1347	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	1348	#endif
tushki7	0:60d829a0353a	1349	#ifdef WATCHDOG_WINDOW_SUPPORT
tushki7	0:60d829a0353a	1350	__IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
tushki7	0:60d829a0353a	1351	__IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
tushki7	0:60d829a0353a	1352	#endif
tushki7	0:60d829a0353a	1353	} LPC_WWDT_T;
tushki7	0:60d829a0353a	1354
tushki7	0:60d829a0353a	1355	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1356	* USART register block structure
tushki7	0:60d829a0353a	1357	*/
tushki7	0:60d829a0353a	1358	#define LPC_USART0_BASE 0x40081000
tushki7	0:60d829a0353a	1359	#define LPC_UART1_BASE 0x40082000
tushki7	0:60d829a0353a	1360	#define LPC_USART2_BASE 0x400C1000
tushki7	0:60d829a0353a	1361	#define LPC_USART3_BASE 0x400C2000
tushki7	0:60d829a0353a	1362
tushki7	0:60d829a0353a	1363	typedef struct { /* USARTn Structure */
tushki7	0:60d829a0353a	1364
tushki7	0:60d829a0353a	1365	union {
tushki7	0:60d829a0353a	1366	__IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
tushki7	0:60d829a0353a	1367	__O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
tushki7	0:60d829a0353a	1368	__I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
tushki7	0:60d829a0353a	1369	};
tushki7	0:60d829a0353a	1370
tushki7	0:60d829a0353a	1371	union {
tushki7	0:60d829a0353a	1372	__IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
tushki7	0:60d829a0353a	1373	__IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
tushki7	0:60d829a0353a	1374	};
tushki7	0:60d829a0353a	1375
tushki7	0:60d829a0353a	1376	union {
tushki7	0:60d829a0353a	1377	__O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
tushki7	0:60d829a0353a	1378	__I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
tushki7	0:60d829a0353a	1379	};
tushki7	0:60d829a0353a	1380
tushki7	0:60d829a0353a	1381	__IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
tushki7	0:60d829a0353a	1382	__IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
tushki7	0:60d829a0353a	1383	__I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
tushki7	0:60d829a0353a	1384	__I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
tushki7	0:60d829a0353a	1385	__IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
tushki7	0:60d829a0353a	1386	__IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
tushki7	0:60d829a0353a	1387	__IO uint32_t ICR; /* IrDA control register (not all UARTS) */
tushki7	0:60d829a0353a	1388	__IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
tushki7	0:60d829a0353a	1389	__IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
tushki7	0:60d829a0353a	1390	__IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
tushki7	0:60d829a0353a	1391	uint32_t RESERVED0[3];
tushki7	0:60d829a0353a	1392	__IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
tushki7	0:60d829a0353a	1393	__I uint32_t RESERVED1[1];
tushki7	0:60d829a0353a	1394	__IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
tushki7	0:60d829a0353a	1395	__IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
tushki7	0:60d829a0353a	1396	__IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
tushki7	0:60d829a0353a	1397	__IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
tushki7	0:60d829a0353a	1398	union {
tushki7	0:60d829a0353a	1399	__IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
tushki7	0:60d829a0353a	1400	__I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
tushki7	0:60d829a0353a	1401	};
tushki7	0:60d829a0353a	1402
tushki7	0:60d829a0353a	1403	__IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
tushki7	0:60d829a0353a	1404	} LPC_USART_T;
tushki7	0:60d829a0353a	1405
tushki7	0:60d829a0353a	1406	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1407	* SSP register block structure
tushki7	0:60d829a0353a	1408	*/
tushki7	0:60d829a0353a	1409	#define LPC_SSP0_BASE 0x40083000
tushki7	0:60d829a0353a	1410	#define LPC_SSP1_BASE 0x400C5000
tushki7	0:60d829a0353a	1411
tushki7	0:60d829a0353a	1412	typedef struct { /* SSPn Structure */
tushki7	0:60d829a0353a	1413	__IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
tushki7	0:60d829a0353a	1414	__IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
tushki7	0:60d829a0353a	1415	__IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
tushki7	0:60d829a0353a	1416	__I uint32_t SR; /* Status Register */
tushki7	0:60d829a0353a	1417	__IO uint32_t CPSR; /* Clock Prescale Register */
tushki7	0:60d829a0353a	1418	__IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
tushki7	0:60d829a0353a	1419	__I uint32_t RIS; /* Raw Interrupt Status Register */
tushki7	0:60d829a0353a	1420	__I uint32_t MIS; /* Masked Interrupt Status Register */
tushki7	0:60d829a0353a	1421	__O uint32_t ICR; /* SSPICR Interrupt Clear Register */
tushki7	0:60d829a0353a	1422	__IO uint32_t DMACR; /* SSPn DMA control register */
tushki7	0:60d829a0353a	1423	} LPC_SSP_T;
tushki7	0:60d829a0353a	1424
tushki7	0:60d829a0353a	1425	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1426	* 32-bit Standard timer register block structure
tushki7	0:60d829a0353a	1427	*/
tushki7	0:60d829a0353a	1428	#define LPC_TIMER0_BASE 0x40084000
tushki7	0:60d829a0353a	1429	#define LPC_TIMER1_BASE 0x40085000
tushki7	0:60d829a0353a	1430	#define LPC_TIMER2_BASE 0x400C3000
tushki7	0:60d829a0353a	1431	#define LPC_TIMER3_BASE 0x400C4000
tushki7	0:60d829a0353a	1432
tushki7	0:60d829a0353a	1433	typedef struct { /* TIMERn Structure */
tushki7	0:60d829a0353a	1434	__IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
tushki7	0:60d829a0353a	1435	__IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
tushki7	0:60d829a0353a	1436	__IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
tushki7	0:60d829a0353a	1437	__IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
tushki7	0:60d829a0353a	1438	__IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
tushki7	0:60d829a0353a	1439	__IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
tushki7	0:60d829a0353a	1440	__IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
tushki7	0:60d829a0353a	1441	__IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
tushki7	0:60d829a0353a	1442	__IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
tushki7	0:60d829a0353a	1443	__IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
tushki7	0:60d829a0353a	1444	__I uint32_t RESERVED0[12];
tushki7	0:60d829a0353a	1445	__IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
tushki7	0:60d829a0353a	1446	} LPC_TIMER_T;
tushki7	0:60d829a0353a	1447
tushki7	0:60d829a0353a	1448	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1449	* System Control Unit register block
tushki7	0:60d829a0353a	1450	*/
tushki7	0:60d829a0353a	1451	#define LPC_SCU_BASE 0x40086000
tushki7	0:60d829a0353a	1452
tushki7	0:60d829a0353a	1453	typedef struct {
tushki7	0:60d829a0353a	1454	__IO uint32_t SFSP[16][32];
tushki7	0:60d829a0353a	1455	__I uint32_t RESERVED0[256];
tushki7	0:60d829a0353a	1456	__IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
tushki7	0:60d829a0353a	1457	__I uint32_t RESERVED16[28];
tushki7	0:60d829a0353a	1458	__IO uint32_t SFSUSB; /* Pin configuration register for USB */
tushki7	0:60d829a0353a	1459	__IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
tushki7	0:60d829a0353a	1460	__IO uint32_t ENAIO[3]; /* Analog function select registers */
tushki7	0:60d829a0353a	1461	__I uint32_t RESERVED17[27];
tushki7	0:60d829a0353a	1462	__IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
tushki7	0:60d829a0353a	1463	__I uint32_t RESERVED18[63];
tushki7	0:60d829a0353a	1464	__IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
tushki7	0:60d829a0353a	1465	__IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
tushki7	0:60d829a0353a	1466	} LPC_SCU_T;
tushki7	0:60d829a0353a	1467
tushki7	0:60d829a0353a	1468	/*
tushki7	0:60d829a0353a	1469	* SCU function and mode selection definitions
tushki7	0:60d829a0353a	1470	* See the User Manual for specific modes and functions supoprted by the
tushki7	0:60d829a0353a	1471	* various LPC18xx/43xx devices. Functionality can vary per device.
tushki7	0:60d829a0353a	1472	*/
tushki7	0:60d829a0353a	1473	#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
tushki7	0:60d829a0353a	1474	#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
tushki7	0:60d829a0353a	1475	#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
tushki7	0:60d829a0353a	1476	#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
tushki7	0:60d829a0353a	1477	#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
tushki7	0:60d829a0353a	1478	#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
tushki7	0:60d829a0353a	1479	#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
tushki7	0:60d829a0353a	1480	#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
tushki7	0:60d829a0353a	1481	#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
tushki7	0:60d829a0353a	1482	#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
tushki7	0:60d829a0353a	1483	#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
tushki7	0:60d829a0353a	1484
tushki7	0:60d829a0353a	1485	#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
tushki7	0:60d829a0353a	1486	#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
tushki7	0:60d829a0353a	1487	#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
tushki7	0:60d829a0353a	1488	#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
tushki7	0:60d829a0353a	1489	#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
tushki7	0:60d829a0353a	1490	#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
tushki7	0:60d829a0353a	1491	#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
tushki7	0:60d829a0353a	1492	#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
tushki7	0:60d829a0353a	1493
tushki7	0:60d829a0353a	1494	/* Common SCU configurations */
tushki7	0:60d829a0353a	1495	#define SCU_PINIO_FAST (SCU_MODE_INACT \| SCU_MODE_HIGHSPEEDSLEW_EN \| SCU_MODE_INBUFF_EN \| SCU_MODE_ZIF_DIS)
tushki7	0:60d829a0353a	1496	#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
tushki7	0:60d829a0353a	1497	#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN \| SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
tushki7	0:60d829a0353a	1498	#define SCU_PINIO_PULLNONE (SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
tushki7	0:60d829a0353a	1499
tushki7	0:60d829a0353a	1500	/* Calculate SCU offset and register address from group and pin number */
tushki7	0:60d829a0353a	1501	#define SCU_OFF(group, num) ((group << 7) + (num << 2))
tushki7	0:60d829a0353a	1502	#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
tushki7	0:60d829a0353a	1503
tushki7	0:60d829a0353a	1504	/**
tushki7	0:60d829a0353a	1505	* SCU function and mode selection definitions (old)
tushki7	0:60d829a0353a	1506	* For backwards compatibility.
tushki7	0:60d829a0353a	1507	*/
tushki7	0:60d829a0353a	1508	#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
tushki7	0:60d829a0353a	1509	#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
tushki7	0:60d829a0353a	1510	#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
tushki7	0:60d829a0353a	1511	#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
tushki7	0:60d829a0353a	1512	#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
tushki7	0:60d829a0353a	1513	#define MD_EZI (0x1 << 6) /* Input buffer enable */
tushki7	0:60d829a0353a	1514	#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
tushki7	0:60d829a0353a	1515	#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
tushki7	0:60d829a0353a	1516	#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
tushki7	0:60d829a0353a	1517	#define MD_PLN_FAST (MD_PLN \| MD_EZI \| MD_ZI \| MD_EHS)
tushki7	0:60d829a0353a	1518	#define I2C0_STANDARD_FAST_MODE (1 << 3 \| 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
tushki7	0:60d829a0353a	1519	#define I2C0_FAST_MODE_PLUS (2 << 1 \| 1 << 3 \| 1 << 7 \| 1 << 10 \| 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
tushki7	0:60d829a0353a	1520
tushki7	0:60d829a0353a	1521	#define FUNC0 0x0 /* Pin function 0 */
tushki7	0:60d829a0353a	1522	#define FUNC1 0x1 /* Pin function 1 */
tushki7	0:60d829a0353a	1523	#define FUNC2 0x2 /* Pin function 2 */
tushki7	0:60d829a0353a	1524	#define FUNC3 0x3 /* Pin function 3 */
tushki7	0:60d829a0353a	1525	#define FUNC4 0x4 /* Pin function 4 */
tushki7	0:60d829a0353a	1526	#define FUNC5 0x5 /* Pin function 5 */
tushki7	0:60d829a0353a	1527	#define FUNC6 0x6 /* Pin function 6 */
tushki7	0:60d829a0353a	1528	#define FUNC7 0x7 /* Pin function 7 */
tushki7	0:60d829a0353a	1529
tushki7	0:60d829a0353a	1530	#define PORT_OFFSET 0x80 /* Port offset definition */
tushki7	0:60d829a0353a	1531	#define PIN_OFFSET 0x04 /* Pin offset definition */
tushki7	0:60d829a0353a	1532
tushki7	0:60d829a0353a	1533	/* Returns the SFSP register address in the SCU for a pin and port,
tushki7	0:60d829a0353a	1534	recommend using ((volatile int ) &LPC_SCU->SFSP[po][pi];) */
tushki7	0:60d829a0353a	1535	#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
tushki7	0:60d829a0353a	1536	((volatile int ) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
tushki7	0:60d829a0353a	1537
tushki7	0:60d829a0353a	1538	/* Returns the address in the SCU for a SFSCLK clock register,
tushki7	0:60d829a0353a	1539	recommend using ((volatile int ) &LPC_SCU->SFSCLK[c];) */
tushki7	0:60d829a0353a	1540	#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
tushki7	0:60d829a0353a	1541	((volatile int ) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
tushki7	0:60d829a0353a	1542
tushki7	0:60d829a0353a	1543	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1544	* GPIO pin interrupt register block structure
tushki7	0:60d829a0353a	1545	*/
tushki7	0:60d829a0353a	1546	#define LPC_GPIO_PIN_INT_BASE 0x40087000
tushki7	0:60d829a0353a	1547
tushki7	0:60d829a0353a	1548	typedef struct { /* GPIO_PIN_INT Structure */
tushki7	0:60d829a0353a	1549	__IO uint32_t ISEL; /* Pin Interrupt Mode register */
tushki7	0:60d829a0353a	1550	__IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
tushki7	0:60d829a0353a	1551	__O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
tushki7	0:60d829a0353a	1552	__O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
tushki7	0:60d829a0353a	1553	__IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
tushki7	0:60d829a0353a	1554	__O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
tushki7	0:60d829a0353a	1555	__O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
tushki7	0:60d829a0353a	1556	__IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
tushki7	0:60d829a0353a	1557	__IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
tushki7	0:60d829a0353a	1558	__IO uint32_t IST; /* Pin Interrupt Status register */
tushki7	0:60d829a0353a	1559	} LPC_GPIOPININT_T;
tushki7	0:60d829a0353a	1560
tushki7	0:60d829a0353a	1561	typedef enum LPC_GPIOPININT_MODE {
tushki7	0:60d829a0353a	1562	GPIOPININT_RISING_EDGE = 0x01,
tushki7	0:60d829a0353a	1563	GPIOPININT_FALLING_EDGE = 0x02,
tushki7	0:60d829a0353a	1564	GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
tushki7	0:60d829a0353a	1565	GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
tushki7	0:60d829a0353a	1566	} LPC_GPIOPININT_MODE_T;
tushki7	0:60d829a0353a	1567
tushki7	0:60d829a0353a	1568	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1569	* GPIO grouped interrupt register block structure
tushki7	0:60d829a0353a	1570	*/
tushki7	0:60d829a0353a	1571	#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
tushki7	0:60d829a0353a	1572	#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
tushki7	0:60d829a0353a	1573
tushki7	0:60d829a0353a	1574	typedef struct { /* GPIO_GROUP_INTn Structure */
tushki7	0:60d829a0353a	1575	__IO uint32_t CTRL; /* GPIO grouped interrupt control register */
tushki7	0:60d829a0353a	1576	__I uint32_t RESERVED0[7];
tushki7	0:60d829a0353a	1577	__IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
tushki7	0:60d829a0353a	1578	__IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
tushki7	0:60d829a0353a	1579	} LPC_GPIOGROUPINT_T;
tushki7	0:60d829a0353a	1580
tushki7	0:60d829a0353a	1581	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1582	* Motor Control PWM register block structure
tushki7	0:60d829a0353a	1583	*/
tushki7	0:60d829a0353a	1584	#define LPC_MCPWM_BASE 0x400A0000
tushki7	0:60d829a0353a	1585
tushki7	0:60d829a0353a	1586	typedef struct { /* MCPWM Structure */
tushki7	0:60d829a0353a	1587	__I uint32_t CON; /* PWM Control read address */
tushki7	0:60d829a0353a	1588	__O uint32_t CON_SET; /* PWM Control set address */
tushki7	0:60d829a0353a	1589	__O uint32_t CON_CLR; /* PWM Control clear address */
tushki7	0:60d829a0353a	1590	__I uint32_t CAPCON; /* Capture Control read address */
tushki7	0:60d829a0353a	1591	__O uint32_t CAPCON_SET; /* Capture Control set address */
tushki7	0:60d829a0353a	1592	__O uint32_t CAPCON_CLR; /* Event Control clear address */
tushki7	0:60d829a0353a	1593	__IO uint32_t TC[3]; /* Timer Counter register */
tushki7	0:60d829a0353a	1594	__IO uint32_t LIM[3]; /* Limit register */
tushki7	0:60d829a0353a	1595	__IO uint32_t MAT[3]; /* Match register */
tushki7	0:60d829a0353a	1596	__IO uint32_t DT; /* Dead time register */
tushki7	0:60d829a0353a	1597	__IO uint32_t CCP; /* Communication Pattern register */
tushki7	0:60d829a0353a	1598	__I uint32_t CAP[3]; /* Capture register */
tushki7	0:60d829a0353a	1599	__I uint32_t INTEN; /* Interrupt Enable read address */
tushki7	0:60d829a0353a	1600	__O uint32_t INTEN_SET; /* Interrupt Enable set address */
tushki7	0:60d829a0353a	1601	__O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
tushki7	0:60d829a0353a	1602	__I uint32_t CNTCON; /* Count Control read address */
tushki7	0:60d829a0353a	1603	__O uint32_t CNTCON_SET; /* Count Control set address */
tushki7	0:60d829a0353a	1604	__O uint32_t CNTCON_CLR; /* Count Control clear address */
tushki7	0:60d829a0353a	1605	__I uint32_t INTF; /* Interrupt flags read address */
tushki7	0:60d829a0353a	1606	__O uint32_t INTF_SET; /* Interrupt flags set address */
tushki7	0:60d829a0353a	1607	__O uint32_t INTF_CLR; /* Interrupt flags clear address */
tushki7	0:60d829a0353a	1608	__O uint32_t CAP_CLR; /* Capture clear address */
tushki7	0:60d829a0353a	1609	} LPC_MCPWM_T;
tushki7	0:60d829a0353a	1610
tushki7	0:60d829a0353a	1611	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1612	* I2C register block structure
tushki7	0:60d829a0353a	1613	*/
tushki7	0:60d829a0353a	1614	#define LPC_I2C0_BASE 0x400A1000
tushki7	0:60d829a0353a	1615	#define LPC_I2C1_BASE 0x400E0000
tushki7	0:60d829a0353a	1616
tushki7	0:60d829a0353a	1617	typedef struct { /* I2C0 Structure */
tushki7	0:60d829a0353a	1618	__IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
tushki7	0:60d829a0353a	1619	__I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
tushki7	0:60d829a0353a	1620	__IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
tushki7	0:60d829a0353a	1621	__IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
tushki7	0:60d829a0353a	1622	__IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
tushki7	0:60d829a0353a	1623	__IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
tushki7	0:60d829a0353a	1624	__O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
tushki7	0:60d829a0353a	1625	__IO uint32_t MMCTRL; /* Monitor mode control register. */
tushki7	0:60d829a0353a	1626	__IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
tushki7	0:60d829a0353a	1627	__IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
tushki7	0:60d829a0353a	1628	__IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
tushki7	0:60d829a0353a	1629	__I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
tushki7	0:60d829a0353a	1630	__IO uint32_t MASK[4]; /* I2C Slave address mask register */
tushki7	0:60d829a0353a	1631	} LPC_I2C_T;
tushki7	0:60d829a0353a	1632
tushki7	0:60d829a0353a	1633	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1634	* I2S register block structure
tushki7	0:60d829a0353a	1635	*/
tushki7	0:60d829a0353a	1636	#define LPC_I2S0_BASE 0x400A2000
tushki7	0:60d829a0353a	1637	#define LPC_I2S1_BASE 0x400A3000
tushki7	0:60d829a0353a	1638
tushki7	0:60d829a0353a	1639	typedef struct { /* I2S Structure */
tushki7	0:60d829a0353a	1640	__IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
tushki7	0:60d829a0353a	1641	__IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
tushki7	0:60d829a0353a	1642	__O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
tushki7	0:60d829a0353a	1643	__I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
tushki7	0:60d829a0353a	1644	__I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
tushki7	0:60d829a0353a	1645	__IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
tushki7	0:60d829a0353a	1646	__IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
tushki7	0:60d829a0353a	1647	__IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
tushki7	0:60d829a0353a	1648	__IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
tushki7	0:60d829a0353a	1649	__IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
tushki7	0:60d829a0353a	1650	__IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
tushki7	0:60d829a0353a	1651	__IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
tushki7	0:60d829a0353a	1652	__IO uint32_t TXMODE; /* I2S Transmit mode control */
tushki7	0:60d829a0353a	1653	__IO uint32_t RXMODE; /* I2S Receive mode control */
tushki7	0:60d829a0353a	1654	} LPC_I2S_T;
tushki7	0:60d829a0353a	1655
tushki7	0:60d829a0353a	1656	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1657	* CCAN Controller Area Network register block structure
tushki7	0:60d829a0353a	1658	*/
tushki7	0:60d829a0353a	1659	#define LPC_C_CAN1_BASE 0x400A4000
tushki7	0:60d829a0353a	1660	#define LPC_C_CAN0_BASE 0x400E2000
tushki7	0:60d829a0353a	1661
tushki7	0:60d829a0353a	1662	typedef struct { /* C_CAN message interface Structure */
tushki7	0:60d829a0353a	1663	__IO uint32_t IF_CMDREQ; /* Message interface command request */
tushki7	0:60d829a0353a	1664	union {
tushki7	0:60d829a0353a	1665	__IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
tushki7	0:60d829a0353a	1666	__IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
tushki7	0:60d829a0353a	1667	};
tushki7	0:60d829a0353a	1668
tushki7	0:60d829a0353a	1669	__IO uint32_t IF_MSK1; /* Message interface mask 1 */
tushki7	0:60d829a0353a	1670	__IO uint32_t IF_MSK2; /* Message interface mask 2 */
tushki7	0:60d829a0353a	1671	__IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
tushki7	0:60d829a0353a	1672	__IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
tushki7	0:60d829a0353a	1673	__IO uint32_t IF_MCTRL; /* Message interface message control */
tushki7	0:60d829a0353a	1674	__IO uint32_t IF_DA1; /* Message interface data A1 */
tushki7	0:60d829a0353a	1675	__IO uint32_t IF_DA2; /* Message interface data A2 */
tushki7	0:60d829a0353a	1676	__IO uint32_t IF_DB1; /* Message interface data B1 */
tushki7	0:60d829a0353a	1677	__IO uint32_t IF_DB2; /* Message interface data B2 */
tushki7	0:60d829a0353a	1678	__I uint32_t RESERVED[13];
tushki7	0:60d829a0353a	1679	} LPC_CCAN_IF_T;
tushki7	0:60d829a0353a	1680
tushki7	0:60d829a0353a	1681	typedef struct { /* C_CAN Structure */
tushki7	0:60d829a0353a	1682	__IO uint32_t CNTL; /* CAN control */
tushki7	0:60d829a0353a	1683	__IO uint32_t STAT; /* Status register */
tushki7	0:60d829a0353a	1684	__I uint32_t EC; /* Error counter */
tushki7	0:60d829a0353a	1685	__IO uint32_t BT; /* Bit timing register */
tushki7	0:60d829a0353a	1686	__I uint32_t INT; /* Interrupt register */
tushki7	0:60d829a0353a	1687	__IO uint32_t TEST; /* Test register */
tushki7	0:60d829a0353a	1688	__IO uint32_t BRPE; /* Baud rate prescaler extension register */
tushki7	0:60d829a0353a	1689	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	1690	LPC_CCAN_IF_T IF[2];
tushki7	0:60d829a0353a	1691	__I uint32_t RESERVED2[8];
tushki7	0:60d829a0353a	1692	__I uint32_t TXREQ1; /* Transmission request 1 */
tushki7	0:60d829a0353a	1693	__I uint32_t TXREQ2; /* Transmission request 2 */
tushki7	0:60d829a0353a	1694	__I uint32_t RESERVED3[6];
tushki7	0:60d829a0353a	1695	__I uint32_t ND1; /* New data 1 */
tushki7	0:60d829a0353a	1696	__I uint32_t ND2; /* New data 2 */
tushki7	0:60d829a0353a	1697	__I uint32_t RESERVED4[6];
tushki7	0:60d829a0353a	1698	__I uint32_t IR1; /* Interrupt pending 1 */
tushki7	0:60d829a0353a	1699	__I uint32_t IR2; /* Interrupt pending 2 */
tushki7	0:60d829a0353a	1700	__I uint32_t RESERVED5[6];
tushki7	0:60d829a0353a	1701	__I uint32_t MSGV1; /* Message valid 1 */
tushki7	0:60d829a0353a	1702	__I uint32_t MSGV2; /* Message valid 2 */
tushki7	0:60d829a0353a	1703	__I uint32_t RESERVED6[6];
tushki7	0:60d829a0353a	1704	__IO uint32_t CLKDIV; /* CAN clock divider register */
tushki7	0:60d829a0353a	1705	} LPC_CCAN_T;
tushki7	0:60d829a0353a	1706
tushki7	0:60d829a0353a	1707	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1708	* Repetitive Interrupt Timer register block structure
tushki7	0:60d829a0353a	1709	*/
tushki7	0:60d829a0353a	1710	#define LPC_RITIMER_BASE 0x400C0000
tushki7	0:60d829a0353a	1711
tushki7	0:60d829a0353a	1712	typedef struct { /* RITIMER Structure */
tushki7	0:60d829a0353a	1713	__IO uint32_t COMPVAL; /* Compare register */
tushki7	0:60d829a0353a	1714	__IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
tushki7	0:60d829a0353a	1715	__IO uint32_t CTRL; /* Control register. */
tushki7	0:60d829a0353a	1716	__IO uint32_t COUNTER; /* 32-bit counter */
tushki7	0:60d829a0353a	1717	} LPC_RITIMER_T;
tushki7	0:60d829a0353a	1718
tushki7	0:60d829a0353a	1719	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1720	* Quadrature Encoder Interface register block structure
tushki7	0:60d829a0353a	1721	*/
tushki7	0:60d829a0353a	1722	#define LPC_QEI_BASE 0x400C6000
tushki7	0:60d829a0353a	1723
tushki7	0:60d829a0353a	1724	typedef struct { /* QEI Structure */
tushki7	0:60d829a0353a	1725	__O uint32_t CON; /* Control register */
tushki7	0:60d829a0353a	1726	__I uint32_t STAT; /* Encoder status register */
tushki7	0:60d829a0353a	1727	__IO uint32_t CONF; /* Configuration register */
tushki7	0:60d829a0353a	1728	__I uint32_t POS; /* Position register */
tushki7	0:60d829a0353a	1729	__IO uint32_t MAXPOS; /* Maximum position register */
tushki7	0:60d829a0353a	1730	__IO uint32_t CMPOS0; /* position compare register 0 */
tushki7	0:60d829a0353a	1731	__IO uint32_t CMPOS1; /* position compare register 1 */
tushki7	0:60d829a0353a	1732	__IO uint32_t CMPOS2; /* position compare register 2 */
tushki7	0:60d829a0353a	1733	__I uint32_t INXCNT; /* Index count register */
tushki7	0:60d829a0353a	1734	__IO uint32_t INXCMP0; /* Index compare register 0 */
tushki7	0:60d829a0353a	1735	__IO uint32_t LOAD; /* Velocity timer reload register */
tushki7	0:60d829a0353a	1736	__I uint32_t TIME; /* Velocity timer register */
tushki7	0:60d829a0353a	1737	__I uint32_t VEL; /* Velocity counter register */
tushki7	0:60d829a0353a	1738	__I uint32_t CAP; /* Velocity capture register */
tushki7	0:60d829a0353a	1739	__IO uint32_t VELCOMP; /* Velocity compare register */
tushki7	0:60d829a0353a	1740	__IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
tushki7	0:60d829a0353a	1741	__IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
tushki7	0:60d829a0353a	1742	__IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
tushki7	0:60d829a0353a	1743	__IO uint32_t WINDOW; /* Index acceptance window register */
tushki7	0:60d829a0353a	1744	__IO uint32_t INXCMP1; /* Index compare register 1 */
tushki7	0:60d829a0353a	1745	__IO uint32_t INXCMP2; /* Index compare register 2 */
tushki7	0:60d829a0353a	1746	__I uint32_t RESERVED0[993];
tushki7	0:60d829a0353a	1747	__O uint32_t IEC; /* Interrupt enable clear register */
tushki7	0:60d829a0353a	1748	__O uint32_t IES; /* Interrupt enable set register */
tushki7	0:60d829a0353a	1749	__I uint32_t INTSTAT; /* Interrupt status register */
tushki7	0:60d829a0353a	1750	__I uint32_t IE; /* Interrupt enable register */
tushki7	0:60d829a0353a	1751	__O uint32_t CLR; /* Interrupt status clear register */
tushki7	0:60d829a0353a	1752	__O uint32_t SET; /* Interrupt status set register */
tushki7	0:60d829a0353a	1753	} LPC_QEI_T;
tushki7	0:60d829a0353a	1754
tushki7	0:60d829a0353a	1755	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1756	* Global Input Multiplexer Array (GIMA) register block structure
tushki7	0:60d829a0353a	1757	*/
tushki7	0:60d829a0353a	1758	#define LPC_GIMA_BASE 0x400C7000
tushki7	0:60d829a0353a	1759
tushki7	0:60d829a0353a	1760	typedef struct { /* GIMA Structure */
tushki7	0:60d829a0353a	1761	__IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x4)+y)) /
tushki7	0:60d829a0353a	1762	__IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
tushki7	0:60d829a0353a	1763	__IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
tushki7	0:60d829a0353a	1764	__IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
tushki7	0:60d829a0353a	1765	__IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
tushki7	0:60d829a0353a	1766	__IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
tushki7	0:60d829a0353a	1767	__IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
tushki7	0:60d829a0353a	1768	__IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
tushki7	0:60d829a0353a	1769	} LPC_GIMA_T;
tushki7	0:60d829a0353a	1770
tushki7	0:60d829a0353a	1771	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1772	* DAC register block structure
tushki7	0:60d829a0353a	1773	*/
tushki7	0:60d829a0353a	1774	#define LPC_DAC_BASE 0x400E1000
tushki7	0:60d829a0353a	1775
tushki7	0:60d829a0353a	1776	typedef struct { /* DAC Structure */
tushki7	0:60d829a0353a	1777	__IO uint32_t CR; /* DAC register. Holds the conversion data. */
tushki7	0:60d829a0353a	1778	__IO uint32_t CTRL; /* DAC control register. */
tushki7	0:60d829a0353a	1779	__IO uint32_t CNTVAL; /* DAC counter value register. */
tushki7	0:60d829a0353a	1780	} LPC_DAC_T;
tushki7	0:60d829a0353a	1781
tushki7	0:60d829a0353a	1782	/* After the selected settling time after this field is written with a
tushki7	0:60d829a0353a	1783	* new VALUE, the voltage on the AOUT pin (with respect to VSSA)
tushki7	0:60d829a0353a	1784	* is VALUE/1024 ? VREF
tushki7	0:60d829a0353a	1785	*/
tushki7	0:60d829a0353a	1786	#define DAC_RANGE 0x3FF
tushki7	0:60d829a0353a	1787	#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
tushki7	0:60d829a0353a	1788	#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
tushki7	0:60d829a0353a	1789	#define DAC_VALUE(n) DAC_SET(n)
tushki7	0:60d829a0353a	1790	/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
tushki7	0:60d829a0353a	1791	* and the maximum current is 700 microAmpere
tushki7	0:60d829a0353a	1792	* If this bit = 1: The settling time of the DAC is 2.5 microsecond
tushki7	0:60d829a0353a	1793	* and the maximum current is 350 microAmpere
tushki7	0:60d829a0353a	1794	*/
tushki7	0:60d829a0353a	1795	#define DAC_BIAS_EN ((uint32_t) (1 << 16))
tushki7	0:60d829a0353a	1796	/* Value to reload interrupt DMA counter */
tushki7	0:60d829a0353a	1797	#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
tushki7	0:60d829a0353a	1798
tushki7	0:60d829a0353a	1799	#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
tushki7	0:60d829a0353a	1800	#define DAC_CNT_ENA ((uint32_t) (1 << 2))
tushki7	0:60d829a0353a	1801	#define DAC_DMA_ENA ((uint32_t) (1 << 3))
tushki7	0:60d829a0353a	1802	#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
tushki7	0:60d829a0353a	1803
tushki7	0:60d829a0353a	1804	/* Current option in DAC configuration option */
tushki7	0:60d829a0353a	1805	typedef enum DAC_CURRENT_OPT {
tushki7	0:60d829a0353a	1806	DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
tushki7	0:60d829a0353a	1807	allows for a maximum update rate of 1 MHz */
tushki7	0:60d829a0353a	1808	DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
tushki7	0:60d829a0353a	1809	allows for a maximum update rate of 400 kHz */
tushki7	0:60d829a0353a	1810	} DAC_CURRENT_OPT_T;
tushki7	0:60d829a0353a	1811
tushki7	0:60d829a0353a	1812	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1813	* ADC register block structure
tushki7	0:60d829a0353a	1814	*/
tushki7	0:60d829a0353a	1815	#define LPC_ADC0_BASE 0x400E3000
tushki7	0:60d829a0353a	1816	#define LPC_ADC1_BASE 0x400E4000
tushki7	0:60d829a0353a	1817	#define ADC_ACC_10BITS
tushki7	0:60d829a0353a	1818
tushki7	0:60d829a0353a	1819	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1820	* 10 or 12-bit ADC register block structure
tushki7	0:60d829a0353a	1821	*/
tushki7	0:60d829a0353a	1822	typedef struct { /* ADCn Structure */
tushki7	0:60d829a0353a	1823	__IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
tushki7	0:60d829a0353a	1824	__I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
tushki7	0:60d829a0353a	1825	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	1826	__IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
tushki7	0:60d829a0353a	1827	__I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
tushki7	0:60d829a0353a	1828	__I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
tushki7	0:60d829a0353a	1829	} LPC_ADC_T;
tushki7	0:60d829a0353a	1830
tushki7	0:60d829a0353a	1831	/* ADC register support bitfields and mask */
tushki7	0:60d829a0353a	1832	#define ADC_RANGE 0x3FF
tushki7	0:60d829a0353a	1833	#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
tushki7	0:60d829a0353a	1834	#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
tushki7	0:60d829a0353a	1835	#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
tushki7	0:60d829a0353a	1836	#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
tushki7	0:60d829a0353a	1837	#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
tushki7	0:60d829a0353a	1838	#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
tushki7	0:60d829a0353a	1839	#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
tushki7	0:60d829a0353a	1840	#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
tushki7	0:60d829a0353a	1841	#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
tushki7	0:60d829a0353a	1842	#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
tushki7	0:60d829a0353a	1843	#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
tushki7	0:60d829a0353a	1844	#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
tushki7	0:60d829a0353a	1845	#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
tushki7	0:60d829a0353a	1846	#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
tushki7	0:60d829a0353a	1847	#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
tushki7	0:60d829a0353a	1848	#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
tushki7	0:60d829a0353a	1849	#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
tushki7	0:60d829a0353a	1850	#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) \| ADC_CR_BITACC(0x07) \| ADC_CR_PDN)
tushki7	0:60d829a0353a	1851
tushki7	0:60d829a0353a	1852	/* ADC status register used for IP drivers */
tushki7	0:60d829a0353a	1853	typedef enum ADC_STATUS {
tushki7	0:60d829a0353a	1854	ADC_DR_DONE_STAT, /* ADC data register staus */
tushki7	0:60d829a0353a	1855	ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
tushki7	0:60d829a0353a	1856	ADC_DR_ADINT_STAT /* ADC interrupt status */
tushki7	0:60d829a0353a	1857	} ADC_STATUS_T;
tushki7	0:60d829a0353a	1858
tushki7	0:60d829a0353a	1859	/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
tushki7	0:60d829a0353a	1860	typedef enum ADC_START_MODE {
tushki7	0:60d829a0353a	1861	ADC_NO_START = 0,
tushki7	0:60d829a0353a	1862	ADC_START_NOW, /* Start conversion now */
tushki7	0:60d829a0353a	1863	ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
tushki7	0:60d829a0353a	1864	ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
tushki7	0:60d829a0353a	1865	ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
tushki7	0:60d829a0353a	1866	ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
tushki7	0:60d829a0353a	1867	ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
tushki7	0:60d829a0353a	1868	} ADC_START_MODE_T;
tushki7	0:60d829a0353a	1869
tushki7	0:60d829a0353a	1870	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1871	* GPIO port register block structure
tushki7	0:60d829a0353a	1872	*/
tushki7	0:60d829a0353a	1873	#define LPC_GPIO_PORT_BASE 0x400F4000
tushki7	0:60d829a0353a	1874	#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
tushki7	0:60d829a0353a	1875	#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
tushki7	0:60d829a0353a	1876	#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
tushki7	0:60d829a0353a	1877	#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
tushki7	0:60d829a0353a	1878	#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
tushki7	0:60d829a0353a	1879	#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
tushki7	0:60d829a0353a	1880	#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
tushki7	0:60d829a0353a	1881	#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
tushki7	0:60d829a0353a	1882
tushki7	0:60d829a0353a	1883	typedef struct { /* GPIO_PORT Structure */
tushki7	0:60d829a0353a	1884	__IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
tushki7	0:60d829a0353a	1885	__IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
tushki7	0:60d829a0353a	1886	__IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
tushki7	0:60d829a0353a	1887	__IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
tushki7	0:60d829a0353a	1888	__IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
tushki7	0:60d829a0353a	1889	__IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
tushki7	0:60d829a0353a	1890	__IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
tushki7	0:60d829a0353a	1891	__O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
tushki7	0:60d829a0353a	1892	__O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
tushki7	0:60d829a0353a	1893	} LPC_GPIO_T;
tushki7	0:60d829a0353a	1894
tushki7	0:60d829a0353a	1895	/* Calculate GPIO offset and port register address from group and pin number */
tushki7	0:60d829a0353a	1896	#define GPIO_OFF(port, pin) ((port << 5) + pin)
tushki7	0:60d829a0353a	1897	#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
tushki7	0:60d829a0353a	1898
tushki7	0:60d829a0353a	1899	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1900	* SPI register block structure
tushki7	0:60d829a0353a	1901	*/
tushki7	0:60d829a0353a	1902	#define LPC_SPI_BASE 0x40100000
tushki7	0:60d829a0353a	1903
tushki7	0:60d829a0353a	1904	typedef struct { /* SPI Structure */
tushki7	0:60d829a0353a	1905	__IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
tushki7	0:60d829a0353a	1906	__I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
tushki7	0:60d829a0353a	1907	__IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
tushki7	0:60d829a0353a	1908	__IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
tushki7	0:60d829a0353a	1909	__I uint32_t RESERVED0[3];
tushki7	0:60d829a0353a	1910	__IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
tushki7	0:60d829a0353a	1911	} LPC_SPI_T;
tushki7	0:60d829a0353a	1912
tushki7	0:60d829a0353a	1913	/* SPI CFG Register BitMask */
tushki7	0:60d829a0353a	1914	#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
tushki7	0:60d829a0353a	1915	/* Enable of controlling the number of bits per transfer */
tushki7	0:60d829a0353a	1916	#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
tushki7	0:60d829a0353a	1917	/* Mask of field of bit controlling */
tushki7	0:60d829a0353a	1918	#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
tushki7	0:60d829a0353a	1919	/* Set the number of bits per a transfer */
tushki7	0:60d829a0353a	1920	#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
tushki7	0:60d829a0353a	1921	/* SPI Clock Phase Select*/
tushki7	0:60d829a0353a	1922	#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /Capture data on the first edge, Change data on the following edge/
tushki7	0:60d829a0353a	1923	#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
tushki7	0:60d829a0353a	1924	/* SPI Clock Polarity Select*/
tushki7	0:60d829a0353a	1925	#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
tushki7	0:60d829a0353a	1926	#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
tushki7	0:60d829a0353a	1927	/* SPI Slave Mode Select */
tushki7	0:60d829a0353a	1928	#define SPI_CR_SLAVE_EN ((uint32_t) 0)
tushki7	0:60d829a0353a	1929	/* SPI Master Mode Select */
tushki7	0:60d829a0353a	1930	#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
tushki7	0:60d829a0353a	1931	/* SPI MSB First mode enable */
tushki7	0:60d829a0353a	1932	#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
tushki7	0:60d829a0353a	1933	/* SPI LSB First mode enable */
tushki7	0:60d829a0353a	1934	#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
tushki7	0:60d829a0353a	1935	/* SPI interrupt enable */
tushki7	0:60d829a0353a	1936	#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
tushki7	0:60d829a0353a	1937	/* SPI STAT Register BitMask */
tushki7	0:60d829a0353a	1938	#define SPI_SR_BITMASK ((uint32_t) 0xF8)
tushki7	0:60d829a0353a	1939	/* Slave abort Flag */
tushki7	0:60d829a0353a	1940	#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
tushki7	0:60d829a0353a	1941	/* Mode fault Flag */
tushki7	0:60d829a0353a	1942	#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
tushki7	0:60d829a0353a	1943	/* Read overrun flag*/
tushki7	0:60d829a0353a	1944	#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
tushki7	0:60d829a0353a	1945	/* Write collision flag. */
tushki7	0:60d829a0353a	1946	#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
tushki7	0:60d829a0353a	1947	/* SPI transfer complete flag. */
tushki7	0:60d829a0353a	1948	#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
tushki7	0:60d829a0353a	1949	/* SPI error flag */
tushki7	0:60d829a0353a	1950	#define SPI_SR_ERROR (SPI_SR_ABRT \| SPI_SR_MODF \| SPI_SR_ROVR \| SPI_SR_WCOL)
tushki7	0:60d829a0353a	1951	/* Enable SPI Test Mode */
tushki7	0:60d829a0353a	1952	#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
tushki7	0:60d829a0353a	1953	/* SPI interrupt flag */
tushki7	0:60d829a0353a	1954	#define SPI_INT_SPIF ((uint32_t) (1 << 0))
tushki7	0:60d829a0353a	1955	/* Receiver Data */
tushki7	0:60d829a0353a	1956	#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
tushki7	0:60d829a0353a	1957
tushki7	0:60d829a0353a	1958	/* SPI Mode*/
tushki7	0:60d829a0353a	1959	typedef enum LPC_SPI_MODE {
tushki7	0:60d829a0353a	1960	SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
tushki7	0:60d829a0353a	1961	SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
tushki7	0:60d829a0353a	1962	} LPC_SPI_MODE_T;
tushki7	0:60d829a0353a	1963
tushki7	0:60d829a0353a	1964	/* SPI Clock Mode*/
tushki7	0:60d829a0353a	1965	typedef enum LPC_SPI_CLOCK_MODE {
tushki7	0:60d829a0353a	1966	SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
tushki7	0:60d829a0353a	1967	SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
tushki7	0:60d829a0353a	1968	SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
tushki7	0:60d829a0353a	1969	SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
tushki7	0:60d829a0353a	1970	SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
tushki7	0:60d829a0353a	1971	SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
tushki7	0:60d829a0353a	1972	SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
tushki7	0:60d829a0353a	1973	SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
tushki7	0:60d829a0353a	1974	} LPC_SPI_CLOCK_MODE_T;
tushki7	0:60d829a0353a	1975
tushki7	0:60d829a0353a	1976	/* SPI Data Order Mode*/
tushki7	0:60d829a0353a	1977	typedef enum LPC_SPI_DATA_ORDER {
tushki7	0:60d829a0353a	1978	SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
tushki7	0:60d829a0353a	1979	SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
tushki7	0:60d829a0353a	1980	} LPC_SPI_DATA_ORDER_T;
tushki7	0:60d829a0353a	1981
tushki7	0:60d829a0353a	1982	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	1983	* Serial GPIO register block structure
tushki7	0:60d829a0353a	1984	*/
tushki7	0:60d829a0353a	1985	#define LPC_SGPIO_BASE 0x40101000
tushki7	0:60d829a0353a	1986
tushki7	0:60d829a0353a	1987	typedef struct { /* SGPIO Structure */
tushki7	0:60d829a0353a	1988	__IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
tushki7	0:60d829a0353a	1989	__IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
tushki7	0:60d829a0353a	1990	__IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
tushki7	0:60d829a0353a	1991	__IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
tushki7	0:60d829a0353a	1992	__IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
tushki7	0:60d829a0353a	1993	__IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
tushki7	0:60d829a0353a	1994	__IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
tushki7	0:60d829a0353a	1995	__IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
tushki7	0:60d829a0353a	1996	__IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
tushki7	0:60d829a0353a	1997	__IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
tushki7	0:60d829a0353a	1998	__IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
tushki7	0:60d829a0353a	1999	__IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
tushki7	0:60d829a0353a	2000	__I uint32_t GPIO_INREG; /* GPIO input status register */
tushki7	0:60d829a0353a	2001	__IO uint32_t GPIO_OUTREG; /* GPIO output control register */
tushki7	0:60d829a0353a	2002	__IO uint32_t GPIO_OENREG; /* GPIO OE control register */
tushki7	0:60d829a0353a	2003	__IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
tushki7	0:60d829a0353a	2004	__IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
tushki7	0:60d829a0353a	2005	__I uint32_t RESERVED0[823];
tushki7	0:60d829a0353a	2006	__O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
tushki7	0:60d829a0353a	2007	__O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
tushki7	0:60d829a0353a	2008	__I uint32_t ENABLE_0; /* Shift clock interrupt enable */
tushki7	0:60d829a0353a	2009	__I uint32_t STATUS_0; /* Shift clock interrupt status */
tushki7	0:60d829a0353a	2010	__O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
tushki7	0:60d829a0353a	2011	__O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
tushki7	0:60d829a0353a	2012	__I uint32_t RESERVED1[2];
tushki7	0:60d829a0353a	2013	__O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
tushki7	0:60d829a0353a	2014	__O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
tushki7	0:60d829a0353a	2015	__I uint32_t ENABLE_1; /* Capture clock interrupt enable */
tushki7	0:60d829a0353a	2016	__I uint32_t STATUS_1; /* Capture clock interrupt status */
tushki7	0:60d829a0353a	2017	__O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
tushki7	0:60d829a0353a	2018	__O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
tushki7	0:60d829a0353a	2019	__I uint32_t RESERVED2[2];
tushki7	0:60d829a0353a	2020	__O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
tushki7	0:60d829a0353a	2021	__O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
tushki7	0:60d829a0353a	2022	__I uint32_t ENABLE_2; /* Pattern match interrupt enable */
tushki7	0:60d829a0353a	2023	__I uint32_t STATUS_2; /* Pattern match interrupt status */
tushki7	0:60d829a0353a	2024	__O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
tushki7	0:60d829a0353a	2025	__O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
tushki7	0:60d829a0353a	2026	__I uint32_t RESERVED3[2];
tushki7	0:60d829a0353a	2027	__O uint32_t CLR_EN_3; /* Input interrupt clear mask */
tushki7	0:60d829a0353a	2028	__O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
tushki7	0:60d829a0353a	2029	__I uint32_t ENABLE_3; /* Input bit match interrupt enable */
tushki7	0:60d829a0353a	2030	__I uint32_t STATUS_3; /* Input bit match interrupt status */
tushki7	0:60d829a0353a	2031	__O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
tushki7	0:60d829a0353a	2032	__O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
tushki7	0:60d829a0353a	2033	} LPC_SGPIO_T;
tushki7	0:60d829a0353a	2034
tushki7	0:60d829a0353a	2035	/* End of section using anonymous unions */
tushki7	0:60d829a0353a	2036	#if defined(__ARMCC_VERSION)
tushki7	0:60d829a0353a	2037	#pragma pop
tushki7	0:60d829a0353a	2038	#elif defined(__CWCC__)
tushki7	0:60d829a0353a	2039	#pragma pop
tushki7	0:60d829a0353a	2040	#elif defined(__IAR_SYSTEMS_ICC__)
tushki7	0:60d829a0353a	2041	//#pragma pop // FIXME not usable for IAR
tushki7	0:60d829a0353a	2042	#else /* defined(__GNUC__) and others */
tushki7	0:60d829a0353a	2043	/* Leave anonymous unions enabled */
tushki7	0:60d829a0353a	2044	#endif
tushki7	0:60d829a0353a	2045
tushki7	0:60d829a0353a	2046	/* ---------------------------------------------------------------------------
tushki7	0:60d829a0353a	2047	* LPC43xx Peripheral register set declarations
tushki7	0:60d829a0353a	2048	*/
tushki7	0:60d829a0353a	2049	#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
tushki7	0:60d829a0353a	2050	#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
tushki7	0:60d829a0353a	2051	#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
tushki7	0:60d829a0353a	2052	#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
tushki7	0:60d829a0353a	2053	#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
tushki7	0:60d829a0353a	2054	#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
tushki7	0:60d829a0353a	2055	#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
tushki7	0:60d829a0353a	2056	#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
tushki7	0:60d829a0353a	2057	#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
tushki7	0:60d829a0353a	2058	#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
tushki7	0:60d829a0353a	2059	#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
tushki7	0:60d829a0353a	2060	#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
tushki7	0:60d829a0353a	2061	#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
tushki7	0:60d829a0353a	2062	#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
tushki7	0:60d829a0353a	2063	#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
tushki7	0:60d829a0353a	2064	#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
tushki7	0:60d829a0353a	2065	#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
tushki7	0:60d829a0353a	2066	#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
tushki7	0:60d829a0353a	2067	#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
tushki7	0:60d829a0353a	2068	#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
tushki7	0:60d829a0353a	2069	#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
tushki7	0:60d829a0353a	2070	#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
tushki7	0:60d829a0353a	2071	#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
tushki7	0:60d829a0353a	2072	#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
tushki7	0:60d829a0353a	2073	#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
tushki7	0:60d829a0353a	2074	#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
tushki7	0:60d829a0353a	2075	#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
tushki7	0:60d829a0353a	2076	#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
tushki7	0:60d829a0353a	2077	#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
tushki7	0:60d829a0353a	2078	#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
tushki7	0:60d829a0353a	2079	#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
tushki7	0:60d829a0353a	2080	#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
tushki7	0:60d829a0353a	2081	#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
tushki7	0:60d829a0353a	2082	#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
tushki7	0:60d829a0353a	2083	#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
tushki7	0:60d829a0353a	2084	#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
tushki7	0:60d829a0353a	2085	#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
tushki7	0:60d829a0353a	2086	#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
tushki7	0:60d829a0353a	2087	#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
tushki7	0:60d829a0353a	2088	#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
tushki7	0:60d829a0353a	2089	#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
tushki7	0:60d829a0353a	2090	#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
tushki7	0:60d829a0353a	2091	#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
tushki7	0:60d829a0353a	2092	#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
tushki7	0:60d829a0353a	2093	#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
tushki7	0:60d829a0353a	2094	#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
tushki7	0:60d829a0353a	2095	#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
tushki7	0:60d829a0353a	2096	#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
tushki7	0:60d829a0353a	2097	#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
tushki7	0:60d829a0353a	2098	#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
tushki7	0:60d829a0353a	2099	#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
tushki7	0:60d829a0353a	2100	#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
tushki7	0:60d829a0353a	2101	#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
tushki7	0:60d829a0353a	2102	#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
tushki7	0:60d829a0353a	2103	#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
tushki7	0:60d829a0353a	2104	#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
tushki7	0:60d829a0353a	2105	#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
tushki7	0:60d829a0353a	2106	#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
tushki7	0:60d829a0353a	2107	#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
tushki7	0:60d829a0353a	2108
tushki7	0:60d829a0353a	2109	#ifdef __cplusplus
tushki7	0:60d829a0353a	2110	}
tushki7	0:60d829a0353a	2111	#endif
tushki7	0:60d829a0353a	2112
tushki7	0:60d829a0353a	2113	#endif /* __LPC43XX_H */

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_LPC4337/LPC43xx.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

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