A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 #ifndef MBED_BITFIELDS_H
tushki7 0:60d829a0353a 2 #define MBED_BITFIELDS_H
tushki7 0:60d829a0353a 3
tushki7 0:60d829a0353a 4 //! Massage  x for use in bitfield  name.
tushki7 0:60d829a0353a 5 #define BFN_PREP(x, name) ( ((x)<<name##_SHIFT) & name##_MASK )
tushki7 0:60d829a0353a 6
tushki7 0:60d829a0353a 7 //! Get the value of bitfield  name from  y. Equivalent to (var=) y.name
tushki7 0:60d829a0353a 8 #define BFN_GET(y, name) ( ((y) & name##_MASK)>>name##_SHIFT )
tushki7 0:60d829a0353a 9
tushki7 0:60d829a0353a 10 //! Set bitfield  name from  y to  x: y.name= x.
tushki7 0:60d829a0353a 11 #define BFN_SET(y, x, name) (y = ((y)&~name##_MASK) | BFN_PREP(x,name) )
tushki7 0:60d829a0353a 12
tushki7 0:60d829a0353a 13
tushki7 0:60d829a0353a 14 /* SYSMEMREMAP, address 0x4004 8000 */
tushki7 0:60d829a0353a 15 #define SYSMEMREMAP_MAP_MASK 0x0003 // System memory remap
tushki7 0:60d829a0353a 16 #define SYSMEMREMAP_MAP_SHIFT 0
tushki7 0:60d829a0353a 17
tushki7 0:60d829a0353a 18 /* PRESETCTRL, address 0x4004 8004 */
tushki7 0:60d829a0353a 19 #define PRESETCTRL_SSP0_RST_N (1 << 0) // SPI0 reset control
tushki7 0:60d829a0353a 20 #define PRESETCTRL_I2C_RST_N (1 << 1) // I2C reset control
tushki7 0:60d829a0353a 21 #define PRESETCTRL_SSP1_RST_N (1 << 2) // SPI1 reset control
tushki7 0:60d829a0353a 22 #define PRESETCTRL_CAN_RST_N (1 << 3) // C_CAN reset control. See Section 3.1 for part specific details.
tushki7 0:60d829a0353a 23
tushki7 0:60d829a0353a 24 /* SYSPLLCTRL, address 0x4004 8008 */
tushki7 0:60d829a0353a 25 #define SYSPLLCTRL_MSEL_MASK 0x001F // Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.
tushki7 0:60d829a0353a 26 #define SYSPLLCTRL_MSEL_SHIFT 0
tushki7 0:60d829a0353a 27 #define SYSPLLCTRL_PSEL_MASK 0x0060 // Post divider ratio P. The division ratio is 2 P.
tushki7 0:60d829a0353a 28 #define SYSPLLCTRL_PSEL_SHIFT 5
tushki7 0:60d829a0353a 29
tushki7 0:60d829a0353a 30 /* SYSPLLSTAT, address 0x4004 800C */
tushki7 0:60d829a0353a 31 #define SYSPLLSTAT_LOCK (1 << 0) // PLL lock status
tushki7 0:60d829a0353a 32
tushki7 0:60d829a0353a 33 /* SYSOSCCTRL, address 0x4004 8020 */
tushki7 0:60d829a0353a 34 #define SYSOSCCTRL_BYPASS (1 << 0) // Bypass system oscillator
tushki7 0:60d829a0353a 35 #define SYSOSCCTRL_FREQRANGE (1 << 1) // Determines frequency range for Low-power oscillator.
tushki7 0:60d829a0353a 36
tushki7 0:60d829a0353a 37 /* WDTOSCCTRL, address 0x4004 8024 */
tushki7 0:60d829a0353a 38 #define WDTOSCCTRL_DIVSEL_MASK 0x001F // Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 (1 + DIVSEL)) 00000: 2 (1 + DIVSEL) = 2 00001: 2 (1 + DIVSEL) = 4 to 11111: 2 (1 + DIVSEL) = 64
tushki7 0:60d829a0353a 39 #define WDTOSCCTRL_DIVSEL_SHIFT 0
tushki7 0:60d829a0353a 40 #define WDTOSCCTRL_FREQSEL_MASK 0x01E0 // Select watchdog oscillator analog output frequency (Fclkana).
tushki7 0:60d829a0353a 41 #define WDTOSCCTRL_FREQSEL_SHIFT 5
tushki7 0:60d829a0353a 42
tushki7 0:60d829a0353a 43 /* IRCCTRL, address 0x4004 8028 */
tushki7 0:60d829a0353a 44 #define IRCCTRL_TRIM_MASK 0x00FF // Trim value
tushki7 0:60d829a0353a 45 #define IRCCTRL_TRIM_SHIFT 0
tushki7 0:60d829a0353a 46
tushki7 0:60d829a0353a 47 /* SYSRSTSTAT, address 0x4004 8030 */
tushki7 0:60d829a0353a 48 #define SYSRSTSTAT_POR (1 << 0) // POR reset status
tushki7 0:60d829a0353a 49 #define SYSRSTSTAT_EXTRST (1 << 1) // Status of the external RESET pin.
tushki7 0:60d829a0353a 50 #define SYSRSTSTAT_WDT (1 << 2) // Status of the Watchdog reset
tushki7 0:60d829a0353a 51 #define SYSRSTSTAT_BOD (1 << 3) // Status of the Brown-out detect reset
tushki7 0:60d829a0353a 52 #define SYSRSTSTAT_SYSRST (1 << 4) // Status of the software system reset
tushki7 0:60d829a0353a 53
tushki7 0:60d829a0353a 54 /* SYSPLLCLKSEL, address 0x4004 8040 */
tushki7 0:60d829a0353a 55 #define SYSPLLCLKSEL_SEL_MASK 0x0003 // System PLL clock source
tushki7 0:60d829a0353a 56 #define SYSPLLCLKSEL_SEL_SHIFT 0
tushki7 0:60d829a0353a 57
tushki7 0:60d829a0353a 58 /* SYSPLLCLKUEN, address 0x4004 8044 */
tushki7 0:60d829a0353a 59 #define SYSPLLCLKUEN_ENA (1 << 0) // Enable system PLL clock source update
tushki7 0:60d829a0353a 60
tushki7 0:60d829a0353a 61 /* MAINCLKSEL, address 0x4004 8070 */
tushki7 0:60d829a0353a 62 #define MAINCLKSEL_SEL_MASK 0x0003 // Clock source for main clock
tushki7 0:60d829a0353a 63 #define MAINCLKSEL_SEL_SHIFT 0
tushki7 0:60d829a0353a 64
tushki7 0:60d829a0353a 65 /* MAINCLKUEN, address 0x4004 8074 */
tushki7 0:60d829a0353a 66 #define MAINCLKUEN_ENA (1 << 0) // Enable main clock source update 0
tushki7 0:60d829a0353a 67
tushki7 0:60d829a0353a 68 /* SYSAHBCLKDIV, address 0x4004 8078 */
tushki7 0:60d829a0353a 69 #define SYSAHBCLKDIV_DIV_MASK 0x00FF // System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
tushki7 0:60d829a0353a 70 #define SYSAHBCLKDIV_DIV_SHIFT 0
tushki7 0:60d829a0353a 71
tushki7 0:60d829a0353a 72 /* SYSAHBCLKCTRL, address 0x4004 8080 */
tushki7 0:60d829a0353a 73 #define SYSAHBCLKCTRL_SYS (1 << 0) // Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.
tushki7 0:60d829a0353a 74 #define SYSAHBCLKCTRL_ROM (1 << 1) // Enables clock for ROM.
tushki7 0:60d829a0353a 75 #define SYSAHBCLKCTRL_RAM (1 << 2) // Enables clock for RAM.
tushki7 0:60d829a0353a 76 #define SYSAHBCLKCTRL_FLASHREG (1 << 3) // Enables clock for flash register interface.
tushki7 0:60d829a0353a 77 #define SYSAHBCLKCTRL_FLASHARRAY (1 << 4) // Enables clock for flash array access.
tushki7 0:60d829a0353a 78 #define SYSAHBCLKCTRL_I2C (1 << 5) // Enables clock for I2C.
tushki7 0:60d829a0353a 79 #define SYSAHBCLKCTRL_GPIO (1 << 6) // Enables clock for GPIO.
tushki7 0:60d829a0353a 80 #define SYSAHBCLKCTRL_CT16B0 (1 << 7) // Enables clock for 16-bit counter/timer 0.
tushki7 0:60d829a0353a 81 #define SYSAHBCLKCTRL_CT16B1 (1 << 8) // Enables clock for 16-bit counter/timer 1.
tushki7 0:60d829a0353a 82 #define SYSAHBCLKCTRL_CT32B0 (1 << 9) // Enables clock for 32-bit counter/timer 0.
tushki7 0:60d829a0353a 83 #define SYSAHBCLKCTRL_CT32B1 (1 << 10) // Enables clock for 32-bit counter/timer 1.
tushki7 0:60d829a0353a 84 #define SYSAHBCLKCTRL_SSP0 (1 << 11) // Enables clock for SPI0.
tushki7 0:60d829a0353a 85 #define SYSAHBCLKCTRL_UART (1 << 12) // Enables clock for UART. See Section 3.1 for part specific details.
tushki7 0:60d829a0353a 86 #define SYSAHBCLKCTRL_ADC (1 << 13) // Enables clock for ADC.
tushki7 0:60d829a0353a 87 #define SYSAHBCLKCTRL_WDT (1 << 15) // Enables clock for WDT.
tushki7 0:60d829a0353a 88 #define SYSAHBCLKCTRL_IOCON (1 << 16) // Enables clock for I/O configuration block.
tushki7 0:60d829a0353a 89 #define SYSAHBCLKCTRL_CAN (1 << 17) // Enables clock for C_CAN. See Section 3.1 for part specific details.
tushki7 0:60d829a0353a 90 #define SYSAHBCLKCTRL_SSP1 (1 << 18) // Enables clock for SPI1.
tushki7 0:60d829a0353a 91
tushki7 0:60d829a0353a 92 /* SSP0CLKDIV, address 0x4004 8094 */
tushki7 0:60d829a0353a 93 #define SSP0CLKDIV_DIV_MASK 0x00FF // SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255.
tushki7 0:60d829a0353a 94 #define SSP0CLKDIV_DIV_SHIFT 0
tushki7 0:60d829a0353a 95
tushki7 0:60d829a0353a 96 /* UARTCLKDIV, address 0x4004 8098 */
tushki7 0:60d829a0353a 97 #define UARTCLKDIV_DIV_MASK 0x00FF // UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.
tushki7 0:60d829a0353a 98 #define UARTCLKDIV_DIV_SHIFT 0
tushki7 0:60d829a0353a 99
tushki7 0:60d829a0353a 100 /* SSP1CLKDIV, address 0x4004 809C */
tushki7 0:60d829a0353a 101 #define SSP1CLKDIV_DIV_MASK 0x00FF // SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255.
tushki7 0:60d829a0353a 102 #define SSP1CLKDIV_DIV_SHIFT 0
tushki7 0:60d829a0353a 103
tushki7 0:60d829a0353a 104 /* WDTCLKSEL, address 0x4004 80D0 */
tushki7 0:60d829a0353a 105 #define WDTCLKSEL_SEL_MASK 0x0003 // WDT clock source
tushki7 0:60d829a0353a 106 #define WDTCLKSEL_SEL_SHIFT 0
tushki7 0:60d829a0353a 107
tushki7 0:60d829a0353a 108 /* WDTCLKUEN, address 0x4004 80D4 */
tushki7 0:60d829a0353a 109 #define WDTCLKUEN_ENA (1 << 0) // Enable WDT clock source update
tushki7 0:60d829a0353a 110
tushki7 0:60d829a0353a 111 /* WDTCLKDIV, address 0x4004 80D8 */
tushki7 0:60d829a0353a 112 #define WDTCLKDIV_DIV_MASK 0x00FF // WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255.
tushki7 0:60d829a0353a 113 #define WDTCLKDIV_DIV_SHIFT 0
tushki7 0:60d829a0353a 114
tushki7 0:60d829a0353a 115 /* CLKOUTCLKSEL, address 0x4004 80E0 */
tushki7 0:60d829a0353a 116 #define CLKOUTCLKSEL_SEL_MASK 0x0003 // CLKOUT clock source
tushki7 0:60d829a0353a 117 #define CLKOUTCLKSEL_SEL_SHIFT 0
tushki7 0:60d829a0353a 118
tushki7 0:60d829a0353a 119 /* CLKOUTUEN, address 0x4004 80E4 */
tushki7 0:60d829a0353a 120 #define CLKOUTUEN_ENA (1 << 0) // Enable CLKOUT clock source update 0
tushki7 0:60d829a0353a 121
tushki7 0:60d829a0353a 122 /* CLKOUTCLKDIV, address 0x4004 80E8 */
tushki7 0:60d829a0353a 123 #define CLKOUTCLKDIV_DIV_MASK 0x00FF // Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255.
tushki7 0:60d829a0353a 124 #define CLKOUTCLKDIV_DIV_SHIFT 0
tushki7 0:60d829a0353a 125
tushki7 0:60d829a0353a 126 /* PIOPORCAP0, address 0x4004 8100 */
tushki7 0:60d829a0353a 127 #define PIOPORCAP0_CAPPIO0_N_MASK 0x0FFF // Raw reset status input PIO0_n: PIO0_11 to PIO0_0
tushki7 0:60d829a0353a 128 #define PIOPORCAP0_CAPPIO0_N_SHIFT 0
tushki7 0:60d829a0353a 129 #define PIOPORCAP0_CAPPIO1_N_MASK 0xFFF000 // Raw reset status input PIO1_n: PIO1_11 to PIO1_0
tushki7 0:60d829a0353a 130 #define PIOPORCAP0_CAPPIO1_N_SHIFT 12
tushki7 0:60d829a0353a 131 #define PIOPORCAP0_CAPPIO2_N_MASK 0xFF000000 // Raw reset status input PIO2_n: PIO2_7 to PIO2_0
tushki7 0:60d829a0353a 132 #define PIOPORCAP0_CAPPIO2_N_SHIFT 24
tushki7 0:60d829a0353a 133
tushki7 0:60d829a0353a 134 /* PIOPORCAP1, address 0x4004 8104 */
tushki7 0:60d829a0353a 135 #define PIOPORCAP1_CAPPIO2_8 (1 << 0) // Raw reset status input PIO2_8
tushki7 0:60d829a0353a 136 #define PIOPORCAP1_CAPPIO2_9 (1 << 1) // Raw reset status input PIO2_9
tushki7 0:60d829a0353a 137 #define PIOPORCAP1_CAPPIO2_10 (1 << 2) // Raw reset status input PIO2_10
tushki7 0:60d829a0353a 138 #define PIOPORCAP1_CAPPIO2_11 (1 << 3) // Raw reset status input PIO2_11
tushki7 0:60d829a0353a 139 #define PIOPORCAP1_CAPPIO3_0 (1 << 4) // Raw reset status input PIO3_0
tushki7 0:60d829a0353a 140 #define PIOPORCAP1_CAPPIO3_1 (1 << 5) // Raw reset status input PIO3_1
tushki7 0:60d829a0353a 141 #define PIOPORCAP1_CAPPIO3_2 (1 << 6) // Raw reset status input PIO3_2
tushki7 0:60d829a0353a 142 #define PIOPORCAP1_CAPPIO3_3 (1 << 7) // Raw reset status input PIO3_3
tushki7 0:60d829a0353a 143 #define PIOPORCAP1_CAPPIO3_4 (1 << 8) // Raw reset status input PIO3_4
tushki7 0:60d829a0353a 144 #define PIOPORCAP1_CAPPIO3_5 (1 << 9) // Raw reset status input PIO3_5
tushki7 0:60d829a0353a 145
tushki7 0:60d829a0353a 146 /* BODCTRL, address 0x4004 8150 */
tushki7 0:60d829a0353a 147 #define BODCTRL_BODRSTLEV_MASK 0x0003 // BOD reset level
tushki7 0:60d829a0353a 148 #define BODCTRL_BODRSTLEV_SHIFT 0
tushki7 0:60d829a0353a 149 #define BODCTRL_BODINTVAL_MASK 0x000C // BOD interrupt level
tushki7 0:60d829a0353a 150 #define BODCTRL_BODINTVAL_SHIFT 2
tushki7 0:60d829a0353a 151 #define BODCTRL_BODRSTENA (1 << 4) // BOD reset enable
tushki7 0:60d829a0353a 152
tushki7 0:60d829a0353a 153 /* SYSTCKCAL, address 0x4004 8154 */
tushki7 0:60d829a0353a 154 #define SYSTCKCAL_CAL_MASK 0x3FFFFFF // System tick timer calibration value
tushki7 0:60d829a0353a 155 #define SYSTCKCAL_CAL_SHIFT 0
tushki7 0:60d829a0353a 156
tushki7 0:60d829a0353a 157 /* NMISRC, address 0x4004 8174 */
tushki7 0:60d829a0353a 158 #define NMISRC_IRQNO_MASK 0x001F // The IRQ number of the interrupt that acts as the Non-Maskable Interrupt 0 (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers.
tushki7 0:60d829a0353a 159 #define NMISRC_IRQNO_SHIFT 0
tushki7 0:60d829a0353a 160 #define NMISRC_NMIEN (1 << 31) // Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.
tushki7 0:60d829a0353a 161
tushki7 0:60d829a0353a 162 /* STARTAPRP0, address 0x4004 8200 */
tushki7 0:60d829a0353a 163 #define STARTAPRP0_APRPIO0_N_MASK 0x0FFF // Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge
tushki7 0:60d829a0353a 164 #define STARTAPRP0_APRPIO0_N_SHIFT 0
tushki7 0:60d829a0353a 165 #define STARTAPRP0_APRPIO1_0 (1 << 12) // Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge Reserved. Do not write a 1 to reserved bits in this register.
tushki7 0:60d829a0353a 166
tushki7 0:60d829a0353a 167 /* STARTERP0, address 0x4004 8204 */
tushki7 0:60d829a0353a 168 #define STARTERP0_ERPIO0_N_MASK 0x0FFF // Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled
tushki7 0:60d829a0353a 169 #define STARTERP0_ERPIO0_N_SHIFT 0
tushki7 0:60d829a0353a 170 #define STARTERP0_ERPIO1_0 (1 << 12) // Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled Reserved. Do not write a 1 to reserved bits in this register.
tushki7 0:60d829a0353a 171
tushki7 0:60d829a0353a 172 /* STARTRSRP0CLR, address 0x4004 8208 */
tushki7 0:60d829a0353a 173 #define STARTRSRP0CLR_RSRPIO0_N_MASK 0x0FFF // Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
tushki7 0:60d829a0353a 174 #define STARTRSRP0CLR_RSRPIO0_N_SHIFT 0
tushki7 0:60d829a0353a 175 #define STARTRSRP0CLR_RSRPIO1_0 (1 << 12) // Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
tushki7 0:60d829a0353a 176
tushki7 0:60d829a0353a 177 /* STARTSRP0, address 0x4004 820C */
tushki7 0:60d829a0353a 178 #define STARTSRP0_SRPIO0_N_MASK 0x0FFF // Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.
tushki7 0:60d829a0353a 179 #define STARTSRP0_SRPIO0_N_SHIFT 0
tushki7 0:60d829a0353a 180 #define STARTSRP0_SRPIO1_0 (1 << 12) // Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending.
tushki7 0:60d829a0353a 181
tushki7 0:60d829a0353a 182 /* PDSLEEPCFG, address 0x4004 8230 */
tushki7 0:60d829a0353a 183 #define PDSLEEPCFG_BOD_PD (1 << 3) // BOD power-down control in Deep-sleep mode, see Table 40.
tushki7 0:60d829a0353a 184 #define PDSLEEPCFG_WDTOSC_PD (1 << 6) // Watchdog oscillator power control in Deep-sleep mode, see Table 40.
tushki7 0:60d829a0353a 185
tushki7 0:60d829a0353a 186 /* PDAWAKECFG, address 0x4004 8234 */
tushki7 0:60d829a0353a 187 #define PDAWAKECFG_IRCOUT_PD (1 << 0) // IRC oscillator output wake-up configuration
tushki7 0:60d829a0353a 188 #define PDAWAKECFG_IRC_PD (1 << 1) // IRC oscillator power-down wake-up configuration
tushki7 0:60d829a0353a 189 #define PDAWAKECFG_FLASH_PD (1 << 2) // Flash wake-up configuration
tushki7 0:60d829a0353a 190 #define PDAWAKECFG_BOD_PD (1 << 3) // BOD wake-up configuration
tushki7 0:60d829a0353a 191 #define PDAWAKECFG_ADC_PD (1 << 4) // ADC wake-up configuration
tushki7 0:60d829a0353a 192 #define PDAWAKECFG_SYSOSC_PD (1 << 5) // System oscillator wake-up configuration
tushki7 0:60d829a0353a 193 #define PDAWAKECFG_WDTOSC_PD (1 << 6) // Watchdog oscillator wake-up configuration
tushki7 0:60d829a0353a 194 #define PDAWAKECFG_SYSPLL_PD (1 << 7) // System PLL wake-up configuration
tushki7 0:60d829a0353a 195
tushki7 0:60d829a0353a 196 /* PDRUNCFG, address 0x4004 8238 */
tushki7 0:60d829a0353a 197 #define PDRUNCFG_IRCOUT_PD (1 << 0) // IRC oscillator output power-down
tushki7 0:60d829a0353a 198 #define PDRUNCFG_IRC_PD (1 << 1) // IRC oscillator power-down
tushki7 0:60d829a0353a 199 #define PDRUNCFG_FLASH_PD (1 << 2) // Flash power-down
tushki7 0:60d829a0353a 200 #define PDRUNCFG_BOD_PD (1 << 3) // BOD power-down
tushki7 0:60d829a0353a 201 #define PDRUNCFG_ADC_PD (1 << 4) // ADC power-down
tushki7 0:60d829a0353a 202 #define PDRUNCFG_SYSOSC_PD (1 << 5) // System oscillator power-down
tushki7 0:60d829a0353a 203 #define PDRUNCFG_WDTOSC_PD (1 << 6) // Watchdog oscillator power-down
tushki7 0:60d829a0353a 204 #define PDRUNCFG_SYSPLL_PD (1 << 7) // System PLL power-down
tushki7 0:60d829a0353a 205
tushki7 0:60d829a0353a 206 /* DEVICE_ID, address 0x4004 83F4 */
tushki7 0:60d829a0353a 207 #define DEVICE_ID_DEVICEID_MASK 0xFFFFFFFF // Part ID numbers for LPC111x/LPC11Cxx parts
tushki7 0:60d829a0353a 208 #define DEVICE_ID_DEVICEID_SHIFT 0
tushki7 0:60d829a0353a 209
tushki7 0:60d829a0353a 210 /* FLASHCFG, address 0x4003 C010 */
tushki7 0:60d829a0353a 211 #define FLASHCFG_FLASHTIM_MASK 0x0003 // Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
tushki7 0:60d829a0353a 212 #define FLASHCFG_FLASHTIM_SHIFT 0
tushki7 0:60d829a0353a 213
tushki7 0:60d829a0353a 214 /* PCON, address 0x4003 8000 */
tushki7 0:60d829a0353a 215 #define PCON_DPDEN (1 << 1) // Deep power-down mode enable
tushki7 0:60d829a0353a 216 #define PCON_SLEEPFLAG (1 << 8) // Sleep mode flag
tushki7 0:60d829a0353a 217 #define PCON_DPDFLAG (1 << 11) // Deep power-down flag
tushki7 0:60d829a0353a 218
tushki7 0:60d829a0353a 219 /* GPREG0 - GPREG3, address 0x4003 8004 to 0x4003 8010 */
tushki7 0:60d829a0353a 220 #define GPREGn_GPDATA_MASK 0xFFFFFFFF // Data retained during Deep power-down mode.
tushki7 0:60d829a0353a 221 #define GPREGn_GPDATA_SHIFT 0
tushki7 0:60d829a0353a 222
tushki7 0:60d829a0353a 223 /* GPREG4, address 0x4003 8014 */
tushki7 0:60d829a0353a 224 #define GPREG4_WAKEUPHYS (1 << 10) // WAKEUP pin hysteresis enable
tushki7 0:60d829a0353a 225 #define GPREG4_GPDATA_MASK 0xFFFFF800 // Data retained during Deep power-down mode.
tushki7 0:60d829a0353a 226 #define GPREG4_GPDATA_SHIFT 11
tushki7 0:60d829a0353a 227
tushki7 0:60d829a0353a 228 /* IOCON_PIO2_6, address 0x4004 4000 */
tushki7 0:60d829a0353a 229 #define IOCON_PIO2_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 230 #define IOCON_PIO2_6_FUNC_SHIFT 0
tushki7 0:60d829a0353a 231 #define IOCON_PIO2_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 232 #define IOCON_PIO2_6_MODE_SHIFT 3
tushki7 0:60d829a0353a 233 #define IOCON_PIO2_6_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 234 #define IOCON_PIO2_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 235
tushki7 0:60d829a0353a 236 /* IOCON_PIO2_0, address 0x4004 4008 */
tushki7 0:60d829a0353a 237 #define IOCON_PIO2_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 238 #define IOCON_PIO2_0_FUNC_SHIFT 0
tushki7 0:60d829a0353a 239 #define IOCON_PIO2_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 240 #define IOCON_PIO2_0_MODE_SHIFT 3
tushki7 0:60d829a0353a 241 #define IOCON_PIO2_0_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 242 #define IOCON_PIO2_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 243
tushki7 0:60d829a0353a 244 /* IOCON_RESET_PIO0_0, address 0x4004 400C */
tushki7 0:60d829a0353a 245 #define IOCON_RESET_PIO0_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 246 #define IOCON_RESET_PIO0_0_FUNC_SHIFT 0
tushki7 0:60d829a0353a 247 #define IOCON_RESET_PIO0_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 248 #define IOCON_RESET_PIO0_0_MODE_SHIFT 3
tushki7 0:60d829a0353a 249 #define IOCON_RESET_PIO0_0_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 250 #define IOCON_RESET_PIO0_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 251
tushki7 0:60d829a0353a 252 /* IOCON_PIO0_1, address 0x4004 4010 */
tushki7 0:60d829a0353a 253 #define IOCON_PIO0_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 254 #define IOCON_PIO0_1_FUNC_SHIFT 0
tushki7 0:60d829a0353a 255 #define IOCON_PIO0_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 256 #define IOCON_PIO0_1_MODE_SHIFT 3
tushki7 0:60d829a0353a 257 #define IOCON_PIO0_1_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 258 #define IOCON_PIO0_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 259
tushki7 0:60d829a0353a 260 /* IOCON_PIO1_8, address 0x4004 4014 */
tushki7 0:60d829a0353a 261 #define IOCON_PIO1_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 262 #define IOCON_PIO1_8_FUNC_SHIFT 0
tushki7 0:60d829a0353a 263 #define IOCON_PIO1_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 264 #define IOCON_PIO1_8_MODE_SHIFT 3
tushki7 0:60d829a0353a 265 #define IOCON_PIO1_8_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 266 #define IOCON_PIO1_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 267
tushki7 0:60d829a0353a 268 /* IOCON_PIO0_2, address 0x4004 401C */
tushki7 0:60d829a0353a 269 #define IOCON_PIO0_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 270 #define IOCON_PIO0_2_FUNC_SHIFT 0
tushki7 0:60d829a0353a 271 #define IOCON_PIO0_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 272 #define IOCON_PIO0_2_MODE_SHIFT 3
tushki7 0:60d829a0353a 273 #define IOCON_PIO0_2_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 274 #define IOCON_PIO0_2_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 275
tushki7 0:60d829a0353a 276 /* IOCON_PIO2_7, address 0x4004 4020 */
tushki7 0:60d829a0353a 277 #define IOCON_PIO2_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 278 #define IOCON_PIO2_7_FUNC_SHIFT 0
tushki7 0:60d829a0353a 279 #define IOCON_PIO2_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 280 #define IOCON_PIO2_7_MODE_SHIFT 3
tushki7 0:60d829a0353a 281 #define IOCON_PIO2_7_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 282 #define IOCON_PIO2_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 283
tushki7 0:60d829a0353a 284 /* IOCON_PIO2_8, address 0x4004 4024 */
tushki7 0:60d829a0353a 285 #define IOCON_PIO2_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 286 #define IOCON_PIO2_8_FUNC_SHIFT 0
tushki7 0:60d829a0353a 287 #define IOCON_PIO2_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 288 #define IOCON_PIO2_8_MODE_SHIFT 3
tushki7 0:60d829a0353a 289 #define IOCON_PIO2_8_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 290 #define IOCON_PIO2_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 291
tushki7 0:60d829a0353a 292 /* IOCON_PIO2_1, address 0x4004 4028 */
tushki7 0:60d829a0353a 293 #define IOCON_PIO2_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 294 #define IOCON_PIO2_1_FUNC_SHIFT 0
tushki7 0:60d829a0353a 295 #define IOCON_PIO2_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 296 #define IOCON_PIO2_1_MODE_SHIFT 3
tushki7 0:60d829a0353a 297 #define IOCON_PIO2_1_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 298 #define IOCON_PIO2_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 299
tushki7 0:60d829a0353a 300 /* IOCON_PIO0_3, address 0x4004 402C */
tushki7 0:60d829a0353a 301 #define IOCON_PIO0_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 302 #define IOCON_PIO0_3_FUNC_SHIFT 0
tushki7 0:60d829a0353a 303 #define IOCON_PIO0_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 304 #define IOCON_PIO0_3_MODE_SHIFT 3
tushki7 0:60d829a0353a 305 #define IOCON_PIO0_3_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 306 #define IOCON_PIO0_3_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 307
tushki7 0:60d829a0353a 308 /* IOCON_PIO0_4, address 0x4004 4030 */
tushki7 0:60d829a0353a 309 #define IOCON_PIO0_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 310 #define IOCON_PIO0_4_FUNC_SHIFT 0
tushki7 0:60d829a0353a 311 #define IOCON_PIO0_4_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
tushki7 0:60d829a0353a 312 #define IOCON_PIO0_4_I2CMODE_SHIFT 8
tushki7 0:60d829a0353a 313
tushki7 0:60d829a0353a 314 /* IOCON_PIO0_5, address 0x4004 4034 */
tushki7 0:60d829a0353a 315 #define IOCON_PIO0_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 316 #define IOCON_PIO0_5_FUNC_SHIFT 0
tushki7 0:60d829a0353a 317 #define IOCON_PIO0_5_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
tushki7 0:60d829a0353a 318 #define IOCON_PIO0_5_I2CMODE_SHIFT 8
tushki7 0:60d829a0353a 319
tushki7 0:60d829a0353a 320 /* IOCON_PIO1_9, address 0x4004 4038 */
tushki7 0:60d829a0353a 321 #define IOCON_PIO1_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 322 #define IOCON_PIO1_9_FUNC_SHIFT 0
tushki7 0:60d829a0353a 323 #define IOCON_PIO1_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 324 #define IOCON_PIO1_9_MODE_SHIFT 3
tushki7 0:60d829a0353a 325 #define IOCON_PIO1_9_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 326 #define IOCON_PIO1_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 327
tushki7 0:60d829a0353a 328 /* IOCON_PIO3_4, address 0x4004 403C */
tushki7 0:60d829a0353a 329 #define IOCON_PIO3_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 330 #define IOCON_PIO3_4_FUNC_SHIFT 0
tushki7 0:60d829a0353a 331 #define IOCON_PIO3_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 332 #define IOCON_PIO3_4_MODE_SHIFT 3
tushki7 0:60d829a0353a 333 #define IOCON_PIO3_4_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 334 #define IOCON_PIO3_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 335
tushki7 0:60d829a0353a 336 /* IOCON_PIO2_4, address 0x4004 4040 */
tushki7 0:60d829a0353a 337 #define IOCON_PIO2_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 338 #define IOCON_PIO2_4_FUNC_SHIFT 0
tushki7 0:60d829a0353a 339 #define IOCON_PIO2_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 340 #define IOCON_PIO2_4_MODE_SHIFT 3
tushki7 0:60d829a0353a 341 #define IOCON_PIO2_4_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 342 #define IOCON_PIO2_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 343
tushki7 0:60d829a0353a 344 /* IOCON_PIO2_5, address 0x4004 4044 */
tushki7 0:60d829a0353a 345 #define IOCON_PIO2_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 346 #define IOCON_PIO2_5_FUNC_SHIFT 0
tushki7 0:60d829a0353a 347 #define IOCON_PIO2_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 348 #define IOCON_PIO2_5_MODE_SHIFT 3
tushki7 0:60d829a0353a 349 #define IOCON_PIO2_5_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 350 #define IOCON_PIO2_5_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 351
tushki7 0:60d829a0353a 352 /* IOCON_PIO3_5, address 0x4004 4048 */
tushki7 0:60d829a0353a 353 #define IOCON_PIO3_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 354 #define IOCON_PIO3_5_FUNC_SHIFT 0
tushki7 0:60d829a0353a 355 #define IOCON_PIO3_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 356 #define IOCON_PIO3_5_MODE_SHIFT 3
tushki7 0:60d829a0353a 357 #define IOCON_PIO3_5_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 358 #define IOCON_PIO3_5_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 359
tushki7 0:60d829a0353a 360 /* IOCON_PIO0_6, address 0x4004 404C */
tushki7 0:60d829a0353a 361 #define IOCON_PIO0_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 362 #define IOCON_PIO0_6_FUNC_SHIFT 0
tushki7 0:60d829a0353a 363 #define IOCON_PIO0_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 364 #define IOCON_PIO0_6_MODE_SHIFT 3
tushki7 0:60d829a0353a 365 #define IOCON_PIO0_6_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 366 #define IOCON_PIO0_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 367
tushki7 0:60d829a0353a 368 /* IOCON_PIO0_7, address 0x4004 4050 */
tushki7 0:60d829a0353a 369 #define IOCON_PIO0_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 370 #define IOCON_PIO0_7_FUNC_SHIFT 0
tushki7 0:60d829a0353a 371 #define IOCON_PIO0_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 372 #define IOCON_PIO0_7_MODE_SHIFT 3
tushki7 0:60d829a0353a 373 #define IOCON_PIO0_7_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 374 #define IOCON_PIO0_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 375
tushki7 0:60d829a0353a 376 /* IOCON_PIO2_9, address 0x4004 4054 */
tushki7 0:60d829a0353a 377 #define IOCON_PIO2_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 378 #define IOCON_PIO2_9_FUNC_SHIFT 0
tushki7 0:60d829a0353a 379 #define IOCON_PIO2_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 380 #define IOCON_PIO2_9_MODE_SHIFT 3
tushki7 0:60d829a0353a 381 #define IOCON_PIO2_9_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 382 #define IOCON_PIO2_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 383
tushki7 0:60d829a0353a 384 /* IOCON_PIO2_10, address 0x4004 4058 */
tushki7 0:60d829a0353a 385 #define IOCON_PIO2_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 386 #define IOCON_PIO2_10_FUNC_SHIFT 0
tushki7 0:60d829a0353a 387 #define IOCON_PIO2_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 388 #define IOCON_PIO2_10_MODE_SHIFT 3
tushki7 0:60d829a0353a 389 #define IOCON_PIO2_10_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 390 #define IOCON_PIO2_10_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 391
tushki7 0:60d829a0353a 392 /* IOCON_PIO2_2, address 0x4004 405C */
tushki7 0:60d829a0353a 393 #define IOCON_PIO2_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 394 #define IOCON_PIO2_2_FUNC_SHIFT 0
tushki7 0:60d829a0353a 395 #define IOCON_PIO2_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 396 #define IOCON_PIO2_2_MODE_SHIFT 3
tushki7 0:60d829a0353a 397 #define IOCON_PIO2_2_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 398 #define IOCON_PIO2_2_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 399
tushki7 0:60d829a0353a 400 /* IOCON_PIO0_8, address 0x4004 4060 */
tushki7 0:60d829a0353a 401 #define IOCON_PIO0_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 402 #define IOCON_PIO0_8_FUNC_SHIFT 0
tushki7 0:60d829a0353a 403 #define IOCON_PIO0_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 404 #define IOCON_PIO0_8_MODE_SHIFT 3
tushki7 0:60d829a0353a 405 #define IOCON_PIO0_8_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 406 #define IOCON_PIO0_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 407
tushki7 0:60d829a0353a 408 /* IOCON_PIO0_9, address 0x4004 4064 */
tushki7 0:60d829a0353a 409 #define IOCON_PIO0_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 410 #define IOCON_PIO0_9_FUNC_SHIFT 0
tushki7 0:60d829a0353a 411 #define IOCON_PIO0_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 412 #define IOCON_PIO0_9_MODE_SHIFT 3
tushki7 0:60d829a0353a 413 #define IOCON_PIO0_9_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 414 #define IOCON_PIO0_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 415
tushki7 0:60d829a0353a 416 /* IOCON_SWCLK_PIO0_10, address 0x4004 4068 */
tushki7 0:60d829a0353a 417 #define IOCON_SWCLK_PIO0_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 418 #define IOCON_SWCLK_PIO0_10_FUNC_SHIFT 0
tushki7 0:60d829a0353a 419 #define IOCON_SWCLK_PIO0_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 420 #define IOCON_SWCLK_PIO0_10_MODE_SHIFT 3
tushki7 0:60d829a0353a 421 #define IOCON_SWCLK_PIO0_10_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 422 #define IOCON_SWCLK_PIO0_10_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 423
tushki7 0:60d829a0353a 424 /* IOCON_PIO1_10, address 0x4004 406C */
tushki7 0:60d829a0353a 425 #define IOCON_PIO1_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 426 #define IOCON_PIO1_10_FUNC_SHIFT 0
tushki7 0:60d829a0353a 427 #define IOCON_PIO1_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 428 #define IOCON_PIO1_10_MODE_SHIFT 3
tushki7 0:60d829a0353a 429 #define IOCON_PIO1_10_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 430 #define IOCON_PIO1_10_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 431 #define IOCON_PIO1_10_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 432
tushki7 0:60d829a0353a 433 /* IOCON_PIO2_11, address 0x4004 4070 */
tushki7 0:60d829a0353a 434 #define IOCON_PIO2_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 435 #define IOCON_PIO2_11_FUNC_SHIFT 0
tushki7 0:60d829a0353a 436 #define IOCON_PIO2_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 437 #define IOCON_PIO2_11_MODE_SHIFT 3
tushki7 0:60d829a0353a 438 #define IOCON_PIO2_11_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 439 #define IOCON_PIO2_11_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 440
tushki7 0:60d829a0353a 441 /* IOCON_R_PIO0_11, address 0x4004 4074 */
tushki7 0:60d829a0353a 442 #define IOCON_R_PIO0_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 443 #define IOCON_R_PIO0_11_FUNC_SHIFT 0
tushki7 0:60d829a0353a 444 #define IOCON_R_PIO0_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 445 #define IOCON_R_PIO0_11_MODE_SHIFT 3
tushki7 0:60d829a0353a 446 #define IOCON_R_PIO0_11_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 447 #define IOCON_R_PIO0_11_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 448 #define IOCON_R_PIO0_11_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 449
tushki7 0:60d829a0353a 450 /* IOCON_R_PIO1_0, address 0x4004 4078 */
tushki7 0:60d829a0353a 451 #define IOCON_R_PIO1_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 452 #define IOCON_R_PIO1_0_FUNC_SHIFT 0
tushki7 0:60d829a0353a 453 #define IOCON_R_PIO1_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 454 #define IOCON_R_PIO1_0_MODE_SHIFT 3
tushki7 0:60d829a0353a 455 #define IOCON_R_PIO1_0_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 456 #define IOCON_R_PIO1_0_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 457 #define IOCON_R_PIO1_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 458
tushki7 0:60d829a0353a 459 /* IOCON_R_PIO1_1, address 0x4004 407C */
tushki7 0:60d829a0353a 460 #define IOCON_R_PIO1_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 461 #define IOCON_R_PIO1_1_FUNC_SHIFT 0
tushki7 0:60d829a0353a 462 #define IOCON_R_PIO1_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 463 #define IOCON_R_PIO1_1_MODE_SHIFT 3
tushki7 0:60d829a0353a 464 #define IOCON_R_PIO1_1_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 465 #define IOCON_R_PIO1_1_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 466 #define IOCON_R_PIO1_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 467
tushki7 0:60d829a0353a 468 /* IOCON_R_PIO1_2, address 0x4004 4080 */
tushki7 0:60d829a0353a 469 #define IOCON_R_PIO1_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 470 #define IOCON_R_PIO1_2_FUNC_SHIFT 0
tushki7 0:60d829a0353a 471 #define IOCON_R_PIO1_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 472 #define IOCON_R_PIO1_2_MODE_SHIFT 3
tushki7 0:60d829a0353a 473 #define IOCON_R_PIO1_2_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 474 #define IOCON_R_PIO1_2_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 475 #define IOCON_R_PIO1_2_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 476
tushki7 0:60d829a0353a 477 /* IOCON_PIO3_0, address 0x4004 4084 */
tushki7 0:60d829a0353a 478 #define IOCON_PIO3_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 479 #define IOCON_PIO3_0_FUNC_SHIFT 0
tushki7 0:60d829a0353a 480 #define IOCON_PIO3_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 481 #define IOCON_PIO3_0_MODE_SHIFT 3
tushki7 0:60d829a0353a 482 #define IOCON_PIO3_0_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 483 #define IOCON_PIO3_0_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 484
tushki7 0:60d829a0353a 485 /* IOCON_PIO3_1, address 0x4004 4088 */
tushki7 0:60d829a0353a 486 #define IOCON_PIO3_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 487 #define IOCON_PIO3_1_FUNC_SHIFT 0
tushki7 0:60d829a0353a 488 #define IOCON_PIO3_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 489 #define IOCON_PIO3_1_MODE_SHIFT 3
tushki7 0:60d829a0353a 490 #define IOCON_PIO3_1_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 491 #define IOCON_PIO3_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 492
tushki7 0:60d829a0353a 493 /* IOCON_PIO2_3, address 0x4004 408C */
tushki7 0:60d829a0353a 494 #define IOCON_PIO2_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 495 #define IOCON_PIO2_3_FUNC_SHIFT 0
tushki7 0:60d829a0353a 496 #define IOCON_PIO2_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 497 #define IOCON_PIO2_3_MODE_SHIFT 3
tushki7 0:60d829a0353a 498 #define IOCON_PIO2_3_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 499 #define IOCON_PIO2_3_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 500
tushki7 0:60d829a0353a 501 /* IOCON_SWDIO_PIO1_3, address 0x4004 4090 */
tushki7 0:60d829a0353a 502 #define IOCON_SWDIO_PIO1_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 503 #define IOCON_SWDIO_PIO1_3_FUNC_SHIFT 0
tushki7 0:60d829a0353a 504 #define IOCON_SWDIO_PIO1_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 505 #define IOCON_SWDIO_PIO1_3_MODE_SHIFT 3
tushki7 0:60d829a0353a 506 #define IOCON_SWDIO_PIO1_3_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 507 #define IOCON_SWDIO_PIO1_3_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 508 #define IOCON_SWDIO_PIO1_3_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 509
tushki7 0:60d829a0353a 510 /* IOCON_PIO1_4, address 0x4004 4094 */
tushki7 0:60d829a0353a 511 #define IOCON_PIO1_4_FUNC_MASK 0x0007 // Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
tushki7 0:60d829a0353a 512 #define IOCON_PIO1_4_FUNC_SHIFT 0
tushki7 0:60d829a0353a 513 #define IOCON_PIO1_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 514 #define IOCON_PIO1_4_MODE_SHIFT 3
tushki7 0:60d829a0353a 515 #define IOCON_PIO1_4_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 516 #define IOCON_PIO1_4_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 517 #define IOCON_PIO1_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 518
tushki7 0:60d829a0353a 519 /* IOCON_PIO1_11, address 0x4004 4098 */
tushki7 0:60d829a0353a 520 #define IOCON_PIO1_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 521 #define IOCON_PIO1_11_FUNC_SHIFT 0
tushki7 0:60d829a0353a 522 #define IOCON_PIO1_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 523 #define IOCON_PIO1_11_MODE_SHIFT 3
tushki7 0:60d829a0353a 524 #define IOCON_PIO1_11_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 525 #define IOCON_PIO1_11_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 526 #define IOCON_PIO1_11_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 527
tushki7 0:60d829a0353a 528 /* IOCON_PIO3_2, address 0x4004 409C */
tushki7 0:60d829a0353a 529 #define IOCON_PIO3_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 530 #define IOCON_PIO3_2_FUNC_SHIFT 0
tushki7 0:60d829a0353a 531 #define IOCON_PIO3_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 532 #define IOCON_PIO3_2_MODE_SHIFT 3
tushki7 0:60d829a0353a 533 #define IOCON_PIO3_2_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 534 #define IOCON_PIO3_2_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 535
tushki7 0:60d829a0353a 536 /* IOCON_PIO1_5, address 0x4004 40A0 */
tushki7 0:60d829a0353a 537 #define IOCON_PIO1_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 538 #define IOCON_PIO1_5_FUNC_SHIFT 0
tushki7 0:60d829a0353a 539 #define IOCON_PIO1_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 540 #define IOCON_PIO1_5_MODE_SHIFT 3
tushki7 0:60d829a0353a 541 #define IOCON_PIO1_5_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 542 #define IOCON_PIO1_5_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 543
tushki7 0:60d829a0353a 544 /* IOCON_PIO1_6, address 0x4004 40A4 */
tushki7 0:60d829a0353a 545 #define IOCON_PIO1_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 546 #define IOCON_PIO1_6_FUNC_SHIFT 0
tushki7 0:60d829a0353a 547 #define IOCON_PIO1_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 548 #define IOCON_PIO1_6_MODE_SHIFT 3
tushki7 0:60d829a0353a 549 #define IOCON_PIO1_6_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 550 #define IOCON_PIO1_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 551
tushki7 0:60d829a0353a 552 /* IOCON_PIO1_7, address 0x4004 40A8 */
tushki7 0:60d829a0353a 553 #define IOCON_PIO1_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 554 #define IOCON_PIO1_7_FUNC_SHIFT 0
tushki7 0:60d829a0353a 555 #define IOCON_PIO1_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 556 #define IOCON_PIO1_7_MODE_SHIFT 3
tushki7 0:60d829a0353a 557 #define IOCON_PIO1_7_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 558 #define IOCON_PIO1_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 559
tushki7 0:60d829a0353a 560 /* IOCON_PIO3_3, address 0x4004 40AC */
tushki7 0:60d829a0353a 561 #define IOCON_PIO3_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 562 #define IOCON_PIO3_3_FUNC_SHIFT 0
tushki7 0:60d829a0353a 563 #define IOCON_PIO3_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 564 #define IOCON_PIO3_3_MODE_SHIFT 3
tushki7 0:60d829a0353a 565 #define IOCON_PIO3_3_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 566 #define IOCON_PIO3_3_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
tushki7 0:60d829a0353a 567
tushki7 0:60d829a0353a 568 /* IOCON_SCK_LOC, address 0x4004 40B0 */
tushki7 0:60d829a0353a 569 #define IOCON_SCK_LOC_SCKLOC_MASK 0x0003 // Selects pin location for SCK0 function.
tushki7 0:60d829a0353a 570 #define IOCON_SCK_LOC_SCKLOC_SHIFT 0
tushki7 0:60d829a0353a 571
tushki7 0:60d829a0353a 572 /* IOCON_DSR_LOC, address 0x4004 40B4 */
tushki7 0:60d829a0353a 573 #define IOCON_DSR_LOC_DSRLOC_MASK 0x0003 // elects pin location for DSR function.
tushki7 0:60d829a0353a 574 #define IOCON_DSR_LOC_DSRLOC_SHIFT 0
tushki7 0:60d829a0353a 575
tushki7 0:60d829a0353a 576 /* IOCON_DCD_LOC, address 0x4004 40B8 */
tushki7 0:60d829a0353a 577 #define IOCON_DCD_LOC_DCDLOC_MASK 0x0003 // Selects pin location for DCD function.
tushki7 0:60d829a0353a 578 #define IOCON_DCD_LOC_DCDLOC_SHIFT 0
tushki7 0:60d829a0353a 579
tushki7 0:60d829a0353a 580 /* IOCON_RI_LOC, address 0x4004 40BC */
tushki7 0:60d829a0353a 581 #define IOCON_RI_LOC_RILOC_MASK 0x0003 // Selects pin location for RI function.
tushki7 0:60d829a0353a 582 #define IOCON_RI_LOC_RILOC_SHIFT 0
tushki7 0:60d829a0353a 583
tushki7 0:60d829a0353a 584 /* IOCON_PIO2_6, address 0x4004 4000 */
tushki7 0:60d829a0353a 585 #define IOCON_PIO2_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 586 #define IOCON_PIO2_6_FUNC_SHIFT 0
tushki7 0:60d829a0353a 587 #define IOCON_PIO2_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 588 #define IOCON_PIO2_6_MODE_SHIFT 3
tushki7 0:60d829a0353a 589 #define IOCON_PIO2_6_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 590 #define IOCON_PIO2_6_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 591
tushki7 0:60d829a0353a 592 /* IOCON_PIO2_0, address 0x4004 4008 */
tushki7 0:60d829a0353a 593 #define IOCON_PIO2_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 594 #define IOCON_PIO2_0_FUNC_SHIFT 0
tushki7 0:60d829a0353a 595 #define IOCON_PIO2_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 596 #define IOCON_PIO2_0_MODE_SHIFT 3
tushki7 0:60d829a0353a 597 #define IOCON_PIO2_0_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 598 #define IOCON_PIO2_0_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 599
tushki7 0:60d829a0353a 600 /* IOCON_RESET_PIO0_0, address 0x4004 400C */
tushki7 0:60d829a0353a 601 #define IOCON_RESET_PIO0_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 602 #define IOCON_RESET_PIO0_0_FUNC_SHIFT 0
tushki7 0:60d829a0353a 603 #define IOCON_RESET_PIO0_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 604 #define IOCON_RESET_PIO0_0_MODE_SHIFT 3
tushki7 0:60d829a0353a 605 #define IOCON_RESET_PIO0_0_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 606 #define IOCON_RESET_PIO0_0_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 607
tushki7 0:60d829a0353a 608 /* IOCON_PIO0_1, address 0x4004 4010 */
tushki7 0:60d829a0353a 609 #define IOCON_PIO0_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 610 #define IOCON_PIO0_1_FUNC_SHIFT 0
tushki7 0:60d829a0353a 611 #define IOCON_PIO0_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 612 #define IOCON_PIO0_1_MODE_SHIFT 3
tushki7 0:60d829a0353a 613 #define IOCON_PIO0_1_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 614 #define IOCON_PIO0_1_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 615
tushki7 0:60d829a0353a 616 /* IOCON_PIO1_8, address 0x4004 4014 */
tushki7 0:60d829a0353a 617 #define IOCON_PIO1_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 618 #define IOCON_PIO1_8_FUNC_SHIFT 0
tushki7 0:60d829a0353a 619 #define IOCON_PIO1_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 620 #define IOCON_PIO1_8_MODE_SHIFT 3
tushki7 0:60d829a0353a 621 #define IOCON_PIO1_8_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 622 #define IOCON_PIO1_8_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 623
tushki7 0:60d829a0353a 624 /* IOCON_PIO0_2, address 0x4004 401C */
tushki7 0:60d829a0353a 625 #define IOCON_PIO0_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 626 #define IOCON_PIO0_2_FUNC_SHIFT 0
tushki7 0:60d829a0353a 627 #define IOCON_PIO0_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 628 #define IOCON_PIO0_2_MODE_SHIFT 3
tushki7 0:60d829a0353a 629 #define IOCON_PIO0_2_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 630 #define IOCON_PIO0_2_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 631
tushki7 0:60d829a0353a 632 /* IOCON_PIO2_7, address 0x4004 4020 */
tushki7 0:60d829a0353a 633 #define IOCON_PIO2_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 634 #define IOCON_PIO2_7_FUNC_SHIFT 0
tushki7 0:60d829a0353a 635 #define IOCON_PIO2_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 636 #define IOCON_PIO2_7_MODE_SHIFT 3
tushki7 0:60d829a0353a 637 #define IOCON_PIO2_7_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 638 #define IOCON_PIO2_7_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 639
tushki7 0:60d829a0353a 640 /* IOCON_PIO2_8, address 0x4004 4024 */
tushki7 0:60d829a0353a 641 #define IOCON_PIO2_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 642 #define IOCON_PIO2_8_FUNC_SHIFT 0
tushki7 0:60d829a0353a 643 #define IOCON_PIO2_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 644 #define IOCON_PIO2_8_MODE_SHIFT 3
tushki7 0:60d829a0353a 645 #define IOCON_PIO2_8_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 646 #define IOCON_PIO2_8_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 647
tushki7 0:60d829a0353a 648 /* IOCON_PIO2_1, address 0x4004 4028 */
tushki7 0:60d829a0353a 649 #define IOCON_PIO2_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 650 #define IOCON_PIO2_1_FUNC_SHIFT 0
tushki7 0:60d829a0353a 651 #define IOCON_PIO2_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 652 #define IOCON_PIO2_1_MODE_SHIFT 3
tushki7 0:60d829a0353a 653 #define IOCON_PIO2_1_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 654 #define IOCON_PIO2_1_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 655
tushki7 0:60d829a0353a 656 /* IOCON_PIO0_3, address 0x4004 402C */
tushki7 0:60d829a0353a 657 #define IOCON_PIO0_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 658 #define IOCON_PIO0_3_FUNC_SHIFT 0
tushki7 0:60d829a0353a 659 #define IOCON_PIO0_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 660 #define IOCON_PIO0_3_MODE_SHIFT 3
tushki7 0:60d829a0353a 661 #define IOCON_PIO0_3_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 662 #define IOCON_PIO0_3_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 663
tushki7 0:60d829a0353a 664 /* IOCON_PIO0_4, address 0x4004 4030 */
tushki7 0:60d829a0353a 665 #define IOCON_PIO0_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 666 #define IOCON_PIO0_4_FUNC_SHIFT 0
tushki7 0:60d829a0353a 667 #define IOCON_PIO0_4_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
tushki7 0:60d829a0353a 668 #define IOCON_PIO0_4_I2CMODE_SHIFT 8
tushki7 0:60d829a0353a 669
tushki7 0:60d829a0353a 670 /* IOCON_PIO0_5, address 0x4004 4034 */
tushki7 0:60d829a0353a 671 #define IOCON_PIO0_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 672 #define IOCON_PIO0_5_FUNC_SHIFT 0
tushki7 0:60d829a0353a 673 #define IOCON_PIO0_5_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
tushki7 0:60d829a0353a 674 #define IOCON_PIO0_5_I2CMODE_SHIFT 8
tushki7 0:60d829a0353a 675
tushki7 0:60d829a0353a 676 /* IOCON_PIO1_9, address 0x4004 4038 */
tushki7 0:60d829a0353a 677 #define IOCON_PIO1_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 678 #define IOCON_PIO1_9_FUNC_SHIFT 0
tushki7 0:60d829a0353a 679 #define IOCON_PIO1_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 680 #define IOCON_PIO1_9_MODE_SHIFT 3
tushki7 0:60d829a0353a 681 #define IOCON_PIO1_9_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 682 #define IOCON_PIO1_9_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 683
tushki7 0:60d829a0353a 684 /* IOCON_PIO3_4, address 0x4004 403C */
tushki7 0:60d829a0353a 685 #define IOCON_PIO3_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 686 #define IOCON_PIO3_4_FUNC_SHIFT 0
tushki7 0:60d829a0353a 687 #define IOCON_PIO3_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 688 #define IOCON_PIO3_4_MODE_SHIFT 3
tushki7 0:60d829a0353a 689 #define IOCON_PIO3_4_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 690 #define IOCON_PIO3_4_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 691
tushki7 0:60d829a0353a 692 /* IOCON_PIO2_4, address 0x4004 4040 */
tushki7 0:60d829a0353a 693 #define IOCON_PIO2_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 694 #define IOCON_PIO2_4_FUNC_SHIFT 0
tushki7 0:60d829a0353a 695 #define IOCON_PIO2_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 696 #define IOCON_PIO2_4_MODE_SHIFT 3
tushki7 0:60d829a0353a 697 #define IOCON_PIO2_4_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 698 #define IOCON_PIO2_4_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 699
tushki7 0:60d829a0353a 700 /* IOCON_PIO2_5, address 0x4004 4044 */
tushki7 0:60d829a0353a 701 #define IOCON_PIO2_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 702 #define IOCON_PIO2_5_FUNC_SHIFT 0
tushki7 0:60d829a0353a 703 #define IOCON_PIO2_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 704 #define IOCON_PIO2_5_MODE_SHIFT 3
tushki7 0:60d829a0353a 705 #define IOCON_PIO2_5_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 706 #define IOCON_PIO2_5_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 707
tushki7 0:60d829a0353a 708 /* IOCON_PIO3_5, address 0x4004 4048 */
tushki7 0:60d829a0353a 709 #define IOCON_PIO3_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 710 #define IOCON_PIO3_5_FUNC_SHIFT 0
tushki7 0:60d829a0353a 711 #define IOCON_PIO3_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 712 #define IOCON_PIO3_5_MODE_SHIFT 3
tushki7 0:60d829a0353a 713 #define IOCON_PIO3_5_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 714 #define IOCON_PIO3_5_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 715
tushki7 0:60d829a0353a 716 /* IOCON_PIO0_6, address 0x4004 404C */
tushki7 0:60d829a0353a 717 #define IOCON_PIO0_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 718 #define IOCON_PIO0_6_FUNC_SHIFT 0
tushki7 0:60d829a0353a 719 #define IOCON_PIO0_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 720 #define IOCON_PIO0_6_MODE_SHIFT 3
tushki7 0:60d829a0353a 721 #define IOCON_PIO0_6_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 722 #define IOCON_PIO0_6_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 723
tushki7 0:60d829a0353a 724 /* IOCON_PIO0_7, address 0x4004 4050 */
tushki7 0:60d829a0353a 725 #define IOCON_PIO0_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 726 #define IOCON_PIO0_7_FUNC_SHIFT 0
tushki7 0:60d829a0353a 727 #define IOCON_PIO0_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 728 #define IOCON_PIO0_7_MODE_SHIFT 3
tushki7 0:60d829a0353a 729 #define IOCON_PIO0_7_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 730 #define IOCON_PIO0_7_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 731
tushki7 0:60d829a0353a 732 /* IOCON_PIO2_9, address 0x4004 4054 */
tushki7 0:60d829a0353a 733 #define IOCON_PIO2_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 734 #define IOCON_PIO2_9_FUNC_SHIFT 0
tushki7 0:60d829a0353a 735 #define IOCON_PIO2_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 736 #define IOCON_PIO2_9_MODE_SHIFT 3
tushki7 0:60d829a0353a 737 #define IOCON_PIO2_9_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 738 #define IOCON_PIO2_9_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 739
tushki7 0:60d829a0353a 740 /* IOCON_PIO2_10, address 0x4004 4058 */
tushki7 0:60d829a0353a 741 #define IOCON_PIO2_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 742 #define IOCON_PIO2_10_FUNC_SHIFT 0
tushki7 0:60d829a0353a 743 #define IOCON_PIO2_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 744 #define IOCON_PIO2_10_MODE_SHIFT 3
tushki7 0:60d829a0353a 745 #define IOCON_PIO2_10_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 746 #define IOCON_PIO2_10_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 747
tushki7 0:60d829a0353a 748 /* IOCON_PIO2_2, address 0x4004 405C */
tushki7 0:60d829a0353a 749 #define IOCON_PIO2_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 750 #define IOCON_PIO2_2_FUNC_SHIFT 0
tushki7 0:60d829a0353a 751 #define IOCON_PIO2_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 752 #define IOCON_PIO2_2_MODE_SHIFT 3
tushki7 0:60d829a0353a 753 #define IOCON_PIO2_2_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 754 #define IOCON_PIO2_2_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 755
tushki7 0:60d829a0353a 756 /* IOCON_PIO0_8, address 0x4004 4060 */
tushki7 0:60d829a0353a 757 #define IOCON_PIO0_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 758 #define IOCON_PIO0_8_FUNC_SHIFT 0
tushki7 0:60d829a0353a 759 #define IOCON_PIO0_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 760 #define IOCON_PIO0_8_MODE_SHIFT 3
tushki7 0:60d829a0353a 761 #define IOCON_PIO0_8_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 762 #define IOCON_PIO0_8_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 763
tushki7 0:60d829a0353a 764 /* IOCON_PIO0_9, address 0x4004 4064 */
tushki7 0:60d829a0353a 765 #define IOCON_PIO0_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 766 #define IOCON_PIO0_9_FUNC_SHIFT 0
tushki7 0:60d829a0353a 767 #define IOCON_PIO0_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 768 #define IOCON_PIO0_9_MODE_SHIFT 3
tushki7 0:60d829a0353a 769 #define IOCON_PIO0_9_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 770 #define IOCON_PIO0_9_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 771
tushki7 0:60d829a0353a 772 /* IOCON_SWCLK_PIO0_10, address 0x4004 4068 */
tushki7 0:60d829a0353a 773 #define IOCON_SWCLK_PIO0_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 774 #define IOCON_SWCLK_PIO0_10_FUNC_SHIFT 0
tushki7 0:60d829a0353a 775 #define IOCON_SWCLK_PIO0_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 776 #define IOCON_SWCLK_PIO0_10_MODE_SHIFT 3
tushki7 0:60d829a0353a 777 #define IOCON_SWCLK_PIO0_10_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 778 #define IOCON_SWCLK_PIO0_10_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 779
tushki7 0:60d829a0353a 780 /* IOCON_PIO1_10, address 0x4004 406C */
tushki7 0:60d829a0353a 781 #define IOCON_PIO1_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 782 #define IOCON_PIO1_10_FUNC_SHIFT 0
tushki7 0:60d829a0353a 783 #define IOCON_PIO1_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 784 #define IOCON_PIO1_10_MODE_SHIFT 3
tushki7 0:60d829a0353a 785 #define IOCON_PIO1_10_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 786 #define IOCON_PIO1_10_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 787 #define IOCON_PIO1_10_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 788
tushki7 0:60d829a0353a 789 /* IOCON_PIO2_11, address 0x4004 4070 */
tushki7 0:60d829a0353a 790 #define IOCON_PIO2_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 791 #define IOCON_PIO2_11_FUNC_SHIFT 0
tushki7 0:60d829a0353a 792 #define IOCON_PIO2_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 793 #define IOCON_PIO2_11_MODE_SHIFT 3
tushki7 0:60d829a0353a 794 #define IOCON_PIO2_11_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 795 #define IOCON_PIO2_11_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 796
tushki7 0:60d829a0353a 797 /* IOCON_R_PIO0_11, address 0x4004 4074 */
tushki7 0:60d829a0353a 798 #define IOCON_R_PIO0_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 799 #define IOCON_R_PIO0_11_FUNC_SHIFT 0
tushki7 0:60d829a0353a 800 #define IOCON_R_PIO0_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 801 #define IOCON_R_PIO0_11_MODE_SHIFT 3
tushki7 0:60d829a0353a 802 #define IOCON_R_PIO0_11_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 803 #define IOCON_R_PIO0_11_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 804 #define IOCON_R_PIO0_11_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 805
tushki7 0:60d829a0353a 806 /* IOCON_R_PIO1_0, address 0x4004 4078 */
tushki7 0:60d829a0353a 807 #define IOCON_R_PIO1_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 808 #define IOCON_R_PIO1_0_FUNC_SHIFT 0
tushki7 0:60d829a0353a 809 #define IOCON_R_PIO1_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 810 #define IOCON_R_PIO1_0_MODE_SHIFT 3
tushki7 0:60d829a0353a 811 #define IOCON_R_PIO1_0_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 812 #define IOCON_R_PIO1_0_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 813 #define IOCON_R_PIO1_0_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 814
tushki7 0:60d829a0353a 815 /* IOCON_R_PIO1_1, address 0x4004 407C */
tushki7 0:60d829a0353a 816 #define IOCON_R_PIO1_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 817 #define IOCON_R_PIO1_1_FUNC_SHIFT 0
tushki7 0:60d829a0353a 818 #define IOCON_R_PIO1_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 819 #define IOCON_R_PIO1_1_MODE_SHIFT 3
tushki7 0:60d829a0353a 820 #define IOCON_R_PIO1_1_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 821 #define IOCON_R_PIO1_1_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 822 #define IOCON_R_PIO1_1_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 823
tushki7 0:60d829a0353a 824 /* IOCON_R_PIO1_2, address 0x4004 4080 */
tushki7 0:60d829a0353a 825 #define IOCON_R_PIO1_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 826 #define IOCON_R_PIO1_2_FUNC_SHIFT 0
tushki7 0:60d829a0353a 827 #define IOCON_R_PIO1_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 828 #define IOCON_R_PIO1_2_MODE_SHIFT 3
tushki7 0:60d829a0353a 829 #define IOCON_R_PIO1_2_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 830 #define IOCON_R_PIO1_2_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 831 #define IOCON_R_PIO1_2_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 832
tushki7 0:60d829a0353a 833 /* IOCON_PIO3_0, address 0x4004 4084 */
tushki7 0:60d829a0353a 834 #define IOCON_PIO3_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 835 #define IOCON_PIO3_0_FUNC_SHIFT 0
tushki7 0:60d829a0353a 836 #define IOCON_PIO3_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 837 #define IOCON_PIO3_0_MODE_SHIFT 3
tushki7 0:60d829a0353a 838 #define IOCON_PIO3_0_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 839 #define IOCON_PIO3_0_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 840
tushki7 0:60d829a0353a 841 /* IOCON_PIO3_1, address 0x4004 4088 */
tushki7 0:60d829a0353a 842 #define IOCON_PIO3_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 843 #define IOCON_PIO3_1_FUNC_SHIFT 0
tushki7 0:60d829a0353a 844 #define IOCON_PIO3_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 845 #define IOCON_PIO3_1_MODE_SHIFT 3
tushki7 0:60d829a0353a 846 #define IOCON_PIO3_1_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 847 #define IOCON_PIO3_1_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 848
tushki7 0:60d829a0353a 849 /* IOCON_PIO2_3, address 0x4004 408C */
tushki7 0:60d829a0353a 850 #define IOCON_PIO2_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 851 #define IOCON_PIO2_3_FUNC_SHIFT 0
tushki7 0:60d829a0353a 852 #define IOCON_PIO2_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 853 #define IOCON_PIO2_3_MODE_SHIFT 3
tushki7 0:60d829a0353a 854 #define IOCON_PIO2_3_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 855 #define IOCON_PIO2_3_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 856
tushki7 0:60d829a0353a 857 /* IOCON_SWDIO_PIO1_3, address 0x4004 4090 */
tushki7 0:60d829a0353a 858 #define IOCON_SWDIO_PIO1_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 859 #define IOCON_SWDIO_PIO1_3_FUNC_SHIFT 0
tushki7 0:60d829a0353a 860 #define IOCON_SWDIO_PIO1_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 861 #define IOCON_SWDIO_PIO1_3_MODE_SHIFT 3
tushki7 0:60d829a0353a 862 #define IOCON_SWDIO_PIO1_3_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 863 #define IOCON_SWDIO_PIO1_3_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 864 #define IOCON_SWDIO_PIO1_3_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 865
tushki7 0:60d829a0353a 866 /* IOCON_PIO1_4, address 0x4004 4094 */
tushki7 0:60d829a0353a 867 #define IOCON_PIO1_4_FUNC_MASK 0x0007 // Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
tushki7 0:60d829a0353a 868 #define IOCON_PIO1_4_FUNC_SHIFT 0
tushki7 0:60d829a0353a 869 #define IOCON_PIO1_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 870 #define IOCON_PIO1_4_MODE_SHIFT 3
tushki7 0:60d829a0353a 871 #define IOCON_PIO1_4_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 872 #define IOCON_PIO1_4_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 873 #define IOCON_PIO1_4_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 874
tushki7 0:60d829a0353a 875 /* IOCON_PIO1_11, address 0x4004 4098 */
tushki7 0:60d829a0353a 876 #define IOCON_PIO1_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 877 #define IOCON_PIO1_11_FUNC_SHIFT 0
tushki7 0:60d829a0353a 878 #define IOCON_PIO1_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 879 #define IOCON_PIO1_11_MODE_SHIFT 3
tushki7 0:60d829a0353a 880 #define IOCON_PIO1_11_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 881 #define IOCON_PIO1_11_ADMODE (1 << 7) // Selects Analog/Digital mode
tushki7 0:60d829a0353a 882 #define IOCON_PIO1_11_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 883
tushki7 0:60d829a0353a 884 /* IOCON_PIO3_2, address 0x4004 409C */
tushki7 0:60d829a0353a 885 #define IOCON_PIO3_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 886 #define IOCON_PIO3_2_FUNC_SHIFT 0
tushki7 0:60d829a0353a 887 #define IOCON_PIO3_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 888 #define IOCON_PIO3_2_MODE_SHIFT 3
tushki7 0:60d829a0353a 889 #define IOCON_PIO3_2_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 890 #define IOCON_PIO3_2_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 891
tushki7 0:60d829a0353a 892 /* IOCON_PIO1_5, address 0x4004 40A0 */
tushki7 0:60d829a0353a 893 #define IOCON_PIO1_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 894 #define IOCON_PIO1_5_FUNC_SHIFT 0
tushki7 0:60d829a0353a 895 #define IOCON_PIO1_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 896 #define IOCON_PIO1_5_MODE_SHIFT 3
tushki7 0:60d829a0353a 897 #define IOCON_PIO1_5_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 898 #define IOCON_PIO1_5_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 899
tushki7 0:60d829a0353a 900 /* IOCON_PIO1_6, address 0x4004 40A4 */
tushki7 0:60d829a0353a 901 #define IOCON_PIO1_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 902 #define IOCON_PIO1_6_FUNC_SHIFT 0
tushki7 0:60d829a0353a 903 #define IOCON_PIO1_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 904 #define IOCON_PIO1_6_MODE_SHIFT 3
tushki7 0:60d829a0353a 905 #define IOCON_PIO1_6_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 906 #define IOCON_PIO1_6_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 907
tushki7 0:60d829a0353a 908 /* IOCON_PIO1_7, address 0x4004 40A8 */
tushki7 0:60d829a0353a 909 #define IOCON_PIO1_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 910 #define IOCON_PIO1_7_FUNC_SHIFT 0
tushki7 0:60d829a0353a 911 #define IOCON_PIO1_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 912 #define IOCON_PIO1_7_MODE_SHIFT 3
tushki7 0:60d829a0353a 913 #define IOCON_PIO1_7_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 914 #define IOCON_PIO1_7_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 915
tushki7 0:60d829a0353a 916 /* IOCON_PIO3_3, address 0x4004 40AC */
tushki7 0:60d829a0353a 917 #define IOCON_PIO3_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
tushki7 0:60d829a0353a 918 #define IOCON_PIO3_3_FUNC_SHIFT 0
tushki7 0:60d829a0353a 919 #define IOCON_PIO3_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
tushki7 0:60d829a0353a 920 #define IOCON_PIO3_3_MODE_SHIFT 3
tushki7 0:60d829a0353a 921 #define IOCON_PIO3_3_HYS (1 << 5) // Hysteresis.
tushki7 0:60d829a0353a 922 #define IOCON_PIO3_3_OD (1 << 10) // Selects pseudo open-drain mode.
tushki7 0:60d829a0353a 923
tushki7 0:60d829a0353a 924 /* IOCON_SCK0_LOC, address 0x4004 40B0 */
tushki7 0:60d829a0353a 925 #define IOCON_SCK0_LOC_SCKLOC_MASK 0x0003 // Selects pin location for SCK0 function.
tushki7 0:60d829a0353a 926 #define IOCON_SCK0_LOC_SCKLOC_SHIFT 0
tushki7 0:60d829a0353a 927
tushki7 0:60d829a0353a 928 /* IOCON_DSR_LOC, address 0x4004 40B4 */
tushki7 0:60d829a0353a 929 #define IOCON_DSR_LOC_DSRLOC_MASK 0x0003 // elects pin location for DSR function.
tushki7 0:60d829a0353a 930 #define IOCON_DSR_LOC_DSRLOC_SHIFT 0
tushki7 0:60d829a0353a 931
tushki7 0:60d829a0353a 932 /* IOCON_DCD_LOC, address 0x4004 40B8 */
tushki7 0:60d829a0353a 933 #define IOCON_DCD_LOC_DCDLOC_MASK 0x0003 // Selects pin location for DCD function.
tushki7 0:60d829a0353a 934 #define IOCON_DCD_LOC_DCDLOC_SHIFT 0
tushki7 0:60d829a0353a 935
tushki7 0:60d829a0353a 936 /* IOCON_RI_LOC, address 0x4004 40BC */
tushki7 0:60d829a0353a 937 #define IOCON_RI_LOC_RILOC_MASK 0x0003 // Selects pin location for RI function.
tushki7 0:60d829a0353a 938 #define IOCON_RI_LOC_RILOC_SHIFT 0
tushki7 0:60d829a0353a 939
tushki7 0:60d829a0353a 940 /* IOCON_SSEL1_LOC, address 0x4004 4018 */
tushki7 0:60d829a0353a 941 #define IOCON_SSEL1_LOC_SSEL1LOC_MASK 0x0003 // Selects pin location for SSEL1 function.
tushki7 0:60d829a0353a 942 #define IOCON_SSEL1_LOC_SSEL1LOC_SHIFT 0
tushki7 0:60d829a0353a 943
tushki7 0:60d829a0353a 944 /* IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0 */
tushki7 0:60d829a0353a 945 #define IOCON_CT16B0_CAP0_LOC_CT16B0_CAP0LOC_MASK 0x0003 // Selects pin location for CT16B0_CAP0 function.
tushki7 0:60d829a0353a 946 #define IOCON_CT16B0_CAP0_LOC_CT16B0_CAP0LOC_SHIFT 0
tushki7 0:60d829a0353a 947
tushki7 0:60d829a0353a 948 /* IOCON_SCK1_LOC, address 0x4004 40C4 */
tushki7 0:60d829a0353a 949 #define IOCON_SCK1_LOC_SCK1LOC_MASK 0x0003 // Selects pin location for SCK1 function.
tushki7 0:60d829a0353a 950 #define IOCON_SCK1_LOC_SCK1LOC_SHIFT 0
tushki7 0:60d829a0353a 951
tushki7 0:60d829a0353a 952 /* IOCON_MISO1_LOC, address 0x4004 40C8 */
tushki7 0:60d829a0353a 953 #define IOCON_MISO1_LOC_MISO1LOC_MASK 0x0003 // Selects pin location for the MISO1 function.
tushki7 0:60d829a0353a 954 #define IOCON_MISO1_LOC_MISO1LOC_SHIFT 0
tushki7 0:60d829a0353a 955
tushki7 0:60d829a0353a 956 /* IOCON_MOSI1_LOC, address 0x4004 40CC */
tushki7 0:60d829a0353a 957 #define IOCON_MOSI1_LOC_MOSI1LOC_MASK 0x0003 // Selects pin location for the MOSI1 function.
tushki7 0:60d829a0353a 958 #define IOCON_MOSI1_LOC_MOSI1LOC_SHIFT 0
tushki7 0:60d829a0353a 959
tushki7 0:60d829a0353a 960 /* IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0 */
tushki7 0:60d829a0353a 961 #define IOCON_CT32B0_CAP0_LOC_CT32B0_CAP0LOC_MASK 0x0003 // Selects pin location for the CT32B0_CAP0 function.
tushki7 0:60d829a0353a 962 #define IOCON_CT32B0_CAP0_LOC_CT32B0_CAP0LOC_SHIFT 0
tushki7 0:60d829a0353a 963
tushki7 0:60d829a0353a 964 /* IOCON_RXD_LOC, address 0x4004 40D4 */
tushki7 0:60d829a0353a 965 #define IOCON_RXD_LOC_RXDLOC_MASK 0x0003 // Selects pin location for the RXD function.
tushki7 0:60d829a0353a 966 #define IOCON_RXD_LOC_RXDLOC_SHIFT 0
tushki7 0:60d829a0353a 967
tushki7 0:60d829a0353a 968 /* GPIO0DIR, address 0x5000 8000 to GPIO3DIR, address 0x5003 8000 */
tushki7 0:60d829a0353a 969 #define GPIO0DIR_IO_MASK 0x0FFF // Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
tushki7 0:60d829a0353a 970 #define GPIO0DIR_IO_SHIFT 0
tushki7 0:60d829a0353a 971
tushki7 0:60d829a0353a 972 /* GPIO0IS, address 0x5000 8004 to GPIO3IS, address 0x5003 8004 */
tushki7 0:60d829a0353a 973 #define GPIO0IS_ISENSE_MASK 0x0FFF // Selects interrupt on pin x as level or edge sensitive (x = 0 to 0x00 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
tushki7 0:60d829a0353a 974 #define GPIO0IS_ISENSE_SHIFT 0
tushki7 0:60d829a0353a 975
tushki7 0:60d829a0353a 976 /* GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003 8008 */
tushki7 0:60d829a0353a 977 #define GPIO0IBE_IBE_MASK 0x0FFF // Selects interrupt on pin x to be triggered on both edges (x = 0 0x00 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
tushki7 0:60d829a0353a 978 #define GPIO0IBE_IBE_SHIFT 0
tushki7 0:60d829a0353a 979
tushki7 0:60d829a0353a 980 /* GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003 800C */
tushki7 0:60d829a0353a 981 #define GPIO0IEV_IEV_MASK 0x0FFF // Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 175), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 175), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
tushki7 0:60d829a0353a 982 #define GPIO0IEV_IEV_SHIFT 0
tushki7 0:60d829a0353a 983
tushki7 0:60d829a0353a 984 /* GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003 8010 */
tushki7 0:60d829a0353a 985 #define GPIO0IE_MASK_MASK 0x0FFF // Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
tushki7 0:60d829a0353a 986 #define GPIO0IE_MASK_SHIFT 0
tushki7 0:60d829a0353a 987
tushki7 0:60d829a0353a 988 /* GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003 8014 */
tushki7 0:60d829a0353a 989 #define GPIO0RIS_RAWST_MASK 0x0FFF // Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
tushki7 0:60d829a0353a 990 #define GPIO0RIS_RAWST_SHIFT 0
tushki7 0:60d829a0353a 991
tushki7 0:60d829a0353a 992 /* GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address 0x5003 8018 */
tushki7 0:60d829a0353a 993 #define GPIO0MIS_MASK_MASK 0x0FFF // Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
tushki7 0:60d829a0353a 994 #define GPIO0MIS_MASK_SHIFT 0
tushki7 0:60d829a0353a 995
tushki7 0:60d829a0353a 996 /* GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003 801C */
tushki7 0:60d829a0353a 997 #define GPIO0IC_CLR_MASK 0x0FFF // Selects interrupt on pin x to be cleared (x = 0 to 11). Clears 0x00 the interrupt edge detection logic. This register is write-only. Remark: The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
tushki7 0:60d829a0353a 998 #define GPIO0IC_CLR_SHIFT 0
tushki7 0:60d829a0353a 999
tushki7 0:60d829a0353a 1000 /* U0IIR - address 0x4004 8008, Read Only */
tushki7 0:60d829a0353a 1001 #define U0IIR_INTSTATUS (1 << 0) // Interrupt status. Note that U0IIR[0] is active low. The pending interrupt can be determined by evaluating U0IIR[3:1].
tushki7 0:60d829a0353a 1002 #define U0IIR_INTID_MASK 0x000E // Interrupt identification. U0IER[3:1] identifies an interrupt 0 corresponding to the UART Rx FIFO. All other combinations of U0IER[3:1] not listed below are reserved (100,101,111).
tushki7 0:60d829a0353a 1003 #define U0IIR_INTID_SHIFT 1
tushki7 0:60d829a0353a 1004 #define U0IIR_FIFOENABLE_MASK 0x00C0 // These bits are equivalent to U0FCR[0].
tushki7 0:60d829a0353a 1005 #define U0IIR_FIFOENABLE_SHIFT 6
tushki7 0:60d829a0353a 1006 #define U0IIR_ABEOINT (1 << 8) // End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
tushki7 0:60d829a0353a 1007 #define U0IIR_ABTOINT (1 << 9) // Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
tushki7 0:60d829a0353a 1008
tushki7 0:60d829a0353a 1009 /* U0FCR - address 0x4000 8008, Write Only */
tushki7 0:60d829a0353a 1010 #define U0FCR_FIFOEN (1 << 0) // FIFO Enable
tushki7 0:60d829a0353a 1011 #define U0FCR_RXFIFORES (1 << 1) // RX FIFO Reset
tushki7 0:60d829a0353a 1012 #define U0FCR_TXFIFORES (1 << 2) // TX FIFO Reset
tushki7 0:60d829a0353a 1013 #define U0FCR_RXTL_MASK 0x00C0 // RX Trigger Level. These two bits determine how many 0 receiver UART FIFO characters must be written before an interrupt is activated.
tushki7 0:60d829a0353a 1014 #define U0FCR_RXTL_SHIFT 6
tushki7 0:60d829a0353a 1015
tushki7 0:60d829a0353a 1016 /* U0LCR - address 0x4000 800C */
tushki7 0:60d829a0353a 1017 #define U0LCR_WLS_MASK 0x0003 // Word Length Select
tushki7 0:60d829a0353a 1018 #define U0LCR_WLS_SHIFT 0
tushki7 0:60d829a0353a 1019 #define U0LCR_SBS (1 << 2) // Stop Bit Select
tushki7 0:60d829a0353a 1020 #define U0LCR_PE (1 << 3) // Parity Enable
tushki7 0:60d829a0353a 1021 #define U0LCR_PS_MASK 0x0030 // Parity Select 0x0 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x2 Forced 1 stick parity. 0x3 Forced 0 stick parity.
tushki7 0:60d829a0353a 1022 #define U0LCR_PS_SHIFT 4
tushki7 0:60d829a0353a 1023 #define U0LCR_BC (1 << 6) // Break Control
tushki7 0:60d829a0353a 1024 #define U0LCR_DLAB (1 << 7) // Divisor Latch Access Bit
tushki7 0:60d829a0353a 1025
tushki7 0:60d829a0353a 1026 /* U0MCR - address 0x4000 8010 */
tushki7 0:60d829a0353a 1027 #define U0MCR_DTRC (1 << 0) // DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
tushki7 0:60d829a0353a 1028 #define U0MCR_RTSC (1 << 1) // RTS Control. Source for modem output pin RTS. This bit reads as 0 0 when modem loopback mode is active.
tushki7 0:60d829a0353a 1029 #define U0MCR_LMS (1 << 4) // Loopback Mode Select. The modem loopback mode provides a 0 mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the U0MSR will be driven by the lower four bits of the U0MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of U0MCR.
tushki7 0:60d829a0353a 1030 #define U0MCR_RTSEN (1 << 6) // RTS flow control
tushki7 0:60d829a0353a 1031 #define U0MCR_CTSEN (1 << 7) // CTS flow control
tushki7 0:60d829a0353a 1032
tushki7 0:60d829a0353a 1033 /* U0LSR - address 0x4000 8014, Read Only */
tushki7 0:60d829a0353a 1034 #define U0LSR_RDR (1 << 0) // Receiver Data Ready. U0LSR[0] is set when the U0RBR holds 0 an unread character and is cleared when the UART RBR FIFO is empty.
tushki7 0:60d829a0353a 1035 #define U0LSR_OE (1 << 1) // Overrun Error. The overrun error condition is set as soon as it 0 occurs. A U0LSR read clears U0LSR[1]. U0LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
tushki7 0:60d829a0353a 1036 #define U0LSR_PE (1 << 2) // Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on U0FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
tushki7 0:60d829a0353a 1037 #define U0LSR_FE (1 << 3) // Framing Error. When the stop bit of a received character is a 0 logic 0, a framing error occurs. A U0LSR read clears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
tushki7 0:60d829a0353a 1038 #define U0LSR_BI (1 << 4) // Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A U0LSR read clears this status bit. The time of break detection is dependent on U0FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
tushki7 0:60d829a0353a 1039 #define U0LSR_THRE (1 << 5) // Transmitter Holding Register Empty. THRE is set immediately 1 upon detection of an empty UART THR and is cleared on a U0THR write.
tushki7 0:60d829a0353a 1040 #define U0LSR_TEMT (1 << 6) // Transmitter Empty. TEMT is set when both U0THR and 1 U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data. This bit is updated as soon as 50 % of the first stop bit has been transmitted or a byte has been written into the THR.
tushki7 0:60d829a0353a 1041 #define U0LSR_RXFE (1 << 7) // Error in RX FIFO. U0LSR[7] is set when a character with a RX 0 error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART FIFO.
tushki7 0:60d829a0353a 1042
tushki7 0:60d829a0353a 1043 /* U0MSR - address 0x4000 8018 */
tushki7 0:60d829a0353a 1044 #define U0MSR_DCTS (1 << 0) // Delta CTS. Set upon state change of input CTS. Cleared on a U0MSR read. 0 No change detected on modem input CTS. 1 State change detected on modem input CTS.
tushki7 0:60d829a0353a 1045 #define U0MSR_DDSR (1 << 1) // Delta DSR. Set upon state change of input DSR. Cleared on a U0MSR read. 0 No change detected on modem input DSR. 1 State change detected on modem input DSR.
tushki7 0:60d829a0353a 1046 #define U0MSR_TERI (1 << 2) // Trailing Edge RI. Set upon low to high transition of input RI. Cleared 0 on a U0MSR read. 0 No change detected on modem input, RI. 1 Low-to-high transition detected on RI.
tushki7 0:60d829a0353a 1047 #define U0MSR_DDCD (1 << 3) // Delta DCD. Set upon state change of input DCD. Cleared on a U0MSR read. 0 No change detected on modem input DCD. 1 State change detected on modem input DCD.
tushki7 0:60d829a0353a 1048 #define U0MSR_CTS (1 << 4) // Clear To Send State. Complement of input signal CTS. This bit is connected to U0MCR[1] in modem loopback mode.
tushki7 0:60d829a0353a 1049 #define U0MSR_DSR (1 << 5) // Data Set Ready State. Complement of input signal DSR. This bit is connected to U0MCR[0] in modem loopback mode.
tushki7 0:60d829a0353a 1050 #define U0MSR_RI (1 << 6) // Ring Indicator State. Complement of input RI. This bit is connected to U0MCR[2] in modem loopback mode.
tushki7 0:60d829a0353a 1051 #define U0MSR_DCD (1 << 7) // Data Carrier Detect State. Complement of input DCD. This bit is connected to U0MCR[3] in modem loopback mode.
tushki7 0:60d829a0353a 1052
tushki7 0:60d829a0353a 1053 /* U0SCR - address 0x4000 801C */
tushki7 0:60d829a0353a 1054 #define U0SCR_PAD_MASK 0x00FF // A readable, writable byte.
tushki7 0:60d829a0353a 1055 #define U0SCR_PAD_SHIFT 0
tushki7 0:60d829a0353a 1056
tushki7 0:60d829a0353a 1057 /* U0ACR - address 0x4000 8020 */
tushki7 0:60d829a0353a 1058 #define U0ACR_START (1 << 0) // Start bit. This bit is automatically cleared after auto-baud completion.
tushki7 0:60d829a0353a 1059 #define U0ACR_MODE (1 << 1) // Auto-baud mode select
tushki7 0:60d829a0353a 1060 #define U0ACR_AUTORESTART (1 << 2) // Restart enable
tushki7 0:60d829a0353a 1061 #define U0ACR_ABEOINTCLR (1 << 8) // End of auto-baud interrupt clear (write only accessible)
tushki7 0:60d829a0353a 1062 #define U0ACR_ABTOINTCLR (1 << 9) // Auto-baud time-out interrupt clear (write only accessible)
tushki7 0:60d829a0353a 1063
tushki7 0:60d829a0353a 1064 /* U0TER - address 0x4000 8030 */
tushki7 0:60d829a0353a 1065 #define U0TER_TXEN (1 << 7) // When this bit is 1, as it is after a Reset, data written to the THR 1 is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. Reserved
tushki7 0:60d829a0353a 1066
tushki7 0:60d829a0353a 1067 /* U0RS485CTRL - address 0x4000 804C */
tushki7 0:60d829a0353a 1068 #define U0RS485CTRL_NMMEN (1 << 0) // NMM enable.
tushki7 0:60d829a0353a 1069 #define U0RS485CTRL_RXDIS (1 << 1) // Receiver enable.
tushki7 0:60d829a0353a 1070 #define U0RS485CTRL_AADEN (1 << 2) // AAD enable.
tushki7 0:60d829a0353a 1071 #define U0RS485CTRL_SEL (1 << 3) // Select direction control pin
tushki7 0:60d829a0353a 1072 #define U0RS485CTRL_DCTRL (1 << 4) // Auto direction control enable.
tushki7 0:60d829a0353a 1073 #define U0RS485CTRL_OINV (1 << 5) // Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
tushki7 0:60d829a0353a 1074
tushki7 0:60d829a0353a 1075 /* U0RS485ADRMATCH - address 0x4000 8050 */
tushki7 0:60d829a0353a 1076 #define U0RS485ADRMATCH_ADRMATCH_MASK 0x00FF // Contains the address match value. 0
tushki7 0:60d829a0353a 1077 #define U0RS485ADRMATCH_ADRMATCH_SHIFT 0
tushki7 0:60d829a0353a 1078
tushki7 0:60d829a0353a 1079 /* U0RS485DLY - address 0x4000 8054 */
tushki7 0:60d829a0353a 1080 #define U0RS485DLY_DLY_MASK 0x00FF // Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
tushki7 0:60d829a0353a 1081 #define U0RS485DLY_DLY_SHIFT 0
tushki7 0:60d829a0353a 1082
tushki7 0:60d829a0353a 1083 /* SSP0CR0 - address 0x4004 0000, SSP1CR0 - address 0x4005 8000 */
tushki7 0:60d829a0353a 1084 #define SSP0CR0_DSS_MASK 0x000F // Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
tushki7 0:60d829a0353a 1085 #define SSP0CR0_DSS_SHIFT 0
tushki7 0:60d829a0353a 1086 #define SSP0CR0_FRF_MASK 0x0030 // Frame Format.
tushki7 0:60d829a0353a 1087 #define SSP0CR0_FRF_SHIFT 4
tushki7 0:60d829a0353a 1088 #define SSP0CR0_CPOL (1 << 6) // Clock Out Polarity. This bit is only used in SPI mode.
tushki7 0:60d829a0353a 1089 #define SSP0CR0_CPHA (1 << 7) // Clock Out Phase. This bit is only used in SPI mode.
tushki7 0:60d829a0353a 1090 #define SSP0CR0_SCR_MASK 0xFF00 // Serial Clock Rate. The number of prescaler output clocks per 0x00 bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR [SCR+1]). Reserved
tushki7 0:60d829a0353a 1091 #define SSP0CR0_SCR_SHIFT 8
tushki7 0:60d829a0353a 1092
tushki7 0:60d829a0353a 1093 /* SSP0CR1 - address 0x4004 0004, SSP1CR1 - address 0x4005 8004 */
tushki7 0:60d829a0353a 1094 #define SSP0CR1_LBM (1 << 0) // Loop Back Mode.
tushki7 0:60d829a0353a 1095 #define SSP0CR1_SSE (1 << 1) // SPI Enable.
tushki7 0:60d829a0353a 1096 #define SSP0CR1_MS (1 << 2) // Master/Slave Mode.This bit can only be written when the SSE bit is 0.
tushki7 0:60d829a0353a 1097 #define SSP0CR1_SOD (1 << 3) // Slave Output Disable. This bit is relevant only in slave 0 mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).
tushki7 0:60d829a0353a 1098
tushki7 0:60d829a0353a 1099 /* SSP0DR - address 0x4004 0008, SSP1DR - address 0x4005 8008 */
tushki7 0:60d829a0353a 1100 #define SSP0DR_DATA_MASK 0xFFFF // Write: software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. Reserved.
tushki7 0:60d829a0353a 1101 #define SSP0DR_DATA_SHIFT 0
tushki7 0:60d829a0353a 1102
tushki7 0:60d829a0353a 1103 /* SSP0SR - address 0x4004 000C, SSP1SR - address 0x4005 800C */
tushki7 0:60d829a0353a 1104 #define SSP0SR_TFE (1 << 0) // Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
tushki7 0:60d829a0353a 1105 #define SSP0SR_TNF (1 << 1) // Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
tushki7 0:60d829a0353a 1106 #define SSP0SR_RNE (1 << 2) // Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
tushki7 0:60d829a0353a 1107 #define SSP0SR_RFF (1 << 3) // Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
tushki7 0:60d829a0353a 1108 #define SSP0SR_BSY (1 << 4) // Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
tushki7 0:60d829a0353a 1109
tushki7 0:60d829a0353a 1110 /* SSP0CPSR - address 0x4004 0010, SSP1CPSR - address 0x4005 8010 */
tushki7 0:60d829a0353a 1111 #define SSP0CPSR_CPSDVSR_MASK 0x00FF // This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
tushki7 0:60d829a0353a 1112 #define SSP0CPSR_CPSDVSR_SHIFT 0
tushki7 0:60d829a0353a 1113
tushki7 0:60d829a0353a 1114 /* SSP0IMSC - address 0x4004 0014, SSP1IMSC - address 0x4005 8014 */
tushki7 0:60d829a0353a 1115 #define SSP0IMSC_RORIM (1 << 0) // Software should set this bit to enable interrupt when a Receive 0 Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
tushki7 0:60d829a0353a 1116 #define SSP0IMSC_RTIM (1 << 1) // Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
tushki7 0:60d829a0353a 1117 #define SSP0IMSC_RXIM (1 << 2) // Software should set this bit to enable interrupt when the Rx FIFO is at 0 least half full.
tushki7 0:60d829a0353a 1118 #define SSP0IMSC_TXIM (1 << 3) // Software should set this bit to enable interrupt when the Tx FIFO is at 0 least half empty.
tushki7 0:60d829a0353a 1119
tushki7 0:60d829a0353a 1120 /* SSP0RIS - address 0x4004 0018, SSP1RIS - address 0x4005 8018 */
tushki7 0:60d829a0353a 1121 #define SSP0RIS_RORRIS (1 << 0) // This bit is 1 if another frame was completely received while the 0 RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
tushki7 0:60d829a0353a 1122 #define SSP0RIS_RTRIS (1 << 1) // This bit is 1 if the Rx FIFO is not empty, and has not been read 0 for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
tushki7 0:60d829a0353a 1123 #define SSP0RIS_RXRIS (1 << 2) // This bit is 1 if the Rx FIFO is at least half full.
tushki7 0:60d829a0353a 1124 #define SSP0RIS_TXRIS (1 << 3) // This bit is 1 if the Tx FIFO is at least half empty.
tushki7 0:60d829a0353a 1125
tushki7 0:60d829a0353a 1126 /* SSP0MIS - address 0x4004 001C, SSP1MIS - address 0x4005 801C */
tushki7 0:60d829a0353a 1127 #define SSP0MIS_RORMIS (1 << 0) // This bit is 1 if another frame was completely received while the 0 RxFIFO was full, and this interrupt is enabled.
tushki7 0:60d829a0353a 1128 #define SSP0MIS_RTMIS (1 << 1) // This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
tushki7 0:60d829a0353a 1129 #define SSP0MIS_RXMIS (1 << 2) // This bit is 1 if the Rx FIFO is at least half full, and this interrupt 0 is enabled.
tushki7 0:60d829a0353a 1130 #define SSP0MIS_TXMIS (1 << 3) // This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
tushki7 0:60d829a0353a 1131
tushki7 0:60d829a0353a 1132 /* SSP0ICR - address 0x4004 0020, SSP1ICR - address 0x4005 8020 */
tushki7 0:60d829a0353a 1133 #define SSP0ICR_RORIC (1 << 0) // Writing a 1 to this bit clears the "frame was received when RxFIFO was full" interrupt.
tushki7 0:60d829a0353a 1134 #define SSP0ICR_RTIC (1 << 1) // Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
tushki7 0:60d829a0353a 1135
tushki7 0:60d829a0353a 1136 /* I2C0CONSET - address 0x4000 0000 */
tushki7 0:60d829a0353a 1137 #define I2C0CONSET_AA (1 << 2) // Assert acknowledge flag.
tushki7 0:60d829a0353a 1138 #define I2C0CONSET_SI (1 << 3) // I2C interrupt flag.
tushki7 0:60d829a0353a 1139 #define I2C0CONSET_STO (1 << 4) // STOP flag.
tushki7 0:60d829a0353a 1140 #define I2C0CONSET_STA (1 << 5) // START flag.
tushki7 0:60d829a0353a 1141 #define I2C0CONSET_I2EN (1 << 6) // I2C interface enable. Reserved. The value read from a reserved bit is not defined.
tushki7 0:60d829a0353a 1142
tushki7 0:60d829a0353a 1143 /* I2C0STAT - 0x4000 0004 */
tushki7 0:60d829a0353a 1144 #define I2C0STAT_STATUS_MASK 0x00F8 // These bits give the actual status information about the I2 C interface. Reserved. The value read from a reserved bit is not defined.
tushki7 0:60d829a0353a 1145 #define I2C0STAT_STATUS_SHIFT 3
tushki7 0:60d829a0353a 1146
tushki7 0:60d829a0353a 1147 /* I2C0DAT - 0x4000 0008 */
tushki7 0:60d829a0353a 1148 #define I2C0DAT_DATA_MASK 0x00FF // This register holds data values that have been received or are to 0 be transmitted. Reserved. The value read from a reserved bit is not defined.
tushki7 0:60d829a0353a 1149 #define I2C0DAT_DATA_SHIFT 0
tushki7 0:60d829a0353a 1150
tushki7 0:60d829a0353a 1151 /* I2C0ADR0 - 0x4000 000C */
tushki7 0:60d829a0353a 1152 #define I2C0ADR0_GC (1 << 0) // General Call enable bit.
tushki7 0:60d829a0353a 1153 #define I2C0ADR0_ADDRESS_MASK 0x00FE // The I2C device address for slave mode. Reserved. The value read from a reserved bit is not defined.
tushki7 0:60d829a0353a 1154 #define I2C0ADR0_ADDRESS_SHIFT 1
tushki7 0:60d829a0353a 1155
tushki7 0:60d829a0353a 1156 /* I2C0SCLH - address 0x4000 0010 */
tushki7 0:60d829a0353a 1157 #define I2C0SCLH_SCLH_MASK 0xFFFF // Count for SCL HIGH time period selection.
tushki7 0:60d829a0353a 1158 #define I2C0SCLH_SCLH_SHIFT 0
tushki7 0:60d829a0353a 1159
tushki7 0:60d829a0353a 1160 /* I2C0SCLL - 0x4000 0014 */
tushki7 0:60d829a0353a 1161 #define I2C0SCLL_SCLL_MASK 0xFFFF // Count for SCL low time period selection.
tushki7 0:60d829a0353a 1162 #define I2C0SCLL_SCLL_SHIFT 0
tushki7 0:60d829a0353a 1163
tushki7 0:60d829a0353a 1164 /* I2C0CONCLR - 0x4000 0018 */
tushki7 0:60d829a0353a 1165 #define I2C0CONCLR_AAC (1 << 2) // Assert acknowledge Clear bit.
tushki7 0:60d829a0353a 1166 #define I2C0CONCLR_SIC (1 << 3) // I2C interrupt Clear bit.
tushki7 0:60d829a0353a 1167 #define I2C0CONCLR_STAC (1 << 5) // START flag Clear bit.
tushki7 0:60d829a0353a 1168 #define I2C0CONCLR_I2ENC (1 << 6) // I2C interface Disable bit. Reserved. The value read from a reserved bit is not defined.
tushki7 0:60d829a0353a 1169
tushki7 0:60d829a0353a 1170 /* I2C0MMCTRL - 0x4000 001C */
tushki7 0:60d829a0353a 1171 #define I2C0MMCTRL_MM_ENA (1 << 0) // Monitor mode enable.
tushki7 0:60d829a0353a 1172 #define I2C0MMCTRL_ENA_SCL (1 << 1) // SCL output enable.
tushki7 0:60d829a0353a 1173
tushki7 0:60d829a0353a 1174 /* I2C0DATA_BUFFER - 0x4000 002C */
tushki7 0:60d829a0353a 1175 #define I2C0DATA_BUFFER_DATA_MASK 0x00FF // This register holds contents of the 8 MSBs of the DAT shift register. Reserved. The value read from a reserved bit is not defined.
tushki7 0:60d829a0353a 1176 #define I2C0DATA_BUFFER_DATA_SHIFT 0
tushki7 0:60d829a0353a 1177
tushki7 0:60d829a0353a 1178 /* CANCNTL, address 0x4005 0000 */
tushki7 0:60d829a0353a 1179 #define CANCNTL_INIT (1 << 0) // Initialization
tushki7 0:60d829a0353a 1180 #define CANCNTL_IE (1 << 1) // Module interrupt enable
tushki7 0:60d829a0353a 1181 #define CANCNTL_SIE (1 << 2) // Status change interrupt enable
tushki7 0:60d829a0353a 1182 #define CANCNTL_EIE (1 << 3) // Error interrupt enable
tushki7 0:60d829a0353a 1183 #define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
tushki7 0:60d829a0353a 1184 #define CANCNTL_CCE (1 << 6) // Configuration change enable
tushki7 0:60d829a0353a 1185 #define CANCNTL_TEST (1 << 7) // Test mode enable
tushki7 0:60d829a0353a 1186
tushki7 0:60d829a0353a 1187 /* CANSTAT, address 0x4005 0004 */
tushki7 0:60d829a0353a 1188 #define CANSTAT_LEC_MASK 0x0007 // Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to `0' when a message has been transferred (reception or transmission) without error. The unused code `111' may be written by the CPU to check for updates.
tushki7 0:60d829a0353a 1189 #define CANSTAT_LEC_SHIFT 0
tushki7 0:60d829a0353a 1190 #define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
tushki7 0:60d829a0353a 1191 #define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
tushki7 0:60d829a0353a 1192 #define CANSTAT_EPASS (1 << 5) // Error passive
tushki7 0:60d829a0353a 1193 #define CANSTAT_EWARN (1 << 6) // Warning status
tushki7 0:60d829a0353a 1194 #define CANSTAT_BOFF (1 << 7) // Busoff status
tushki7 0:60d829a0353a 1195
tushki7 0:60d829a0353a 1196 /* CANEC, address 0x4005 0008 */
tushki7 0:60d829a0353a 1197 #define CANEC_TEC_MASK 0x00FF // Transmit error counter Current value of the transmit error counter (maximum value 255)
tushki7 0:60d829a0353a 1198 #define CANEC_TEC_SHIFT 0
tushki7 0:60d829a0353a 1199 #define CANEC_REC_MASK 0x7F00 // Receive error counter Current value of the receive error counter (maximum value 127).
tushki7 0:60d829a0353a 1200 #define CANEC_REC_SHIFT 8
tushki7 0:60d829a0353a 1201 #define CANEC_RP (1 << 15) // Receive error passive
tushki7 0:60d829a0353a 1202
tushki7 0:60d829a0353a 1203 /* CANBT, address 0x4005 000C */
tushki7 0:60d829a0353a 1204 #define CANBT_BRP_MASK 0x003F // Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1]
tushki7 0:60d829a0353a 1205 #define CANBT_BRP_SHIFT 0
tushki7 0:60d829a0353a 1206 #define CANBT_SJW_MASK 0x00C0 // (Re)synchronization jump width Valid programmed values are 0 to 3.[1]
tushki7 0:60d829a0353a 1207 #define CANBT_SJW_SHIFT 6
tushki7 0:60d829a0353a 1208 #define CANBT_TSEG1_MASK 0x0F00 // Time segment before the sample point Valid values are 1 to 15.[1]
tushki7 0:60d829a0353a 1209 #define CANBT_TSEG1_SHIFT 8
tushki7 0:60d829a0353a 1210 #define CANBT_TSEG2_MASK 0x7000 // Time segment after the sample point Valid values are 0 to 7.[1]
tushki7 0:60d829a0353a 1211 #define CANBT_TSEG2_SHIFT 12
tushki7 0:60d829a0353a 1212
tushki7 0:60d829a0353a 1213 /* CANINT, address 0x4005 0010 */
tushki7 0:60d829a0353a 1214 #define CANINT_INTID_MASK 0xFFFF // 0x0000 = No interrupt is pending. 0 0x0001 - 0x0020 = Number of message object which caused the interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 - 0xFFFF = Unused
tushki7 0:60d829a0353a 1215 #define CANINT_INTID_SHIFT 0
tushki7 0:60d829a0353a 1216
tushki7 0:60d829a0353a 1217 /* CANTEST, address 0x4005 0014 */
tushki7 0:60d829a0353a 1218 #define CANTEST_BASIC (1 << 2) // Basic mode
tushki7 0:60d829a0353a 1219 #define CANTEST_SILENT (1 << 3) // Silent mode
tushki7 0:60d829a0353a 1220 #define CANTEST_LBACK (1 << 4) // Loop back mode
tushki7 0:60d829a0353a 1221 #define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
tushki7 0:60d829a0353a 1222 #define CANTEST_TX_SHIFT 5
tushki7 0:60d829a0353a 1223 #define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
tushki7 0:60d829a0353a 1224
tushki7 0:60d829a0353a 1225 /* CANBRPE, address 0x4005 0018 */
tushki7 0:60d829a0353a 1226 #define CANBRPE_BRPE_MASK 0x000F // Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15.
tushki7 0:60d829a0353a 1227 #define CANBRPE_BRPE_SHIFT 0
tushki7 0:60d829a0353a 1228
tushki7 0:60d829a0353a 1229 /* CANIF1_CMDREQ, address 0x4005 0020 and CANIF2_CMDREQ, address 0x4005 0080 */
tushki7 0:60d829a0353a 1230 #define CANIFn_CMDREQ_MN_MASK 0x003F // Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]
tushki7 0:60d829a0353a 1231 #define CANIFn_CMDREQ_MN_SHIFT 0
tushki7 0:60d829a0353a 1232 #define CANIFn_CMDREQ_BUSY (1 << 15) // BUSY flag
tushki7 0:60d829a0353a 1233
tushki7 0:60d829a0353a 1234 /* CANIF1_CMDMSK, address 0x4005 0024 and CANIF2_CMDMSK, address 0x4005 0084 */
tushki7 0:60d829a0353a 1235 #define CANIFn_CMDMSK_DATA_B (1 << 0) // Access data bytes 4-7
tushki7 0:60d829a0353a 1236 #define CANIFn_CMDMSK_DATA_A (1 << 1) // Access data bytes 0-3
tushki7 0:60d829a0353a 1237 #define CANIFn_CMDMSK_TXRQST (1 << 2) // Access transmission request bit (Write direction)
tushki7 0:60d829a0353a 1238 #define CANIFn_CMDMSK_NEWDAT (1 << 2) // Access new data bit (Read direction)
tushki7 0:60d829a0353a 1239 #define CANIFn_CMDMSK_CLRINTPND (1 << 3) // This bit is ignored in the write direction.
tushki7 0:60d829a0353a 1240 #define CANIFn_CMDMSK_CTRL (1 << 4) // Access control bits
tushki7 0:60d829a0353a 1241 #define CANIFn_CMDMSK_ARB (1 << 5) // Access arbitration bits
tushki7 0:60d829a0353a 1242 #define CANIFn_CMDMSK_MASK (1 << 6) // Access mask bits
tushki7 0:60d829a0353a 1243 #define CANIFn_CMDMSK_WR (1 << 7) // Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
tushki7 0:60d829a0353a 1244 #define CANIFn_CMDMSK_RD (0 << 7) // Read transfer Read data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
tushki7 0:60d829a0353a 1245
tushki7 0:60d829a0353a 1246 /* CANIF1_MSK1, address 0x4005 0028 and CANIF2_MASK1, address 0x4005 0088 */
tushki7 0:60d829a0353a 1247 #define CANIFn_MSK1_MSK_MASK 0xFFFF // Identifier mask
tushki7 0:60d829a0353a 1248 #define CANIFn_MSK1_MSK_SHIFT 0
tushki7 0:60d829a0353a 1249
tushki7 0:60d829a0353a 1250 /* CANIF1_MSK2, address 0x4005 002C and CANIF2_MASK2, address 0x4005 008C */
tushki7 0:60d829a0353a 1251 #define CANIFn_MSK2_MSK_MASK 0x1FFF // Identifier mask
tushki7 0:60d829a0353a 1252 #define CANIFn_MSK2_MSK_SHIFT 0
tushki7 0:60d829a0353a 1253 #define CANIFn_MSK2_MDIR (1 << 14) // Mask message direction
tushki7 0:60d829a0353a 1254 #define CANIFn_MSK2_MXTD (1 << 15) // Mask extend identifier
tushki7 0:60d829a0353a 1255
tushki7 0:60d829a0353a 1256 /* CANIF1_ARB1, address 0x4005 0030 and CANIF2_ARB1, address 0x4005 0090 */
tushki7 0:60d829a0353a 1257 #define CANIFn_ARB1_ID_MASK 0xFFFF // Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
tushki7 0:60d829a0353a 1258 #define CANIFn_ARB1_ID_SHIFT 0
tushki7 0:60d829a0353a 1259
tushki7 0:60d829a0353a 1260 /* CANIF1_ARB2, address 0x4005 0034 and CANIF2_ARB2, address 0x4005 0094 */
tushki7 0:60d829a0353a 1261 #define CANIFn_ARB2_ID_MASK 0x1FFF // Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
tushki7 0:60d829a0353a 1262 #define CANIFn_ARB2_ID_SHIFT 0
tushki7 0:60d829a0353a 1263 #define CANIFn_ARB2_DIR (1 << 13) // Message direction
tushki7 0:60d829a0353a 1264 #define CANIFn_ARB2_XTD (1 << 14) // Extend identifier
tushki7 0:60d829a0353a 1265 #define CANIFn_ARB2_MSGVAL (1 << 15) // Message valid Remark: The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.
tushki7 0:60d829a0353a 1266
tushki7 0:60d829a0353a 1267 /* CANIF1_MCTRL, address 0x4005 0038 and CANIF2_MCTRL, address 0x4005 0098 */
tushki7 0:60d829a0353a 1268 #define CANIFn_MCTRL_DLC_MASK 0x000F // Data length code Remark: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes.
tushki7 0:60d829a0353a 1269 #define CANIFn_MCTRL_DLC_SHIFT 0
tushki7 0:60d829a0353a 1270 #define CANIFn_MCTRL_EOB (1 << 7) // End of buffer
tushki7 0:60d829a0353a 1271 #define CANIFn_MCTRL_TXRQST (1 << 8) // Transmit request
tushki7 0:60d829a0353a 1272 #define CANIFn_MCTRL_RMTEN (1 << 9) // Remote enable
tushki7 0:60d829a0353a 1273 #define CANIFn_MCTRL_RXIE (1 << 10) // Receive interrupt enable
tushki7 0:60d829a0353a 1274 #define CANIFn_MCTRL_TXIE (1 << 11) // Transmit interrupt enable
tushki7 0:60d829a0353a 1275 #define CANIFn_MCTRL_UMASK (1 << 12) // Use acceptance mask Remark: If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.
tushki7 0:60d829a0353a 1276 #define CANIFn_MCTRL_INTPND (1 << 13) // Interrupt pending
tushki7 0:60d829a0353a 1277 #define CANIFn_MCTRL_MSGLST (1 << 14) // Message lost (only valid for message objects in the direction receive).
tushki7 0:60d829a0353a 1278 #define CANIFn_MCTRL_NEWDAT (1 << 15) // New data
tushki7 0:60d829a0353a 1279
tushki7 0:60d829a0353a 1280 /* CANIF1_DA1, address 0x4005 003C and CANIF2_DA1, address 0x4005 009C */
tushki7 0:60d829a0353a 1281 #define CANIFn_DA1_DATA0_MASK 0x00FF // Data byte 0
tushki7 0:60d829a0353a 1282 #define CANIFn_DA1_DATA0_SHIFT 0
tushki7 0:60d829a0353a 1283 #define CANIFn_DA1_DATA1_MASK 0xFF00 // Data byte 1
tushki7 0:60d829a0353a 1284 #define CANIFn_DA1_DATA1_SHIFT 8
tushki7 0:60d829a0353a 1285
tushki7 0:60d829a0353a 1286 /* CANIF1_DA2, address 0x4005 0040 and CANIF2_DA2, address 0x4005 00A0 */
tushki7 0:60d829a0353a 1287 #define CANIFn_DA2_DATA2_MASK 0x00FF // Data byte 2
tushki7 0:60d829a0353a 1288 #define CANIFn_DA2_DATA2_SHIFT 0
tushki7 0:60d829a0353a 1289 #define CANIFn_DA2_DATA3_MASK 0xFF00 // Data byte 3
tushki7 0:60d829a0353a 1290 #define CANIFn_DA2_DATA3_SHIFT 8
tushki7 0:60d829a0353a 1291
tushki7 0:60d829a0353a 1292 /* CANIF1_DB1, address 0x4005 0044 and CANIF2_DB1, address 0x4005 00A4 */
tushki7 0:60d829a0353a 1293 #define CANIFn_DB1_DATA4_MASK 0x00FF // Data byte 4
tushki7 0:60d829a0353a 1294 #define CANIFn_DB1_DATA4_SHIFT 0
tushki7 0:60d829a0353a 1295 #define CANIFn_DB1_DATA5_MASK 0xFF00 // Data byte 5
tushki7 0:60d829a0353a 1296 #define CANIFn_DB1_DATA5_SHIFT 8
tushki7 0:60d829a0353a 1297
tushki7 0:60d829a0353a 1298 /* CANIF1_DB2, address 0x4005 0048 and CANIF2_DB2, address 0x4005 00A8 */
tushki7 0:60d829a0353a 1299 #define CANIFn_DB2_DATA6_MASK 0x00FF // Data byte 6
tushki7 0:60d829a0353a 1300 #define CANIFn_DB2_DATA6_SHIFT 0
tushki7 0:60d829a0353a 1301 #define CANIFn_DB2_DATA7_MASK 0xFF00 // Data byte 7
tushki7 0:60d829a0353a 1302 #define CANIFn_DB2_DATA7_SHIFT 8
tushki7 0:60d829a0353a 1303
tushki7 0:60d829a0353a 1304 /* CANTXREQ1, address 0x4005 0100 */
tushki7 0:60d829a0353a 1305 #define CANTXREQ1_TXRQST_MASK 0xFFFF // Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
tushki7 0:60d829a0353a 1306 #define CANTXREQ1_TXRQST_SHIFT 0
tushki7 0:60d829a0353a 1307
tushki7 0:60d829a0353a 1308 /* CANTXREQ2, address 0x4005 0104 */
tushki7 0:60d829a0353a 1309 #define CANTXREQ2_TXRQST_MASK 0xFFFF // Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
tushki7 0:60d829a0353a 1310 #define CANTXREQ2_TXRQST_SHIFT 0
tushki7 0:60d829a0353a 1311
tushki7 0:60d829a0353a 1312 /* CANND1, address 0x4005 0120 */
tushki7 0:60d829a0353a 1313 #define CANND1_NEWDAT_MASK 0xFFFF // New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
tushki7 0:60d829a0353a 1314 #define CANND1_NEWDAT_SHIFT 0
tushki7 0:60d829a0353a 1315
tushki7 0:60d829a0353a 1316 /* CANND2, address 0x4005 0124 */
tushki7 0:60d829a0353a 1317 #define CANND2_NEWDAT_MASK 0xFFFF // New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
tushki7 0:60d829a0353a 1318 #define CANND2_NEWDAT_SHIFT 0
tushki7 0:60d829a0353a 1319
tushki7 0:60d829a0353a 1320 /* CANIR1, address 0x4005 0140 */
tushki7 0:60d829a0353a 1321 #define CANIR1_INTPND_INTERRUPT_MASK 0xFFFF // pending bits of message objects 16 to 1. essage object is ignored by the message essage object is the source of an interrupt. Reserved
tushki7 0:60d829a0353a 1322 #define CANIR1_INTPND_INTERRUPT_SHIFT 0
tushki7 0:60d829a0353a 1323
tushki7 0:60d829a0353a 1324 /* CANIR2, addresses 0x4005 0144 */
tushki7 0:60d829a0353a 1325 #define CANIR2_INTPND_MASK 0xFFFF // Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. Reserved
tushki7 0:60d829a0353a 1326 #define CANIR2_INTPND_SHIFT 0
tushki7 0:60d829a0353a 1327
tushki7 0:60d829a0353a 1328 /* CANMSGV1, addresses 0x4005 0160 */
tushki7 0:60d829a0353a 1329 #define CANMSGV1_MSGVAL_MASK 0xFFFF // Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
tushki7 0:60d829a0353a 1330 #define CANMSGV1_MSGVAL_SHIFT 0
tushki7 0:60d829a0353a 1331
tushki7 0:60d829a0353a 1332 /* CANMSGV2, address 0x4005 0164 */
tushki7 0:60d829a0353a 1333 #define CANMSGV2_MSGVAL_MASK 0xFFFF // Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
tushki7 0:60d829a0353a 1334 #define CANMSGV2_MSGVAL_SHIFT 0
tushki7 0:60d829a0353a 1335
tushki7 0:60d829a0353a 1336 /* CANCLKDIV, address 0x4005 0180 */
tushki7 0:60d829a0353a 1337 #define CANCLKDIV_CLKDIVVAL_MASK 0x000F // Clock divider value. CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3 0011: CAN_CLK = PCLK divided by 4. ... 1111: CAN_CLK = PCLK divided by 16.
tushki7 0:60d829a0353a 1338 #define CANCLKDIV_CLKDIVVAL_SHIFT 0
tushki7 0:60d829a0353a 1339
tushki7 0:60d829a0353a 1340 /* TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000 */
tushki7 0:60d829a0353a 1341 #define TMR16B0IR_MR0 (1 << 0) // Interrupt flag for match channel 0.
tushki7 0:60d829a0353a 1342 #define TMR16B0IR_MR1 (1 << 1) // Interrupt flag for match channel 1.
tushki7 0:60d829a0353a 1343 #define TMR16B0IR_MR2 (1 << 2) // Interrupt flag for match channel 2.
tushki7 0:60d829a0353a 1344 #define TMR16B0IR_MR3 (1 << 3) // Interrupt flag for match channel 3.
tushki7 0:60d829a0353a 1345 #define TMR16B0IR_CR0 (1 << 4) // Interrupt flag for capture channel 0 event.
tushki7 0:60d829a0353a 1346
tushki7 0:60d829a0353a 1347 /* TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004 */
tushki7 0:60d829a0353a 1348 #define TMR16B0TCR_CEN (1 << 0) // Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
tushki7 0:60d829a0353a 1349 #define TMR16B0TCR_CRST (1 << 1) // Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
tushki7 0:60d829a0353a 1350
tushki7 0:60d829a0353a 1351 /* TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008 */
tushki7 0:60d829a0353a 1352 #define TMR16B0TC_TC_MASK 0xFFFF // Timer counter value.
tushki7 0:60d829a0353a 1353 #define TMR16B0TC_TC_SHIFT 0
tushki7 0:60d829a0353a 1354
tushki7 0:60d829a0353a 1355 /* TMR16B0PR, address 0x4000 C00C and TMR16B1PR 0x4001 000C */
tushki7 0:60d829a0353a 1356 #define TMR16B0PR_PR_MASK 0xFFFF // Prescale max value.
tushki7 0:60d829a0353a 1357 #define TMR16B0PR_PR_SHIFT 0
tushki7 0:60d829a0353a 1358
tushki7 0:60d829a0353a 1359 /* TMR16B0PC, address 0x4001 C010 and TMR16B1PC 0x4000 0010 */
tushki7 0:60d829a0353a 1360 #define TMR16B0PC_PC_MASK 0xFFFF // Prescale counter value.
tushki7 0:60d829a0353a 1361 #define TMR16B0PC_PC_SHIFT 0
tushki7 0:60d829a0353a 1362
tushki7 0:60d829a0353a 1363 /* TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014 */
tushki7 0:60d829a0353a 1364 #define TMR16B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
tushki7 0:60d829a0353a 1365 #define TMR16B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
tushki7 0:60d829a0353a 1366 #define TMR16B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
tushki7 0:60d829a0353a 1367 #define TMR16B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
tushki7 0:60d829a0353a 1368 #define TMR16B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
tushki7 0:60d829a0353a 1369 #define TMR16B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
tushki7 0:60d829a0353a 1370 #define TMR16B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
tushki7 0:60d829a0353a 1371 #define TMR16B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
tushki7 0:60d829a0353a 1372 #define TMR16B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
tushki7 0:60d829a0353a 1373 #define TMR16B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
tushki7 0:60d829a0353a 1374 #define TMR16B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
tushki7 0:60d829a0353a 1375 #define TMR16B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
tushki7 0:60d829a0353a 1376
tushki7 0:60d829a0353a 1377 /* TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24 */
tushki7 0:60d829a0353a 1378 #define TMR16B0MR0_to_3_MATCH_MASK 0xFFFF // Timer counter match value.
tushki7 0:60d829a0353a 1379 #define TMR16B0MR0_to_3_MATCH_SHIFT 0
tushki7 0:60d829a0353a 1380
tushki7 0:60d829a0353a 1381 /* TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address 0x4001 0028 */
tushki7 0:60d829a0353a 1382 #define TMR16B0CCR_CAP0RE (1 << 0) // Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1383 #define TMR16B0CCR_CAP0FE (1 << 1) // Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1384 #define TMR16B0CCR_CAP0I (1 << 2) // Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
tushki7 0:60d829a0353a 1385
tushki7 0:60d829a0353a 1386 /* TMR16B0CR0, address 0x4000 C02C and TMR16B1CR0, address 0x4001 002C */
tushki7 0:60d829a0353a 1387 #define TMR16B0CR0_CAP_MASK 0xFFFF // Timer counter capture value.
tushki7 0:60d829a0353a 1388 #define TMR16B0CR0_CAP_SHIFT 0
tushki7 0:60d829a0353a 1389
tushki7 0:60d829a0353a 1390 /* TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C */
tushki7 0:60d829a0353a 1391 #define TMR16B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1392 #define TMR16B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1393 #define TMR16B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1394 #define TMR16B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
tushki7 0:60d829a0353a 1395 #define TMR16B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
tushki7 0:60d829a0353a 1396 #define TMR16B0EMR_EMC0_SHIFT 4
tushki7 0:60d829a0353a 1397 #define TMR16B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
tushki7 0:60d829a0353a 1398 #define TMR16B0EMR_EMC1_SHIFT 6
tushki7 0:60d829a0353a 1399 #define TMR16B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
tushki7 0:60d829a0353a 1400 #define TMR16B0EMR_EMC2_SHIFT 8
tushki7 0:60d829a0353a 1401 #define TMR16B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
tushki7 0:60d829a0353a 1402 #define TMR16B0EMR_EMC3_SHIFT 10
tushki7 0:60d829a0353a 1403
tushki7 0:60d829a0353a 1404 /* TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070 */
tushki7 0:60d829a0353a 1405 #define TMR16B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
tushki7 0:60d829a0353a 1406 #define TMR16B0CTCR_CTM_SHIFT 0
tushki7 0:60d829a0353a 1407
tushki7 0:60d829a0353a 1408 /* TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074 */
tushki7 0:60d829a0353a 1409 #define TMR16B0PWMC_PWMEN0 (1 << 0) // PWM channel0 enable
tushki7 0:60d829a0353a 1410 #define TMR16B0PWMC_PWMEN1 (1 << 1) // PWM channel1 enable
tushki7 0:60d829a0353a 1411 #define TMR16B0PWMC_PWMEN2 (1 << 2) // PWM channel2 enable
tushki7 0:60d829a0353a 1412 #define TMR16B0PWMC_PWMEN3 (1 << 3) // PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
tushki7 0:60d829a0353a 1413
tushki7 0:60d829a0353a 1414 /* TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000 */
tushki7 0:60d829a0353a 1415 #define TMR16B0IR_MR0INT (1 << 0) // Interrupt flag for match channel 0.
tushki7 0:60d829a0353a 1416 #define TMR16B0IR_MR1INT (1 << 1) // Interrupt flag for match channel 1.
tushki7 0:60d829a0353a 1417 #define TMR16B0IR_MR2INT (1 << 2) // Interrupt flag for match channel 2.
tushki7 0:60d829a0353a 1418 #define TMR16B0IR_MR3INT (1 << 3) // Interrupt flag for match channel 3.
tushki7 0:60d829a0353a 1419 #define TMR16B0IR_CR0INT (1 << 4) // Interrupt flag for capture channel 0 event.
tushki7 0:60d829a0353a 1420 #define TMR16B0IR_CR1INT (1 << 5) // Interrupt flag for capture channel 1 event.
tushki7 0:60d829a0353a 1421
tushki7 0:60d829a0353a 1422 /* TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004 */
tushki7 0:60d829a0353a 1423 #define TMR16B0TCR_CEN (1 << 0) // Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
tushki7 0:60d829a0353a 1424 #define TMR16B0TCR_CRST (1 << 1) // Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
tushki7 0:60d829a0353a 1425
tushki7 0:60d829a0353a 1426 /* TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008 */
tushki7 0:60d829a0353a 1427 #define TMR16B0TC_TC_MASK 0xFFFF // Timer counter value.
tushki7 0:60d829a0353a 1428 #define TMR16B0TC_TC_SHIFT 0
tushki7 0:60d829a0353a 1429
tushki7 0:60d829a0353a 1430 /* TMR16B0PR, address 0x4000 C00C and TMR16B1PR 0x4001 000C */
tushki7 0:60d829a0353a 1431 #define TMR16B0PR_PR_MASK 0xFFFF // Prescale max value.
tushki7 0:60d829a0353a 1432 #define TMR16B0PR_PR_SHIFT 0
tushki7 0:60d829a0353a 1433
tushki7 0:60d829a0353a 1434 /* TMR16B0PC, address 0x4001 C010 and TMR16B1PC 0x4000 0010 */
tushki7 0:60d829a0353a 1435 #define TMR16B0PC_PC_MASK 0xFFFF // Prescale counter value.
tushki7 0:60d829a0353a 1436 #define TMR16B0PC_PC_SHIFT 0
tushki7 0:60d829a0353a 1437
tushki7 0:60d829a0353a 1438 /* TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014 */
tushki7 0:60d829a0353a 1439 #define TMR16B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
tushki7 0:60d829a0353a 1440 #define TMR16B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
tushki7 0:60d829a0353a 1441 #define TMR16B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
tushki7 0:60d829a0353a 1442 #define TMR16B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
tushki7 0:60d829a0353a 1443 #define TMR16B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
tushki7 0:60d829a0353a 1444 #define TMR16B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
tushki7 0:60d829a0353a 1445 #define TMR16B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
tushki7 0:60d829a0353a 1446 #define TMR16B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
tushki7 0:60d829a0353a 1447 #define TMR16B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
tushki7 0:60d829a0353a 1448 #define TMR16B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
tushki7 0:60d829a0353a 1449 #define TMR16B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
tushki7 0:60d829a0353a 1450 #define TMR16B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
tushki7 0:60d829a0353a 1451
tushki7 0:60d829a0353a 1452 /* TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24 */
tushki7 0:60d829a0353a 1453 #define TMR16B0MR0_to_3_MATCH_MASK 0xFFFF // Timer counter match value.
tushki7 0:60d829a0353a 1454 #define TMR16B0MR0_to_3_MATCH_SHIFT 0
tushki7 0:60d829a0353a 1455
tushki7 0:60d829a0353a 1456 /* TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address 0x4001 0028 */
tushki7 0:60d829a0353a 1457 #define TMR16B0CCR_CAP0RE (1 << 0) // Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1458 #define TMR16B0CCR_CAP0FE (1 << 1) // Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1459 #define TMR16B0CCR_CAP0I (1 << 2) // Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
tushki7 0:60d829a0353a 1460 #define TMR16B0CCR_CAP1RE (1 << 3) // Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1461 #define TMR16B0CCR_CAP1FE (1 << 4) // Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1462 #define TMR16B0CCR_CAP1I (1 << 5) // Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.
tushki7 0:60d829a0353a 1463
tushki7 0:60d829a0353a 1464 /* TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C */
tushki7 0:60d829a0353a 1465 #define TMR16B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1466 #define TMR16B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1467 #define TMR16B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1468 #define TMR16B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
tushki7 0:60d829a0353a 1469 #define TMR16B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
tushki7 0:60d829a0353a 1470 #define TMR16B0EMR_EMC0_SHIFT 4
tushki7 0:60d829a0353a 1471 #define TMR16B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
tushki7 0:60d829a0353a 1472 #define TMR16B0EMR_EMC1_SHIFT 6
tushki7 0:60d829a0353a 1473 #define TMR16B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
tushki7 0:60d829a0353a 1474 #define TMR16B0EMR_EMC2_SHIFT 8
tushki7 0:60d829a0353a 1475 #define TMR16B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
tushki7 0:60d829a0353a 1476 #define TMR16B0EMR_EMC3_SHIFT 10
tushki7 0:60d829a0353a 1477
tushki7 0:60d829a0353a 1478 /* TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070 */
tushki7 0:60d829a0353a 1479 #define TMR16B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
tushki7 0:60d829a0353a 1480 #define TMR16B0CTCR_CTM_SHIFT 0
tushki7 0:60d829a0353a 1481 #define TMR16B0CTCR_SELCC_MASK 0x00E0 // When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
tushki7 0:60d829a0353a 1482 #define TMR16B0CTCR_SELCC_SHIFT 5
tushki7 0:60d829a0353a 1483
tushki7 0:60d829a0353a 1484 /* TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074 */
tushki7 0:60d829a0353a 1485 #define TMR16B0PWMC_PWMEN0 (1 << 0) // PWM channel0 enable
tushki7 0:60d829a0353a 1486 #define TMR16B0PWMC_PWMEN1 (1 << 1) // PWM channel1 enable
tushki7 0:60d829a0353a 1487 #define TMR16B0PWMC_PWMEN2 (1 << 2) // PWM channel2 enable
tushki7 0:60d829a0353a 1488 #define TMR16B0PWMC_PWMEN3 (1 << 3) // PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
tushki7 0:60d829a0353a 1489
tushki7 0:60d829a0353a 1490 /* TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000 */
tushki7 0:60d829a0353a 1491 #define TMR32B0IR_MR0_INTERRUPT (1 << 0) // Interrupt flag for match channel 0.
tushki7 0:60d829a0353a 1492 #define TMR32B0IR_MR1_INTERRUPT (1 << 1) // Interrupt flag for match channel 1.
tushki7 0:60d829a0353a 1493 #define TMR32B0IR_MR2_INTERRUPT (1 << 2) // Interrupt flag for match channel 2.
tushki7 0:60d829a0353a 1494 #define TMR32B0IR_MR3_INTERRUPT (1 << 3) // Interrupt flag for match channel 3.
tushki7 0:60d829a0353a 1495 #define TMR32B0IR_CR0_INTERRUPT (1 << 4) // Interrupt flag for capture channel 0 event.
tushki7 0:60d829a0353a 1496
tushki7 0:60d829a0353a 1497 /* TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR - address 0x4001 8004 */
tushki7 0:60d829a0353a 1498 #define TMR32B0TCR_CEN (1 << 0) // When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
tushki7 0:60d829a0353a 1499 #define TMR32B0TCR_CRST (1 << 1) // When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
tushki7 0:60d829a0353a 1500
tushki7 0:60d829a0353a 1501 /* TMR32B0TC, address 0x4001 4008 and TMR32B1TC 0x4001 8008 */
tushki7 0:60d829a0353a 1502 #define TMR32B0TC_TC_MASK 0xFFFFFFFF // Timer counter value.
tushki7 0:60d829a0353a 1503 #define TMR32B0TC_TC_SHIFT 0
tushki7 0:60d829a0353a 1504
tushki7 0:60d829a0353a 1505 /* TMR32B0PR, address 0x4001 400C and TMR32B1PR 0x4001 800C */
tushki7 0:60d829a0353a 1506 #define TMR32B0PR_PR_MASK 0xFFFFFFFF // Prescale value.
tushki7 0:60d829a0353a 1507 #define TMR32B0PR_PR_SHIFT 0
tushki7 0:60d829a0353a 1508
tushki7 0:60d829a0353a 1509 /* TMR32B0PC, address 0x4001 4010 and TMR32B1PC 0x4001 8010 */
tushki7 0:60d829a0353a 1510 #define TMR32B0PC_PC_MASK 0xFFFFFFFF // Prescale counter value.
tushki7 0:60d829a0353a 1511 #define TMR32B0PC_PC_SHIFT 0
tushki7 0:60d829a0353a 1512
tushki7 0:60d829a0353a 1513 /* TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014 */
tushki7 0:60d829a0353a 1514 #define TMR32B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
tushki7 0:60d829a0353a 1515 #define TMR32B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
tushki7 0:60d829a0353a 1516 #define TMR32B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
tushki7 0:60d829a0353a 1517 #define TMR32B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
tushki7 0:60d829a0353a 1518 #define TMR32B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
tushki7 0:60d829a0353a 1519 #define TMR32B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
tushki7 0:60d829a0353a 1520 #define TMR32B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
tushki7 0:60d829a0353a 1521 #define TMR32B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
tushki7 0:60d829a0353a 1522 #define TMR32B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
tushki7 0:60d829a0353a 1523 #define TMR32B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
tushki7 0:60d829a0353a 1524 #define TMR32B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
tushki7 0:60d829a0353a 1525 #define TMR32B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
tushki7 0:60d829a0353a 1526
tushki7 0:60d829a0353a 1527 /* TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and TMR32B1MR0 to 3, addresses 0x4001 8018 to 24 */
tushki7 0:60d829a0353a 1528 #define TMR32B0MRn_MATCH_MASK 0xFFFFFFFF // Timer counter match value.
tushki7 0:60d829a0353a 1529 #define TMR32B0MRn_MATCH_SHIFT 0
tushki7 0:60d829a0353a 1530
tushki7 0:60d829a0353a 1531 /* TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address 0x4001 8028 */
tushki7 0:60d829a0353a 1532 #define TMR32B0CCR_CAP0RE (1 << 0) // Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1533 #define TMR32B0CCR_CAP0FE (1 << 1) // Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1534 #define TMR32B0CCR_CAP0I (1 << 2) // Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
tushki7 0:60d829a0353a 1535
tushki7 0:60d829a0353a 1536 /* TMR32B0CR0, addresses 0x4001 402C and TMR32B1CR0, addresses 0x4001 802C */
tushki7 0:60d829a0353a 1537 #define TMR32B0CR0_CAP_MASK 0xFFFFFFFF // Timer counter capture value.
tushki7 0:60d829a0353a 1538 #define TMR32B0CR0_CAP_SHIFT 0
tushki7 0:60d829a0353a 1539
tushki7 0:60d829a0353a 1540 /* TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C */
tushki7 0:60d829a0353a 1541 #define TMR32B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1542 #define TMR32B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1543 #define TMR32B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1544 #define TMR32B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1545 #define TMR32B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
tushki7 0:60d829a0353a 1546 #define TMR32B0EMR_EMC0_SHIFT 4
tushki7 0:60d829a0353a 1547 #define TMR32B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
tushki7 0:60d829a0353a 1548 #define TMR32B0EMR_EMC1_SHIFT 6
tushki7 0:60d829a0353a 1549 #define TMR32B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
tushki7 0:60d829a0353a 1550 #define TMR32B0EMR_EMC2_SHIFT 8
tushki7 0:60d829a0353a 1551 #define TMR32B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
tushki7 0:60d829a0353a 1552 #define TMR32B0EMR_EMC3_SHIFT 10
tushki7 0:60d829a0353a 1553
tushki7 0:60d829a0353a 1554 /* TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070 */
tushki7 0:60d829a0353a 1555 #define TMR32B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
tushki7 0:60d829a0353a 1556 #define TMR32B0CTCR_CTM_SHIFT 0
tushki7 0:60d829a0353a 1557 #define TMR32B0CTCR_CIS_MASK 0x000C // Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
tushki7 0:60d829a0353a 1558 #define TMR32B0CTCR_CIS_SHIFT 2
tushki7 0:60d829a0353a 1559
tushki7 0:60d829a0353a 1560 /* TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074 */
tushki7 0:60d829a0353a 1561 #define TMR32B0PWMC_PWMEN0 (1 << 0) // PWM channel 0 enable
tushki7 0:60d829a0353a 1562 #define TMR32B0PWMC_PWMEN1 (1 << 1) // PWM channel 1 enable
tushki7 0:60d829a0353a 1563 #define TMR32B0PWMC_PWMEN2 (1 << 2) // PWM channel 2 enable
tushki7 0:60d829a0353a 1564 #define TMR32B0PWMC_PWMEN3 (1 << 3) // PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
tushki7 0:60d829a0353a 1565
tushki7 0:60d829a0353a 1566 /* TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000 */
tushki7 0:60d829a0353a 1567 #define TMR32B0IR_MR0INT (1 << 0) // Interrupt flag for match channel 0.
tushki7 0:60d829a0353a 1568 #define TMR32B0IR_MR1INT (1 << 1) // Interrupt flag for match channel 1.
tushki7 0:60d829a0353a 1569 #define TMR32B0IR_MR2INT (1 << 2) // Interrupt flag for match channel 2.
tushki7 0:60d829a0353a 1570 #define TMR32B0IR_MR3INT (1 << 3) // Interrupt flag for match channel 3.
tushki7 0:60d829a0353a 1571 #define TMR32B0IR_CR0INT (1 << 4) // Interrupt flag for capture channel 0 event.
tushki7 0:60d829a0353a 1572 #define TMR32B0IR_CR1INT (1 << 5) // Interrupt flag for capture channel 1 event.
tushki7 0:60d829a0353a 1573
tushki7 0:60d829a0353a 1574 /* TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR - address 0x4001 8004 */
tushki7 0:60d829a0353a 1575 #define TMR32B0TCR_CEN (1 << 0) // When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
tushki7 0:60d829a0353a 1576 #define TMR32B0TCR_CRST (1 << 1) // When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
tushki7 0:60d829a0353a 1577
tushki7 0:60d829a0353a 1578 /* TMR32B0TC, address 0x4001 4008 and TMR32B1TC 0x4001 8008 */
tushki7 0:60d829a0353a 1579 #define TMR32B0TC_TC_MASK 0xFFFFFFFF // Timer counter value.
tushki7 0:60d829a0353a 1580 #define TMR32B0TC_TC_SHIFT 0
tushki7 0:60d829a0353a 1581
tushki7 0:60d829a0353a 1582 /* TMR32B0PR, address 0x4001 400C and TMR32B1PR 0x4001 800C */
tushki7 0:60d829a0353a 1583 #define TMR32B0PR_PR_MASK 0xFFFFFFFF // Prescale value.
tushki7 0:60d829a0353a 1584 #define TMR32B0PR_PR_SHIFT 0
tushki7 0:60d829a0353a 1585
tushki7 0:60d829a0353a 1586 /* TMR32B0PC, address 0x4001 4010 and TMR32B1PC 0x4001 8010 */
tushki7 0:60d829a0353a 1587 #define TMR32B0PC_PC_MASK 0xFFFFFFFF // Prescale counter value.
tushki7 0:60d829a0353a 1588 #define TMR32B0PC_PC_SHIFT 0
tushki7 0:60d829a0353a 1589
tushki7 0:60d829a0353a 1590 /* TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014 */
tushki7 0:60d829a0353a 1591 #define TMR32B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
tushki7 0:60d829a0353a 1592 #define TMR32B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
tushki7 0:60d829a0353a 1593 #define TMR32B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
tushki7 0:60d829a0353a 1594 #define TMR32B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
tushki7 0:60d829a0353a 1595 #define TMR32B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
tushki7 0:60d829a0353a 1596 #define TMR32B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
tushki7 0:60d829a0353a 1597 #define TMR32B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
tushki7 0:60d829a0353a 1598 #define TMR32B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
tushki7 0:60d829a0353a 1599 #define TMR32B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
tushki7 0:60d829a0353a 1600 #define TMR32B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
tushki7 0:60d829a0353a 1601 #define TMR32B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
tushki7 0:60d829a0353a 1602 #define TMR32B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
tushki7 0:60d829a0353a 1603
tushki7 0:60d829a0353a 1604 /* TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and TMR32B1MR0 to 3, addresses 0x4001 8018 to 24 */
tushki7 0:60d829a0353a 1605 #define TMR32B0MRn_MATCH_MASK 0xFFFFFFFF // Timer counter match value.
tushki7 0:60d829a0353a 1606 #define TMR32B0MRn_MATCH_SHIFT 0
tushki7 0:60d829a0353a 1607
tushki7 0:60d829a0353a 1608 /* TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address 0x4001 8028 */
tushki7 0:60d829a0353a 1609 #define TMR32B0CCR_CAP0RE (1 << 0) // Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1610 #define TMR32B0CCR_CAP0FE (1 << 1) // Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1611 #define TMR32B0CCR_CAP0I (1 << 2) // Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
tushki7 0:60d829a0353a 1612 #define TMR32B0CCR_CAP1RE (1 << 3) // Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1613 #define TMR32B0CCR_CAP1FE (1 << 4) // Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
tushki7 0:60d829a0353a 1614 #define TMR32B0CCR_CAP1I (1 << 5) // Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.
tushki7 0:60d829a0353a 1615
tushki7 0:60d829a0353a 1616 /* TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C */
tushki7 0:60d829a0353a 1617 #define TMR32B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1618 #define TMR32B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1619 #define TMR32B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1620 #define TMR32B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
tushki7 0:60d829a0353a 1621 #define TMR32B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
tushki7 0:60d829a0353a 1622 #define TMR32B0EMR_EMC0_SHIFT 4
tushki7 0:60d829a0353a 1623 #define TMR32B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
tushki7 0:60d829a0353a 1624 #define TMR32B0EMR_EMC1_SHIFT 6
tushki7 0:60d829a0353a 1625 #define TMR32B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
tushki7 0:60d829a0353a 1626 #define TMR32B0EMR_EMC2_SHIFT 8
tushki7 0:60d829a0353a 1627 #define TMR32B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
tushki7 0:60d829a0353a 1628 #define TMR32B0EMR_EMC3_SHIFT 10
tushki7 0:60d829a0353a 1629
tushki7 0:60d829a0353a 1630 /* TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070 */
tushki7 0:60d829a0353a 1631 #define TMR32B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
tushki7 0:60d829a0353a 1632 #define TMR32B0CTCR_CTM_SHIFT 0
tushki7 0:60d829a0353a 1633 #define TMR32B0CTCR_CIS_MASK 0x000C // Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
tushki7 0:60d829a0353a 1634 #define TMR32B0CTCR_CIS_SHIFT 2
tushki7 0:60d829a0353a 1635 #define TMR32B0CTCR_ENCC (1 << 4) // Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
tushki7 0:60d829a0353a 1636 #define TMR32B0CTCR_SELCC_MASK 0x00E0 // When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
tushki7 0:60d829a0353a 1637 #define TMR32B0CTCR_SELCC_SHIFT 5
tushki7 0:60d829a0353a 1638
tushki7 0:60d829a0353a 1639 /* TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074 */
tushki7 0:60d829a0353a 1640 #define TMR32B0PWMC_PWMEN0 (1 << 0) // PWM channel 0 enable
tushki7 0:60d829a0353a 1641 #define TMR32B0PWMC_PWMEN1 (1 << 1) // PWM channel 1 enable
tushki7 0:60d829a0353a 1642 #define TMR32B0PWMC_PWMEN2 (1 << 2) // PWM channel 2 enable
tushki7 0:60d829a0353a 1643 #define TMR32B0PWMC_PWMEN3 (1 << 3) // PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
tushki7 0:60d829a0353a 1644
tushki7 0:60d829a0353a 1645 /* WDMOD - 0x4000 4000 */
tushki7 0:60d829a0353a 1646 #define WDMOD_WDEN (1 << 0) // Watchdog enable bit. This bit is Set Only. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one.
tushki7 0:60d829a0353a 1647 #define WDMOD_WDRESET (1 << 1) // Watchdog reset enable bit. This bit is Set Only.
tushki7 0:60d829a0353a 1648 #define WDMOD_WDTOF (1 << 2) // Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1.
tushki7 0:60d829a0353a 1649 #define WDMOD_WDINT (1 << 3) // Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
tushki7 0:60d829a0353a 1650 #define WDMOD_WDPROTECT (1 << 4) // Watchdog update mode. This bit is Set Only.
tushki7 0:60d829a0353a 1651
tushki7 0:60d829a0353a 1652 /* WDTC - 0x4000 4004 */
tushki7 0:60d829a0353a 1653 #define WDTC_COUNT_MASK 0xFFFFFF // Watchdog time-out interval.
tushki7 0:60d829a0353a 1654 #define WDTC_COUNT_SHIFT 0
tushki7 0:60d829a0353a 1655
tushki7 0:60d829a0353a 1656 /* WDFEED - 0x4000 4008 */
tushki7 0:60d829a0353a 1657 #define WDFEED_FEED_MASK 0x00FF // Feed value should be 0xAA followed by 0x55.
tushki7 0:60d829a0353a 1658 #define WDFEED_FEED_SHIFT 0
tushki7 0:60d829a0353a 1659
tushki7 0:60d829a0353a 1660 /* WDTV - 0x4000 400C */
tushki7 0:60d829a0353a 1661 #define WDTV_COUNT_MASK 0xFFFFFF // Counter timer value.
tushki7 0:60d829a0353a 1662 #define WDTV_COUNT_SHIFT 0
tushki7 0:60d829a0353a 1663
tushki7 0:60d829a0353a 1664 /* WDWARNINT - 0x4000 4014 */
tushki7 0:60d829a0353a 1665 #define WDWARNINT_WARNINT_MASK 0x03FF // Watchdog warning interrupt compare value.
tushki7 0:60d829a0353a 1666 #define WDWARNINT_WARNINT_SHIFT 0
tushki7 0:60d829a0353a 1667
tushki7 0:60d829a0353a 1668 /* WDWINDOW - 0x4000 4018 */
tushki7 0:60d829a0353a 1669 #define WDWINDOW_WINDOW_MASK 0xFFFFFF // Watchdog window value.
tushki7 0:60d829a0353a 1670 #define WDWINDOW_WINDOW_SHIFT 0
tushki7 0:60d829a0353a 1671
tushki7 0:60d829a0353a 1672 /* WDMOD - address 0x4000 4000 */
tushki7 0:60d829a0353a 1673 #define WDMOD_WDEN (1 << 0) // WDEN Watchdog enable bit (Set Only). When 1, the watchdog timer is running. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. The clock source lock feature is not available on all parts, see Section 23.1).
tushki7 0:60d829a0353a 1674 #define WDMOD_WDRESET_WDRESET (1 << 1) // Watchdog reset enable bit (Set Only). When 1, og time-out will cause a chip reset.
tushki7 0:60d829a0353a 1675 #define WDMOD_WDTOF (1 << 2) // WDTOF Watchdog time-out flag. Set when the watchdog
tushki7 0:60d829a0353a 1676 #define WDMOD_WDINT (1 << 3) // WDINT Watchdog interrupt flag (Read Only, not clearable by software).
tushki7 0:60d829a0353a 1677
tushki7 0:60d829a0353a 1678 /* WDTC - address 0x4000 4004 */
tushki7 0:60d829a0353a 1679 #define WDTC_COUNT_MASK 0xFFFFFF // Watchdog time-out interval.
tushki7 0:60d829a0353a 1680 #define WDTC_COUNT_SHIFT 0
tushki7 0:60d829a0353a 1681
tushki7 0:60d829a0353a 1682 /* WDFEED - address 0x4000 4008 */
tushki7 0:60d829a0353a 1683 #define WDFEED_FEED_MASK 0x00FF // Feed value should be 0xAA followed by 0x55.
tushki7 0:60d829a0353a 1684 #define WDFEED_FEED_SHIFT 0
tushki7 0:60d829a0353a 1685
tushki7 0:60d829a0353a 1686 /* WDTV - address 0x4000 000C */
tushki7 0:60d829a0353a 1687 #define WDTV_COUNT_MASK 0xFFFFFF // Counter timer value.
tushki7 0:60d829a0353a 1688 #define WDTV_COUNT_SHIFT 0
tushki7 0:60d829a0353a 1689
tushki7 0:60d829a0353a 1690 /* SYST_CSR - 0xE000 E010 */
tushki7 0:60d829a0353a 1691 #define SYST_CSR_ENABLE (1 << 0) // System Tick counter enable. When 1, the counter is enabled. When 0, the counter is disabled.
tushki7 0:60d829a0353a 1692 #define SYST_CSR_TICKINT (1 << 1) // System Tick interrupt enable. When 1, the System Tick interrupt 0 is enabled. When 0, the System Tick interrupt is disabled. When enabled, the interrupt is generated when the System Tick counter counts down to 0.
tushki7 0:60d829a0353a 1693 #define SYST_CSR_CLKSOURCE (1 << 2) // System Tick clock source selection. When 1, the system clock (CPU) clock is selected. When 0, the system clock/2 is selected as the reference clock.
tushki7 0:60d829a0353a 1694 #define SYST_CSR_COUNTFLAG (1 << 16) // Returns 1 if the SysTick timer counted to 0 since the last read of this register. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
tushki7 0:60d829a0353a 1695
tushki7 0:60d829a0353a 1696 /* SYST_RVR - 0xE000 E014 */
tushki7 0:60d829a0353a 1697 #define SYST_RVR_RELOAD_MASK 0xFFFFFF // This is the value that is loaded into the System Tick counter when it 0 counts down to 0.
tushki7 0:60d829a0353a 1698 #define SYST_RVR_RELOAD_SHIFT 0
tushki7 0:60d829a0353a 1699
tushki7 0:60d829a0353a 1700 /* SYST_CVR - 0xE000 E018 */
tushki7 0:60d829a0353a 1701 #define SYST_CVR_CURRENT_MASK 0xFFFFFF // Reading this register returns the current value of the System Tick counter. Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL.
tushki7 0:60d829a0353a 1702 #define SYST_CVR_CURRENT_SHIFT 0
tushki7 0:60d829a0353a 1703
tushki7 0:60d829a0353a 1704 /* SYST_CALIB - 0xE000 E01C */
tushki7 0:60d829a0353a 1705 #define SYST_CALIB_TENMS_MASK 0xFFFFFF // See Table 461.
tushki7 0:60d829a0353a 1706 #define SYST_CALIB_TENMS_SHIFT 0
tushki7 0:60d829a0353a 1707 #define SYST_CALIB_SKEW (1 << 30) // See Table 461.
tushki7 0:60d829a0353a 1708 #define SYST_CALIB_NOREF (1 << 31) // See Table 461.
tushki7 0:60d829a0353a 1709
tushki7 0:60d829a0353a 1710 /* AD0CR - address 0x4001 C000 */
tushki7 0:60d829a0353a 1711 #define AD0CR_SEL_MASK 0x00FF // Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin 0x00 AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).
tushki7 0:60d829a0353a 1712 #define AD0CR_SEL_SHIFT 0
tushki7 0:60d829a0353a 1713 #define AD0CR_CLKDIV_MASK 0xFF00 // The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which 0 should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
tushki7 0:60d829a0353a 1714 #define AD0CR_CLKDIV_SHIFT 8
tushki7 0:60d829a0353a 1715 #define AD0CR_BURST (1 << 16) // Burst mode Remark: If BURST is set to 1, the ADGINTEN bit in the AD0INTEN register (Table 365) must be set to 0.
tushki7 0:60d829a0353a 1716 #define AD0CR_CLKS_MASK 0xE0000 // This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
tushki7 0:60d829a0353a 1717 #define AD0CR_CLKS_SHIFT 17
tushki7 0:60d829a0353a 1718 #define AD0CR_START_MASK 0x7000000 // When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
tushki7 0:60d829a0353a 1719 #define AD0CR_START_SHIFT 24
tushki7 0:60d829a0353a 1720 #define AD0CR_EDGE (1 << 27) // This bit is significant only when the START field contains 010-111. In these cases:
tushki7 0:60d829a0353a 1721
tushki7 0:60d829a0353a 1722 /* AD0GDR - address 0x4001 C004 */
tushki7 0:60d829a0353a 1723 #define AD0GDR_V_VREF_MASK 0xFFC0 // When DONE is 1, this field contains a binary fraction representing X the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
tushki7 0:60d829a0353a 1724 #define AD0GDR_V_VREF_SHIFT 6
tushki7 0:60d829a0353a 1725 #define AD0GDR_CHN_MASK 0x7000000 // These bits contain the channel from which the result bits V_VREF X were converted.
tushki7 0:60d829a0353a 1726 #define AD0GDR_CHN_SHIFT 24
tushki7 0:60d829a0353a 1727 #define AD0GDR_OVERRUN (1 << 30) // This bit is 1 in burst mode if the results of one or more conversions 0 was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.
tushki7 0:60d829a0353a 1728 #define AD0GDR_DONE (1 << 31) // This bit is set to 1 when an A/D conversion completes. It is cleared 0 when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
tushki7 0:60d829a0353a 1729
tushki7 0:60d829a0353a 1730 /* AD0INTEN - address 0x4001 C00C */
tushki7 0:60d829a0353a 1731 #define AD0INTEN_ADINTEN_MASK 0x00FF // These bits allow control over which A/D channels generate 0x00 interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
tushki7 0:60d829a0353a 1732 #define AD0INTEN_ADINTEN_SHIFT 0
tushki7 0:60d829a0353a 1733 #define AD0INTEN_ADGINTEN (1 << 8) // When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. Remark: This bit must be set to 0 in burst mode (BURST = 1 in the AD0CR register). Reserved. Unused, always 0.
tushki7 0:60d829a0353a 1734
tushki7 0:60d829a0353a 1735 /* AD0DR0 to AD0DR7 - addresses 0x4001 C010 to 0x4001 C02C */
tushki7 0:60d829a0353a 1736 #define AD0DRn_V_VREF_MASK 0xFFC0 // When DONE is 1, this field contains a binary fraction representing the NA voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. Reserved.
tushki7 0:60d829a0353a 1737 #define AD0DRn_V_VREF_SHIFT 6
tushki7 0:60d829a0353a 1738 #define AD0DRn_OVERRUN (1 << 30) // This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
tushki7 0:60d829a0353a 1739 #define AD0DRn_DONE (1 << 31) // This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
tushki7 0:60d829a0353a 1740
tushki7 0:60d829a0353a 1741 /* AD0STAT - address 0x4001 C030 */
tushki7 0:60d829a0353a 1742 #define AD0STAT_DONE_MASK 0x00FF // These bits mirror the DONE status flags that appear in the result register for each A/D channel n.
tushki7 0:60d829a0353a 1743 #define AD0STAT_DONE_SHIFT 0
tushki7 0:60d829a0353a 1744 #define AD0STAT_OVERRUN_MASK 0xFF00 // These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
tushki7 0:60d829a0353a 1745 #define AD0STAT_OVERRUN_SHIFT 8
tushki7 0:60d829a0353a 1746 #define AD0STAT_ADINT (1 << 16) // This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. Reserved. Unused, always 0.
tushki7 0:60d829a0353a 1747
tushki7 0:60d829a0353a 1748 /* FLASHCFG, address 0x4003 C010 */
tushki7 0:60d829a0353a 1749 #define FLASHCFG_FLASHTIM_MASK 0x0003 // Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
tushki7 0:60d829a0353a 1750 #define FLASHCFG_FLASHTIM_SHIFT 0
tushki7 0:60d829a0353a 1751
tushki7 0:60d829a0353a 1752 /* FMSSTART - 0x4003 C020 */
tushki7 0:60d829a0353a 1753 #define FMSSTART_START_MASK 0x1FFFF // Signature generation start address (corresponds to AHB byte address bits[20:4]).
tushki7 0:60d829a0353a 1754 #define FMSSTART_START_SHIFT 0
tushki7 0:60d829a0353a 1755
tushki7 0:60d829a0353a 1756 /* FMSSTOP - 0x4003 C024 */
tushki7 0:60d829a0353a 1757 #define FMSSTOP_STOP_MASK 0x1FFFF // BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).
tushki7 0:60d829a0353a 1758 #define FMSSTOP_STOP_SHIFT 0
tushki7 0:60d829a0353a 1759 #define FMSSTOP_SIG_START (1 << 17) // Start control bit for signature generation.
tushki7 0:60d829a0353a 1760
tushki7 0:60d829a0353a 1761 /* FMSTAT - 0x4003 CFE0 */
tushki7 0:60d829a0353a 1762 #define FMSTAT_SIG_DONE (1 << 2) // When 1, a previously started signature generation has 0 completed. See FMSTATCLR register description for clearing this flag.
tushki7 0:60d829a0353a 1763
tushki7 0:60d829a0353a 1764 /* FMSTATCLR - 0x0x4003 CFE8 */
tushki7 0:60d829a0353a 1765 #define FMSTATCLR_SIG_DONE_CLR (1 << 2) // Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.
tushki7 0:60d829a0353a 1766
tushki7 0:60d829a0353a 1767
tushki7 0:60d829a0353a 1768 #endif