Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_KL43Z/MKL43Z4.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /*
tushki7 0:60d829a0353a 2 ** ###################################################################
tushki7 0:60d829a0353a 3 ** Processors: MKL43Z256VLH4
tushki7 0:60d829a0353a 4 ** MKL43Z128VLH4
tushki7 0:60d829a0353a 5 ** MKL43Z64VLH4
tushki7 0:60d829a0353a 6 ** MKL43Z256VMP4
tushki7 0:60d829a0353a 7 ** MKL43Z128VMP4
tushki7 0:60d829a0353a 8 ** MKL43Z64VMP4
tushki7 0:60d829a0353a 9 **
tushki7 0:60d829a0353a 10 ** Compilers: Keil ARM C/C++ Compiler
tushki7 0:60d829a0353a 11 ** Freescale C/C++ for Embedded ARM
tushki7 0:60d829a0353a 12 ** GNU C Compiler
tushki7 0:60d829a0353a 13 ** GNU C Compiler - CodeSourcery Sourcery G++
tushki7 0:60d829a0353a 14 ** IAR ANSI C/C++ Compiler for ARM
tushki7 0:60d829a0353a 15 **
tushki7 0:60d829a0353a 16 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
tushki7 0:60d829a0353a 17 ** Version: rev. 1.5, 2014-09-05
tushki7 0:60d829a0353a 18 ** Build: b140905
tushki7 0:60d829a0353a 19 **
tushki7 0:60d829a0353a 20 ** Abstract:
tushki7 0:60d829a0353a 21 ** CMSIS Peripheral Access Layer for MKL43Z4
tushki7 0:60d829a0353a 22 **
tushki7 0:60d829a0353a 23 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
tushki7 0:60d829a0353a 24 ** All rights reserved.
tushki7 0:60d829a0353a 25 **
tushki7 0:60d829a0353a 26 ** Redistribution and use in source and binary forms, with or without modification,
tushki7 0:60d829a0353a 27 ** are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 28 **
tushki7 0:60d829a0353a 29 ** o Redistributions of source code must retain the above copyright notice, this list
tushki7 0:60d829a0353a 30 ** of conditions and the following disclaimer.
tushki7 0:60d829a0353a 31 **
tushki7 0:60d829a0353a 32 ** o Redistributions in binary form must reproduce the above copyright notice, this
tushki7 0:60d829a0353a 33 ** list of conditions and the following disclaimer in the documentation and/or
tushki7 0:60d829a0353a 34 ** other materials provided with the distribution.
tushki7 0:60d829a0353a 35 **
tushki7 0:60d829a0353a 36 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
tushki7 0:60d829a0353a 37 ** contributors may be used to endorse or promote products derived from this
tushki7 0:60d829a0353a 38 ** software without specific prior written permission.
tushki7 0:60d829a0353a 39 **
tushki7 0:60d829a0353a 40 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
tushki7 0:60d829a0353a 41 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
tushki7 0:60d829a0353a 42 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7 0:60d829a0353a 43 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
tushki7 0:60d829a0353a 44 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
tushki7 0:60d829a0353a 45 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
tushki7 0:60d829a0353a 46 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
tushki7 0:60d829a0353a 47 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
tushki7 0:60d829a0353a 48 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
tushki7 0:60d829a0353a 49 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 50 **
tushki7 0:60d829a0353a 51 ** http: www.freescale.com
tushki7 0:60d829a0353a 52 ** mail: support@freescale.com
tushki7 0:60d829a0353a 53 **
tushki7 0:60d829a0353a 54 ** Revisions:
tushki7 0:60d829a0353a 55 ** - rev. 1.0 (2014-03-27)
tushki7 0:60d829a0353a 56 ** Initial version.
tushki7 0:60d829a0353a 57 ** - rev. 1.1 (2014-05-26)
tushki7 0:60d829a0353a 58 ** I2S registers TCR2/RCR2 and others were changed.
tushki7 0:60d829a0353a 59 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
tushki7 0:60d829a0353a 60 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
tushki7 0:60d829a0353a 61 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
tushki7 0:60d829a0353a 62 ** Clock configuration for high range external oscillator has been added.
tushki7 0:60d829a0353a 63 ** RFSYS module access has been added.
tushki7 0:60d829a0353a 64 ** - rev. 1.2 (2014-07-10)
tushki7 0:60d829a0353a 65 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
tushki7 0:60d829a0353a 66 ** UART0 - UART0 module renamed to UART2.
tushki7 0:60d829a0353a 67 ** I2S - removed MDR register.
tushki7 0:60d829a0353a 68 ** - rev. 1.3 (2014-08-21)
tushki7 0:60d829a0353a 69 ** UART2 - Removed ED register.
tushki7 0:60d829a0353a 70 ** UART2 - Removed MODEM register.
tushki7 0:60d829a0353a 71 ** UART2 - Removed IR register.
tushki7 0:60d829a0353a 72 ** UART2 - Removed PFIFO register.
tushki7 0:60d829a0353a 73 ** UART2 - Removed CFIFO register.
tushki7 0:60d829a0353a 74 ** UART2 - Removed SFIFO register.
tushki7 0:60d829a0353a 75 ** UART2 - Removed TWFIFO register.
tushki7 0:60d829a0353a 76 ** UART2 - Removed TCFIFO register.
tushki7 0:60d829a0353a 77 ** UART2 - Removed RWFIFO register.
tushki7 0:60d829a0353a 78 ** UART2 - Removed RCFIFO register.
tushki7 0:60d829a0353a 79 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
tushki7 0:60d829a0353a 80 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
tushki7 0:60d829a0353a 81 ** SIM - Removed bitfield DIEID in SDID register.
tushki7 0:60d829a0353a 82 ** - rev. 1.4 (2014-09-01)
tushki7 0:60d829a0353a 83 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
tushki7 0:60d829a0353a 84 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
tushki7 0:60d829a0353a 85 ** - rev. 1.5 (2014-09-05)
tushki7 0:60d829a0353a 86 ** USB - USBEN bitfield of the USB0_CTL renamed to USBENSOFEN.
tushki7 0:60d829a0353a 87 **
tushki7 0:60d829a0353a 88 ** ###################################################################
tushki7 0:60d829a0353a 89 */
tushki7 0:60d829a0353a 90
tushki7 0:60d829a0353a 91 /*!
tushki7 0:60d829a0353a 92 * @file MKL43Z4.h
tushki7 0:60d829a0353a 93 * @version 1.5
tushki7 0:60d829a0353a 94 * @date 2014-09-05
tushki7 0:60d829a0353a 95 * @brief CMSIS Peripheral Access Layer for MKL43Z4
tushki7 0:60d829a0353a 96 *
tushki7 0:60d829a0353a 97 * CMSIS Peripheral Access Layer for MKL43Z4
tushki7 0:60d829a0353a 98 */
tushki7 0:60d829a0353a 99
tushki7 0:60d829a0353a 100
tushki7 0:60d829a0353a 101 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 102 -- MCU activation
tushki7 0:60d829a0353a 103 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 104
tushki7 0:60d829a0353a 105 /* Prevention from multiple including the same memory map */
tushki7 0:60d829a0353a 106 #if !defined(MKL43Z4_H_) /* Check if memory map has not been already included */
tushki7 0:60d829a0353a 107 #define MKL43Z4_H_
tushki7 0:60d829a0353a 108 #define MCU_MKL43Z4
tushki7 0:60d829a0353a 109
tushki7 0:60d829a0353a 110 /* Check if another memory map has not been also included */
tushki7 0:60d829a0353a 111 #if (defined(MCU_ACTIVE))
tushki7 0:60d829a0353a 112 #error MKL43Z4 memory map: There is already included another memory map. Only one memory map can be included.
tushki7 0:60d829a0353a 113 #endif /* (defined(MCU_ACTIVE)) */
tushki7 0:60d829a0353a 114 #define MCU_ACTIVE
tushki7 0:60d829a0353a 115
tushki7 0:60d829a0353a 116 #include <stdint.h>
tushki7 0:60d829a0353a 117
tushki7 0:60d829a0353a 118 /** Memory map major version (memory maps with equal major version number are
tushki7 0:60d829a0353a 119 * compatible) */
tushki7 0:60d829a0353a 120 #define MCU_MEM_MAP_VERSION 0x0100u
tushki7 0:60d829a0353a 121 /** Memory map minor version */
tushki7 0:60d829a0353a 122 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
tushki7 0:60d829a0353a 123
tushki7 0:60d829a0353a 124
tushki7 0:60d829a0353a 125 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 126 -- Interrupt vector numbers
tushki7 0:60d829a0353a 127 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 128
tushki7 0:60d829a0353a 129 /*!
tushki7 0:60d829a0353a 130 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
tushki7 0:60d829a0353a 131 * @{
tushki7 0:60d829a0353a 132 */
tushki7 0:60d829a0353a 133
tushki7 0:60d829a0353a 134 /** Interrupt Number Definitions */
tushki7 0:60d829a0353a 135 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137 typedef enum IRQn {
tushki7 0:60d829a0353a 138 /* Auxiliary constants */
tushki7 0:60d829a0353a 139 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
tushki7 0:60d829a0353a 140
tushki7 0:60d829a0353a 141 /* Core interrupts */
tushki7 0:60d829a0353a 142 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
tushki7 0:60d829a0353a 143 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
tushki7 0:60d829a0353a 144 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
tushki7 0:60d829a0353a 145 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
tushki7 0:60d829a0353a 146 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
tushki7 0:60d829a0353a 147
tushki7 0:60d829a0353a 148 /* Device specific interrupts */
tushki7 0:60d829a0353a 149 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
tushki7 0:60d829a0353a 150 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
tushki7 0:60d829a0353a 151 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
tushki7 0:60d829a0353a 152 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
tushki7 0:60d829a0353a 153 Reserved20_IRQn = 4, /**< Reserved interrupt */
tushki7 0:60d829a0353a 154 FTFA_IRQn = 5, /**< Command complete and read collision */
tushki7 0:60d829a0353a 155 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
tushki7 0:60d829a0353a 156 LLWU_IRQn = 7, /**< Low leakage wakeup */
tushki7 0:60d829a0353a 157 I2C0_IRQn = 8, /**< I2C0 interrupt */
tushki7 0:60d829a0353a 158 I2C1_IRQn = 9, /**< I2C1 interrupt */
tushki7 0:60d829a0353a 159 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
tushki7 0:60d829a0353a 160 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
tushki7 0:60d829a0353a 161 LPUART0_IRQn = 12, /**< LPUART0 status and error */
tushki7 0:60d829a0353a 162 LPUART1_IRQn = 13, /**< LPUART1 status and error */
tushki7 0:60d829a0353a 163 UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
tushki7 0:60d829a0353a 164 ADC0_IRQn = 15, /**< ADC0 interrupt */
tushki7 0:60d829a0353a 165 CMP0_IRQn = 16, /**< CMP0 interrupt */
tushki7 0:60d829a0353a 166 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
tushki7 0:60d829a0353a 167 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
tushki7 0:60d829a0353a 168 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
tushki7 0:60d829a0353a 169 RTC_IRQn = 20, /**< RTC alarm */
tushki7 0:60d829a0353a 170 RTC_Seconds_IRQn = 21, /**< RTC seconds */
tushki7 0:60d829a0353a 171 PIT_IRQn = 22, /**< PIT interrupt */
tushki7 0:60d829a0353a 172 I2S0_IRQn = 23, /**< I2S0 interrupt */
tushki7 0:60d829a0353a 173 USB0_IRQn = 24, /**< USB0 interrupt */
tushki7 0:60d829a0353a 174 DAC0_IRQn = 25, /**< DAC0 interrupt */
tushki7 0:60d829a0353a 175 Reserved42_IRQn = 26, /**< Reserved interrupt */
tushki7 0:60d829a0353a 176 Reserved43_IRQn = 27, /**< Reserved interrupt */
tushki7 0:60d829a0353a 177 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
tushki7 0:60d829a0353a 178 LCD_IRQn = 29, /**< LCD interrupt */
tushki7 0:60d829a0353a 179 PORTA_IRQn = 30, /**< PORTA Pin detect */
tushki7 0:60d829a0353a 180 PORTCD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */
tushki7 0:60d829a0353a 181 } IRQn_Type;
tushki7 0:60d829a0353a 182
tushki7 0:60d829a0353a 183 /*!
tushki7 0:60d829a0353a 184 * @}
tushki7 0:60d829a0353a 185 */ /* end of group Interrupt_vector_numbers */
tushki7 0:60d829a0353a 186
tushki7 0:60d829a0353a 187
tushki7 0:60d829a0353a 188 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 189 -- Cortex M0 Core Configuration
tushki7 0:60d829a0353a 190 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 191
tushki7 0:60d829a0353a 192 /*!
tushki7 0:60d829a0353a 193 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
tushki7 0:60d829a0353a 194 * @{
tushki7 0:60d829a0353a 195 */
tushki7 0:60d829a0353a 196
tushki7 0:60d829a0353a 197 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
tushki7 0:60d829a0353a 198 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
tushki7 0:60d829a0353a 199 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
tushki7 0:60d829a0353a 200 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
tushki7 0:60d829a0353a 201 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
tushki7 0:60d829a0353a 202
tushki7 0:60d829a0353a 203 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
tushki7 0:60d829a0353a 204 #include "system_MKL43Z4.h" /* Device specific configuration file */
tushki7 0:60d829a0353a 205
tushki7 0:60d829a0353a 206 /*!
tushki7 0:60d829a0353a 207 * @}
tushki7 0:60d829a0353a 208 */ /* end of group Cortex_Core_Configuration */
tushki7 0:60d829a0353a 209
tushki7 0:60d829a0353a 210
tushki7 0:60d829a0353a 211 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 212 -- Device Peripheral Access Layer
tushki7 0:60d829a0353a 213 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 214
tushki7 0:60d829a0353a 215 /*!
tushki7 0:60d829a0353a 216 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
tushki7 0:60d829a0353a 217 * @{
tushki7 0:60d829a0353a 218 */
tushki7 0:60d829a0353a 219
tushki7 0:60d829a0353a 220
tushki7 0:60d829a0353a 221 /*
tushki7 0:60d829a0353a 222 ** Start of section using anonymous unions
tushki7 0:60d829a0353a 223 */
tushki7 0:60d829a0353a 224
tushki7 0:60d829a0353a 225 #if defined(__ARMCC_VERSION)
tushki7 0:60d829a0353a 226 #pragma push
tushki7 0:60d829a0353a 227 #pragma anon_unions
tushki7 0:60d829a0353a 228 #elif defined(__CWCC__)
tushki7 0:60d829a0353a 229 #pragma push
tushki7 0:60d829a0353a 230 #pragma cpp_extensions on
tushki7 0:60d829a0353a 231 #elif defined(__GNUC__)
tushki7 0:60d829a0353a 232 /* anonymous unions are enabled by default */
tushki7 0:60d829a0353a 233 #elif defined(__IAR_SYSTEMS_ICC__)
tushki7 0:60d829a0353a 234 #pragma language=extended
tushki7 0:60d829a0353a 235 #else
tushki7 0:60d829a0353a 236 #error Not supported compiler type
tushki7 0:60d829a0353a 237 #endif
tushki7 0:60d829a0353a 238
tushki7 0:60d829a0353a 239 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 240 -- ADC Peripheral Access Layer
tushki7 0:60d829a0353a 241 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 242
tushki7 0:60d829a0353a 243 /*!
tushki7 0:60d829a0353a 244 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
tushki7 0:60d829a0353a 245 * @{
tushki7 0:60d829a0353a 246 */
tushki7 0:60d829a0353a 247
tushki7 0:60d829a0353a 248 /** ADC - Register Layout Typedef */
tushki7 0:60d829a0353a 249 typedef struct {
tushki7 0:60d829a0353a 250 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
tushki7 0:60d829a0353a 251 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
tushki7 0:60d829a0353a 252 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
tushki7 0:60d829a0353a 253 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
tushki7 0:60d829a0353a 254 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
tushki7 0:60d829a0353a 255 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
tushki7 0:60d829a0353a 256 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
tushki7 0:60d829a0353a 257 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
tushki7 0:60d829a0353a 258 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
tushki7 0:60d829a0353a 259 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
tushki7 0:60d829a0353a 260 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
tushki7 0:60d829a0353a 261 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
tushki7 0:60d829a0353a 262 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
tushki7 0:60d829a0353a 263 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
tushki7 0:60d829a0353a 264 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
tushki7 0:60d829a0353a 265 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
tushki7 0:60d829a0353a 266 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
tushki7 0:60d829a0353a 267 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
tushki7 0:60d829a0353a 268 uint8_t RESERVED_0[4];
tushki7 0:60d829a0353a 269 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
tushki7 0:60d829a0353a 270 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
tushki7 0:60d829a0353a 271 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
tushki7 0:60d829a0353a 272 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
tushki7 0:60d829a0353a 273 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
tushki7 0:60d829a0353a 274 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
tushki7 0:60d829a0353a 275 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
tushki7 0:60d829a0353a 276 } ADC_Type, *ADC_MemMapPtr;
tushki7 0:60d829a0353a 277
tushki7 0:60d829a0353a 278 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 279 -- ADC - Register accessor macros
tushki7 0:60d829a0353a 280 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 281
tushki7 0:60d829a0353a 282 /*!
tushki7 0:60d829a0353a 283 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
tushki7 0:60d829a0353a 284 * @{
tushki7 0:60d829a0353a 285 */
tushki7 0:60d829a0353a 286
tushki7 0:60d829a0353a 287
tushki7 0:60d829a0353a 288 /* ADC - Register accessors */
tushki7 0:60d829a0353a 289 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
tushki7 0:60d829a0353a 290 #define ADC_CFG1_REG(base) ((base)->CFG1)
tushki7 0:60d829a0353a 291 #define ADC_CFG2_REG(base) ((base)->CFG2)
tushki7 0:60d829a0353a 292 #define ADC_R_REG(base,index) ((base)->R[index])
tushki7 0:60d829a0353a 293 #define ADC_CV1_REG(base) ((base)->CV1)
tushki7 0:60d829a0353a 294 #define ADC_CV2_REG(base) ((base)->CV2)
tushki7 0:60d829a0353a 295 #define ADC_SC2_REG(base) ((base)->SC2)
tushki7 0:60d829a0353a 296 #define ADC_SC3_REG(base) ((base)->SC3)
tushki7 0:60d829a0353a 297 #define ADC_OFS_REG(base) ((base)->OFS)
tushki7 0:60d829a0353a 298 #define ADC_PG_REG(base) ((base)->PG)
tushki7 0:60d829a0353a 299 #define ADC_MG_REG(base) ((base)->MG)
tushki7 0:60d829a0353a 300 #define ADC_CLPD_REG(base) ((base)->CLPD)
tushki7 0:60d829a0353a 301 #define ADC_CLPS_REG(base) ((base)->CLPS)
tushki7 0:60d829a0353a 302 #define ADC_CLP4_REG(base) ((base)->CLP4)
tushki7 0:60d829a0353a 303 #define ADC_CLP3_REG(base) ((base)->CLP3)
tushki7 0:60d829a0353a 304 #define ADC_CLP2_REG(base) ((base)->CLP2)
tushki7 0:60d829a0353a 305 #define ADC_CLP1_REG(base) ((base)->CLP1)
tushki7 0:60d829a0353a 306 #define ADC_CLP0_REG(base) ((base)->CLP0)
tushki7 0:60d829a0353a 307 #define ADC_CLMD_REG(base) ((base)->CLMD)
tushki7 0:60d829a0353a 308 #define ADC_CLMS_REG(base) ((base)->CLMS)
tushki7 0:60d829a0353a 309 #define ADC_CLM4_REG(base) ((base)->CLM4)
tushki7 0:60d829a0353a 310 #define ADC_CLM3_REG(base) ((base)->CLM3)
tushki7 0:60d829a0353a 311 #define ADC_CLM2_REG(base) ((base)->CLM2)
tushki7 0:60d829a0353a 312 #define ADC_CLM1_REG(base) ((base)->CLM1)
tushki7 0:60d829a0353a 313 #define ADC_CLM0_REG(base) ((base)->CLM0)
tushki7 0:60d829a0353a 314
tushki7 0:60d829a0353a 315 /*!
tushki7 0:60d829a0353a 316 * @}
tushki7 0:60d829a0353a 317 */ /* end of group ADC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 318
tushki7 0:60d829a0353a 319
tushki7 0:60d829a0353a 320 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 321 -- ADC Register Masks
tushki7 0:60d829a0353a 322 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 323
tushki7 0:60d829a0353a 324 /*!
tushki7 0:60d829a0353a 325 * @addtogroup ADC_Register_Masks ADC Register Masks
tushki7 0:60d829a0353a 326 * @{
tushki7 0:60d829a0353a 327 */
tushki7 0:60d829a0353a 328
tushki7 0:60d829a0353a 329 /* SC1 Bit Fields */
tushki7 0:60d829a0353a 330 #define ADC_SC1_ADCH_MASK 0x1Fu
tushki7 0:60d829a0353a 331 #define ADC_SC1_ADCH_SHIFT 0
tushki7 0:60d829a0353a 332 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
tushki7 0:60d829a0353a 333 #define ADC_SC1_DIFF_MASK 0x20u
tushki7 0:60d829a0353a 334 #define ADC_SC1_DIFF_SHIFT 5
tushki7 0:60d829a0353a 335 #define ADC_SC1_AIEN_MASK 0x40u
tushki7 0:60d829a0353a 336 #define ADC_SC1_AIEN_SHIFT 6
tushki7 0:60d829a0353a 337 #define ADC_SC1_COCO_MASK 0x80u
tushki7 0:60d829a0353a 338 #define ADC_SC1_COCO_SHIFT 7
tushki7 0:60d829a0353a 339 /* CFG1 Bit Fields */
tushki7 0:60d829a0353a 340 #define ADC_CFG1_ADICLK_MASK 0x3u
tushki7 0:60d829a0353a 341 #define ADC_CFG1_ADICLK_SHIFT 0
tushki7 0:60d829a0353a 342 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
tushki7 0:60d829a0353a 343 #define ADC_CFG1_MODE_MASK 0xCu
tushki7 0:60d829a0353a 344 #define ADC_CFG1_MODE_SHIFT 2
tushki7 0:60d829a0353a 345 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
tushki7 0:60d829a0353a 346 #define ADC_CFG1_ADLSMP_MASK 0x10u
tushki7 0:60d829a0353a 347 #define ADC_CFG1_ADLSMP_SHIFT 4
tushki7 0:60d829a0353a 348 #define ADC_CFG1_ADIV_MASK 0x60u
tushki7 0:60d829a0353a 349 #define ADC_CFG1_ADIV_SHIFT 5
tushki7 0:60d829a0353a 350 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
tushki7 0:60d829a0353a 351 #define ADC_CFG1_ADLPC_MASK 0x80u
tushki7 0:60d829a0353a 352 #define ADC_CFG1_ADLPC_SHIFT 7
tushki7 0:60d829a0353a 353 /* CFG2 Bit Fields */
tushki7 0:60d829a0353a 354 #define ADC_CFG2_ADLSTS_MASK 0x3u
tushki7 0:60d829a0353a 355 #define ADC_CFG2_ADLSTS_SHIFT 0
tushki7 0:60d829a0353a 356 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
tushki7 0:60d829a0353a 357 #define ADC_CFG2_ADHSC_MASK 0x4u
tushki7 0:60d829a0353a 358 #define ADC_CFG2_ADHSC_SHIFT 2
tushki7 0:60d829a0353a 359 #define ADC_CFG2_ADACKEN_MASK 0x8u
tushki7 0:60d829a0353a 360 #define ADC_CFG2_ADACKEN_SHIFT 3
tushki7 0:60d829a0353a 361 #define ADC_CFG2_MUXSEL_MASK 0x10u
tushki7 0:60d829a0353a 362 #define ADC_CFG2_MUXSEL_SHIFT 4
tushki7 0:60d829a0353a 363 /* R Bit Fields */
tushki7 0:60d829a0353a 364 #define ADC_R_D_MASK 0xFFFFu
tushki7 0:60d829a0353a 365 #define ADC_R_D_SHIFT 0
tushki7 0:60d829a0353a 366 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
tushki7 0:60d829a0353a 367 /* CV1 Bit Fields */
tushki7 0:60d829a0353a 368 #define ADC_CV1_CV_MASK 0xFFFFu
tushki7 0:60d829a0353a 369 #define ADC_CV1_CV_SHIFT 0
tushki7 0:60d829a0353a 370 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
tushki7 0:60d829a0353a 371 /* CV2 Bit Fields */
tushki7 0:60d829a0353a 372 #define ADC_CV2_CV_MASK 0xFFFFu
tushki7 0:60d829a0353a 373 #define ADC_CV2_CV_SHIFT 0
tushki7 0:60d829a0353a 374 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
tushki7 0:60d829a0353a 375 /* SC2 Bit Fields */
tushki7 0:60d829a0353a 376 #define ADC_SC2_REFSEL_MASK 0x3u
tushki7 0:60d829a0353a 377 #define ADC_SC2_REFSEL_SHIFT 0
tushki7 0:60d829a0353a 378 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
tushki7 0:60d829a0353a 379 #define ADC_SC2_DMAEN_MASK 0x4u
tushki7 0:60d829a0353a 380 #define ADC_SC2_DMAEN_SHIFT 2
tushki7 0:60d829a0353a 381 #define ADC_SC2_ACREN_MASK 0x8u
tushki7 0:60d829a0353a 382 #define ADC_SC2_ACREN_SHIFT 3
tushki7 0:60d829a0353a 383 #define ADC_SC2_ACFGT_MASK 0x10u
tushki7 0:60d829a0353a 384 #define ADC_SC2_ACFGT_SHIFT 4
tushki7 0:60d829a0353a 385 #define ADC_SC2_ACFE_MASK 0x20u
tushki7 0:60d829a0353a 386 #define ADC_SC2_ACFE_SHIFT 5
tushki7 0:60d829a0353a 387 #define ADC_SC2_ADTRG_MASK 0x40u
tushki7 0:60d829a0353a 388 #define ADC_SC2_ADTRG_SHIFT 6
tushki7 0:60d829a0353a 389 #define ADC_SC2_ADACT_MASK 0x80u
tushki7 0:60d829a0353a 390 #define ADC_SC2_ADACT_SHIFT 7
tushki7 0:60d829a0353a 391 /* SC3 Bit Fields */
tushki7 0:60d829a0353a 392 #define ADC_SC3_AVGS_MASK 0x3u
tushki7 0:60d829a0353a 393 #define ADC_SC3_AVGS_SHIFT 0
tushki7 0:60d829a0353a 394 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
tushki7 0:60d829a0353a 395 #define ADC_SC3_AVGE_MASK 0x4u
tushki7 0:60d829a0353a 396 #define ADC_SC3_AVGE_SHIFT 2
tushki7 0:60d829a0353a 397 #define ADC_SC3_ADCO_MASK 0x8u
tushki7 0:60d829a0353a 398 #define ADC_SC3_ADCO_SHIFT 3
tushki7 0:60d829a0353a 399 #define ADC_SC3_CALF_MASK 0x40u
tushki7 0:60d829a0353a 400 #define ADC_SC3_CALF_SHIFT 6
tushki7 0:60d829a0353a 401 #define ADC_SC3_CAL_MASK 0x80u
tushki7 0:60d829a0353a 402 #define ADC_SC3_CAL_SHIFT 7
tushki7 0:60d829a0353a 403 /* OFS Bit Fields */
tushki7 0:60d829a0353a 404 #define ADC_OFS_OFS_MASK 0xFFFFu
tushki7 0:60d829a0353a 405 #define ADC_OFS_OFS_SHIFT 0
tushki7 0:60d829a0353a 406 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
tushki7 0:60d829a0353a 407 /* PG Bit Fields */
tushki7 0:60d829a0353a 408 #define ADC_PG_PG_MASK 0xFFFFu
tushki7 0:60d829a0353a 409 #define ADC_PG_PG_SHIFT 0
tushki7 0:60d829a0353a 410 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
tushki7 0:60d829a0353a 411 /* MG Bit Fields */
tushki7 0:60d829a0353a 412 #define ADC_MG_MG_MASK 0xFFFFu
tushki7 0:60d829a0353a 413 #define ADC_MG_MG_SHIFT 0
tushki7 0:60d829a0353a 414 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
tushki7 0:60d829a0353a 415 /* CLPD Bit Fields */
tushki7 0:60d829a0353a 416 #define ADC_CLPD_CLPD_MASK 0x3Fu
tushki7 0:60d829a0353a 417 #define ADC_CLPD_CLPD_SHIFT 0
tushki7 0:60d829a0353a 418 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
tushki7 0:60d829a0353a 419 /* CLPS Bit Fields */
tushki7 0:60d829a0353a 420 #define ADC_CLPS_CLPS_MASK 0x3Fu
tushki7 0:60d829a0353a 421 #define ADC_CLPS_CLPS_SHIFT 0
tushki7 0:60d829a0353a 422 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
tushki7 0:60d829a0353a 423 /* CLP4 Bit Fields */
tushki7 0:60d829a0353a 424 #define ADC_CLP4_CLP4_MASK 0x3FFu
tushki7 0:60d829a0353a 425 #define ADC_CLP4_CLP4_SHIFT 0
tushki7 0:60d829a0353a 426 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
tushki7 0:60d829a0353a 427 /* CLP3 Bit Fields */
tushki7 0:60d829a0353a 428 #define ADC_CLP3_CLP3_MASK 0x1FFu
tushki7 0:60d829a0353a 429 #define ADC_CLP3_CLP3_SHIFT 0
tushki7 0:60d829a0353a 430 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
tushki7 0:60d829a0353a 431 /* CLP2 Bit Fields */
tushki7 0:60d829a0353a 432 #define ADC_CLP2_CLP2_MASK 0xFFu
tushki7 0:60d829a0353a 433 #define ADC_CLP2_CLP2_SHIFT 0
tushki7 0:60d829a0353a 434 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
tushki7 0:60d829a0353a 435 /* CLP1 Bit Fields */
tushki7 0:60d829a0353a 436 #define ADC_CLP1_CLP1_MASK 0x7Fu
tushki7 0:60d829a0353a 437 #define ADC_CLP1_CLP1_SHIFT 0
tushki7 0:60d829a0353a 438 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
tushki7 0:60d829a0353a 439 /* CLP0 Bit Fields */
tushki7 0:60d829a0353a 440 #define ADC_CLP0_CLP0_MASK 0x3Fu
tushki7 0:60d829a0353a 441 #define ADC_CLP0_CLP0_SHIFT 0
tushki7 0:60d829a0353a 442 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
tushki7 0:60d829a0353a 443 /* CLMD Bit Fields */
tushki7 0:60d829a0353a 444 #define ADC_CLMD_CLMD_MASK 0x3Fu
tushki7 0:60d829a0353a 445 #define ADC_CLMD_CLMD_SHIFT 0
tushki7 0:60d829a0353a 446 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
tushki7 0:60d829a0353a 447 /* CLMS Bit Fields */
tushki7 0:60d829a0353a 448 #define ADC_CLMS_CLMS_MASK 0x3Fu
tushki7 0:60d829a0353a 449 #define ADC_CLMS_CLMS_SHIFT 0
tushki7 0:60d829a0353a 450 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
tushki7 0:60d829a0353a 451 /* CLM4 Bit Fields */
tushki7 0:60d829a0353a 452 #define ADC_CLM4_CLM4_MASK 0x3FFu
tushki7 0:60d829a0353a 453 #define ADC_CLM4_CLM4_SHIFT 0
tushki7 0:60d829a0353a 454 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
tushki7 0:60d829a0353a 455 /* CLM3 Bit Fields */
tushki7 0:60d829a0353a 456 #define ADC_CLM3_CLM3_MASK 0x1FFu
tushki7 0:60d829a0353a 457 #define ADC_CLM3_CLM3_SHIFT 0
tushki7 0:60d829a0353a 458 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
tushki7 0:60d829a0353a 459 /* CLM2 Bit Fields */
tushki7 0:60d829a0353a 460 #define ADC_CLM2_CLM2_MASK 0xFFu
tushki7 0:60d829a0353a 461 #define ADC_CLM2_CLM2_SHIFT 0
tushki7 0:60d829a0353a 462 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
tushki7 0:60d829a0353a 463 /* CLM1 Bit Fields */
tushki7 0:60d829a0353a 464 #define ADC_CLM1_CLM1_MASK 0x7Fu
tushki7 0:60d829a0353a 465 #define ADC_CLM1_CLM1_SHIFT 0
tushki7 0:60d829a0353a 466 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
tushki7 0:60d829a0353a 467 /* CLM0 Bit Fields */
tushki7 0:60d829a0353a 468 #define ADC_CLM0_CLM0_MASK 0x3Fu
tushki7 0:60d829a0353a 469 #define ADC_CLM0_CLM0_SHIFT 0
tushki7 0:60d829a0353a 470 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
tushki7 0:60d829a0353a 471
tushki7 0:60d829a0353a 472 /*!
tushki7 0:60d829a0353a 473 * @}
tushki7 0:60d829a0353a 474 */ /* end of group ADC_Register_Masks */
tushki7 0:60d829a0353a 475
tushki7 0:60d829a0353a 476
tushki7 0:60d829a0353a 477 /* ADC - Peripheral instance base addresses */
tushki7 0:60d829a0353a 478 /** Peripheral ADC0 base address */
tushki7 0:60d829a0353a 479 #define ADC0_BASE (0x4003B000u)
tushki7 0:60d829a0353a 480 /** Peripheral ADC0 base pointer */
tushki7 0:60d829a0353a 481 #define ADC0 ((ADC_Type *)ADC0_BASE)
tushki7 0:60d829a0353a 482 #define ADC0_BASE_PTR (ADC0)
tushki7 0:60d829a0353a 483 /** Array initializer of ADC peripheral base addresses */
tushki7 0:60d829a0353a 484 #define ADC_BASE_ADDRS { ADC0_BASE }
tushki7 0:60d829a0353a 485 /** Array initializer of ADC peripheral base pointers */
tushki7 0:60d829a0353a 486 #define ADC_BASE_PTRS { ADC0 }
tushki7 0:60d829a0353a 487 /** Interrupt vectors for the ADC peripheral type */
tushki7 0:60d829a0353a 488 #define ADC_IRQS { ADC0_IRQn }
tushki7 0:60d829a0353a 489
tushki7 0:60d829a0353a 490 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 491 -- ADC - Register accessor macros
tushki7 0:60d829a0353a 492 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 493
tushki7 0:60d829a0353a 494 /*!
tushki7 0:60d829a0353a 495 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
tushki7 0:60d829a0353a 496 * @{
tushki7 0:60d829a0353a 497 */
tushki7 0:60d829a0353a 498
tushki7 0:60d829a0353a 499
tushki7 0:60d829a0353a 500 /* ADC - Register instance definitions */
tushki7 0:60d829a0353a 501 /* ADC0 */
tushki7 0:60d829a0353a 502 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
tushki7 0:60d829a0353a 503 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
tushki7 0:60d829a0353a 504 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
tushki7 0:60d829a0353a 505 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
tushki7 0:60d829a0353a 506 #define ADC0_RA ADC_R_REG(ADC0,0)
tushki7 0:60d829a0353a 507 #define ADC0_RB ADC_R_REG(ADC0,1)
tushki7 0:60d829a0353a 508 #define ADC0_CV1 ADC_CV1_REG(ADC0)
tushki7 0:60d829a0353a 509 #define ADC0_CV2 ADC_CV2_REG(ADC0)
tushki7 0:60d829a0353a 510 #define ADC0_SC2 ADC_SC2_REG(ADC0)
tushki7 0:60d829a0353a 511 #define ADC0_SC3 ADC_SC3_REG(ADC0)
tushki7 0:60d829a0353a 512 #define ADC0_OFS ADC_OFS_REG(ADC0)
tushki7 0:60d829a0353a 513 #define ADC0_PG ADC_PG_REG(ADC0)
tushki7 0:60d829a0353a 514 #define ADC0_MG ADC_MG_REG(ADC0)
tushki7 0:60d829a0353a 515 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
tushki7 0:60d829a0353a 516 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
tushki7 0:60d829a0353a 517 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
tushki7 0:60d829a0353a 518 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
tushki7 0:60d829a0353a 519 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
tushki7 0:60d829a0353a 520 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
tushki7 0:60d829a0353a 521 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
tushki7 0:60d829a0353a 522 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
tushki7 0:60d829a0353a 523 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
tushki7 0:60d829a0353a 524 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
tushki7 0:60d829a0353a 525 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
tushki7 0:60d829a0353a 526 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
tushki7 0:60d829a0353a 527 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
tushki7 0:60d829a0353a 528 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
tushki7 0:60d829a0353a 529
tushki7 0:60d829a0353a 530 /* ADC - Register array accessors */
tushki7 0:60d829a0353a 531 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
tushki7 0:60d829a0353a 532 #define ADC0_R(index) ADC_R_REG(ADC0,index)
tushki7 0:60d829a0353a 533
tushki7 0:60d829a0353a 534 /*!
tushki7 0:60d829a0353a 535 * @}
tushki7 0:60d829a0353a 536 */ /* end of group ADC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 537
tushki7 0:60d829a0353a 538
tushki7 0:60d829a0353a 539 /*!
tushki7 0:60d829a0353a 540 * @}
tushki7 0:60d829a0353a 541 */ /* end of group ADC_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 542
tushki7 0:60d829a0353a 543
tushki7 0:60d829a0353a 544 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 545 -- CMP Peripheral Access Layer
tushki7 0:60d829a0353a 546 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 547
tushki7 0:60d829a0353a 548 /*!
tushki7 0:60d829a0353a 549 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
tushki7 0:60d829a0353a 550 * @{
tushki7 0:60d829a0353a 551 */
tushki7 0:60d829a0353a 552
tushki7 0:60d829a0353a 553 /** CMP - Register Layout Typedef */
tushki7 0:60d829a0353a 554 typedef struct {
tushki7 0:60d829a0353a 555 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
tushki7 0:60d829a0353a 556 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
tushki7 0:60d829a0353a 557 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
tushki7 0:60d829a0353a 558 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
tushki7 0:60d829a0353a 559 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
tushki7 0:60d829a0353a 560 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
tushki7 0:60d829a0353a 561 } CMP_Type, *CMP_MemMapPtr;
tushki7 0:60d829a0353a 562
tushki7 0:60d829a0353a 563 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 564 -- CMP - Register accessor macros
tushki7 0:60d829a0353a 565 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 566
tushki7 0:60d829a0353a 567 /*!
tushki7 0:60d829a0353a 568 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
tushki7 0:60d829a0353a 569 * @{
tushki7 0:60d829a0353a 570 */
tushki7 0:60d829a0353a 571
tushki7 0:60d829a0353a 572
tushki7 0:60d829a0353a 573 /* CMP - Register accessors */
tushki7 0:60d829a0353a 574 #define CMP_CR0_REG(base) ((base)->CR0)
tushki7 0:60d829a0353a 575 #define CMP_CR1_REG(base) ((base)->CR1)
tushki7 0:60d829a0353a 576 #define CMP_FPR_REG(base) ((base)->FPR)
tushki7 0:60d829a0353a 577 #define CMP_SCR_REG(base) ((base)->SCR)
tushki7 0:60d829a0353a 578 #define CMP_DACCR_REG(base) ((base)->DACCR)
tushki7 0:60d829a0353a 579 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
tushki7 0:60d829a0353a 580
tushki7 0:60d829a0353a 581 /*!
tushki7 0:60d829a0353a 582 * @}
tushki7 0:60d829a0353a 583 */ /* end of group CMP_Register_Accessor_Macros */
tushki7 0:60d829a0353a 584
tushki7 0:60d829a0353a 585
tushki7 0:60d829a0353a 586 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 587 -- CMP Register Masks
tushki7 0:60d829a0353a 588 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 589
tushki7 0:60d829a0353a 590 /*!
tushki7 0:60d829a0353a 591 * @addtogroup CMP_Register_Masks CMP Register Masks
tushki7 0:60d829a0353a 592 * @{
tushki7 0:60d829a0353a 593 */
tushki7 0:60d829a0353a 594
tushki7 0:60d829a0353a 595 /* CR0 Bit Fields */
tushki7 0:60d829a0353a 596 #define CMP_CR0_HYSTCTR_MASK 0x3u
tushki7 0:60d829a0353a 597 #define CMP_CR0_HYSTCTR_SHIFT 0
tushki7 0:60d829a0353a 598 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
tushki7 0:60d829a0353a 599 #define CMP_CR0_FILTER_CNT_MASK 0x70u
tushki7 0:60d829a0353a 600 #define CMP_CR0_FILTER_CNT_SHIFT 4
tushki7 0:60d829a0353a 601 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
tushki7 0:60d829a0353a 602 /* CR1 Bit Fields */
tushki7 0:60d829a0353a 603 #define CMP_CR1_EN_MASK 0x1u
tushki7 0:60d829a0353a 604 #define CMP_CR1_EN_SHIFT 0
tushki7 0:60d829a0353a 605 #define CMP_CR1_OPE_MASK 0x2u
tushki7 0:60d829a0353a 606 #define CMP_CR1_OPE_SHIFT 1
tushki7 0:60d829a0353a 607 #define CMP_CR1_COS_MASK 0x4u
tushki7 0:60d829a0353a 608 #define CMP_CR1_COS_SHIFT 2
tushki7 0:60d829a0353a 609 #define CMP_CR1_INV_MASK 0x8u
tushki7 0:60d829a0353a 610 #define CMP_CR1_INV_SHIFT 3
tushki7 0:60d829a0353a 611 #define CMP_CR1_PMODE_MASK 0x10u
tushki7 0:60d829a0353a 612 #define CMP_CR1_PMODE_SHIFT 4
tushki7 0:60d829a0353a 613 #define CMP_CR1_TRIGM_MASK 0x20u
tushki7 0:60d829a0353a 614 #define CMP_CR1_TRIGM_SHIFT 5
tushki7 0:60d829a0353a 615 #define CMP_CR1_WE_MASK 0x40u
tushki7 0:60d829a0353a 616 #define CMP_CR1_WE_SHIFT 6
tushki7 0:60d829a0353a 617 #define CMP_CR1_SE_MASK 0x80u
tushki7 0:60d829a0353a 618 #define CMP_CR1_SE_SHIFT 7
tushki7 0:60d829a0353a 619 /* FPR Bit Fields */
tushki7 0:60d829a0353a 620 #define CMP_FPR_FILT_PER_MASK 0xFFu
tushki7 0:60d829a0353a 621 #define CMP_FPR_FILT_PER_SHIFT 0
tushki7 0:60d829a0353a 622 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
tushki7 0:60d829a0353a 623 /* SCR Bit Fields */
tushki7 0:60d829a0353a 624 #define CMP_SCR_COUT_MASK 0x1u
tushki7 0:60d829a0353a 625 #define CMP_SCR_COUT_SHIFT 0
tushki7 0:60d829a0353a 626 #define CMP_SCR_CFF_MASK 0x2u
tushki7 0:60d829a0353a 627 #define CMP_SCR_CFF_SHIFT 1
tushki7 0:60d829a0353a 628 #define CMP_SCR_CFR_MASK 0x4u
tushki7 0:60d829a0353a 629 #define CMP_SCR_CFR_SHIFT 2
tushki7 0:60d829a0353a 630 #define CMP_SCR_IEF_MASK 0x8u
tushki7 0:60d829a0353a 631 #define CMP_SCR_IEF_SHIFT 3
tushki7 0:60d829a0353a 632 #define CMP_SCR_IER_MASK 0x10u
tushki7 0:60d829a0353a 633 #define CMP_SCR_IER_SHIFT 4
tushki7 0:60d829a0353a 634 #define CMP_SCR_DMAEN_MASK 0x40u
tushki7 0:60d829a0353a 635 #define CMP_SCR_DMAEN_SHIFT 6
tushki7 0:60d829a0353a 636 /* DACCR Bit Fields */
tushki7 0:60d829a0353a 637 #define CMP_DACCR_VOSEL_MASK 0x3Fu
tushki7 0:60d829a0353a 638 #define CMP_DACCR_VOSEL_SHIFT 0
tushki7 0:60d829a0353a 639 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
tushki7 0:60d829a0353a 640 #define CMP_DACCR_VRSEL_MASK 0x40u
tushki7 0:60d829a0353a 641 #define CMP_DACCR_VRSEL_SHIFT 6
tushki7 0:60d829a0353a 642 #define CMP_DACCR_DACEN_MASK 0x80u
tushki7 0:60d829a0353a 643 #define CMP_DACCR_DACEN_SHIFT 7
tushki7 0:60d829a0353a 644 /* MUXCR Bit Fields */
tushki7 0:60d829a0353a 645 #define CMP_MUXCR_MSEL_MASK 0x7u
tushki7 0:60d829a0353a 646 #define CMP_MUXCR_MSEL_SHIFT 0
tushki7 0:60d829a0353a 647 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
tushki7 0:60d829a0353a 648 #define CMP_MUXCR_PSEL_MASK 0x38u
tushki7 0:60d829a0353a 649 #define CMP_MUXCR_PSEL_SHIFT 3
tushki7 0:60d829a0353a 650 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
tushki7 0:60d829a0353a 651 #define CMP_MUXCR_PSTM_MASK 0x80u
tushki7 0:60d829a0353a 652 #define CMP_MUXCR_PSTM_SHIFT 7
tushki7 0:60d829a0353a 653
tushki7 0:60d829a0353a 654 /*!
tushki7 0:60d829a0353a 655 * @}
tushki7 0:60d829a0353a 656 */ /* end of group CMP_Register_Masks */
tushki7 0:60d829a0353a 657
tushki7 0:60d829a0353a 658
tushki7 0:60d829a0353a 659 /* CMP - Peripheral instance base addresses */
tushki7 0:60d829a0353a 660 /** Peripheral CMP0 base address */
tushki7 0:60d829a0353a 661 #define CMP0_BASE (0x40073000u)
tushki7 0:60d829a0353a 662 /** Peripheral CMP0 base pointer */
tushki7 0:60d829a0353a 663 #define CMP0 ((CMP_Type *)CMP0_BASE)
tushki7 0:60d829a0353a 664 #define CMP0_BASE_PTR (CMP0)
tushki7 0:60d829a0353a 665 /** Array initializer of CMP peripheral base addresses */
tushki7 0:60d829a0353a 666 #define CMP_BASE_ADDRS { CMP0_BASE }
tushki7 0:60d829a0353a 667 /** Array initializer of CMP peripheral base pointers */
tushki7 0:60d829a0353a 668 #define CMP_BASE_PTRS { CMP0 }
tushki7 0:60d829a0353a 669 /** Interrupt vectors for the CMP peripheral type */
tushki7 0:60d829a0353a 670 #define CMP_IRQS { CMP0_IRQn }
tushki7 0:60d829a0353a 671
tushki7 0:60d829a0353a 672 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 673 -- CMP - Register accessor macros
tushki7 0:60d829a0353a 674 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 675
tushki7 0:60d829a0353a 676 /*!
tushki7 0:60d829a0353a 677 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
tushki7 0:60d829a0353a 678 * @{
tushki7 0:60d829a0353a 679 */
tushki7 0:60d829a0353a 680
tushki7 0:60d829a0353a 681
tushki7 0:60d829a0353a 682 /* CMP - Register instance definitions */
tushki7 0:60d829a0353a 683 /* CMP0 */
tushki7 0:60d829a0353a 684 #define CMP0_CR0 CMP_CR0_REG(CMP0)
tushki7 0:60d829a0353a 685 #define CMP0_CR1 CMP_CR1_REG(CMP0)
tushki7 0:60d829a0353a 686 #define CMP0_FPR CMP_FPR_REG(CMP0)
tushki7 0:60d829a0353a 687 #define CMP0_SCR CMP_SCR_REG(CMP0)
tushki7 0:60d829a0353a 688 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
tushki7 0:60d829a0353a 689 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
tushki7 0:60d829a0353a 690
tushki7 0:60d829a0353a 691 /*!
tushki7 0:60d829a0353a 692 * @}
tushki7 0:60d829a0353a 693 */ /* end of group CMP_Register_Accessor_Macros */
tushki7 0:60d829a0353a 694
tushki7 0:60d829a0353a 695
tushki7 0:60d829a0353a 696 /*!
tushki7 0:60d829a0353a 697 * @}
tushki7 0:60d829a0353a 698 */ /* end of group CMP_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 699
tushki7 0:60d829a0353a 700
tushki7 0:60d829a0353a 701 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 702 -- DAC Peripheral Access Layer
tushki7 0:60d829a0353a 703 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 704
tushki7 0:60d829a0353a 705 /*!
tushki7 0:60d829a0353a 706 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
tushki7 0:60d829a0353a 707 * @{
tushki7 0:60d829a0353a 708 */
tushki7 0:60d829a0353a 709
tushki7 0:60d829a0353a 710 /** DAC - Register Layout Typedef */
tushki7 0:60d829a0353a 711 typedef struct {
tushki7 0:60d829a0353a 712 struct { /* offset: 0x0, array step: 0x2 */
tushki7 0:60d829a0353a 713 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
tushki7 0:60d829a0353a 714 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
tushki7 0:60d829a0353a 715 } DAT[2];
tushki7 0:60d829a0353a 716 uint8_t RESERVED_0[28];
tushki7 0:60d829a0353a 717 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
tushki7 0:60d829a0353a 718 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
tushki7 0:60d829a0353a 719 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
tushki7 0:60d829a0353a 720 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
tushki7 0:60d829a0353a 721 } DAC_Type, *DAC_MemMapPtr;
tushki7 0:60d829a0353a 722
tushki7 0:60d829a0353a 723 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 724 -- DAC - Register accessor macros
tushki7 0:60d829a0353a 725 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 726
tushki7 0:60d829a0353a 727 /*!
tushki7 0:60d829a0353a 728 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
tushki7 0:60d829a0353a 729 * @{
tushki7 0:60d829a0353a 730 */
tushki7 0:60d829a0353a 731
tushki7 0:60d829a0353a 732
tushki7 0:60d829a0353a 733 /* DAC - Register accessors */
tushki7 0:60d829a0353a 734 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
tushki7 0:60d829a0353a 735 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
tushki7 0:60d829a0353a 736 #define DAC_SR_REG(base) ((base)->SR)
tushki7 0:60d829a0353a 737 #define DAC_C0_REG(base) ((base)->C0)
tushki7 0:60d829a0353a 738 #define DAC_C1_REG(base) ((base)->C1)
tushki7 0:60d829a0353a 739 #define DAC_C2_REG(base) ((base)->C2)
tushki7 0:60d829a0353a 740
tushki7 0:60d829a0353a 741 /*!
tushki7 0:60d829a0353a 742 * @}
tushki7 0:60d829a0353a 743 */ /* end of group DAC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 744
tushki7 0:60d829a0353a 745
tushki7 0:60d829a0353a 746 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 747 -- DAC Register Masks
tushki7 0:60d829a0353a 748 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 749
tushki7 0:60d829a0353a 750 /*!
tushki7 0:60d829a0353a 751 * @addtogroup DAC_Register_Masks DAC Register Masks
tushki7 0:60d829a0353a 752 * @{
tushki7 0:60d829a0353a 753 */
tushki7 0:60d829a0353a 754
tushki7 0:60d829a0353a 755 /* DATL Bit Fields */
tushki7 0:60d829a0353a 756 #define DAC_DATL_DATA0_MASK 0xFFu
tushki7 0:60d829a0353a 757 #define DAC_DATL_DATA0_SHIFT 0
tushki7 0:60d829a0353a 758 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
tushki7 0:60d829a0353a 759 /* DATH Bit Fields */
tushki7 0:60d829a0353a 760 #define DAC_DATH_DATA1_MASK 0xFu
tushki7 0:60d829a0353a 761 #define DAC_DATH_DATA1_SHIFT 0
tushki7 0:60d829a0353a 762 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
tushki7 0:60d829a0353a 763 /* SR Bit Fields */
tushki7 0:60d829a0353a 764 #define DAC_SR_DACBFRPBF_MASK 0x1u
tushki7 0:60d829a0353a 765 #define DAC_SR_DACBFRPBF_SHIFT 0
tushki7 0:60d829a0353a 766 #define DAC_SR_DACBFRPTF_MASK 0x2u
tushki7 0:60d829a0353a 767 #define DAC_SR_DACBFRPTF_SHIFT 1
tushki7 0:60d829a0353a 768 /* C0 Bit Fields */
tushki7 0:60d829a0353a 769 #define DAC_C0_DACBBIEN_MASK 0x1u
tushki7 0:60d829a0353a 770 #define DAC_C0_DACBBIEN_SHIFT 0
tushki7 0:60d829a0353a 771 #define DAC_C0_DACBTIEN_MASK 0x2u
tushki7 0:60d829a0353a 772 #define DAC_C0_DACBTIEN_SHIFT 1
tushki7 0:60d829a0353a 773 #define DAC_C0_LPEN_MASK 0x8u
tushki7 0:60d829a0353a 774 #define DAC_C0_LPEN_SHIFT 3
tushki7 0:60d829a0353a 775 #define DAC_C0_DACSWTRG_MASK 0x10u
tushki7 0:60d829a0353a 776 #define DAC_C0_DACSWTRG_SHIFT 4
tushki7 0:60d829a0353a 777 #define DAC_C0_DACTRGSEL_MASK 0x20u
tushki7 0:60d829a0353a 778 #define DAC_C0_DACTRGSEL_SHIFT 5
tushki7 0:60d829a0353a 779 #define DAC_C0_DACRFS_MASK 0x40u
tushki7 0:60d829a0353a 780 #define DAC_C0_DACRFS_SHIFT 6
tushki7 0:60d829a0353a 781 #define DAC_C0_DACEN_MASK 0x80u
tushki7 0:60d829a0353a 782 #define DAC_C0_DACEN_SHIFT 7
tushki7 0:60d829a0353a 783 /* C1 Bit Fields */
tushki7 0:60d829a0353a 784 #define DAC_C1_DACBFEN_MASK 0x1u
tushki7 0:60d829a0353a 785 #define DAC_C1_DACBFEN_SHIFT 0
tushki7 0:60d829a0353a 786 #define DAC_C1_DACBFMD_MASK 0x6u
tushki7 0:60d829a0353a 787 #define DAC_C1_DACBFMD_SHIFT 1
tushki7 0:60d829a0353a 788 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
tushki7 0:60d829a0353a 789 #define DAC_C1_DMAEN_MASK 0x80u
tushki7 0:60d829a0353a 790 #define DAC_C1_DMAEN_SHIFT 7
tushki7 0:60d829a0353a 791 /* C2 Bit Fields */
tushki7 0:60d829a0353a 792 #define DAC_C2_DACBFUP_MASK 0x1u
tushki7 0:60d829a0353a 793 #define DAC_C2_DACBFUP_SHIFT 0
tushki7 0:60d829a0353a 794 #define DAC_C2_DACBFRP_MASK 0x10u
tushki7 0:60d829a0353a 795 #define DAC_C2_DACBFRP_SHIFT 4
tushki7 0:60d829a0353a 796
tushki7 0:60d829a0353a 797 /*!
tushki7 0:60d829a0353a 798 * @}
tushki7 0:60d829a0353a 799 */ /* end of group DAC_Register_Masks */
tushki7 0:60d829a0353a 800
tushki7 0:60d829a0353a 801
tushki7 0:60d829a0353a 802 /* DAC - Peripheral instance base addresses */
tushki7 0:60d829a0353a 803 /** Peripheral DAC0 base address */
tushki7 0:60d829a0353a 804 #define DAC0_BASE (0x4003F000u)
tushki7 0:60d829a0353a 805 /** Peripheral DAC0 base pointer */
tushki7 0:60d829a0353a 806 #define DAC0 ((DAC_Type *)DAC0_BASE)
tushki7 0:60d829a0353a 807 #define DAC0_BASE_PTR (DAC0)
tushki7 0:60d829a0353a 808 /** Array initializer of DAC peripheral base addresses */
tushki7 0:60d829a0353a 809 #define DAC_BASE_ADDRS { DAC0_BASE }
tushki7 0:60d829a0353a 810 /** Array initializer of DAC peripheral base pointers */
tushki7 0:60d829a0353a 811 #define DAC_BASE_PTRS { DAC0 }
tushki7 0:60d829a0353a 812 /** Interrupt vectors for the DAC peripheral type */
tushki7 0:60d829a0353a 813 #define DAC_IRQS { DAC0_IRQn }
tushki7 0:60d829a0353a 814
tushki7 0:60d829a0353a 815 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 816 -- DAC - Register accessor macros
tushki7 0:60d829a0353a 817 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 818
tushki7 0:60d829a0353a 819 /*!
tushki7 0:60d829a0353a 820 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
tushki7 0:60d829a0353a 821 * @{
tushki7 0:60d829a0353a 822 */
tushki7 0:60d829a0353a 823
tushki7 0:60d829a0353a 824
tushki7 0:60d829a0353a 825 /* DAC - Register instance definitions */
tushki7 0:60d829a0353a 826 /* DAC0 */
tushki7 0:60d829a0353a 827 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
tushki7 0:60d829a0353a 828 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
tushki7 0:60d829a0353a 829 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
tushki7 0:60d829a0353a 830 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
tushki7 0:60d829a0353a 831 #define DAC0_SR DAC_SR_REG(DAC0)
tushki7 0:60d829a0353a 832 #define DAC0_C0 DAC_C0_REG(DAC0)
tushki7 0:60d829a0353a 833 #define DAC0_C1 DAC_C1_REG(DAC0)
tushki7 0:60d829a0353a 834 #define DAC0_C2 DAC_C2_REG(DAC0)
tushki7 0:60d829a0353a 835
tushki7 0:60d829a0353a 836 /* DAC - Register array accessors */
tushki7 0:60d829a0353a 837 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
tushki7 0:60d829a0353a 838 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
tushki7 0:60d829a0353a 839
tushki7 0:60d829a0353a 840 /*!
tushki7 0:60d829a0353a 841 * @}
tushki7 0:60d829a0353a 842 */ /* end of group DAC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 843
tushki7 0:60d829a0353a 844
tushki7 0:60d829a0353a 845 /*!
tushki7 0:60d829a0353a 846 * @}
tushki7 0:60d829a0353a 847 */ /* end of group DAC_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 848
tushki7 0:60d829a0353a 849
tushki7 0:60d829a0353a 850 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 851 -- DMA Peripheral Access Layer
tushki7 0:60d829a0353a 852 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 853
tushki7 0:60d829a0353a 854 /*!
tushki7 0:60d829a0353a 855 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
tushki7 0:60d829a0353a 856 * @{
tushki7 0:60d829a0353a 857 */
tushki7 0:60d829a0353a 858
tushki7 0:60d829a0353a 859 /** DMA - Register Layout Typedef */
tushki7 0:60d829a0353a 860 typedef struct {
tushki7 0:60d829a0353a 861 uint8_t RESERVED_0[256];
tushki7 0:60d829a0353a 862 struct { /* offset: 0x100, array step: 0x10 */
tushki7 0:60d829a0353a 863 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
tushki7 0:60d829a0353a 864 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
tushki7 0:60d829a0353a 865 union { /* offset: 0x108, array step: 0x10 */
tushki7 0:60d829a0353a 866 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
tushki7 0:60d829a0353a 867 struct { /* offset: 0x108, array step: 0x10 */
tushki7 0:60d829a0353a 868 uint8_t RESERVED_0[3];
tushki7 0:60d829a0353a 869 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
tushki7 0:60d829a0353a 870 } DMA_DSR_ACCESS8BIT;
tushki7 0:60d829a0353a 871 };
tushki7 0:60d829a0353a 872 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
tushki7 0:60d829a0353a 873 } DMA[4];
tushki7 0:60d829a0353a 874 } DMA_Type, *DMA_MemMapPtr;
tushki7 0:60d829a0353a 875
tushki7 0:60d829a0353a 876 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 877 -- DMA - Register accessor macros
tushki7 0:60d829a0353a 878 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 879
tushki7 0:60d829a0353a 880 /*!
tushki7 0:60d829a0353a 881 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
tushki7 0:60d829a0353a 882 * @{
tushki7 0:60d829a0353a 883 */
tushki7 0:60d829a0353a 884
tushki7 0:60d829a0353a 885
tushki7 0:60d829a0353a 886 /* DMA - Register accessors */
tushki7 0:60d829a0353a 887 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
tushki7 0:60d829a0353a 888 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
tushki7 0:60d829a0353a 889 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
tushki7 0:60d829a0353a 890 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
tushki7 0:60d829a0353a 891 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
tushki7 0:60d829a0353a 892
tushki7 0:60d829a0353a 893 /*!
tushki7 0:60d829a0353a 894 * @}
tushki7 0:60d829a0353a 895 */ /* end of group DMA_Register_Accessor_Macros */
tushki7 0:60d829a0353a 896
tushki7 0:60d829a0353a 897
tushki7 0:60d829a0353a 898 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 899 -- DMA Register Masks
tushki7 0:60d829a0353a 900 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 901
tushki7 0:60d829a0353a 902 /*!
tushki7 0:60d829a0353a 903 * @addtogroup DMA_Register_Masks DMA Register Masks
tushki7 0:60d829a0353a 904 * @{
tushki7 0:60d829a0353a 905 */
tushki7 0:60d829a0353a 906
tushki7 0:60d829a0353a 907 /* SAR Bit Fields */
tushki7 0:60d829a0353a 908 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 909 #define DMA_SAR_SAR_SHIFT 0
tushki7 0:60d829a0353a 910 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
tushki7 0:60d829a0353a 911 /* DAR Bit Fields */
tushki7 0:60d829a0353a 912 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 913 #define DMA_DAR_DAR_SHIFT 0
tushki7 0:60d829a0353a 914 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
tushki7 0:60d829a0353a 915 /* DSR_BCR Bit Fields */
tushki7 0:60d829a0353a 916 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
tushki7 0:60d829a0353a 917 #define DMA_DSR_BCR_BCR_SHIFT 0
tushki7 0:60d829a0353a 918 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
tushki7 0:60d829a0353a 919 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
tushki7 0:60d829a0353a 920 #define DMA_DSR_BCR_DONE_SHIFT 24
tushki7 0:60d829a0353a 921 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
tushki7 0:60d829a0353a 922 #define DMA_DSR_BCR_BSY_SHIFT 25
tushki7 0:60d829a0353a 923 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
tushki7 0:60d829a0353a 924 #define DMA_DSR_BCR_REQ_SHIFT 26
tushki7 0:60d829a0353a 925 #define DMA_DSR_BCR_BED_MASK 0x10000000u
tushki7 0:60d829a0353a 926 #define DMA_DSR_BCR_BED_SHIFT 28
tushki7 0:60d829a0353a 927 #define DMA_DSR_BCR_BES_MASK 0x20000000u
tushki7 0:60d829a0353a 928 #define DMA_DSR_BCR_BES_SHIFT 29
tushki7 0:60d829a0353a 929 #define DMA_DSR_BCR_CE_MASK 0x40000000u
tushki7 0:60d829a0353a 930 #define DMA_DSR_BCR_CE_SHIFT 30
tushki7 0:60d829a0353a 931 /* DCR Bit Fields */
tushki7 0:60d829a0353a 932 #define DMA_DCR_LCH2_MASK 0x3u
tushki7 0:60d829a0353a 933 #define DMA_DCR_LCH2_SHIFT 0
tushki7 0:60d829a0353a 934 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
tushki7 0:60d829a0353a 935 #define DMA_DCR_LCH1_MASK 0xCu
tushki7 0:60d829a0353a 936 #define DMA_DCR_LCH1_SHIFT 2
tushki7 0:60d829a0353a 937 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
tushki7 0:60d829a0353a 938 #define DMA_DCR_LINKCC_MASK 0x30u
tushki7 0:60d829a0353a 939 #define DMA_DCR_LINKCC_SHIFT 4
tushki7 0:60d829a0353a 940 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
tushki7 0:60d829a0353a 941 #define DMA_DCR_D_REQ_MASK 0x80u
tushki7 0:60d829a0353a 942 #define DMA_DCR_D_REQ_SHIFT 7
tushki7 0:60d829a0353a 943 #define DMA_DCR_DMOD_MASK 0xF00u
tushki7 0:60d829a0353a 944 #define DMA_DCR_DMOD_SHIFT 8
tushki7 0:60d829a0353a 945 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
tushki7 0:60d829a0353a 946 #define DMA_DCR_SMOD_MASK 0xF000u
tushki7 0:60d829a0353a 947 #define DMA_DCR_SMOD_SHIFT 12
tushki7 0:60d829a0353a 948 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
tushki7 0:60d829a0353a 949 #define DMA_DCR_START_MASK 0x10000u
tushki7 0:60d829a0353a 950 #define DMA_DCR_START_SHIFT 16
tushki7 0:60d829a0353a 951 #define DMA_DCR_DSIZE_MASK 0x60000u
tushki7 0:60d829a0353a 952 #define DMA_DCR_DSIZE_SHIFT 17
tushki7 0:60d829a0353a 953 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
tushki7 0:60d829a0353a 954 #define DMA_DCR_DINC_MASK 0x80000u
tushki7 0:60d829a0353a 955 #define DMA_DCR_DINC_SHIFT 19
tushki7 0:60d829a0353a 956 #define DMA_DCR_SSIZE_MASK 0x300000u
tushki7 0:60d829a0353a 957 #define DMA_DCR_SSIZE_SHIFT 20
tushki7 0:60d829a0353a 958 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
tushki7 0:60d829a0353a 959 #define DMA_DCR_SINC_MASK 0x400000u
tushki7 0:60d829a0353a 960 #define DMA_DCR_SINC_SHIFT 22
tushki7 0:60d829a0353a 961 #define DMA_DCR_EADREQ_MASK 0x800000u
tushki7 0:60d829a0353a 962 #define DMA_DCR_EADREQ_SHIFT 23
tushki7 0:60d829a0353a 963 #define DMA_DCR_AA_MASK 0x10000000u
tushki7 0:60d829a0353a 964 #define DMA_DCR_AA_SHIFT 28
tushki7 0:60d829a0353a 965 #define DMA_DCR_CS_MASK 0x20000000u
tushki7 0:60d829a0353a 966 #define DMA_DCR_CS_SHIFT 29
tushki7 0:60d829a0353a 967 #define DMA_DCR_ERQ_MASK 0x40000000u
tushki7 0:60d829a0353a 968 #define DMA_DCR_ERQ_SHIFT 30
tushki7 0:60d829a0353a 969 #define DMA_DCR_EINT_MASK 0x80000000u
tushki7 0:60d829a0353a 970 #define DMA_DCR_EINT_SHIFT 31
tushki7 0:60d829a0353a 971
tushki7 0:60d829a0353a 972 /*!
tushki7 0:60d829a0353a 973 * @}
tushki7 0:60d829a0353a 974 */ /* end of group DMA_Register_Masks */
tushki7 0:60d829a0353a 975
tushki7 0:60d829a0353a 976
tushki7 0:60d829a0353a 977 /* DMA - Peripheral instance base addresses */
tushki7 0:60d829a0353a 978 /** Peripheral DMA base address */
tushki7 0:60d829a0353a 979 #define DMA_BASE (0x40008000u)
tushki7 0:60d829a0353a 980 /** Peripheral DMA base pointer */
tushki7 0:60d829a0353a 981 #define DMA0 ((DMA_Type *)DMA_BASE)
tushki7 0:60d829a0353a 982 #define DMA_BASE_PTR (DMA0)
tushki7 0:60d829a0353a 983 /** Array initializer of DMA peripheral base addresses */
tushki7 0:60d829a0353a 984 #define DMA_BASE_ADDRS { DMA_BASE }
tushki7 0:60d829a0353a 985 /** Array initializer of DMA peripheral base pointers */
tushki7 0:60d829a0353a 986 #define DMA_BASE_PTRS { DMA0 }
tushki7 0:60d829a0353a 987 /** Interrupt vectors for the DMA peripheral type */
tushki7 0:60d829a0353a 988 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
tushki7 0:60d829a0353a 989
tushki7 0:60d829a0353a 990 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 991 -- DMA - Register accessor macros
tushki7 0:60d829a0353a 992 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 993
tushki7 0:60d829a0353a 994 /*!
tushki7 0:60d829a0353a 995 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
tushki7 0:60d829a0353a 996 * @{
tushki7 0:60d829a0353a 997 */
tushki7 0:60d829a0353a 998
tushki7 0:60d829a0353a 999
tushki7 0:60d829a0353a 1000 /* DMA - Register instance definitions */
tushki7 0:60d829a0353a 1001 /* DMA */
tushki7 0:60d829a0353a 1002 #define DMA_SAR0 DMA_SAR_REG(DMA0,0)
tushki7 0:60d829a0353a 1003 #define DMA_DAR0 DMA_DAR_REG(DMA0,0)
tushki7 0:60d829a0353a 1004 #define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA0,0)
tushki7 0:60d829a0353a 1005 #define DMA_DSR0 DMA_DSR_REG(DMA0,0)
tushki7 0:60d829a0353a 1006 #define DMA_DCR0 DMA_DCR_REG(DMA0,0)
tushki7 0:60d829a0353a 1007 #define DMA_SAR1 DMA_SAR_REG(DMA0,1)
tushki7 0:60d829a0353a 1008 #define DMA_DAR1 DMA_DAR_REG(DMA0,1)
tushki7 0:60d829a0353a 1009 #define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA0,1)
tushki7 0:60d829a0353a 1010 #define DMA_DSR1 DMA_DSR_REG(DMA0,1)
tushki7 0:60d829a0353a 1011 #define DMA_DCR1 DMA_DCR_REG(DMA0,1)
tushki7 0:60d829a0353a 1012 #define DMA_SAR2 DMA_SAR_REG(DMA0,2)
tushki7 0:60d829a0353a 1013 #define DMA_DAR2 DMA_DAR_REG(DMA0,2)
tushki7 0:60d829a0353a 1014 #define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA0,2)
tushki7 0:60d829a0353a 1015 #define DMA_DSR2 DMA_DSR_REG(DMA0,2)
tushki7 0:60d829a0353a 1016 #define DMA_DCR2 DMA_DCR_REG(DMA0,2)
tushki7 0:60d829a0353a 1017 #define DMA_SAR3 DMA_SAR_REG(DMA0,3)
tushki7 0:60d829a0353a 1018 #define DMA_DAR3 DMA_DAR_REG(DMA0,3)
tushki7 0:60d829a0353a 1019 #define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA0,3)
tushki7 0:60d829a0353a 1020 #define DMA_DSR3 DMA_DSR_REG(DMA0,3)
tushki7 0:60d829a0353a 1021 #define DMA_DCR3 DMA_DCR_REG(DMA0,3)
tushki7 0:60d829a0353a 1022
tushki7 0:60d829a0353a 1023 /* DMA - Register array accessors */
tushki7 0:60d829a0353a 1024 #define DMA_SAR(index) DMA_SAR_REG(DMA0,index)
tushki7 0:60d829a0353a 1025 #define DMA_DAR(index) DMA_DAR_REG(DMA0,index)
tushki7 0:60d829a0353a 1026 #define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA0,index)
tushki7 0:60d829a0353a 1027 #define DMA_DSR(index) DMA_DSR_REG(DMA0,index)
tushki7 0:60d829a0353a 1028 #define DMA_DCR(index) DMA_DCR_REG(DMA0,index)
tushki7 0:60d829a0353a 1029
tushki7 0:60d829a0353a 1030 /*!
tushki7 0:60d829a0353a 1031 * @}
tushki7 0:60d829a0353a 1032 */ /* end of group DMA_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1033
tushki7 0:60d829a0353a 1034
tushki7 0:60d829a0353a 1035 /*!
tushki7 0:60d829a0353a 1036 * @}
tushki7 0:60d829a0353a 1037 */ /* end of group DMA_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 1038
tushki7 0:60d829a0353a 1039
tushki7 0:60d829a0353a 1040 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1041 -- DMAMUX Peripheral Access Layer
tushki7 0:60d829a0353a 1042 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1043
tushki7 0:60d829a0353a 1044 /*!
tushki7 0:60d829a0353a 1045 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
tushki7 0:60d829a0353a 1046 * @{
tushki7 0:60d829a0353a 1047 */
tushki7 0:60d829a0353a 1048
tushki7 0:60d829a0353a 1049 /** DMAMUX - Register Layout Typedef */
tushki7 0:60d829a0353a 1050 typedef struct {
tushki7 0:60d829a0353a 1051 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
tushki7 0:60d829a0353a 1052 } DMAMUX_Type, *DMAMUX_MemMapPtr;
tushki7 0:60d829a0353a 1053
tushki7 0:60d829a0353a 1054 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1055 -- DMAMUX - Register accessor macros
tushki7 0:60d829a0353a 1056 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1057
tushki7 0:60d829a0353a 1058 /*!
tushki7 0:60d829a0353a 1059 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
tushki7 0:60d829a0353a 1060 * @{
tushki7 0:60d829a0353a 1061 */
tushki7 0:60d829a0353a 1062
tushki7 0:60d829a0353a 1063
tushki7 0:60d829a0353a 1064 /* DMAMUX - Register accessors */
tushki7 0:60d829a0353a 1065 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
tushki7 0:60d829a0353a 1066
tushki7 0:60d829a0353a 1067 /*!
tushki7 0:60d829a0353a 1068 * @}
tushki7 0:60d829a0353a 1069 */ /* end of group DMAMUX_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1070
tushki7 0:60d829a0353a 1071
tushki7 0:60d829a0353a 1072 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1073 -- DMAMUX Register Masks
tushki7 0:60d829a0353a 1074 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1075
tushki7 0:60d829a0353a 1076 /*!
tushki7 0:60d829a0353a 1077 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
tushki7 0:60d829a0353a 1078 * @{
tushki7 0:60d829a0353a 1079 */
tushki7 0:60d829a0353a 1080
tushki7 0:60d829a0353a 1081 /* CHCFG Bit Fields */
tushki7 0:60d829a0353a 1082 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
tushki7 0:60d829a0353a 1083 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
tushki7 0:60d829a0353a 1084 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
tushki7 0:60d829a0353a 1085 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
tushki7 0:60d829a0353a 1086 #define DMAMUX_CHCFG_TRIG_SHIFT 6
tushki7 0:60d829a0353a 1087 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
tushki7 0:60d829a0353a 1088 #define DMAMUX_CHCFG_ENBL_SHIFT 7
tushki7 0:60d829a0353a 1089
tushki7 0:60d829a0353a 1090 /*!
tushki7 0:60d829a0353a 1091 * @}
tushki7 0:60d829a0353a 1092 */ /* end of group DMAMUX_Register_Masks */
tushki7 0:60d829a0353a 1093
tushki7 0:60d829a0353a 1094
tushki7 0:60d829a0353a 1095 /* DMAMUX - Peripheral instance base addresses */
tushki7 0:60d829a0353a 1096 /** Peripheral DMAMUX0 base address */
tushki7 0:60d829a0353a 1097 #define DMAMUX0_BASE (0x40021000u)
tushki7 0:60d829a0353a 1098 /** Peripheral DMAMUX0 base pointer */
tushki7 0:60d829a0353a 1099 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
tushki7 0:60d829a0353a 1100 #define DMAMUX0_BASE_PTR (DMAMUX0)
tushki7 0:60d829a0353a 1101 /** Array initializer of DMAMUX peripheral base addresses */
tushki7 0:60d829a0353a 1102 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
tushki7 0:60d829a0353a 1103 /** Array initializer of DMAMUX peripheral base pointers */
tushki7 0:60d829a0353a 1104 #define DMAMUX_BASE_PTRS { DMAMUX0 }
tushki7 0:60d829a0353a 1105
tushki7 0:60d829a0353a 1106 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1107 -- DMAMUX - Register accessor macros
tushki7 0:60d829a0353a 1108 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1109
tushki7 0:60d829a0353a 1110 /*!
tushki7 0:60d829a0353a 1111 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
tushki7 0:60d829a0353a 1112 * @{
tushki7 0:60d829a0353a 1113 */
tushki7 0:60d829a0353a 1114
tushki7 0:60d829a0353a 1115
tushki7 0:60d829a0353a 1116 /* DMAMUX - Register instance definitions */
tushki7 0:60d829a0353a 1117 /* DMAMUX0 */
tushki7 0:60d829a0353a 1118 #define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0)
tushki7 0:60d829a0353a 1119 #define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1)
tushki7 0:60d829a0353a 1120 #define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2)
tushki7 0:60d829a0353a 1121 #define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3)
tushki7 0:60d829a0353a 1122
tushki7 0:60d829a0353a 1123 /* DMAMUX - Register array accessors */
tushki7 0:60d829a0353a 1124 #define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index)
tushki7 0:60d829a0353a 1125
tushki7 0:60d829a0353a 1126 /*!
tushki7 0:60d829a0353a 1127 * @}
tushki7 0:60d829a0353a 1128 */ /* end of group DMAMUX_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1129
tushki7 0:60d829a0353a 1130
tushki7 0:60d829a0353a 1131 /*!
tushki7 0:60d829a0353a 1132 * @}
tushki7 0:60d829a0353a 1133 */ /* end of group DMAMUX_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 1134
tushki7 0:60d829a0353a 1135
tushki7 0:60d829a0353a 1136 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1137 -- FLEXIO Peripheral Access Layer
tushki7 0:60d829a0353a 1138 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1139
tushki7 0:60d829a0353a 1140 /*!
tushki7 0:60d829a0353a 1141 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
tushki7 0:60d829a0353a 1142 * @{
tushki7 0:60d829a0353a 1143 */
tushki7 0:60d829a0353a 1144
tushki7 0:60d829a0353a 1145 /** FLEXIO - Register Layout Typedef */
tushki7 0:60d829a0353a 1146 typedef struct {
tushki7 0:60d829a0353a 1147 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
tushki7 0:60d829a0353a 1148 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
tushki7 0:60d829a0353a 1149 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
tushki7 0:60d829a0353a 1150 uint8_t RESERVED_0[4];
tushki7 0:60d829a0353a 1151 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
tushki7 0:60d829a0353a 1152 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
tushki7 0:60d829a0353a 1153 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
tushki7 0:60d829a0353a 1154 uint8_t RESERVED_1[4];
tushki7 0:60d829a0353a 1155 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
tushki7 0:60d829a0353a 1156 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
tushki7 0:60d829a0353a 1157 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
tushki7 0:60d829a0353a 1158 uint8_t RESERVED_2[4];
tushki7 0:60d829a0353a 1159 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
tushki7 0:60d829a0353a 1160 uint8_t RESERVED_3[76];
tushki7 0:60d829a0353a 1161 __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
tushki7 0:60d829a0353a 1162 uint8_t RESERVED_4[112];
tushki7 0:60d829a0353a 1163 __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
tushki7 0:60d829a0353a 1164 uint8_t RESERVED_5[240];
tushki7 0:60d829a0353a 1165 __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
tushki7 0:60d829a0353a 1166 uint8_t RESERVED_6[112];
tushki7 0:60d829a0353a 1167 __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x280, array step: 0x4 */
tushki7 0:60d829a0353a 1168 uint8_t RESERVED_7[112];
tushki7 0:60d829a0353a 1169 __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
tushki7 0:60d829a0353a 1170 uint8_t RESERVED_8[112];
tushki7 0:60d829a0353a 1171 __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x380, array step: 0x4 */
tushki7 0:60d829a0353a 1172 uint8_t RESERVED_9[112];
tushki7 0:60d829a0353a 1173 __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
tushki7 0:60d829a0353a 1174 uint8_t RESERVED_10[112];
tushki7 0:60d829a0353a 1175 __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
tushki7 0:60d829a0353a 1176 uint8_t RESERVED_11[112];
tushki7 0:60d829a0353a 1177 __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
tushki7 0:60d829a0353a 1178 } FLEXIO_Type, *FLEXIO_MemMapPtr;
tushki7 0:60d829a0353a 1179
tushki7 0:60d829a0353a 1180 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1181 -- FLEXIO - Register accessor macros
tushki7 0:60d829a0353a 1182 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1183
tushki7 0:60d829a0353a 1184 /*!
tushki7 0:60d829a0353a 1185 * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
tushki7 0:60d829a0353a 1186 * @{
tushki7 0:60d829a0353a 1187 */
tushki7 0:60d829a0353a 1188
tushki7 0:60d829a0353a 1189
tushki7 0:60d829a0353a 1190 /* FLEXIO - Register accessors */
tushki7 0:60d829a0353a 1191 #define FLEXIO_VERID_REG(base) ((base)->VERID)
tushki7 0:60d829a0353a 1192 #define FLEXIO_PARAM_REG(base) ((base)->PARAM)
tushki7 0:60d829a0353a 1193 #define FLEXIO_CTRL_REG(base) ((base)->CTRL)
tushki7 0:60d829a0353a 1194 #define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT)
tushki7 0:60d829a0353a 1195 #define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR)
tushki7 0:60d829a0353a 1196 #define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT)
tushki7 0:60d829a0353a 1197 #define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN)
tushki7 0:60d829a0353a 1198 #define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN)
tushki7 0:60d829a0353a 1199 #define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN)
tushki7 0:60d829a0353a 1200 #define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN)
tushki7 0:60d829a0353a 1201 #define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index])
tushki7 0:60d829a0353a 1202 #define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index])
tushki7 0:60d829a0353a 1203 #define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index])
tushki7 0:60d829a0353a 1204 #define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index])
tushki7 0:60d829a0353a 1205 #define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index])
tushki7 0:60d829a0353a 1206 #define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index])
tushki7 0:60d829a0353a 1207 #define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index])
tushki7 0:60d829a0353a 1208 #define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index])
tushki7 0:60d829a0353a 1209 #define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index])
tushki7 0:60d829a0353a 1210
tushki7 0:60d829a0353a 1211 /*!
tushki7 0:60d829a0353a 1212 * @}
tushki7 0:60d829a0353a 1213 */ /* end of group FLEXIO_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1214
tushki7 0:60d829a0353a 1215
tushki7 0:60d829a0353a 1216 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1217 -- FLEXIO Register Masks
tushki7 0:60d829a0353a 1218 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1219
tushki7 0:60d829a0353a 1220 /*!
tushki7 0:60d829a0353a 1221 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
tushki7 0:60d829a0353a 1222 * @{
tushki7 0:60d829a0353a 1223 */
tushki7 0:60d829a0353a 1224
tushki7 0:60d829a0353a 1225 /* VERID Bit Fields */
tushki7 0:60d829a0353a 1226 #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
tushki7 0:60d829a0353a 1227 #define FLEXIO_VERID_FEATURE_SHIFT 0
tushki7 0:60d829a0353a 1228 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
tushki7 0:60d829a0353a 1229 #define FLEXIO_VERID_MINOR_MASK 0xFF0000u
tushki7 0:60d829a0353a 1230 #define FLEXIO_VERID_MINOR_SHIFT 16
tushki7 0:60d829a0353a 1231 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
tushki7 0:60d829a0353a 1232 #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
tushki7 0:60d829a0353a 1233 #define FLEXIO_VERID_MAJOR_SHIFT 24
tushki7 0:60d829a0353a 1234 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
tushki7 0:60d829a0353a 1235 /* PARAM Bit Fields */
tushki7 0:60d829a0353a 1236 #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
tushki7 0:60d829a0353a 1237 #define FLEXIO_PARAM_SHIFTER_SHIFT 0
tushki7 0:60d829a0353a 1238 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
tushki7 0:60d829a0353a 1239 #define FLEXIO_PARAM_TIMER_MASK 0xFF00u
tushki7 0:60d829a0353a 1240 #define FLEXIO_PARAM_TIMER_SHIFT 8
tushki7 0:60d829a0353a 1241 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
tushki7 0:60d829a0353a 1242 #define FLEXIO_PARAM_PIN_MASK 0xFF0000u
tushki7 0:60d829a0353a 1243 #define FLEXIO_PARAM_PIN_SHIFT 16
tushki7 0:60d829a0353a 1244 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
tushki7 0:60d829a0353a 1245 #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
tushki7 0:60d829a0353a 1246 #define FLEXIO_PARAM_TRIGGER_SHIFT 24
tushki7 0:60d829a0353a 1247 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
tushki7 0:60d829a0353a 1248 /* CTRL Bit Fields */
tushki7 0:60d829a0353a 1249 #define FLEXIO_CTRL_FLEXEN_MASK 0x1u
tushki7 0:60d829a0353a 1250 #define FLEXIO_CTRL_FLEXEN_SHIFT 0
tushki7 0:60d829a0353a 1251 #define FLEXIO_CTRL_SWRST_MASK 0x2u
tushki7 0:60d829a0353a 1252 #define FLEXIO_CTRL_SWRST_SHIFT 1
tushki7 0:60d829a0353a 1253 #define FLEXIO_CTRL_FASTACC_MASK 0x4u
tushki7 0:60d829a0353a 1254 #define FLEXIO_CTRL_FASTACC_SHIFT 2
tushki7 0:60d829a0353a 1255 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u
tushki7 0:60d829a0353a 1256 #define FLEXIO_CTRL_DBGE_SHIFT 30
tushki7 0:60d829a0353a 1257 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
tushki7 0:60d829a0353a 1258 #define FLEXIO_CTRL_DOZEN_SHIFT 31
tushki7 0:60d829a0353a 1259 /* SHIFTSTAT Bit Fields */
tushki7 0:60d829a0353a 1260 #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
tushki7 0:60d829a0353a 1261 #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0
tushki7 0:60d829a0353a 1262 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
tushki7 0:60d829a0353a 1263 /* SHIFTERR Bit Fields */
tushki7 0:60d829a0353a 1264 #define FLEXIO_SHIFTERR_SEF_MASK 0xFu
tushki7 0:60d829a0353a 1265 #define FLEXIO_SHIFTERR_SEF_SHIFT 0
tushki7 0:60d829a0353a 1266 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
tushki7 0:60d829a0353a 1267 /* TIMSTAT Bit Fields */
tushki7 0:60d829a0353a 1268 #define FLEXIO_TIMSTAT_TSF_MASK 0xFu
tushki7 0:60d829a0353a 1269 #define FLEXIO_TIMSTAT_TSF_SHIFT 0
tushki7 0:60d829a0353a 1270 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
tushki7 0:60d829a0353a 1271 /* SHIFTSIEN Bit Fields */
tushki7 0:60d829a0353a 1272 #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
tushki7 0:60d829a0353a 1273 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0
tushki7 0:60d829a0353a 1274 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
tushki7 0:60d829a0353a 1275 /* SHIFTEIEN Bit Fields */
tushki7 0:60d829a0353a 1276 #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
tushki7 0:60d829a0353a 1277 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0
tushki7 0:60d829a0353a 1278 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
tushki7 0:60d829a0353a 1279 /* TIMIEN Bit Fields */
tushki7 0:60d829a0353a 1280 #define FLEXIO_TIMIEN_TEIE_MASK 0xFu
tushki7 0:60d829a0353a 1281 #define FLEXIO_TIMIEN_TEIE_SHIFT 0
tushki7 0:60d829a0353a 1282 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
tushki7 0:60d829a0353a 1283 /* SHIFTSDEN Bit Fields */
tushki7 0:60d829a0353a 1284 #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
tushki7 0:60d829a0353a 1285 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0
tushki7 0:60d829a0353a 1286 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
tushki7 0:60d829a0353a 1287 /* SHIFTCTL Bit Fields */
tushki7 0:60d829a0353a 1288 #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
tushki7 0:60d829a0353a 1289 #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0
tushki7 0:60d829a0353a 1290 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
tushki7 0:60d829a0353a 1291 #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
tushki7 0:60d829a0353a 1292 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7
tushki7 0:60d829a0353a 1293 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
tushki7 0:60d829a0353a 1294 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8
tushki7 0:60d829a0353a 1295 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
tushki7 0:60d829a0353a 1296 #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
tushki7 0:60d829a0353a 1297 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16
tushki7 0:60d829a0353a 1298 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
tushki7 0:60d829a0353a 1299 #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
tushki7 0:60d829a0353a 1300 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23
tushki7 0:60d829a0353a 1301 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
tushki7 0:60d829a0353a 1302 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24
tushki7 0:60d829a0353a 1303 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
tushki7 0:60d829a0353a 1304 /* SHIFTCFG Bit Fields */
tushki7 0:60d829a0353a 1305 #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
tushki7 0:60d829a0353a 1306 #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0
tushki7 0:60d829a0353a 1307 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
tushki7 0:60d829a0353a 1308 #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
tushki7 0:60d829a0353a 1309 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4
tushki7 0:60d829a0353a 1310 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
tushki7 0:60d829a0353a 1311 #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
tushki7 0:60d829a0353a 1312 #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8
tushki7 0:60d829a0353a 1313 /* SHIFTBUF Bit Fields */
tushki7 0:60d829a0353a 1314 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1315 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0
tushki7 0:60d829a0353a 1316 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
tushki7 0:60d829a0353a 1317 /* SHIFTBUFBBS Bit Fields */
tushki7 0:60d829a0353a 1318 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1319 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0
tushki7 0:60d829a0353a 1320 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
tushki7 0:60d829a0353a 1321 /* SHIFTBUFBYS Bit Fields */
tushki7 0:60d829a0353a 1322 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1323 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0
tushki7 0:60d829a0353a 1324 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
tushki7 0:60d829a0353a 1325 /* SHIFTBUFBIS Bit Fields */
tushki7 0:60d829a0353a 1326 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1327 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0
tushki7 0:60d829a0353a 1328 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
tushki7 0:60d829a0353a 1329 /* TIMCTL Bit Fields */
tushki7 0:60d829a0353a 1330 #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
tushki7 0:60d829a0353a 1331 #define FLEXIO_TIMCTL_TIMOD_SHIFT 0
tushki7 0:60d829a0353a 1332 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
tushki7 0:60d829a0353a 1333 #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
tushki7 0:60d829a0353a 1334 #define FLEXIO_TIMCTL_PINPOL_SHIFT 7
tushki7 0:60d829a0353a 1335 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
tushki7 0:60d829a0353a 1336 #define FLEXIO_TIMCTL_PINSEL_SHIFT 8
tushki7 0:60d829a0353a 1337 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
tushki7 0:60d829a0353a 1338 #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
tushki7 0:60d829a0353a 1339 #define FLEXIO_TIMCTL_PINCFG_SHIFT 16
tushki7 0:60d829a0353a 1340 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
tushki7 0:60d829a0353a 1341 #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
tushki7 0:60d829a0353a 1342 #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22
tushki7 0:60d829a0353a 1343 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
tushki7 0:60d829a0353a 1344 #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23
tushki7 0:60d829a0353a 1345 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
tushki7 0:60d829a0353a 1346 #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24
tushki7 0:60d829a0353a 1347 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
tushki7 0:60d829a0353a 1348 /* TIMCFG Bit Fields */
tushki7 0:60d829a0353a 1349 #define FLEXIO_TIMCFG_TSTART_MASK 0x2u
tushki7 0:60d829a0353a 1350 #define FLEXIO_TIMCFG_TSTART_SHIFT 1
tushki7 0:60d829a0353a 1351 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
tushki7 0:60d829a0353a 1352 #define FLEXIO_TIMCFG_TSTOP_SHIFT 4
tushki7 0:60d829a0353a 1353 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
tushki7 0:60d829a0353a 1354 #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
tushki7 0:60d829a0353a 1355 #define FLEXIO_TIMCFG_TIMENA_SHIFT 8
tushki7 0:60d829a0353a 1356 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
tushki7 0:60d829a0353a 1357 #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
tushki7 0:60d829a0353a 1358 #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12
tushki7 0:60d829a0353a 1359 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
tushki7 0:60d829a0353a 1360 #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
tushki7 0:60d829a0353a 1361 #define FLEXIO_TIMCFG_TIMRST_SHIFT 16
tushki7 0:60d829a0353a 1362 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
tushki7 0:60d829a0353a 1363 #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
tushki7 0:60d829a0353a 1364 #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20
tushki7 0:60d829a0353a 1365 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
tushki7 0:60d829a0353a 1366 #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
tushki7 0:60d829a0353a 1367 #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24
tushki7 0:60d829a0353a 1368 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
tushki7 0:60d829a0353a 1369 /* TIMCMP Bit Fields */
tushki7 0:60d829a0353a 1370 #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
tushki7 0:60d829a0353a 1371 #define FLEXIO_TIMCMP_CMP_SHIFT 0
tushki7 0:60d829a0353a 1372 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
tushki7 0:60d829a0353a 1373
tushki7 0:60d829a0353a 1374 /*!
tushki7 0:60d829a0353a 1375 * @}
tushki7 0:60d829a0353a 1376 */ /* end of group FLEXIO_Register_Masks */
tushki7 0:60d829a0353a 1377
tushki7 0:60d829a0353a 1378
tushki7 0:60d829a0353a 1379 /* FLEXIO - Peripheral instance base addresses */
tushki7 0:60d829a0353a 1380 /** Peripheral FLEXIO base address */
tushki7 0:60d829a0353a 1381 #define FLEXIO_BASE (0x4005F000u)
tushki7 0:60d829a0353a 1382 /** Peripheral FLEXIO base pointer */
tushki7 0:60d829a0353a 1383 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
tushki7 0:60d829a0353a 1384 #define FLEXIO_BASE_PTR (FLEXIO)
tushki7 0:60d829a0353a 1385 /** Array initializer of FLEXIO peripheral base addresses */
tushki7 0:60d829a0353a 1386 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
tushki7 0:60d829a0353a 1387 /** Array initializer of FLEXIO peripheral base pointers */
tushki7 0:60d829a0353a 1388 #define FLEXIO_BASE_PTRS { FLEXIO }
tushki7 0:60d829a0353a 1389
tushki7 0:60d829a0353a 1390 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1391 -- FLEXIO - Register accessor macros
tushki7 0:60d829a0353a 1392 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1393
tushki7 0:60d829a0353a 1394 /*!
tushki7 0:60d829a0353a 1395 * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
tushki7 0:60d829a0353a 1396 * @{
tushki7 0:60d829a0353a 1397 */
tushki7 0:60d829a0353a 1398
tushki7 0:60d829a0353a 1399
tushki7 0:60d829a0353a 1400 /* FLEXIO - Register instance definitions */
tushki7 0:60d829a0353a 1401 /* FLEXIO */
tushki7 0:60d829a0353a 1402 #define FLEXIO_VERID FLEXIO_VERID_REG(FLEXIO)
tushki7 0:60d829a0353a 1403 #define FLEXIO_PARAM FLEXIO_PARAM_REG(FLEXIO)
tushki7 0:60d829a0353a 1404 #define FLEXIO_CTRL FLEXIO_CTRL_REG(FLEXIO)
tushki7 0:60d829a0353a 1405 #define FLEXIO_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO)
tushki7 0:60d829a0353a 1406 #define FLEXIO_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO)
tushki7 0:60d829a0353a 1407 #define FLEXIO_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO)
tushki7 0:60d829a0353a 1408 #define FLEXIO_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO)
tushki7 0:60d829a0353a 1409 #define FLEXIO_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO)
tushki7 0:60d829a0353a 1410 #define FLEXIO_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO)
tushki7 0:60d829a0353a 1411 #define FLEXIO_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO)
tushki7 0:60d829a0353a 1412 #define FLEXIO_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1413 #define FLEXIO_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1414 #define FLEXIO_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1415 #define FLEXIO_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1416 #define FLEXIO_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1417 #define FLEXIO_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1418 #define FLEXIO_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1419 #define FLEXIO_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1420 #define FLEXIO_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1421 #define FLEXIO_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1422 #define FLEXIO_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1423 #define FLEXIO_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1424 #define FLEXIO_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1425 #define FLEXIO_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1426 #define FLEXIO_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1427 #define FLEXIO_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1428 #define FLEXIO_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1429 #define FLEXIO_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1430 #define FLEXIO_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1431 #define FLEXIO_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1432 #define FLEXIO_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1433 #define FLEXIO_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1434 #define FLEXIO_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1435 #define FLEXIO_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1436 #define FLEXIO_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1437 #define FLEXIO_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1438 #define FLEXIO_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1439 #define FLEXIO_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1440 #define FLEXIO_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1441 #define FLEXIO_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1442 #define FLEXIO_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1443 #define FLEXIO_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1444 #define FLEXIO_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO,0)
tushki7 0:60d829a0353a 1445 #define FLEXIO_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO,1)
tushki7 0:60d829a0353a 1446 #define FLEXIO_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO,2)
tushki7 0:60d829a0353a 1447 #define FLEXIO_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO,3)
tushki7 0:60d829a0353a 1448
tushki7 0:60d829a0353a 1449 /* FLEXIO - Register array accessors */
tushki7 0:60d829a0353a 1450 #define FLEXIO_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1451 #define FLEXIO_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1452 #define FLEXIO_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1453 #define FLEXIO_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1454 #define FLEXIO_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1455 #define FLEXIO_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1456 #define FLEXIO_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1457 #define FLEXIO_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1458 #define FLEXIO_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO,index)
tushki7 0:60d829a0353a 1459
tushki7 0:60d829a0353a 1460 /*!
tushki7 0:60d829a0353a 1461 * @}
tushki7 0:60d829a0353a 1462 */ /* end of group FLEXIO_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1463
tushki7 0:60d829a0353a 1464
tushki7 0:60d829a0353a 1465 /*!
tushki7 0:60d829a0353a 1466 * @}
tushki7 0:60d829a0353a 1467 */ /* end of group FLEXIO_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 1468
tushki7 0:60d829a0353a 1469
tushki7 0:60d829a0353a 1470 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1471 -- FTFA Peripheral Access Layer
tushki7 0:60d829a0353a 1472 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1473
tushki7 0:60d829a0353a 1474 /*!
tushki7 0:60d829a0353a 1475 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
tushki7 0:60d829a0353a 1476 * @{
tushki7 0:60d829a0353a 1477 */
tushki7 0:60d829a0353a 1478
tushki7 0:60d829a0353a 1479 /** FTFA - Register Layout Typedef */
tushki7 0:60d829a0353a 1480 typedef struct {
tushki7 0:60d829a0353a 1481 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
tushki7 0:60d829a0353a 1482 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
tushki7 0:60d829a0353a 1483 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
tushki7 0:60d829a0353a 1484 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
tushki7 0:60d829a0353a 1485 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
tushki7 0:60d829a0353a 1486 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
tushki7 0:60d829a0353a 1487 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
tushki7 0:60d829a0353a 1488 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
tushki7 0:60d829a0353a 1489 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
tushki7 0:60d829a0353a 1490 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
tushki7 0:60d829a0353a 1491 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
tushki7 0:60d829a0353a 1492 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
tushki7 0:60d829a0353a 1493 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
tushki7 0:60d829a0353a 1494 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
tushki7 0:60d829a0353a 1495 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
tushki7 0:60d829a0353a 1496 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
tushki7 0:60d829a0353a 1497 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
tushki7 0:60d829a0353a 1498 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
tushki7 0:60d829a0353a 1499 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
tushki7 0:60d829a0353a 1500 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
tushki7 0:60d829a0353a 1501 } FTFA_Type, *FTFA_MemMapPtr;
tushki7 0:60d829a0353a 1502
tushki7 0:60d829a0353a 1503 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1504 -- FTFA - Register accessor macros
tushki7 0:60d829a0353a 1505 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1506
tushki7 0:60d829a0353a 1507 /*!
tushki7 0:60d829a0353a 1508 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
tushki7 0:60d829a0353a 1509 * @{
tushki7 0:60d829a0353a 1510 */
tushki7 0:60d829a0353a 1511
tushki7 0:60d829a0353a 1512
tushki7 0:60d829a0353a 1513 /* FTFA - Register accessors */
tushki7 0:60d829a0353a 1514 #define FTFA_FSTAT_REG(base) ((base)->FSTAT)
tushki7 0:60d829a0353a 1515 #define FTFA_FCNFG_REG(base) ((base)->FCNFG)
tushki7 0:60d829a0353a 1516 #define FTFA_FSEC_REG(base) ((base)->FSEC)
tushki7 0:60d829a0353a 1517 #define FTFA_FOPT_REG(base) ((base)->FOPT)
tushki7 0:60d829a0353a 1518 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
tushki7 0:60d829a0353a 1519 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
tushki7 0:60d829a0353a 1520 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
tushki7 0:60d829a0353a 1521 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
tushki7 0:60d829a0353a 1522 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
tushki7 0:60d829a0353a 1523 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
tushki7 0:60d829a0353a 1524 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
tushki7 0:60d829a0353a 1525 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
tushki7 0:60d829a0353a 1526 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
tushki7 0:60d829a0353a 1527 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
tushki7 0:60d829a0353a 1528 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
tushki7 0:60d829a0353a 1529 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
tushki7 0:60d829a0353a 1530 #define FTFA_FPROT3_REG(base) ((base)->FPROT3)
tushki7 0:60d829a0353a 1531 #define FTFA_FPROT2_REG(base) ((base)->FPROT2)
tushki7 0:60d829a0353a 1532 #define FTFA_FPROT1_REG(base) ((base)->FPROT1)
tushki7 0:60d829a0353a 1533 #define FTFA_FPROT0_REG(base) ((base)->FPROT0)
tushki7 0:60d829a0353a 1534
tushki7 0:60d829a0353a 1535 /*!
tushki7 0:60d829a0353a 1536 * @}
tushki7 0:60d829a0353a 1537 */ /* end of group FTFA_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1538
tushki7 0:60d829a0353a 1539
tushki7 0:60d829a0353a 1540 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1541 -- FTFA Register Masks
tushki7 0:60d829a0353a 1542 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1543
tushki7 0:60d829a0353a 1544 /*!
tushki7 0:60d829a0353a 1545 * @addtogroup FTFA_Register_Masks FTFA Register Masks
tushki7 0:60d829a0353a 1546 * @{
tushki7 0:60d829a0353a 1547 */
tushki7 0:60d829a0353a 1548
tushki7 0:60d829a0353a 1549 /* FSTAT Bit Fields */
tushki7 0:60d829a0353a 1550 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
tushki7 0:60d829a0353a 1551 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
tushki7 0:60d829a0353a 1552 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
tushki7 0:60d829a0353a 1553 #define FTFA_FSTAT_FPVIOL_SHIFT 4
tushki7 0:60d829a0353a 1554 #define FTFA_FSTAT_ACCERR_MASK 0x20u
tushki7 0:60d829a0353a 1555 #define FTFA_FSTAT_ACCERR_SHIFT 5
tushki7 0:60d829a0353a 1556 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
tushki7 0:60d829a0353a 1557 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
tushki7 0:60d829a0353a 1558 #define FTFA_FSTAT_CCIF_MASK 0x80u
tushki7 0:60d829a0353a 1559 #define FTFA_FSTAT_CCIF_SHIFT 7
tushki7 0:60d829a0353a 1560 /* FCNFG Bit Fields */
tushki7 0:60d829a0353a 1561 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
tushki7 0:60d829a0353a 1562 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
tushki7 0:60d829a0353a 1563 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
tushki7 0:60d829a0353a 1564 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
tushki7 0:60d829a0353a 1565 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
tushki7 0:60d829a0353a 1566 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
tushki7 0:60d829a0353a 1567 #define FTFA_FCNFG_CCIE_MASK 0x80u
tushki7 0:60d829a0353a 1568 #define FTFA_FCNFG_CCIE_SHIFT 7
tushki7 0:60d829a0353a 1569 /* FSEC Bit Fields */
tushki7 0:60d829a0353a 1570 #define FTFA_FSEC_SEC_MASK 0x3u
tushki7 0:60d829a0353a 1571 #define FTFA_FSEC_SEC_SHIFT 0
tushki7 0:60d829a0353a 1572 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
tushki7 0:60d829a0353a 1573 #define FTFA_FSEC_FSLACC_MASK 0xCu
tushki7 0:60d829a0353a 1574 #define FTFA_FSEC_FSLACC_SHIFT 2
tushki7 0:60d829a0353a 1575 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
tushki7 0:60d829a0353a 1576 #define FTFA_FSEC_MEEN_MASK 0x30u
tushki7 0:60d829a0353a 1577 #define FTFA_FSEC_MEEN_SHIFT 4
tushki7 0:60d829a0353a 1578 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
tushki7 0:60d829a0353a 1579 #define FTFA_FSEC_KEYEN_MASK 0xC0u
tushki7 0:60d829a0353a 1580 #define FTFA_FSEC_KEYEN_SHIFT 6
tushki7 0:60d829a0353a 1581 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
tushki7 0:60d829a0353a 1582 /* FOPT Bit Fields */
tushki7 0:60d829a0353a 1583 #define FTFA_FOPT_OPT_MASK 0xFFu
tushki7 0:60d829a0353a 1584 #define FTFA_FOPT_OPT_SHIFT 0
tushki7 0:60d829a0353a 1585 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
tushki7 0:60d829a0353a 1586 /* FCCOB3 Bit Fields */
tushki7 0:60d829a0353a 1587 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1588 #define FTFA_FCCOB3_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1589 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
tushki7 0:60d829a0353a 1590 /* FCCOB2 Bit Fields */
tushki7 0:60d829a0353a 1591 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1592 #define FTFA_FCCOB2_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1593 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
tushki7 0:60d829a0353a 1594 /* FCCOB1 Bit Fields */
tushki7 0:60d829a0353a 1595 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1596 #define FTFA_FCCOB1_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1597 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
tushki7 0:60d829a0353a 1598 /* FCCOB0 Bit Fields */
tushki7 0:60d829a0353a 1599 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1600 #define FTFA_FCCOB0_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1601 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
tushki7 0:60d829a0353a 1602 /* FCCOB7 Bit Fields */
tushki7 0:60d829a0353a 1603 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1604 #define FTFA_FCCOB7_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1605 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
tushki7 0:60d829a0353a 1606 /* FCCOB6 Bit Fields */
tushki7 0:60d829a0353a 1607 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1608 #define FTFA_FCCOB6_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1609 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
tushki7 0:60d829a0353a 1610 /* FCCOB5 Bit Fields */
tushki7 0:60d829a0353a 1611 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1612 #define FTFA_FCCOB5_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1613 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
tushki7 0:60d829a0353a 1614 /* FCCOB4 Bit Fields */
tushki7 0:60d829a0353a 1615 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1616 #define FTFA_FCCOB4_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1617 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
tushki7 0:60d829a0353a 1618 /* FCCOBB Bit Fields */
tushki7 0:60d829a0353a 1619 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1620 #define FTFA_FCCOBB_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1621 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
tushki7 0:60d829a0353a 1622 /* FCCOBA Bit Fields */
tushki7 0:60d829a0353a 1623 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1624 #define FTFA_FCCOBA_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1625 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
tushki7 0:60d829a0353a 1626 /* FCCOB9 Bit Fields */
tushki7 0:60d829a0353a 1627 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1628 #define FTFA_FCCOB9_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1629 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
tushki7 0:60d829a0353a 1630 /* FCCOB8 Bit Fields */
tushki7 0:60d829a0353a 1631 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
tushki7 0:60d829a0353a 1632 #define FTFA_FCCOB8_CCOBn_SHIFT 0
tushki7 0:60d829a0353a 1633 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
tushki7 0:60d829a0353a 1634 /* FPROT3 Bit Fields */
tushki7 0:60d829a0353a 1635 #define FTFA_FPROT3_PROT_MASK 0xFFu
tushki7 0:60d829a0353a 1636 #define FTFA_FPROT3_PROT_SHIFT 0
tushki7 0:60d829a0353a 1637 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
tushki7 0:60d829a0353a 1638 /* FPROT2 Bit Fields */
tushki7 0:60d829a0353a 1639 #define FTFA_FPROT2_PROT_MASK 0xFFu
tushki7 0:60d829a0353a 1640 #define FTFA_FPROT2_PROT_SHIFT 0
tushki7 0:60d829a0353a 1641 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
tushki7 0:60d829a0353a 1642 /* FPROT1 Bit Fields */
tushki7 0:60d829a0353a 1643 #define FTFA_FPROT1_PROT_MASK 0xFFu
tushki7 0:60d829a0353a 1644 #define FTFA_FPROT1_PROT_SHIFT 0
tushki7 0:60d829a0353a 1645 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
tushki7 0:60d829a0353a 1646 /* FPROT0 Bit Fields */
tushki7 0:60d829a0353a 1647 #define FTFA_FPROT0_PROT_MASK 0xFFu
tushki7 0:60d829a0353a 1648 #define FTFA_FPROT0_PROT_SHIFT 0
tushki7 0:60d829a0353a 1649 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
tushki7 0:60d829a0353a 1650
tushki7 0:60d829a0353a 1651 /*!
tushki7 0:60d829a0353a 1652 * @}
tushki7 0:60d829a0353a 1653 */ /* end of group FTFA_Register_Masks */
tushki7 0:60d829a0353a 1654
tushki7 0:60d829a0353a 1655
tushki7 0:60d829a0353a 1656 /* FTFA - Peripheral instance base addresses */
tushki7 0:60d829a0353a 1657 /** Peripheral FTFA base address */
tushki7 0:60d829a0353a 1658 #define FTFA_BASE (0x40020000u)
tushki7 0:60d829a0353a 1659 /** Peripheral FTFA base pointer */
tushki7 0:60d829a0353a 1660 #define FTFA ((FTFA_Type *)FTFA_BASE)
tushki7 0:60d829a0353a 1661 #define FTFA_BASE_PTR (FTFA)
tushki7 0:60d829a0353a 1662 /** Array initializer of FTFA peripheral base addresses */
tushki7 0:60d829a0353a 1663 #define FTFA_BASE_ADDRS { FTFA_BASE }
tushki7 0:60d829a0353a 1664 /** Array initializer of FTFA peripheral base pointers */
tushki7 0:60d829a0353a 1665 #define FTFA_BASE_PTRS { FTFA }
tushki7 0:60d829a0353a 1666 /** Interrupt vectors for the FTFA peripheral type */
tushki7 0:60d829a0353a 1667 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
tushki7 0:60d829a0353a 1668
tushki7 0:60d829a0353a 1669 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1670 -- FTFA - Register accessor macros
tushki7 0:60d829a0353a 1671 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1672
tushki7 0:60d829a0353a 1673 /*!
tushki7 0:60d829a0353a 1674 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
tushki7 0:60d829a0353a 1675 * @{
tushki7 0:60d829a0353a 1676 */
tushki7 0:60d829a0353a 1677
tushki7 0:60d829a0353a 1678
tushki7 0:60d829a0353a 1679 /* FTFA - Register instance definitions */
tushki7 0:60d829a0353a 1680 /* FTFA */
tushki7 0:60d829a0353a 1681 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
tushki7 0:60d829a0353a 1682 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
tushki7 0:60d829a0353a 1683 #define FTFA_FSEC FTFA_FSEC_REG(FTFA)
tushki7 0:60d829a0353a 1684 #define FTFA_FOPT FTFA_FOPT_REG(FTFA)
tushki7 0:60d829a0353a 1685 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
tushki7 0:60d829a0353a 1686 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
tushki7 0:60d829a0353a 1687 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
tushki7 0:60d829a0353a 1688 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
tushki7 0:60d829a0353a 1689 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
tushki7 0:60d829a0353a 1690 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
tushki7 0:60d829a0353a 1691 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
tushki7 0:60d829a0353a 1692 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
tushki7 0:60d829a0353a 1693 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
tushki7 0:60d829a0353a 1694 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
tushki7 0:60d829a0353a 1695 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
tushki7 0:60d829a0353a 1696 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
tushki7 0:60d829a0353a 1697 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
tushki7 0:60d829a0353a 1698 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
tushki7 0:60d829a0353a 1699 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
tushki7 0:60d829a0353a 1700 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
tushki7 0:60d829a0353a 1701
tushki7 0:60d829a0353a 1702 /*!
tushki7 0:60d829a0353a 1703 * @}
tushki7 0:60d829a0353a 1704 */ /* end of group FTFA_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1705
tushki7 0:60d829a0353a 1706
tushki7 0:60d829a0353a 1707 /*!
tushki7 0:60d829a0353a 1708 * @}
tushki7 0:60d829a0353a 1709 */ /* end of group FTFA_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 1710
tushki7 0:60d829a0353a 1711
tushki7 0:60d829a0353a 1712 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1713 -- GPIO Peripheral Access Layer
tushki7 0:60d829a0353a 1714 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1715
tushki7 0:60d829a0353a 1716 /*!
tushki7 0:60d829a0353a 1717 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
tushki7 0:60d829a0353a 1718 * @{
tushki7 0:60d829a0353a 1719 */
tushki7 0:60d829a0353a 1720
tushki7 0:60d829a0353a 1721 /** GPIO - Register Layout Typedef */
tushki7 0:60d829a0353a 1722 typedef struct {
tushki7 0:60d829a0353a 1723 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
tushki7 0:60d829a0353a 1724 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
tushki7 0:60d829a0353a 1725 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
tushki7 0:60d829a0353a 1726 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
tushki7 0:60d829a0353a 1727 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
tushki7 0:60d829a0353a 1728 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
tushki7 0:60d829a0353a 1729 } GPIO_Type, *GPIO_MemMapPtr;
tushki7 0:60d829a0353a 1730
tushki7 0:60d829a0353a 1731 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1732 -- GPIO - Register accessor macros
tushki7 0:60d829a0353a 1733 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1734
tushki7 0:60d829a0353a 1735 /*!
tushki7 0:60d829a0353a 1736 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
tushki7 0:60d829a0353a 1737 * @{
tushki7 0:60d829a0353a 1738 */
tushki7 0:60d829a0353a 1739
tushki7 0:60d829a0353a 1740
tushki7 0:60d829a0353a 1741 /* GPIO - Register accessors */
tushki7 0:60d829a0353a 1742 #define GPIO_PDOR_REG(base) ((base)->PDOR)
tushki7 0:60d829a0353a 1743 #define GPIO_PSOR_REG(base) ((base)->PSOR)
tushki7 0:60d829a0353a 1744 #define GPIO_PCOR_REG(base) ((base)->PCOR)
tushki7 0:60d829a0353a 1745 #define GPIO_PTOR_REG(base) ((base)->PTOR)
tushki7 0:60d829a0353a 1746 #define GPIO_PDIR_REG(base) ((base)->PDIR)
tushki7 0:60d829a0353a 1747 #define GPIO_PDDR_REG(base) ((base)->PDDR)
tushki7 0:60d829a0353a 1748
tushki7 0:60d829a0353a 1749 /*!
tushki7 0:60d829a0353a 1750 * @}
tushki7 0:60d829a0353a 1751 */ /* end of group GPIO_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1752
tushki7 0:60d829a0353a 1753
tushki7 0:60d829a0353a 1754 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1755 -- GPIO Register Masks
tushki7 0:60d829a0353a 1756 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1757
tushki7 0:60d829a0353a 1758 /*!
tushki7 0:60d829a0353a 1759 * @addtogroup GPIO_Register_Masks GPIO Register Masks
tushki7 0:60d829a0353a 1760 * @{
tushki7 0:60d829a0353a 1761 */
tushki7 0:60d829a0353a 1762
tushki7 0:60d829a0353a 1763 /* PDOR Bit Fields */
tushki7 0:60d829a0353a 1764 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1765 #define GPIO_PDOR_PDO_SHIFT 0
tushki7 0:60d829a0353a 1766 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
tushki7 0:60d829a0353a 1767 /* PSOR Bit Fields */
tushki7 0:60d829a0353a 1768 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1769 #define GPIO_PSOR_PTSO_SHIFT 0
tushki7 0:60d829a0353a 1770 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
tushki7 0:60d829a0353a 1771 /* PCOR Bit Fields */
tushki7 0:60d829a0353a 1772 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1773 #define GPIO_PCOR_PTCO_SHIFT 0
tushki7 0:60d829a0353a 1774 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
tushki7 0:60d829a0353a 1775 /* PTOR Bit Fields */
tushki7 0:60d829a0353a 1776 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1777 #define GPIO_PTOR_PTTO_SHIFT 0
tushki7 0:60d829a0353a 1778 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
tushki7 0:60d829a0353a 1779 /* PDIR Bit Fields */
tushki7 0:60d829a0353a 1780 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1781 #define GPIO_PDIR_PDI_SHIFT 0
tushki7 0:60d829a0353a 1782 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
tushki7 0:60d829a0353a 1783 /* PDDR Bit Fields */
tushki7 0:60d829a0353a 1784 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 1785 #define GPIO_PDDR_PDD_SHIFT 0
tushki7 0:60d829a0353a 1786 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
tushki7 0:60d829a0353a 1787
tushki7 0:60d829a0353a 1788 /*!
tushki7 0:60d829a0353a 1789 * @}
tushki7 0:60d829a0353a 1790 */ /* end of group GPIO_Register_Masks */
tushki7 0:60d829a0353a 1791
tushki7 0:60d829a0353a 1792
tushki7 0:60d829a0353a 1793 /* GPIO - Peripheral instance base addresses */
tushki7 0:60d829a0353a 1794 /** Peripheral GPIOA base address */
tushki7 0:60d829a0353a 1795 #define GPIOA_BASE (0x400FF000u)
tushki7 0:60d829a0353a 1796 /** Peripheral GPIOA base pointer */
tushki7 0:60d829a0353a 1797 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
tushki7 0:60d829a0353a 1798 #define GPIOA_BASE_PTR (GPIOA)
tushki7 0:60d829a0353a 1799 /** Peripheral GPIOB base address */
tushki7 0:60d829a0353a 1800 #define GPIOB_BASE (0x400FF040u)
tushki7 0:60d829a0353a 1801 /** Peripheral GPIOB base pointer */
tushki7 0:60d829a0353a 1802 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
tushki7 0:60d829a0353a 1803 #define GPIOB_BASE_PTR (GPIOB)
tushki7 0:60d829a0353a 1804 /** Peripheral GPIOC base address */
tushki7 0:60d829a0353a 1805 #define GPIOC_BASE (0x400FF080u)
tushki7 0:60d829a0353a 1806 /** Peripheral GPIOC base pointer */
tushki7 0:60d829a0353a 1807 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
tushki7 0:60d829a0353a 1808 #define GPIOC_BASE_PTR (GPIOC)
tushki7 0:60d829a0353a 1809 /** Peripheral GPIOD base address */
tushki7 0:60d829a0353a 1810 #define GPIOD_BASE (0x400FF0C0u)
tushki7 0:60d829a0353a 1811 /** Peripheral GPIOD base pointer */
tushki7 0:60d829a0353a 1812 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
tushki7 0:60d829a0353a 1813 #define GPIOD_BASE_PTR (GPIOD)
tushki7 0:60d829a0353a 1814 /** Peripheral GPIOE base address */
tushki7 0:60d829a0353a 1815 #define GPIOE_BASE (0x400FF100u)
tushki7 0:60d829a0353a 1816 /** Peripheral GPIOE base pointer */
tushki7 0:60d829a0353a 1817 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
tushki7 0:60d829a0353a 1818 #define GPIOE_BASE_PTR (GPIOE)
tushki7 0:60d829a0353a 1819 /** Array initializer of GPIO peripheral base addresses */
tushki7 0:60d829a0353a 1820 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
tushki7 0:60d829a0353a 1821 /** Array initializer of GPIO peripheral base pointers */
tushki7 0:60d829a0353a 1822 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
tushki7 0:60d829a0353a 1823
tushki7 0:60d829a0353a 1824 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1825 -- GPIO - Register accessor macros
tushki7 0:60d829a0353a 1826 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1827
tushki7 0:60d829a0353a 1828 /*!
tushki7 0:60d829a0353a 1829 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
tushki7 0:60d829a0353a 1830 * @{
tushki7 0:60d829a0353a 1831 */
tushki7 0:60d829a0353a 1832
tushki7 0:60d829a0353a 1833
tushki7 0:60d829a0353a 1834 /* GPIO - Register instance definitions */
tushki7 0:60d829a0353a 1835 /* GPIOA */
tushki7 0:60d829a0353a 1836 #define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
tushki7 0:60d829a0353a 1837 #define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
tushki7 0:60d829a0353a 1838 #define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
tushki7 0:60d829a0353a 1839 #define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
tushki7 0:60d829a0353a 1840 #define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
tushki7 0:60d829a0353a 1841 #define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
tushki7 0:60d829a0353a 1842 /* GPIOB */
tushki7 0:60d829a0353a 1843 #define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
tushki7 0:60d829a0353a 1844 #define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
tushki7 0:60d829a0353a 1845 #define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
tushki7 0:60d829a0353a 1846 #define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
tushki7 0:60d829a0353a 1847 #define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
tushki7 0:60d829a0353a 1848 #define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
tushki7 0:60d829a0353a 1849 /* GPIOC */
tushki7 0:60d829a0353a 1850 #define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
tushki7 0:60d829a0353a 1851 #define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
tushki7 0:60d829a0353a 1852 #define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
tushki7 0:60d829a0353a 1853 #define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
tushki7 0:60d829a0353a 1854 #define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
tushki7 0:60d829a0353a 1855 #define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
tushki7 0:60d829a0353a 1856 /* GPIOD */
tushki7 0:60d829a0353a 1857 #define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
tushki7 0:60d829a0353a 1858 #define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
tushki7 0:60d829a0353a 1859 #define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
tushki7 0:60d829a0353a 1860 #define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
tushki7 0:60d829a0353a 1861 #define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
tushki7 0:60d829a0353a 1862 #define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
tushki7 0:60d829a0353a 1863 /* GPIOE */
tushki7 0:60d829a0353a 1864 #define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
tushki7 0:60d829a0353a 1865 #define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
tushki7 0:60d829a0353a 1866 #define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
tushki7 0:60d829a0353a 1867 #define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
tushki7 0:60d829a0353a 1868 #define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
tushki7 0:60d829a0353a 1869 #define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
tushki7 0:60d829a0353a 1870
tushki7 0:60d829a0353a 1871 /*!
tushki7 0:60d829a0353a 1872 * @}
tushki7 0:60d829a0353a 1873 */ /* end of group GPIO_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1874
tushki7 0:60d829a0353a 1875
tushki7 0:60d829a0353a 1876 /*!
tushki7 0:60d829a0353a 1877 * @}
tushki7 0:60d829a0353a 1878 */ /* end of group GPIO_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 1879
tushki7 0:60d829a0353a 1880
tushki7 0:60d829a0353a 1881 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1882 -- I2C Peripheral Access Layer
tushki7 0:60d829a0353a 1883 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1884
tushki7 0:60d829a0353a 1885 /*!
tushki7 0:60d829a0353a 1886 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
tushki7 0:60d829a0353a 1887 * @{
tushki7 0:60d829a0353a 1888 */
tushki7 0:60d829a0353a 1889
tushki7 0:60d829a0353a 1890 /** I2C - Register Layout Typedef */
tushki7 0:60d829a0353a 1891 typedef struct {
tushki7 0:60d829a0353a 1892 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
tushki7 0:60d829a0353a 1893 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
tushki7 0:60d829a0353a 1894 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
tushki7 0:60d829a0353a 1895 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
tushki7 0:60d829a0353a 1896 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
tushki7 0:60d829a0353a 1897 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
tushki7 0:60d829a0353a 1898 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
tushki7 0:60d829a0353a 1899 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
tushki7 0:60d829a0353a 1900 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
tushki7 0:60d829a0353a 1901 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
tushki7 0:60d829a0353a 1902 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
tushki7 0:60d829a0353a 1903 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
tushki7 0:60d829a0353a 1904 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
tushki7 0:60d829a0353a 1905 } I2C_Type, *I2C_MemMapPtr;
tushki7 0:60d829a0353a 1906
tushki7 0:60d829a0353a 1907 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1908 -- I2C - Register accessor macros
tushki7 0:60d829a0353a 1909 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1910
tushki7 0:60d829a0353a 1911 /*!
tushki7 0:60d829a0353a 1912 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
tushki7 0:60d829a0353a 1913 * @{
tushki7 0:60d829a0353a 1914 */
tushki7 0:60d829a0353a 1915
tushki7 0:60d829a0353a 1916
tushki7 0:60d829a0353a 1917 /* I2C - Register accessors */
tushki7 0:60d829a0353a 1918 #define I2C_A1_REG(base) ((base)->A1)
tushki7 0:60d829a0353a 1919 #define I2C_F_REG(base) ((base)->F)
tushki7 0:60d829a0353a 1920 #define I2C_C1_REG(base) ((base)->C1)
tushki7 0:60d829a0353a 1921 #define I2C_S_REG(base) ((base)->S)
tushki7 0:60d829a0353a 1922 #define I2C_D_REG(base) ((base)->D)
tushki7 0:60d829a0353a 1923 #define I2C_C2_REG(base) ((base)->C2)
tushki7 0:60d829a0353a 1924 #define I2C_FLT_REG(base) ((base)->FLT)
tushki7 0:60d829a0353a 1925 #define I2C_RA_REG(base) ((base)->RA)
tushki7 0:60d829a0353a 1926 #define I2C_SMB_REG(base) ((base)->SMB)
tushki7 0:60d829a0353a 1927 #define I2C_A2_REG(base) ((base)->A2)
tushki7 0:60d829a0353a 1928 #define I2C_SLTH_REG(base) ((base)->SLTH)
tushki7 0:60d829a0353a 1929 #define I2C_SLTL_REG(base) ((base)->SLTL)
tushki7 0:60d829a0353a 1930 #define I2C_S2_REG(base) ((base)->S2)
tushki7 0:60d829a0353a 1931
tushki7 0:60d829a0353a 1932 /*!
tushki7 0:60d829a0353a 1933 * @}
tushki7 0:60d829a0353a 1934 */ /* end of group I2C_Register_Accessor_Macros */
tushki7 0:60d829a0353a 1935
tushki7 0:60d829a0353a 1936
tushki7 0:60d829a0353a 1937 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 1938 -- I2C Register Masks
tushki7 0:60d829a0353a 1939 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 1940
tushki7 0:60d829a0353a 1941 /*!
tushki7 0:60d829a0353a 1942 * @addtogroup I2C_Register_Masks I2C Register Masks
tushki7 0:60d829a0353a 1943 * @{
tushki7 0:60d829a0353a 1944 */
tushki7 0:60d829a0353a 1945
tushki7 0:60d829a0353a 1946 /* A1 Bit Fields */
tushki7 0:60d829a0353a 1947 #define I2C_A1_AD_MASK 0xFEu
tushki7 0:60d829a0353a 1948 #define I2C_A1_AD_SHIFT 1
tushki7 0:60d829a0353a 1949 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
tushki7 0:60d829a0353a 1950 /* F Bit Fields */
tushki7 0:60d829a0353a 1951 #define I2C_F_ICR_MASK 0x3Fu
tushki7 0:60d829a0353a 1952 #define I2C_F_ICR_SHIFT 0
tushki7 0:60d829a0353a 1953 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
tushki7 0:60d829a0353a 1954 #define I2C_F_MULT_MASK 0xC0u
tushki7 0:60d829a0353a 1955 #define I2C_F_MULT_SHIFT 6
tushki7 0:60d829a0353a 1956 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
tushki7 0:60d829a0353a 1957 /* C1 Bit Fields */
tushki7 0:60d829a0353a 1958 #define I2C_C1_DMAEN_MASK 0x1u
tushki7 0:60d829a0353a 1959 #define I2C_C1_DMAEN_SHIFT 0
tushki7 0:60d829a0353a 1960 #define I2C_C1_WUEN_MASK 0x2u
tushki7 0:60d829a0353a 1961 #define I2C_C1_WUEN_SHIFT 1
tushki7 0:60d829a0353a 1962 #define I2C_C1_RSTA_MASK 0x4u
tushki7 0:60d829a0353a 1963 #define I2C_C1_RSTA_SHIFT 2
tushki7 0:60d829a0353a 1964 #define I2C_C1_TXAK_MASK 0x8u
tushki7 0:60d829a0353a 1965 #define I2C_C1_TXAK_SHIFT 3
tushki7 0:60d829a0353a 1966 #define I2C_C1_TX_MASK 0x10u
tushki7 0:60d829a0353a 1967 #define I2C_C1_TX_SHIFT 4
tushki7 0:60d829a0353a 1968 #define I2C_C1_MST_MASK 0x20u
tushki7 0:60d829a0353a 1969 #define I2C_C1_MST_SHIFT 5
tushki7 0:60d829a0353a 1970 #define I2C_C1_IICIE_MASK 0x40u
tushki7 0:60d829a0353a 1971 #define I2C_C1_IICIE_SHIFT 6
tushki7 0:60d829a0353a 1972 #define I2C_C1_IICEN_MASK 0x80u
tushki7 0:60d829a0353a 1973 #define I2C_C1_IICEN_SHIFT 7
tushki7 0:60d829a0353a 1974 /* S Bit Fields */
tushki7 0:60d829a0353a 1975 #define I2C_S_RXAK_MASK 0x1u
tushki7 0:60d829a0353a 1976 #define I2C_S_RXAK_SHIFT 0
tushki7 0:60d829a0353a 1977 #define I2C_S_IICIF_MASK 0x2u
tushki7 0:60d829a0353a 1978 #define I2C_S_IICIF_SHIFT 1
tushki7 0:60d829a0353a 1979 #define I2C_S_SRW_MASK 0x4u
tushki7 0:60d829a0353a 1980 #define I2C_S_SRW_SHIFT 2
tushki7 0:60d829a0353a 1981 #define I2C_S_RAM_MASK 0x8u
tushki7 0:60d829a0353a 1982 #define I2C_S_RAM_SHIFT 3
tushki7 0:60d829a0353a 1983 #define I2C_S_ARBL_MASK 0x10u
tushki7 0:60d829a0353a 1984 #define I2C_S_ARBL_SHIFT 4
tushki7 0:60d829a0353a 1985 #define I2C_S_BUSY_MASK 0x20u
tushki7 0:60d829a0353a 1986 #define I2C_S_BUSY_SHIFT 5
tushki7 0:60d829a0353a 1987 #define I2C_S_IAAS_MASK 0x40u
tushki7 0:60d829a0353a 1988 #define I2C_S_IAAS_SHIFT 6
tushki7 0:60d829a0353a 1989 #define I2C_S_TCF_MASK 0x80u
tushki7 0:60d829a0353a 1990 #define I2C_S_TCF_SHIFT 7
tushki7 0:60d829a0353a 1991 /* D Bit Fields */
tushki7 0:60d829a0353a 1992 #define I2C_D_DATA_MASK 0xFFu
tushki7 0:60d829a0353a 1993 #define I2C_D_DATA_SHIFT 0
tushki7 0:60d829a0353a 1994 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
tushki7 0:60d829a0353a 1995 /* C2 Bit Fields */
tushki7 0:60d829a0353a 1996 #define I2C_C2_AD_MASK 0x7u
tushki7 0:60d829a0353a 1997 #define I2C_C2_AD_SHIFT 0
tushki7 0:60d829a0353a 1998 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
tushki7 0:60d829a0353a 1999 #define I2C_C2_RMEN_MASK 0x8u
tushki7 0:60d829a0353a 2000 #define I2C_C2_RMEN_SHIFT 3
tushki7 0:60d829a0353a 2001 #define I2C_C2_SBRC_MASK 0x10u
tushki7 0:60d829a0353a 2002 #define I2C_C2_SBRC_SHIFT 4
tushki7 0:60d829a0353a 2003 #define I2C_C2_HDRS_MASK 0x20u
tushki7 0:60d829a0353a 2004 #define I2C_C2_HDRS_SHIFT 5
tushki7 0:60d829a0353a 2005 #define I2C_C2_ADEXT_MASK 0x40u
tushki7 0:60d829a0353a 2006 #define I2C_C2_ADEXT_SHIFT 6
tushki7 0:60d829a0353a 2007 #define I2C_C2_GCAEN_MASK 0x80u
tushki7 0:60d829a0353a 2008 #define I2C_C2_GCAEN_SHIFT 7
tushki7 0:60d829a0353a 2009 /* FLT Bit Fields */
tushki7 0:60d829a0353a 2010 #define I2C_FLT_FLT_MASK 0xFu
tushki7 0:60d829a0353a 2011 #define I2C_FLT_FLT_SHIFT 0
tushki7 0:60d829a0353a 2012 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
tushki7 0:60d829a0353a 2013 #define I2C_FLT_STARTF_MASK 0x10u
tushki7 0:60d829a0353a 2014 #define I2C_FLT_STARTF_SHIFT 4
tushki7 0:60d829a0353a 2015 #define I2C_FLT_SSIE_MASK 0x20u
tushki7 0:60d829a0353a 2016 #define I2C_FLT_SSIE_SHIFT 5
tushki7 0:60d829a0353a 2017 #define I2C_FLT_STOPF_MASK 0x40u
tushki7 0:60d829a0353a 2018 #define I2C_FLT_STOPF_SHIFT 6
tushki7 0:60d829a0353a 2019 #define I2C_FLT_SHEN_MASK 0x80u
tushki7 0:60d829a0353a 2020 #define I2C_FLT_SHEN_SHIFT 7
tushki7 0:60d829a0353a 2021 /* RA Bit Fields */
tushki7 0:60d829a0353a 2022 #define I2C_RA_RAD_MASK 0xFEu
tushki7 0:60d829a0353a 2023 #define I2C_RA_RAD_SHIFT 1
tushki7 0:60d829a0353a 2024 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
tushki7 0:60d829a0353a 2025 /* SMB Bit Fields */
tushki7 0:60d829a0353a 2026 #define I2C_SMB_SHTF2IE_MASK 0x1u
tushki7 0:60d829a0353a 2027 #define I2C_SMB_SHTF2IE_SHIFT 0
tushki7 0:60d829a0353a 2028 #define I2C_SMB_SHTF2_MASK 0x2u
tushki7 0:60d829a0353a 2029 #define I2C_SMB_SHTF2_SHIFT 1
tushki7 0:60d829a0353a 2030 #define I2C_SMB_SHTF1_MASK 0x4u
tushki7 0:60d829a0353a 2031 #define I2C_SMB_SHTF1_SHIFT 2
tushki7 0:60d829a0353a 2032 #define I2C_SMB_SLTF_MASK 0x8u
tushki7 0:60d829a0353a 2033 #define I2C_SMB_SLTF_SHIFT 3
tushki7 0:60d829a0353a 2034 #define I2C_SMB_TCKSEL_MASK 0x10u
tushki7 0:60d829a0353a 2035 #define I2C_SMB_TCKSEL_SHIFT 4
tushki7 0:60d829a0353a 2036 #define I2C_SMB_SIICAEN_MASK 0x20u
tushki7 0:60d829a0353a 2037 #define I2C_SMB_SIICAEN_SHIFT 5
tushki7 0:60d829a0353a 2038 #define I2C_SMB_ALERTEN_MASK 0x40u
tushki7 0:60d829a0353a 2039 #define I2C_SMB_ALERTEN_SHIFT 6
tushki7 0:60d829a0353a 2040 #define I2C_SMB_FACK_MASK 0x80u
tushki7 0:60d829a0353a 2041 #define I2C_SMB_FACK_SHIFT 7
tushki7 0:60d829a0353a 2042 /* A2 Bit Fields */
tushki7 0:60d829a0353a 2043 #define I2C_A2_SAD_MASK 0xFEu
tushki7 0:60d829a0353a 2044 #define I2C_A2_SAD_SHIFT 1
tushki7 0:60d829a0353a 2045 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
tushki7 0:60d829a0353a 2046 /* SLTH Bit Fields */
tushki7 0:60d829a0353a 2047 #define I2C_SLTH_SSLT_MASK 0xFFu
tushki7 0:60d829a0353a 2048 #define I2C_SLTH_SSLT_SHIFT 0
tushki7 0:60d829a0353a 2049 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
tushki7 0:60d829a0353a 2050 /* SLTL Bit Fields */
tushki7 0:60d829a0353a 2051 #define I2C_SLTL_SSLT_MASK 0xFFu
tushki7 0:60d829a0353a 2052 #define I2C_SLTL_SSLT_SHIFT 0
tushki7 0:60d829a0353a 2053 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
tushki7 0:60d829a0353a 2054 /* S2 Bit Fields */
tushki7 0:60d829a0353a 2055 #define I2C_S2_EMPTY_MASK 0x1u
tushki7 0:60d829a0353a 2056 #define I2C_S2_EMPTY_SHIFT 0
tushki7 0:60d829a0353a 2057 #define I2C_S2_ERROR_MASK 0x2u
tushki7 0:60d829a0353a 2058 #define I2C_S2_ERROR_SHIFT 1
tushki7 0:60d829a0353a 2059
tushki7 0:60d829a0353a 2060 /*!
tushki7 0:60d829a0353a 2061 * @}
tushki7 0:60d829a0353a 2062 */ /* end of group I2C_Register_Masks */
tushki7 0:60d829a0353a 2063
tushki7 0:60d829a0353a 2064
tushki7 0:60d829a0353a 2065 /* I2C - Peripheral instance base addresses */
tushki7 0:60d829a0353a 2066 /** Peripheral I2C0 base address */
tushki7 0:60d829a0353a 2067 #define I2C0_BASE (0x40066000u)
tushki7 0:60d829a0353a 2068 /** Peripheral I2C0 base pointer */
tushki7 0:60d829a0353a 2069 #define I2C0 ((I2C_Type *)I2C0_BASE)
tushki7 0:60d829a0353a 2070 #define I2C0_BASE_PTR (I2C0)
tushki7 0:60d829a0353a 2071 /** Peripheral I2C1 base address */
tushki7 0:60d829a0353a 2072 #define I2C1_BASE (0x40067000u)
tushki7 0:60d829a0353a 2073 /** Peripheral I2C1 base pointer */
tushki7 0:60d829a0353a 2074 #define I2C1 ((I2C_Type *)I2C1_BASE)
tushki7 0:60d829a0353a 2075 #define I2C1_BASE_PTR (I2C1)
tushki7 0:60d829a0353a 2076 /** Array initializer of I2C peripheral base addresses */
tushki7 0:60d829a0353a 2077 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
tushki7 0:60d829a0353a 2078 /** Array initializer of I2C peripheral base pointers */
tushki7 0:60d829a0353a 2079 #define I2C_BASE_PTRS { I2C0, I2C1 }
tushki7 0:60d829a0353a 2080 /** Interrupt vectors for the I2C peripheral type */
tushki7 0:60d829a0353a 2081 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
tushki7 0:60d829a0353a 2082
tushki7 0:60d829a0353a 2083 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 2084 -- I2C - Register accessor macros
tushki7 0:60d829a0353a 2085 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 2086
tushki7 0:60d829a0353a 2087 /*!
tushki7 0:60d829a0353a 2088 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
tushki7 0:60d829a0353a 2089 * @{
tushki7 0:60d829a0353a 2090 */
tushki7 0:60d829a0353a 2091
tushki7 0:60d829a0353a 2092
tushki7 0:60d829a0353a 2093 /* I2C - Register instance definitions */
tushki7 0:60d829a0353a 2094 /* I2C0 */
tushki7 0:60d829a0353a 2095 #define I2C0_A1 I2C_A1_REG(I2C0)
tushki7 0:60d829a0353a 2096 #define I2C0_F I2C_F_REG(I2C0)
tushki7 0:60d829a0353a 2097 #define I2C0_C1 I2C_C1_REG(I2C0)
tushki7 0:60d829a0353a 2098 #define I2C0_S I2C_S_REG(I2C0)
tushki7 0:60d829a0353a 2099 #define I2C0_D I2C_D_REG(I2C0)
tushki7 0:60d829a0353a 2100 #define I2C0_C2 I2C_C2_REG(I2C0)
tushki7 0:60d829a0353a 2101 #define I2C0_FLT I2C_FLT_REG(I2C0)
tushki7 0:60d829a0353a 2102 #define I2C0_RA I2C_RA_REG(I2C0)
tushki7 0:60d829a0353a 2103 #define I2C0_SMB I2C_SMB_REG(I2C0)
tushki7 0:60d829a0353a 2104 #define I2C0_A2 I2C_A2_REG(I2C0)
tushki7 0:60d829a0353a 2105 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
tushki7 0:60d829a0353a 2106 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
tushki7 0:60d829a0353a 2107 #define I2C0_S2 I2C_S2_REG(I2C0)
tushki7 0:60d829a0353a 2108 /* I2C1 */
tushki7 0:60d829a0353a 2109 #define I2C1_A1 I2C_A1_REG(I2C1)
tushki7 0:60d829a0353a 2110 #define I2C1_F I2C_F_REG(I2C1)
tushki7 0:60d829a0353a 2111 #define I2C1_C1 I2C_C1_REG(I2C1)
tushki7 0:60d829a0353a 2112 #define I2C1_S I2C_S_REG(I2C1)
tushki7 0:60d829a0353a 2113 #define I2C1_D I2C_D_REG(I2C1)
tushki7 0:60d829a0353a 2114 #define I2C1_C2 I2C_C2_REG(I2C1)
tushki7 0:60d829a0353a 2115 #define I2C1_FLT I2C_FLT_REG(I2C1)
tushki7 0:60d829a0353a 2116 #define I2C1_RA I2C_RA_REG(I2C1)
tushki7 0:60d829a0353a 2117 #define I2C1_SMB I2C_SMB_REG(I2C1)
tushki7 0:60d829a0353a 2118 #define I2C1_A2 I2C_A2_REG(I2C1)
tushki7 0:60d829a0353a 2119 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
tushki7 0:60d829a0353a 2120 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
tushki7 0:60d829a0353a 2121 #define I2C1_S2 I2C_S2_REG(I2C1)
tushki7 0:60d829a0353a 2122
tushki7 0:60d829a0353a 2123 /*!
tushki7 0:60d829a0353a 2124 * @}
tushki7 0:60d829a0353a 2125 */ /* end of group I2C_Register_Accessor_Macros */
tushki7 0:60d829a0353a 2126
tushki7 0:60d829a0353a 2127
tushki7 0:60d829a0353a 2128 /*!
tushki7 0:60d829a0353a 2129 * @}
tushki7 0:60d829a0353a 2130 */ /* end of group I2C_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 2131
tushki7 0:60d829a0353a 2132
tushki7 0:60d829a0353a 2133 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 2134 -- I2S Peripheral Access Layer
tushki7 0:60d829a0353a 2135 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 2136
tushki7 0:60d829a0353a 2137 /*!
tushki7 0:60d829a0353a 2138 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
tushki7 0:60d829a0353a 2139 * @{
tushki7 0:60d829a0353a 2140 */
tushki7 0:60d829a0353a 2141
tushki7 0:60d829a0353a 2142 /** I2S - Register Layout Typedef */
tushki7 0:60d829a0353a 2143 typedef struct {
tushki7 0:60d829a0353a 2144 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
tushki7 0:60d829a0353a 2145 uint8_t RESERVED_0[4];
tushki7 0:60d829a0353a 2146 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
tushki7 0:60d829a0353a 2147 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
tushki7 0:60d829a0353a 2148 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
tushki7 0:60d829a0353a 2149 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
tushki7 0:60d829a0353a 2150 uint8_t RESERVED_1[8];
tushki7 0:60d829a0353a 2151 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
tushki7 0:60d829a0353a 2152 uint8_t RESERVED_2[60];
tushki7 0:60d829a0353a 2153 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
tushki7 0:60d829a0353a 2154 uint8_t RESERVED_3[28];
tushki7 0:60d829a0353a 2155 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
tushki7 0:60d829a0353a 2156 uint8_t RESERVED_4[4];
tushki7 0:60d829a0353a 2157 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
tushki7 0:60d829a0353a 2158 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
tushki7 0:60d829a0353a 2159 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
tushki7 0:60d829a0353a 2160 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
tushki7 0:60d829a0353a 2161 uint8_t RESERVED_5[8];
tushki7 0:60d829a0353a 2162 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
tushki7 0:60d829a0353a 2163 uint8_t RESERVED_6[60];
tushki7 0:60d829a0353a 2164 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
tushki7 0:60d829a0353a 2165 uint8_t RESERVED_7[28];
tushki7 0:60d829a0353a 2166 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
tushki7 0:60d829a0353a 2167 } I2S_Type, *I2S_MemMapPtr;
tushki7 0:60d829a0353a 2168
tushki7 0:60d829a0353a 2169 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 2170 -- I2S - Register accessor macros
tushki7 0:60d829a0353a 2171 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 2172
tushki7 0:60d829a0353a 2173 /*!
tushki7 0:60d829a0353a 2174 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
tushki7 0:60d829a0353a 2175 * @{
tushki7 0:60d829a0353a 2176 */
tushki7 0:60d829a0353a 2177
tushki7 0:60d829a0353a 2178
tushki7 0:60d829a0353a 2179 /* I2S - Register accessors */
tushki7 0:60d829a0353a 2180 #define I2S_TCSR_REG(base) ((base)->TCSR)
tushki7 0:60d829a0353a 2181 #define I2S_TCR2_REG(base) ((base)->TCR2)
tushki7 0:60d829a0353a 2182 #define I2S_TCR3_REG(base) ((base)->TCR3)
tushki7 0:60d829a0353a 2183 #define I2S_TCR4_REG(base) ((base)->TCR4)
tushki7 0:60d829a0353a 2184 #define I2S_TCR5_REG(base) ((base)->TCR5)
tushki7 0:60d829a0353a 2185 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
tushki7 0:60d829a0353a 2186 #define I2S_TMR_REG(base) ((base)->TMR)
tushki7 0:60d829a0353a 2187 #define I2S_RCSR_REG(base) ((base)->RCSR)
tushki7 0:60d829a0353a 2188 #define I2S_RCR2_REG(base) ((base)->RCR2)
tushki7 0:60d829a0353a 2189 #define I2S_RCR3_REG(base) ((base)->RCR3)
tushki7 0:60d829a0353a 2190 #define I2S_RCR4_REG(base) ((base)->RCR4)
tushki7 0:60d829a0353a 2191 #define I2S_RCR5_REG(base) ((base)->RCR5)
tushki7 0:60d829a0353a 2192 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
tushki7 0:60d829a0353a 2193 #define I2S_RMR_REG(base) ((base)->RMR)
tushki7 0:60d829a0353a 2194 #define I2S_MCR_REG(base) ((base)->MCR)
tushki7 0:60d829a0353a 2195
tushki7 0:60d829a0353a 2196 /*!
tushki7 0:60d829a0353a 2197 * @}
tushki7 0:60d829a0353a 2198 */ /* end of group I2S_Register_Accessor_Macros */
tushki7 0:60d829a0353a 2199
tushki7 0:60d829a0353a 2200
tushki7 0:60d829a0353a 2201 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 2202 -- I2S Register Masks
tushki7 0:60d829a0353a 2203 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 2204
tushki7 0:60d829a0353a 2205 /*!
tushki7 0:60d829a0353a 2206 * @addtogroup I2S_Register_Masks I2S Register Masks
tushki7 0:60d829a0353a 2207 * @{
tushki7 0:60d829a0353a 2208 */
tushki7 0:60d829a0353a 2209
tushki7 0:60d829a0353a 2210 /* TCSR Bit Fields */
tushki7 0:60d829a0353a 2211 #define I2S_TCSR_FWDE_MASK 0x2u
tushki7 0:60d829a0353a 2212 #define I2S_TCSR_FWDE_SHIFT 1
tushki7 0:60d829a0353a 2213 #define I2S_TCSR_FWIE_MASK 0x200u
tushki7 0:60d829a0353a 2214 #define I2S_TCSR_FWIE_SHIFT 9
tushki7 0:60d829a0353a 2215 #define I2S_TCSR_FEIE_MASK 0x400u
tushki7 0:60d829a0353a 2216 #define I2S_TCSR_FEIE_SHIFT 10
tushki7 0:60d829a0353a 2217 #define I2S_TCSR_SEIE_MASK 0x800u
tushki7 0:60d829a0353a 2218 #define I2S_TCSR_SEIE_SHIFT 11
tushki7 0:60d829a0353a 2219 #define I2S_TCSR_WSIE_MASK 0x1000u
tushki7 0:60d829a0353a 2220 #define I2S_TCSR_WSIE_SHIFT 12
tushki7 0:60d829a0353a 2221 #define I2S_TCSR_FWF_MASK 0x20000u
tushki7 0:60d829a0353a 2222 #define I2S_TCSR_FWF_SHIFT 17
tushki7 0:60d829a0353a 2223 #define I2S_TCSR_FEF_MASK 0x40000u
tushki7 0:60d829a0353a 2224 #define I2S_TCSR_FEF_SHIFT 18
tushki7 0:60d829a0353a 2225 #define I2S_TCSR_SEF_MASK 0x80000u
tushki7 0:60d829a0353a 2226 #define I2S_TCSR_SEF_SHIFT 19
tushki7 0:60d829a0353a 2227 #define I2S_TCSR_WSF_MASK 0x100000u
tushki7 0:60d829a0353a 2228 #define I2S_TCSR_WSF_SHIFT 20
tushki7 0:60d829a0353a 2229 #define I2S_TCSR_SR_MASK 0x1000000u
tushki7 0:60d829a0353a 2230 #define I2S_TCSR_SR_SHIFT 24
tushki7 0:60d829a0353a 2231 #define I2S_TCSR_FR_MASK 0x2000000u
tushki7 0:60d829a0353a 2232 #define I2S_TCSR_FR_SHIFT 25
tushki7 0:60d829a0353a 2233 #define I2S_TCSR_BCE_MASK 0x10000000u
tushki7 0:60d829a0353a 2234 #define I2S_TCSR_BCE_SHIFT 28
tushki7 0:60d829a0353a 2235 #define I2S_TCSR_DBGE_MASK 0x20000000u
tushki7 0:60d829a0353a 2236 #define I2S_TCSR_DBGE_SHIFT 29
tushki7 0:60d829a0353a 2237 #define I2S_TCSR_STOPE_MASK 0x40000000u
tushki7 0:60d829a0353a 2238 #define I2S_TCSR_STOPE_SHIFT 30
tushki7 0:60d829a0353a 2239 #define I2S_TCSR_TE_MASK 0x80000000u
tushki7 0:60d829a0353a 2240 #define I2S_TCSR_TE_SHIFT 31
tushki7 0:60d829a0353a 2241 /* TCR2 Bit Fields */
tushki7 0:60d829a0353a 2242 #define I2S_TCR2_DIV_MASK 0xFFu
tushki7 0:60d829a0353a 2243 #define I2S_TCR2_DIV_SHIFT 0
tushki7 0:60d829a0353a 2244 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
tushki7 0:60d829a0353a 2245 #define I2S_TCR2_BCD_MASK 0x1000000u
tushki7 0:60d829a0353a 2246 #define I2S_TCR2_BCD_SHIFT 24
tushki7 0:60d829a0353a 2247 #define I2S_TCR2_BCP_MASK 0x2000000u
tushki7 0:60d829a0353a 2248 #define I2S_TCR2_BCP_SHIFT 25
tushki7 0:60d829a0353a 2249 #define I2S_TCR2_MSEL_MASK 0xC000000u
tushki7 0:60d829a0353a 2250 #define I2S_TCR2_MSEL_SHIFT 26
tushki7 0:60d829a0353a 2251 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
tushki7 0:60d829a0353a 2252 #define I2S_TCR2_BCI_MASK 0x10000000u
tushki7 0:60d829a0353a 2253 #define I2S_TCR2_BCI_SHIFT 28
tushki7 0:60d829a0353a 2254 #define I2S_TCR2_BCS_MASK 0x20000000u
tushki7 0:60d829a0353a 2255 #define I2S_TCR2_BCS_SHIFT 29
tushki7 0:60d829a0353a 2256 #define I2S_TCR2_SYNC_MASK 0xC0000000u
tushki7 0:60d829a0353a 2257 #define I2S_TCR2_SYNC_SHIFT 30
tushki7 0:60d829a0353a 2258 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
tushki7 0:60d829a0353a 2259 /* TCR3 Bit Fields */
tushki7 0:60d829a0353a 2260 #define I2S_TCR3_WDFL_MASK 0x1u
tushki7 0:60d829a0353a 2261 #define I2S_TCR3_WDFL_SHIFT 0
tushki7 0:60d829a0353a 2262 #define I2S_TCR3_TCE_MASK 0x10000u
tushki7 0:60d829a0353a 2263 #define I2S_TCR3_TCE_SHIFT 16
tushki7 0:60d829a0353a 2264 /* TCR4 Bit Fields */
tushki7 0:60d829a0353a 2265 #define I2S_TCR4_FSD_MASK 0x1u
tushki7 0:60d829a0353a 2266 #define I2S_TCR4_FSD_SHIFT 0
tushki7 0:60d829a0353a 2267 #define I2S_TCR4_FSP_MASK 0x2u
tushki7 0:60d829a0353a 2268 #define I2S_TCR4_FSP_SHIFT 1
tushki7 0:60d829a0353a 2269 #define I2S_TCR4_ONDEM_MASK 0x4u
tushki7 0:60d829a0353a 2270 #define I2S_TCR4_ONDEM_SHIFT 2
tushki7 0:60d829a0353a 2271 #define I2S_TCR4_FSE_MASK 0x8u
tushki7 0:60d829a0353a 2272 #define I2S_TCR4_FSE_SHIFT 3
tushki7 0:60d829a0353a 2273 #define I2S_TCR4_MF_MASK 0x10u
tushki7 0:60d829a0353a 2274 #define I2S_TCR4_MF_SHIFT 4
tushki7 0:60d829a0353a 2275 #define I2S_TCR4_SYWD_MASK 0x1F00u
tushki7 0:60d829a0353a 2276 #define I2S_TCR4_SYWD_SHIFT 8
tushki7 0:60d829a0353a 2277 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
tushki7 0:60d829a0353a 2278 #define I2S_TCR4_FRSZ_MASK 0x10000u
tushki7 0:60d829a0353a 2279 #define I2S_TCR4_FRSZ_SHIFT 16
tushki7 0:60d829a0353a 2280 #define I2S_TCR4_FPACK_MASK 0x3000000u
tushki7 0:60d829a0353a 2281 #define I2S_TCR4_FPACK_SHIFT 24
tushki7 0:60d829a0353a 2282 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
tushki7 0:60d829a0353a 2283 #define I2S_TCR4_FCONT_MASK 0x10000000u
tushki7 0:60d829a0353a 2284 #define I2S_TCR4_FCONT_SHIFT 28
tushki7 0:60d829a0353a 2285 /* TCR5 Bit Fields */
tushki7 0:60d829a0353a 2286 #define I2S_TCR5_FBT_MASK 0x1F00u
tushki7 0:60d829a0353a 2287 #define I2S_TCR5_FBT_SHIFT 8
tushki7 0:60d829a0353a 2288 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
tushki7 0:60d829a0353a 2289 #define I2S_TCR5_W0W_MASK 0x1F0000u
tushki7 0:60d829a0353a 2290 #define I2S_TCR5_W0W_SHIFT 16
tushki7 0:60d829a0353a 2291 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
tushki7 0:60d829a0353a 2292 #define I2S_TCR5_WNW_MASK 0x1F000000u
tushki7 0:60d829a0353a 2293 #define I2S_TCR5_WNW_SHIFT 24
tushki7 0:60d829a0353a 2294 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
tushki7 0:60d829a0353a 2295 /* TDR Bit Fields */
tushki7 0:60d829a0353a 2296 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 2297 #define I2S_TDR_TDR_SHIFT 0
tushki7 0:60d829a0353a 2298 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
tushki7 0:60d829a0353a 2299 /* TMR Bit Fields */
tushki7 0:60d829a0353a 2300 #define I2S_TMR_TWM_MASK 0x3u
tushki7 0:60d829a0353a 2301 #define I2S_TMR_TWM_SHIFT 0
tushki7 0:60d829a0353a 2302 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
tushki7 0:60d829a0353a 2303 /* RCSR Bit Fields */
tushki7 0:60d829a0353a 2304 #define I2S_RCSR_FWDE_MASK 0x2u
tushki7 0:60d829a0353a 2305 #define I2S_RCSR_FWDE_SHIFT 1
tushki7 0:60d829a0353a 2306 #define I2S_RCSR_FWIE_MASK 0x200u
tushki7 0:60d829a0353a 2307 #define I2S_RCSR_FWIE_SHIFT 9
tushki7 0:60d829a0353a 2308 #define I2S_RCSR_FEIE_MASK 0x400u
tushki7 0:60d829a0353a 2309 #define I2S_RCSR_FEIE_SHIFT 10
tushki7 0:60d829a0353a 2310 #define I2S_RCSR_SEIE_MASK 0x800u
tushki7 0:60d829a0353a 2311 #define I2S_RCSR_SEIE_SHIFT 11
tushki7 0:60d829a0353a 2312 #define I2S_RCSR_WSIE_MASK 0x1000u
tushki7 0:60d829a0353a 2313 #define I2S_RCSR_WSIE_SHIFT 12
tushki7 0:60d829a0353a 2314 #define I2S_RCSR_FWF_MASK 0x20000u
tushki7 0:60d829a0353a 2315 #define I2S_RCSR_FWF_SHIFT 17
tushki7 0:60d829a0353a 2316 #define I2S_RCSR_FEF_MASK 0x40000u
tushki7 0:60d829a0353a 2317 #define I2S_RCSR_FEF_SHIFT 18
tushki7 0:60d829a0353a 2318 #define I2S_RCSR_SEF_MASK 0x80000u
tushki7 0:60d829a0353a 2319 #define I2S_RCSR_SEF_SHIFT 19
tushki7 0:60d829a0353a 2320 #define I2S_RCSR_WSF_MASK 0x100000u
tushki7 0:60d829a0353a 2321 #define I2S_RCSR_WSF_SHIFT 20
tushki7 0:60d829a0353a 2322 #define I2S_RCSR_SR_MASK 0x1000000u
tushki7 0:60d829a0353a 2323 #define I2S_RCSR_SR_SHIFT 24
tushki7 0:60d829a0353a 2324 #define I2S_RCSR_FR_MASK 0x2000000u
tushki7 0:60d829a0353a 2325 #define I2S_RCSR_FR_SHIFT 25
tushki7 0:60d829a0353a 2326 #define I2S_RCSR_BCE_MASK 0x10000000u
tushki7 0:60d829a0353a 2327 #define I2S_RCSR_BCE_SHIFT 28
tushki7 0:60d829a0353a 2328 #define I2S_RCSR_DBGE_MASK 0x20000000u
tushki7 0:60d829a0353a 2329 #define I2S_RCSR_DBGE_SHIFT 29
tushki7 0:60d829a0353a 2330 #define I2S_RCSR_STOPE_MASK 0x40000000u
tushki7 0:60d829a0353a 2331 #define I2S_RCSR_STOPE_SHIFT 30
tushki7 0:60d829a0353a 2332 #define I2S_RCSR_RE_MASK 0x80000000u
tushki7 0:60d829a0353a 2333 #define I2S_RCSR_RE_SHIFT 31
tushki7 0:60d829a0353a 2334 /* RCR2 Bit Fields */
tushki7 0:60d829a0353a 2335 #define I2S_RCR2_DIV_MASK 0xFFu
tushki7 0:60d829a0353a 2336 #define I2S_RCR2_DIV_SHIFT 0
tushki7 0:60d829a0353a 2337 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
tushki7 0:60d829a0353a 2338 #define I2S_RCR2_BCD_MASK 0x1000000u
tushki7 0:60d829a0353a 2339 #define I2S_RCR2_BCD_SHIFT 24
tushki7 0:60d829a0353a 2340 #define I2S_RCR2_BCP_MASK 0x2000000u
tushki7 0:60d829a0353a 2341 #define I2S_RCR2_BCP_SHIFT 25
tushki7 0:60d829a0353a 2342 #define I2S_RCR2_MSEL_MASK 0xC000000u
tushki7 0:60d829a0353a 2343 #define I2S_RCR2_MSEL_SHIFT 26
tushki7 0:60d829a0353a 2344 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
tushki7 0:60d829a0353a 2345 #define I2S_RCR2_BCI_MASK 0x10000000u
tushki7 0:60d829a0353a 2346 #define I2S_RCR2_BCI_SHIFT 28
tushki7 0:60d829a0353a 2347 #define I2S_RCR2_BCS_MASK 0x20000000u
tushki7 0:60d829a0353a 2348 #define I2S_RCR2_BCS_SHIFT 29
tushki7 0:60d829a0353a 2349 #define I2S_RCR2_SYNC_MASK 0xC0000000u
tushki7 0:60d829a0353a 2350 #define I2S_RCR2_SYNC_SHIFT 30
tushki7 0:60d829a0353a 2351 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
tushki7 0:60d829a0353a 2352 /* RCR3 Bit Fields */
tushki7 0:60d829a0353a 2353 #define I2S_RCR3_WDFL_MASK 0x1u
tushki7 0:60d829a0353a 2354 #define I2S_RCR3_WDFL_SHIFT 0
tushki7 0:60d829a0353a 2355 #define I2S_RCR3_RCE_MASK 0x10000u
tushki7 0:60d829a0353a 2356 #define I2S_RCR3_RCE_SHIFT 16
tushki7 0:60d829a0353a 2357 /* RCR4 Bit Fields */
tushki7 0:60d829a0353a 2358 #define I2S_RCR4_FSD_MASK 0x1u
tushki7 0:60d829a0353a 2359 #define I2S_RCR4_FSD_SHIFT 0
tushki7 0:60d829a0353a 2360 #define I2S_RCR4_FSP_MASK 0x2u
tushki7 0:60d829a0353a 2361 #define I2S_RCR4_FSP_SHIFT 1
tushki7 0:60d829a0353a 2362 #define I2S_RCR4_ONDEM_MASK 0x4u
tushki7 0:60d829a0353a 2363 #define I2S_RCR4_ONDEM_SHIFT 2
tushki7 0:60d829a0353a 2364 #define I2S_RCR4_FSE_MASK 0x8u
tushki7 0:60d829a0353a 2365 #define I2S_RCR4_FSE_SHIFT 3
tushki7 0:60d829a0353a 2366 #define I2S_RCR4_MF_MASK 0x10u
tushki7 0:60d829a0353a 2367 #define I2S_RCR4_MF_SHIFT 4
tushki7 0:60d829a0353a 2368 #define I2S_RCR4_SYWD_MASK 0x1F00u
tushki7 0:60d829a0353a 2369 #define I2S_RCR4_SYWD_SHIFT 8
tushki7 0:60d829a0353a 2370 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
tushki7 0:60d829a0353a 2371 #define I2S_RCR4_FRSZ_MASK 0x10000u
tushki7 0:60d829a0353a 2372 #define I2S_RCR4_FRSZ_SHIFT 16
tushki7 0:60d829a0353a 2373 #define I2S_RCR4_FPACK_MASK 0x3000000u
tushki7 0:60d829a0353a 2374 #define I2S_RCR4_FPACK_SHIFT 24
tushki7 0:60d829a0353a 2375 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
tushki7 0:60d829a0353a 2376 #define I2S_RCR4_FCONT_MASK 0x10000000u
tushki7 0:60d829a0353a 2377 #define I2S_RCR4_FCONT_SHIFT 28
tushki7 0:60d829a0353a 2378 /* RCR5 Bit Fields */
tushki7 0:60d829a0353a 2379 #define I2S_RCR5_FBT_MASK 0x1F00u
tushki7 0:60d829a0353a 2380 #define I2S_RCR5_FBT_SHIFT 8
tushki7 0:60d829a0353a 2381 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
tushki7 0:60d829a0353a 2382 #define I2S_RCR5_W0W_MASK 0x1F0000u
tushki7 0:60d829a0353a 2383 #define I2S_RCR5_W0W_SHIFT 16
tushki7 0:60d829a0353a 2384 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
tushki7 0:60d829a0353a 2385 #define I2S_RCR5_WNW_MASK 0x1F000000u
tushki7 0:60d829a0353a 2386 #define I2S_RCR5_WNW_SHIFT 24
tushki7 0:60d829a0353a 2387 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
tushki7 0:60d829a0353a 2388 /* RDR Bit Fields */
tushki7 0:60d829a0353a 2389 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 2390 #define I2S_RDR_RDR_SHIFT 0
tushki7 0:60d829a0353a 2391 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
tushki7 0:60d829a0353a 2392 /* RMR Bit Fields */
tushki7 0:60d829a0353a 2393 #define I2S_RMR_RWM_MASK 0x3u
tushki7 0:60d829a0353a 2394 #define I2S_RMR_RWM_SHIFT 0
tushki7 0:60d829a0353a 2395 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
tushki7 0:60d829a0353a 2396 /* MCR Bit Fields */
tushki7 0:60d829a0353a 2397 #define I2S_MCR_MICS_MASK 0x3000000u
tushki7 0:60d829a0353a 2398 #define I2S_MCR_MICS_SHIFT 24
tushki7 0:60d829a0353a 2399 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
tushki7 0:60d829a0353a 2400 #define I2S_MCR_MOE_MASK 0x40000000u
tushki7 0:60d829a0353a 2401 #define I2S_MCR_MOE_SHIFT 30
tushki7 0:60d829a0353a 2402 #define I2S_MCR_DUF_MASK 0x80000000u
tushki7 0:60d829a0353a 2403 #define I2S_MCR_DUF_SHIFT 31
tushki7 0:60d829a0353a 2404
tushki7 0:60d829a0353a 2405 /*!
tushki7 0:60d829a0353a 2406 * @}
tushki7 0:60d829a0353a 2407 */ /* end of group I2S_Register_Masks */
tushki7 0:60d829a0353a 2408
tushki7 0:60d829a0353a 2409
tushki7 0:60d829a0353a 2410 /* I2S - Peripheral instance base addresses */
tushki7 0:60d829a0353a 2411 /** Peripheral I2S0 base address */
tushki7 0:60d829a0353a 2412 #define I2S0_BASE (0x4002F000u)
tushki7 0:60d829a0353a 2413 /** Peripheral I2S0 base pointer */
tushki7 0:60d829a0353a 2414 #define I2S0 ((I2S_Type *)I2S0_BASE)
tushki7 0:60d829a0353a 2415 #define I2S0_BASE_PTR (I2S0)
tushki7 0:60d829a0353a 2416 /** Array initializer of I2S peripheral base addresses */
tushki7 0:60d829a0353a 2417 #define I2S_BASE_ADDRS { I2S0_BASE }
tushki7 0:60d829a0353a 2418 /** Array initializer of I2S peripheral base pointers */
tushki7 0:60d829a0353a 2419 #define I2S_BASE_PTRS { I2S0 }
tushki7 0:60d829a0353a 2420 /** Interrupt vectors for the I2S peripheral type */
tushki7 0:60d829a0353a 2421 #define I2S_RX_IRQS { I2S0_IRQn }
tushki7 0:60d829a0353a 2422 #define I2S_TX_IRQS { I2S0_IRQn }
tushki7 0:60d829a0353a 2423
tushki7 0:60d829a0353a 2424 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 2425 -- I2S - Register accessor macros
tushki7 0:60d829a0353a 2426 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 2427
tushki7 0:60d829a0353a 2428 /*!
tushki7 0:60d829a0353a 2429 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
tushki7 0:60d829a0353a 2430 * @{
tushki7 0:60d829a0353a 2431 */
tushki7 0:60d829a0353a 2432
tushki7 0:60d829a0353a 2433
tushki7 0:60d829a0353a 2434 /* I2S - Register instance definitions */
tushki7 0:60d829a0353a 2435 /* I2S0 */
tushki7 0:60d829a0353a 2436 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
tushki7 0:60d829a0353a 2437 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
tushki7 0:60d829a0353a 2438 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
tushki7 0:60d829a0353a 2439 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
tushki7 0:60d829a0353a 2440 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
tushki7 0:60d829a0353a 2441 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
tushki7 0:60d829a0353a 2442 #define I2S0_TMR I2S_TMR_REG(I2S0)
tushki7 0:60d829a0353a 2443 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
tushki7 0:60d829a0353a 2444 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
tushki7 0:60d829a0353a 2445 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
tushki7 0:60d829a0353a 2446 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
tushki7 0:60d829a0353a 2447 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
tushki7 0:60d829a0353a 2448 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
tushki7 0:60d829a0353a 2449 #define I2S0_RMR I2S_RMR_REG(I2S0)
tushki7 0:60d829a0353a 2450 #define I2S0_MCR I2S_MCR_REG(I2S0)
tushki7 0:60d829a0353a 2451
tushki7 0:60d829a0353a 2452 /* I2S - Register array accessors */
tushki7 0:60d829a0353a 2453 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
tushki7 0:60d829a0353a 2454 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
tushki7 0:60d829a0353a 2455
tushki7 0:60d829a0353a 2456 /*!
tushki7 0:60d829a0353a 2457 * @}
tushki7 0:60d829a0353a 2458 */ /* end of group I2S_Register_Accessor_Macros */
tushki7 0:60d829a0353a 2459
tushki7 0:60d829a0353a 2460
tushki7 0:60d829a0353a 2461 /*!
tushki7 0:60d829a0353a 2462 * @}
tushki7 0:60d829a0353a 2463 */ /* end of group I2S_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 2464
tushki7 0:60d829a0353a 2465
tushki7 0:60d829a0353a 2466 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 2467 -- LCD Peripheral Access Layer
tushki7 0:60d829a0353a 2468 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 2469
tushki7 0:60d829a0353a 2470 /*!
tushki7 0:60d829a0353a 2471 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
tushki7 0:60d829a0353a 2472 * @{
tushki7 0:60d829a0353a 2473 */
tushki7 0:60d829a0353a 2474
tushki7 0:60d829a0353a 2475 /** LCD - Register Layout Typedef */
tushki7 0:60d829a0353a 2476 typedef struct {
tushki7 0:60d829a0353a 2477 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
tushki7 0:60d829a0353a 2478 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
tushki7 0:60d829a0353a 2479 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
tushki7 0:60d829a0353a 2480 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
tushki7 0:60d829a0353a 2481 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
tushki7 0:60d829a0353a 2482 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
tushki7 0:60d829a0353a 2483 union { /* offset: 0x20 */
tushki7 0:60d829a0353a 2484 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
tushki7 0:60d829a0353a 2485 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
tushki7 0:60d829a0353a 2486 };
tushki7 0:60d829a0353a 2487 } LCD_Type, *LCD_MemMapPtr;
tushki7 0:60d829a0353a 2488
tushki7 0:60d829a0353a 2489 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 2490 -- LCD - Register accessor macros
tushki7 0:60d829a0353a 2491 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 2492
tushki7 0:60d829a0353a 2493 /*!
tushki7 0:60d829a0353a 2494 * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
tushki7 0:60d829a0353a 2495 * @{
tushki7 0:60d829a0353a 2496 */
tushki7 0:60d829a0353a 2497
tushki7 0:60d829a0353a 2498
tushki7 0:60d829a0353a 2499 /* LCD - Register accessors */
tushki7 0:60d829a0353a 2500 #define LCD_GCR_REG(base) ((base)->GCR)
tushki7 0:60d829a0353a 2501 #define LCD_AR_REG(base) ((base)->AR)
tushki7 0:60d829a0353a 2502 #define LCD_FDCR_REG(base) ((base)->FDCR)
tushki7 0:60d829a0353a 2503 #define LCD_FDSR_REG(base) ((base)->FDSR)
tushki7 0:60d829a0353a 2504 #define LCD_PEN_REG(base,index) ((base)->PEN[index])
tushki7 0:60d829a0353a 2505 #define LCD_BPEN_REG(base,index) ((base)->BPEN[index])
tushki7 0:60d829a0353a 2506 #define LCD_WF_REG(base,index2) ((base)->WF[index2])
tushki7 0:60d829a0353a 2507 #define LCD_WF8B_REG(base,index2) ((base)->WF8B[index2])
tushki7 0:60d829a0353a 2508
tushki7 0:60d829a0353a 2509 /*!
tushki7 0:60d829a0353a 2510 * @}
tushki7 0:60d829a0353a 2511 */ /* end of group LCD_Register_Accessor_Macros */
tushki7 0:60d829a0353a 2512
tushki7 0:60d829a0353a 2513
tushki7 0:60d829a0353a 2514 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 2515 -- LCD Register Masks
tushki7 0:60d829a0353a 2516 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 2517
tushki7 0:60d829a0353a 2518 /*!
tushki7 0:60d829a0353a 2519 * @addtogroup LCD_Register_Masks LCD Register Masks
tushki7 0:60d829a0353a 2520 * @{
tushki7 0:60d829a0353a 2521 */
tushki7 0:60d829a0353a 2522
tushki7 0:60d829a0353a 2523 /* GCR Bit Fields */
tushki7 0:60d829a0353a 2524 #define LCD_GCR_DUTY_MASK 0x7u
tushki7 0:60d829a0353a 2525 #define LCD_GCR_DUTY_SHIFT 0
tushki7 0:60d829a0353a 2526 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
tushki7 0:60d829a0353a 2527 #define LCD_GCR_LCLK_MASK 0x38u
tushki7 0:60d829a0353a 2528 #define LCD_GCR_LCLK_SHIFT 3
tushki7 0:60d829a0353a 2529 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
tushki7 0:60d829a0353a 2530 #define LCD_GCR_SOURCE_MASK 0x40u
tushki7 0:60d829a0353a 2531 #define LCD_GCR_SOURCE_SHIFT 6
tushki7 0:60d829a0353a 2532 #define LCD_GCR_LCDEN_MASK 0x80u
tushki7 0:60d829a0353a 2533 #define LCD_GCR_LCDEN_SHIFT 7
tushki7 0:60d829a0353a 2534 #define LCD_GCR_LCDSTP_MASK 0x100u
tushki7 0:60d829a0353a 2535 #define LCD_GCR_LCDSTP_SHIFT 8
tushki7 0:60d829a0353a 2536 #define LCD_GCR_LCDDOZE_MASK 0x200u
tushki7 0:60d829a0353a 2537 #define LCD_GCR_LCDDOZE_SHIFT 9
tushki7 0:60d829a0353a 2538 #define LCD_GCR_FFR_MASK 0x400u
tushki7 0:60d829a0353a 2539 #define LCD_GCR_FFR_SHIFT 10
tushki7 0:60d829a0353a 2540 #define LCD_GCR_ALTSOURCE_MASK 0x800u
tushki7 0:60d829a0353a 2541 #define LCD_GCR_ALTSOURCE_SHIFT 11
tushki7 0:60d829a0353a 2542 #define LCD_GCR_ALTDIV_MASK 0x3000u
tushki7 0:60d829a0353a 2543 #define LCD_GCR_ALTDIV_SHIFT 12
tushki7 0:60d829a0353a 2544 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
tushki7 0:60d829a0353a 2545 #define LCD_GCR_FDCIEN_MASK 0x4000u
tushki7 0:60d829a0353a 2546 #define LCD_GCR_FDCIEN_SHIFT 14
tushki7 0:60d829a0353a 2547 #define LCD_GCR_PADSAFE_MASK 0x8000u
tushki7 0:60d829a0353a 2548 #define LCD_GCR_PADSAFE_SHIFT 15
tushki7 0:60d829a0353a 2549 #define LCD_GCR_VSUPPLY_MASK 0x20000u
tushki7 0:60d829a0353a 2550 #define LCD_GCR_VSUPPLY_SHIFT 17
tushki7 0:60d829a0353a 2551 #define LCD_GCR_LADJ_MASK 0x300000u
tushki7 0:60d829a0353a 2552 #define LCD_GCR_LADJ_SHIFT 20
tushki7 0:60d829a0353a 2553 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
tushki7 0:60d829a0353a 2554 #define LCD_GCR_CPSEL_MASK 0x800000u
tushki7 0:60d829a0353a 2555 #define LCD_GCR_CPSEL_SHIFT 23
tushki7 0:60d829a0353a 2556 #define LCD_GCR_RVTRIM_MASK 0xF000000u
tushki7 0:60d829a0353a 2557 #define LCD_GCR_RVTRIM_SHIFT 24
tushki7 0:60d829a0353a 2558 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
tushki7 0:60d829a0353a 2559 #define LCD_GCR_RVEN_MASK 0x80000000u
tushki7 0:60d829a0353a 2560 #define LCD_GCR_RVEN_SHIFT 31
tushki7 0:60d829a0353a 2561 /* AR Bit Fields */
tushki7 0:60d829a0353a 2562 #define LCD_AR_BRATE_MASK 0x7u
tushki7 0:60d829a0353a 2563 #define LCD_AR_BRATE_SHIFT 0
tushki7 0:60d829a0353a 2564 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
tushki7 0:60d829a0353a 2565 #define LCD_AR_BMODE_MASK 0x8u
tushki7 0:60d829a0353a 2566 #define LCD_AR_BMODE_SHIFT 3
tushki7 0:60d829a0353a 2567 #define LCD_AR_BLANK_MASK 0x20u
tushki7 0:60d829a0353a 2568 #define LCD_AR_BLANK_SHIFT 5
tushki7 0:60d829a0353a 2569 #define LCD_AR_ALT_MASK 0x40u
tushki7 0:60d829a0353a 2570 #define LCD_AR_ALT_SHIFT 6
tushki7 0:60d829a0353a 2571 #define LCD_AR_BLINK_MASK 0x80u
tushki7 0:60d829a0353a 2572 #define LCD_AR_BLINK_SHIFT 7
tushki7 0:60d829a0353a 2573 /* FDCR Bit Fields */
tushki7 0:60d829a0353a 2574 #define LCD_FDCR_FDPINID_MASK 0x3Fu
tushki7 0:60d829a0353a 2575 #define LCD_FDCR_FDPINID_SHIFT 0
tushki7 0:60d829a0353a 2576 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
tushki7 0:60d829a0353a 2577 #define LCD_FDCR_FDBPEN_MASK 0x40u
tushki7 0:60d829a0353a 2578 #define LCD_FDCR_FDBPEN_SHIFT 6
tushki7 0:60d829a0353a 2579 #define LCD_FDCR_FDEN_MASK 0x80u
tushki7 0:60d829a0353a 2580 #define LCD_FDCR_FDEN_SHIFT 7
tushki7 0:60d829a0353a 2581 #define LCD_FDCR_FDSWW_MASK 0xE00u
tushki7 0:60d829a0353a 2582 #define LCD_FDCR_FDSWW_SHIFT 9
tushki7 0:60d829a0353a 2583 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
tushki7 0:60d829a0353a 2584 #define LCD_FDCR_FDPRS_MASK 0x7000u
tushki7 0:60d829a0353a 2585 #define LCD_FDCR_FDPRS_SHIFT 12
tushki7 0:60d829a0353a 2586 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
tushki7 0:60d829a0353a 2587 /* FDSR Bit Fields */
tushki7 0:60d829a0353a 2588 #define LCD_FDSR_FDCNT_MASK 0xFFu
tushki7 0:60d829a0353a 2589 #define LCD_FDSR_FDCNT_SHIFT 0
tushki7 0:60d829a0353a 2590 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
tushki7 0:60d829a0353a 2591 #define LCD_FDSR_FDCF_MASK 0x8000u
tushki7 0:60d829a0353a 2592 #define LCD_FDSR_FDCF_SHIFT 15
tushki7 0:60d829a0353a 2593 /* PEN Bit Fields */
tushki7 0:60d829a0353a 2594 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 2595 #define LCD_PEN_PEN_SHIFT 0
tushki7 0:60d829a0353a 2596 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
tushki7 0:60d829a0353a 2597 /* BPEN Bit Fields */
tushki7 0:60d829a0353a 2598 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 2599 #define LCD_BPEN_BPEN_SHIFT 0
tushki7 0:60d829a0353a 2600 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
tushki7 0:60d829a0353a 2601 /* WF Bit Fields */
tushki7 0:60d829a0353a 2602 #define LCD_WF_WF0_MASK 0xFFu
tushki7 0:60d829a0353a 2603 #define LCD_WF_WF0_SHIFT 0
tushki7 0:60d829a0353a 2604 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
tushki7 0:60d829a0353a 2605 #define LCD_WF_WF60_MASK 0xFFu
tushki7 0:60d829a0353a 2606 #define LCD_WF_WF60_SHIFT 0
tushki7 0:60d829a0353a 2607 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
tushki7 0:60d829a0353a 2608 #define LCD_WF_WF56_MASK 0xFFu
tushki7 0:60d829a0353a 2609 #define LCD_WF_WF56_SHIFT 0
tushki7 0:60d829a0353a 2610 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
tushki7 0:60d829a0353a 2611 #define LCD_WF_WF52_MASK 0xFFu
tushki7 0:60d829a0353a 2612 #define LCD_WF_WF52_SHIFT 0
tushki7 0:60d829a0353a 2613 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
tushki7 0:60d829a0353a 2614 #define LCD_WF_WF4_MASK 0xFFu
tushki7 0:60d829a0353a 2615 #define LCD_WF_WF4_SHIFT 0
tushki7 0:60d829a0353a 2616 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
tushki7 0:60d829a0353a 2617 #define LCD_WF_WF48_MASK 0xFFu
tushki7 0:60d829a0353a 2618 #define LCD_WF_WF48_SHIFT 0
tushki7 0:60d829a0353a 2619 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
tushki7 0:60d829a0353a 2620 #define LCD_WF_WF44_MASK 0xFFu
tushki7 0:60d829a0353a 2621 #define LCD_WF_WF44_SHIFT 0
tushki7 0:60d829a0353a 2622 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
tushki7 0:60d829a0353a 2623 #define LCD_WF_WF40_MASK 0xFFu
tushki7 0:60d829a0353a 2624 #define LCD_WF_WF40_SHIFT 0
tushki7 0:60d829a0353a 2625 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
tushki7 0:60d829a0353a 2626 #define LCD_WF_WF8_MASK 0xFFu
tushki7 0:60d829a0353a 2627 #define LCD_WF_WF8_SHIFT 0
tushki7 0:60d829a0353a 2628 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
tushki7 0:60d829a0353a 2629 #define LCD_WF_WF36_MASK 0xFFu
tushki7 0:60d829a0353a 2630 #define LCD_WF_WF36_SHIFT 0
tushki7 0:60d829a0353a 2631 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
tushki7 0:60d829a0353a 2632 #define LCD_WF_WF32_MASK 0xFFu
tushki7 0:60d829a0353a 2633 #define LCD_WF_WF32_SHIFT 0
tushki7 0:60d829a0353a 2634 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
tushki7 0:60d829a0353a 2635 #define LCD_WF_WF28_MASK 0xFFu
tushki7 0:60d829a0353a 2636 #define LCD_WF_WF28_SHIFT 0
tushki7 0:60d829a0353a 2637 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
tushki7 0:60d829a0353a 2638 #define LCD_WF_WF12_MASK 0xFFu
tushki7 0:60d829a0353a 2639 #define LCD_WF_WF12_SHIFT 0
tushki7 0:60d829a0353a 2640 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
tushki7 0:60d829a0353a 2641 #define LCD_WF_WF24_MASK 0xFFu
tushki7 0:60d829a0353a 2642 #define LCD_WF_WF24_SHIFT 0
tushki7 0:60d829a0353a 2643 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
tushki7 0:60d829a0353a 2644 #define LCD_WF_WF20_MASK 0xFFu
tushki7 0:60d829a0353a 2645 #define LCD_WF_WF20_SHIFT 0
tushki7 0:60d829a0353a 2646 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
tushki7 0:60d829a0353a 2647 #define LCD_WF_WF16_MASK 0xFFu
tushki7 0:60d829a0353a 2648 #define LCD_WF_WF16_SHIFT 0
tushki7 0:60d829a0353a 2649 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
tushki7 0:60d829a0353a 2650 #define LCD_WF_WF5_MASK 0xFF00u
tushki7 0:60d829a0353a 2651 #define LCD_WF_WF5_SHIFT 8
tushki7 0:60d829a0353a 2652 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
tushki7 0:60d829a0353a 2653 #define LCD_WF_WF49_MASK 0xFF00u
tushki7 0:60d829a0353a 2654 #define LCD_WF_WF49_SHIFT 8
tushki7 0:60d829a0353a 2655 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
tushki7 0:60d829a0353a 2656 #define LCD_WF_WF45_MASK 0xFF00u
tushki7 0:60d829a0353a 2657 #define LCD_WF_WF45_SHIFT 8
tushki7 0:60d829a0353a 2658 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
tushki7 0:60d829a0353a 2659 #define LCD_WF_WF61_MASK 0xFF00u
tushki7 0:60d829a0353a 2660 #define LCD_WF_WF61_SHIFT 8
tushki7 0:60d829a0353a 2661 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
tushki7 0:60d829a0353a 2662 #define LCD_WF_WF25_MASK 0xFF00u
tushki7 0:60d829a0353a 2663 #define LCD_WF_WF25_SHIFT 8
tushki7 0:60d829a0353a 2664 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
tushki7 0:60d829a0353a 2665 #define LCD_WF_WF17_MASK 0xFF00u
tushki7 0:60d829a0353a 2666 #define LCD_WF_WF17_SHIFT 8
tushki7 0:60d829a0353a 2667 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
tushki7 0:60d829a0353a 2668 #define LCD_WF_WF41_MASK 0xFF00u
tushki7 0:60d829a0353a 2669 #define LCD_WF_WF41_SHIFT 8
tushki7 0:60d829a0353a 2670 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
tushki7 0:60d829a0353a 2671 #define LCD_WF_WF13_MASK 0xFF00u
tushki7 0:60d829a0353a 2672 #define LCD_WF_WF13_SHIFT 8
tushki7 0:60d829a0353a 2673 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
tushki7 0:60d829a0353a 2674 #define LCD_WF_WF57_MASK 0xFF00u
tushki7 0:60d829a0353a 2675 #define LCD_WF_WF57_SHIFT 8
tushki7 0:60d829a0353a 2676 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
tushki7 0:60d829a0353a 2677 #define LCD_WF_WF53_MASK 0xFF00u
tushki7 0:60d829a0353a 2678 #define LCD_WF_WF53_SHIFT 8
tushki7 0:60d829a0353a 2679 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
tushki7 0:60d829a0353a 2680 #define LCD_WF_WF37_MASK 0xFF00u
tushki7 0:60d829a0353a 2681 #define LCD_WF_WF37_SHIFT 8
tushki7 0:60d829a0353a 2682 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
tushki7 0:60d829a0353a 2683 #define LCD_WF_WF9_MASK 0xFF00u
tushki7 0:60d829a0353a 2684 #define LCD_WF_WF9_SHIFT 8
tushki7 0:60d829a0353a 2685 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
tushki7 0:60d829a0353a 2686 #define LCD_WF_WF1_MASK 0xFF00u
tushki7 0:60d829a0353a 2687 #define LCD_WF_WF1_SHIFT 8
tushki7 0:60d829a0353a 2688 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
tushki7 0:60d829a0353a 2689 #define LCD_WF_WF29_MASK 0xFF00u
tushki7 0:60d829a0353a 2690 #define LCD_WF_WF29_SHIFT 8
tushki7 0:60d829a0353a 2691 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
tushki7 0:60d829a0353a 2692 #define LCD_WF_WF33_MASK 0xFF00u
tushki7 0:60d829a0353a 2693 #define LCD_WF_WF33_SHIFT 8
tushki7 0:60d829a0353a 2694 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
tushki7 0:60d829a0353a 2695 #define LCD_WF_WF21_MASK 0xFF00u
tushki7 0:60d829a0353a 2696 #define LCD_WF_WF21_SHIFT 8
tushki7 0:60d829a0353a 2697 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
tushki7 0:60d829a0353a 2698 #define LCD_WF_WF26_MASK 0xFF0000u
tushki7 0:60d829a0353a 2699 #define LCD_WF_WF26_SHIFT 16
tushki7 0:60d829a0353a 2700 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
tushki7 0:60d829a0353a 2701 #define LCD_WF_WF46_MASK 0xFF0000u
tushki7 0:60d829a0353a 2702 #define LCD_WF_WF46_SHIFT 16
tushki7 0:60d829a0353a 2703 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
tushki7 0:60d829a0353a 2704 #define LCD_WF_WF6_MASK 0xFF0000u
tushki7 0:60d829a0353a 2705 #define LCD_WF_WF6_SHIFT 16
tushki7 0:60d829a0353a 2706 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
tushki7 0:60d829a0353a 2707 #define LCD_WF_WF42_MASK 0xFF0000u
tushki7 0:60d829a0353a 2708 #define LCD_WF_WF42_SHIFT 16
tushki7 0:60d829a0353a 2709 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
tushki7 0:60d829a0353a 2710 #define LCD_WF_WF18_MASK 0xFF0000u
tushki7 0:60d829a0353a 2711 #define LCD_WF_WF18_SHIFT 16
tushki7 0:60d829a0353a 2712 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
tushki7 0:60d829a0353a 2713 #define LCD_WF_WF38_MASK 0xFF0000u
tushki7 0:60d829a0353a 2714 #define LCD_WF_WF38_SHIFT 16
tushki7 0:60d829a0353a 2715 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
tushki7 0:60d829a0353a 2716 #define LCD_WF_WF22_MASK 0xFF0000u
tushki7 0:60d829a0353a 2717 #define LCD_WF_WF22_SHIFT 16
tushki7 0:60d829a0353a 2718 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
tushki7 0:60d829a0353a 2719 #define LCD_WF_WF34_MASK 0xFF0000u
tushki7 0:60d829a0353a 2720 #define LCD_WF_WF34_SHIFT 16
tushki7 0:60d829a0353a 2721 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
tushki7 0:60d829a0353a 2722 #define LCD_WF_WF50_MASK 0xFF0000u
tushki7 0:60d829a0353a 2723 #define LCD_WF_WF50_SHIFT 16
tushki7 0:60d829a0353a 2724 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
tushki7 0:60d829a0353a 2725 #define LCD_WF_WF14_MASK 0xFF0000u
tushki7 0:60d829a0353a 2726 #define LCD_WF_WF14_SHIFT 16
tushki7 0:60d829a0353a 2727 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
tushki7 0:60d829a0353a 2728 #define LCD_WF_WF54_MASK 0xFF0000u
tushki7 0:60d829a0353a 2729 #define LCD_WF_WF54_SHIFT 16
tushki7 0:60d829a0353a 2730 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
tushki7 0:60d829a0353a 2731 #define LCD_WF_WF2_MASK 0xFF0000u
tushki7 0:60d829a0353a 2732 #define LCD_WF_WF2_SHIFT 16
tushki7 0:60d829a0353a 2733 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
tushki7 0:60d829a0353a 2734 #define LCD_WF_WF58_MASK 0xFF0000u
tushki7 0:60d829a0353a 2735 #define LCD_WF_WF58_SHIFT 16
tushki7 0:60d829a0353a 2736 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
tushki7 0:60d829a0353a 2737 #define LCD_WF_WF30_MASK 0xFF0000u
tushki7 0:60d829a0353a 2738 #define LCD_WF_WF30_SHIFT 16
tushki7 0:60d829a0353a 2739 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
tushki7 0:60d829a0353a 2740 #define LCD_WF_WF62_MASK 0xFF0000u
tushki7 0:60d829a0353a 2741 #define LCD_WF_WF62_SHIFT 16
tushki7 0:60d829a0353a 2742 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
tushki7 0:60d829a0353a 2743 #define LCD_WF_WF10_MASK 0xFF0000u
tushki7 0:60d829a0353a 2744 #define LCD_WF_WF10_SHIFT 16
tushki7 0:60d829a0353a 2745 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
tushki7 0:60d829a0353a 2746 #define LCD_WF_WF63_MASK 0xFF000000u
tushki7 0:60d829a0353a 2747 #define LCD_WF_WF63_SHIFT 24
tushki7 0:60d829a0353a 2748 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
tushki7 0:60d829a0353a 2749 #define LCD_WF_WF59_MASK 0xFF000000u
tushki7 0:60d829a0353a 2750 #define LCD_WF_WF59_SHIFT 24
tushki7 0:60d829a0353a 2751 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
tushki7 0:60d829a0353a 2752 #define LCD_WF_WF55_MASK 0xFF000000u
tushki7 0:60d829a0353a 2753 #define LCD_WF_WF55_SHIFT 24
tushki7 0:60d829a0353a 2754 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
tushki7 0:60d829a0353a 2755 #define LCD_WF_WF3_MASK 0xFF000000u
tushki7 0:60d829a0353a 2756 #define LCD_WF_WF3_SHIFT 24
tushki7 0:60d829a0353a 2757 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
tushki7 0:60d829a0353a 2758 #define LCD_WF_WF51_MASK 0xFF000000u
tushki7 0:60d829a0353a 2759 #define LCD_WF_WF51_SHIFT 24
tushki7 0:60d829a0353a 2760 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
tushki7 0:60d829a0353a 2761 #define LCD_WF_WF47_MASK 0xFF000000u
tushki7 0:60d829a0353a 2762 #define LCD_WF_WF47_SHIFT 24
tushki7 0:60d829a0353a 2763 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
tushki7 0:60d829a0353a 2764 #define LCD_WF_WF43_MASK 0xFF000000u
tushki7 0:60d829a0353a 2765 #define LCD_WF_WF43_SHIFT 24
tushki7 0:60d829a0353a 2766 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
tushki7 0:60d829a0353a 2767 #define LCD_WF_WF7_MASK 0xFF000000u
tushki7 0:60d829a0353a 2768 #define LCD_WF_WF7_SHIFT 24
tushki7 0:60d829a0353a 2769 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
tushki7 0:60d829a0353a 2770 #define LCD_WF_WF39_MASK 0xFF000000u
tushki7 0:60d829a0353a 2771 #define LCD_WF_WF39_SHIFT 24
tushki7 0:60d829a0353a 2772 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
tushki7 0:60d829a0353a 2773 #define LCD_WF_WF35_MASK 0xFF000000u
tushki7 0:60d829a0353a 2774 #define LCD_WF_WF35_SHIFT 24
tushki7 0:60d829a0353a 2775 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
tushki7 0:60d829a0353a 2776 #define LCD_WF_WF31_MASK 0xFF000000u
tushki7 0:60d829a0353a 2777 #define LCD_WF_WF31_SHIFT 24
tushki7 0:60d829a0353a 2778 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
tushki7 0:60d829a0353a 2779 #define LCD_WF_WF11_MASK 0xFF000000u
tushki7 0:60d829a0353a 2780 #define LCD_WF_WF11_SHIFT 24
tushki7 0:60d829a0353a 2781 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
tushki7 0:60d829a0353a 2782 #define LCD_WF_WF27_MASK 0xFF000000u
tushki7 0:60d829a0353a 2783 #define LCD_WF_WF27_SHIFT 24
tushki7 0:60d829a0353a 2784 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
tushki7 0:60d829a0353a 2785 #define LCD_WF_WF23_MASK 0xFF000000u
tushki7 0:60d829a0353a 2786 #define LCD_WF_WF23_SHIFT 24
tushki7 0:60d829a0353a 2787 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
tushki7 0:60d829a0353a 2788 #define LCD_WF_WF19_MASK 0xFF000000u
tushki7 0:60d829a0353a 2789 #define LCD_WF_WF19_SHIFT 24
tushki7 0:60d829a0353a 2790 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
tushki7 0:60d829a0353a 2791 #define LCD_WF_WF15_MASK 0xFF000000u
tushki7 0:60d829a0353a 2792 #define LCD_WF_WF15_SHIFT 24
tushki7 0:60d829a0353a 2793 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
tushki7 0:60d829a0353a 2794 /* WF8B Bit Fields */
tushki7 0:60d829a0353a 2795 #define LCD_WF8B_BPALCD0_MASK 0x1u
tushki7 0:60d829a0353a 2796 #define LCD_WF8B_BPALCD0_SHIFT 0
tushki7 0:60d829a0353a 2797 #define LCD_WF8B_BPALCD63_MASK 0x1u
tushki7 0:60d829a0353a 2798 #define LCD_WF8B_BPALCD63_SHIFT 0
tushki7 0:60d829a0353a 2799 #define LCD_WF8B_BPALCD62_MASK 0x1u
tushki7 0:60d829a0353a 2800 #define LCD_WF8B_BPALCD62_SHIFT 0
tushki7 0:60d829a0353a 2801 #define LCD_WF8B_BPALCD61_MASK 0x1u
tushki7 0:60d829a0353a 2802 #define LCD_WF8B_BPALCD61_SHIFT 0
tushki7 0:60d829a0353a 2803 #define LCD_WF8B_BPALCD60_MASK 0x1u
tushki7 0:60d829a0353a 2804 #define LCD_WF8B_BPALCD60_SHIFT 0
tushki7 0:60d829a0353a 2805 #define LCD_WF8B_BPALCD59_MASK 0x1u
tushki7 0:60d829a0353a 2806 #define LCD_WF8B_BPALCD59_SHIFT 0
tushki7 0:60d829a0353a 2807 #define LCD_WF8B_BPALCD58_MASK 0x1u
tushki7 0:60d829a0353a 2808 #define LCD_WF8B_BPALCD58_SHIFT 0
tushki7 0:60d829a0353a 2809 #define LCD_WF8B_BPALCD57_MASK 0x1u
tushki7 0:60d829a0353a 2810 #define LCD_WF8B_BPALCD57_SHIFT 0
tushki7 0:60d829a0353a 2811 #define LCD_WF8B_BPALCD1_MASK 0x1u
tushki7 0:60d829a0353a 2812 #define LCD_WF8B_BPALCD1_SHIFT 0
tushki7 0:60d829a0353a 2813 #define LCD_WF8B_BPALCD56_MASK 0x1u
tushki7 0:60d829a0353a 2814 #define LCD_WF8B_BPALCD56_SHIFT 0
tushki7 0:60d829a0353a 2815 #define LCD_WF8B_BPALCD55_MASK 0x1u
tushki7 0:60d829a0353a 2816 #define LCD_WF8B_BPALCD55_SHIFT 0
tushki7 0:60d829a0353a 2817 #define LCD_WF8B_BPALCD54_MASK 0x1u
tushki7 0:60d829a0353a 2818 #define LCD_WF8B_BPALCD54_SHIFT 0
tushki7 0:60d829a0353a 2819 #define LCD_WF8B_BPALCD53_MASK 0x1u
tushki7 0:60d829a0353a 2820 #define LCD_WF8B_BPALCD53_SHIFT 0
tushki7 0:60d829a0353a 2821 #define LCD_WF8B_BPALCD52_MASK 0x1u
tushki7 0:60d829a0353a 2822 #define LCD_WF8B_BPALCD52_SHIFT 0
tushki7 0:60d829a0353a 2823 #define LCD_WF8B_BPALCD51_MASK 0x1u
tushki7 0:60d829a0353a 2824 #define LCD_WF8B_BPALCD51_SHIFT 0
tushki7 0:60d829a0353a 2825 #define LCD_WF8B_BPALCD50_MASK 0x1u
tushki7 0:60d829a0353a 2826 #define LCD_WF8B_BPALCD50_SHIFT 0
tushki7 0:60d829a0353a 2827 #define LCD_WF8B_BPALCD2_MASK 0x1u
tushki7 0:60d829a0353a 2828 #define LCD_WF8B_BPALCD2_SHIFT 0
tushki7 0:60d829a0353a 2829 #define LCD_WF8B_BPALCD49_MASK 0x1u
tushki7 0:60d829a0353a 2830 #define LCD_WF8B_BPALCD49_SHIFT 0
tushki7 0:60d829a0353a 2831 #define LCD_WF8B_BPALCD48_MASK 0x1u
tushki7 0:60d829a0353a 2832 #define LCD_WF8B_BPALCD48_SHIFT 0
tushki7 0:60d829a0353a 2833 #define LCD_WF8B_BPALCD47_MASK 0x1u
tushki7 0:60d829a0353a 2834 #define LCD_WF8B_BPALCD47_SHIFT 0
tushki7 0:60d829a0353a 2835 #define LCD_WF8B_BPALCD46_MASK 0x1u
tushki7 0:60d829a0353a 2836 #define LCD_WF8B_BPALCD46_SHIFT 0
tushki7 0:60d829a0353a 2837 #define LCD_WF8B_BPALCD45_MASK 0x1u
tushki7 0:60d829a0353a 2838 #define LCD_WF8B_BPALCD45_SHIFT 0
tushki7 0:60d829a0353a 2839 #define LCD_WF8B_BPALCD44_MASK 0x1u
tushki7 0:60d829a0353a 2840 #define LCD_WF8B_BPALCD44_SHIFT 0
tushki7 0:60d829a0353a 2841 #define LCD_WF8B_BPALCD43_MASK 0x1u
tushki7 0:60d829a0353a 2842 #define LCD_WF8B_BPALCD43_SHIFT 0
tushki7 0:60d829a0353a 2843 #define LCD_WF8B_BPALCD3_MASK 0x1u
tushki7 0:60d829a0353a 2844 #define LCD_WF8B_BPALCD3_SHIFT 0
tushki7 0:60d829a0353a 2845 #define LCD_WF8B_BPALCD42_MASK 0x1u
tushki7 0:60d829a0353a 2846 #define LCD_WF8B_BPALCD42_SHIFT 0
tushki7 0:60d829a0353a 2847 #define LCD_WF8B_BPALCD41_MASK 0x1u
tushki7 0:60d829a0353a 2848 #define LCD_WF8B_BPALCD41_SHIFT 0
tushki7 0:60d829a0353a 2849 #define LCD_WF8B_BPALCD40_MASK 0x1u
tushki7 0:60d829a0353a 2850 #define LCD_WF8B_BPALCD40_SHIFT 0
tushki7 0:60d829a0353a 2851 #define LCD_WF8B_BPALCD39_MASK 0x1u
tushki7 0:60d829a0353a 2852 #define LCD_WF8B_BPALCD39_SHIFT 0
tushki7 0:60d829a0353a 2853 #define LCD_WF8B_BPALCD38_MASK 0x1u
tushki7 0:60d829a0353a 2854 #define LCD_WF8B_BPALCD38_SHIFT 0
tushki7 0:60d829a0353a 2855 #define LCD_WF8B_BPALCD37_MASK 0x1u
tushki7 0:60d829a0353a 2856 #define LCD_WF8B_BPALCD37_SHIFT 0
tushki7 0:60d829a0353a 2857 #define LCD_WF8B_BPALCD36_MASK 0x1u
tushki7 0:60d829a0353a 2858 #define LCD_WF8B_BPALCD36_SHIFT 0
tushki7 0:60d829a0353a 2859 #define LCD_WF8B_BPALCD4_MASK 0x1u
tushki7 0:60d829a0353a 2860 #define LCD_WF8B_BPALCD4_SHIFT 0
tushki7 0:60d829a0353a 2861 #define LCD_WF8B_BPALCD35_MASK 0x1u
tushki7 0:60d829a0353a 2862 #define LCD_WF8B_BPALCD35_SHIFT 0
tushki7 0:60d829a0353a 2863 #define LCD_WF8B_BPALCD34_MASK 0x1u
tushki7 0:60d829a0353a 2864 #define LCD_WF8B_BPALCD34_SHIFT 0
tushki7 0:60d829a0353a 2865 #define LCD_WF8B_BPALCD33_MASK 0x1u
tushki7 0:60d829a0353a 2866 #define LCD_WF8B_BPALCD33_SHIFT 0
tushki7 0:60d829a0353a 2867 #define LCD_WF8B_BPALCD32_MASK 0x1u
tushki7 0:60d829a0353a 2868 #define LCD_WF8B_BPALCD32_SHIFT 0
tushki7 0:60d829a0353a 2869 #define LCD_WF8B_BPALCD31_MASK 0x1u
tushki7 0:60d829a0353a 2870 #define LCD_WF8B_BPALCD31_SHIFT 0
tushki7 0:60d829a0353a 2871 #define LCD_WF8B_BPALCD30_MASK 0x1u
tushki7 0:60d829a0353a 2872 #define LCD_WF8B_BPALCD30_SHIFT 0
tushki7 0:60d829a0353a 2873 #define LCD_WF8B_BPALCD29_MASK 0x1u
tushki7 0:60d829a0353a 2874 #define LCD_WF8B_BPALCD29_SHIFT 0
tushki7 0:60d829a0353a 2875 #define LCD_WF8B_BPALCD5_MASK 0x1u
tushki7 0:60d829a0353a 2876 #define LCD_WF8B_BPALCD5_SHIFT 0
tushki7 0:60d829a0353a 2877 #define LCD_WF8B_BPALCD28_MASK 0x1u
tushki7 0:60d829a0353a 2878 #define LCD_WF8B_BPALCD28_SHIFT 0
tushki7 0:60d829a0353a 2879 #define LCD_WF8B_BPALCD27_MASK 0x1u
tushki7 0:60d829a0353a 2880 #define LCD_WF8B_BPALCD27_SHIFT 0
tushki7 0:60d829a0353a 2881 #define LCD_WF8B_BPALCD26_MASK 0x1u
tushki7 0:60d829a0353a 2882 #define LCD_WF8B_BPALCD26_SHIFT 0
tushki7 0:60d829a0353a 2883 #define LCD_WF8B_BPALCD25_MASK 0x1u
tushki7 0:60d829a0353a 2884 #define LCD_WF8B_BPALCD25_SHIFT 0
tushki7 0:60d829a0353a 2885 #define LCD_WF8B_BPALCD24_MASK 0x1u
tushki7 0:60d829a0353a 2886 #define LCD_WF8B_BPALCD24_SHIFT 0
tushki7 0:60d829a0353a 2887 #define LCD_WF8B_BPALCD23_MASK 0x1u
tushki7 0:60d829a0353a 2888 #define LCD_WF8B_BPALCD23_SHIFT 0
tushki7 0:60d829a0353a 2889 #define LCD_WF8B_BPALCD22_MASK 0x1u
tushki7 0:60d829a0353a 2890 #define LCD_WF8B_BPALCD22_SHIFT 0
tushki7 0:60d829a0353a 2891 #define LCD_WF8B_BPALCD6_MASK 0x1u
tushki7 0:60d829a0353a 2892 #define LCD_WF8B_BPALCD6_SHIFT 0
tushki7 0:60d829a0353a 2893 #define LCD_WF8B_BPALCD21_MASK 0x1u
tushki7 0:60d829a0353a 2894 #define LCD_WF8B_BPALCD21_SHIFT 0
tushki7 0:60d829a0353a 2895 #define LCD_WF8B_BPALCD20_MASK 0x1u
tushki7 0:60d829a0353a 2896 #define LCD_WF8B_BPALCD20_SHIFT 0
tushki7 0:60d829a0353a 2897 #define LCD_WF8B_BPALCD19_MASK 0x1u
tushki7 0:60d829a0353a 2898 #define LCD_WF8B_BPALCD19_SHIFT 0
tushki7 0:60d829a0353a 2899 #define LCD_WF8B_BPALCD18_MASK 0x1u
tushki7 0:60d829a0353a 2900 #define LCD_WF8B_BPALCD18_SHIFT 0
tushki7 0:60d829a0353a 2901 #define LCD_WF8B_BPALCD17_MASK 0x1u
tushki7 0:60d829a0353a 2902 #define LCD_WF8B_BPALCD17_SHIFT 0
tushki7 0:60d829a0353a 2903 #define LCD_WF8B_BPALCD16_MASK 0x1u
tushki7 0:60d829a0353a 2904 #define LCD_WF8B_BPALCD16_SHIFT 0
tushki7 0:60d829a0353a 2905 #define LCD_WF8B_BPALCD15_MASK 0x1u
tushki7 0:60d829a0353a 2906 #define LCD_WF8B_BPALCD15_SHIFT 0
tushki7 0:60d829a0353a 2907 #define LCD_WF8B_BPALCD7_MASK 0x1u
tushki7 0:60d829a0353a 2908 #define LCD_WF8B_BPALCD7_SHIFT 0
tushki7 0:60d829a0353a 2909 #define LCD_WF8B_BPALCD14_MASK 0x1u
tushki7 0:60d829a0353a 2910 #define LCD_WF8B_BPALCD14_SHIFT 0
tushki7 0:60d829a0353a 2911 #define LCD_WF8B_BPALCD13_MASK 0x1u
tushki7 0:60d829a0353a 2912 #define LCD_WF8B_BPALCD13_SHIFT 0
tushki7 0:60d829a0353a 2913 #define LCD_WF8B_BPALCD12_MASK 0x1u
tushki7 0:60d829a0353a 2914 #define LCD_WF8B_BPALCD12_SHIFT 0
tushki7 0:60d829a0353a 2915 #define LCD_WF8B_BPALCD11_MASK 0x1u
tushki7 0:60d829a0353a 2916 #define LCD_WF8B_BPALCD11_SHIFT 0
tushki7 0:60d829a0353a 2917 #define LCD_WF8B_BPALCD10_MASK 0x1u
tushki7 0:60d829a0353a 2918 #define LCD_WF8B_BPALCD10_SHIFT 0
tushki7 0:60d829a0353a 2919 #define LCD_WF8B_BPALCD9_MASK 0x1u
tushki7 0:60d829a0353a 2920 #define LCD_WF8B_BPALCD9_SHIFT 0
tushki7 0:60d829a0353a 2921 #define LCD_WF8B_BPALCD8_MASK 0x1u
tushki7 0:60d829a0353a 2922 #define LCD_WF8B_BPALCD8_SHIFT 0
tushki7 0:60d829a0353a 2923 #define LCD_WF8B_BPBLCD1_MASK 0x2u
tushki7 0:60d829a0353a 2924 #define LCD_WF8B_BPBLCD1_SHIFT 1
tushki7 0:60d829a0353a 2925 #define LCD_WF8B_BPBLCD32_MASK 0x2u
tushki7 0:60d829a0353a 2926 #define LCD_WF8B_BPBLCD32_SHIFT 1
tushki7 0:60d829a0353a 2927 #define LCD_WF8B_BPBLCD30_MASK 0x2u
tushki7 0:60d829a0353a 2928 #define LCD_WF8B_BPBLCD30_SHIFT 1
tushki7 0:60d829a0353a 2929 #define LCD_WF8B_BPBLCD60_MASK 0x2u
tushki7 0:60d829a0353a 2930 #define LCD_WF8B_BPBLCD60_SHIFT 1
tushki7 0:60d829a0353a 2931 #define LCD_WF8B_BPBLCD24_MASK 0x2u
tushki7 0:60d829a0353a 2932 #define LCD_WF8B_BPBLCD24_SHIFT 1
tushki7 0:60d829a0353a 2933 #define LCD_WF8B_BPBLCD28_MASK 0x2u
tushki7 0:60d829a0353a 2934 #define LCD_WF8B_BPBLCD28_SHIFT 1
tushki7 0:60d829a0353a 2935 #define LCD_WF8B_BPBLCD23_MASK 0x2u
tushki7 0:60d829a0353a 2936 #define LCD_WF8B_BPBLCD23_SHIFT 1
tushki7 0:60d829a0353a 2937 #define LCD_WF8B_BPBLCD48_MASK 0x2u
tushki7 0:60d829a0353a 2938 #define LCD_WF8B_BPBLCD48_SHIFT 1
tushki7 0:60d829a0353a 2939 #define LCD_WF8B_BPBLCD10_MASK 0x2u
tushki7 0:60d829a0353a 2940 #define LCD_WF8B_BPBLCD10_SHIFT 1
tushki7 0:60d829a0353a 2941 #define LCD_WF8B_BPBLCD15_MASK 0x2u
tushki7 0:60d829a0353a 2942 #define LCD_WF8B_BPBLCD15_SHIFT 1
tushki7 0:60d829a0353a 2943 #define LCD_WF8B_BPBLCD36_MASK 0x2u
tushki7 0:60d829a0353a 2944 #define LCD_WF8B_BPBLCD36_SHIFT 1
tushki7 0:60d829a0353a 2945 #define LCD_WF8B_BPBLCD44_MASK 0x2u
tushki7 0:60d829a0353a 2946 #define LCD_WF8B_BPBLCD44_SHIFT 1
tushki7 0:60d829a0353a 2947 #define LCD_WF8B_BPBLCD62_MASK 0x2u
tushki7 0:60d829a0353a 2948 #define LCD_WF8B_BPBLCD62_SHIFT 1
tushki7 0:60d829a0353a 2949 #define LCD_WF8B_BPBLCD53_MASK 0x2u
tushki7 0:60d829a0353a 2950 #define LCD_WF8B_BPBLCD53_SHIFT 1
tushki7 0:60d829a0353a 2951 #define LCD_WF8B_BPBLCD22_MASK 0x2u
tushki7 0:60d829a0353a 2952 #define LCD_WF8B_BPBLCD22_SHIFT 1
tushki7 0:60d829a0353a 2953 #define LCD_WF8B_BPBLCD47_MASK 0x2u
tushki7 0:60d829a0353a 2954 #define LCD_WF8B_BPBLCD47_SHIFT 1
tushki7 0:60d829a0353a 2955 #define LCD_WF8B_BPBLCD33_MASK 0x2u
tushki7 0:60d829a0353a 2956 #define LCD_WF8B_BPBLCD33_SHIFT 1
tushki7 0:60d829a0353a 2957 #define LCD_WF8B_BPBLCD2_MASK 0x2u
tushki7 0:60d829a0353a 2958 #define LCD_WF8B_BPBLCD2_SHIFT 1
tushki7 0:60d829a0353a 2959 #define LCD_WF8B_BPBLCD49_MASK 0x2u
tushki7 0:60d829a0353a 2960 #define LCD_WF8B_BPBLCD49_SHIFT 1
tushki7 0:60d829a0353a 2961 #define LCD_WF8B_BPBLCD0_MASK 0x2u
tushki7 0:60d829a0353a 2962 #define LCD_WF8B_BPBLCD0_SHIFT 1
tushki7 0:60d829a0353a 2963 #define LCD_WF8B_BPBLCD55_MASK 0x2u
tushki7 0:60d829a0353a 2964 #define LCD_WF8B_BPBLCD55_SHIFT 1
tushki7 0:60d829a0353a 2965 #define LCD_WF8B_BPBLCD56_MASK 0x2u
tushki7 0:60d829a0353a 2966 #define LCD_WF8B_BPBLCD56_SHIFT 1
tushki7 0:60d829a0353a 2967 #define LCD_WF8B_BPBLCD21_MASK 0x2u
tushki7 0:60d829a0353a 2968 #define LCD_WF8B_BPBLCD21_SHIFT 1
tushki7 0:60d829a0353a 2969 #define LCD_WF8B_BPBLCD6_MASK 0x2u
tushki7 0:60d829a0353a 2970 #define LCD_WF8B_BPBLCD6_SHIFT 1
tushki7 0:60d829a0353a 2971 #define LCD_WF8B_BPBLCD29_MASK 0x2u
tushki7 0:60d829a0353a 2972 #define LCD_WF8B_BPBLCD29_SHIFT 1
tushki7 0:60d829a0353a 2973 #define LCD_WF8B_BPBLCD25_MASK 0x2u
tushki7 0:60d829a0353a 2974 #define LCD_WF8B_BPBLCD25_SHIFT 1
tushki7 0:60d829a0353a 2975 #define LCD_WF8B_BPBLCD8_MASK 0x2u
tushki7 0:60d829a0353a 2976 #define LCD_WF8B_BPBLCD8_SHIFT 1
tushki7 0:60d829a0353a 2977 #define LCD_WF8B_BPBLCD54_MASK 0x2u
tushki7 0:60d829a0353a 2978 #define LCD_WF8B_BPBLCD54_SHIFT 1
tushki7 0:60d829a0353a 2979 #define LCD_WF8B_BPBLCD38_MASK 0x2u
tushki7 0:60d829a0353a 2980 #define LCD_WF8B_BPBLCD38_SHIFT 1
tushki7 0:60d829a0353a 2981 #define LCD_WF8B_BPBLCD43_MASK 0x2u
tushki7 0:60d829a0353a 2982 #define LCD_WF8B_BPBLCD43_SHIFT 1
tushki7 0:60d829a0353a 2983 #define LCD_WF8B_BPBLCD20_MASK 0x2u
tushki7 0:60d829a0353a 2984 #define LCD_WF8B_BPBLCD20_SHIFT 1
tushki7 0:60d829a0353a 2985 #define LCD_WF8B_BPBLCD9_MASK 0x2u
tushki7 0:60d829a0353a 2986 #define LCD_WF8B_BPBLCD9_SHIFT 1
tushki7 0:60d829a0353a 2987 #define LCD_WF8B_BPBLCD7_MASK 0x2u
tushki7 0:60d829a0353a 2988 #define LCD_WF8B_BPBLCD7_SHIFT 1
tushki7 0:60d829a0353a 2989 #define LCD_WF8B_BPBLCD50_MASK 0x2u
tushki7 0:60d829a0353a 2990 #define LCD_WF8B_BPBLCD50_SHIFT 1
tushki7 0:60d829a0353a 2991 #define LCD_WF8B_BPBLCD40_MASK 0x2u
tushki7 0:60d829a0353a 2992 #define LCD_WF8B_BPBLCD40_SHIFT 1
tushki7 0:60d829a0353a 2993 #define LCD_WF8B_BPBLCD63_MASK 0x2u
tushki7 0:60d829a0353a 2994 #define LCD_WF8B_BPBLCD63_SHIFT 1
tushki7 0:60d829a0353a 2995 #define LCD_WF8B_BPBLCD26_MASK 0x2u
tushki7 0:60d829a0353a 2996 #define LCD_WF8B_BPBLCD26_SHIFT 1
tushki7 0:60d829a0353a 2997 #define LCD_WF8B_BPBLCD12_MASK 0x2u
tushki7 0:60d829a0353a 2998 #define LCD_WF8B_BPBLCD12_SHIFT 1
tushki7 0:60d829a0353a 2999 #define LCD_WF8B_BPBLCD19_MASK 0x2u
tushki7 0:60d829a0353a 3000 #define LCD_WF8B_BPBLCD19_SHIFT 1
tushki7 0:60d829a0353a 3001 #define LCD_WF8B_BPBLCD34_MASK 0x2u
tushki7 0:60d829a0353a 3002 #define LCD_WF8B_BPBLCD34_SHIFT 1
tushki7 0:60d829a0353a 3003 #define LCD_WF8B_BPBLCD39_MASK 0x2u
tushki7 0:60d829a0353a 3004 #define LCD_WF8B_BPBLCD39_SHIFT 1
tushki7 0:60d829a0353a 3005 #define LCD_WF8B_BPBLCD59_MASK 0x2u
tushki7 0:60d829a0353a 3006 #define LCD_WF8B_BPBLCD59_SHIFT 1
tushki7 0:60d829a0353a 3007 #define LCD_WF8B_BPBLCD61_MASK 0x2u
tushki7 0:60d829a0353a 3008 #define LCD_WF8B_BPBLCD61_SHIFT 1
tushki7 0:60d829a0353a 3009 #define LCD_WF8B_BPBLCD37_MASK 0x2u
tushki7 0:60d829a0353a 3010 #define LCD_WF8B_BPBLCD37_SHIFT 1
tushki7 0:60d829a0353a 3011 #define LCD_WF8B_BPBLCD31_MASK 0x2u
tushki7 0:60d829a0353a 3012 #define LCD_WF8B_BPBLCD31_SHIFT 1
tushki7 0:60d829a0353a 3013 #define LCD_WF8B_BPBLCD58_MASK 0x2u
tushki7 0:60d829a0353a 3014 #define LCD_WF8B_BPBLCD58_SHIFT 1
tushki7 0:60d829a0353a 3015 #define LCD_WF8B_BPBLCD18_MASK 0x2u
tushki7 0:60d829a0353a 3016 #define LCD_WF8B_BPBLCD18_SHIFT 1
tushki7 0:60d829a0353a 3017 #define LCD_WF8B_BPBLCD45_MASK 0x2u
tushki7 0:60d829a0353a 3018 #define LCD_WF8B_BPBLCD45_SHIFT 1
tushki7 0:60d829a0353a 3019 #define LCD_WF8B_BPBLCD27_MASK 0x2u
tushki7 0:60d829a0353a 3020 #define LCD_WF8B_BPBLCD27_SHIFT 1
tushki7 0:60d829a0353a 3021 #define LCD_WF8B_BPBLCD14_MASK 0x2u
tushki7 0:60d829a0353a 3022 #define LCD_WF8B_BPBLCD14_SHIFT 1
tushki7 0:60d829a0353a 3023 #define LCD_WF8B_BPBLCD51_MASK 0x2u
tushki7 0:60d829a0353a 3024 #define LCD_WF8B_BPBLCD51_SHIFT 1
tushki7 0:60d829a0353a 3025 #define LCD_WF8B_BPBLCD52_MASK 0x2u
tushki7 0:60d829a0353a 3026 #define LCD_WF8B_BPBLCD52_SHIFT 1
tushki7 0:60d829a0353a 3027 #define LCD_WF8B_BPBLCD4_MASK 0x2u
tushki7 0:60d829a0353a 3028 #define LCD_WF8B_BPBLCD4_SHIFT 1
tushki7 0:60d829a0353a 3029 #define LCD_WF8B_BPBLCD35_MASK 0x2u
tushki7 0:60d829a0353a 3030 #define LCD_WF8B_BPBLCD35_SHIFT 1
tushki7 0:60d829a0353a 3031 #define LCD_WF8B_BPBLCD17_MASK 0x2u
tushki7 0:60d829a0353a 3032 #define LCD_WF8B_BPBLCD17_SHIFT 1
tushki7 0:60d829a0353a 3033 #define LCD_WF8B_BPBLCD41_MASK 0x2u
tushki7 0:60d829a0353a 3034 #define LCD_WF8B_BPBLCD41_SHIFT 1
tushki7 0:60d829a0353a 3035 #define LCD_WF8B_BPBLCD11_MASK 0x2u
tushki7 0:60d829a0353a 3036 #define LCD_WF8B_BPBLCD11_SHIFT 1
tushki7 0:60d829a0353a 3037 #define LCD_WF8B_BPBLCD46_MASK 0x2u
tushki7 0:60d829a0353a 3038 #define LCD_WF8B_BPBLCD46_SHIFT 1
tushki7 0:60d829a0353a 3039 #define LCD_WF8B_BPBLCD57_MASK 0x2u
tushki7 0:60d829a0353a 3040 #define LCD_WF8B_BPBLCD57_SHIFT 1
tushki7 0:60d829a0353a 3041 #define LCD_WF8B_BPBLCD42_MASK 0x2u
tushki7 0:60d829a0353a 3042 #define LCD_WF8B_BPBLCD42_SHIFT 1
tushki7 0:60d829a0353a 3043 #define LCD_WF8B_BPBLCD5_MASK 0x2u
tushki7 0:60d829a0353a 3044 #define LCD_WF8B_BPBLCD5_SHIFT 1
tushki7 0:60d829a0353a 3045 #define LCD_WF8B_BPBLCD3_MASK 0x2u
tushki7 0:60d829a0353a 3046 #define LCD_WF8B_BPBLCD3_SHIFT 1
tushki7 0:60d829a0353a 3047 #define LCD_WF8B_BPBLCD16_MASK 0x2u
tushki7 0:60d829a0353a 3048 #define LCD_WF8B_BPBLCD16_SHIFT 1
tushki7 0:60d829a0353a 3049 #define LCD_WF8B_BPBLCD13_MASK 0x2u
tushki7 0:60d829a0353a 3050 #define LCD_WF8B_BPBLCD13_SHIFT 1
tushki7 0:60d829a0353a 3051 #define LCD_WF8B_BPCLCD10_MASK 0x4u
tushki7 0:60d829a0353a 3052 #define LCD_WF8B_BPCLCD10_SHIFT 2
tushki7 0:60d829a0353a 3053 #define LCD_WF8B_BPCLCD55_MASK 0x4u
tushki7 0:60d829a0353a 3054 #define LCD_WF8B_BPCLCD55_SHIFT 2
tushki7 0:60d829a0353a 3055 #define LCD_WF8B_BPCLCD2_MASK 0x4u
tushki7 0:60d829a0353a 3056 #define LCD_WF8B_BPCLCD2_SHIFT 2
tushki7 0:60d829a0353a 3057 #define LCD_WF8B_BPCLCD23_MASK 0x4u
tushki7 0:60d829a0353a 3058 #define LCD_WF8B_BPCLCD23_SHIFT 2
tushki7 0:60d829a0353a 3059 #define LCD_WF8B_BPCLCD48_MASK 0x4u
tushki7 0:60d829a0353a 3060 #define LCD_WF8B_BPCLCD48_SHIFT 2
tushki7 0:60d829a0353a 3061 #define LCD_WF8B_BPCLCD24_MASK 0x4u
tushki7 0:60d829a0353a 3062 #define LCD_WF8B_BPCLCD24_SHIFT 2
tushki7 0:60d829a0353a 3063 #define LCD_WF8B_BPCLCD60_MASK 0x4u
tushki7 0:60d829a0353a 3064 #define LCD_WF8B_BPCLCD60_SHIFT 2
tushki7 0:60d829a0353a 3065 #define LCD_WF8B_BPCLCD47_MASK 0x4u
tushki7 0:60d829a0353a 3066 #define LCD_WF8B_BPCLCD47_SHIFT 2
tushki7 0:60d829a0353a 3067 #define LCD_WF8B_BPCLCD22_MASK 0x4u
tushki7 0:60d829a0353a 3068 #define LCD_WF8B_BPCLCD22_SHIFT 2
tushki7 0:60d829a0353a 3069 #define LCD_WF8B_BPCLCD8_MASK 0x4u
tushki7 0:60d829a0353a 3070 #define LCD_WF8B_BPCLCD8_SHIFT 2
tushki7 0:60d829a0353a 3071 #define LCD_WF8B_BPCLCD21_MASK 0x4u
tushki7 0:60d829a0353a 3072 #define LCD_WF8B_BPCLCD21_SHIFT 2
tushki7 0:60d829a0353a 3073 #define LCD_WF8B_BPCLCD49_MASK 0x4u
tushki7 0:60d829a0353a 3074 #define LCD_WF8B_BPCLCD49_SHIFT 2
tushki7 0:60d829a0353a 3075 #define LCD_WF8B_BPCLCD25_MASK 0x4u
tushki7 0:60d829a0353a 3076 #define LCD_WF8B_BPCLCD25_SHIFT 2
tushki7 0:60d829a0353a 3077 #define LCD_WF8B_BPCLCD1_MASK 0x4u
tushki7 0:60d829a0353a 3078 #define LCD_WF8B_BPCLCD1_SHIFT 2
tushki7 0:60d829a0353a 3079 #define LCD_WF8B_BPCLCD20_MASK 0x4u
tushki7 0:60d829a0353a 3080 #define LCD_WF8B_BPCLCD20_SHIFT 2
tushki7 0:60d829a0353a 3081 #define LCD_WF8B_BPCLCD50_MASK 0x4u
tushki7 0:60d829a0353a 3082 #define LCD_WF8B_BPCLCD50_SHIFT 2
tushki7 0:60d829a0353a 3083 #define LCD_WF8B_BPCLCD19_MASK 0x4u
tushki7 0:60d829a0353a 3084 #define LCD_WF8B_BPCLCD19_SHIFT 2
tushki7 0:60d829a0353a 3085 #define LCD_WF8B_BPCLCD26_MASK 0x4u
tushki7 0:60d829a0353a 3086 #define LCD_WF8B_BPCLCD26_SHIFT 2
tushki7 0:60d829a0353a 3087 #define LCD_WF8B_BPCLCD59_MASK 0x4u
tushki7 0:60d829a0353a 3088 #define LCD_WF8B_BPCLCD59_SHIFT 2
tushki7 0:60d829a0353a 3089 #define LCD_WF8B_BPCLCD61_MASK 0x4u
tushki7 0:60d829a0353a 3090 #define LCD_WF8B_BPCLCD61_SHIFT 2
tushki7 0:60d829a0353a 3091 #define LCD_WF8B_BPCLCD46_MASK 0x4u
tushki7 0:60d829a0353a 3092 #define LCD_WF8B_BPCLCD46_SHIFT 2
tushki7 0:60d829a0353a 3093 #define LCD_WF8B_BPCLCD18_MASK 0x4u
tushki7 0:60d829a0353a 3094 #define LCD_WF8B_BPCLCD18_SHIFT 2
tushki7 0:60d829a0353a 3095 #define LCD_WF8B_BPCLCD5_MASK 0x4u
tushki7 0:60d829a0353a 3096 #define LCD_WF8B_BPCLCD5_SHIFT 2
tushki7 0:60d829a0353a 3097 #define LCD_WF8B_BPCLCD63_MASK 0x4u
tushki7 0:60d829a0353a 3098 #define LCD_WF8B_BPCLCD63_SHIFT 2
tushki7 0:60d829a0353a 3099 #define LCD_WF8B_BPCLCD27_MASK 0x4u
tushki7 0:60d829a0353a 3100 #define LCD_WF8B_BPCLCD27_SHIFT 2
tushki7 0:60d829a0353a 3101 #define LCD_WF8B_BPCLCD17_MASK 0x4u
tushki7 0:60d829a0353a 3102 #define LCD_WF8B_BPCLCD17_SHIFT 2
tushki7 0:60d829a0353a 3103 #define LCD_WF8B_BPCLCD51_MASK 0x4u
tushki7 0:60d829a0353a 3104 #define LCD_WF8B_BPCLCD51_SHIFT 2
tushki7 0:60d829a0353a 3105 #define LCD_WF8B_BPCLCD9_MASK 0x4u
tushki7 0:60d829a0353a 3106 #define LCD_WF8B_BPCLCD9_SHIFT 2
tushki7 0:60d829a0353a 3107 #define LCD_WF8B_BPCLCD54_MASK 0x4u
tushki7 0:60d829a0353a 3108 #define LCD_WF8B_BPCLCD54_SHIFT 2
tushki7 0:60d829a0353a 3109 #define LCD_WF8B_BPCLCD15_MASK 0x4u
tushki7 0:60d829a0353a 3110 #define LCD_WF8B_BPCLCD15_SHIFT 2
tushki7 0:60d829a0353a 3111 #define LCD_WF8B_BPCLCD16_MASK 0x4u
tushki7 0:60d829a0353a 3112 #define LCD_WF8B_BPCLCD16_SHIFT 2
tushki7 0:60d829a0353a 3113 #define LCD_WF8B_BPCLCD14_MASK 0x4u
tushki7 0:60d829a0353a 3114 #define LCD_WF8B_BPCLCD14_SHIFT 2
tushki7 0:60d829a0353a 3115 #define LCD_WF8B_BPCLCD32_MASK 0x4u
tushki7 0:60d829a0353a 3116 #define LCD_WF8B_BPCLCD32_SHIFT 2
tushki7 0:60d829a0353a 3117 #define LCD_WF8B_BPCLCD28_MASK 0x4u
tushki7 0:60d829a0353a 3118 #define LCD_WF8B_BPCLCD28_SHIFT 2
tushki7 0:60d829a0353a 3119 #define LCD_WF8B_BPCLCD53_MASK 0x4u
tushki7 0:60d829a0353a 3120 #define LCD_WF8B_BPCLCD53_SHIFT 2
tushki7 0:60d829a0353a 3121 #define LCD_WF8B_BPCLCD33_MASK 0x4u
tushki7 0:60d829a0353a 3122 #define LCD_WF8B_BPCLCD33_SHIFT 2
tushki7 0:60d829a0353a 3123 #define LCD_WF8B_BPCLCD0_MASK 0x4u
tushki7 0:60d829a0353a 3124 #define LCD_WF8B_BPCLCD0_SHIFT 2
tushki7 0:60d829a0353a 3125 #define LCD_WF8B_BPCLCD43_MASK 0x4u
tushki7 0:60d829a0353a 3126 #define LCD_WF8B_BPCLCD43_SHIFT 2
tushki7 0:60d829a0353a 3127 #define LCD_WF8B_BPCLCD7_MASK 0x4u
tushki7 0:60d829a0353a 3128 #define LCD_WF8B_BPCLCD7_SHIFT 2
tushki7 0:60d829a0353a 3129 #define LCD_WF8B_BPCLCD4_MASK 0x4u
tushki7 0:60d829a0353a 3130 #define LCD_WF8B_BPCLCD4_SHIFT 2
tushki7 0:60d829a0353a 3131 #define LCD_WF8B_BPCLCD34_MASK 0x4u
tushki7 0:60d829a0353a 3132 #define LCD_WF8B_BPCLCD34_SHIFT 2
tushki7 0:60d829a0353a 3133 #define LCD_WF8B_BPCLCD29_MASK 0x4u
tushki7 0:60d829a0353a 3134 #define LCD_WF8B_BPCLCD29_SHIFT 2
tushki7 0:60d829a0353a 3135 #define LCD_WF8B_BPCLCD45_MASK 0x4u
tushki7 0:60d829a0353a 3136 #define LCD_WF8B_BPCLCD45_SHIFT 2
tushki7 0:60d829a0353a 3137 #define LCD_WF8B_BPCLCD57_MASK 0x4u
tushki7 0:60d829a0353a 3138 #define LCD_WF8B_BPCLCD57_SHIFT 2
tushki7 0:60d829a0353a 3139 #define LCD_WF8B_BPCLCD42_MASK 0x4u
tushki7 0:60d829a0353a 3140 #define LCD_WF8B_BPCLCD42_SHIFT 2
tushki7 0:60d829a0353a 3141 #define LCD_WF8B_BPCLCD35_MASK 0x4u
tushki7 0:60d829a0353a 3142 #define LCD_WF8B_BPCLCD35_SHIFT 2
tushki7 0:60d829a0353a 3143 #define LCD_WF8B_BPCLCD13_MASK 0x4u
tushki7 0:60d829a0353a 3144 #define LCD_WF8B_BPCLCD13_SHIFT 2
tushki7 0:60d829a0353a 3145 #define LCD_WF8B_BPCLCD36_MASK 0x4u
tushki7 0:60d829a0353a 3146 #define LCD_WF8B_BPCLCD36_SHIFT 2
tushki7 0:60d829a0353a 3147 #define LCD_WF8B_BPCLCD30_MASK 0x4u
tushki7 0:60d829a0353a 3148 #define LCD_WF8B_BPCLCD30_SHIFT 2
tushki7 0:60d829a0353a 3149 #define LCD_WF8B_BPCLCD52_MASK 0x4u
tushki7 0:60d829a0353a 3150 #define LCD_WF8B_BPCLCD52_SHIFT 2
tushki7 0:60d829a0353a 3151 #define LCD_WF8B_BPCLCD58_MASK 0x4u
tushki7 0:60d829a0353a 3152 #define LCD_WF8B_BPCLCD58_SHIFT 2
tushki7 0:60d829a0353a 3153 #define LCD_WF8B_BPCLCD41_MASK 0x4u
tushki7 0:60d829a0353a 3154 #define LCD_WF8B_BPCLCD41_SHIFT 2
tushki7 0:60d829a0353a 3155 #define LCD_WF8B_BPCLCD37_MASK 0x4u
tushki7 0:60d829a0353a 3156 #define LCD_WF8B_BPCLCD37_SHIFT 2
tushki7 0:60d829a0353a 3157 #define LCD_WF8B_BPCLCD3_MASK 0x4u
tushki7 0:60d829a0353a 3158 #define LCD_WF8B_BPCLCD3_SHIFT 2
tushki7 0:60d829a0353a 3159 #define LCD_WF8B_BPCLCD12_MASK 0x4u
tushki7 0:60d829a0353a 3160 #define LCD_WF8B_BPCLCD12_SHIFT 2
tushki7 0:60d829a0353a 3161 #define LCD_WF8B_BPCLCD11_MASK 0x4u
tushki7 0:60d829a0353a 3162 #define LCD_WF8B_BPCLCD11_SHIFT 2
tushki7 0:60d829a0353a 3163 #define LCD_WF8B_BPCLCD38_MASK 0x4u
tushki7 0:60d829a0353a 3164 #define LCD_WF8B_BPCLCD38_SHIFT 2
tushki7 0:60d829a0353a 3165 #define LCD_WF8B_BPCLCD44_MASK 0x4u
tushki7 0:60d829a0353a 3166 #define LCD_WF8B_BPCLCD44_SHIFT 2
tushki7 0:60d829a0353a 3167 #define LCD_WF8B_BPCLCD31_MASK 0x4u
tushki7 0:60d829a0353a 3168 #define LCD_WF8B_BPCLCD31_SHIFT 2
tushki7 0:60d829a0353a 3169 #define LCD_WF8B_BPCLCD40_MASK 0x4u
tushki7 0:60d829a0353a 3170 #define LCD_WF8B_BPCLCD40_SHIFT 2
tushki7 0:60d829a0353a 3171 #define LCD_WF8B_BPCLCD62_MASK 0x4u
tushki7 0:60d829a0353a 3172 #define LCD_WF8B_BPCLCD62_SHIFT 2
tushki7 0:60d829a0353a 3173 #define LCD_WF8B_BPCLCD56_MASK 0x4u
tushki7 0:60d829a0353a 3174 #define LCD_WF8B_BPCLCD56_SHIFT 2
tushki7 0:60d829a0353a 3175 #define LCD_WF8B_BPCLCD39_MASK 0x4u
tushki7 0:60d829a0353a 3176 #define LCD_WF8B_BPCLCD39_SHIFT 2
tushki7 0:60d829a0353a 3177 #define LCD_WF8B_BPCLCD6_MASK 0x4u
tushki7 0:60d829a0353a 3178 #define LCD_WF8B_BPCLCD6_SHIFT 2
tushki7 0:60d829a0353a 3179 #define LCD_WF8B_BPDLCD47_MASK 0x8u
tushki7 0:60d829a0353a 3180 #define LCD_WF8B_BPDLCD47_SHIFT 3
tushki7 0:60d829a0353a 3181 #define LCD_WF8B_BPDLCD23_MASK 0x8u
tushki7 0:60d829a0353a 3182 #define LCD_WF8B_BPDLCD23_SHIFT 3
tushki7 0:60d829a0353a 3183 #define LCD_WF8B_BPDLCD48_MASK 0x8u
tushki7 0:60d829a0353a 3184 #define LCD_WF8B_BPDLCD48_SHIFT 3
tushki7 0:60d829a0353a 3185 #define LCD_WF8B_BPDLCD24_MASK 0x8u
tushki7 0:60d829a0353a 3186 #define LCD_WF8B_BPDLCD24_SHIFT 3
tushki7 0:60d829a0353a 3187 #define LCD_WF8B_BPDLCD15_MASK 0x8u
tushki7 0:60d829a0353a 3188 #define LCD_WF8B_BPDLCD15_SHIFT 3
tushki7 0:60d829a0353a 3189 #define LCD_WF8B_BPDLCD22_MASK 0x8u
tushki7 0:60d829a0353a 3190 #define LCD_WF8B_BPDLCD22_SHIFT 3
tushki7 0:60d829a0353a 3191 #define LCD_WF8B_BPDLCD60_MASK 0x8u
tushki7 0:60d829a0353a 3192 #define LCD_WF8B_BPDLCD60_SHIFT 3
tushki7 0:60d829a0353a 3193 #define LCD_WF8B_BPDLCD10_MASK 0x8u
tushki7 0:60d829a0353a 3194 #define LCD_WF8B_BPDLCD10_SHIFT 3
tushki7 0:60d829a0353a 3195 #define LCD_WF8B_BPDLCD21_MASK 0x8u
tushki7 0:60d829a0353a 3196 #define LCD_WF8B_BPDLCD21_SHIFT 3
tushki7 0:60d829a0353a 3197 #define LCD_WF8B_BPDLCD49_MASK 0x8u
tushki7 0:60d829a0353a 3198 #define LCD_WF8B_BPDLCD49_SHIFT 3
tushki7 0:60d829a0353a 3199 #define LCD_WF8B_BPDLCD1_MASK 0x8u
tushki7 0:60d829a0353a 3200 #define LCD_WF8B_BPDLCD1_SHIFT 3
tushki7 0:60d829a0353a 3201 #define LCD_WF8B_BPDLCD25_MASK 0x8u
tushki7 0:60d829a0353a 3202 #define LCD_WF8B_BPDLCD25_SHIFT 3
tushki7 0:60d829a0353a 3203 #define LCD_WF8B_BPDLCD20_MASK 0x8u
tushki7 0:60d829a0353a 3204 #define LCD_WF8B_BPDLCD20_SHIFT 3
tushki7 0:60d829a0353a 3205 #define LCD_WF8B_BPDLCD2_MASK 0x8u
tushki7 0:60d829a0353a 3206 #define LCD_WF8B_BPDLCD2_SHIFT 3
tushki7 0:60d829a0353a 3207 #define LCD_WF8B_BPDLCD55_MASK 0x8u
tushki7 0:60d829a0353a 3208 #define LCD_WF8B_BPDLCD55_SHIFT 3
tushki7 0:60d829a0353a 3209 #define LCD_WF8B_BPDLCD59_MASK 0x8u
tushki7 0:60d829a0353a 3210 #define LCD_WF8B_BPDLCD59_SHIFT 3
tushki7 0:60d829a0353a 3211 #define LCD_WF8B_BPDLCD5_MASK 0x8u
tushki7 0:60d829a0353a 3212 #define LCD_WF8B_BPDLCD5_SHIFT 3
tushki7 0:60d829a0353a 3213 #define LCD_WF8B_BPDLCD19_MASK 0x8u
tushki7 0:60d829a0353a 3214 #define LCD_WF8B_BPDLCD19_SHIFT 3
tushki7 0:60d829a0353a 3215 #define LCD_WF8B_BPDLCD6_MASK 0x8u
tushki7 0:60d829a0353a 3216 #define LCD_WF8B_BPDLCD6_SHIFT 3
tushki7 0:60d829a0353a 3217 #define LCD_WF8B_BPDLCD26_MASK 0x8u
tushki7 0:60d829a0353a 3218 #define LCD_WF8B_BPDLCD26_SHIFT 3
tushki7 0:60d829a0353a 3219 #define LCD_WF8B_BPDLCD0_MASK 0x8u
tushki7 0:60d829a0353a 3220 #define LCD_WF8B_BPDLCD0_SHIFT 3
tushki7 0:60d829a0353a 3221 #define LCD_WF8B_BPDLCD50_MASK 0x8u
tushki7 0:60d829a0353a 3222 #define LCD_WF8B_BPDLCD50_SHIFT 3
tushki7 0:60d829a0353a 3223 #define LCD_WF8B_BPDLCD46_MASK 0x8u
tushki7 0:60d829a0353a 3224 #define LCD_WF8B_BPDLCD46_SHIFT 3
tushki7 0:60d829a0353a 3225 #define LCD_WF8B_BPDLCD18_MASK 0x8u
tushki7 0:60d829a0353a 3226 #define LCD_WF8B_BPDLCD18_SHIFT 3
tushki7 0:60d829a0353a 3227 #define LCD_WF8B_BPDLCD61_MASK 0x8u
tushki7 0:60d829a0353a 3228 #define LCD_WF8B_BPDLCD61_SHIFT 3
tushki7 0:60d829a0353a 3229 #define LCD_WF8B_BPDLCD9_MASK 0x8u
tushki7 0:60d829a0353a 3230 #define LCD_WF8B_BPDLCD9_SHIFT 3
tushki7 0:60d829a0353a 3231 #define LCD_WF8B_BPDLCD17_MASK 0x8u
tushki7 0:60d829a0353a 3232 #define LCD_WF8B_BPDLCD17_SHIFT 3
tushki7 0:60d829a0353a 3233 #define LCD_WF8B_BPDLCD27_MASK 0x8u
tushki7 0:60d829a0353a 3234 #define LCD_WF8B_BPDLCD27_SHIFT 3
tushki7 0:60d829a0353a 3235 #define LCD_WF8B_BPDLCD53_MASK 0x8u
tushki7 0:60d829a0353a 3236 #define LCD_WF8B_BPDLCD53_SHIFT 3
tushki7 0:60d829a0353a 3237 #define LCD_WF8B_BPDLCD51_MASK 0x8u
tushki7 0:60d829a0353a 3238 #define LCD_WF8B_BPDLCD51_SHIFT 3
tushki7 0:60d829a0353a 3239 #define LCD_WF8B_BPDLCD54_MASK 0x8u
tushki7 0:60d829a0353a 3240 #define LCD_WF8B_BPDLCD54_SHIFT 3
tushki7 0:60d829a0353a 3241 #define LCD_WF8B_BPDLCD13_MASK 0x8u
tushki7 0:60d829a0353a 3242 #define LCD_WF8B_BPDLCD13_SHIFT 3
tushki7 0:60d829a0353a 3243 #define LCD_WF8B_BPDLCD16_MASK 0x8u
tushki7 0:60d829a0353a 3244 #define LCD_WF8B_BPDLCD16_SHIFT 3
tushki7 0:60d829a0353a 3245 #define LCD_WF8B_BPDLCD32_MASK 0x8u
tushki7 0:60d829a0353a 3246 #define LCD_WF8B_BPDLCD32_SHIFT 3
tushki7 0:60d829a0353a 3247 #define LCD_WF8B_BPDLCD14_MASK 0x8u
tushki7 0:60d829a0353a 3248 #define LCD_WF8B_BPDLCD14_SHIFT 3
tushki7 0:60d829a0353a 3249 #define LCD_WF8B_BPDLCD28_MASK 0x8u
tushki7 0:60d829a0353a 3250 #define LCD_WF8B_BPDLCD28_SHIFT 3
tushki7 0:60d829a0353a 3251 #define LCD_WF8B_BPDLCD43_MASK 0x8u
tushki7 0:60d829a0353a 3252 #define LCD_WF8B_BPDLCD43_SHIFT 3
tushki7 0:60d829a0353a 3253 #define LCD_WF8B_BPDLCD4_MASK 0x8u
tushki7 0:60d829a0353a 3254 #define LCD_WF8B_BPDLCD4_SHIFT 3
tushki7 0:60d829a0353a 3255 #define LCD_WF8B_BPDLCD45_MASK 0x8u
tushki7 0:60d829a0353a 3256 #define LCD_WF8B_BPDLCD45_SHIFT 3
tushki7 0:60d829a0353a 3257 #define LCD_WF8B_BPDLCD8_MASK 0x8u
tushki7 0:60d829a0353a 3258 #define LCD_WF8B_BPDLCD8_SHIFT 3
tushki7 0:60d829a0353a 3259 #define LCD_WF8B_BPDLCD62_MASK 0x8u
tushki7 0:60d829a0353a 3260 #define LCD_WF8B_BPDLCD62_SHIFT 3
tushki7 0:60d829a0353a 3261 #define LCD_WF8B_BPDLCD33_MASK 0x8u
tushki7 0:60d829a0353a 3262 #define LCD_WF8B_BPDLCD33_SHIFT 3
tushki7 0:60d829a0353a 3263 #define LCD_WF8B_BPDLCD34_MASK 0x8u
tushki7 0:60d829a0353a 3264 #define LCD_WF8B_BPDLCD34_SHIFT 3
tushki7 0:60d829a0353a 3265 #define LCD_WF8B_BPDLCD29_MASK 0x8u
tushki7 0:60d829a0353a 3266 #define LCD_WF8B_BPDLCD29_SHIFT 3
tushki7 0:60d829a0353a 3267 #define LCD_WF8B_BPDLCD58_MASK 0x8u
tushki7 0:60d829a0353a 3268 #define LCD_WF8B_BPDLCD58_SHIFT 3
tushki7 0:60d829a0353a 3269 #define LCD_WF8B_BPDLCD57_MASK 0x8u
tushki7 0:60d829a0353a 3270 #define LCD_WF8B_BPDLCD57_SHIFT 3
tushki7 0:60d829a0353a 3271 #define LCD_WF8B_BPDLCD42_MASK 0x8u
tushki7 0:60d829a0353a 3272 #define LCD_WF8B_BPDLCD42_SHIFT 3
tushki7 0:60d829a0353a 3273 #define LCD_WF8B_BPDLCD35_MASK 0x8u
tushki7 0:60d829a0353a 3274 #define LCD_WF8B_BPDLCD35_SHIFT 3
tushki7 0:60d829a0353a 3275 #define LCD_WF8B_BPDLCD52_MASK 0x8u
tushki7 0:60d829a0353a 3276 #define LCD_WF8B_BPDLCD52_SHIFT 3
tushki7 0:60d829a0353a 3277 #define LCD_WF8B_BPDLCD7_MASK 0x8u
tushki7 0:60d829a0353a 3278 #define LCD_WF8B_BPDLCD7_SHIFT 3
tushki7 0:60d829a0353a 3279 #define LCD_WF8B_BPDLCD36_MASK 0x8u
tushki7 0:60d829a0353a 3280 #define LCD_WF8B_BPDLCD36_SHIFT 3
tushki7 0:60d829a0353a 3281 #define LCD_WF8B_BPDLCD30_MASK 0x8u
tushki7 0:60d829a0353a 3282 #define LCD_WF8B_BPDLCD30_SHIFT 3
tushki7 0:60d829a0353a 3283 #define LCD_WF8B_BPDLCD41_MASK 0x8u
tushki7 0:60d829a0353a 3284 #define LCD_WF8B_BPDLCD41_SHIFT 3
tushki7 0:60d829a0353a 3285 #define LCD_WF8B_BPDLCD37_MASK 0x8u
tushki7 0:60d829a0353a 3286 #define LCD_WF8B_BPDLCD37_SHIFT 3
tushki7 0:60d829a0353a 3287 #define LCD_WF8B_BPDLCD44_MASK 0x8u
tushki7 0:60d829a0353a 3288 #define LCD_WF8B_BPDLCD44_SHIFT 3
tushki7 0:60d829a0353a 3289 #define LCD_WF8B_BPDLCD63_MASK 0x8u
tushki7 0:60d829a0353a 3290 #define LCD_WF8B_BPDLCD63_SHIFT 3
tushki7 0:60d829a0353a 3291 #define LCD_WF8B_BPDLCD38_MASK 0x8u
tushki7 0:60d829a0353a 3292 #define LCD_WF8B_BPDLCD38_SHIFT 3
tushki7 0:60d829a0353a 3293 #define LCD_WF8B_BPDLCD56_MASK 0x8u
tushki7 0:60d829a0353a 3294 #define LCD_WF8B_BPDLCD56_SHIFT 3
tushki7 0:60d829a0353a 3295 #define LCD_WF8B_BPDLCD40_MASK 0x8u
tushki7 0:60d829a0353a 3296 #define LCD_WF8B_BPDLCD40_SHIFT 3
tushki7 0:60d829a0353a 3297 #define LCD_WF8B_BPDLCD31_MASK 0x8u
tushki7 0:60d829a0353a 3298 #define LCD_WF8B_BPDLCD31_SHIFT 3
tushki7 0:60d829a0353a 3299 #define LCD_WF8B_BPDLCD12_MASK 0x8u
tushki7 0:60d829a0353a 3300 #define LCD_WF8B_BPDLCD12_SHIFT 3
tushki7 0:60d829a0353a 3301 #define LCD_WF8B_BPDLCD39_MASK 0x8u
tushki7 0:60d829a0353a 3302 #define LCD_WF8B_BPDLCD39_SHIFT 3
tushki7 0:60d829a0353a 3303 #define LCD_WF8B_BPDLCD3_MASK 0x8u
tushki7 0:60d829a0353a 3304 #define LCD_WF8B_BPDLCD3_SHIFT 3
tushki7 0:60d829a0353a 3305 #define LCD_WF8B_BPDLCD11_MASK 0x8u
tushki7 0:60d829a0353a 3306 #define LCD_WF8B_BPDLCD11_SHIFT 3
tushki7 0:60d829a0353a 3307 #define LCD_WF8B_BPELCD12_MASK 0x10u
tushki7 0:60d829a0353a 3308 #define LCD_WF8B_BPELCD12_SHIFT 4
tushki7 0:60d829a0353a 3309 #define LCD_WF8B_BPELCD39_MASK 0x10u
tushki7 0:60d829a0353a 3310 #define LCD_WF8B_BPELCD39_SHIFT 4
tushki7 0:60d829a0353a 3311 #define LCD_WF8B_BPELCD3_MASK 0x10u
tushki7 0:60d829a0353a 3312 #define LCD_WF8B_BPELCD3_SHIFT 4
tushki7 0:60d829a0353a 3313 #define LCD_WF8B_BPELCD38_MASK 0x10u
tushki7 0:60d829a0353a 3314 #define LCD_WF8B_BPELCD38_SHIFT 4
tushki7 0:60d829a0353a 3315 #define LCD_WF8B_BPELCD40_MASK 0x10u
tushki7 0:60d829a0353a 3316 #define LCD_WF8B_BPELCD40_SHIFT 4
tushki7 0:60d829a0353a 3317 #define LCD_WF8B_BPELCD37_MASK 0x10u
tushki7 0:60d829a0353a 3318 #define LCD_WF8B_BPELCD37_SHIFT 4
tushki7 0:60d829a0353a 3319 #define LCD_WF8B_BPELCD41_MASK 0x10u
tushki7 0:60d829a0353a 3320 #define LCD_WF8B_BPELCD41_SHIFT 4
tushki7 0:60d829a0353a 3321 #define LCD_WF8B_BPELCD36_MASK 0x10u
tushki7 0:60d829a0353a 3322 #define LCD_WF8B_BPELCD36_SHIFT 4
tushki7 0:60d829a0353a 3323 #define LCD_WF8B_BPELCD8_MASK 0x10u
tushki7 0:60d829a0353a 3324 #define LCD_WF8B_BPELCD8_SHIFT 4
tushki7 0:60d829a0353a 3325 #define LCD_WF8B_BPELCD35_MASK 0x10u
tushki7 0:60d829a0353a 3326 #define LCD_WF8B_BPELCD35_SHIFT 4
tushki7 0:60d829a0353a 3327 #define LCD_WF8B_BPELCD42_MASK 0x10u
tushki7 0:60d829a0353a 3328 #define LCD_WF8B_BPELCD42_SHIFT 4
tushki7 0:60d829a0353a 3329 #define LCD_WF8B_BPELCD34_MASK 0x10u
tushki7 0:60d829a0353a 3330 #define LCD_WF8B_BPELCD34_SHIFT 4
tushki7 0:60d829a0353a 3331 #define LCD_WF8B_BPELCD33_MASK 0x10u
tushki7 0:60d829a0353a 3332 #define LCD_WF8B_BPELCD33_SHIFT 4
tushki7 0:60d829a0353a 3333 #define LCD_WF8B_BPELCD11_MASK 0x10u
tushki7 0:60d829a0353a 3334 #define LCD_WF8B_BPELCD11_SHIFT 4
tushki7 0:60d829a0353a 3335 #define LCD_WF8B_BPELCD43_MASK 0x10u
tushki7 0:60d829a0353a 3336 #define LCD_WF8B_BPELCD43_SHIFT 4
tushki7 0:60d829a0353a 3337 #define LCD_WF8B_BPELCD32_MASK 0x10u
tushki7 0:60d829a0353a 3338 #define LCD_WF8B_BPELCD32_SHIFT 4
tushki7 0:60d829a0353a 3339 #define LCD_WF8B_BPELCD31_MASK 0x10u
tushki7 0:60d829a0353a 3340 #define LCD_WF8B_BPELCD31_SHIFT 4
tushki7 0:60d829a0353a 3341 #define LCD_WF8B_BPELCD44_MASK 0x10u
tushki7 0:60d829a0353a 3342 #define LCD_WF8B_BPELCD44_SHIFT 4
tushki7 0:60d829a0353a 3343 #define LCD_WF8B_BPELCD30_MASK 0x10u
tushki7 0:60d829a0353a 3344 #define LCD_WF8B_BPELCD30_SHIFT 4
tushki7 0:60d829a0353a 3345 #define LCD_WF8B_BPELCD29_MASK 0x10u
tushki7 0:60d829a0353a 3346 #define LCD_WF8B_BPELCD29_SHIFT 4
tushki7 0:60d829a0353a 3347 #define LCD_WF8B_BPELCD7_MASK 0x10u
tushki7 0:60d829a0353a 3348 #define LCD_WF8B_BPELCD7_SHIFT 4
tushki7 0:60d829a0353a 3349 #define LCD_WF8B_BPELCD45_MASK 0x10u
tushki7 0:60d829a0353a 3350 #define LCD_WF8B_BPELCD45_SHIFT 4
tushki7 0:60d829a0353a 3351 #define LCD_WF8B_BPELCD28_MASK 0x10u
tushki7 0:60d829a0353a 3352 #define LCD_WF8B_BPELCD28_SHIFT 4
tushki7 0:60d829a0353a 3353 #define LCD_WF8B_BPELCD2_MASK 0x10u
tushki7 0:60d829a0353a 3354 #define LCD_WF8B_BPELCD2_SHIFT 4
tushki7 0:60d829a0353a 3355 #define LCD_WF8B_BPELCD27_MASK 0x10u
tushki7 0:60d829a0353a 3356 #define LCD_WF8B_BPELCD27_SHIFT 4
tushki7 0:60d829a0353a 3357 #define LCD_WF8B_BPELCD46_MASK 0x10u
tushki7 0:60d829a0353a 3358 #define LCD_WF8B_BPELCD46_SHIFT 4
tushki7 0:60d829a0353a 3359 #define LCD_WF8B_BPELCD26_MASK 0x10u
tushki7 0:60d829a0353a 3360 #define LCD_WF8B_BPELCD26_SHIFT 4
tushki7 0:60d829a0353a 3361 #define LCD_WF8B_BPELCD10_MASK 0x10u
tushki7 0:60d829a0353a 3362 #define LCD_WF8B_BPELCD10_SHIFT 4
tushki7 0:60d829a0353a 3363 #define LCD_WF8B_BPELCD13_MASK 0x10u
tushki7 0:60d829a0353a 3364 #define LCD_WF8B_BPELCD13_SHIFT 4
tushki7 0:60d829a0353a 3365 #define LCD_WF8B_BPELCD25_MASK 0x10u
tushki7 0:60d829a0353a 3366 #define LCD_WF8B_BPELCD25_SHIFT 4
tushki7 0:60d829a0353a 3367 #define LCD_WF8B_BPELCD5_MASK 0x10u
tushki7 0:60d829a0353a 3368 #define LCD_WF8B_BPELCD5_SHIFT 4
tushki7 0:60d829a0353a 3369 #define LCD_WF8B_BPELCD24_MASK 0x10u
tushki7 0:60d829a0353a 3370 #define LCD_WF8B_BPELCD24_SHIFT 4
tushki7 0:60d829a0353a 3371 #define LCD_WF8B_BPELCD47_MASK 0x10u
tushki7 0:60d829a0353a 3372 #define LCD_WF8B_BPELCD47_SHIFT 4
tushki7 0:60d829a0353a 3373 #define LCD_WF8B_BPELCD23_MASK 0x10u
tushki7 0:60d829a0353a 3374 #define LCD_WF8B_BPELCD23_SHIFT 4
tushki7 0:60d829a0353a 3375 #define LCD_WF8B_BPELCD22_MASK 0x10u
tushki7 0:60d829a0353a 3376 #define LCD_WF8B_BPELCD22_SHIFT 4
tushki7 0:60d829a0353a 3377 #define LCD_WF8B_BPELCD48_MASK 0x10u
tushki7 0:60d829a0353a 3378 #define LCD_WF8B_BPELCD48_SHIFT 4
tushki7 0:60d829a0353a 3379 #define LCD_WF8B_BPELCD21_MASK 0x10u
tushki7 0:60d829a0353a 3380 #define LCD_WF8B_BPELCD21_SHIFT 4
tushki7 0:60d829a0353a 3381 #define LCD_WF8B_BPELCD49_MASK 0x10u
tushki7 0:60d829a0353a 3382 #define LCD_WF8B_BPELCD49_SHIFT 4
tushki7 0:60d829a0353a 3383 #define LCD_WF8B_BPELCD20_MASK 0x10u
tushki7 0:60d829a0353a 3384 #define LCD_WF8B_BPELCD20_SHIFT 4
tushki7 0:60d829a0353a 3385 #define LCD_WF8B_BPELCD19_MASK 0x10u
tushki7 0:60d829a0353a 3386 #define LCD_WF8B_BPELCD19_SHIFT 4
tushki7 0:60d829a0353a 3387 #define LCD_WF8B_BPELCD9_MASK 0x10u
tushki7 0:60d829a0353a 3388 #define LCD_WF8B_BPELCD9_SHIFT 4
tushki7 0:60d829a0353a 3389 #define LCD_WF8B_BPELCD50_MASK 0x10u
tushki7 0:60d829a0353a 3390 #define LCD_WF8B_BPELCD50_SHIFT 4
tushki7 0:60d829a0353a 3391 #define LCD_WF8B_BPELCD18_MASK 0x10u
tushki7 0:60d829a0353a 3392 #define LCD_WF8B_BPELCD18_SHIFT 4
tushki7 0:60d829a0353a 3393 #define LCD_WF8B_BPELCD6_MASK 0x10u
tushki7 0:60d829a0353a 3394 #define LCD_WF8B_BPELCD6_SHIFT 4
tushki7 0:60d829a0353a 3395 #define LCD_WF8B_BPELCD17_MASK 0x10u
tushki7 0:60d829a0353a 3396 #define LCD_WF8B_BPELCD17_SHIFT 4
tushki7 0:60d829a0353a 3397 #define LCD_WF8B_BPELCD51_MASK 0x10u
tushki7 0:60d829a0353a 3398 #define LCD_WF8B_BPELCD51_SHIFT 4
tushki7 0:60d829a0353a 3399 #define LCD_WF8B_BPELCD16_MASK 0x10u
tushki7 0:60d829a0353a 3400 #define LCD_WF8B_BPELCD16_SHIFT 4
tushki7 0:60d829a0353a 3401 #define LCD_WF8B_BPELCD56_MASK 0x10u
tushki7 0:60d829a0353a 3402 #define LCD_WF8B_BPELCD56_SHIFT 4
tushki7 0:60d829a0353a 3403 #define LCD_WF8B_BPELCD57_MASK 0x10u
tushki7 0:60d829a0353a 3404 #define LCD_WF8B_BPELCD57_SHIFT 4
tushki7 0:60d829a0353a 3405 #define LCD_WF8B_BPELCD52_MASK 0x10u
tushki7 0:60d829a0353a 3406 #define LCD_WF8B_BPELCD52_SHIFT 4
tushki7 0:60d829a0353a 3407 #define LCD_WF8B_BPELCD1_MASK 0x10u
tushki7 0:60d829a0353a 3408 #define LCD_WF8B_BPELCD1_SHIFT 4
tushki7 0:60d829a0353a 3409 #define LCD_WF8B_BPELCD58_MASK 0x10u
tushki7 0:60d829a0353a 3410 #define LCD_WF8B_BPELCD58_SHIFT 4
tushki7 0:60d829a0353a 3411 #define LCD_WF8B_BPELCD59_MASK 0x10u
tushki7 0:60d829a0353a 3412 #define LCD_WF8B_BPELCD59_SHIFT 4
tushki7 0:60d829a0353a 3413 #define LCD_WF8B_BPELCD53_MASK 0x10u
tushki7 0:60d829a0353a 3414 #define LCD_WF8B_BPELCD53_SHIFT 4
tushki7 0:60d829a0353a 3415 #define LCD_WF8B_BPELCD14_MASK 0x10u
tushki7 0:60d829a0353a 3416 #define LCD_WF8B_BPELCD14_SHIFT 4
tushki7 0:60d829a0353a 3417 #define LCD_WF8B_BPELCD0_MASK 0x10u
tushki7 0:60d829a0353a 3418 #define LCD_WF8B_BPELCD0_SHIFT 4
tushki7 0:60d829a0353a 3419 #define LCD_WF8B_BPELCD60_MASK 0x10u
tushki7 0:60d829a0353a 3420 #define LCD_WF8B_BPELCD60_SHIFT 4
tushki7 0:60d829a0353a 3421 #define LCD_WF8B_BPELCD15_MASK 0x10u
tushki7 0:60d829a0353a 3422 #define LCD_WF8B_BPELCD15_SHIFT 4
tushki7 0:60d829a0353a 3423 #define LCD_WF8B_BPELCD61_MASK 0x10u
tushki7 0:60d829a0353a 3424 #define LCD_WF8B_BPELCD61_SHIFT 4
tushki7 0:60d829a0353a 3425 #define LCD_WF8B_BPELCD54_MASK 0x10u
tushki7 0:60d829a0353a 3426 #define LCD_WF8B_BPELCD54_SHIFT 4
tushki7 0:60d829a0353a 3427 #define LCD_WF8B_BPELCD62_MASK 0x10u
tushki7 0:60d829a0353a 3428 #define LCD_WF8B_BPELCD62_SHIFT 4
tushki7 0:60d829a0353a 3429 #define LCD_WF8B_BPELCD63_MASK 0x10u
tushki7 0:60d829a0353a 3430 #define LCD_WF8B_BPELCD63_SHIFT 4
tushki7 0:60d829a0353a 3431 #define LCD_WF8B_BPELCD55_MASK 0x10u
tushki7 0:60d829a0353a 3432 #define LCD_WF8B_BPELCD55_SHIFT 4
tushki7 0:60d829a0353a 3433 #define LCD_WF8B_BPELCD4_MASK 0x10u
tushki7 0:60d829a0353a 3434 #define LCD_WF8B_BPELCD4_SHIFT 4
tushki7 0:60d829a0353a 3435 #define LCD_WF8B_BPFLCD13_MASK 0x20u
tushki7 0:60d829a0353a 3436 #define LCD_WF8B_BPFLCD13_SHIFT 5
tushki7 0:60d829a0353a 3437 #define LCD_WF8B_BPFLCD39_MASK 0x20u
tushki7 0:60d829a0353a 3438 #define LCD_WF8B_BPFLCD39_SHIFT 5
tushki7 0:60d829a0353a 3439 #define LCD_WF8B_BPFLCD55_MASK 0x20u
tushki7 0:60d829a0353a 3440 #define LCD_WF8B_BPFLCD55_SHIFT 5
tushki7 0:60d829a0353a 3441 #define LCD_WF8B_BPFLCD47_MASK 0x20u
tushki7 0:60d829a0353a 3442 #define LCD_WF8B_BPFLCD47_SHIFT 5
tushki7 0:60d829a0353a 3443 #define LCD_WF8B_BPFLCD63_MASK 0x20u
tushki7 0:60d829a0353a 3444 #define LCD_WF8B_BPFLCD63_SHIFT 5
tushki7 0:60d829a0353a 3445 #define LCD_WF8B_BPFLCD43_MASK 0x20u
tushki7 0:60d829a0353a 3446 #define LCD_WF8B_BPFLCD43_SHIFT 5
tushki7 0:60d829a0353a 3447 #define LCD_WF8B_BPFLCD5_MASK 0x20u
tushki7 0:60d829a0353a 3448 #define LCD_WF8B_BPFLCD5_SHIFT 5
tushki7 0:60d829a0353a 3449 #define LCD_WF8B_BPFLCD62_MASK 0x20u
tushki7 0:60d829a0353a 3450 #define LCD_WF8B_BPFLCD62_SHIFT 5
tushki7 0:60d829a0353a 3451 #define LCD_WF8B_BPFLCD14_MASK 0x20u
tushki7 0:60d829a0353a 3452 #define LCD_WF8B_BPFLCD14_SHIFT 5
tushki7 0:60d829a0353a 3453 #define LCD_WF8B_BPFLCD24_MASK 0x20u
tushki7 0:60d829a0353a 3454 #define LCD_WF8B_BPFLCD24_SHIFT 5
tushki7 0:60d829a0353a 3455 #define LCD_WF8B_BPFLCD54_MASK 0x20u
tushki7 0:60d829a0353a 3456 #define LCD_WF8B_BPFLCD54_SHIFT 5
tushki7 0:60d829a0353a 3457 #define LCD_WF8B_BPFLCD15_MASK 0x20u
tushki7 0:60d829a0353a 3458 #define LCD_WF8B_BPFLCD15_SHIFT 5
tushki7 0:60d829a0353a 3459 #define LCD_WF8B_BPFLCD32_MASK 0x20u
tushki7 0:60d829a0353a 3460 #define LCD_WF8B_BPFLCD32_SHIFT 5
tushki7 0:60d829a0353a 3461 #define LCD_WF8B_BPFLCD61_MASK 0x20u
tushki7 0:60d829a0353a 3462 #define LCD_WF8B_BPFLCD61_SHIFT 5
tushki7 0:60d829a0353a 3463 #define LCD_WF8B_BPFLCD25_MASK 0x20u
tushki7 0:60d829a0353a 3464 #define LCD_WF8B_BPFLCD25_SHIFT 5
tushki7 0:60d829a0353a 3465 #define LCD_WF8B_BPFLCD60_MASK 0x20u
tushki7 0:60d829a0353a 3466 #define LCD_WF8B_BPFLCD60_SHIFT 5
tushki7 0:60d829a0353a 3467 #define LCD_WF8B_BPFLCD41_MASK 0x20u
tushki7 0:60d829a0353a 3468 #define LCD_WF8B_BPFLCD41_SHIFT 5
tushki7 0:60d829a0353a 3469 #define LCD_WF8B_BPFLCD33_MASK 0x20u
tushki7 0:60d829a0353a 3470 #define LCD_WF8B_BPFLCD33_SHIFT 5
tushki7 0:60d829a0353a 3471 #define LCD_WF8B_BPFLCD53_MASK 0x20u
tushki7 0:60d829a0353a 3472 #define LCD_WF8B_BPFLCD53_SHIFT 5
tushki7 0:60d829a0353a 3473 #define LCD_WF8B_BPFLCD59_MASK 0x20u
tushki7 0:60d829a0353a 3474 #define LCD_WF8B_BPFLCD59_SHIFT 5
tushki7 0:60d829a0353a 3475 #define LCD_WF8B_BPFLCD0_MASK 0x20u
tushki7 0:60d829a0353a 3476 #define LCD_WF8B_BPFLCD0_SHIFT 5
tushki7 0:60d829a0353a 3477 #define LCD_WF8B_BPFLCD46_MASK 0x20u
tushki7 0:60d829a0353a 3478 #define LCD_WF8B_BPFLCD46_SHIFT 5
tushki7 0:60d829a0353a 3479 #define LCD_WF8B_BPFLCD58_MASK 0x20u
tushki7 0:60d829a0353a 3480 #define LCD_WF8B_BPFLCD58_SHIFT 5
tushki7 0:60d829a0353a 3481 #define LCD_WF8B_BPFLCD26_MASK 0x20u
tushki7 0:60d829a0353a 3482 #define LCD_WF8B_BPFLCD26_SHIFT 5
tushki7 0:60d829a0353a 3483 #define LCD_WF8B_BPFLCD36_MASK 0x20u
tushki7 0:60d829a0353a 3484 #define LCD_WF8B_BPFLCD36_SHIFT 5
tushki7 0:60d829a0353a 3485 #define LCD_WF8B_BPFLCD10_MASK 0x20u
tushki7 0:60d829a0353a 3486 #define LCD_WF8B_BPFLCD10_SHIFT 5
tushki7 0:60d829a0353a 3487 #define LCD_WF8B_BPFLCD52_MASK 0x20u
tushki7 0:60d829a0353a 3488 #define LCD_WF8B_BPFLCD52_SHIFT 5
tushki7 0:60d829a0353a 3489 #define LCD_WF8B_BPFLCD57_MASK 0x20u
tushki7 0:60d829a0353a 3490 #define LCD_WF8B_BPFLCD57_SHIFT 5
tushki7 0:60d829a0353a 3491 #define LCD_WF8B_BPFLCD27_MASK 0x20u
tushki7 0:60d829a0353a 3492 #define LCD_WF8B_BPFLCD27_SHIFT 5
tushki7 0:60d829a0353a 3493 #define LCD_WF8B_BPFLCD11_MASK 0x20u
tushki7 0:60d829a0353a 3494 #define LCD_WF8B_BPFLCD11_SHIFT 5
tushki7 0:60d829a0353a 3495 #define LCD_WF8B_BPFLCD56_MASK 0x20u
tushki7 0:60d829a0353a 3496 #define LCD_WF8B_BPFLCD56_SHIFT 5
tushki7 0:60d829a0353a 3497 #define LCD_WF8B_BPFLCD1_MASK 0x20u
tushki7 0:60d829a0353a 3498 #define LCD_WF8B_BPFLCD1_SHIFT 5
tushki7 0:60d829a0353a 3499 #define LCD_WF8B_BPFLCD8_MASK 0x20u
tushki7 0:60d829a0353a 3500 #define LCD_WF8B_BPFLCD8_SHIFT 5
tushki7 0:60d829a0353a 3501 #define LCD_WF8B_BPFLCD40_MASK 0x20u
tushki7 0:60d829a0353a 3502 #define LCD_WF8B_BPFLCD40_SHIFT 5
tushki7 0:60d829a0353a 3503 #define LCD_WF8B_BPFLCD51_MASK 0x20u
tushki7 0:60d829a0353a 3504 #define LCD_WF8B_BPFLCD51_SHIFT 5
tushki7 0:60d829a0353a 3505 #define LCD_WF8B_BPFLCD16_MASK 0x20u
tushki7 0:60d829a0353a 3506 #define LCD_WF8B_BPFLCD16_SHIFT 5
tushki7 0:60d829a0353a 3507 #define LCD_WF8B_BPFLCD45_MASK 0x20u
tushki7 0:60d829a0353a 3508 #define LCD_WF8B_BPFLCD45_SHIFT 5
tushki7 0:60d829a0353a 3509 #define LCD_WF8B_BPFLCD6_MASK 0x20u
tushki7 0:60d829a0353a 3510 #define LCD_WF8B_BPFLCD6_SHIFT 5
tushki7 0:60d829a0353a 3511 #define LCD_WF8B_BPFLCD17_MASK 0x20u
tushki7 0:60d829a0353a 3512 #define LCD_WF8B_BPFLCD17_SHIFT 5
tushki7 0:60d829a0353a 3513 #define LCD_WF8B_BPFLCD28_MASK 0x20u
tushki7 0:60d829a0353a 3514 #define LCD_WF8B_BPFLCD28_SHIFT 5
tushki7 0:60d829a0353a 3515 #define LCD_WF8B_BPFLCD42_MASK 0x20u
tushki7 0:60d829a0353a 3516 #define LCD_WF8B_BPFLCD42_SHIFT 5
tushki7 0:60d829a0353a 3517 #define LCD_WF8B_BPFLCD29_MASK 0x20u
tushki7 0:60d829a0353a 3518 #define LCD_WF8B_BPFLCD29_SHIFT 5
tushki7 0:60d829a0353a 3519 #define LCD_WF8B_BPFLCD50_MASK 0x20u
tushki7 0:60d829a0353a 3520 #define LCD_WF8B_BPFLCD50_SHIFT 5
tushki7 0:60d829a0353a 3521 #define LCD_WF8B_BPFLCD18_MASK 0x20u
tushki7 0:60d829a0353a 3522 #define LCD_WF8B_BPFLCD18_SHIFT 5
tushki7 0:60d829a0353a 3523 #define LCD_WF8B_BPFLCD34_MASK 0x20u
tushki7 0:60d829a0353a 3524 #define LCD_WF8B_BPFLCD34_SHIFT 5
tushki7 0:60d829a0353a 3525 #define LCD_WF8B_BPFLCD19_MASK 0x20u
tushki7 0:60d829a0353a 3526 #define LCD_WF8B_BPFLCD19_SHIFT 5
tushki7 0:60d829a0353a 3527 #define LCD_WF8B_BPFLCD2_MASK 0x20u
tushki7 0:60d829a0353a 3528 #define LCD_WF8B_BPFLCD2_SHIFT 5
tushki7 0:60d829a0353a 3529 #define LCD_WF8B_BPFLCD9_MASK 0x20u
tushki7 0:60d829a0353a 3530 #define LCD_WF8B_BPFLCD9_SHIFT 5
tushki7 0:60d829a0353a 3531 #define LCD_WF8B_BPFLCD3_MASK 0x20u
tushki7 0:60d829a0353a 3532 #define LCD_WF8B_BPFLCD3_SHIFT 5
tushki7 0:60d829a0353a 3533 #define LCD_WF8B_BPFLCD37_MASK 0x20u
tushki7 0:60d829a0353a 3534 #define LCD_WF8B_BPFLCD37_SHIFT 5
tushki7 0:60d829a0353a 3535 #define LCD_WF8B_BPFLCD49_MASK 0x20u
tushki7 0:60d829a0353a 3536 #define LCD_WF8B_BPFLCD49_SHIFT 5
tushki7 0:60d829a0353a 3537 #define LCD_WF8B_BPFLCD20_MASK 0x20u
tushki7 0:60d829a0353a 3538 #define LCD_WF8B_BPFLCD20_SHIFT 5
tushki7 0:60d829a0353a 3539 #define LCD_WF8B_BPFLCD44_MASK 0x20u
tushki7 0:60d829a0353a 3540 #define LCD_WF8B_BPFLCD44_SHIFT 5
tushki7 0:60d829a0353a 3541 #define LCD_WF8B_BPFLCD30_MASK 0x20u
tushki7 0:60d829a0353a 3542 #define LCD_WF8B_BPFLCD30_SHIFT 5
tushki7 0:60d829a0353a 3543 #define LCD_WF8B_BPFLCD21_MASK 0x20u
tushki7 0:60d829a0353a 3544 #define LCD_WF8B_BPFLCD21_SHIFT 5
tushki7 0:60d829a0353a 3545 #define LCD_WF8B_BPFLCD35_MASK 0x20u
tushki7 0:60d829a0353a 3546 #define LCD_WF8B_BPFLCD35_SHIFT 5
tushki7 0:60d829a0353a 3547 #define LCD_WF8B_BPFLCD4_MASK 0x20u
tushki7 0:60d829a0353a 3548 #define LCD_WF8B_BPFLCD4_SHIFT 5
tushki7 0:60d829a0353a 3549 #define LCD_WF8B_BPFLCD31_MASK 0x20u
tushki7 0:60d829a0353a 3550 #define LCD_WF8B_BPFLCD31_SHIFT 5
tushki7 0:60d829a0353a 3551 #define LCD_WF8B_BPFLCD48_MASK 0x20u
tushki7 0:60d829a0353a 3552 #define LCD_WF8B_BPFLCD48_SHIFT 5
tushki7 0:60d829a0353a 3553 #define LCD_WF8B_BPFLCD7_MASK 0x20u
tushki7 0:60d829a0353a 3554 #define LCD_WF8B_BPFLCD7_SHIFT 5
tushki7 0:60d829a0353a 3555 #define LCD_WF8B_BPFLCD22_MASK 0x20u
tushki7 0:60d829a0353a 3556 #define LCD_WF8B_BPFLCD22_SHIFT 5
tushki7 0:60d829a0353a 3557 #define LCD_WF8B_BPFLCD38_MASK 0x20u
tushki7 0:60d829a0353a 3558 #define LCD_WF8B_BPFLCD38_SHIFT 5
tushki7 0:60d829a0353a 3559 #define LCD_WF8B_BPFLCD12_MASK 0x20u
tushki7 0:60d829a0353a 3560 #define LCD_WF8B_BPFLCD12_SHIFT 5
tushki7 0:60d829a0353a 3561 #define LCD_WF8B_BPFLCD23_MASK 0x20u
tushki7 0:60d829a0353a 3562 #define LCD_WF8B_BPFLCD23_SHIFT 5
tushki7 0:60d829a0353a 3563 #define LCD_WF8B_BPGLCD14_MASK 0x40u
tushki7 0:60d829a0353a 3564 #define LCD_WF8B_BPGLCD14_SHIFT 6
tushki7 0:60d829a0353a 3565 #define LCD_WF8B_BPGLCD55_MASK 0x40u
tushki7 0:60d829a0353a 3566 #define LCD_WF8B_BPGLCD55_SHIFT 6
tushki7 0:60d829a0353a 3567 #define LCD_WF8B_BPGLCD63_MASK 0x40u
tushki7 0:60d829a0353a 3568 #define LCD_WF8B_BPGLCD63_SHIFT 6
tushki7 0:60d829a0353a 3569 #define LCD_WF8B_BPGLCD15_MASK 0x40u
tushki7 0:60d829a0353a 3570 #define LCD_WF8B_BPGLCD15_SHIFT 6
tushki7 0:60d829a0353a 3571 #define LCD_WF8B_BPGLCD62_MASK 0x40u
tushki7 0:60d829a0353a 3572 #define LCD_WF8B_BPGLCD62_SHIFT 6
tushki7 0:60d829a0353a 3573 #define LCD_WF8B_BPGLCD54_MASK 0x40u
tushki7 0:60d829a0353a 3574 #define LCD_WF8B_BPGLCD54_SHIFT 6
tushki7 0:60d829a0353a 3575 #define LCD_WF8B_BPGLCD61_MASK 0x40u
tushki7 0:60d829a0353a 3576 #define LCD_WF8B_BPGLCD61_SHIFT 6
tushki7 0:60d829a0353a 3577 #define LCD_WF8B_BPGLCD60_MASK 0x40u
tushki7 0:60d829a0353a 3578 #define LCD_WF8B_BPGLCD60_SHIFT 6
tushki7 0:60d829a0353a 3579 #define LCD_WF8B_BPGLCD59_MASK 0x40u
tushki7 0:60d829a0353a 3580 #define LCD_WF8B_BPGLCD59_SHIFT 6
tushki7 0:60d829a0353a 3581 #define LCD_WF8B_BPGLCD53_MASK 0x40u
tushki7 0:60d829a0353a 3582 #define LCD_WF8B_BPGLCD53_SHIFT 6
tushki7 0:60d829a0353a 3583 #define LCD_WF8B_BPGLCD58_MASK 0x40u
tushki7 0:60d829a0353a 3584 #define LCD_WF8B_BPGLCD58_SHIFT 6
tushki7 0:60d829a0353a 3585 #define LCD_WF8B_BPGLCD0_MASK 0x40u
tushki7 0:60d829a0353a 3586 #define LCD_WF8B_BPGLCD0_SHIFT 6
tushki7 0:60d829a0353a 3587 #define LCD_WF8B_BPGLCD57_MASK 0x40u
tushki7 0:60d829a0353a 3588 #define LCD_WF8B_BPGLCD57_SHIFT 6
tushki7 0:60d829a0353a 3589 #define LCD_WF8B_BPGLCD52_MASK 0x40u
tushki7 0:60d829a0353a 3590 #define LCD_WF8B_BPGLCD52_SHIFT 6
tushki7 0:60d829a0353a 3591 #define LCD_WF8B_BPGLCD7_MASK 0x40u
tushki7 0:60d829a0353a 3592 #define LCD_WF8B_BPGLCD7_SHIFT 6
tushki7 0:60d829a0353a 3593 #define LCD_WF8B_BPGLCD56_MASK 0x40u
tushki7 0:60d829a0353a 3594 #define LCD_WF8B_BPGLCD56_SHIFT 6
tushki7 0:60d829a0353a 3595 #define LCD_WF8B_BPGLCD6_MASK 0x40u
tushki7 0:60d829a0353a 3596 #define LCD_WF8B_BPGLCD6_SHIFT 6
tushki7 0:60d829a0353a 3597 #define LCD_WF8B_BPGLCD51_MASK 0x40u
tushki7 0:60d829a0353a 3598 #define LCD_WF8B_BPGLCD51_SHIFT 6
tushki7 0:60d829a0353a 3599 #define LCD_WF8B_BPGLCD16_MASK 0x40u
tushki7 0:60d829a0353a 3600 #define LCD_WF8B_BPGLCD16_SHIFT 6
tushki7 0:60d829a0353a 3601 #define LCD_WF8B_BPGLCD1_MASK 0x40u
tushki7 0:60d829a0353a 3602 #define LCD_WF8B_BPGLCD1_SHIFT 6
tushki7 0:60d829a0353a 3603 #define LCD_WF8B_BPGLCD17_MASK 0x40u
tushki7 0:60d829a0353a 3604 #define LCD_WF8B_BPGLCD17_SHIFT 6
tushki7 0:60d829a0353a 3605 #define LCD_WF8B_BPGLCD50_MASK 0x40u
tushki7 0:60d829a0353a 3606 #define LCD_WF8B_BPGLCD50_SHIFT 6
tushki7 0:60d829a0353a 3607 #define LCD_WF8B_BPGLCD18_MASK 0x40u
tushki7 0:60d829a0353a 3608 #define LCD_WF8B_BPGLCD18_SHIFT 6
tushki7 0:60d829a0353a 3609 #define LCD_WF8B_BPGLCD19_MASK 0x40u
tushki7 0:60d829a0353a 3610 #define LCD_WF8B_BPGLCD19_SHIFT 6
tushki7 0:60d829a0353a 3611 #define LCD_WF8B_BPGLCD8_MASK 0x40u
tushki7 0:60d829a0353a 3612 #define LCD_WF8B_BPGLCD8_SHIFT 6
tushki7 0:60d829a0353a 3613 #define LCD_WF8B_BPGLCD49_MASK 0x40u
tushki7 0:60d829a0353a 3614 #define LCD_WF8B_BPGLCD49_SHIFT 6
tushki7 0:60d829a0353a 3615 #define LCD_WF8B_BPGLCD20_MASK 0x40u
tushki7 0:60d829a0353a 3616 #define LCD_WF8B_BPGLCD20_SHIFT 6
tushki7 0:60d829a0353a 3617 #define LCD_WF8B_BPGLCD9_MASK 0x40u
tushki7 0:60d829a0353a 3618 #define LCD_WF8B_BPGLCD9_SHIFT 6
tushki7 0:60d829a0353a 3619 #define LCD_WF8B_BPGLCD21_MASK 0x40u
tushki7 0:60d829a0353a 3620 #define LCD_WF8B_BPGLCD21_SHIFT 6
tushki7 0:60d829a0353a 3621 #define LCD_WF8B_BPGLCD13_MASK 0x40u
tushki7 0:60d829a0353a 3622 #define LCD_WF8B_BPGLCD13_SHIFT 6
tushki7 0:60d829a0353a 3623 #define LCD_WF8B_BPGLCD48_MASK 0x40u
tushki7 0:60d829a0353a 3624 #define LCD_WF8B_BPGLCD48_SHIFT 6
tushki7 0:60d829a0353a 3625 #define LCD_WF8B_BPGLCD22_MASK 0x40u
tushki7 0:60d829a0353a 3626 #define LCD_WF8B_BPGLCD22_SHIFT 6
tushki7 0:60d829a0353a 3627 #define LCD_WF8B_BPGLCD5_MASK 0x40u
tushki7 0:60d829a0353a 3628 #define LCD_WF8B_BPGLCD5_SHIFT 6
tushki7 0:60d829a0353a 3629 #define LCD_WF8B_BPGLCD47_MASK 0x40u
tushki7 0:60d829a0353a 3630 #define LCD_WF8B_BPGLCD47_SHIFT 6
tushki7 0:60d829a0353a 3631 #define LCD_WF8B_BPGLCD23_MASK 0x40u
tushki7 0:60d829a0353a 3632 #define LCD_WF8B_BPGLCD23_SHIFT 6
tushki7 0:60d829a0353a 3633 #define LCD_WF8B_BPGLCD24_MASK 0x40u
tushki7 0:60d829a0353a 3634 #define LCD_WF8B_BPGLCD24_SHIFT 6
tushki7 0:60d829a0353a 3635 #define LCD_WF8B_BPGLCD25_MASK 0x40u
tushki7 0:60d829a0353a 3636 #define LCD_WF8B_BPGLCD25_SHIFT 6
tushki7 0:60d829a0353a 3637 #define LCD_WF8B_BPGLCD46_MASK 0x40u
tushki7 0:60d829a0353a 3638 #define LCD_WF8B_BPGLCD46_SHIFT 6
tushki7 0:60d829a0353a 3639 #define LCD_WF8B_BPGLCD26_MASK 0x40u
tushki7 0:60d829a0353a 3640 #define LCD_WF8B_BPGLCD26_SHIFT 6
tushki7 0:60d829a0353a 3641 #define LCD_WF8B_BPGLCD27_MASK 0x40u
tushki7 0:60d829a0353a 3642 #define LCD_WF8B_BPGLCD27_SHIFT 6
tushki7 0:60d829a0353a 3643 #define LCD_WF8B_BPGLCD10_MASK 0x40u
tushki7 0:60d829a0353a 3644 #define LCD_WF8B_BPGLCD10_SHIFT 6
tushki7 0:60d829a0353a 3645 #define LCD_WF8B_BPGLCD45_MASK 0x40u
tushki7 0:60d829a0353a 3646 #define LCD_WF8B_BPGLCD45_SHIFT 6
tushki7 0:60d829a0353a 3647 #define LCD_WF8B_BPGLCD28_MASK 0x40u
tushki7 0:60d829a0353a 3648 #define LCD_WF8B_BPGLCD28_SHIFT 6
tushki7 0:60d829a0353a 3649 #define LCD_WF8B_BPGLCD29_MASK 0x40u
tushki7 0:60d829a0353a 3650 #define LCD_WF8B_BPGLCD29_SHIFT 6
tushki7 0:60d829a0353a 3651 #define LCD_WF8B_BPGLCD4_MASK 0x40u
tushki7 0:60d829a0353a 3652 #define LCD_WF8B_BPGLCD4_SHIFT 6
tushki7 0:60d829a0353a 3653 #define LCD_WF8B_BPGLCD44_MASK 0x40u
tushki7 0:60d829a0353a 3654 #define LCD_WF8B_BPGLCD44_SHIFT 6
tushki7 0:60d829a0353a 3655 #define LCD_WF8B_BPGLCD30_MASK 0x40u
tushki7 0:60d829a0353a 3656 #define LCD_WF8B_BPGLCD30_SHIFT 6
tushki7 0:60d829a0353a 3657 #define LCD_WF8B_BPGLCD2_MASK 0x40u
tushki7 0:60d829a0353a 3658 #define LCD_WF8B_BPGLCD2_SHIFT 6
tushki7 0:60d829a0353a 3659 #define LCD_WF8B_BPGLCD31_MASK 0x40u
tushki7 0:60d829a0353a 3660 #define LCD_WF8B_BPGLCD31_SHIFT 6
tushki7 0:60d829a0353a 3661 #define LCD_WF8B_BPGLCD43_MASK 0x40u
tushki7 0:60d829a0353a 3662 #define LCD_WF8B_BPGLCD43_SHIFT 6
tushki7 0:60d829a0353a 3663 #define LCD_WF8B_BPGLCD32_MASK 0x40u
tushki7 0:60d829a0353a 3664 #define LCD_WF8B_BPGLCD32_SHIFT 6
tushki7 0:60d829a0353a 3665 #define LCD_WF8B_BPGLCD33_MASK 0x40u
tushki7 0:60d829a0353a 3666 #define LCD_WF8B_BPGLCD33_SHIFT 6
tushki7 0:60d829a0353a 3667 #define LCD_WF8B_BPGLCD42_MASK 0x40u
tushki7 0:60d829a0353a 3668 #define LCD_WF8B_BPGLCD42_SHIFT 6
tushki7 0:60d829a0353a 3669 #define LCD_WF8B_BPGLCD34_MASK 0x40u
tushki7 0:60d829a0353a 3670 #define LCD_WF8B_BPGLCD34_SHIFT 6
tushki7 0:60d829a0353a 3671 #define LCD_WF8B_BPGLCD11_MASK 0x40u
tushki7 0:60d829a0353a 3672 #define LCD_WF8B_BPGLCD11_SHIFT 6
tushki7 0:60d829a0353a 3673 #define LCD_WF8B_BPGLCD35_MASK 0x40u
tushki7 0:60d829a0353a 3674 #define LCD_WF8B_BPGLCD35_SHIFT 6
tushki7 0:60d829a0353a 3675 #define LCD_WF8B_BPGLCD12_MASK 0x40u
tushki7 0:60d829a0353a 3676 #define LCD_WF8B_BPGLCD12_SHIFT 6
tushki7 0:60d829a0353a 3677 #define LCD_WF8B_BPGLCD41_MASK 0x40u
tushki7 0:60d829a0353a 3678 #define LCD_WF8B_BPGLCD41_SHIFT 6
tushki7 0:60d829a0353a 3679 #define LCD_WF8B_BPGLCD36_MASK 0x40u
tushki7 0:60d829a0353a 3680 #define LCD_WF8B_BPGLCD36_SHIFT 6
tushki7 0:60d829a0353a 3681 #define LCD_WF8B_BPGLCD3_MASK 0x40u
tushki7 0:60d829a0353a 3682 #define LCD_WF8B_BPGLCD3_SHIFT 6
tushki7 0:60d829a0353a 3683 #define LCD_WF8B_BPGLCD37_MASK 0x40u
tushki7 0:60d829a0353a 3684 #define LCD_WF8B_BPGLCD37_SHIFT 6
tushki7 0:60d829a0353a 3685 #define LCD_WF8B_BPGLCD40_MASK 0x40u
tushki7 0:60d829a0353a 3686 #define LCD_WF8B_BPGLCD40_SHIFT 6
tushki7 0:60d829a0353a 3687 #define LCD_WF8B_BPGLCD38_MASK 0x40u
tushki7 0:60d829a0353a 3688 #define LCD_WF8B_BPGLCD38_SHIFT 6
tushki7 0:60d829a0353a 3689 #define LCD_WF8B_BPGLCD39_MASK 0x40u
tushki7 0:60d829a0353a 3690 #define LCD_WF8B_BPGLCD39_SHIFT 6
tushki7 0:60d829a0353a 3691 #define LCD_WF8B_BPHLCD63_MASK 0x80u
tushki7 0:60d829a0353a 3692 #define LCD_WF8B_BPHLCD63_SHIFT 7
tushki7 0:60d829a0353a 3693 #define LCD_WF8B_BPHLCD62_MASK 0x80u
tushki7 0:60d829a0353a 3694 #define LCD_WF8B_BPHLCD62_SHIFT 7
tushki7 0:60d829a0353a 3695 #define LCD_WF8B_BPHLCD61_MASK 0x80u
tushki7 0:60d829a0353a 3696 #define LCD_WF8B_BPHLCD61_SHIFT 7
tushki7 0:60d829a0353a 3697 #define LCD_WF8B_BPHLCD60_MASK 0x80u
tushki7 0:60d829a0353a 3698 #define LCD_WF8B_BPHLCD60_SHIFT 7
tushki7 0:60d829a0353a 3699 #define LCD_WF8B_BPHLCD59_MASK 0x80u
tushki7 0:60d829a0353a 3700 #define LCD_WF8B_BPHLCD59_SHIFT 7
tushki7 0:60d829a0353a 3701 #define LCD_WF8B_BPHLCD58_MASK 0x80u
tushki7 0:60d829a0353a 3702 #define LCD_WF8B_BPHLCD58_SHIFT 7
tushki7 0:60d829a0353a 3703 #define LCD_WF8B_BPHLCD57_MASK 0x80u
tushki7 0:60d829a0353a 3704 #define LCD_WF8B_BPHLCD57_SHIFT 7
tushki7 0:60d829a0353a 3705 #define LCD_WF8B_BPHLCD0_MASK 0x80u
tushki7 0:60d829a0353a 3706 #define LCD_WF8B_BPHLCD0_SHIFT 7
tushki7 0:60d829a0353a 3707 #define LCD_WF8B_BPHLCD56_MASK 0x80u
tushki7 0:60d829a0353a 3708 #define LCD_WF8B_BPHLCD56_SHIFT 7
tushki7 0:60d829a0353a 3709 #define LCD_WF8B_BPHLCD55_MASK 0x80u
tushki7 0:60d829a0353a 3710 #define LCD_WF8B_BPHLCD55_SHIFT 7
tushki7 0:60d829a0353a 3711 #define LCD_WF8B_BPHLCD54_MASK 0x80u
tushki7 0:60d829a0353a 3712 #define LCD_WF8B_BPHLCD54_SHIFT 7
tushki7 0:60d829a0353a 3713 #define LCD_WF8B_BPHLCD53_MASK 0x80u
tushki7 0:60d829a0353a 3714 #define LCD_WF8B_BPHLCD53_SHIFT 7
tushki7 0:60d829a0353a 3715 #define LCD_WF8B_BPHLCD52_MASK 0x80u
tushki7 0:60d829a0353a 3716 #define LCD_WF8B_BPHLCD52_SHIFT 7
tushki7 0:60d829a0353a 3717 #define LCD_WF8B_BPHLCD51_MASK 0x80u
tushki7 0:60d829a0353a 3718 #define LCD_WF8B_BPHLCD51_SHIFT 7
tushki7 0:60d829a0353a 3719 #define LCD_WF8B_BPHLCD50_MASK 0x80u
tushki7 0:60d829a0353a 3720 #define LCD_WF8B_BPHLCD50_SHIFT 7
tushki7 0:60d829a0353a 3721 #define LCD_WF8B_BPHLCD1_MASK 0x80u
tushki7 0:60d829a0353a 3722 #define LCD_WF8B_BPHLCD1_SHIFT 7
tushki7 0:60d829a0353a 3723 #define LCD_WF8B_BPHLCD49_MASK 0x80u
tushki7 0:60d829a0353a 3724 #define LCD_WF8B_BPHLCD49_SHIFT 7
tushki7 0:60d829a0353a 3725 #define LCD_WF8B_BPHLCD48_MASK 0x80u
tushki7 0:60d829a0353a 3726 #define LCD_WF8B_BPHLCD48_SHIFT 7
tushki7 0:60d829a0353a 3727 #define LCD_WF8B_BPHLCD47_MASK 0x80u
tushki7 0:60d829a0353a 3728 #define LCD_WF8B_BPHLCD47_SHIFT 7
tushki7 0:60d829a0353a 3729 #define LCD_WF8B_BPHLCD46_MASK 0x80u
tushki7 0:60d829a0353a 3730 #define LCD_WF8B_BPHLCD46_SHIFT 7
tushki7 0:60d829a0353a 3731 #define LCD_WF8B_BPHLCD45_MASK 0x80u
tushki7 0:60d829a0353a 3732 #define LCD_WF8B_BPHLCD45_SHIFT 7
tushki7 0:60d829a0353a 3733 #define LCD_WF8B_BPHLCD44_MASK 0x80u
tushki7 0:60d829a0353a 3734 #define LCD_WF8B_BPHLCD44_SHIFT 7
tushki7 0:60d829a0353a 3735 #define LCD_WF8B_BPHLCD43_MASK 0x80u
tushki7 0:60d829a0353a 3736 #define LCD_WF8B_BPHLCD43_SHIFT 7
tushki7 0:60d829a0353a 3737 #define LCD_WF8B_BPHLCD2_MASK 0x80u
tushki7 0:60d829a0353a 3738 #define LCD_WF8B_BPHLCD2_SHIFT 7
tushki7 0:60d829a0353a 3739 #define LCD_WF8B_BPHLCD42_MASK 0x80u
tushki7 0:60d829a0353a 3740 #define LCD_WF8B_BPHLCD42_SHIFT 7
tushki7 0:60d829a0353a 3741 #define LCD_WF8B_BPHLCD41_MASK 0x80u
tushki7 0:60d829a0353a 3742 #define LCD_WF8B_BPHLCD41_SHIFT 7
tushki7 0:60d829a0353a 3743 #define LCD_WF8B_BPHLCD40_MASK 0x80u
tushki7 0:60d829a0353a 3744 #define LCD_WF8B_BPHLCD40_SHIFT 7
tushki7 0:60d829a0353a 3745 #define LCD_WF8B_BPHLCD39_MASK 0x80u
tushki7 0:60d829a0353a 3746 #define LCD_WF8B_BPHLCD39_SHIFT 7
tushki7 0:60d829a0353a 3747 #define LCD_WF8B_BPHLCD38_MASK 0x80u
tushki7 0:60d829a0353a 3748 #define LCD_WF8B_BPHLCD38_SHIFT 7
tushki7 0:60d829a0353a 3749 #define LCD_WF8B_BPHLCD37_MASK 0x80u
tushki7 0:60d829a0353a 3750 #define LCD_WF8B_BPHLCD37_SHIFT 7
tushki7 0:60d829a0353a 3751 #define LCD_WF8B_BPHLCD36_MASK 0x80u
tushki7 0:60d829a0353a 3752 #define LCD_WF8B_BPHLCD36_SHIFT 7
tushki7 0:60d829a0353a 3753 #define LCD_WF8B_BPHLCD3_MASK 0x80u
tushki7 0:60d829a0353a 3754 #define LCD_WF8B_BPHLCD3_SHIFT 7
tushki7 0:60d829a0353a 3755 #define LCD_WF8B_BPHLCD35_MASK 0x80u
tushki7 0:60d829a0353a 3756 #define LCD_WF8B_BPHLCD35_SHIFT 7
tushki7 0:60d829a0353a 3757 #define LCD_WF8B_BPHLCD34_MASK 0x80u
tushki7 0:60d829a0353a 3758 #define LCD_WF8B_BPHLCD34_SHIFT 7
tushki7 0:60d829a0353a 3759 #define LCD_WF8B_BPHLCD33_MASK 0x80u
tushki7 0:60d829a0353a 3760 #define LCD_WF8B_BPHLCD33_SHIFT 7
tushki7 0:60d829a0353a 3761 #define LCD_WF8B_BPHLCD32_MASK 0x80u
tushki7 0:60d829a0353a 3762 #define LCD_WF8B_BPHLCD32_SHIFT 7
tushki7 0:60d829a0353a 3763 #define LCD_WF8B_BPHLCD31_MASK 0x80u
tushki7 0:60d829a0353a 3764 #define LCD_WF8B_BPHLCD31_SHIFT 7
tushki7 0:60d829a0353a 3765 #define LCD_WF8B_BPHLCD30_MASK 0x80u
tushki7 0:60d829a0353a 3766 #define LCD_WF8B_BPHLCD30_SHIFT 7
tushki7 0:60d829a0353a 3767 #define LCD_WF8B_BPHLCD29_MASK 0x80u
tushki7 0:60d829a0353a 3768 #define LCD_WF8B_BPHLCD29_SHIFT 7
tushki7 0:60d829a0353a 3769 #define LCD_WF8B_BPHLCD4_MASK 0x80u
tushki7 0:60d829a0353a 3770 #define LCD_WF8B_BPHLCD4_SHIFT 7
tushki7 0:60d829a0353a 3771 #define LCD_WF8B_BPHLCD28_MASK 0x80u
tushki7 0:60d829a0353a 3772 #define LCD_WF8B_BPHLCD28_SHIFT 7
tushki7 0:60d829a0353a 3773 #define LCD_WF8B_BPHLCD27_MASK 0x80u
tushki7 0:60d829a0353a 3774 #define LCD_WF8B_BPHLCD27_SHIFT 7
tushki7 0:60d829a0353a 3775 #define LCD_WF8B_BPHLCD26_MASK 0x80u
tushki7 0:60d829a0353a 3776 #define LCD_WF8B_BPHLCD26_SHIFT 7
tushki7 0:60d829a0353a 3777 #define LCD_WF8B_BPHLCD25_MASK 0x80u
tushki7 0:60d829a0353a 3778 #define LCD_WF8B_BPHLCD25_SHIFT 7
tushki7 0:60d829a0353a 3779 #define LCD_WF8B_BPHLCD24_MASK 0x80u
tushki7 0:60d829a0353a 3780 #define LCD_WF8B_BPHLCD24_SHIFT 7
tushki7 0:60d829a0353a 3781 #define LCD_WF8B_BPHLCD23_MASK 0x80u
tushki7 0:60d829a0353a 3782 #define LCD_WF8B_BPHLCD23_SHIFT 7
tushki7 0:60d829a0353a 3783 #define LCD_WF8B_BPHLCD22_MASK 0x80u
tushki7 0:60d829a0353a 3784 #define LCD_WF8B_BPHLCD22_SHIFT 7
tushki7 0:60d829a0353a 3785 #define LCD_WF8B_BPHLCD5_MASK 0x80u
tushki7 0:60d829a0353a 3786 #define LCD_WF8B_BPHLCD5_SHIFT 7
tushki7 0:60d829a0353a 3787 #define LCD_WF8B_BPHLCD21_MASK 0x80u
tushki7 0:60d829a0353a 3788 #define LCD_WF8B_BPHLCD21_SHIFT 7
tushki7 0:60d829a0353a 3789 #define LCD_WF8B_BPHLCD20_MASK 0x80u
tushki7 0:60d829a0353a 3790 #define LCD_WF8B_BPHLCD20_SHIFT 7
tushki7 0:60d829a0353a 3791 #define LCD_WF8B_BPHLCD19_MASK 0x80u
tushki7 0:60d829a0353a 3792 #define LCD_WF8B_BPHLCD19_SHIFT 7
tushki7 0:60d829a0353a 3793 #define LCD_WF8B_BPHLCD18_MASK 0x80u
tushki7 0:60d829a0353a 3794 #define LCD_WF8B_BPHLCD18_SHIFT 7
tushki7 0:60d829a0353a 3795 #define LCD_WF8B_BPHLCD17_MASK 0x80u
tushki7 0:60d829a0353a 3796 #define LCD_WF8B_BPHLCD17_SHIFT 7
tushki7 0:60d829a0353a 3797 #define LCD_WF8B_BPHLCD16_MASK 0x80u
tushki7 0:60d829a0353a 3798 #define LCD_WF8B_BPHLCD16_SHIFT 7
tushki7 0:60d829a0353a 3799 #define LCD_WF8B_BPHLCD15_MASK 0x80u
tushki7 0:60d829a0353a 3800 #define LCD_WF8B_BPHLCD15_SHIFT 7
tushki7 0:60d829a0353a 3801 #define LCD_WF8B_BPHLCD6_MASK 0x80u
tushki7 0:60d829a0353a 3802 #define LCD_WF8B_BPHLCD6_SHIFT 7
tushki7 0:60d829a0353a 3803 #define LCD_WF8B_BPHLCD14_MASK 0x80u
tushki7 0:60d829a0353a 3804 #define LCD_WF8B_BPHLCD14_SHIFT 7
tushki7 0:60d829a0353a 3805 #define LCD_WF8B_BPHLCD13_MASK 0x80u
tushki7 0:60d829a0353a 3806 #define LCD_WF8B_BPHLCD13_SHIFT 7
tushki7 0:60d829a0353a 3807 #define LCD_WF8B_BPHLCD12_MASK 0x80u
tushki7 0:60d829a0353a 3808 #define LCD_WF8B_BPHLCD12_SHIFT 7
tushki7 0:60d829a0353a 3809 #define LCD_WF8B_BPHLCD11_MASK 0x80u
tushki7 0:60d829a0353a 3810 #define LCD_WF8B_BPHLCD11_SHIFT 7
tushki7 0:60d829a0353a 3811 #define LCD_WF8B_BPHLCD10_MASK 0x80u
tushki7 0:60d829a0353a 3812 #define LCD_WF8B_BPHLCD10_SHIFT 7
tushki7 0:60d829a0353a 3813 #define LCD_WF8B_BPHLCD9_MASK 0x80u
tushki7 0:60d829a0353a 3814 #define LCD_WF8B_BPHLCD9_SHIFT 7
tushki7 0:60d829a0353a 3815 #define LCD_WF8B_BPHLCD8_MASK 0x80u
tushki7 0:60d829a0353a 3816 #define LCD_WF8B_BPHLCD8_SHIFT 7
tushki7 0:60d829a0353a 3817 #define LCD_WF8B_BPHLCD7_MASK 0x80u
tushki7 0:60d829a0353a 3818 #define LCD_WF8B_BPHLCD7_SHIFT 7
tushki7 0:60d829a0353a 3819
tushki7 0:60d829a0353a 3820 /*!
tushki7 0:60d829a0353a 3821 * @}
tushki7 0:60d829a0353a 3822 */ /* end of group LCD_Register_Masks */
tushki7 0:60d829a0353a 3823
tushki7 0:60d829a0353a 3824
tushki7 0:60d829a0353a 3825 /* LCD - Peripheral instance base addresses */
tushki7 0:60d829a0353a 3826 /** Peripheral LCD base address */
tushki7 0:60d829a0353a 3827 #define LCD_BASE (0x40053000u)
tushki7 0:60d829a0353a 3828 /** Peripheral LCD base pointer */
tushki7 0:60d829a0353a 3829 #define LCD ((LCD_Type *)LCD_BASE)
tushki7 0:60d829a0353a 3830 #define LCD_BASE_PTR (LCD)
tushki7 0:60d829a0353a 3831 /** Array initializer of LCD peripheral base addresses */
tushki7 0:60d829a0353a 3832 #define LCD_BASE_ADDRS { LCD_BASE }
tushki7 0:60d829a0353a 3833 /** Array initializer of LCD peripheral base pointers */
tushki7 0:60d829a0353a 3834 #define LCD_BASE_PTRS { LCD }
tushki7 0:60d829a0353a 3835 /** Interrupt vectors for the LCD peripheral type */
tushki7 0:60d829a0353a 3836 #define LCD_LCD_IRQS { LCD_IRQn }
tushki7 0:60d829a0353a 3837
tushki7 0:60d829a0353a 3838 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 3839 -- LCD - Register accessor macros
tushki7 0:60d829a0353a 3840 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 3841
tushki7 0:60d829a0353a 3842 /*!
tushki7 0:60d829a0353a 3843 * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
tushki7 0:60d829a0353a 3844 * @{
tushki7 0:60d829a0353a 3845 */
tushki7 0:60d829a0353a 3846
tushki7 0:60d829a0353a 3847
tushki7 0:60d829a0353a 3848 /* LCD - Register instance definitions */
tushki7 0:60d829a0353a 3849 /* LCD */
tushki7 0:60d829a0353a 3850 #define LCD_GCR LCD_GCR_REG(LCD)
tushki7 0:60d829a0353a 3851 #define LCD_AR LCD_AR_REG(LCD)
tushki7 0:60d829a0353a 3852 #define LCD_FDCR LCD_FDCR_REG(LCD)
tushki7 0:60d829a0353a 3853 #define LCD_FDSR LCD_FDSR_REG(LCD)
tushki7 0:60d829a0353a 3854 #define LCD_PENL LCD_PEN_REG(LCD,0)
tushki7 0:60d829a0353a 3855 #define LCD_PENH LCD_PEN_REG(LCD,1)
tushki7 0:60d829a0353a 3856 #define LCD_BPENL LCD_BPEN_REG(LCD,0)
tushki7 0:60d829a0353a 3857 #define LCD_BPENH LCD_BPEN_REG(LCD,1)
tushki7 0:60d829a0353a 3858 #define LCD_WF0 LCD_WF8B_REG(LCD,0)
tushki7 0:60d829a0353a 3859 #define LCD_WF3TO0 LCD_WF_REG(LCD,0)
tushki7 0:60d829a0353a 3860 #define LCD_WF1 LCD_WF8B_REG(LCD,1)
tushki7 0:60d829a0353a 3861 #define LCD_WF2 LCD_WF8B_REG(LCD,2)
tushki7 0:60d829a0353a 3862 #define LCD_WF3 LCD_WF8B_REG(LCD,3)
tushki7 0:60d829a0353a 3863 #define LCD_WF4 LCD_WF8B_REG(LCD,4)
tushki7 0:60d829a0353a 3864 #define LCD_WF7TO4 LCD_WF_REG(LCD,1)
tushki7 0:60d829a0353a 3865 #define LCD_WF5 LCD_WF8B_REG(LCD,5)
tushki7 0:60d829a0353a 3866 #define LCD_WF6 LCD_WF8B_REG(LCD,6)
tushki7 0:60d829a0353a 3867 #define LCD_WF7 LCD_WF8B_REG(LCD,7)
tushki7 0:60d829a0353a 3868 #define LCD_WF11TO8 LCD_WF_REG(LCD,2)
tushki7 0:60d829a0353a 3869 #define LCD_WF8 LCD_WF8B_REG(LCD,8)
tushki7 0:60d829a0353a 3870 #define LCD_WF9 LCD_WF8B_REG(LCD,9)
tushki7 0:60d829a0353a 3871 #define LCD_WF10 LCD_WF8B_REG(LCD,10)
tushki7 0:60d829a0353a 3872 #define LCD_WF11 LCD_WF8B_REG(LCD,11)
tushki7 0:60d829a0353a 3873 #define LCD_WF12 LCD_WF8B_REG(LCD,12)
tushki7 0:60d829a0353a 3874 #define LCD_WF15TO12 LCD_WF_REG(LCD,3)
tushki7 0:60d829a0353a 3875 #define LCD_WF13 LCD_WF8B_REG(LCD,13)
tushki7 0:60d829a0353a 3876 #define LCD_WF14 LCD_WF8B_REG(LCD,14)
tushki7 0:60d829a0353a 3877 #define LCD_WF15 LCD_WF8B_REG(LCD,15)
tushki7 0:60d829a0353a 3878 #define LCD_WF16 LCD_WF8B_REG(LCD,16)
tushki7 0:60d829a0353a 3879 #define LCD_WF19TO16 LCD_WF_REG(LCD,4)
tushki7 0:60d829a0353a 3880 #define LCD_WF17 LCD_WF8B_REG(LCD,17)
tushki7 0:60d829a0353a 3881 #define LCD_WF18 LCD_WF8B_REG(LCD,18)
tushki7 0:60d829a0353a 3882 #define LCD_WF19 LCD_WF8B_REG(LCD,19)
tushki7 0:60d829a0353a 3883 #define LCD_WF20 LCD_WF8B_REG(LCD,20)
tushki7 0:60d829a0353a 3884 #define LCD_WF23TO20 LCD_WF_REG(LCD,5)
tushki7 0:60d829a0353a 3885 #define LCD_WF21 LCD_WF8B_REG(LCD,21)
tushki7 0:60d829a0353a 3886 #define LCD_WF22 LCD_WF8B_REG(LCD,22)
tushki7 0:60d829a0353a 3887 #define LCD_WF23 LCD_WF8B_REG(LCD,23)
tushki7 0:60d829a0353a 3888 #define LCD_WF24 LCD_WF8B_REG(LCD,24)
tushki7 0:60d829a0353a 3889 #define LCD_WF27TO24 LCD_WF_REG(LCD,6)
tushki7 0:60d829a0353a 3890 #define LCD_WF25 LCD_WF8B_REG(LCD,25)
tushki7 0:60d829a0353a 3891 #define LCD_WF26 LCD_WF8B_REG(LCD,26)
tushki7 0:60d829a0353a 3892 #define LCD_WF27 LCD_WF8B_REG(LCD,27)
tushki7 0:60d829a0353a 3893 #define LCD_WF28 LCD_WF8B_REG(LCD,28)
tushki7 0:60d829a0353a 3894 #define LCD_WF31TO28 LCD_WF_REG(LCD,7)
tushki7 0:60d829a0353a 3895 #define LCD_WF29 LCD_WF8B_REG(LCD,29)
tushki7 0:60d829a0353a 3896 #define LCD_WF30 LCD_WF8B_REG(LCD,30)
tushki7 0:60d829a0353a 3897 #define LCD_WF31 LCD_WF8B_REG(LCD,31)
tushki7 0:60d829a0353a 3898 #define LCD_WF32 LCD_WF8B_REG(LCD,32)
tushki7 0:60d829a0353a 3899 #define LCD_WF35TO32 LCD_WF_REG(LCD,8)
tushki7 0:60d829a0353a 3900 #define LCD_WF33 LCD_WF8B_REG(LCD,33)
tushki7 0:60d829a0353a 3901 #define LCD_WF34 LCD_WF8B_REG(LCD,34)
tushki7 0:60d829a0353a 3902 #define LCD_WF35 LCD_WF8B_REG(LCD,35)
tushki7 0:60d829a0353a 3903 #define LCD_WF36 LCD_WF8B_REG(LCD,36)
tushki7 0:60d829a0353a 3904 #define LCD_WF39TO36 LCD_WF_REG(LCD,9)
tushki7 0:60d829a0353a 3905 #define LCD_WF37 LCD_WF8B_REG(LCD,37)
tushki7 0:60d829a0353a 3906 #define LCD_WF38 LCD_WF8B_REG(LCD,38)
tushki7 0:60d829a0353a 3907 #define LCD_WF39 LCD_WF8B_REG(LCD,39)
tushki7 0:60d829a0353a 3908 #define LCD_WF40 LCD_WF8B_REG(LCD,40)
tushki7 0:60d829a0353a 3909 #define LCD_WF43TO40 LCD_WF_REG(LCD,10)
tushki7 0:60d829a0353a 3910 #define LCD_WF41 LCD_WF8B_REG(LCD,41)
tushki7 0:60d829a0353a 3911 #define LCD_WF42 LCD_WF8B_REG(LCD,42)
tushki7 0:60d829a0353a 3912 #define LCD_WF43 LCD_WF8B_REG(LCD,43)
tushki7 0:60d829a0353a 3913 #define LCD_WF44 LCD_WF8B_REG(LCD,44)
tushki7 0:60d829a0353a 3914 #define LCD_WF47TO44 LCD_WF_REG(LCD,11)
tushki7 0:60d829a0353a 3915 #define LCD_WF45 LCD_WF8B_REG(LCD,45)
tushki7 0:60d829a0353a 3916 #define LCD_WF46 LCD_WF8B_REG(LCD,46)
tushki7 0:60d829a0353a 3917 #define LCD_WF47 LCD_WF8B_REG(LCD,47)
tushki7 0:60d829a0353a 3918 #define LCD_WF48 LCD_WF8B_REG(LCD,48)
tushki7 0:60d829a0353a 3919 #define LCD_WF51TO48 LCD_WF_REG(LCD,12)
tushki7 0:60d829a0353a 3920 #define LCD_WF49 LCD_WF8B_REG(LCD,49)
tushki7 0:60d829a0353a 3921 #define LCD_WF50 LCD_WF8B_REG(LCD,50)
tushki7 0:60d829a0353a 3922 #define LCD_WF51 LCD_WF8B_REG(LCD,51)
tushki7 0:60d829a0353a 3923 #define LCD_WF52 LCD_WF8B_REG(LCD,52)
tushki7 0:60d829a0353a 3924 #define LCD_WF55TO52 LCD_WF_REG(LCD,13)
tushki7 0:60d829a0353a 3925 #define LCD_WF53 LCD_WF8B_REG(LCD,53)
tushki7 0:60d829a0353a 3926 #define LCD_WF54 LCD_WF8B_REG(LCD,54)
tushki7 0:60d829a0353a 3927 #define LCD_WF55 LCD_WF8B_REG(LCD,55)
tushki7 0:60d829a0353a 3928 #define LCD_WF56 LCD_WF8B_REG(LCD,56)
tushki7 0:60d829a0353a 3929 #define LCD_WF59TO56 LCD_WF_REG(LCD,14)
tushki7 0:60d829a0353a 3930 #define LCD_WF57 LCD_WF8B_REG(LCD,57)
tushki7 0:60d829a0353a 3931 #define LCD_WF58 LCD_WF8B_REG(LCD,58)
tushki7 0:60d829a0353a 3932 #define LCD_WF59 LCD_WF8B_REG(LCD,59)
tushki7 0:60d829a0353a 3933 #define LCD_WF60 LCD_WF8B_REG(LCD,60)
tushki7 0:60d829a0353a 3934 #define LCD_WF63TO60 LCD_WF_REG(LCD,15)
tushki7 0:60d829a0353a 3935 #define LCD_WF61 LCD_WF8B_REG(LCD,61)
tushki7 0:60d829a0353a 3936 #define LCD_WF62 LCD_WF8B_REG(LCD,62)
tushki7 0:60d829a0353a 3937 #define LCD_WF63 LCD_WF8B_REG(LCD,63)
tushki7 0:60d829a0353a 3938
tushki7 0:60d829a0353a 3939 /* LCD - Register array accessors */
tushki7 0:60d829a0353a 3940 #define LCD_PEN(index) LCD_PEN_REG(LCD,index)
tushki7 0:60d829a0353a 3941 #define LCD_BPEN(index) LCD_BPEN_REG(LCD,index)
tushki7 0:60d829a0353a 3942 #define LCD_WF(index2) LCD_WF_REG(LCD,index2)
tushki7 0:60d829a0353a 3943 #define LCD_WF8B(index2) LCD_WF8B_REG(LCD,index2)
tushki7 0:60d829a0353a 3944
tushki7 0:60d829a0353a 3945 /*!
tushki7 0:60d829a0353a 3946 * @}
tushki7 0:60d829a0353a 3947 */ /* end of group LCD_Register_Accessor_Macros */
tushki7 0:60d829a0353a 3948
tushki7 0:60d829a0353a 3949
tushki7 0:60d829a0353a 3950 /*!
tushki7 0:60d829a0353a 3951 * @}
tushki7 0:60d829a0353a 3952 */ /* end of group LCD_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 3953
tushki7 0:60d829a0353a 3954
tushki7 0:60d829a0353a 3955 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 3956 -- LLWU Peripheral Access Layer
tushki7 0:60d829a0353a 3957 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 3958
tushki7 0:60d829a0353a 3959 /*!
tushki7 0:60d829a0353a 3960 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
tushki7 0:60d829a0353a 3961 * @{
tushki7 0:60d829a0353a 3962 */
tushki7 0:60d829a0353a 3963
tushki7 0:60d829a0353a 3964 /** LLWU - Register Layout Typedef */
tushki7 0:60d829a0353a 3965 typedef struct {
tushki7 0:60d829a0353a 3966 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
tushki7 0:60d829a0353a 3967 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
tushki7 0:60d829a0353a 3968 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
tushki7 0:60d829a0353a 3969 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
tushki7 0:60d829a0353a 3970 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
tushki7 0:60d829a0353a 3971 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
tushki7 0:60d829a0353a 3972 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
tushki7 0:60d829a0353a 3973 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
tushki7 0:60d829a0353a 3974 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
tushki7 0:60d829a0353a 3975 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
tushki7 0:60d829a0353a 3976 } LLWU_Type, *LLWU_MemMapPtr;
tushki7 0:60d829a0353a 3977
tushki7 0:60d829a0353a 3978 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 3979 -- LLWU - Register accessor macros
tushki7 0:60d829a0353a 3980 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 3981
tushki7 0:60d829a0353a 3982 /*!
tushki7 0:60d829a0353a 3983 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
tushki7 0:60d829a0353a 3984 * @{
tushki7 0:60d829a0353a 3985 */
tushki7 0:60d829a0353a 3986
tushki7 0:60d829a0353a 3987
tushki7 0:60d829a0353a 3988 /* LLWU - Register accessors */
tushki7 0:60d829a0353a 3989 #define LLWU_PE1_REG(base) ((base)->PE1)
tushki7 0:60d829a0353a 3990 #define LLWU_PE2_REG(base) ((base)->PE2)
tushki7 0:60d829a0353a 3991 #define LLWU_PE3_REG(base) ((base)->PE3)
tushki7 0:60d829a0353a 3992 #define LLWU_PE4_REG(base) ((base)->PE4)
tushki7 0:60d829a0353a 3993 #define LLWU_ME_REG(base) ((base)->ME)
tushki7 0:60d829a0353a 3994 #define LLWU_F1_REG(base) ((base)->F1)
tushki7 0:60d829a0353a 3995 #define LLWU_F2_REG(base) ((base)->F2)
tushki7 0:60d829a0353a 3996 #define LLWU_F3_REG(base) ((base)->F3)
tushki7 0:60d829a0353a 3997 #define LLWU_FILT1_REG(base) ((base)->FILT1)
tushki7 0:60d829a0353a 3998 #define LLWU_FILT2_REG(base) ((base)->FILT2)
tushki7 0:60d829a0353a 3999
tushki7 0:60d829a0353a 4000 /*!
tushki7 0:60d829a0353a 4001 * @}
tushki7 0:60d829a0353a 4002 */ /* end of group LLWU_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4003
tushki7 0:60d829a0353a 4004
tushki7 0:60d829a0353a 4005 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4006 -- LLWU Register Masks
tushki7 0:60d829a0353a 4007 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4008
tushki7 0:60d829a0353a 4009 /*!
tushki7 0:60d829a0353a 4010 * @addtogroup LLWU_Register_Masks LLWU Register Masks
tushki7 0:60d829a0353a 4011 * @{
tushki7 0:60d829a0353a 4012 */
tushki7 0:60d829a0353a 4013
tushki7 0:60d829a0353a 4014 /* PE1 Bit Fields */
tushki7 0:60d829a0353a 4015 #define LLWU_PE1_WUPE0_MASK 0x3u
tushki7 0:60d829a0353a 4016 #define LLWU_PE1_WUPE0_SHIFT 0
tushki7 0:60d829a0353a 4017 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
tushki7 0:60d829a0353a 4018 #define LLWU_PE1_WUPE1_MASK 0xCu
tushki7 0:60d829a0353a 4019 #define LLWU_PE1_WUPE1_SHIFT 2
tushki7 0:60d829a0353a 4020 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
tushki7 0:60d829a0353a 4021 #define LLWU_PE1_WUPE2_MASK 0x30u
tushki7 0:60d829a0353a 4022 #define LLWU_PE1_WUPE2_SHIFT 4
tushki7 0:60d829a0353a 4023 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
tushki7 0:60d829a0353a 4024 #define LLWU_PE1_WUPE3_MASK 0xC0u
tushki7 0:60d829a0353a 4025 #define LLWU_PE1_WUPE3_SHIFT 6
tushki7 0:60d829a0353a 4026 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
tushki7 0:60d829a0353a 4027 /* PE2 Bit Fields */
tushki7 0:60d829a0353a 4028 #define LLWU_PE2_WUPE4_MASK 0x3u
tushki7 0:60d829a0353a 4029 #define LLWU_PE2_WUPE4_SHIFT 0
tushki7 0:60d829a0353a 4030 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
tushki7 0:60d829a0353a 4031 #define LLWU_PE2_WUPE5_MASK 0xCu
tushki7 0:60d829a0353a 4032 #define LLWU_PE2_WUPE5_SHIFT 2
tushki7 0:60d829a0353a 4033 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
tushki7 0:60d829a0353a 4034 #define LLWU_PE2_WUPE6_MASK 0x30u
tushki7 0:60d829a0353a 4035 #define LLWU_PE2_WUPE6_SHIFT 4
tushki7 0:60d829a0353a 4036 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
tushki7 0:60d829a0353a 4037 #define LLWU_PE2_WUPE7_MASK 0xC0u
tushki7 0:60d829a0353a 4038 #define LLWU_PE2_WUPE7_SHIFT 6
tushki7 0:60d829a0353a 4039 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
tushki7 0:60d829a0353a 4040 /* PE3 Bit Fields */
tushki7 0:60d829a0353a 4041 #define LLWU_PE3_WUPE8_MASK 0x3u
tushki7 0:60d829a0353a 4042 #define LLWU_PE3_WUPE8_SHIFT 0
tushki7 0:60d829a0353a 4043 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
tushki7 0:60d829a0353a 4044 #define LLWU_PE3_WUPE9_MASK 0xCu
tushki7 0:60d829a0353a 4045 #define LLWU_PE3_WUPE9_SHIFT 2
tushki7 0:60d829a0353a 4046 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
tushki7 0:60d829a0353a 4047 #define LLWU_PE3_WUPE10_MASK 0x30u
tushki7 0:60d829a0353a 4048 #define LLWU_PE3_WUPE10_SHIFT 4
tushki7 0:60d829a0353a 4049 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
tushki7 0:60d829a0353a 4050 #define LLWU_PE3_WUPE11_MASK 0xC0u
tushki7 0:60d829a0353a 4051 #define LLWU_PE3_WUPE11_SHIFT 6
tushki7 0:60d829a0353a 4052 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
tushki7 0:60d829a0353a 4053 /* PE4 Bit Fields */
tushki7 0:60d829a0353a 4054 #define LLWU_PE4_WUPE12_MASK 0x3u
tushki7 0:60d829a0353a 4055 #define LLWU_PE4_WUPE12_SHIFT 0
tushki7 0:60d829a0353a 4056 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
tushki7 0:60d829a0353a 4057 #define LLWU_PE4_WUPE13_MASK 0xCu
tushki7 0:60d829a0353a 4058 #define LLWU_PE4_WUPE13_SHIFT 2
tushki7 0:60d829a0353a 4059 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
tushki7 0:60d829a0353a 4060 #define LLWU_PE4_WUPE14_MASK 0x30u
tushki7 0:60d829a0353a 4061 #define LLWU_PE4_WUPE14_SHIFT 4
tushki7 0:60d829a0353a 4062 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
tushki7 0:60d829a0353a 4063 #define LLWU_PE4_WUPE15_MASK 0xC0u
tushki7 0:60d829a0353a 4064 #define LLWU_PE4_WUPE15_SHIFT 6
tushki7 0:60d829a0353a 4065 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
tushki7 0:60d829a0353a 4066 /* ME Bit Fields */
tushki7 0:60d829a0353a 4067 #define LLWU_ME_WUME0_MASK 0x1u
tushki7 0:60d829a0353a 4068 #define LLWU_ME_WUME0_SHIFT 0
tushki7 0:60d829a0353a 4069 #define LLWU_ME_WUME1_MASK 0x2u
tushki7 0:60d829a0353a 4070 #define LLWU_ME_WUME1_SHIFT 1
tushki7 0:60d829a0353a 4071 #define LLWU_ME_WUME2_MASK 0x4u
tushki7 0:60d829a0353a 4072 #define LLWU_ME_WUME2_SHIFT 2
tushki7 0:60d829a0353a 4073 #define LLWU_ME_WUME3_MASK 0x8u
tushki7 0:60d829a0353a 4074 #define LLWU_ME_WUME3_SHIFT 3
tushki7 0:60d829a0353a 4075 #define LLWU_ME_WUME4_MASK 0x10u
tushki7 0:60d829a0353a 4076 #define LLWU_ME_WUME4_SHIFT 4
tushki7 0:60d829a0353a 4077 #define LLWU_ME_WUME5_MASK 0x20u
tushki7 0:60d829a0353a 4078 #define LLWU_ME_WUME5_SHIFT 5
tushki7 0:60d829a0353a 4079 #define LLWU_ME_WUME6_MASK 0x40u
tushki7 0:60d829a0353a 4080 #define LLWU_ME_WUME6_SHIFT 6
tushki7 0:60d829a0353a 4081 #define LLWU_ME_WUME7_MASK 0x80u
tushki7 0:60d829a0353a 4082 #define LLWU_ME_WUME7_SHIFT 7
tushki7 0:60d829a0353a 4083 /* F1 Bit Fields */
tushki7 0:60d829a0353a 4084 #define LLWU_F1_WUF0_MASK 0x1u
tushki7 0:60d829a0353a 4085 #define LLWU_F1_WUF0_SHIFT 0
tushki7 0:60d829a0353a 4086 #define LLWU_F1_WUF1_MASK 0x2u
tushki7 0:60d829a0353a 4087 #define LLWU_F1_WUF1_SHIFT 1
tushki7 0:60d829a0353a 4088 #define LLWU_F1_WUF2_MASK 0x4u
tushki7 0:60d829a0353a 4089 #define LLWU_F1_WUF2_SHIFT 2
tushki7 0:60d829a0353a 4090 #define LLWU_F1_WUF3_MASK 0x8u
tushki7 0:60d829a0353a 4091 #define LLWU_F1_WUF3_SHIFT 3
tushki7 0:60d829a0353a 4092 #define LLWU_F1_WUF4_MASK 0x10u
tushki7 0:60d829a0353a 4093 #define LLWU_F1_WUF4_SHIFT 4
tushki7 0:60d829a0353a 4094 #define LLWU_F1_WUF5_MASK 0x20u
tushki7 0:60d829a0353a 4095 #define LLWU_F1_WUF5_SHIFT 5
tushki7 0:60d829a0353a 4096 #define LLWU_F1_WUF6_MASK 0x40u
tushki7 0:60d829a0353a 4097 #define LLWU_F1_WUF6_SHIFT 6
tushki7 0:60d829a0353a 4098 #define LLWU_F1_WUF7_MASK 0x80u
tushki7 0:60d829a0353a 4099 #define LLWU_F1_WUF7_SHIFT 7
tushki7 0:60d829a0353a 4100 /* F2 Bit Fields */
tushki7 0:60d829a0353a 4101 #define LLWU_F2_WUF8_MASK 0x1u
tushki7 0:60d829a0353a 4102 #define LLWU_F2_WUF8_SHIFT 0
tushki7 0:60d829a0353a 4103 #define LLWU_F2_WUF9_MASK 0x2u
tushki7 0:60d829a0353a 4104 #define LLWU_F2_WUF9_SHIFT 1
tushki7 0:60d829a0353a 4105 #define LLWU_F2_WUF10_MASK 0x4u
tushki7 0:60d829a0353a 4106 #define LLWU_F2_WUF10_SHIFT 2
tushki7 0:60d829a0353a 4107 #define LLWU_F2_WUF11_MASK 0x8u
tushki7 0:60d829a0353a 4108 #define LLWU_F2_WUF11_SHIFT 3
tushki7 0:60d829a0353a 4109 #define LLWU_F2_WUF12_MASK 0x10u
tushki7 0:60d829a0353a 4110 #define LLWU_F2_WUF12_SHIFT 4
tushki7 0:60d829a0353a 4111 #define LLWU_F2_WUF13_MASK 0x20u
tushki7 0:60d829a0353a 4112 #define LLWU_F2_WUF13_SHIFT 5
tushki7 0:60d829a0353a 4113 #define LLWU_F2_WUF14_MASK 0x40u
tushki7 0:60d829a0353a 4114 #define LLWU_F2_WUF14_SHIFT 6
tushki7 0:60d829a0353a 4115 #define LLWU_F2_WUF15_MASK 0x80u
tushki7 0:60d829a0353a 4116 #define LLWU_F2_WUF15_SHIFT 7
tushki7 0:60d829a0353a 4117 /* F3 Bit Fields */
tushki7 0:60d829a0353a 4118 #define LLWU_F3_MWUF0_MASK 0x1u
tushki7 0:60d829a0353a 4119 #define LLWU_F3_MWUF0_SHIFT 0
tushki7 0:60d829a0353a 4120 #define LLWU_F3_MWUF1_MASK 0x2u
tushki7 0:60d829a0353a 4121 #define LLWU_F3_MWUF1_SHIFT 1
tushki7 0:60d829a0353a 4122 #define LLWU_F3_MWUF2_MASK 0x4u
tushki7 0:60d829a0353a 4123 #define LLWU_F3_MWUF2_SHIFT 2
tushki7 0:60d829a0353a 4124 #define LLWU_F3_MWUF3_MASK 0x8u
tushki7 0:60d829a0353a 4125 #define LLWU_F3_MWUF3_SHIFT 3
tushki7 0:60d829a0353a 4126 #define LLWU_F3_MWUF4_MASK 0x10u
tushki7 0:60d829a0353a 4127 #define LLWU_F3_MWUF4_SHIFT 4
tushki7 0:60d829a0353a 4128 #define LLWU_F3_MWUF5_MASK 0x20u
tushki7 0:60d829a0353a 4129 #define LLWU_F3_MWUF5_SHIFT 5
tushki7 0:60d829a0353a 4130 #define LLWU_F3_MWUF6_MASK 0x40u
tushki7 0:60d829a0353a 4131 #define LLWU_F3_MWUF6_SHIFT 6
tushki7 0:60d829a0353a 4132 #define LLWU_F3_MWUF7_MASK 0x80u
tushki7 0:60d829a0353a 4133 #define LLWU_F3_MWUF7_SHIFT 7
tushki7 0:60d829a0353a 4134 /* FILT1 Bit Fields */
tushki7 0:60d829a0353a 4135 #define LLWU_FILT1_FILTSEL_MASK 0xFu
tushki7 0:60d829a0353a 4136 #define LLWU_FILT1_FILTSEL_SHIFT 0
tushki7 0:60d829a0353a 4137 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
tushki7 0:60d829a0353a 4138 #define LLWU_FILT1_FILTE_MASK 0x60u
tushki7 0:60d829a0353a 4139 #define LLWU_FILT1_FILTE_SHIFT 5
tushki7 0:60d829a0353a 4140 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
tushki7 0:60d829a0353a 4141 #define LLWU_FILT1_FILTF_MASK 0x80u
tushki7 0:60d829a0353a 4142 #define LLWU_FILT1_FILTF_SHIFT 7
tushki7 0:60d829a0353a 4143 /* FILT2 Bit Fields */
tushki7 0:60d829a0353a 4144 #define LLWU_FILT2_FILTSEL_MASK 0xFu
tushki7 0:60d829a0353a 4145 #define LLWU_FILT2_FILTSEL_SHIFT 0
tushki7 0:60d829a0353a 4146 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
tushki7 0:60d829a0353a 4147 #define LLWU_FILT2_FILTE_MASK 0x60u
tushki7 0:60d829a0353a 4148 #define LLWU_FILT2_FILTE_SHIFT 5
tushki7 0:60d829a0353a 4149 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
tushki7 0:60d829a0353a 4150 #define LLWU_FILT2_FILTF_MASK 0x80u
tushki7 0:60d829a0353a 4151 #define LLWU_FILT2_FILTF_SHIFT 7
tushki7 0:60d829a0353a 4152
tushki7 0:60d829a0353a 4153 /*!
tushki7 0:60d829a0353a 4154 * @}
tushki7 0:60d829a0353a 4155 */ /* end of group LLWU_Register_Masks */
tushki7 0:60d829a0353a 4156
tushki7 0:60d829a0353a 4157
tushki7 0:60d829a0353a 4158 /* LLWU - Peripheral instance base addresses */
tushki7 0:60d829a0353a 4159 /** Peripheral LLWU base address */
tushki7 0:60d829a0353a 4160 #define LLWU_BASE (0x4007C000u)
tushki7 0:60d829a0353a 4161 /** Peripheral LLWU base pointer */
tushki7 0:60d829a0353a 4162 #define LLWU ((LLWU_Type *)LLWU_BASE)
tushki7 0:60d829a0353a 4163 #define LLWU_BASE_PTR (LLWU)
tushki7 0:60d829a0353a 4164 /** Array initializer of LLWU peripheral base addresses */
tushki7 0:60d829a0353a 4165 #define LLWU_BASE_ADDRS { LLWU_BASE }
tushki7 0:60d829a0353a 4166 /** Array initializer of LLWU peripheral base pointers */
tushki7 0:60d829a0353a 4167 #define LLWU_BASE_PTRS { LLWU }
tushki7 0:60d829a0353a 4168 /** Interrupt vectors for the LLWU peripheral type */
tushki7 0:60d829a0353a 4169 #define LLWU_IRQS { LLWU_IRQn }
tushki7 0:60d829a0353a 4170
tushki7 0:60d829a0353a 4171 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4172 -- LLWU - Register accessor macros
tushki7 0:60d829a0353a 4173 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4174
tushki7 0:60d829a0353a 4175 /*!
tushki7 0:60d829a0353a 4176 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
tushki7 0:60d829a0353a 4177 * @{
tushki7 0:60d829a0353a 4178 */
tushki7 0:60d829a0353a 4179
tushki7 0:60d829a0353a 4180
tushki7 0:60d829a0353a 4181 /* LLWU - Register instance definitions */
tushki7 0:60d829a0353a 4182 /* LLWU */
tushki7 0:60d829a0353a 4183 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
tushki7 0:60d829a0353a 4184 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
tushki7 0:60d829a0353a 4185 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
tushki7 0:60d829a0353a 4186 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
tushki7 0:60d829a0353a 4187 #define LLWU_ME LLWU_ME_REG(LLWU)
tushki7 0:60d829a0353a 4188 #define LLWU_F1 LLWU_F1_REG(LLWU)
tushki7 0:60d829a0353a 4189 #define LLWU_F2 LLWU_F2_REG(LLWU)
tushki7 0:60d829a0353a 4190 #define LLWU_F3 LLWU_F3_REG(LLWU)
tushki7 0:60d829a0353a 4191 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
tushki7 0:60d829a0353a 4192 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
tushki7 0:60d829a0353a 4193
tushki7 0:60d829a0353a 4194 /*!
tushki7 0:60d829a0353a 4195 * @}
tushki7 0:60d829a0353a 4196 */ /* end of group LLWU_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4197
tushki7 0:60d829a0353a 4198
tushki7 0:60d829a0353a 4199 /*!
tushki7 0:60d829a0353a 4200 * @}
tushki7 0:60d829a0353a 4201 */ /* end of group LLWU_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 4202
tushki7 0:60d829a0353a 4203
tushki7 0:60d829a0353a 4204 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4205 -- LPTMR Peripheral Access Layer
tushki7 0:60d829a0353a 4206 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4207
tushki7 0:60d829a0353a 4208 /*!
tushki7 0:60d829a0353a 4209 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
tushki7 0:60d829a0353a 4210 * @{
tushki7 0:60d829a0353a 4211 */
tushki7 0:60d829a0353a 4212
tushki7 0:60d829a0353a 4213 /** LPTMR - Register Layout Typedef */
tushki7 0:60d829a0353a 4214 typedef struct {
tushki7 0:60d829a0353a 4215 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
tushki7 0:60d829a0353a 4216 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
tushki7 0:60d829a0353a 4217 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
tushki7 0:60d829a0353a 4218 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
tushki7 0:60d829a0353a 4219 } LPTMR_Type, *LPTMR_MemMapPtr;
tushki7 0:60d829a0353a 4220
tushki7 0:60d829a0353a 4221 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4222 -- LPTMR - Register accessor macros
tushki7 0:60d829a0353a 4223 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4224
tushki7 0:60d829a0353a 4225 /*!
tushki7 0:60d829a0353a 4226 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
tushki7 0:60d829a0353a 4227 * @{
tushki7 0:60d829a0353a 4228 */
tushki7 0:60d829a0353a 4229
tushki7 0:60d829a0353a 4230
tushki7 0:60d829a0353a 4231 /* LPTMR - Register accessors */
tushki7 0:60d829a0353a 4232 #define LPTMR_CSR_REG(base) ((base)->CSR)
tushki7 0:60d829a0353a 4233 #define LPTMR_PSR_REG(base) ((base)->PSR)
tushki7 0:60d829a0353a 4234 #define LPTMR_CMR_REG(base) ((base)->CMR)
tushki7 0:60d829a0353a 4235 #define LPTMR_CNR_REG(base) ((base)->CNR)
tushki7 0:60d829a0353a 4236
tushki7 0:60d829a0353a 4237 /*!
tushki7 0:60d829a0353a 4238 * @}
tushki7 0:60d829a0353a 4239 */ /* end of group LPTMR_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4240
tushki7 0:60d829a0353a 4241
tushki7 0:60d829a0353a 4242 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4243 -- LPTMR Register Masks
tushki7 0:60d829a0353a 4244 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4245
tushki7 0:60d829a0353a 4246 /*!
tushki7 0:60d829a0353a 4247 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
tushki7 0:60d829a0353a 4248 * @{
tushki7 0:60d829a0353a 4249 */
tushki7 0:60d829a0353a 4250
tushki7 0:60d829a0353a 4251 /* CSR Bit Fields */
tushki7 0:60d829a0353a 4252 #define LPTMR_CSR_TEN_MASK 0x1u
tushki7 0:60d829a0353a 4253 #define LPTMR_CSR_TEN_SHIFT 0
tushki7 0:60d829a0353a 4254 #define LPTMR_CSR_TMS_MASK 0x2u
tushki7 0:60d829a0353a 4255 #define LPTMR_CSR_TMS_SHIFT 1
tushki7 0:60d829a0353a 4256 #define LPTMR_CSR_TFC_MASK 0x4u
tushki7 0:60d829a0353a 4257 #define LPTMR_CSR_TFC_SHIFT 2
tushki7 0:60d829a0353a 4258 #define LPTMR_CSR_TPP_MASK 0x8u
tushki7 0:60d829a0353a 4259 #define LPTMR_CSR_TPP_SHIFT 3
tushki7 0:60d829a0353a 4260 #define LPTMR_CSR_TPS_MASK 0x30u
tushki7 0:60d829a0353a 4261 #define LPTMR_CSR_TPS_SHIFT 4
tushki7 0:60d829a0353a 4262 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
tushki7 0:60d829a0353a 4263 #define LPTMR_CSR_TIE_MASK 0x40u
tushki7 0:60d829a0353a 4264 #define LPTMR_CSR_TIE_SHIFT 6
tushki7 0:60d829a0353a 4265 #define LPTMR_CSR_TCF_MASK 0x80u
tushki7 0:60d829a0353a 4266 #define LPTMR_CSR_TCF_SHIFT 7
tushki7 0:60d829a0353a 4267 /* PSR Bit Fields */
tushki7 0:60d829a0353a 4268 #define LPTMR_PSR_PCS_MASK 0x3u
tushki7 0:60d829a0353a 4269 #define LPTMR_PSR_PCS_SHIFT 0
tushki7 0:60d829a0353a 4270 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
tushki7 0:60d829a0353a 4271 #define LPTMR_PSR_PBYP_MASK 0x4u
tushki7 0:60d829a0353a 4272 #define LPTMR_PSR_PBYP_SHIFT 2
tushki7 0:60d829a0353a 4273 #define LPTMR_PSR_PRESCALE_MASK 0x78u
tushki7 0:60d829a0353a 4274 #define LPTMR_PSR_PRESCALE_SHIFT 3
tushki7 0:60d829a0353a 4275 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
tushki7 0:60d829a0353a 4276 /* CMR Bit Fields */
tushki7 0:60d829a0353a 4277 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
tushki7 0:60d829a0353a 4278 #define LPTMR_CMR_COMPARE_SHIFT 0
tushki7 0:60d829a0353a 4279 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
tushki7 0:60d829a0353a 4280 /* CNR Bit Fields */
tushki7 0:60d829a0353a 4281 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
tushki7 0:60d829a0353a 4282 #define LPTMR_CNR_COUNTER_SHIFT 0
tushki7 0:60d829a0353a 4283 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
tushki7 0:60d829a0353a 4284
tushki7 0:60d829a0353a 4285 /*!
tushki7 0:60d829a0353a 4286 * @}
tushki7 0:60d829a0353a 4287 */ /* end of group LPTMR_Register_Masks */
tushki7 0:60d829a0353a 4288
tushki7 0:60d829a0353a 4289
tushki7 0:60d829a0353a 4290 /* LPTMR - Peripheral instance base addresses */
tushki7 0:60d829a0353a 4291 /** Peripheral LPTMR0 base address */
tushki7 0:60d829a0353a 4292 #define LPTMR0_BASE (0x40040000u)
tushki7 0:60d829a0353a 4293 /** Peripheral LPTMR0 base pointer */
tushki7 0:60d829a0353a 4294 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
tushki7 0:60d829a0353a 4295 #define LPTMR0_BASE_PTR (LPTMR0)
tushki7 0:60d829a0353a 4296 /** Array initializer of LPTMR peripheral base addresses */
tushki7 0:60d829a0353a 4297 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
tushki7 0:60d829a0353a 4298 /** Array initializer of LPTMR peripheral base pointers */
tushki7 0:60d829a0353a 4299 #define LPTMR_BASE_PTRS { LPTMR0 }
tushki7 0:60d829a0353a 4300 /** Interrupt vectors for the LPTMR peripheral type */
tushki7 0:60d829a0353a 4301 #define LPTMR_IRQS { LPTMR0_IRQn }
tushki7 0:60d829a0353a 4302
tushki7 0:60d829a0353a 4303 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4304 -- LPTMR - Register accessor macros
tushki7 0:60d829a0353a 4305 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4306
tushki7 0:60d829a0353a 4307 /*!
tushki7 0:60d829a0353a 4308 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
tushki7 0:60d829a0353a 4309 * @{
tushki7 0:60d829a0353a 4310 */
tushki7 0:60d829a0353a 4311
tushki7 0:60d829a0353a 4312
tushki7 0:60d829a0353a 4313 /* LPTMR - Register instance definitions */
tushki7 0:60d829a0353a 4314 /* LPTMR0 */
tushki7 0:60d829a0353a 4315 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
tushki7 0:60d829a0353a 4316 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
tushki7 0:60d829a0353a 4317 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
tushki7 0:60d829a0353a 4318 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
tushki7 0:60d829a0353a 4319
tushki7 0:60d829a0353a 4320 /*!
tushki7 0:60d829a0353a 4321 * @}
tushki7 0:60d829a0353a 4322 */ /* end of group LPTMR_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4323
tushki7 0:60d829a0353a 4324
tushki7 0:60d829a0353a 4325 /*!
tushki7 0:60d829a0353a 4326 * @}
tushki7 0:60d829a0353a 4327 */ /* end of group LPTMR_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 4328
tushki7 0:60d829a0353a 4329
tushki7 0:60d829a0353a 4330 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4331 -- LPUART Peripheral Access Layer
tushki7 0:60d829a0353a 4332 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4333
tushki7 0:60d829a0353a 4334 /*!
tushki7 0:60d829a0353a 4335 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
tushki7 0:60d829a0353a 4336 * @{
tushki7 0:60d829a0353a 4337 */
tushki7 0:60d829a0353a 4338
tushki7 0:60d829a0353a 4339 /** LPUART - Register Layout Typedef */
tushki7 0:60d829a0353a 4340 typedef struct {
tushki7 0:60d829a0353a 4341 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
tushki7 0:60d829a0353a 4342 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
tushki7 0:60d829a0353a 4343 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
tushki7 0:60d829a0353a 4344 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
tushki7 0:60d829a0353a 4345 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
tushki7 0:60d829a0353a 4346 } LPUART_Type, *LPUART_MemMapPtr;
tushki7 0:60d829a0353a 4347
tushki7 0:60d829a0353a 4348 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4349 -- LPUART - Register accessor macros
tushki7 0:60d829a0353a 4350 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4351
tushki7 0:60d829a0353a 4352 /*!
tushki7 0:60d829a0353a 4353 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
tushki7 0:60d829a0353a 4354 * @{
tushki7 0:60d829a0353a 4355 */
tushki7 0:60d829a0353a 4356
tushki7 0:60d829a0353a 4357
tushki7 0:60d829a0353a 4358 /* LPUART - Register accessors */
tushki7 0:60d829a0353a 4359 #define LPUART_BAUD_REG(base) ((base)->BAUD)
tushki7 0:60d829a0353a 4360 #define LPUART_STAT_REG(base) ((base)->STAT)
tushki7 0:60d829a0353a 4361 #define LPUART_CTRL_REG(base) ((base)->CTRL)
tushki7 0:60d829a0353a 4362 #define LPUART_DATA_REG(base) ((base)->DATA)
tushki7 0:60d829a0353a 4363 #define LPUART_MATCH_REG(base) ((base)->MATCH)
tushki7 0:60d829a0353a 4364
tushki7 0:60d829a0353a 4365 /*!
tushki7 0:60d829a0353a 4366 * @}
tushki7 0:60d829a0353a 4367 */ /* end of group LPUART_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4368
tushki7 0:60d829a0353a 4369
tushki7 0:60d829a0353a 4370 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4371 -- LPUART Register Masks
tushki7 0:60d829a0353a 4372 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4373
tushki7 0:60d829a0353a 4374 /*!
tushki7 0:60d829a0353a 4375 * @addtogroup LPUART_Register_Masks LPUART Register Masks
tushki7 0:60d829a0353a 4376 * @{
tushki7 0:60d829a0353a 4377 */
tushki7 0:60d829a0353a 4378
tushki7 0:60d829a0353a 4379 /* BAUD Bit Fields */
tushki7 0:60d829a0353a 4380 #define LPUART_BAUD_SBR_MASK 0x1FFFu
tushki7 0:60d829a0353a 4381 #define LPUART_BAUD_SBR_SHIFT 0
tushki7 0:60d829a0353a 4382 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
tushki7 0:60d829a0353a 4383 #define LPUART_BAUD_SBNS_MASK 0x2000u
tushki7 0:60d829a0353a 4384 #define LPUART_BAUD_SBNS_SHIFT 13
tushki7 0:60d829a0353a 4385 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
tushki7 0:60d829a0353a 4386 #define LPUART_BAUD_RXEDGIE_SHIFT 14
tushki7 0:60d829a0353a 4387 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
tushki7 0:60d829a0353a 4388 #define LPUART_BAUD_LBKDIE_SHIFT 15
tushki7 0:60d829a0353a 4389 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
tushki7 0:60d829a0353a 4390 #define LPUART_BAUD_RESYNCDIS_SHIFT 16
tushki7 0:60d829a0353a 4391 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
tushki7 0:60d829a0353a 4392 #define LPUART_BAUD_BOTHEDGE_SHIFT 17
tushki7 0:60d829a0353a 4393 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
tushki7 0:60d829a0353a 4394 #define LPUART_BAUD_MATCFG_SHIFT 18
tushki7 0:60d829a0353a 4395 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
tushki7 0:60d829a0353a 4396 #define LPUART_BAUD_RDMAE_MASK 0x200000u
tushki7 0:60d829a0353a 4397 #define LPUART_BAUD_RDMAE_SHIFT 21
tushki7 0:60d829a0353a 4398 #define LPUART_BAUD_TDMAE_MASK 0x800000u
tushki7 0:60d829a0353a 4399 #define LPUART_BAUD_TDMAE_SHIFT 23
tushki7 0:60d829a0353a 4400 #define LPUART_BAUD_OSR_MASK 0x1F000000u
tushki7 0:60d829a0353a 4401 #define LPUART_BAUD_OSR_SHIFT 24
tushki7 0:60d829a0353a 4402 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
tushki7 0:60d829a0353a 4403 #define LPUART_BAUD_M10_MASK 0x20000000u
tushki7 0:60d829a0353a 4404 #define LPUART_BAUD_M10_SHIFT 29
tushki7 0:60d829a0353a 4405 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
tushki7 0:60d829a0353a 4406 #define LPUART_BAUD_MAEN2_SHIFT 30
tushki7 0:60d829a0353a 4407 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
tushki7 0:60d829a0353a 4408 #define LPUART_BAUD_MAEN1_SHIFT 31
tushki7 0:60d829a0353a 4409 /* STAT Bit Fields */
tushki7 0:60d829a0353a 4410 #define LPUART_STAT_MA2F_MASK 0x4000u
tushki7 0:60d829a0353a 4411 #define LPUART_STAT_MA2F_SHIFT 14
tushki7 0:60d829a0353a 4412 #define LPUART_STAT_MA1F_MASK 0x8000u
tushki7 0:60d829a0353a 4413 #define LPUART_STAT_MA1F_SHIFT 15
tushki7 0:60d829a0353a 4414 #define LPUART_STAT_PF_MASK 0x10000u
tushki7 0:60d829a0353a 4415 #define LPUART_STAT_PF_SHIFT 16
tushki7 0:60d829a0353a 4416 #define LPUART_STAT_FE_MASK 0x20000u
tushki7 0:60d829a0353a 4417 #define LPUART_STAT_FE_SHIFT 17
tushki7 0:60d829a0353a 4418 #define LPUART_STAT_NF_MASK 0x40000u
tushki7 0:60d829a0353a 4419 #define LPUART_STAT_NF_SHIFT 18
tushki7 0:60d829a0353a 4420 #define LPUART_STAT_OR_MASK 0x80000u
tushki7 0:60d829a0353a 4421 #define LPUART_STAT_OR_SHIFT 19
tushki7 0:60d829a0353a 4422 #define LPUART_STAT_IDLE_MASK 0x100000u
tushki7 0:60d829a0353a 4423 #define LPUART_STAT_IDLE_SHIFT 20
tushki7 0:60d829a0353a 4424 #define LPUART_STAT_RDRF_MASK 0x200000u
tushki7 0:60d829a0353a 4425 #define LPUART_STAT_RDRF_SHIFT 21
tushki7 0:60d829a0353a 4426 #define LPUART_STAT_TC_MASK 0x400000u
tushki7 0:60d829a0353a 4427 #define LPUART_STAT_TC_SHIFT 22
tushki7 0:60d829a0353a 4428 #define LPUART_STAT_TDRE_MASK 0x800000u
tushki7 0:60d829a0353a 4429 #define LPUART_STAT_TDRE_SHIFT 23
tushki7 0:60d829a0353a 4430 #define LPUART_STAT_RAF_MASK 0x1000000u
tushki7 0:60d829a0353a 4431 #define LPUART_STAT_RAF_SHIFT 24
tushki7 0:60d829a0353a 4432 #define LPUART_STAT_LBKDE_MASK 0x2000000u
tushki7 0:60d829a0353a 4433 #define LPUART_STAT_LBKDE_SHIFT 25
tushki7 0:60d829a0353a 4434 #define LPUART_STAT_BRK13_MASK 0x4000000u
tushki7 0:60d829a0353a 4435 #define LPUART_STAT_BRK13_SHIFT 26
tushki7 0:60d829a0353a 4436 #define LPUART_STAT_RWUID_MASK 0x8000000u
tushki7 0:60d829a0353a 4437 #define LPUART_STAT_RWUID_SHIFT 27
tushki7 0:60d829a0353a 4438 #define LPUART_STAT_RXINV_MASK 0x10000000u
tushki7 0:60d829a0353a 4439 #define LPUART_STAT_RXINV_SHIFT 28
tushki7 0:60d829a0353a 4440 #define LPUART_STAT_MSBF_MASK 0x20000000u
tushki7 0:60d829a0353a 4441 #define LPUART_STAT_MSBF_SHIFT 29
tushki7 0:60d829a0353a 4442 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
tushki7 0:60d829a0353a 4443 #define LPUART_STAT_RXEDGIF_SHIFT 30
tushki7 0:60d829a0353a 4444 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
tushki7 0:60d829a0353a 4445 #define LPUART_STAT_LBKDIF_SHIFT 31
tushki7 0:60d829a0353a 4446 /* CTRL Bit Fields */
tushki7 0:60d829a0353a 4447 #define LPUART_CTRL_PT_MASK 0x1u
tushki7 0:60d829a0353a 4448 #define LPUART_CTRL_PT_SHIFT 0
tushki7 0:60d829a0353a 4449 #define LPUART_CTRL_PE_MASK 0x2u
tushki7 0:60d829a0353a 4450 #define LPUART_CTRL_PE_SHIFT 1
tushki7 0:60d829a0353a 4451 #define LPUART_CTRL_ILT_MASK 0x4u
tushki7 0:60d829a0353a 4452 #define LPUART_CTRL_ILT_SHIFT 2
tushki7 0:60d829a0353a 4453 #define LPUART_CTRL_WAKE_MASK 0x8u
tushki7 0:60d829a0353a 4454 #define LPUART_CTRL_WAKE_SHIFT 3
tushki7 0:60d829a0353a 4455 #define LPUART_CTRL_M_MASK 0x10u
tushki7 0:60d829a0353a 4456 #define LPUART_CTRL_M_SHIFT 4
tushki7 0:60d829a0353a 4457 #define LPUART_CTRL_RSRC_MASK 0x20u
tushki7 0:60d829a0353a 4458 #define LPUART_CTRL_RSRC_SHIFT 5
tushki7 0:60d829a0353a 4459 #define LPUART_CTRL_DOZEEN_MASK 0x40u
tushki7 0:60d829a0353a 4460 #define LPUART_CTRL_DOZEEN_SHIFT 6
tushki7 0:60d829a0353a 4461 #define LPUART_CTRL_LOOPS_MASK 0x80u
tushki7 0:60d829a0353a 4462 #define LPUART_CTRL_LOOPS_SHIFT 7
tushki7 0:60d829a0353a 4463 #define LPUART_CTRL_IDLECFG_MASK 0x700u
tushki7 0:60d829a0353a 4464 #define LPUART_CTRL_IDLECFG_SHIFT 8
tushki7 0:60d829a0353a 4465 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
tushki7 0:60d829a0353a 4466 #define LPUART_CTRL_MA2IE_MASK 0x4000u
tushki7 0:60d829a0353a 4467 #define LPUART_CTRL_MA2IE_SHIFT 14
tushki7 0:60d829a0353a 4468 #define LPUART_CTRL_MA1IE_MASK 0x8000u
tushki7 0:60d829a0353a 4469 #define LPUART_CTRL_MA1IE_SHIFT 15
tushki7 0:60d829a0353a 4470 #define LPUART_CTRL_SBK_MASK 0x10000u
tushki7 0:60d829a0353a 4471 #define LPUART_CTRL_SBK_SHIFT 16
tushki7 0:60d829a0353a 4472 #define LPUART_CTRL_RWU_MASK 0x20000u
tushki7 0:60d829a0353a 4473 #define LPUART_CTRL_RWU_SHIFT 17
tushki7 0:60d829a0353a 4474 #define LPUART_CTRL_RE_MASK 0x40000u
tushki7 0:60d829a0353a 4475 #define LPUART_CTRL_RE_SHIFT 18
tushki7 0:60d829a0353a 4476 #define LPUART_CTRL_TE_MASK 0x80000u
tushki7 0:60d829a0353a 4477 #define LPUART_CTRL_TE_SHIFT 19
tushki7 0:60d829a0353a 4478 #define LPUART_CTRL_ILIE_MASK 0x100000u
tushki7 0:60d829a0353a 4479 #define LPUART_CTRL_ILIE_SHIFT 20
tushki7 0:60d829a0353a 4480 #define LPUART_CTRL_RIE_MASK 0x200000u
tushki7 0:60d829a0353a 4481 #define LPUART_CTRL_RIE_SHIFT 21
tushki7 0:60d829a0353a 4482 #define LPUART_CTRL_TCIE_MASK 0x400000u
tushki7 0:60d829a0353a 4483 #define LPUART_CTRL_TCIE_SHIFT 22
tushki7 0:60d829a0353a 4484 #define LPUART_CTRL_TIE_MASK 0x800000u
tushki7 0:60d829a0353a 4485 #define LPUART_CTRL_TIE_SHIFT 23
tushki7 0:60d829a0353a 4486 #define LPUART_CTRL_PEIE_MASK 0x1000000u
tushki7 0:60d829a0353a 4487 #define LPUART_CTRL_PEIE_SHIFT 24
tushki7 0:60d829a0353a 4488 #define LPUART_CTRL_FEIE_MASK 0x2000000u
tushki7 0:60d829a0353a 4489 #define LPUART_CTRL_FEIE_SHIFT 25
tushki7 0:60d829a0353a 4490 #define LPUART_CTRL_NEIE_MASK 0x4000000u
tushki7 0:60d829a0353a 4491 #define LPUART_CTRL_NEIE_SHIFT 26
tushki7 0:60d829a0353a 4492 #define LPUART_CTRL_ORIE_MASK 0x8000000u
tushki7 0:60d829a0353a 4493 #define LPUART_CTRL_ORIE_SHIFT 27
tushki7 0:60d829a0353a 4494 #define LPUART_CTRL_TXINV_MASK 0x10000000u
tushki7 0:60d829a0353a 4495 #define LPUART_CTRL_TXINV_SHIFT 28
tushki7 0:60d829a0353a 4496 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
tushki7 0:60d829a0353a 4497 #define LPUART_CTRL_TXDIR_SHIFT 29
tushki7 0:60d829a0353a 4498 #define LPUART_CTRL_R9T8_MASK 0x40000000u
tushki7 0:60d829a0353a 4499 #define LPUART_CTRL_R9T8_SHIFT 30
tushki7 0:60d829a0353a 4500 #define LPUART_CTRL_R8T9_MASK 0x80000000u
tushki7 0:60d829a0353a 4501 #define LPUART_CTRL_R8T9_SHIFT 31
tushki7 0:60d829a0353a 4502 /* DATA Bit Fields */
tushki7 0:60d829a0353a 4503 #define LPUART_DATA_R0T0_MASK 0x1u
tushki7 0:60d829a0353a 4504 #define LPUART_DATA_R0T0_SHIFT 0
tushki7 0:60d829a0353a 4505 #define LPUART_DATA_R1T1_MASK 0x2u
tushki7 0:60d829a0353a 4506 #define LPUART_DATA_R1T1_SHIFT 1
tushki7 0:60d829a0353a 4507 #define LPUART_DATA_R2T2_MASK 0x4u
tushki7 0:60d829a0353a 4508 #define LPUART_DATA_R2T2_SHIFT 2
tushki7 0:60d829a0353a 4509 #define LPUART_DATA_R3T3_MASK 0x8u
tushki7 0:60d829a0353a 4510 #define LPUART_DATA_R3T3_SHIFT 3
tushki7 0:60d829a0353a 4511 #define LPUART_DATA_R4T4_MASK 0x10u
tushki7 0:60d829a0353a 4512 #define LPUART_DATA_R4T4_SHIFT 4
tushki7 0:60d829a0353a 4513 #define LPUART_DATA_R5T5_MASK 0x20u
tushki7 0:60d829a0353a 4514 #define LPUART_DATA_R5T5_SHIFT 5
tushki7 0:60d829a0353a 4515 #define LPUART_DATA_R6T6_MASK 0x40u
tushki7 0:60d829a0353a 4516 #define LPUART_DATA_R6T6_SHIFT 6
tushki7 0:60d829a0353a 4517 #define LPUART_DATA_R7T7_MASK 0x80u
tushki7 0:60d829a0353a 4518 #define LPUART_DATA_R7T7_SHIFT 7
tushki7 0:60d829a0353a 4519 #define LPUART_DATA_R8T8_MASK 0x100u
tushki7 0:60d829a0353a 4520 #define LPUART_DATA_R8T8_SHIFT 8
tushki7 0:60d829a0353a 4521 #define LPUART_DATA_R9T9_MASK 0x200u
tushki7 0:60d829a0353a 4522 #define LPUART_DATA_R9T9_SHIFT 9
tushki7 0:60d829a0353a 4523 #define LPUART_DATA_IDLINE_MASK 0x800u
tushki7 0:60d829a0353a 4524 #define LPUART_DATA_IDLINE_SHIFT 11
tushki7 0:60d829a0353a 4525 #define LPUART_DATA_RXEMPT_MASK 0x1000u
tushki7 0:60d829a0353a 4526 #define LPUART_DATA_RXEMPT_SHIFT 12
tushki7 0:60d829a0353a 4527 #define LPUART_DATA_FRETSC_MASK 0x2000u
tushki7 0:60d829a0353a 4528 #define LPUART_DATA_FRETSC_SHIFT 13
tushki7 0:60d829a0353a 4529 #define LPUART_DATA_PARITYE_MASK 0x4000u
tushki7 0:60d829a0353a 4530 #define LPUART_DATA_PARITYE_SHIFT 14
tushki7 0:60d829a0353a 4531 #define LPUART_DATA_NOISY_MASK 0x8000u
tushki7 0:60d829a0353a 4532 #define LPUART_DATA_NOISY_SHIFT 15
tushki7 0:60d829a0353a 4533 /* MATCH Bit Fields */
tushki7 0:60d829a0353a 4534 #define LPUART_MATCH_MA1_MASK 0x3FFu
tushki7 0:60d829a0353a 4535 #define LPUART_MATCH_MA1_SHIFT 0
tushki7 0:60d829a0353a 4536 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
tushki7 0:60d829a0353a 4537 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
tushki7 0:60d829a0353a 4538 #define LPUART_MATCH_MA2_SHIFT 16
tushki7 0:60d829a0353a 4539 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
tushki7 0:60d829a0353a 4540
tushki7 0:60d829a0353a 4541 /*!
tushki7 0:60d829a0353a 4542 * @}
tushki7 0:60d829a0353a 4543 */ /* end of group LPUART_Register_Masks */
tushki7 0:60d829a0353a 4544
tushki7 0:60d829a0353a 4545
tushki7 0:60d829a0353a 4546 /* LPUART - Peripheral instance base addresses */
tushki7 0:60d829a0353a 4547 /** Peripheral LPUART0 base address */
tushki7 0:60d829a0353a 4548 #define LPUART0_BASE (0x40054000u)
tushki7 0:60d829a0353a 4549 /** Peripheral LPUART0 base pointer */
tushki7 0:60d829a0353a 4550 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
tushki7 0:60d829a0353a 4551 #define LPUART0_BASE_PTR (LPUART0)
tushki7 0:60d829a0353a 4552 /** Peripheral LPUART1 base address */
tushki7 0:60d829a0353a 4553 #define LPUART1_BASE (0x40055000u)
tushki7 0:60d829a0353a 4554 /** Peripheral LPUART1 base pointer */
tushki7 0:60d829a0353a 4555 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
tushki7 0:60d829a0353a 4556 #define LPUART1_BASE_PTR (LPUART1)
tushki7 0:60d829a0353a 4557 /** Array initializer of LPUART peripheral base addresses */
tushki7 0:60d829a0353a 4558 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
tushki7 0:60d829a0353a 4559 /** Array initializer of LPUART peripheral base pointers */
tushki7 0:60d829a0353a 4560 #define LPUART_BASE_PTRS { LPUART0, LPUART1 }
tushki7 0:60d829a0353a 4561 /** Interrupt vectors for the LPUART peripheral type */
tushki7 0:60d829a0353a 4562 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn }
tushki7 0:60d829a0353a 4563 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn }
tushki7 0:60d829a0353a 4564
tushki7 0:60d829a0353a 4565 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4566 -- LPUART - Register accessor macros
tushki7 0:60d829a0353a 4567 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4568
tushki7 0:60d829a0353a 4569 /*!
tushki7 0:60d829a0353a 4570 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
tushki7 0:60d829a0353a 4571 * @{
tushki7 0:60d829a0353a 4572 */
tushki7 0:60d829a0353a 4573
tushki7 0:60d829a0353a 4574
tushki7 0:60d829a0353a 4575 /* LPUART - Register instance definitions */
tushki7 0:60d829a0353a 4576 /* LPUART0 */
tushki7 0:60d829a0353a 4577 #define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
tushki7 0:60d829a0353a 4578 #define LPUART0_STAT LPUART_STAT_REG(LPUART0)
tushki7 0:60d829a0353a 4579 #define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
tushki7 0:60d829a0353a 4580 #define LPUART0_DATA LPUART_DATA_REG(LPUART0)
tushki7 0:60d829a0353a 4581 #define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
tushki7 0:60d829a0353a 4582 /* LPUART1 */
tushki7 0:60d829a0353a 4583 #define LPUART1_BAUD LPUART_BAUD_REG(LPUART1)
tushki7 0:60d829a0353a 4584 #define LPUART1_STAT LPUART_STAT_REG(LPUART1)
tushki7 0:60d829a0353a 4585 #define LPUART1_CTRL LPUART_CTRL_REG(LPUART1)
tushki7 0:60d829a0353a 4586 #define LPUART1_DATA LPUART_DATA_REG(LPUART1)
tushki7 0:60d829a0353a 4587 #define LPUART1_MATCH LPUART_MATCH_REG(LPUART1)
tushki7 0:60d829a0353a 4588
tushki7 0:60d829a0353a 4589 /*!
tushki7 0:60d829a0353a 4590 * @}
tushki7 0:60d829a0353a 4591 */ /* end of group LPUART_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4592
tushki7 0:60d829a0353a 4593
tushki7 0:60d829a0353a 4594 /*!
tushki7 0:60d829a0353a 4595 * @}
tushki7 0:60d829a0353a 4596 */ /* end of group LPUART_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 4597
tushki7 0:60d829a0353a 4598
tushki7 0:60d829a0353a 4599 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4600 -- MCG Peripheral Access Layer
tushki7 0:60d829a0353a 4601 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4602
tushki7 0:60d829a0353a 4603 /*!
tushki7 0:60d829a0353a 4604 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
tushki7 0:60d829a0353a 4605 * @{
tushki7 0:60d829a0353a 4606 */
tushki7 0:60d829a0353a 4607
tushki7 0:60d829a0353a 4608 /** MCG - Register Layout Typedef */
tushki7 0:60d829a0353a 4609 typedef struct {
tushki7 0:60d829a0353a 4610 __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
tushki7 0:60d829a0353a 4611 __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
tushki7 0:60d829a0353a 4612 uint8_t RESERVED_0[4];
tushki7 0:60d829a0353a 4613 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
tushki7 0:60d829a0353a 4614 uint8_t RESERVED_1[1];
tushki7 0:60d829a0353a 4615 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
tushki7 0:60d829a0353a 4616 uint8_t RESERVED_2[11];
tushki7 0:60d829a0353a 4617 __I uint8_t HCTRIM; /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
tushki7 0:60d829a0353a 4618 __I uint8_t HTTRIM; /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
tushki7 0:60d829a0353a 4619 __I uint8_t HFTRIM; /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
tushki7 0:60d829a0353a 4620 uint8_t RESERVED_3[1];
tushki7 0:60d829a0353a 4621 __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
tushki7 0:60d829a0353a 4622 __I uint8_t LTRIMRNG; /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
tushki7 0:60d829a0353a 4623 __I uint8_t LFTRIM; /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
tushki7 0:60d829a0353a 4624 __I uint8_t LSTRIM; /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
tushki7 0:60d829a0353a 4625 } MCG_Type, *MCG_MemMapPtr;
tushki7 0:60d829a0353a 4626
tushki7 0:60d829a0353a 4627 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4628 -- MCG - Register accessor macros
tushki7 0:60d829a0353a 4629 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4630
tushki7 0:60d829a0353a 4631 /*!
tushki7 0:60d829a0353a 4632 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
tushki7 0:60d829a0353a 4633 * @{
tushki7 0:60d829a0353a 4634 */
tushki7 0:60d829a0353a 4635
tushki7 0:60d829a0353a 4636
tushki7 0:60d829a0353a 4637 /* MCG - Register accessors */
tushki7 0:60d829a0353a 4638 #define MCG_C1_REG(base) ((base)->C1)
tushki7 0:60d829a0353a 4639 #define MCG_C2_REG(base) ((base)->C2)
tushki7 0:60d829a0353a 4640 #define MCG_S_REG(base) ((base)->S)
tushki7 0:60d829a0353a 4641 #define MCG_SC_REG(base) ((base)->SC)
tushki7 0:60d829a0353a 4642 #define MCG_HCTRIM_REG(base) ((base)->HCTRIM)
tushki7 0:60d829a0353a 4643 #define MCG_HTTRIM_REG(base) ((base)->HTTRIM)
tushki7 0:60d829a0353a 4644 #define MCG_HFTRIM_REG(base) ((base)->HFTRIM)
tushki7 0:60d829a0353a 4645 #define MCG_MC_REG(base) ((base)->MC)
tushki7 0:60d829a0353a 4646 #define MCG_LTRIMRNG_REG(base) ((base)->LTRIMRNG)
tushki7 0:60d829a0353a 4647 #define MCG_LFTRIM_REG(base) ((base)->LFTRIM)
tushki7 0:60d829a0353a 4648 #define MCG_LSTRIM_REG(base) ((base)->LSTRIM)
tushki7 0:60d829a0353a 4649
tushki7 0:60d829a0353a 4650 /*!
tushki7 0:60d829a0353a 4651 * @}
tushki7 0:60d829a0353a 4652 */ /* end of group MCG_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4653
tushki7 0:60d829a0353a 4654
tushki7 0:60d829a0353a 4655 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4656 -- MCG Register Masks
tushki7 0:60d829a0353a 4657 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4658
tushki7 0:60d829a0353a 4659 /*!
tushki7 0:60d829a0353a 4660 * @addtogroup MCG_Register_Masks MCG Register Masks
tushki7 0:60d829a0353a 4661 * @{
tushki7 0:60d829a0353a 4662 */
tushki7 0:60d829a0353a 4663
tushki7 0:60d829a0353a 4664 /* C1 Bit Fields */
tushki7 0:60d829a0353a 4665 #define MCG_C1_IREFSTEN_MASK 0x1u
tushki7 0:60d829a0353a 4666 #define MCG_C1_IREFSTEN_SHIFT 0
tushki7 0:60d829a0353a 4667 #define MCG_C1_IRCLKEN_MASK 0x2u
tushki7 0:60d829a0353a 4668 #define MCG_C1_IRCLKEN_SHIFT 1
tushki7 0:60d829a0353a 4669 #define MCG_C1_CLKS_MASK 0xC0u
tushki7 0:60d829a0353a 4670 #define MCG_C1_CLKS_SHIFT 6
tushki7 0:60d829a0353a 4671 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
tushki7 0:60d829a0353a 4672 /* C2 Bit Fields */
tushki7 0:60d829a0353a 4673 #define MCG_C2_IRCS_MASK 0x1u
tushki7 0:60d829a0353a 4674 #define MCG_C2_IRCS_SHIFT 0
tushki7 0:60d829a0353a 4675 #define MCG_C2_EREFS0_MASK 0x4u
tushki7 0:60d829a0353a 4676 #define MCG_C2_EREFS0_SHIFT 2
tushki7 0:60d829a0353a 4677 #define MCG_C2_HGO0_MASK 0x8u
tushki7 0:60d829a0353a 4678 #define MCG_C2_HGO0_SHIFT 3
tushki7 0:60d829a0353a 4679 #define MCG_C2_RANGE0_MASK 0x30u
tushki7 0:60d829a0353a 4680 #define MCG_C2_RANGE0_SHIFT 4
tushki7 0:60d829a0353a 4681 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
tushki7 0:60d829a0353a 4682 /* S Bit Fields */
tushki7 0:60d829a0353a 4683 #define MCG_S_OSCINIT0_MASK 0x2u
tushki7 0:60d829a0353a 4684 #define MCG_S_OSCINIT0_SHIFT 1
tushki7 0:60d829a0353a 4685 #define MCG_S_CLKST_MASK 0xCu
tushki7 0:60d829a0353a 4686 #define MCG_S_CLKST_SHIFT 2
tushki7 0:60d829a0353a 4687 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
tushki7 0:60d829a0353a 4688 /* SC Bit Fields */
tushki7 0:60d829a0353a 4689 #define MCG_SC_FCRDIV_MASK 0xEu
tushki7 0:60d829a0353a 4690 #define MCG_SC_FCRDIV_SHIFT 1
tushki7 0:60d829a0353a 4691 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
tushki7 0:60d829a0353a 4692 /* HCTRIM Bit Fields */
tushki7 0:60d829a0353a 4693 #define MCG_HCTRIM_COARSE_TRIM_MASK 0x3Fu
tushki7 0:60d829a0353a 4694 #define MCG_HCTRIM_COARSE_TRIM_SHIFT 0
tushki7 0:60d829a0353a 4695 #define MCG_HCTRIM_COARSE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HCTRIM_COARSE_TRIM_SHIFT))&MCG_HCTRIM_COARSE_TRIM_MASK)
tushki7 0:60d829a0353a 4696 /* HTTRIM Bit Fields */
tushki7 0:60d829a0353a 4697 #define MCG_HTTRIM_TEMPCO_TRIM_MASK 0x1Fu
tushki7 0:60d829a0353a 4698 #define MCG_HTTRIM_TEMPCO_TRIM_SHIFT 0
tushki7 0:60d829a0353a 4699 #define MCG_HTTRIM_TEMPCO_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HTTRIM_TEMPCO_TRIM_SHIFT))&MCG_HTTRIM_TEMPCO_TRIM_MASK)
tushki7 0:60d829a0353a 4700 /* HFTRIM Bit Fields */
tushki7 0:60d829a0353a 4701 #define MCG_HFTRIM_FINE_TRIM_MASK 0x7Fu
tushki7 0:60d829a0353a 4702 #define MCG_HFTRIM_FINE_TRIM_SHIFT 0
tushki7 0:60d829a0353a 4703 #define MCG_HFTRIM_FINE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HFTRIM_FINE_TRIM_SHIFT))&MCG_HFTRIM_FINE_TRIM_MASK)
tushki7 0:60d829a0353a 4704 /* MC Bit Fields */
tushki7 0:60d829a0353a 4705 #define MCG_MC_LIRC_DIV2_MASK 0x7u
tushki7 0:60d829a0353a 4706 #define MCG_MC_LIRC_DIV2_SHIFT 0
tushki7 0:60d829a0353a 4707 #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x))<<MCG_MC_LIRC_DIV2_SHIFT))&MCG_MC_LIRC_DIV2_MASK)
tushki7 0:60d829a0353a 4708 #define MCG_MC_HIRCEN_MASK 0x80u
tushki7 0:60d829a0353a 4709 #define MCG_MC_HIRCEN_SHIFT 7
tushki7 0:60d829a0353a 4710 /* LTRIMRNG Bit Fields */
tushki7 0:60d829a0353a 4711 #define MCG_LTRIMRNG_STRIMRNG_MASK 0x3u
tushki7 0:60d829a0353a 4712 #define MCG_LTRIMRNG_STRIMRNG_SHIFT 0
tushki7 0:60d829a0353a 4713 #define MCG_LTRIMRNG_STRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_STRIMRNG_SHIFT))&MCG_LTRIMRNG_STRIMRNG_MASK)
tushki7 0:60d829a0353a 4714 #define MCG_LTRIMRNG_FTRIMRNG_MASK 0xCu
tushki7 0:60d829a0353a 4715 #define MCG_LTRIMRNG_FTRIMRNG_SHIFT 2
tushki7 0:60d829a0353a 4716 #define MCG_LTRIMRNG_FTRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_FTRIMRNG_SHIFT))&MCG_LTRIMRNG_FTRIMRNG_MASK)
tushki7 0:60d829a0353a 4717 /* LFTRIM Bit Fields */
tushki7 0:60d829a0353a 4718 #define MCG_LFTRIM_LIRC_FTRIM_MASK 0x7Fu
tushki7 0:60d829a0353a 4719 #define MCG_LFTRIM_LIRC_FTRIM_SHIFT 0
tushki7 0:60d829a0353a 4720 #define MCG_LFTRIM_LIRC_FTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LFTRIM_LIRC_FTRIM_SHIFT))&MCG_LFTRIM_LIRC_FTRIM_MASK)
tushki7 0:60d829a0353a 4721 /* LSTRIM Bit Fields */
tushki7 0:60d829a0353a 4722 #define MCG_LSTRIM_LIRC_STRIM_MASK 0x7Fu
tushki7 0:60d829a0353a 4723 #define MCG_LSTRIM_LIRC_STRIM_SHIFT 0
tushki7 0:60d829a0353a 4724 #define MCG_LSTRIM_LIRC_STRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LSTRIM_LIRC_STRIM_SHIFT))&MCG_LSTRIM_LIRC_STRIM_MASK)
tushki7 0:60d829a0353a 4725
tushki7 0:60d829a0353a 4726 /*!
tushki7 0:60d829a0353a 4727 * @}
tushki7 0:60d829a0353a 4728 */ /* end of group MCG_Register_Masks */
tushki7 0:60d829a0353a 4729
tushki7 0:60d829a0353a 4730
tushki7 0:60d829a0353a 4731 /* MCG - Peripheral instance base addresses */
tushki7 0:60d829a0353a 4732 /** Peripheral MCG base address */
tushki7 0:60d829a0353a 4733 #define MCG_BASE (0x40064000u)
tushki7 0:60d829a0353a 4734 /** Peripheral MCG base pointer */
tushki7 0:60d829a0353a 4735 #define MCG ((MCG_Type *)MCG_BASE)
tushki7 0:60d829a0353a 4736 #define MCG_BASE_PTR (MCG)
tushki7 0:60d829a0353a 4737 /** Array initializer of MCG peripheral base addresses */
tushki7 0:60d829a0353a 4738 #define MCG_BASE_ADDRS { MCG_BASE }
tushki7 0:60d829a0353a 4739 /** Array initializer of MCG peripheral base pointers */
tushki7 0:60d829a0353a 4740 #define MCG_BASE_PTRS { MCG }
tushki7 0:60d829a0353a 4741
tushki7 0:60d829a0353a 4742 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4743 -- MCG - Register accessor macros
tushki7 0:60d829a0353a 4744 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4745
tushki7 0:60d829a0353a 4746 /*!
tushki7 0:60d829a0353a 4747 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
tushki7 0:60d829a0353a 4748 * @{
tushki7 0:60d829a0353a 4749 */
tushki7 0:60d829a0353a 4750
tushki7 0:60d829a0353a 4751
tushki7 0:60d829a0353a 4752 /* MCG - Register instance definitions */
tushki7 0:60d829a0353a 4753 /* MCG */
tushki7 0:60d829a0353a 4754 #define MCG_C1 MCG_C1_REG(MCG)
tushki7 0:60d829a0353a 4755 #define MCG_C2 MCG_C2_REG(MCG)
tushki7 0:60d829a0353a 4756 #define MCG_S MCG_S_REG(MCG)
tushki7 0:60d829a0353a 4757 #define MCG_SC MCG_SC_REG(MCG)
tushki7 0:60d829a0353a 4758 #define MCG_HCTRIM MCG_HCTRIM_REG(MCG)
tushki7 0:60d829a0353a 4759 #define MCG_HTTRIM MCG_HTTRIM_REG(MCG)
tushki7 0:60d829a0353a 4760 #define MCG_HFTRIM MCG_HFTRIM_REG(MCG)
tushki7 0:60d829a0353a 4761 #define MCG_MC MCG_MC_REG(MCG)
tushki7 0:60d829a0353a 4762 #define MCG_LTRIMRNG MCG_LTRIMRNG_REG(MCG)
tushki7 0:60d829a0353a 4763 #define MCG_LFTRIM MCG_LFTRIM_REG(MCG)
tushki7 0:60d829a0353a 4764 #define MCG_LSTRIM MCG_LSTRIM_REG(MCG)
tushki7 0:60d829a0353a 4765
tushki7 0:60d829a0353a 4766 /*!
tushki7 0:60d829a0353a 4767 * @}
tushki7 0:60d829a0353a 4768 */ /* end of group MCG_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4769
tushki7 0:60d829a0353a 4770
tushki7 0:60d829a0353a 4771 /*!
tushki7 0:60d829a0353a 4772 * @}
tushki7 0:60d829a0353a 4773 */ /* end of group MCG_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 4774
tushki7 0:60d829a0353a 4775
tushki7 0:60d829a0353a 4776 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4777 -- MCM Peripheral Access Layer
tushki7 0:60d829a0353a 4778 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4779
tushki7 0:60d829a0353a 4780 /*!
tushki7 0:60d829a0353a 4781 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
tushki7 0:60d829a0353a 4782 * @{
tushki7 0:60d829a0353a 4783 */
tushki7 0:60d829a0353a 4784
tushki7 0:60d829a0353a 4785 /** MCM - Register Layout Typedef */
tushki7 0:60d829a0353a 4786 typedef struct {
tushki7 0:60d829a0353a 4787 uint8_t RESERVED_0[8];
tushki7 0:60d829a0353a 4788 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
tushki7 0:60d829a0353a 4789 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
tushki7 0:60d829a0353a 4790 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
tushki7 0:60d829a0353a 4791 uint8_t RESERVED_1[48];
tushki7 0:60d829a0353a 4792 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
tushki7 0:60d829a0353a 4793 } MCM_Type, *MCM_MemMapPtr;
tushki7 0:60d829a0353a 4794
tushki7 0:60d829a0353a 4795 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4796 -- MCM - Register accessor macros
tushki7 0:60d829a0353a 4797 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4798
tushki7 0:60d829a0353a 4799 /*!
tushki7 0:60d829a0353a 4800 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
tushki7 0:60d829a0353a 4801 * @{
tushki7 0:60d829a0353a 4802 */
tushki7 0:60d829a0353a 4803
tushki7 0:60d829a0353a 4804
tushki7 0:60d829a0353a 4805 /* MCM - Register accessors */
tushki7 0:60d829a0353a 4806 #define MCM_PLASC_REG(base) ((base)->PLASC)
tushki7 0:60d829a0353a 4807 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
tushki7 0:60d829a0353a 4808 #define MCM_PLACR_REG(base) ((base)->PLACR)
tushki7 0:60d829a0353a 4809 #define MCM_CPO_REG(base) ((base)->CPO)
tushki7 0:60d829a0353a 4810
tushki7 0:60d829a0353a 4811 /*!
tushki7 0:60d829a0353a 4812 * @}
tushki7 0:60d829a0353a 4813 */ /* end of group MCM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4814
tushki7 0:60d829a0353a 4815
tushki7 0:60d829a0353a 4816 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4817 -- MCM Register Masks
tushki7 0:60d829a0353a 4818 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4819
tushki7 0:60d829a0353a 4820 /*!
tushki7 0:60d829a0353a 4821 * @addtogroup MCM_Register_Masks MCM Register Masks
tushki7 0:60d829a0353a 4822 * @{
tushki7 0:60d829a0353a 4823 */
tushki7 0:60d829a0353a 4824
tushki7 0:60d829a0353a 4825 /* PLASC Bit Fields */
tushki7 0:60d829a0353a 4826 #define MCM_PLASC_ASC_MASK 0xFFu
tushki7 0:60d829a0353a 4827 #define MCM_PLASC_ASC_SHIFT 0
tushki7 0:60d829a0353a 4828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
tushki7 0:60d829a0353a 4829 /* PLAMC Bit Fields */
tushki7 0:60d829a0353a 4830 #define MCM_PLAMC_AMC_MASK 0xFFu
tushki7 0:60d829a0353a 4831 #define MCM_PLAMC_AMC_SHIFT 0
tushki7 0:60d829a0353a 4832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
tushki7 0:60d829a0353a 4833 /* PLACR Bit Fields */
tushki7 0:60d829a0353a 4834 #define MCM_PLACR_ARB_MASK 0x200u
tushki7 0:60d829a0353a 4835 #define MCM_PLACR_ARB_SHIFT 9
tushki7 0:60d829a0353a 4836 #define MCM_PLACR_CFCC_MASK 0x400u
tushki7 0:60d829a0353a 4837 #define MCM_PLACR_CFCC_SHIFT 10
tushki7 0:60d829a0353a 4838 #define MCM_PLACR_DFCDA_MASK 0x800u
tushki7 0:60d829a0353a 4839 #define MCM_PLACR_DFCDA_SHIFT 11
tushki7 0:60d829a0353a 4840 #define MCM_PLACR_DFCIC_MASK 0x1000u
tushki7 0:60d829a0353a 4841 #define MCM_PLACR_DFCIC_SHIFT 12
tushki7 0:60d829a0353a 4842 #define MCM_PLACR_DFCC_MASK 0x2000u
tushki7 0:60d829a0353a 4843 #define MCM_PLACR_DFCC_SHIFT 13
tushki7 0:60d829a0353a 4844 #define MCM_PLACR_EFDS_MASK 0x4000u
tushki7 0:60d829a0353a 4845 #define MCM_PLACR_EFDS_SHIFT 14
tushki7 0:60d829a0353a 4846 #define MCM_PLACR_DFCS_MASK 0x8000u
tushki7 0:60d829a0353a 4847 #define MCM_PLACR_DFCS_SHIFT 15
tushki7 0:60d829a0353a 4848 #define MCM_PLACR_ESFC_MASK 0x10000u
tushki7 0:60d829a0353a 4849 #define MCM_PLACR_ESFC_SHIFT 16
tushki7 0:60d829a0353a 4850 /* CPO Bit Fields */
tushki7 0:60d829a0353a 4851 #define MCM_CPO_CPOREQ_MASK 0x1u
tushki7 0:60d829a0353a 4852 #define MCM_CPO_CPOREQ_SHIFT 0
tushki7 0:60d829a0353a 4853 #define MCM_CPO_CPOACK_MASK 0x2u
tushki7 0:60d829a0353a 4854 #define MCM_CPO_CPOACK_SHIFT 1
tushki7 0:60d829a0353a 4855 #define MCM_CPO_CPOWOI_MASK 0x4u
tushki7 0:60d829a0353a 4856 #define MCM_CPO_CPOWOI_SHIFT 2
tushki7 0:60d829a0353a 4857
tushki7 0:60d829a0353a 4858 /*!
tushki7 0:60d829a0353a 4859 * @}
tushki7 0:60d829a0353a 4860 */ /* end of group MCM_Register_Masks */
tushki7 0:60d829a0353a 4861
tushki7 0:60d829a0353a 4862
tushki7 0:60d829a0353a 4863 /* MCM - Peripheral instance base addresses */
tushki7 0:60d829a0353a 4864 /** Peripheral MCM base address */
tushki7 0:60d829a0353a 4865 #define MCM_BASE (0xF0003000u)
tushki7 0:60d829a0353a 4866 /** Peripheral MCM base pointer */
tushki7 0:60d829a0353a 4867 #define MCM ((MCM_Type *)MCM_BASE)
tushki7 0:60d829a0353a 4868 #define MCM_BASE_PTR (MCM)
tushki7 0:60d829a0353a 4869 /** Array initializer of MCM peripheral base addresses */
tushki7 0:60d829a0353a 4870 #define MCM_BASE_ADDRS { MCM_BASE }
tushki7 0:60d829a0353a 4871 /** Array initializer of MCM peripheral base pointers */
tushki7 0:60d829a0353a 4872 #define MCM_BASE_PTRS { MCM }
tushki7 0:60d829a0353a 4873
tushki7 0:60d829a0353a 4874 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4875 -- MCM - Register accessor macros
tushki7 0:60d829a0353a 4876 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4877
tushki7 0:60d829a0353a 4878 /*!
tushki7 0:60d829a0353a 4879 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
tushki7 0:60d829a0353a 4880 * @{
tushki7 0:60d829a0353a 4881 */
tushki7 0:60d829a0353a 4882
tushki7 0:60d829a0353a 4883
tushki7 0:60d829a0353a 4884 /* MCM - Register instance definitions */
tushki7 0:60d829a0353a 4885 /* MCM */
tushki7 0:60d829a0353a 4886 #define MCM_PLASC MCM_PLASC_REG(MCM)
tushki7 0:60d829a0353a 4887 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
tushki7 0:60d829a0353a 4888 #define MCM_PLACR MCM_PLACR_REG(MCM)
tushki7 0:60d829a0353a 4889 #define MCM_CPO MCM_CPO_REG(MCM)
tushki7 0:60d829a0353a 4890
tushki7 0:60d829a0353a 4891 /*!
tushki7 0:60d829a0353a 4892 * @}
tushki7 0:60d829a0353a 4893 */ /* end of group MCM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4894
tushki7 0:60d829a0353a 4895
tushki7 0:60d829a0353a 4896 /*!
tushki7 0:60d829a0353a 4897 * @}
tushki7 0:60d829a0353a 4898 */ /* end of group MCM_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 4899
tushki7 0:60d829a0353a 4900
tushki7 0:60d829a0353a 4901 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4902 -- MTB Peripheral Access Layer
tushki7 0:60d829a0353a 4903 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4904
tushki7 0:60d829a0353a 4905 /*!
tushki7 0:60d829a0353a 4906 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
tushki7 0:60d829a0353a 4907 * @{
tushki7 0:60d829a0353a 4908 */
tushki7 0:60d829a0353a 4909
tushki7 0:60d829a0353a 4910 /** MTB - Register Layout Typedef */
tushki7 0:60d829a0353a 4911 typedef struct {
tushki7 0:60d829a0353a 4912 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
tushki7 0:60d829a0353a 4913 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
tushki7 0:60d829a0353a 4914 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
tushki7 0:60d829a0353a 4915 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
tushki7 0:60d829a0353a 4916 uint8_t RESERVED_0[3824];
tushki7 0:60d829a0353a 4917 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
tushki7 0:60d829a0353a 4918 uint8_t RESERVED_1[156];
tushki7 0:60d829a0353a 4919 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
tushki7 0:60d829a0353a 4920 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
tushki7 0:60d829a0353a 4921 uint8_t RESERVED_2[8];
tushki7 0:60d829a0353a 4922 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
tushki7 0:60d829a0353a 4923 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
tushki7 0:60d829a0353a 4924 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
tushki7 0:60d829a0353a 4925 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
tushki7 0:60d829a0353a 4926 uint8_t RESERVED_3[8];
tushki7 0:60d829a0353a 4927 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
tushki7 0:60d829a0353a 4928 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
tushki7 0:60d829a0353a 4929 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
tushki7 0:60d829a0353a 4930 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
tushki7 0:60d829a0353a 4931 } MTB_Type, *MTB_MemMapPtr;
tushki7 0:60d829a0353a 4932
tushki7 0:60d829a0353a 4933 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4934 -- MTB - Register accessor macros
tushki7 0:60d829a0353a 4935 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4936
tushki7 0:60d829a0353a 4937 /*!
tushki7 0:60d829a0353a 4938 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
tushki7 0:60d829a0353a 4939 * @{
tushki7 0:60d829a0353a 4940 */
tushki7 0:60d829a0353a 4941
tushki7 0:60d829a0353a 4942
tushki7 0:60d829a0353a 4943 /* MTB - Register accessors */
tushki7 0:60d829a0353a 4944 #define MTB_POSITION_REG(base) ((base)->POSITION)
tushki7 0:60d829a0353a 4945 #define MTB_MASTER_REG(base) ((base)->MASTER)
tushki7 0:60d829a0353a 4946 #define MTB_FLOW_REG(base) ((base)->FLOW)
tushki7 0:60d829a0353a 4947 #define MTB_BASE_REG(base) ((base)->BASE)
tushki7 0:60d829a0353a 4948 #define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
tushki7 0:60d829a0353a 4949 #define MTB_TAGSET_REG(base) ((base)->TAGSET)
tushki7 0:60d829a0353a 4950 #define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
tushki7 0:60d829a0353a 4951 #define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
tushki7 0:60d829a0353a 4952 #define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
tushki7 0:60d829a0353a 4953 #define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
tushki7 0:60d829a0353a 4954 #define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
tushki7 0:60d829a0353a 4955 #define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
tushki7 0:60d829a0353a 4956 #define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
tushki7 0:60d829a0353a 4957 #define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
tushki7 0:60d829a0353a 4958 #define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
tushki7 0:60d829a0353a 4959
tushki7 0:60d829a0353a 4960 /*!
tushki7 0:60d829a0353a 4961 * @}
tushki7 0:60d829a0353a 4962 */ /* end of group MTB_Register_Accessor_Macros */
tushki7 0:60d829a0353a 4963
tushki7 0:60d829a0353a 4964
tushki7 0:60d829a0353a 4965 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 4966 -- MTB Register Masks
tushki7 0:60d829a0353a 4967 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 4968
tushki7 0:60d829a0353a 4969 /*!
tushki7 0:60d829a0353a 4970 * @addtogroup MTB_Register_Masks MTB Register Masks
tushki7 0:60d829a0353a 4971 * @{
tushki7 0:60d829a0353a 4972 */
tushki7 0:60d829a0353a 4973
tushki7 0:60d829a0353a 4974 /* POSITION Bit Fields */
tushki7 0:60d829a0353a 4975 #define MTB_POSITION_WRAP_MASK 0x4u
tushki7 0:60d829a0353a 4976 #define MTB_POSITION_WRAP_SHIFT 2
tushki7 0:60d829a0353a 4977 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
tushki7 0:60d829a0353a 4978 #define MTB_POSITION_POINTER_SHIFT 3
tushki7 0:60d829a0353a 4979 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
tushki7 0:60d829a0353a 4980 /* MASTER Bit Fields */
tushki7 0:60d829a0353a 4981 #define MTB_MASTER_MASK_MASK 0x1Fu
tushki7 0:60d829a0353a 4982 #define MTB_MASTER_MASK_SHIFT 0
tushki7 0:60d829a0353a 4983 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
tushki7 0:60d829a0353a 4984 #define MTB_MASTER_TSTARTEN_MASK 0x20u
tushki7 0:60d829a0353a 4985 #define MTB_MASTER_TSTARTEN_SHIFT 5
tushki7 0:60d829a0353a 4986 #define MTB_MASTER_TSTOPEN_MASK 0x40u
tushki7 0:60d829a0353a 4987 #define MTB_MASTER_TSTOPEN_SHIFT 6
tushki7 0:60d829a0353a 4988 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
tushki7 0:60d829a0353a 4989 #define MTB_MASTER_SFRWPRIV_SHIFT 7
tushki7 0:60d829a0353a 4990 #define MTB_MASTER_RAMPRIV_MASK 0x100u
tushki7 0:60d829a0353a 4991 #define MTB_MASTER_RAMPRIV_SHIFT 8
tushki7 0:60d829a0353a 4992 #define MTB_MASTER_HALTREQ_MASK 0x200u
tushki7 0:60d829a0353a 4993 #define MTB_MASTER_HALTREQ_SHIFT 9
tushki7 0:60d829a0353a 4994 #define MTB_MASTER_EN_MASK 0x80000000u
tushki7 0:60d829a0353a 4995 #define MTB_MASTER_EN_SHIFT 31
tushki7 0:60d829a0353a 4996 /* FLOW Bit Fields */
tushki7 0:60d829a0353a 4997 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
tushki7 0:60d829a0353a 4998 #define MTB_FLOW_AUTOSTOP_SHIFT 0
tushki7 0:60d829a0353a 4999 #define MTB_FLOW_AUTOHALT_MASK 0x2u
tushki7 0:60d829a0353a 5000 #define MTB_FLOW_AUTOHALT_SHIFT 1
tushki7 0:60d829a0353a 5001 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
tushki7 0:60d829a0353a 5002 #define MTB_FLOW_WATERMARK_SHIFT 3
tushki7 0:60d829a0353a 5003 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
tushki7 0:60d829a0353a 5004 /* BASE Bit Fields */
tushki7 0:60d829a0353a 5005 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5006 #define MTB_BASE_BASEADDR_SHIFT 0
tushki7 0:60d829a0353a 5007 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
tushki7 0:60d829a0353a 5008 /* MODECTRL Bit Fields */
tushki7 0:60d829a0353a 5009 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5010 #define MTB_MODECTRL_MODECTRL_SHIFT 0
tushki7 0:60d829a0353a 5011 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
tushki7 0:60d829a0353a 5012 /* TAGSET Bit Fields */
tushki7 0:60d829a0353a 5013 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5014 #define MTB_TAGSET_TAGSET_SHIFT 0
tushki7 0:60d829a0353a 5015 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
tushki7 0:60d829a0353a 5016 /* TAGCLEAR Bit Fields */
tushki7 0:60d829a0353a 5017 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5018 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
tushki7 0:60d829a0353a 5019 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
tushki7 0:60d829a0353a 5020 /* LOCKACCESS Bit Fields */
tushki7 0:60d829a0353a 5021 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5022 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
tushki7 0:60d829a0353a 5023 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
tushki7 0:60d829a0353a 5024 /* LOCKSTAT Bit Fields */
tushki7 0:60d829a0353a 5025 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5026 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
tushki7 0:60d829a0353a 5027 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
tushki7 0:60d829a0353a 5028 /* AUTHSTAT Bit Fields */
tushki7 0:60d829a0353a 5029 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
tushki7 0:60d829a0353a 5030 #define MTB_AUTHSTAT_BIT0_SHIFT 0
tushki7 0:60d829a0353a 5031 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
tushki7 0:60d829a0353a 5032 #define MTB_AUTHSTAT_BIT1_SHIFT 1
tushki7 0:60d829a0353a 5033 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
tushki7 0:60d829a0353a 5034 #define MTB_AUTHSTAT_BIT2_SHIFT 2
tushki7 0:60d829a0353a 5035 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
tushki7 0:60d829a0353a 5036 #define MTB_AUTHSTAT_BIT3_SHIFT 3
tushki7 0:60d829a0353a 5037 /* DEVICEARCH Bit Fields */
tushki7 0:60d829a0353a 5038 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5039 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
tushki7 0:60d829a0353a 5040 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
tushki7 0:60d829a0353a 5041 /* DEVICECFG Bit Fields */
tushki7 0:60d829a0353a 5042 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5043 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
tushki7 0:60d829a0353a 5044 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
tushki7 0:60d829a0353a 5045 /* DEVICETYPID Bit Fields */
tushki7 0:60d829a0353a 5046 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5047 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
tushki7 0:60d829a0353a 5048 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
tushki7 0:60d829a0353a 5049 /* PERIPHID Bit Fields */
tushki7 0:60d829a0353a 5050 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5051 #define MTB_PERIPHID_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 5052 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
tushki7 0:60d829a0353a 5053 /* COMPID Bit Fields */
tushki7 0:60d829a0353a 5054 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5055 #define MTB_COMPID_COMPID_SHIFT 0
tushki7 0:60d829a0353a 5056 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
tushki7 0:60d829a0353a 5057
tushki7 0:60d829a0353a 5058 /*!
tushki7 0:60d829a0353a 5059 * @}
tushki7 0:60d829a0353a 5060 */ /* end of group MTB_Register_Masks */
tushki7 0:60d829a0353a 5061
tushki7 0:60d829a0353a 5062
tushki7 0:60d829a0353a 5063 /* MTB - Peripheral instance base addresses */
tushki7 0:60d829a0353a 5064 /** Peripheral MTB base address */
tushki7 0:60d829a0353a 5065 #define MTB_BASE (0xF0000000u)
tushki7 0:60d829a0353a 5066 /** Peripheral MTB base pointer */
tushki7 0:60d829a0353a 5067 #define MTB ((MTB_Type *)MTB_BASE)
tushki7 0:60d829a0353a 5068 #define MTB_BASE_PTR (MTB)
tushki7 0:60d829a0353a 5069 /** Array initializer of MTB peripheral base addresses */
tushki7 0:60d829a0353a 5070 #define MTB_BASE_ADDRS { MTB_BASE }
tushki7 0:60d829a0353a 5071 /** Array initializer of MTB peripheral base pointers */
tushki7 0:60d829a0353a 5072 #define MTB_BASE_PTRS { MTB }
tushki7 0:60d829a0353a 5073
tushki7 0:60d829a0353a 5074 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5075 -- MTB - Register accessor macros
tushki7 0:60d829a0353a 5076 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5077
tushki7 0:60d829a0353a 5078 /*!
tushki7 0:60d829a0353a 5079 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
tushki7 0:60d829a0353a 5080 * @{
tushki7 0:60d829a0353a 5081 */
tushki7 0:60d829a0353a 5082
tushki7 0:60d829a0353a 5083
tushki7 0:60d829a0353a 5084 /* MTB - Register instance definitions */
tushki7 0:60d829a0353a 5085 /* MTB */
tushki7 0:60d829a0353a 5086 #define MTB_POSITION MTB_POSITION_REG(MTB)
tushki7 0:60d829a0353a 5087 #define MTB_MASTER MTB_MASTER_REG(MTB)
tushki7 0:60d829a0353a 5088 #define MTB_FLOW MTB_FLOW_REG(MTB)
tushki7 0:60d829a0353a 5089 #define MTB_BASEr MTB_BASE_REG(MTB)
tushki7 0:60d829a0353a 5090 #define MTB_MODECTRL MTB_MODECTRL_REG(MTB)
tushki7 0:60d829a0353a 5091 #define MTB_TAGSET MTB_TAGSET_REG(MTB)
tushki7 0:60d829a0353a 5092 #define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB)
tushki7 0:60d829a0353a 5093 #define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB)
tushki7 0:60d829a0353a 5094 #define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB)
tushki7 0:60d829a0353a 5095 #define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB)
tushki7 0:60d829a0353a 5096 #define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB)
tushki7 0:60d829a0353a 5097 #define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB)
tushki7 0:60d829a0353a 5098 #define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB)
tushki7 0:60d829a0353a 5099 #define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB,0)
tushki7 0:60d829a0353a 5100 #define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB,1)
tushki7 0:60d829a0353a 5101 #define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB,2)
tushki7 0:60d829a0353a 5102 #define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB,3)
tushki7 0:60d829a0353a 5103 #define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB,4)
tushki7 0:60d829a0353a 5104 #define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB,5)
tushki7 0:60d829a0353a 5105 #define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB,6)
tushki7 0:60d829a0353a 5106 #define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB,7)
tushki7 0:60d829a0353a 5107 #define MTB_COMPID0 MTB_COMPID_REG(MTB,0)
tushki7 0:60d829a0353a 5108 #define MTB_COMPID1 MTB_COMPID_REG(MTB,1)
tushki7 0:60d829a0353a 5109 #define MTB_COMPID2 MTB_COMPID_REG(MTB,2)
tushki7 0:60d829a0353a 5110 #define MTB_COMPID3 MTB_COMPID_REG(MTB,3)
tushki7 0:60d829a0353a 5111
tushki7 0:60d829a0353a 5112 /* MTB - Register array accessors */
tushki7 0:60d829a0353a 5113 #define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB,index)
tushki7 0:60d829a0353a 5114 #define MTB_COMPID(index) MTB_COMPID_REG(MTB,index)
tushki7 0:60d829a0353a 5115
tushki7 0:60d829a0353a 5116 /*!
tushki7 0:60d829a0353a 5117 * @}
tushki7 0:60d829a0353a 5118 */ /* end of group MTB_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5119
tushki7 0:60d829a0353a 5120
tushki7 0:60d829a0353a 5121 /*!
tushki7 0:60d829a0353a 5122 * @}
tushki7 0:60d829a0353a 5123 */ /* end of group MTB_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 5124
tushki7 0:60d829a0353a 5125
tushki7 0:60d829a0353a 5126 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5127 -- MTBDWT Peripheral Access Layer
tushki7 0:60d829a0353a 5128 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5129
tushki7 0:60d829a0353a 5130 /*!
tushki7 0:60d829a0353a 5131 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
tushki7 0:60d829a0353a 5132 * @{
tushki7 0:60d829a0353a 5133 */
tushki7 0:60d829a0353a 5134
tushki7 0:60d829a0353a 5135 /** MTBDWT - Register Layout Typedef */
tushki7 0:60d829a0353a 5136 typedef struct {
tushki7 0:60d829a0353a 5137 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
tushki7 0:60d829a0353a 5138 uint8_t RESERVED_0[28];
tushki7 0:60d829a0353a 5139 struct { /* offset: 0x20, array step: 0x10 */
tushki7 0:60d829a0353a 5140 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
tushki7 0:60d829a0353a 5141 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
tushki7 0:60d829a0353a 5142 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
tushki7 0:60d829a0353a 5143 uint8_t RESERVED_0[4];
tushki7 0:60d829a0353a 5144 } COMPARATOR[2];
tushki7 0:60d829a0353a 5145 uint8_t RESERVED_1[448];
tushki7 0:60d829a0353a 5146 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
tushki7 0:60d829a0353a 5147 uint8_t RESERVED_2[3524];
tushki7 0:60d829a0353a 5148 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
tushki7 0:60d829a0353a 5149 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
tushki7 0:60d829a0353a 5150 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
tushki7 0:60d829a0353a 5151 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
tushki7 0:60d829a0353a 5152 } MTBDWT_Type, *MTBDWT_MemMapPtr;
tushki7 0:60d829a0353a 5153
tushki7 0:60d829a0353a 5154 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5155 -- MTBDWT - Register accessor macros
tushki7 0:60d829a0353a 5156 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5157
tushki7 0:60d829a0353a 5158 /*!
tushki7 0:60d829a0353a 5159 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
tushki7 0:60d829a0353a 5160 * @{
tushki7 0:60d829a0353a 5161 */
tushki7 0:60d829a0353a 5162
tushki7 0:60d829a0353a 5163
tushki7 0:60d829a0353a 5164 /* MTBDWT - Register accessors */
tushki7 0:60d829a0353a 5165 #define MTBDWT_CTRL_REG(base) ((base)->CTRL)
tushki7 0:60d829a0353a 5166 #define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
tushki7 0:60d829a0353a 5167 #define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
tushki7 0:60d829a0353a 5168 #define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT)
tushki7 0:60d829a0353a 5169 #define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL)
tushki7 0:60d829a0353a 5170 #define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG)
tushki7 0:60d829a0353a 5171 #define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
tushki7 0:60d829a0353a 5172 #define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
tushki7 0:60d829a0353a 5173 #define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index])
tushki7 0:60d829a0353a 5174
tushki7 0:60d829a0353a 5175 /*!
tushki7 0:60d829a0353a 5176 * @}
tushki7 0:60d829a0353a 5177 */ /* end of group MTBDWT_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5178
tushki7 0:60d829a0353a 5179
tushki7 0:60d829a0353a 5180 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5181 -- MTBDWT Register Masks
tushki7 0:60d829a0353a 5182 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5183
tushki7 0:60d829a0353a 5184 /*!
tushki7 0:60d829a0353a 5185 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
tushki7 0:60d829a0353a 5186 * @{
tushki7 0:60d829a0353a 5187 */
tushki7 0:60d829a0353a 5188
tushki7 0:60d829a0353a 5189 /* CTRL Bit Fields */
tushki7 0:60d829a0353a 5190 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
tushki7 0:60d829a0353a 5191 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
tushki7 0:60d829a0353a 5192 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
tushki7 0:60d829a0353a 5193 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
tushki7 0:60d829a0353a 5194 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
tushki7 0:60d829a0353a 5195 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
tushki7 0:60d829a0353a 5196 /* COMP Bit Fields */
tushki7 0:60d829a0353a 5197 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5198 #define MTBDWT_COMP_COMP_SHIFT 0
tushki7 0:60d829a0353a 5199 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
tushki7 0:60d829a0353a 5200 /* MASK Bit Fields */
tushki7 0:60d829a0353a 5201 #define MTBDWT_MASK_MASK_MASK 0x1Fu
tushki7 0:60d829a0353a 5202 #define MTBDWT_MASK_MASK_SHIFT 0
tushki7 0:60d829a0353a 5203 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
tushki7 0:60d829a0353a 5204 /* FCT Bit Fields */
tushki7 0:60d829a0353a 5205 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
tushki7 0:60d829a0353a 5206 #define MTBDWT_FCT_FUNCTION_SHIFT 0
tushki7 0:60d829a0353a 5207 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
tushki7 0:60d829a0353a 5208 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
tushki7 0:60d829a0353a 5209 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
tushki7 0:60d829a0353a 5210 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
tushki7 0:60d829a0353a 5211 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
tushki7 0:60d829a0353a 5212 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
tushki7 0:60d829a0353a 5213 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
tushki7 0:60d829a0353a 5214 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
tushki7 0:60d829a0353a 5215 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
tushki7 0:60d829a0353a 5216 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
tushki7 0:60d829a0353a 5217 #define MTBDWT_FCT_MATCHED_SHIFT 24
tushki7 0:60d829a0353a 5218 /* TBCTRL Bit Fields */
tushki7 0:60d829a0353a 5219 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
tushki7 0:60d829a0353a 5220 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
tushki7 0:60d829a0353a 5221 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
tushki7 0:60d829a0353a 5222 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
tushki7 0:60d829a0353a 5223 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
tushki7 0:60d829a0353a 5224 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
tushki7 0:60d829a0353a 5225 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
tushki7 0:60d829a0353a 5226 /* DEVICECFG Bit Fields */
tushki7 0:60d829a0353a 5227 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5228 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
tushki7 0:60d829a0353a 5229 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
tushki7 0:60d829a0353a 5230 /* DEVICETYPID Bit Fields */
tushki7 0:60d829a0353a 5231 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5232 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
tushki7 0:60d829a0353a 5233 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
tushki7 0:60d829a0353a 5234 /* PERIPHID Bit Fields */
tushki7 0:60d829a0353a 5235 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5236 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 5237 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
tushki7 0:60d829a0353a 5238 /* COMPID Bit Fields */
tushki7 0:60d829a0353a 5239 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5240 #define MTBDWT_COMPID_COMPID_SHIFT 0
tushki7 0:60d829a0353a 5241 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
tushki7 0:60d829a0353a 5242
tushki7 0:60d829a0353a 5243 /*!
tushki7 0:60d829a0353a 5244 * @}
tushki7 0:60d829a0353a 5245 */ /* end of group MTBDWT_Register_Masks */
tushki7 0:60d829a0353a 5246
tushki7 0:60d829a0353a 5247
tushki7 0:60d829a0353a 5248 /* MTBDWT - Peripheral instance base addresses */
tushki7 0:60d829a0353a 5249 /** Peripheral MTBDWT base address */
tushki7 0:60d829a0353a 5250 #define MTBDWT_BASE (0xF0001000u)
tushki7 0:60d829a0353a 5251 /** Peripheral MTBDWT base pointer */
tushki7 0:60d829a0353a 5252 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
tushki7 0:60d829a0353a 5253 #define MTBDWT_BASE_PTR (MTBDWT)
tushki7 0:60d829a0353a 5254 /** Array initializer of MTBDWT peripheral base addresses */
tushki7 0:60d829a0353a 5255 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
tushki7 0:60d829a0353a 5256 /** Array initializer of MTBDWT peripheral base pointers */
tushki7 0:60d829a0353a 5257 #define MTBDWT_BASE_PTRS { MTBDWT }
tushki7 0:60d829a0353a 5258
tushki7 0:60d829a0353a 5259 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5260 -- MTBDWT - Register accessor macros
tushki7 0:60d829a0353a 5261 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5262
tushki7 0:60d829a0353a 5263 /*!
tushki7 0:60d829a0353a 5264 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
tushki7 0:60d829a0353a 5265 * @{
tushki7 0:60d829a0353a 5266 */
tushki7 0:60d829a0353a 5267
tushki7 0:60d829a0353a 5268
tushki7 0:60d829a0353a 5269 /* MTBDWT - Register instance definitions */
tushki7 0:60d829a0353a 5270 /* MTBDWT */
tushki7 0:60d829a0353a 5271 #define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT)
tushki7 0:60d829a0353a 5272 #define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT,0)
tushki7 0:60d829a0353a 5273 #define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT,0)
tushki7 0:60d829a0353a 5274 #define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT,0)
tushki7 0:60d829a0353a 5275 #define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT,1)
tushki7 0:60d829a0353a 5276 #define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT,1)
tushki7 0:60d829a0353a 5277 #define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT,1)
tushki7 0:60d829a0353a 5278 #define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT)
tushki7 0:60d829a0353a 5279 #define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT)
tushki7 0:60d829a0353a 5280 #define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT)
tushki7 0:60d829a0353a 5281 #define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT,0)
tushki7 0:60d829a0353a 5282 #define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT,1)
tushki7 0:60d829a0353a 5283 #define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT,2)
tushki7 0:60d829a0353a 5284 #define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT,3)
tushki7 0:60d829a0353a 5285 #define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT,4)
tushki7 0:60d829a0353a 5286 #define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT,5)
tushki7 0:60d829a0353a 5287 #define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT,6)
tushki7 0:60d829a0353a 5288 #define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT,7)
tushki7 0:60d829a0353a 5289 #define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT,0)
tushki7 0:60d829a0353a 5290 #define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT,1)
tushki7 0:60d829a0353a 5291 #define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT,2)
tushki7 0:60d829a0353a 5292 #define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT,3)
tushki7 0:60d829a0353a 5293
tushki7 0:60d829a0353a 5294 /* MTBDWT - Register array accessors */
tushki7 0:60d829a0353a 5295 #define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT,index)
tushki7 0:60d829a0353a 5296 #define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT,index)
tushki7 0:60d829a0353a 5297 #define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT,index)
tushki7 0:60d829a0353a 5298 #define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT,index)
tushki7 0:60d829a0353a 5299 #define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT,index)
tushki7 0:60d829a0353a 5300
tushki7 0:60d829a0353a 5301 /*!
tushki7 0:60d829a0353a 5302 * @}
tushki7 0:60d829a0353a 5303 */ /* end of group MTBDWT_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5304
tushki7 0:60d829a0353a 5305
tushki7 0:60d829a0353a 5306 /*!
tushki7 0:60d829a0353a 5307 * @}
tushki7 0:60d829a0353a 5308 */ /* end of group MTBDWT_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 5309
tushki7 0:60d829a0353a 5310
tushki7 0:60d829a0353a 5311 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5312 -- NV Peripheral Access Layer
tushki7 0:60d829a0353a 5313 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5314
tushki7 0:60d829a0353a 5315 /*!
tushki7 0:60d829a0353a 5316 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
tushki7 0:60d829a0353a 5317 * @{
tushki7 0:60d829a0353a 5318 */
tushki7 0:60d829a0353a 5319
tushki7 0:60d829a0353a 5320 /** NV - Register Layout Typedef */
tushki7 0:60d829a0353a 5321 typedef struct {
tushki7 0:60d829a0353a 5322 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
tushki7 0:60d829a0353a 5323 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
tushki7 0:60d829a0353a 5324 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
tushki7 0:60d829a0353a 5325 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
tushki7 0:60d829a0353a 5326 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
tushki7 0:60d829a0353a 5327 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
tushki7 0:60d829a0353a 5328 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
tushki7 0:60d829a0353a 5329 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
tushki7 0:60d829a0353a 5330 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
tushki7 0:60d829a0353a 5331 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
tushki7 0:60d829a0353a 5332 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
tushki7 0:60d829a0353a 5333 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
tushki7 0:60d829a0353a 5334 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
tushki7 0:60d829a0353a 5335 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
tushki7 0:60d829a0353a 5336 } NV_Type, *NV_MemMapPtr;
tushki7 0:60d829a0353a 5337
tushki7 0:60d829a0353a 5338 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5339 -- NV - Register accessor macros
tushki7 0:60d829a0353a 5340 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5341
tushki7 0:60d829a0353a 5342 /*!
tushki7 0:60d829a0353a 5343 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
tushki7 0:60d829a0353a 5344 * @{
tushki7 0:60d829a0353a 5345 */
tushki7 0:60d829a0353a 5346
tushki7 0:60d829a0353a 5347
tushki7 0:60d829a0353a 5348 /* NV - Register accessors */
tushki7 0:60d829a0353a 5349 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
tushki7 0:60d829a0353a 5350 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
tushki7 0:60d829a0353a 5351 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
tushki7 0:60d829a0353a 5352 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
tushki7 0:60d829a0353a 5353 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
tushki7 0:60d829a0353a 5354 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
tushki7 0:60d829a0353a 5355 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
tushki7 0:60d829a0353a 5356 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
tushki7 0:60d829a0353a 5357 #define NV_FPROT3_REG(base) ((base)->FPROT3)
tushki7 0:60d829a0353a 5358 #define NV_FPROT2_REG(base) ((base)->FPROT2)
tushki7 0:60d829a0353a 5359 #define NV_FPROT1_REG(base) ((base)->FPROT1)
tushki7 0:60d829a0353a 5360 #define NV_FPROT0_REG(base) ((base)->FPROT0)
tushki7 0:60d829a0353a 5361 #define NV_FSEC_REG(base) ((base)->FSEC)
tushki7 0:60d829a0353a 5362 #define NV_FOPT_REG(base) ((base)->FOPT)
tushki7 0:60d829a0353a 5363
tushki7 0:60d829a0353a 5364 /*!
tushki7 0:60d829a0353a 5365 * @}
tushki7 0:60d829a0353a 5366 */ /* end of group NV_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5367
tushki7 0:60d829a0353a 5368
tushki7 0:60d829a0353a 5369 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5370 -- NV Register Masks
tushki7 0:60d829a0353a 5371 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5372
tushki7 0:60d829a0353a 5373 /*!
tushki7 0:60d829a0353a 5374 * @addtogroup NV_Register_Masks NV Register Masks
tushki7 0:60d829a0353a 5375 * @{
tushki7 0:60d829a0353a 5376 */
tushki7 0:60d829a0353a 5377
tushki7 0:60d829a0353a 5378 /* BACKKEY3 Bit Fields */
tushki7 0:60d829a0353a 5379 #define NV_BACKKEY3_KEY_MASK 0xFFu
tushki7 0:60d829a0353a 5380 #define NV_BACKKEY3_KEY_SHIFT 0
tushki7 0:60d829a0353a 5381 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
tushki7 0:60d829a0353a 5382 /* BACKKEY2 Bit Fields */
tushki7 0:60d829a0353a 5383 #define NV_BACKKEY2_KEY_MASK 0xFFu
tushki7 0:60d829a0353a 5384 #define NV_BACKKEY2_KEY_SHIFT 0
tushki7 0:60d829a0353a 5385 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
tushki7 0:60d829a0353a 5386 /* BACKKEY1 Bit Fields */
tushki7 0:60d829a0353a 5387 #define NV_BACKKEY1_KEY_MASK 0xFFu
tushki7 0:60d829a0353a 5388 #define NV_BACKKEY1_KEY_SHIFT 0
tushki7 0:60d829a0353a 5389 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
tushki7 0:60d829a0353a 5390 /* BACKKEY0 Bit Fields */
tushki7 0:60d829a0353a 5391 #define NV_BACKKEY0_KEY_MASK 0xFFu
tushki7 0:60d829a0353a 5392 #define NV_BACKKEY0_KEY_SHIFT 0
tushki7 0:60d829a0353a 5393 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
tushki7 0:60d829a0353a 5394 /* BACKKEY7 Bit Fields */
tushki7 0:60d829a0353a 5395 #define NV_BACKKEY7_KEY_MASK 0xFFu
tushki7 0:60d829a0353a 5396 #define NV_BACKKEY7_KEY_SHIFT 0
tushki7 0:60d829a0353a 5397 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
tushki7 0:60d829a0353a 5398 /* BACKKEY6 Bit Fields */
tushki7 0:60d829a0353a 5399 #define NV_BACKKEY6_KEY_MASK 0xFFu
tushki7 0:60d829a0353a 5400 #define NV_BACKKEY6_KEY_SHIFT 0
tushki7 0:60d829a0353a 5401 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
tushki7 0:60d829a0353a 5402 /* BACKKEY5 Bit Fields */
tushki7 0:60d829a0353a 5403 #define NV_BACKKEY5_KEY_MASK 0xFFu
tushki7 0:60d829a0353a 5404 #define NV_BACKKEY5_KEY_SHIFT 0
tushki7 0:60d829a0353a 5405 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
tushki7 0:60d829a0353a 5406 /* BACKKEY4 Bit Fields */
tushki7 0:60d829a0353a 5407 #define NV_BACKKEY4_KEY_MASK 0xFFu
tushki7 0:60d829a0353a 5408 #define NV_BACKKEY4_KEY_SHIFT 0
tushki7 0:60d829a0353a 5409 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
tushki7 0:60d829a0353a 5410 /* FPROT3 Bit Fields */
tushki7 0:60d829a0353a 5411 #define NV_FPROT3_PROT_MASK 0xFFu
tushki7 0:60d829a0353a 5412 #define NV_FPROT3_PROT_SHIFT 0
tushki7 0:60d829a0353a 5413 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
tushki7 0:60d829a0353a 5414 /* FPROT2 Bit Fields */
tushki7 0:60d829a0353a 5415 #define NV_FPROT2_PROT_MASK 0xFFu
tushki7 0:60d829a0353a 5416 #define NV_FPROT2_PROT_SHIFT 0
tushki7 0:60d829a0353a 5417 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
tushki7 0:60d829a0353a 5418 /* FPROT1 Bit Fields */
tushki7 0:60d829a0353a 5419 #define NV_FPROT1_PROT_MASK 0xFFu
tushki7 0:60d829a0353a 5420 #define NV_FPROT1_PROT_SHIFT 0
tushki7 0:60d829a0353a 5421 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
tushki7 0:60d829a0353a 5422 /* FPROT0 Bit Fields */
tushki7 0:60d829a0353a 5423 #define NV_FPROT0_PROT_MASK 0xFFu
tushki7 0:60d829a0353a 5424 #define NV_FPROT0_PROT_SHIFT 0
tushki7 0:60d829a0353a 5425 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
tushki7 0:60d829a0353a 5426 /* FSEC Bit Fields */
tushki7 0:60d829a0353a 5427 #define NV_FSEC_SEC_MASK 0x3u
tushki7 0:60d829a0353a 5428 #define NV_FSEC_SEC_SHIFT 0
tushki7 0:60d829a0353a 5429 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
tushki7 0:60d829a0353a 5430 #define NV_FSEC_FSLACC_MASK 0xCu
tushki7 0:60d829a0353a 5431 #define NV_FSEC_FSLACC_SHIFT 2
tushki7 0:60d829a0353a 5432 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
tushki7 0:60d829a0353a 5433 #define NV_FSEC_MEEN_MASK 0x30u
tushki7 0:60d829a0353a 5434 #define NV_FSEC_MEEN_SHIFT 4
tushki7 0:60d829a0353a 5435 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
tushki7 0:60d829a0353a 5436 #define NV_FSEC_KEYEN_MASK 0xC0u
tushki7 0:60d829a0353a 5437 #define NV_FSEC_KEYEN_SHIFT 6
tushki7 0:60d829a0353a 5438 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
tushki7 0:60d829a0353a 5439 /* FOPT Bit Fields */
tushki7 0:60d829a0353a 5440 #define NV_FOPT_LPBOOT0_MASK 0x1u
tushki7 0:60d829a0353a 5441 #define NV_FOPT_LPBOOT0_SHIFT 0
tushki7 0:60d829a0353a 5442 #define NV_FOPT_BOOTPIN_OPT_MASK 0x2u
tushki7 0:60d829a0353a 5443 #define NV_FOPT_BOOTPIN_OPT_SHIFT 1
tushki7 0:60d829a0353a 5444 #define NV_FOPT_NMI_DIS_MASK 0x4u
tushki7 0:60d829a0353a 5445 #define NV_FOPT_NMI_DIS_SHIFT 2
tushki7 0:60d829a0353a 5446 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
tushki7 0:60d829a0353a 5447 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
tushki7 0:60d829a0353a 5448 #define NV_FOPT_LPBOOT1_MASK 0x10u
tushki7 0:60d829a0353a 5449 #define NV_FOPT_LPBOOT1_SHIFT 4
tushki7 0:60d829a0353a 5450 #define NV_FOPT_FAST_INIT_MASK 0x20u
tushki7 0:60d829a0353a 5451 #define NV_FOPT_FAST_INIT_SHIFT 5
tushki7 0:60d829a0353a 5452 #define NV_FOPT_BOOTSRC_SEL_MASK 0xC0u
tushki7 0:60d829a0353a 5453 #define NV_FOPT_BOOTSRC_SEL_SHIFT 6
tushki7 0:60d829a0353a 5454 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK)
tushki7 0:60d829a0353a 5455
tushki7 0:60d829a0353a 5456 /*!
tushki7 0:60d829a0353a 5457 * @}
tushki7 0:60d829a0353a 5458 */ /* end of group NV_Register_Masks */
tushki7 0:60d829a0353a 5459
tushki7 0:60d829a0353a 5460
tushki7 0:60d829a0353a 5461 /* NV - Peripheral instance base addresses */
tushki7 0:60d829a0353a 5462 /** Peripheral FTFA_FlashConfig base address */
tushki7 0:60d829a0353a 5463 #define FTFA_FlashConfig_BASE (0x400u)
tushki7 0:60d829a0353a 5464 /** Peripheral FTFA_FlashConfig base pointer */
tushki7 0:60d829a0353a 5465 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
tushki7 0:60d829a0353a 5466 #define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
tushki7 0:60d829a0353a 5467 /** Array initializer of NV peripheral base addresses */
tushki7 0:60d829a0353a 5468 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
tushki7 0:60d829a0353a 5469 /** Array initializer of NV peripheral base pointers */
tushki7 0:60d829a0353a 5470 #define NV_BASE_PTRS { FTFA_FlashConfig }
tushki7 0:60d829a0353a 5471
tushki7 0:60d829a0353a 5472 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5473 -- NV - Register accessor macros
tushki7 0:60d829a0353a 5474 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5475
tushki7 0:60d829a0353a 5476 /*!
tushki7 0:60d829a0353a 5477 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
tushki7 0:60d829a0353a 5478 * @{
tushki7 0:60d829a0353a 5479 */
tushki7 0:60d829a0353a 5480
tushki7 0:60d829a0353a 5481
tushki7 0:60d829a0353a 5482 /* NV - Register instance definitions */
tushki7 0:60d829a0353a 5483 /* FTFA_FlashConfig */
tushki7 0:60d829a0353a 5484 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5485 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5486 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5487 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5488 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5489 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5490 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5491 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5492 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5493 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5494 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5495 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5496 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5497 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
tushki7 0:60d829a0353a 5498
tushki7 0:60d829a0353a 5499 /*!
tushki7 0:60d829a0353a 5500 * @}
tushki7 0:60d829a0353a 5501 */ /* end of group NV_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5502
tushki7 0:60d829a0353a 5503
tushki7 0:60d829a0353a 5504 /*!
tushki7 0:60d829a0353a 5505 * @}
tushki7 0:60d829a0353a 5506 */ /* end of group NV_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 5507
tushki7 0:60d829a0353a 5508
tushki7 0:60d829a0353a 5509 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5510 -- OSC Peripheral Access Layer
tushki7 0:60d829a0353a 5511 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5512
tushki7 0:60d829a0353a 5513 /*!
tushki7 0:60d829a0353a 5514 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
tushki7 0:60d829a0353a 5515 * @{
tushki7 0:60d829a0353a 5516 */
tushki7 0:60d829a0353a 5517
tushki7 0:60d829a0353a 5518 /** OSC - Register Layout Typedef */
tushki7 0:60d829a0353a 5519 typedef struct {
tushki7 0:60d829a0353a 5520 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
tushki7 0:60d829a0353a 5521 } OSC_Type, *OSC_MemMapPtr;
tushki7 0:60d829a0353a 5522
tushki7 0:60d829a0353a 5523 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5524 -- OSC - Register accessor macros
tushki7 0:60d829a0353a 5525 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5526
tushki7 0:60d829a0353a 5527 /*!
tushki7 0:60d829a0353a 5528 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
tushki7 0:60d829a0353a 5529 * @{
tushki7 0:60d829a0353a 5530 */
tushki7 0:60d829a0353a 5531
tushki7 0:60d829a0353a 5532
tushki7 0:60d829a0353a 5533 /* OSC - Register accessors */
tushki7 0:60d829a0353a 5534 #define OSC_CR_REG(base) ((base)->CR)
tushki7 0:60d829a0353a 5535
tushki7 0:60d829a0353a 5536 /*!
tushki7 0:60d829a0353a 5537 * @}
tushki7 0:60d829a0353a 5538 */ /* end of group OSC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5539
tushki7 0:60d829a0353a 5540
tushki7 0:60d829a0353a 5541 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5542 -- OSC Register Masks
tushki7 0:60d829a0353a 5543 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5544
tushki7 0:60d829a0353a 5545 /*!
tushki7 0:60d829a0353a 5546 * @addtogroup OSC_Register_Masks OSC Register Masks
tushki7 0:60d829a0353a 5547 * @{
tushki7 0:60d829a0353a 5548 */
tushki7 0:60d829a0353a 5549
tushki7 0:60d829a0353a 5550 /* CR Bit Fields */
tushki7 0:60d829a0353a 5551 #define OSC_CR_SC16P_MASK 0x1u
tushki7 0:60d829a0353a 5552 #define OSC_CR_SC16P_SHIFT 0
tushki7 0:60d829a0353a 5553 #define OSC_CR_SC8P_MASK 0x2u
tushki7 0:60d829a0353a 5554 #define OSC_CR_SC8P_SHIFT 1
tushki7 0:60d829a0353a 5555 #define OSC_CR_SC4P_MASK 0x4u
tushki7 0:60d829a0353a 5556 #define OSC_CR_SC4P_SHIFT 2
tushki7 0:60d829a0353a 5557 #define OSC_CR_SC2P_MASK 0x8u
tushki7 0:60d829a0353a 5558 #define OSC_CR_SC2P_SHIFT 3
tushki7 0:60d829a0353a 5559 #define OSC_CR_EREFSTEN_MASK 0x20u
tushki7 0:60d829a0353a 5560 #define OSC_CR_EREFSTEN_SHIFT 5
tushki7 0:60d829a0353a 5561 #define OSC_CR_ERCLKEN_MASK 0x80u
tushki7 0:60d829a0353a 5562 #define OSC_CR_ERCLKEN_SHIFT 7
tushki7 0:60d829a0353a 5563
tushki7 0:60d829a0353a 5564 /*!
tushki7 0:60d829a0353a 5565 * @}
tushki7 0:60d829a0353a 5566 */ /* end of group OSC_Register_Masks */
tushki7 0:60d829a0353a 5567
tushki7 0:60d829a0353a 5568
tushki7 0:60d829a0353a 5569 /* OSC - Peripheral instance base addresses */
tushki7 0:60d829a0353a 5570 /** Peripheral OSC0 base address */
tushki7 0:60d829a0353a 5571 #define OSC0_BASE (0x40065000u)
tushki7 0:60d829a0353a 5572 /** Peripheral OSC0 base pointer */
tushki7 0:60d829a0353a 5573 #define OSC0 ((OSC_Type *)OSC0_BASE)
tushki7 0:60d829a0353a 5574 #define OSC0_BASE_PTR (OSC0)
tushki7 0:60d829a0353a 5575 /** Array initializer of OSC peripheral base addresses */
tushki7 0:60d829a0353a 5576 #define OSC_BASE_ADDRS { OSC0_BASE }
tushki7 0:60d829a0353a 5577 /** Array initializer of OSC peripheral base pointers */
tushki7 0:60d829a0353a 5578 #define OSC_BASE_PTRS { OSC0 }
tushki7 0:60d829a0353a 5579
tushki7 0:60d829a0353a 5580 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5581 -- OSC - Register accessor macros
tushki7 0:60d829a0353a 5582 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5583
tushki7 0:60d829a0353a 5584 /*!
tushki7 0:60d829a0353a 5585 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
tushki7 0:60d829a0353a 5586 * @{
tushki7 0:60d829a0353a 5587 */
tushki7 0:60d829a0353a 5588
tushki7 0:60d829a0353a 5589
tushki7 0:60d829a0353a 5590 /* OSC - Register instance definitions */
tushki7 0:60d829a0353a 5591 /* OSC0 */
tushki7 0:60d829a0353a 5592 #define OSC0_CR OSC_CR_REG(OSC0)
tushki7 0:60d829a0353a 5593
tushki7 0:60d829a0353a 5594 /*!
tushki7 0:60d829a0353a 5595 * @}
tushki7 0:60d829a0353a 5596 */ /* end of group OSC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5597
tushki7 0:60d829a0353a 5598
tushki7 0:60d829a0353a 5599 /*!
tushki7 0:60d829a0353a 5600 * @}
tushki7 0:60d829a0353a 5601 */ /* end of group OSC_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 5602
tushki7 0:60d829a0353a 5603
tushki7 0:60d829a0353a 5604 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5605 -- PIT Peripheral Access Layer
tushki7 0:60d829a0353a 5606 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5607
tushki7 0:60d829a0353a 5608 /*!
tushki7 0:60d829a0353a 5609 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
tushki7 0:60d829a0353a 5610 * @{
tushki7 0:60d829a0353a 5611 */
tushki7 0:60d829a0353a 5612
tushki7 0:60d829a0353a 5613 /** PIT - Register Layout Typedef */
tushki7 0:60d829a0353a 5614 typedef struct {
tushki7 0:60d829a0353a 5615 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
tushki7 0:60d829a0353a 5616 uint8_t RESERVED_0[220];
tushki7 0:60d829a0353a 5617 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
tushki7 0:60d829a0353a 5618 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
tushki7 0:60d829a0353a 5619 uint8_t RESERVED_1[24];
tushki7 0:60d829a0353a 5620 struct { /* offset: 0x100, array step: 0x10 */
tushki7 0:60d829a0353a 5621 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
tushki7 0:60d829a0353a 5622 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
tushki7 0:60d829a0353a 5623 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
tushki7 0:60d829a0353a 5624 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
tushki7 0:60d829a0353a 5625 } CHANNEL[2];
tushki7 0:60d829a0353a 5626 } PIT_Type, *PIT_MemMapPtr;
tushki7 0:60d829a0353a 5627
tushki7 0:60d829a0353a 5628 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5629 -- PIT - Register accessor macros
tushki7 0:60d829a0353a 5630 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5631
tushki7 0:60d829a0353a 5632 /*!
tushki7 0:60d829a0353a 5633 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
tushki7 0:60d829a0353a 5634 * @{
tushki7 0:60d829a0353a 5635 */
tushki7 0:60d829a0353a 5636
tushki7 0:60d829a0353a 5637
tushki7 0:60d829a0353a 5638 /* PIT - Register accessors */
tushki7 0:60d829a0353a 5639 #define PIT_MCR_REG(base) ((base)->MCR)
tushki7 0:60d829a0353a 5640 #define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
tushki7 0:60d829a0353a 5641 #define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
tushki7 0:60d829a0353a 5642 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
tushki7 0:60d829a0353a 5643 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
tushki7 0:60d829a0353a 5644 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
tushki7 0:60d829a0353a 5645 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
tushki7 0:60d829a0353a 5646
tushki7 0:60d829a0353a 5647 /*!
tushki7 0:60d829a0353a 5648 * @}
tushki7 0:60d829a0353a 5649 */ /* end of group PIT_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5650
tushki7 0:60d829a0353a 5651
tushki7 0:60d829a0353a 5652 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5653 -- PIT Register Masks
tushki7 0:60d829a0353a 5654 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5655
tushki7 0:60d829a0353a 5656 /*!
tushki7 0:60d829a0353a 5657 * @addtogroup PIT_Register_Masks PIT Register Masks
tushki7 0:60d829a0353a 5658 * @{
tushki7 0:60d829a0353a 5659 */
tushki7 0:60d829a0353a 5660
tushki7 0:60d829a0353a 5661 /* MCR Bit Fields */
tushki7 0:60d829a0353a 5662 #define PIT_MCR_FRZ_MASK 0x1u
tushki7 0:60d829a0353a 5663 #define PIT_MCR_FRZ_SHIFT 0
tushki7 0:60d829a0353a 5664 #define PIT_MCR_MDIS_MASK 0x2u
tushki7 0:60d829a0353a 5665 #define PIT_MCR_MDIS_SHIFT 1
tushki7 0:60d829a0353a 5666 /* LTMR64H Bit Fields */
tushki7 0:60d829a0353a 5667 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5668 #define PIT_LTMR64H_LTH_SHIFT 0
tushki7 0:60d829a0353a 5669 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
tushki7 0:60d829a0353a 5670 /* LTMR64L Bit Fields */
tushki7 0:60d829a0353a 5671 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5672 #define PIT_LTMR64L_LTL_SHIFT 0
tushki7 0:60d829a0353a 5673 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
tushki7 0:60d829a0353a 5674 /* LDVAL Bit Fields */
tushki7 0:60d829a0353a 5675 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5676 #define PIT_LDVAL_TSV_SHIFT 0
tushki7 0:60d829a0353a 5677 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
tushki7 0:60d829a0353a 5678 /* CVAL Bit Fields */
tushki7 0:60d829a0353a 5679 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5680 #define PIT_CVAL_TVL_SHIFT 0
tushki7 0:60d829a0353a 5681 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
tushki7 0:60d829a0353a 5682 /* TCTRL Bit Fields */
tushki7 0:60d829a0353a 5683 #define PIT_TCTRL_TEN_MASK 0x1u
tushki7 0:60d829a0353a 5684 #define PIT_TCTRL_TEN_SHIFT 0
tushki7 0:60d829a0353a 5685 #define PIT_TCTRL_TIE_MASK 0x2u
tushki7 0:60d829a0353a 5686 #define PIT_TCTRL_TIE_SHIFT 1
tushki7 0:60d829a0353a 5687 #define PIT_TCTRL_CHN_MASK 0x4u
tushki7 0:60d829a0353a 5688 #define PIT_TCTRL_CHN_SHIFT 2
tushki7 0:60d829a0353a 5689 /* TFLG Bit Fields */
tushki7 0:60d829a0353a 5690 #define PIT_TFLG_TIF_MASK 0x1u
tushki7 0:60d829a0353a 5691 #define PIT_TFLG_TIF_SHIFT 0
tushki7 0:60d829a0353a 5692
tushki7 0:60d829a0353a 5693 /*!
tushki7 0:60d829a0353a 5694 * @}
tushki7 0:60d829a0353a 5695 */ /* end of group PIT_Register_Masks */
tushki7 0:60d829a0353a 5696
tushki7 0:60d829a0353a 5697
tushki7 0:60d829a0353a 5698 /* PIT - Peripheral instance base addresses */
tushki7 0:60d829a0353a 5699 /** Peripheral PIT base address */
tushki7 0:60d829a0353a 5700 #define PIT_BASE (0x40037000u)
tushki7 0:60d829a0353a 5701 /** Peripheral PIT base pointer */
tushki7 0:60d829a0353a 5702 #define PIT ((PIT_Type *)PIT_BASE)
tushki7 0:60d829a0353a 5703 #define PIT_BASE_PTR (PIT)
tushki7 0:60d829a0353a 5704 /** Array initializer of PIT peripheral base addresses */
tushki7 0:60d829a0353a 5705 #define PIT_BASE_ADDRS { PIT_BASE }
tushki7 0:60d829a0353a 5706 /** Array initializer of PIT peripheral base pointers */
tushki7 0:60d829a0353a 5707 #define PIT_BASE_PTRS { PIT }
tushki7 0:60d829a0353a 5708 /** Interrupt vectors for the PIT peripheral type */
tushki7 0:60d829a0353a 5709 #define PIT_IRQS { PIT_IRQn, PIT_IRQn }
tushki7 0:60d829a0353a 5710
tushki7 0:60d829a0353a 5711 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5712 -- PIT - Register accessor macros
tushki7 0:60d829a0353a 5713 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5714
tushki7 0:60d829a0353a 5715 /*!
tushki7 0:60d829a0353a 5716 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
tushki7 0:60d829a0353a 5717 * @{
tushki7 0:60d829a0353a 5718 */
tushki7 0:60d829a0353a 5719
tushki7 0:60d829a0353a 5720
tushki7 0:60d829a0353a 5721 /* PIT - Register instance definitions */
tushki7 0:60d829a0353a 5722 /* PIT */
tushki7 0:60d829a0353a 5723 #define PIT_MCR PIT_MCR_REG(PIT)
tushki7 0:60d829a0353a 5724 #define PIT_LTMR64H PIT_LTMR64H_REG(PIT)
tushki7 0:60d829a0353a 5725 #define PIT_LTMR64L PIT_LTMR64L_REG(PIT)
tushki7 0:60d829a0353a 5726 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
tushki7 0:60d829a0353a 5727 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
tushki7 0:60d829a0353a 5728 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
tushki7 0:60d829a0353a 5729 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
tushki7 0:60d829a0353a 5730 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
tushki7 0:60d829a0353a 5731 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
tushki7 0:60d829a0353a 5732 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
tushki7 0:60d829a0353a 5733 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
tushki7 0:60d829a0353a 5734
tushki7 0:60d829a0353a 5735 /* PIT - Register array accessors */
tushki7 0:60d829a0353a 5736 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
tushki7 0:60d829a0353a 5737 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
tushki7 0:60d829a0353a 5738 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
tushki7 0:60d829a0353a 5739 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
tushki7 0:60d829a0353a 5740
tushki7 0:60d829a0353a 5741 /*!
tushki7 0:60d829a0353a 5742 * @}
tushki7 0:60d829a0353a 5743 */ /* end of group PIT_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5744
tushki7 0:60d829a0353a 5745
tushki7 0:60d829a0353a 5746 /*!
tushki7 0:60d829a0353a 5747 * @}
tushki7 0:60d829a0353a 5748 */ /* end of group PIT_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 5749
tushki7 0:60d829a0353a 5750
tushki7 0:60d829a0353a 5751 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5752 -- PMC Peripheral Access Layer
tushki7 0:60d829a0353a 5753 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5754
tushki7 0:60d829a0353a 5755 /*!
tushki7 0:60d829a0353a 5756 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
tushki7 0:60d829a0353a 5757 * @{
tushki7 0:60d829a0353a 5758 */
tushki7 0:60d829a0353a 5759
tushki7 0:60d829a0353a 5760 /** PMC - Register Layout Typedef */
tushki7 0:60d829a0353a 5761 typedef struct {
tushki7 0:60d829a0353a 5762 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
tushki7 0:60d829a0353a 5763 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
tushki7 0:60d829a0353a 5764 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
tushki7 0:60d829a0353a 5765 } PMC_Type, *PMC_MemMapPtr;
tushki7 0:60d829a0353a 5766
tushki7 0:60d829a0353a 5767 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5768 -- PMC - Register accessor macros
tushki7 0:60d829a0353a 5769 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5770
tushki7 0:60d829a0353a 5771 /*!
tushki7 0:60d829a0353a 5772 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
tushki7 0:60d829a0353a 5773 * @{
tushki7 0:60d829a0353a 5774 */
tushki7 0:60d829a0353a 5775
tushki7 0:60d829a0353a 5776
tushki7 0:60d829a0353a 5777 /* PMC - Register accessors */
tushki7 0:60d829a0353a 5778 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
tushki7 0:60d829a0353a 5779 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
tushki7 0:60d829a0353a 5780 #define PMC_REGSC_REG(base) ((base)->REGSC)
tushki7 0:60d829a0353a 5781
tushki7 0:60d829a0353a 5782 /*!
tushki7 0:60d829a0353a 5783 * @}
tushki7 0:60d829a0353a 5784 */ /* end of group PMC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5785
tushki7 0:60d829a0353a 5786
tushki7 0:60d829a0353a 5787 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5788 -- PMC Register Masks
tushki7 0:60d829a0353a 5789 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5790
tushki7 0:60d829a0353a 5791 /*!
tushki7 0:60d829a0353a 5792 * @addtogroup PMC_Register_Masks PMC Register Masks
tushki7 0:60d829a0353a 5793 * @{
tushki7 0:60d829a0353a 5794 */
tushki7 0:60d829a0353a 5795
tushki7 0:60d829a0353a 5796 /* LVDSC1 Bit Fields */
tushki7 0:60d829a0353a 5797 #define PMC_LVDSC1_LVDV_MASK 0x3u
tushki7 0:60d829a0353a 5798 #define PMC_LVDSC1_LVDV_SHIFT 0
tushki7 0:60d829a0353a 5799 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
tushki7 0:60d829a0353a 5800 #define PMC_LVDSC1_LVDRE_MASK 0x10u
tushki7 0:60d829a0353a 5801 #define PMC_LVDSC1_LVDRE_SHIFT 4
tushki7 0:60d829a0353a 5802 #define PMC_LVDSC1_LVDIE_MASK 0x20u
tushki7 0:60d829a0353a 5803 #define PMC_LVDSC1_LVDIE_SHIFT 5
tushki7 0:60d829a0353a 5804 #define PMC_LVDSC1_LVDACK_MASK 0x40u
tushki7 0:60d829a0353a 5805 #define PMC_LVDSC1_LVDACK_SHIFT 6
tushki7 0:60d829a0353a 5806 #define PMC_LVDSC1_LVDF_MASK 0x80u
tushki7 0:60d829a0353a 5807 #define PMC_LVDSC1_LVDF_SHIFT 7
tushki7 0:60d829a0353a 5808 /* LVDSC2 Bit Fields */
tushki7 0:60d829a0353a 5809 #define PMC_LVDSC2_LVWV_MASK 0x3u
tushki7 0:60d829a0353a 5810 #define PMC_LVDSC2_LVWV_SHIFT 0
tushki7 0:60d829a0353a 5811 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
tushki7 0:60d829a0353a 5812 #define PMC_LVDSC2_LVWIE_MASK 0x20u
tushki7 0:60d829a0353a 5813 #define PMC_LVDSC2_LVWIE_SHIFT 5
tushki7 0:60d829a0353a 5814 #define PMC_LVDSC2_LVWACK_MASK 0x40u
tushki7 0:60d829a0353a 5815 #define PMC_LVDSC2_LVWACK_SHIFT 6
tushki7 0:60d829a0353a 5816 #define PMC_LVDSC2_LVWF_MASK 0x80u
tushki7 0:60d829a0353a 5817 #define PMC_LVDSC2_LVWF_SHIFT 7
tushki7 0:60d829a0353a 5818 /* REGSC Bit Fields */
tushki7 0:60d829a0353a 5819 #define PMC_REGSC_BGBE_MASK 0x1u
tushki7 0:60d829a0353a 5820 #define PMC_REGSC_BGBE_SHIFT 0
tushki7 0:60d829a0353a 5821 #define PMC_REGSC_REGONS_MASK 0x4u
tushki7 0:60d829a0353a 5822 #define PMC_REGSC_REGONS_SHIFT 2
tushki7 0:60d829a0353a 5823 #define PMC_REGSC_ACKISO_MASK 0x8u
tushki7 0:60d829a0353a 5824 #define PMC_REGSC_ACKISO_SHIFT 3
tushki7 0:60d829a0353a 5825 #define PMC_REGSC_BGEN_MASK 0x10u
tushki7 0:60d829a0353a 5826 #define PMC_REGSC_BGEN_SHIFT 4
tushki7 0:60d829a0353a 5827
tushki7 0:60d829a0353a 5828 /*!
tushki7 0:60d829a0353a 5829 * @}
tushki7 0:60d829a0353a 5830 */ /* end of group PMC_Register_Masks */
tushki7 0:60d829a0353a 5831
tushki7 0:60d829a0353a 5832
tushki7 0:60d829a0353a 5833 /* PMC - Peripheral instance base addresses */
tushki7 0:60d829a0353a 5834 /** Peripheral PMC base address */
tushki7 0:60d829a0353a 5835 #define PMC_BASE (0x4007D000u)
tushki7 0:60d829a0353a 5836 /** Peripheral PMC base pointer */
tushki7 0:60d829a0353a 5837 #define PMC ((PMC_Type *)PMC_BASE)
tushki7 0:60d829a0353a 5838 #define PMC_BASE_PTR (PMC)
tushki7 0:60d829a0353a 5839 /** Array initializer of PMC peripheral base addresses */
tushki7 0:60d829a0353a 5840 #define PMC_BASE_ADDRS { PMC_BASE }
tushki7 0:60d829a0353a 5841 /** Array initializer of PMC peripheral base pointers */
tushki7 0:60d829a0353a 5842 #define PMC_BASE_PTRS { PMC }
tushki7 0:60d829a0353a 5843 /** Interrupt vectors for the PMC peripheral type */
tushki7 0:60d829a0353a 5844 #define PMC_IRQS { PMC_IRQn }
tushki7 0:60d829a0353a 5845
tushki7 0:60d829a0353a 5846 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5847 -- PMC - Register accessor macros
tushki7 0:60d829a0353a 5848 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5849
tushki7 0:60d829a0353a 5850 /*!
tushki7 0:60d829a0353a 5851 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
tushki7 0:60d829a0353a 5852 * @{
tushki7 0:60d829a0353a 5853 */
tushki7 0:60d829a0353a 5854
tushki7 0:60d829a0353a 5855
tushki7 0:60d829a0353a 5856 /* PMC - Register instance definitions */
tushki7 0:60d829a0353a 5857 /* PMC */
tushki7 0:60d829a0353a 5858 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
tushki7 0:60d829a0353a 5859 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
tushki7 0:60d829a0353a 5860 #define PMC_REGSC PMC_REGSC_REG(PMC)
tushki7 0:60d829a0353a 5861
tushki7 0:60d829a0353a 5862 /*!
tushki7 0:60d829a0353a 5863 * @}
tushki7 0:60d829a0353a 5864 */ /* end of group PMC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5865
tushki7 0:60d829a0353a 5866
tushki7 0:60d829a0353a 5867 /*!
tushki7 0:60d829a0353a 5868 * @}
tushki7 0:60d829a0353a 5869 */ /* end of group PMC_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 5870
tushki7 0:60d829a0353a 5871
tushki7 0:60d829a0353a 5872 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5873 -- PORT Peripheral Access Layer
tushki7 0:60d829a0353a 5874 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5875
tushki7 0:60d829a0353a 5876 /*!
tushki7 0:60d829a0353a 5877 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
tushki7 0:60d829a0353a 5878 * @{
tushki7 0:60d829a0353a 5879 */
tushki7 0:60d829a0353a 5880
tushki7 0:60d829a0353a 5881 /** PORT - Register Layout Typedef */
tushki7 0:60d829a0353a 5882 typedef struct {
tushki7 0:60d829a0353a 5883 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
tushki7 0:60d829a0353a 5884 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
tushki7 0:60d829a0353a 5885 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
tushki7 0:60d829a0353a 5886 uint8_t RESERVED_0[24];
tushki7 0:60d829a0353a 5887 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
tushki7 0:60d829a0353a 5888 } PORT_Type, *PORT_MemMapPtr;
tushki7 0:60d829a0353a 5889
tushki7 0:60d829a0353a 5890 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5891 -- PORT - Register accessor macros
tushki7 0:60d829a0353a 5892 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5893
tushki7 0:60d829a0353a 5894 /*!
tushki7 0:60d829a0353a 5895 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
tushki7 0:60d829a0353a 5896 * @{
tushki7 0:60d829a0353a 5897 */
tushki7 0:60d829a0353a 5898
tushki7 0:60d829a0353a 5899
tushki7 0:60d829a0353a 5900 /* PORT - Register accessors */
tushki7 0:60d829a0353a 5901 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
tushki7 0:60d829a0353a 5902 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
tushki7 0:60d829a0353a 5903 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
tushki7 0:60d829a0353a 5904 #define PORT_ISFR_REG(base) ((base)->ISFR)
tushki7 0:60d829a0353a 5905
tushki7 0:60d829a0353a 5906 /*!
tushki7 0:60d829a0353a 5907 * @}
tushki7 0:60d829a0353a 5908 */ /* end of group PORT_Register_Accessor_Macros */
tushki7 0:60d829a0353a 5909
tushki7 0:60d829a0353a 5910
tushki7 0:60d829a0353a 5911 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5912 -- PORT Register Masks
tushki7 0:60d829a0353a 5913 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5914
tushki7 0:60d829a0353a 5915 /*!
tushki7 0:60d829a0353a 5916 * @addtogroup PORT_Register_Masks PORT Register Masks
tushki7 0:60d829a0353a 5917 * @{
tushki7 0:60d829a0353a 5918 */
tushki7 0:60d829a0353a 5919
tushki7 0:60d829a0353a 5920 /* PCR Bit Fields */
tushki7 0:60d829a0353a 5921 #define PORT_PCR_PS_MASK 0x1u
tushki7 0:60d829a0353a 5922 #define PORT_PCR_PS_SHIFT 0
tushki7 0:60d829a0353a 5923 #define PORT_PCR_PE_MASK 0x2u
tushki7 0:60d829a0353a 5924 #define PORT_PCR_PE_SHIFT 1
tushki7 0:60d829a0353a 5925 #define PORT_PCR_SRE_MASK 0x4u
tushki7 0:60d829a0353a 5926 #define PORT_PCR_SRE_SHIFT 2
tushki7 0:60d829a0353a 5927 #define PORT_PCR_PFE_MASK 0x10u
tushki7 0:60d829a0353a 5928 #define PORT_PCR_PFE_SHIFT 4
tushki7 0:60d829a0353a 5929 #define PORT_PCR_DSE_MASK 0x40u
tushki7 0:60d829a0353a 5930 #define PORT_PCR_DSE_SHIFT 6
tushki7 0:60d829a0353a 5931 #define PORT_PCR_MUX_MASK 0x700u
tushki7 0:60d829a0353a 5932 #define PORT_PCR_MUX_SHIFT 8
tushki7 0:60d829a0353a 5933 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
tushki7 0:60d829a0353a 5934 #define PORT_PCR_IRQC_MASK 0xF0000u
tushki7 0:60d829a0353a 5935 #define PORT_PCR_IRQC_SHIFT 16
tushki7 0:60d829a0353a 5936 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
tushki7 0:60d829a0353a 5937 #define PORT_PCR_ISF_MASK 0x1000000u
tushki7 0:60d829a0353a 5938 #define PORT_PCR_ISF_SHIFT 24
tushki7 0:60d829a0353a 5939 /* GPCLR Bit Fields */
tushki7 0:60d829a0353a 5940 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
tushki7 0:60d829a0353a 5941 #define PORT_GPCLR_GPWD_SHIFT 0
tushki7 0:60d829a0353a 5942 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
tushki7 0:60d829a0353a 5943 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
tushki7 0:60d829a0353a 5944 #define PORT_GPCLR_GPWE_SHIFT 16
tushki7 0:60d829a0353a 5945 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
tushki7 0:60d829a0353a 5946 /* GPCHR Bit Fields */
tushki7 0:60d829a0353a 5947 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
tushki7 0:60d829a0353a 5948 #define PORT_GPCHR_GPWD_SHIFT 0
tushki7 0:60d829a0353a 5949 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
tushki7 0:60d829a0353a 5950 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
tushki7 0:60d829a0353a 5951 #define PORT_GPCHR_GPWE_SHIFT 16
tushki7 0:60d829a0353a 5952 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
tushki7 0:60d829a0353a 5953 /* ISFR Bit Fields */
tushki7 0:60d829a0353a 5954 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 5955 #define PORT_ISFR_ISF_SHIFT 0
tushki7 0:60d829a0353a 5956 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
tushki7 0:60d829a0353a 5957
tushki7 0:60d829a0353a 5958 /*!
tushki7 0:60d829a0353a 5959 * @}
tushki7 0:60d829a0353a 5960 */ /* end of group PORT_Register_Masks */
tushki7 0:60d829a0353a 5961
tushki7 0:60d829a0353a 5962
tushki7 0:60d829a0353a 5963 /* PORT - Peripheral instance base addresses */
tushki7 0:60d829a0353a 5964 /** Peripheral PORTA base address */
tushki7 0:60d829a0353a 5965 #define PORTA_BASE (0x40049000u)
tushki7 0:60d829a0353a 5966 /** Peripheral PORTA base pointer */
tushki7 0:60d829a0353a 5967 #define PORTA ((PORT_Type *)PORTA_BASE)
tushki7 0:60d829a0353a 5968 #define PORTA_BASE_PTR (PORTA)
tushki7 0:60d829a0353a 5969 /** Peripheral PORTB base address */
tushki7 0:60d829a0353a 5970 #define PORTB_BASE (0x4004A000u)
tushki7 0:60d829a0353a 5971 /** Peripheral PORTB base pointer */
tushki7 0:60d829a0353a 5972 #define PORTB ((PORT_Type *)PORTB_BASE)
tushki7 0:60d829a0353a 5973 #define PORTB_BASE_PTR (PORTB)
tushki7 0:60d829a0353a 5974 /** Peripheral PORTC base address */
tushki7 0:60d829a0353a 5975 #define PORTC_BASE (0x4004B000u)
tushki7 0:60d829a0353a 5976 /** Peripheral PORTC base pointer */
tushki7 0:60d829a0353a 5977 #define PORTC ((PORT_Type *)PORTC_BASE)
tushki7 0:60d829a0353a 5978 #define PORTC_BASE_PTR (PORTC)
tushki7 0:60d829a0353a 5979 /** Peripheral PORTD base address */
tushki7 0:60d829a0353a 5980 #define PORTD_BASE (0x4004C000u)
tushki7 0:60d829a0353a 5981 /** Peripheral PORTD base pointer */
tushki7 0:60d829a0353a 5982 #define PORTD ((PORT_Type *)PORTD_BASE)
tushki7 0:60d829a0353a 5983 #define PORTD_BASE_PTR (PORTD)
tushki7 0:60d829a0353a 5984 /** Peripheral PORTE base address */
tushki7 0:60d829a0353a 5985 #define PORTE_BASE (0x4004D000u)
tushki7 0:60d829a0353a 5986 /** Peripheral PORTE base pointer */
tushki7 0:60d829a0353a 5987 #define PORTE ((PORT_Type *)PORTE_BASE)
tushki7 0:60d829a0353a 5988 #define PORTE_BASE_PTR (PORTE)
tushki7 0:60d829a0353a 5989 /** Array initializer of PORT peripheral base addresses */
tushki7 0:60d829a0353a 5990 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
tushki7 0:60d829a0353a 5991 /** Array initializer of PORT peripheral base pointers */
tushki7 0:60d829a0353a 5992 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
tushki7 0:60d829a0353a 5993 /** Interrupt vectors for the PORT peripheral type */
tushki7 0:60d829a0353a 5994 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTCD_IRQn, PORTCD_IRQn, NotAvail_IRQn }
tushki7 0:60d829a0353a 5995
tushki7 0:60d829a0353a 5996 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 5997 -- PORT - Register accessor macros
tushki7 0:60d829a0353a 5998 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 5999
tushki7 0:60d829a0353a 6000 /*!
tushki7 0:60d829a0353a 6001 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
tushki7 0:60d829a0353a 6002 * @{
tushki7 0:60d829a0353a 6003 */
tushki7 0:60d829a0353a 6004
tushki7 0:60d829a0353a 6005
tushki7 0:60d829a0353a 6006 /* PORT - Register instance definitions */
tushki7 0:60d829a0353a 6007 /* PORTA */
tushki7 0:60d829a0353a 6008 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
tushki7 0:60d829a0353a 6009 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
tushki7 0:60d829a0353a 6010 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
tushki7 0:60d829a0353a 6011 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
tushki7 0:60d829a0353a 6012 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
tushki7 0:60d829a0353a 6013 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
tushki7 0:60d829a0353a 6014 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
tushki7 0:60d829a0353a 6015 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
tushki7 0:60d829a0353a 6016 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
tushki7 0:60d829a0353a 6017 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
tushki7 0:60d829a0353a 6018 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
tushki7 0:60d829a0353a 6019 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
tushki7 0:60d829a0353a 6020 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
tushki7 0:60d829a0353a 6021 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
tushki7 0:60d829a0353a 6022 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
tushki7 0:60d829a0353a 6023 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
tushki7 0:60d829a0353a 6024 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
tushki7 0:60d829a0353a 6025 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
tushki7 0:60d829a0353a 6026 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
tushki7 0:60d829a0353a 6027 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
tushki7 0:60d829a0353a 6028 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
tushki7 0:60d829a0353a 6029 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
tushki7 0:60d829a0353a 6030 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
tushki7 0:60d829a0353a 6031 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
tushki7 0:60d829a0353a 6032 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
tushki7 0:60d829a0353a 6033 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
tushki7 0:60d829a0353a 6034 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
tushki7 0:60d829a0353a 6035 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
tushki7 0:60d829a0353a 6036 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
tushki7 0:60d829a0353a 6037 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
tushki7 0:60d829a0353a 6038 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
tushki7 0:60d829a0353a 6039 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
tushki7 0:60d829a0353a 6040 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
tushki7 0:60d829a0353a 6041 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
tushki7 0:60d829a0353a 6042 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
tushki7 0:60d829a0353a 6043 /* PORTB */
tushki7 0:60d829a0353a 6044 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
tushki7 0:60d829a0353a 6045 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
tushki7 0:60d829a0353a 6046 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
tushki7 0:60d829a0353a 6047 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
tushki7 0:60d829a0353a 6048 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
tushki7 0:60d829a0353a 6049 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
tushki7 0:60d829a0353a 6050 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
tushki7 0:60d829a0353a 6051 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
tushki7 0:60d829a0353a 6052 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
tushki7 0:60d829a0353a 6053 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
tushki7 0:60d829a0353a 6054 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
tushki7 0:60d829a0353a 6055 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
tushki7 0:60d829a0353a 6056 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
tushki7 0:60d829a0353a 6057 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
tushki7 0:60d829a0353a 6058 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
tushki7 0:60d829a0353a 6059 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
tushki7 0:60d829a0353a 6060 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
tushki7 0:60d829a0353a 6061 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
tushki7 0:60d829a0353a 6062 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
tushki7 0:60d829a0353a 6063 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
tushki7 0:60d829a0353a 6064 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
tushki7 0:60d829a0353a 6065 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
tushki7 0:60d829a0353a 6066 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
tushki7 0:60d829a0353a 6067 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
tushki7 0:60d829a0353a 6068 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
tushki7 0:60d829a0353a 6069 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
tushki7 0:60d829a0353a 6070 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
tushki7 0:60d829a0353a 6071 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
tushki7 0:60d829a0353a 6072 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
tushki7 0:60d829a0353a 6073 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
tushki7 0:60d829a0353a 6074 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
tushki7 0:60d829a0353a 6075 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
tushki7 0:60d829a0353a 6076 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
tushki7 0:60d829a0353a 6077 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
tushki7 0:60d829a0353a 6078 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
tushki7 0:60d829a0353a 6079 /* PORTC */
tushki7 0:60d829a0353a 6080 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
tushki7 0:60d829a0353a 6081 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
tushki7 0:60d829a0353a 6082 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
tushki7 0:60d829a0353a 6083 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
tushki7 0:60d829a0353a 6084 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
tushki7 0:60d829a0353a 6085 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
tushki7 0:60d829a0353a 6086 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
tushki7 0:60d829a0353a 6087 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
tushki7 0:60d829a0353a 6088 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
tushki7 0:60d829a0353a 6089 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
tushki7 0:60d829a0353a 6090 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
tushki7 0:60d829a0353a 6091 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
tushki7 0:60d829a0353a 6092 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
tushki7 0:60d829a0353a 6093 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
tushki7 0:60d829a0353a 6094 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
tushki7 0:60d829a0353a 6095 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
tushki7 0:60d829a0353a 6096 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
tushki7 0:60d829a0353a 6097 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
tushki7 0:60d829a0353a 6098 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
tushki7 0:60d829a0353a 6099 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
tushki7 0:60d829a0353a 6100 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
tushki7 0:60d829a0353a 6101 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
tushki7 0:60d829a0353a 6102 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
tushki7 0:60d829a0353a 6103 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
tushki7 0:60d829a0353a 6104 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
tushki7 0:60d829a0353a 6105 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
tushki7 0:60d829a0353a 6106 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
tushki7 0:60d829a0353a 6107 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
tushki7 0:60d829a0353a 6108 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
tushki7 0:60d829a0353a 6109 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
tushki7 0:60d829a0353a 6110 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
tushki7 0:60d829a0353a 6111 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
tushki7 0:60d829a0353a 6112 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
tushki7 0:60d829a0353a 6113 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
tushki7 0:60d829a0353a 6114 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
tushki7 0:60d829a0353a 6115 /* PORTD */
tushki7 0:60d829a0353a 6116 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
tushki7 0:60d829a0353a 6117 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
tushki7 0:60d829a0353a 6118 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
tushki7 0:60d829a0353a 6119 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
tushki7 0:60d829a0353a 6120 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
tushki7 0:60d829a0353a 6121 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
tushki7 0:60d829a0353a 6122 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
tushki7 0:60d829a0353a 6123 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
tushki7 0:60d829a0353a 6124 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
tushki7 0:60d829a0353a 6125 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
tushki7 0:60d829a0353a 6126 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
tushki7 0:60d829a0353a 6127 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
tushki7 0:60d829a0353a 6128 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
tushki7 0:60d829a0353a 6129 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
tushki7 0:60d829a0353a 6130 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
tushki7 0:60d829a0353a 6131 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
tushki7 0:60d829a0353a 6132 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
tushki7 0:60d829a0353a 6133 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
tushki7 0:60d829a0353a 6134 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
tushki7 0:60d829a0353a 6135 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
tushki7 0:60d829a0353a 6136 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
tushki7 0:60d829a0353a 6137 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
tushki7 0:60d829a0353a 6138 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
tushki7 0:60d829a0353a 6139 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
tushki7 0:60d829a0353a 6140 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
tushki7 0:60d829a0353a 6141 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
tushki7 0:60d829a0353a 6142 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
tushki7 0:60d829a0353a 6143 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
tushki7 0:60d829a0353a 6144 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
tushki7 0:60d829a0353a 6145 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
tushki7 0:60d829a0353a 6146 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
tushki7 0:60d829a0353a 6147 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
tushki7 0:60d829a0353a 6148 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
tushki7 0:60d829a0353a 6149 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
tushki7 0:60d829a0353a 6150 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
tushki7 0:60d829a0353a 6151 /* PORTE */
tushki7 0:60d829a0353a 6152 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
tushki7 0:60d829a0353a 6153 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
tushki7 0:60d829a0353a 6154 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
tushki7 0:60d829a0353a 6155 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
tushki7 0:60d829a0353a 6156 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
tushki7 0:60d829a0353a 6157 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
tushki7 0:60d829a0353a 6158 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
tushki7 0:60d829a0353a 6159 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
tushki7 0:60d829a0353a 6160 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
tushki7 0:60d829a0353a 6161 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
tushki7 0:60d829a0353a 6162 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
tushki7 0:60d829a0353a 6163 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
tushki7 0:60d829a0353a 6164 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
tushki7 0:60d829a0353a 6165 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
tushki7 0:60d829a0353a 6166 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
tushki7 0:60d829a0353a 6167 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
tushki7 0:60d829a0353a 6168 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
tushki7 0:60d829a0353a 6169 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
tushki7 0:60d829a0353a 6170 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
tushki7 0:60d829a0353a 6171 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
tushki7 0:60d829a0353a 6172 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
tushki7 0:60d829a0353a 6173 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
tushki7 0:60d829a0353a 6174 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
tushki7 0:60d829a0353a 6175 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
tushki7 0:60d829a0353a 6176 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
tushki7 0:60d829a0353a 6177 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
tushki7 0:60d829a0353a 6178 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
tushki7 0:60d829a0353a 6179 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
tushki7 0:60d829a0353a 6180 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
tushki7 0:60d829a0353a 6181 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
tushki7 0:60d829a0353a 6182 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
tushki7 0:60d829a0353a 6183 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
tushki7 0:60d829a0353a 6184 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
tushki7 0:60d829a0353a 6185 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
tushki7 0:60d829a0353a 6186 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
tushki7 0:60d829a0353a 6187
tushki7 0:60d829a0353a 6188 /* PORT - Register array accessors */
tushki7 0:60d829a0353a 6189 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
tushki7 0:60d829a0353a 6190 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
tushki7 0:60d829a0353a 6191 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
tushki7 0:60d829a0353a 6192 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
tushki7 0:60d829a0353a 6193 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
tushki7 0:60d829a0353a 6194
tushki7 0:60d829a0353a 6195 /*!
tushki7 0:60d829a0353a 6196 * @}
tushki7 0:60d829a0353a 6197 */ /* end of group PORT_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6198
tushki7 0:60d829a0353a 6199
tushki7 0:60d829a0353a 6200 /*!
tushki7 0:60d829a0353a 6201 * @}
tushki7 0:60d829a0353a 6202 */ /* end of group PORT_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 6203
tushki7 0:60d829a0353a 6204
tushki7 0:60d829a0353a 6205 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6206 -- RCM Peripheral Access Layer
tushki7 0:60d829a0353a 6207 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6208
tushki7 0:60d829a0353a 6209 /*!
tushki7 0:60d829a0353a 6210 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
tushki7 0:60d829a0353a 6211 * @{
tushki7 0:60d829a0353a 6212 */
tushki7 0:60d829a0353a 6213
tushki7 0:60d829a0353a 6214 /** RCM - Register Layout Typedef */
tushki7 0:60d829a0353a 6215 typedef struct {
tushki7 0:60d829a0353a 6216 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
tushki7 0:60d829a0353a 6217 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
tushki7 0:60d829a0353a 6218 uint8_t RESERVED_0[2];
tushki7 0:60d829a0353a 6219 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
tushki7 0:60d829a0353a 6220 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
tushki7 0:60d829a0353a 6221 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
tushki7 0:60d829a0353a 6222 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
tushki7 0:60d829a0353a 6223 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
tushki7 0:60d829a0353a 6224 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
tushki7 0:60d829a0353a 6225 } RCM_Type, *RCM_MemMapPtr;
tushki7 0:60d829a0353a 6226
tushki7 0:60d829a0353a 6227 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6228 -- RCM - Register accessor macros
tushki7 0:60d829a0353a 6229 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6230
tushki7 0:60d829a0353a 6231 /*!
tushki7 0:60d829a0353a 6232 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
tushki7 0:60d829a0353a 6233 * @{
tushki7 0:60d829a0353a 6234 */
tushki7 0:60d829a0353a 6235
tushki7 0:60d829a0353a 6236
tushki7 0:60d829a0353a 6237 /* RCM - Register accessors */
tushki7 0:60d829a0353a 6238 #define RCM_SRS0_REG(base) ((base)->SRS0)
tushki7 0:60d829a0353a 6239 #define RCM_SRS1_REG(base) ((base)->SRS1)
tushki7 0:60d829a0353a 6240 #define RCM_RPFC_REG(base) ((base)->RPFC)
tushki7 0:60d829a0353a 6241 #define RCM_RPFW_REG(base) ((base)->RPFW)
tushki7 0:60d829a0353a 6242 #define RCM_FM_REG(base) ((base)->FM)
tushki7 0:60d829a0353a 6243 #define RCM_MR_REG(base) ((base)->MR)
tushki7 0:60d829a0353a 6244 #define RCM_SSRS0_REG(base) ((base)->SSRS0)
tushki7 0:60d829a0353a 6245 #define RCM_SSRS1_REG(base) ((base)->SSRS1)
tushki7 0:60d829a0353a 6246
tushki7 0:60d829a0353a 6247 /*!
tushki7 0:60d829a0353a 6248 * @}
tushki7 0:60d829a0353a 6249 */ /* end of group RCM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6250
tushki7 0:60d829a0353a 6251
tushki7 0:60d829a0353a 6252 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6253 -- RCM Register Masks
tushki7 0:60d829a0353a 6254 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6255
tushki7 0:60d829a0353a 6256 /*!
tushki7 0:60d829a0353a 6257 * @addtogroup RCM_Register_Masks RCM Register Masks
tushki7 0:60d829a0353a 6258 * @{
tushki7 0:60d829a0353a 6259 */
tushki7 0:60d829a0353a 6260
tushki7 0:60d829a0353a 6261 /* SRS0 Bit Fields */
tushki7 0:60d829a0353a 6262 #define RCM_SRS0_WAKEUP_MASK 0x1u
tushki7 0:60d829a0353a 6263 #define RCM_SRS0_WAKEUP_SHIFT 0
tushki7 0:60d829a0353a 6264 #define RCM_SRS0_LVD_MASK 0x2u
tushki7 0:60d829a0353a 6265 #define RCM_SRS0_LVD_SHIFT 1
tushki7 0:60d829a0353a 6266 #define RCM_SRS0_WDOG_MASK 0x20u
tushki7 0:60d829a0353a 6267 #define RCM_SRS0_WDOG_SHIFT 5
tushki7 0:60d829a0353a 6268 #define RCM_SRS0_PIN_MASK 0x40u
tushki7 0:60d829a0353a 6269 #define RCM_SRS0_PIN_SHIFT 6
tushki7 0:60d829a0353a 6270 #define RCM_SRS0_POR_MASK 0x80u
tushki7 0:60d829a0353a 6271 #define RCM_SRS0_POR_SHIFT 7
tushki7 0:60d829a0353a 6272 /* SRS1 Bit Fields */
tushki7 0:60d829a0353a 6273 #define RCM_SRS1_LOCKUP_MASK 0x2u
tushki7 0:60d829a0353a 6274 #define RCM_SRS1_LOCKUP_SHIFT 1
tushki7 0:60d829a0353a 6275 #define RCM_SRS1_SW_MASK 0x4u
tushki7 0:60d829a0353a 6276 #define RCM_SRS1_SW_SHIFT 2
tushki7 0:60d829a0353a 6277 #define RCM_SRS1_MDM_AP_MASK 0x8u
tushki7 0:60d829a0353a 6278 #define RCM_SRS1_MDM_AP_SHIFT 3
tushki7 0:60d829a0353a 6279 #define RCM_SRS1_SACKERR_MASK 0x20u
tushki7 0:60d829a0353a 6280 #define RCM_SRS1_SACKERR_SHIFT 5
tushki7 0:60d829a0353a 6281 /* RPFC Bit Fields */
tushki7 0:60d829a0353a 6282 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
tushki7 0:60d829a0353a 6283 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
tushki7 0:60d829a0353a 6284 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
tushki7 0:60d829a0353a 6285 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
tushki7 0:60d829a0353a 6286 #define RCM_RPFC_RSTFLTSS_SHIFT 2
tushki7 0:60d829a0353a 6287 /* RPFW Bit Fields */
tushki7 0:60d829a0353a 6288 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
tushki7 0:60d829a0353a 6289 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
tushki7 0:60d829a0353a 6290 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
tushki7 0:60d829a0353a 6291 /* FM Bit Fields */
tushki7 0:60d829a0353a 6292 #define RCM_FM_FORCEROM_MASK 0x6u
tushki7 0:60d829a0353a 6293 #define RCM_FM_FORCEROM_SHIFT 1
tushki7 0:60d829a0353a 6294 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK)
tushki7 0:60d829a0353a 6295 /* MR Bit Fields */
tushki7 0:60d829a0353a 6296 #define RCM_MR_BOOTROM_MASK 0x6u
tushki7 0:60d829a0353a 6297 #define RCM_MR_BOOTROM_SHIFT 1
tushki7 0:60d829a0353a 6298 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK)
tushki7 0:60d829a0353a 6299 /* SSRS0 Bit Fields */
tushki7 0:60d829a0353a 6300 #define RCM_SSRS0_SWAKEUP_MASK 0x1u
tushki7 0:60d829a0353a 6301 #define RCM_SSRS0_SWAKEUP_SHIFT 0
tushki7 0:60d829a0353a 6302 #define RCM_SSRS0_SLVD_MASK 0x2u
tushki7 0:60d829a0353a 6303 #define RCM_SSRS0_SLVD_SHIFT 1
tushki7 0:60d829a0353a 6304 #define RCM_SSRS0_SWDOG_MASK 0x20u
tushki7 0:60d829a0353a 6305 #define RCM_SSRS0_SWDOG_SHIFT 5
tushki7 0:60d829a0353a 6306 #define RCM_SSRS0_SPIN_MASK 0x40u
tushki7 0:60d829a0353a 6307 #define RCM_SSRS0_SPIN_SHIFT 6
tushki7 0:60d829a0353a 6308 #define RCM_SSRS0_SPOR_MASK 0x80u
tushki7 0:60d829a0353a 6309 #define RCM_SSRS0_SPOR_SHIFT 7
tushki7 0:60d829a0353a 6310 /* SSRS1 Bit Fields */
tushki7 0:60d829a0353a 6311 #define RCM_SSRS1_SLOCKUP_MASK 0x2u
tushki7 0:60d829a0353a 6312 #define RCM_SSRS1_SLOCKUP_SHIFT 1
tushki7 0:60d829a0353a 6313 #define RCM_SSRS1_SSW_MASK 0x4u
tushki7 0:60d829a0353a 6314 #define RCM_SSRS1_SSW_SHIFT 2
tushki7 0:60d829a0353a 6315 #define RCM_SSRS1_SMDM_AP_MASK 0x8u
tushki7 0:60d829a0353a 6316 #define RCM_SSRS1_SMDM_AP_SHIFT 3
tushki7 0:60d829a0353a 6317 #define RCM_SSRS1_SSACKERR_MASK 0x20u
tushki7 0:60d829a0353a 6318 #define RCM_SSRS1_SSACKERR_SHIFT 5
tushki7 0:60d829a0353a 6319
tushki7 0:60d829a0353a 6320 /*!
tushki7 0:60d829a0353a 6321 * @}
tushki7 0:60d829a0353a 6322 */ /* end of group RCM_Register_Masks */
tushki7 0:60d829a0353a 6323
tushki7 0:60d829a0353a 6324
tushki7 0:60d829a0353a 6325 /* RCM - Peripheral instance base addresses */
tushki7 0:60d829a0353a 6326 /** Peripheral RCM base address */
tushki7 0:60d829a0353a 6327 #define RCM_BASE (0x4007F000u)
tushki7 0:60d829a0353a 6328 /** Peripheral RCM base pointer */
tushki7 0:60d829a0353a 6329 #define RCM ((RCM_Type *)RCM_BASE)
tushki7 0:60d829a0353a 6330 #define RCM_BASE_PTR (RCM)
tushki7 0:60d829a0353a 6331 /** Array initializer of RCM peripheral base addresses */
tushki7 0:60d829a0353a 6332 #define RCM_BASE_ADDRS { RCM_BASE }
tushki7 0:60d829a0353a 6333 /** Array initializer of RCM peripheral base pointers */
tushki7 0:60d829a0353a 6334 #define RCM_BASE_PTRS { RCM }
tushki7 0:60d829a0353a 6335
tushki7 0:60d829a0353a 6336 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6337 -- RCM - Register accessor macros
tushki7 0:60d829a0353a 6338 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6339
tushki7 0:60d829a0353a 6340 /*!
tushki7 0:60d829a0353a 6341 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
tushki7 0:60d829a0353a 6342 * @{
tushki7 0:60d829a0353a 6343 */
tushki7 0:60d829a0353a 6344
tushki7 0:60d829a0353a 6345
tushki7 0:60d829a0353a 6346 /* RCM - Register instance definitions */
tushki7 0:60d829a0353a 6347 /* RCM */
tushki7 0:60d829a0353a 6348 #define RCM_SRS0 RCM_SRS0_REG(RCM)
tushki7 0:60d829a0353a 6349 #define RCM_SRS1 RCM_SRS1_REG(RCM)
tushki7 0:60d829a0353a 6350 #define RCM_RPFC RCM_RPFC_REG(RCM)
tushki7 0:60d829a0353a 6351 #define RCM_RPFW RCM_RPFW_REG(RCM)
tushki7 0:60d829a0353a 6352 #define RCM_FM RCM_FM_REG(RCM)
tushki7 0:60d829a0353a 6353 #define RCM_MR RCM_MR_REG(RCM)
tushki7 0:60d829a0353a 6354 #define RCM_SSRS0 RCM_SSRS0_REG(RCM)
tushki7 0:60d829a0353a 6355 #define RCM_SSRS1 RCM_SSRS1_REG(RCM)
tushki7 0:60d829a0353a 6356
tushki7 0:60d829a0353a 6357 /*!
tushki7 0:60d829a0353a 6358 * @}
tushki7 0:60d829a0353a 6359 */ /* end of group RCM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6360
tushki7 0:60d829a0353a 6361
tushki7 0:60d829a0353a 6362 /*!
tushki7 0:60d829a0353a 6363 * @}
tushki7 0:60d829a0353a 6364 */ /* end of group RCM_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 6365
tushki7 0:60d829a0353a 6366
tushki7 0:60d829a0353a 6367 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6368 -- RFSYS Peripheral Access Layer
tushki7 0:60d829a0353a 6369 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6370
tushki7 0:60d829a0353a 6371 /*!
tushki7 0:60d829a0353a 6372 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
tushki7 0:60d829a0353a 6373 * @{
tushki7 0:60d829a0353a 6374 */
tushki7 0:60d829a0353a 6375
tushki7 0:60d829a0353a 6376 /** RFSYS - Register Layout Typedef */
tushki7 0:60d829a0353a 6377 typedef struct {
tushki7 0:60d829a0353a 6378 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
tushki7 0:60d829a0353a 6379 } RFSYS_Type, *RFSYS_MemMapPtr;
tushki7 0:60d829a0353a 6380
tushki7 0:60d829a0353a 6381 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6382 -- RFSYS - Register accessor macros
tushki7 0:60d829a0353a 6383 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6384
tushki7 0:60d829a0353a 6385 /*!
tushki7 0:60d829a0353a 6386 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
tushki7 0:60d829a0353a 6387 * @{
tushki7 0:60d829a0353a 6388 */
tushki7 0:60d829a0353a 6389
tushki7 0:60d829a0353a 6390
tushki7 0:60d829a0353a 6391 /* RFSYS - Register accessors */
tushki7 0:60d829a0353a 6392 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
tushki7 0:60d829a0353a 6393
tushki7 0:60d829a0353a 6394 /*!
tushki7 0:60d829a0353a 6395 * @}
tushki7 0:60d829a0353a 6396 */ /* end of group RFSYS_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6397
tushki7 0:60d829a0353a 6398
tushki7 0:60d829a0353a 6399 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6400 -- RFSYS Register Masks
tushki7 0:60d829a0353a 6401 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6402
tushki7 0:60d829a0353a 6403 /*!
tushki7 0:60d829a0353a 6404 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
tushki7 0:60d829a0353a 6405 * @{
tushki7 0:60d829a0353a 6406 */
tushki7 0:60d829a0353a 6407
tushki7 0:60d829a0353a 6408 /* REG Bit Fields */
tushki7 0:60d829a0353a 6409 #define RFSYS_REG_LL_MASK 0xFFu
tushki7 0:60d829a0353a 6410 #define RFSYS_REG_LL_SHIFT 0
tushki7 0:60d829a0353a 6411 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
tushki7 0:60d829a0353a 6412 #define RFSYS_REG_LH_MASK 0xFF00u
tushki7 0:60d829a0353a 6413 #define RFSYS_REG_LH_SHIFT 8
tushki7 0:60d829a0353a 6414 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
tushki7 0:60d829a0353a 6415 #define RFSYS_REG_HL_MASK 0xFF0000u
tushki7 0:60d829a0353a 6416 #define RFSYS_REG_HL_SHIFT 16
tushki7 0:60d829a0353a 6417 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
tushki7 0:60d829a0353a 6418 #define RFSYS_REG_HH_MASK 0xFF000000u
tushki7 0:60d829a0353a 6419 #define RFSYS_REG_HH_SHIFT 24
tushki7 0:60d829a0353a 6420 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
tushki7 0:60d829a0353a 6421
tushki7 0:60d829a0353a 6422 /*!
tushki7 0:60d829a0353a 6423 * @}
tushki7 0:60d829a0353a 6424 */ /* end of group RFSYS_Register_Masks */
tushki7 0:60d829a0353a 6425
tushki7 0:60d829a0353a 6426
tushki7 0:60d829a0353a 6427 /* RFSYS - Peripheral instance base addresses */
tushki7 0:60d829a0353a 6428 /** Peripheral RFSYS base address */
tushki7 0:60d829a0353a 6429 #define RFSYS_BASE (0x40041000u)
tushki7 0:60d829a0353a 6430 /** Peripheral RFSYS base pointer */
tushki7 0:60d829a0353a 6431 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
tushki7 0:60d829a0353a 6432 #define RFSYS_BASE_PTR (RFSYS)
tushki7 0:60d829a0353a 6433 /** Array initializer of RFSYS peripheral base addresses */
tushki7 0:60d829a0353a 6434 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
tushki7 0:60d829a0353a 6435 /** Array initializer of RFSYS peripheral base pointers */
tushki7 0:60d829a0353a 6436 #define RFSYS_BASE_PTRS { RFSYS }
tushki7 0:60d829a0353a 6437
tushki7 0:60d829a0353a 6438 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6439 -- RFSYS - Register accessor macros
tushki7 0:60d829a0353a 6440 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6441
tushki7 0:60d829a0353a 6442 /*!
tushki7 0:60d829a0353a 6443 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
tushki7 0:60d829a0353a 6444 * @{
tushki7 0:60d829a0353a 6445 */
tushki7 0:60d829a0353a 6446
tushki7 0:60d829a0353a 6447
tushki7 0:60d829a0353a 6448 /* RFSYS - Register instance definitions */
tushki7 0:60d829a0353a 6449 /* RFSYS */
tushki7 0:60d829a0353a 6450 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
tushki7 0:60d829a0353a 6451 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
tushki7 0:60d829a0353a 6452 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
tushki7 0:60d829a0353a 6453 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
tushki7 0:60d829a0353a 6454 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
tushki7 0:60d829a0353a 6455 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
tushki7 0:60d829a0353a 6456 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
tushki7 0:60d829a0353a 6457 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
tushki7 0:60d829a0353a 6458
tushki7 0:60d829a0353a 6459 /* RFSYS - Register array accessors */
tushki7 0:60d829a0353a 6460 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
tushki7 0:60d829a0353a 6461
tushki7 0:60d829a0353a 6462 /*!
tushki7 0:60d829a0353a 6463 * @}
tushki7 0:60d829a0353a 6464 */ /* end of group RFSYS_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6465
tushki7 0:60d829a0353a 6466
tushki7 0:60d829a0353a 6467 /*!
tushki7 0:60d829a0353a 6468 * @}
tushki7 0:60d829a0353a 6469 */ /* end of group RFSYS_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 6470
tushki7 0:60d829a0353a 6471
tushki7 0:60d829a0353a 6472 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6473 -- ROM Peripheral Access Layer
tushki7 0:60d829a0353a 6474 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6475
tushki7 0:60d829a0353a 6476 /*!
tushki7 0:60d829a0353a 6477 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
tushki7 0:60d829a0353a 6478 * @{
tushki7 0:60d829a0353a 6479 */
tushki7 0:60d829a0353a 6480
tushki7 0:60d829a0353a 6481 /** ROM - Register Layout Typedef */
tushki7 0:60d829a0353a 6482 typedef struct {
tushki7 0:60d829a0353a 6483 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
tushki7 0:60d829a0353a 6484 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
tushki7 0:60d829a0353a 6485 uint8_t RESERVED_0[4028];
tushki7 0:60d829a0353a 6486 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
tushki7 0:60d829a0353a 6487 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
tushki7 0:60d829a0353a 6488 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
tushki7 0:60d829a0353a 6489 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
tushki7 0:60d829a0353a 6490 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
tushki7 0:60d829a0353a 6491 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
tushki7 0:60d829a0353a 6492 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
tushki7 0:60d829a0353a 6493 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
tushki7 0:60d829a0353a 6494 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
tushki7 0:60d829a0353a 6495 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
tushki7 0:60d829a0353a 6496 } ROM_Type, *ROM_MemMapPtr;
tushki7 0:60d829a0353a 6497
tushki7 0:60d829a0353a 6498 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6499 -- ROM - Register accessor macros
tushki7 0:60d829a0353a 6500 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6501
tushki7 0:60d829a0353a 6502 /*!
tushki7 0:60d829a0353a 6503 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
tushki7 0:60d829a0353a 6504 * @{
tushki7 0:60d829a0353a 6505 */
tushki7 0:60d829a0353a 6506
tushki7 0:60d829a0353a 6507
tushki7 0:60d829a0353a 6508 /* ROM - Register accessors */
tushki7 0:60d829a0353a 6509 #define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index])
tushki7 0:60d829a0353a 6510 #define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK)
tushki7 0:60d829a0353a 6511 #define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS)
tushki7 0:60d829a0353a 6512 #define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4)
tushki7 0:60d829a0353a 6513 #define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5)
tushki7 0:60d829a0353a 6514 #define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6)
tushki7 0:60d829a0353a 6515 #define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7)
tushki7 0:60d829a0353a 6516 #define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0)
tushki7 0:60d829a0353a 6517 #define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1)
tushki7 0:60d829a0353a 6518 #define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2)
tushki7 0:60d829a0353a 6519 #define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3)
tushki7 0:60d829a0353a 6520 #define ROM_COMPID_REG(base,index) ((base)->COMPID[index])
tushki7 0:60d829a0353a 6521
tushki7 0:60d829a0353a 6522 /*!
tushki7 0:60d829a0353a 6523 * @}
tushki7 0:60d829a0353a 6524 */ /* end of group ROM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6525
tushki7 0:60d829a0353a 6526
tushki7 0:60d829a0353a 6527 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6528 -- ROM Register Masks
tushki7 0:60d829a0353a 6529 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6530
tushki7 0:60d829a0353a 6531 /*!
tushki7 0:60d829a0353a 6532 * @addtogroup ROM_Register_Masks ROM Register Masks
tushki7 0:60d829a0353a 6533 * @{
tushki7 0:60d829a0353a 6534 */
tushki7 0:60d829a0353a 6535
tushki7 0:60d829a0353a 6536 /* ENTRY Bit Fields */
tushki7 0:60d829a0353a 6537 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6538 #define ROM_ENTRY_ENTRY_SHIFT 0
tushki7 0:60d829a0353a 6539 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
tushki7 0:60d829a0353a 6540 /* TABLEMARK Bit Fields */
tushki7 0:60d829a0353a 6541 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6542 #define ROM_TABLEMARK_MARK_SHIFT 0
tushki7 0:60d829a0353a 6543 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
tushki7 0:60d829a0353a 6544 /* SYSACCESS Bit Fields */
tushki7 0:60d829a0353a 6545 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6546 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
tushki7 0:60d829a0353a 6547 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
tushki7 0:60d829a0353a 6548 /* PERIPHID4 Bit Fields */
tushki7 0:60d829a0353a 6549 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6550 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 6551 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
tushki7 0:60d829a0353a 6552 /* PERIPHID5 Bit Fields */
tushki7 0:60d829a0353a 6553 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6554 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 6555 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
tushki7 0:60d829a0353a 6556 /* PERIPHID6 Bit Fields */
tushki7 0:60d829a0353a 6557 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6558 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 6559 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
tushki7 0:60d829a0353a 6560 /* PERIPHID7 Bit Fields */
tushki7 0:60d829a0353a 6561 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6562 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 6563 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
tushki7 0:60d829a0353a 6564 /* PERIPHID0 Bit Fields */
tushki7 0:60d829a0353a 6565 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6566 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 6567 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
tushki7 0:60d829a0353a 6568 /* PERIPHID1 Bit Fields */
tushki7 0:60d829a0353a 6569 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6570 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 6571 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
tushki7 0:60d829a0353a 6572 /* PERIPHID2 Bit Fields */
tushki7 0:60d829a0353a 6573 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6574 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 6575 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
tushki7 0:60d829a0353a 6576 /* PERIPHID3 Bit Fields */
tushki7 0:60d829a0353a 6577 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6578 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
tushki7 0:60d829a0353a 6579 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
tushki7 0:60d829a0353a 6580 /* COMPID Bit Fields */
tushki7 0:60d829a0353a 6581 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6582 #define ROM_COMPID_COMPID_SHIFT 0
tushki7 0:60d829a0353a 6583 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
tushki7 0:60d829a0353a 6584
tushki7 0:60d829a0353a 6585 /*!
tushki7 0:60d829a0353a 6586 * @}
tushki7 0:60d829a0353a 6587 */ /* end of group ROM_Register_Masks */
tushki7 0:60d829a0353a 6588
tushki7 0:60d829a0353a 6589
tushki7 0:60d829a0353a 6590 /* ROM - Peripheral instance base addresses */
tushki7 0:60d829a0353a 6591 /** Peripheral ROM base address */
tushki7 0:60d829a0353a 6592 #define ROM_BASE (0xF0002000u)
tushki7 0:60d829a0353a 6593 /** Peripheral ROM base pointer */
tushki7 0:60d829a0353a 6594 #define ROM ((ROM_Type *)ROM_BASE)
tushki7 0:60d829a0353a 6595 #define ROM_BASE_PTR (ROM)
tushki7 0:60d829a0353a 6596 /** Array initializer of ROM peripheral base addresses */
tushki7 0:60d829a0353a 6597 #define ROM_BASE_ADDRS { ROM_BASE }
tushki7 0:60d829a0353a 6598 /** Array initializer of ROM peripheral base pointers */
tushki7 0:60d829a0353a 6599 #define ROM_BASE_PTRS { ROM }
tushki7 0:60d829a0353a 6600
tushki7 0:60d829a0353a 6601 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6602 -- ROM - Register accessor macros
tushki7 0:60d829a0353a 6603 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6604
tushki7 0:60d829a0353a 6605 /*!
tushki7 0:60d829a0353a 6606 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
tushki7 0:60d829a0353a 6607 * @{
tushki7 0:60d829a0353a 6608 */
tushki7 0:60d829a0353a 6609
tushki7 0:60d829a0353a 6610
tushki7 0:60d829a0353a 6611 /* ROM - Register instance definitions */
tushki7 0:60d829a0353a 6612 /* ROM */
tushki7 0:60d829a0353a 6613 #define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0)
tushki7 0:60d829a0353a 6614 #define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1)
tushki7 0:60d829a0353a 6615 #define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2)
tushki7 0:60d829a0353a 6616 #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM)
tushki7 0:60d829a0353a 6617 #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM)
tushki7 0:60d829a0353a 6618 #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM)
tushki7 0:60d829a0353a 6619 #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM)
tushki7 0:60d829a0353a 6620 #define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM)
tushki7 0:60d829a0353a 6621 #define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM)
tushki7 0:60d829a0353a 6622 #define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM)
tushki7 0:60d829a0353a 6623 #define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM)
tushki7 0:60d829a0353a 6624 #define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM)
tushki7 0:60d829a0353a 6625 #define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM)
tushki7 0:60d829a0353a 6626 #define ROM_COMPID0 ROM_COMPID_REG(ROM,0)
tushki7 0:60d829a0353a 6627 #define ROM_COMPID1 ROM_COMPID_REG(ROM,1)
tushki7 0:60d829a0353a 6628 #define ROM_COMPID2 ROM_COMPID_REG(ROM,2)
tushki7 0:60d829a0353a 6629 #define ROM_COMPID3 ROM_COMPID_REG(ROM,3)
tushki7 0:60d829a0353a 6630
tushki7 0:60d829a0353a 6631 /* ROM - Register array accessors */
tushki7 0:60d829a0353a 6632 #define ROM_ENTRY(index) ROM_ENTRY_REG(ROM,index)
tushki7 0:60d829a0353a 6633 #define ROM_COMPID(index) ROM_COMPID_REG(ROM,index)
tushki7 0:60d829a0353a 6634
tushki7 0:60d829a0353a 6635 /*!
tushki7 0:60d829a0353a 6636 * @}
tushki7 0:60d829a0353a 6637 */ /* end of group ROM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6638
tushki7 0:60d829a0353a 6639
tushki7 0:60d829a0353a 6640 /*!
tushki7 0:60d829a0353a 6641 * @}
tushki7 0:60d829a0353a 6642 */ /* end of group ROM_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 6643
tushki7 0:60d829a0353a 6644
tushki7 0:60d829a0353a 6645 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6646 -- RTC Peripheral Access Layer
tushki7 0:60d829a0353a 6647 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6648
tushki7 0:60d829a0353a 6649 /*!
tushki7 0:60d829a0353a 6650 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
tushki7 0:60d829a0353a 6651 * @{
tushki7 0:60d829a0353a 6652 */
tushki7 0:60d829a0353a 6653
tushki7 0:60d829a0353a 6654 /** RTC - Register Layout Typedef */
tushki7 0:60d829a0353a 6655 typedef struct {
tushki7 0:60d829a0353a 6656 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
tushki7 0:60d829a0353a 6657 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
tushki7 0:60d829a0353a 6658 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
tushki7 0:60d829a0353a 6659 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
tushki7 0:60d829a0353a 6660 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
tushki7 0:60d829a0353a 6661 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
tushki7 0:60d829a0353a 6662 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
tushki7 0:60d829a0353a 6663 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
tushki7 0:60d829a0353a 6664 } RTC_Type, *RTC_MemMapPtr;
tushki7 0:60d829a0353a 6665
tushki7 0:60d829a0353a 6666 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6667 -- RTC - Register accessor macros
tushki7 0:60d829a0353a 6668 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6669
tushki7 0:60d829a0353a 6670 /*!
tushki7 0:60d829a0353a 6671 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
tushki7 0:60d829a0353a 6672 * @{
tushki7 0:60d829a0353a 6673 */
tushki7 0:60d829a0353a 6674
tushki7 0:60d829a0353a 6675
tushki7 0:60d829a0353a 6676 /* RTC - Register accessors */
tushki7 0:60d829a0353a 6677 #define RTC_TSR_REG(base) ((base)->TSR)
tushki7 0:60d829a0353a 6678 #define RTC_TPR_REG(base) ((base)->TPR)
tushki7 0:60d829a0353a 6679 #define RTC_TAR_REG(base) ((base)->TAR)
tushki7 0:60d829a0353a 6680 #define RTC_TCR_REG(base) ((base)->TCR)
tushki7 0:60d829a0353a 6681 #define RTC_CR_REG(base) ((base)->CR)
tushki7 0:60d829a0353a 6682 #define RTC_SR_REG(base) ((base)->SR)
tushki7 0:60d829a0353a 6683 #define RTC_LR_REG(base) ((base)->LR)
tushki7 0:60d829a0353a 6684 #define RTC_IER_REG(base) ((base)->IER)
tushki7 0:60d829a0353a 6685
tushki7 0:60d829a0353a 6686 /*!
tushki7 0:60d829a0353a 6687 * @}
tushki7 0:60d829a0353a 6688 */ /* end of group RTC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6689
tushki7 0:60d829a0353a 6690
tushki7 0:60d829a0353a 6691 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6692 -- RTC Register Masks
tushki7 0:60d829a0353a 6693 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6694
tushki7 0:60d829a0353a 6695 /*!
tushki7 0:60d829a0353a 6696 * @addtogroup RTC_Register_Masks RTC Register Masks
tushki7 0:60d829a0353a 6697 * @{
tushki7 0:60d829a0353a 6698 */
tushki7 0:60d829a0353a 6699
tushki7 0:60d829a0353a 6700 /* TSR Bit Fields */
tushki7 0:60d829a0353a 6701 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6702 #define RTC_TSR_TSR_SHIFT 0
tushki7 0:60d829a0353a 6703 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
tushki7 0:60d829a0353a 6704 /* TPR Bit Fields */
tushki7 0:60d829a0353a 6705 #define RTC_TPR_TPR_MASK 0xFFFFu
tushki7 0:60d829a0353a 6706 #define RTC_TPR_TPR_SHIFT 0
tushki7 0:60d829a0353a 6707 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
tushki7 0:60d829a0353a 6708 /* TAR Bit Fields */
tushki7 0:60d829a0353a 6709 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 6710 #define RTC_TAR_TAR_SHIFT 0
tushki7 0:60d829a0353a 6711 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
tushki7 0:60d829a0353a 6712 /* TCR Bit Fields */
tushki7 0:60d829a0353a 6713 #define RTC_TCR_TCR_MASK 0xFFu
tushki7 0:60d829a0353a 6714 #define RTC_TCR_TCR_SHIFT 0
tushki7 0:60d829a0353a 6715 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
tushki7 0:60d829a0353a 6716 #define RTC_TCR_CIR_MASK 0xFF00u
tushki7 0:60d829a0353a 6717 #define RTC_TCR_CIR_SHIFT 8
tushki7 0:60d829a0353a 6718 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
tushki7 0:60d829a0353a 6719 #define RTC_TCR_TCV_MASK 0xFF0000u
tushki7 0:60d829a0353a 6720 #define RTC_TCR_TCV_SHIFT 16
tushki7 0:60d829a0353a 6721 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
tushki7 0:60d829a0353a 6722 #define RTC_TCR_CIC_MASK 0xFF000000u
tushki7 0:60d829a0353a 6723 #define RTC_TCR_CIC_SHIFT 24
tushki7 0:60d829a0353a 6724 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
tushki7 0:60d829a0353a 6725 /* CR Bit Fields */
tushki7 0:60d829a0353a 6726 #define RTC_CR_SWR_MASK 0x1u
tushki7 0:60d829a0353a 6727 #define RTC_CR_SWR_SHIFT 0
tushki7 0:60d829a0353a 6728 #define RTC_CR_WPE_MASK 0x2u
tushki7 0:60d829a0353a 6729 #define RTC_CR_WPE_SHIFT 1
tushki7 0:60d829a0353a 6730 #define RTC_CR_SUP_MASK 0x4u
tushki7 0:60d829a0353a 6731 #define RTC_CR_SUP_SHIFT 2
tushki7 0:60d829a0353a 6732 #define RTC_CR_UM_MASK 0x8u
tushki7 0:60d829a0353a 6733 #define RTC_CR_UM_SHIFT 3
tushki7 0:60d829a0353a 6734 #define RTC_CR_WPS_MASK 0x10u
tushki7 0:60d829a0353a 6735 #define RTC_CR_WPS_SHIFT 4
tushki7 0:60d829a0353a 6736 #define RTC_CR_OSCE_MASK 0x100u
tushki7 0:60d829a0353a 6737 #define RTC_CR_OSCE_SHIFT 8
tushki7 0:60d829a0353a 6738 #define RTC_CR_CLKO_MASK 0x200u
tushki7 0:60d829a0353a 6739 #define RTC_CR_CLKO_SHIFT 9
tushki7 0:60d829a0353a 6740 #define RTC_CR_SC16P_MASK 0x400u
tushki7 0:60d829a0353a 6741 #define RTC_CR_SC16P_SHIFT 10
tushki7 0:60d829a0353a 6742 #define RTC_CR_SC8P_MASK 0x800u
tushki7 0:60d829a0353a 6743 #define RTC_CR_SC8P_SHIFT 11
tushki7 0:60d829a0353a 6744 #define RTC_CR_SC4P_MASK 0x1000u
tushki7 0:60d829a0353a 6745 #define RTC_CR_SC4P_SHIFT 12
tushki7 0:60d829a0353a 6746 #define RTC_CR_SC2P_MASK 0x2000u
tushki7 0:60d829a0353a 6747 #define RTC_CR_SC2P_SHIFT 13
tushki7 0:60d829a0353a 6748 /* SR Bit Fields */
tushki7 0:60d829a0353a 6749 #define RTC_SR_TIF_MASK 0x1u
tushki7 0:60d829a0353a 6750 #define RTC_SR_TIF_SHIFT 0
tushki7 0:60d829a0353a 6751 #define RTC_SR_TOF_MASK 0x2u
tushki7 0:60d829a0353a 6752 #define RTC_SR_TOF_SHIFT 1
tushki7 0:60d829a0353a 6753 #define RTC_SR_TAF_MASK 0x4u
tushki7 0:60d829a0353a 6754 #define RTC_SR_TAF_SHIFT 2
tushki7 0:60d829a0353a 6755 #define RTC_SR_TCE_MASK 0x10u
tushki7 0:60d829a0353a 6756 #define RTC_SR_TCE_SHIFT 4
tushki7 0:60d829a0353a 6757 /* LR Bit Fields */
tushki7 0:60d829a0353a 6758 #define RTC_LR_TCL_MASK 0x8u
tushki7 0:60d829a0353a 6759 #define RTC_LR_TCL_SHIFT 3
tushki7 0:60d829a0353a 6760 #define RTC_LR_CRL_MASK 0x10u
tushki7 0:60d829a0353a 6761 #define RTC_LR_CRL_SHIFT 4
tushki7 0:60d829a0353a 6762 #define RTC_LR_SRL_MASK 0x20u
tushki7 0:60d829a0353a 6763 #define RTC_LR_SRL_SHIFT 5
tushki7 0:60d829a0353a 6764 #define RTC_LR_LRL_MASK 0x40u
tushki7 0:60d829a0353a 6765 #define RTC_LR_LRL_SHIFT 6
tushki7 0:60d829a0353a 6766 /* IER Bit Fields */
tushki7 0:60d829a0353a 6767 #define RTC_IER_TIIE_MASK 0x1u
tushki7 0:60d829a0353a 6768 #define RTC_IER_TIIE_SHIFT 0
tushki7 0:60d829a0353a 6769 #define RTC_IER_TOIE_MASK 0x2u
tushki7 0:60d829a0353a 6770 #define RTC_IER_TOIE_SHIFT 1
tushki7 0:60d829a0353a 6771 #define RTC_IER_TAIE_MASK 0x4u
tushki7 0:60d829a0353a 6772 #define RTC_IER_TAIE_SHIFT 2
tushki7 0:60d829a0353a 6773 #define RTC_IER_TSIE_MASK 0x10u
tushki7 0:60d829a0353a 6774 #define RTC_IER_TSIE_SHIFT 4
tushki7 0:60d829a0353a 6775 #define RTC_IER_WPON_MASK 0x80u
tushki7 0:60d829a0353a 6776 #define RTC_IER_WPON_SHIFT 7
tushki7 0:60d829a0353a 6777
tushki7 0:60d829a0353a 6778 /*!
tushki7 0:60d829a0353a 6779 * @}
tushki7 0:60d829a0353a 6780 */ /* end of group RTC_Register_Masks */
tushki7 0:60d829a0353a 6781
tushki7 0:60d829a0353a 6782
tushki7 0:60d829a0353a 6783 /* RTC - Peripheral instance base addresses */
tushki7 0:60d829a0353a 6784 /** Peripheral RTC base address */
tushki7 0:60d829a0353a 6785 #define RTC_BASE (0x4003D000u)
tushki7 0:60d829a0353a 6786 /** Peripheral RTC base pointer */
tushki7 0:60d829a0353a 6787 #define RTC ((RTC_Type *)RTC_BASE)
tushki7 0:60d829a0353a 6788 #define RTC_BASE_PTR (RTC)
tushki7 0:60d829a0353a 6789 /** Array initializer of RTC peripheral base addresses */
tushki7 0:60d829a0353a 6790 #define RTC_BASE_ADDRS { RTC_BASE }
tushki7 0:60d829a0353a 6791 /** Array initializer of RTC peripheral base pointers */
tushki7 0:60d829a0353a 6792 #define RTC_BASE_PTRS { RTC }
tushki7 0:60d829a0353a 6793 /** Interrupt vectors for the RTC peripheral type */
tushki7 0:60d829a0353a 6794 #define RTC_IRQS { RTC_IRQn }
tushki7 0:60d829a0353a 6795 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
tushki7 0:60d829a0353a 6796
tushki7 0:60d829a0353a 6797 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6798 -- RTC - Register accessor macros
tushki7 0:60d829a0353a 6799 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6800
tushki7 0:60d829a0353a 6801 /*!
tushki7 0:60d829a0353a 6802 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
tushki7 0:60d829a0353a 6803 * @{
tushki7 0:60d829a0353a 6804 */
tushki7 0:60d829a0353a 6805
tushki7 0:60d829a0353a 6806
tushki7 0:60d829a0353a 6807 /* RTC - Register instance definitions */
tushki7 0:60d829a0353a 6808 /* RTC */
tushki7 0:60d829a0353a 6809 #define RTC_TSR RTC_TSR_REG(RTC)
tushki7 0:60d829a0353a 6810 #define RTC_TPR RTC_TPR_REG(RTC)
tushki7 0:60d829a0353a 6811 #define RTC_TAR RTC_TAR_REG(RTC)
tushki7 0:60d829a0353a 6812 #define RTC_TCR RTC_TCR_REG(RTC)
tushki7 0:60d829a0353a 6813 #define RTC_CR RTC_CR_REG(RTC)
tushki7 0:60d829a0353a 6814 #define RTC_SR RTC_SR_REG(RTC)
tushki7 0:60d829a0353a 6815 #define RTC_LR RTC_LR_REG(RTC)
tushki7 0:60d829a0353a 6816 #define RTC_IER RTC_IER_REG(RTC)
tushki7 0:60d829a0353a 6817
tushki7 0:60d829a0353a 6818 /*!
tushki7 0:60d829a0353a 6819 * @}
tushki7 0:60d829a0353a 6820 */ /* end of group RTC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6821
tushki7 0:60d829a0353a 6822
tushki7 0:60d829a0353a 6823 /*!
tushki7 0:60d829a0353a 6824 * @}
tushki7 0:60d829a0353a 6825 */ /* end of group RTC_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 6826
tushki7 0:60d829a0353a 6827
tushki7 0:60d829a0353a 6828 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6829 -- SIM Peripheral Access Layer
tushki7 0:60d829a0353a 6830 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6831
tushki7 0:60d829a0353a 6832 /*!
tushki7 0:60d829a0353a 6833 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
tushki7 0:60d829a0353a 6834 * @{
tushki7 0:60d829a0353a 6835 */
tushki7 0:60d829a0353a 6836
tushki7 0:60d829a0353a 6837 /** SIM - Register Layout Typedef */
tushki7 0:60d829a0353a 6838 typedef struct {
tushki7 0:60d829a0353a 6839 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
tushki7 0:60d829a0353a 6840 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
tushki7 0:60d829a0353a 6841 uint8_t RESERVED_0[4092];
tushki7 0:60d829a0353a 6842 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
tushki7 0:60d829a0353a 6843 uint8_t RESERVED_1[4];
tushki7 0:60d829a0353a 6844 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
tushki7 0:60d829a0353a 6845 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
tushki7 0:60d829a0353a 6846 uint8_t RESERVED_2[4];
tushki7 0:60d829a0353a 6847 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
tushki7 0:60d829a0353a 6848 uint8_t RESERVED_3[8];
tushki7 0:60d829a0353a 6849 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
tushki7 0:60d829a0353a 6850 uint8_t RESERVED_4[12];
tushki7 0:60d829a0353a 6851 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
tushki7 0:60d829a0353a 6852 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
tushki7 0:60d829a0353a 6853 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
tushki7 0:60d829a0353a 6854 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
tushki7 0:60d829a0353a 6855 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
tushki7 0:60d829a0353a 6856 uint8_t RESERVED_5[4];
tushki7 0:60d829a0353a 6857 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
tushki7 0:60d829a0353a 6858 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
tushki7 0:60d829a0353a 6859 uint8_t RESERVED_6[4];
tushki7 0:60d829a0353a 6860 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
tushki7 0:60d829a0353a 6861 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
tushki7 0:60d829a0353a 6862 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
tushki7 0:60d829a0353a 6863 uint8_t RESERVED_7[156];
tushki7 0:60d829a0353a 6864 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
tushki7 0:60d829a0353a 6865 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
tushki7 0:60d829a0353a 6866 } SIM_Type, *SIM_MemMapPtr;
tushki7 0:60d829a0353a 6867
tushki7 0:60d829a0353a 6868 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6869 -- SIM - Register accessor macros
tushki7 0:60d829a0353a 6870 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6871
tushki7 0:60d829a0353a 6872 /*!
tushki7 0:60d829a0353a 6873 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
tushki7 0:60d829a0353a 6874 * @{
tushki7 0:60d829a0353a 6875 */
tushki7 0:60d829a0353a 6876
tushki7 0:60d829a0353a 6877
tushki7 0:60d829a0353a 6878 /* SIM - Register accessors */
tushki7 0:60d829a0353a 6879 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
tushki7 0:60d829a0353a 6880 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
tushki7 0:60d829a0353a 6881 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
tushki7 0:60d829a0353a 6882 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
tushki7 0:60d829a0353a 6883 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
tushki7 0:60d829a0353a 6884 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
tushki7 0:60d829a0353a 6885 #define SIM_SDID_REG(base) ((base)->SDID)
tushki7 0:60d829a0353a 6886 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
tushki7 0:60d829a0353a 6887 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
tushki7 0:60d829a0353a 6888 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
tushki7 0:60d829a0353a 6889 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
tushki7 0:60d829a0353a 6890 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
tushki7 0:60d829a0353a 6891 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
tushki7 0:60d829a0353a 6892 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
tushki7 0:60d829a0353a 6893 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
tushki7 0:60d829a0353a 6894 #define SIM_UIDML_REG(base) ((base)->UIDML)
tushki7 0:60d829a0353a 6895 #define SIM_UIDL_REG(base) ((base)->UIDL)
tushki7 0:60d829a0353a 6896 #define SIM_COPC_REG(base) ((base)->COPC)
tushki7 0:60d829a0353a 6897 #define SIM_SRVCOP_REG(base) ((base)->SRVCOP)
tushki7 0:60d829a0353a 6898
tushki7 0:60d829a0353a 6899 /*!
tushki7 0:60d829a0353a 6900 * @}
tushki7 0:60d829a0353a 6901 */ /* end of group SIM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 6902
tushki7 0:60d829a0353a 6903
tushki7 0:60d829a0353a 6904 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 6905 -- SIM Register Masks
tushki7 0:60d829a0353a 6906 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 6907
tushki7 0:60d829a0353a 6908 /*!
tushki7 0:60d829a0353a 6909 * @addtogroup SIM_Register_Masks SIM Register Masks
tushki7 0:60d829a0353a 6910 * @{
tushki7 0:60d829a0353a 6911 */
tushki7 0:60d829a0353a 6912
tushki7 0:60d829a0353a 6913 /* SOPT1 Bit Fields */
tushki7 0:60d829a0353a 6914 #define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
tushki7 0:60d829a0353a 6915 #define SIM_SOPT1_OSC32KOUT_SHIFT 16
tushki7 0:60d829a0353a 6916 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
tushki7 0:60d829a0353a 6917 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
tushki7 0:60d829a0353a 6918 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
tushki7 0:60d829a0353a 6919 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
tushki7 0:60d829a0353a 6920 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
tushki7 0:60d829a0353a 6921 #define SIM_SOPT1_USBVSTBY_SHIFT 29
tushki7 0:60d829a0353a 6922 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
tushki7 0:60d829a0353a 6923 #define SIM_SOPT1_USBSSTBY_SHIFT 30
tushki7 0:60d829a0353a 6924 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
tushki7 0:60d829a0353a 6925 #define SIM_SOPT1_USBREGEN_SHIFT 31
tushki7 0:60d829a0353a 6926 /* SOPT1CFG Bit Fields */
tushki7 0:60d829a0353a 6927 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
tushki7 0:60d829a0353a 6928 #define SIM_SOPT1CFG_URWE_SHIFT 24
tushki7 0:60d829a0353a 6929 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
tushki7 0:60d829a0353a 6930 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
tushki7 0:60d829a0353a 6931 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
tushki7 0:60d829a0353a 6932 #define SIM_SOPT1CFG_USSWE_SHIFT 26
tushki7 0:60d829a0353a 6933 /* SOPT2 Bit Fields */
tushki7 0:60d829a0353a 6934 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
tushki7 0:60d829a0353a 6935 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
tushki7 0:60d829a0353a 6936 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
tushki7 0:60d829a0353a 6937 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
tushki7 0:60d829a0353a 6938 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
tushki7 0:60d829a0353a 6939 #define SIM_SOPT2_USBSRC_MASK 0x40000u
tushki7 0:60d829a0353a 6940 #define SIM_SOPT2_USBSRC_SHIFT 18
tushki7 0:60d829a0353a 6941 #define SIM_SOPT2_FLEXIOSRC_MASK 0xC00000u
tushki7 0:60d829a0353a 6942 #define SIM_SOPT2_FLEXIOSRC_SHIFT 22
tushki7 0:60d829a0353a 6943 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
tushki7 0:60d829a0353a 6944 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
tushki7 0:60d829a0353a 6945 #define SIM_SOPT2_TPMSRC_SHIFT 24
tushki7 0:60d829a0353a 6946 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
tushki7 0:60d829a0353a 6947 #define SIM_SOPT2_LPUART0SRC_MASK 0xC000000u
tushki7 0:60d829a0353a 6948 #define SIM_SOPT2_LPUART0SRC_SHIFT 26
tushki7 0:60d829a0353a 6949 #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART0SRC_SHIFT))&SIM_SOPT2_LPUART0SRC_MASK)
tushki7 0:60d829a0353a 6950 #define SIM_SOPT2_LPUART1SRC_MASK 0x30000000u
tushki7 0:60d829a0353a 6951 #define SIM_SOPT2_LPUART1SRC_SHIFT 28
tushki7 0:60d829a0353a 6952 #define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART1SRC_SHIFT))&SIM_SOPT2_LPUART1SRC_MASK)
tushki7 0:60d829a0353a 6953 /* SOPT4 Bit Fields */
tushki7 0:60d829a0353a 6954 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
tushki7 0:60d829a0353a 6955 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
tushki7 0:60d829a0353a 6956 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
tushki7 0:60d829a0353a 6957 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
tushki7 0:60d829a0353a 6958 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
tushki7 0:60d829a0353a 6959 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
tushki7 0:60d829a0353a 6960 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
tushki7 0:60d829a0353a 6961 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
tushki7 0:60d829a0353a 6962 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
tushki7 0:60d829a0353a 6963 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
tushki7 0:60d829a0353a 6964 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
tushki7 0:60d829a0353a 6965 /* SOPT5 Bit Fields */
tushki7 0:60d829a0353a 6966 #define SIM_SOPT5_LPUART0TXSRC_MASK 0x3u
tushki7 0:60d829a0353a 6967 #define SIM_SOPT5_LPUART0TXSRC_SHIFT 0
tushki7 0:60d829a0353a 6968 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
tushki7 0:60d829a0353a 6969 #define SIM_SOPT5_LPUART0RXSRC_MASK 0x4u
tushki7 0:60d829a0353a 6970 #define SIM_SOPT5_LPUART0RXSRC_SHIFT 2
tushki7 0:60d829a0353a 6971 #define SIM_SOPT5_LPUART1TXSRC_MASK 0x30u
tushki7 0:60d829a0353a 6972 #define SIM_SOPT5_LPUART1TXSRC_SHIFT 4
tushki7 0:60d829a0353a 6973 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1TXSRC_SHIFT))&SIM_SOPT5_LPUART1TXSRC_MASK)
tushki7 0:60d829a0353a 6974 #define SIM_SOPT5_LPUART1RXSRC_MASK 0x40u
tushki7 0:60d829a0353a 6975 #define SIM_SOPT5_LPUART1RXSRC_SHIFT 6
tushki7 0:60d829a0353a 6976 #define SIM_SOPT5_LPUART0ODE_MASK 0x10000u
tushki7 0:60d829a0353a 6977 #define SIM_SOPT5_LPUART0ODE_SHIFT 16
tushki7 0:60d829a0353a 6978 #define SIM_SOPT5_LPUART1ODE_MASK 0x20000u
tushki7 0:60d829a0353a 6979 #define SIM_SOPT5_LPUART1ODE_SHIFT 17
tushki7 0:60d829a0353a 6980 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
tushki7 0:60d829a0353a 6981 #define SIM_SOPT5_UART2ODE_SHIFT 18
tushki7 0:60d829a0353a 6982 /* SOPT7 Bit Fields */
tushki7 0:60d829a0353a 6983 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
tushki7 0:60d829a0353a 6984 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
tushki7 0:60d829a0353a 6985 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
tushki7 0:60d829a0353a 6986 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
tushki7 0:60d829a0353a 6987 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
tushki7 0:60d829a0353a 6988 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
tushki7 0:60d829a0353a 6989 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
tushki7 0:60d829a0353a 6990 /* SDID Bit Fields */
tushki7 0:60d829a0353a 6991 #define SIM_SDID_PINID_MASK 0xFu
tushki7 0:60d829a0353a 6992 #define SIM_SDID_PINID_SHIFT 0
tushki7 0:60d829a0353a 6993 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
tushki7 0:60d829a0353a 6994 #define SIM_SDID_REVID_MASK 0xF000u
tushki7 0:60d829a0353a 6995 #define SIM_SDID_REVID_SHIFT 12
tushki7 0:60d829a0353a 6996 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
tushki7 0:60d829a0353a 6997 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
tushki7 0:60d829a0353a 6998 #define SIM_SDID_SRAMSIZE_SHIFT 16
tushki7 0:60d829a0353a 6999 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
tushki7 0:60d829a0353a 7000 #define SIM_SDID_SERIESID_MASK 0xF00000u
tushki7 0:60d829a0353a 7001 #define SIM_SDID_SERIESID_SHIFT 20
tushki7 0:60d829a0353a 7002 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
tushki7 0:60d829a0353a 7003 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
tushki7 0:60d829a0353a 7004 #define SIM_SDID_SUBFAMID_SHIFT 24
tushki7 0:60d829a0353a 7005 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
tushki7 0:60d829a0353a 7006 #define SIM_SDID_FAMID_MASK 0xF0000000u
tushki7 0:60d829a0353a 7007 #define SIM_SDID_FAMID_SHIFT 28
tushki7 0:60d829a0353a 7008 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
tushki7 0:60d829a0353a 7009 /* SCGC4 Bit Fields */
tushki7 0:60d829a0353a 7010 #define SIM_SCGC4_I2C0_MASK 0x40u
tushki7 0:60d829a0353a 7011 #define SIM_SCGC4_I2C0_SHIFT 6
tushki7 0:60d829a0353a 7012 #define SIM_SCGC4_I2C1_MASK 0x80u
tushki7 0:60d829a0353a 7013 #define SIM_SCGC4_I2C1_SHIFT 7
tushki7 0:60d829a0353a 7014 #define SIM_SCGC4_UART2_MASK 0x1000u
tushki7 0:60d829a0353a 7015 #define SIM_SCGC4_UART2_SHIFT 12
tushki7 0:60d829a0353a 7016 #define SIM_SCGC4_USBFS_MASK 0x40000u
tushki7 0:60d829a0353a 7017 #define SIM_SCGC4_USBFS_SHIFT 18
tushki7 0:60d829a0353a 7018 #define SIM_SCGC4_CMP0_MASK 0x80000u
tushki7 0:60d829a0353a 7019 #define SIM_SCGC4_CMP0_SHIFT 19
tushki7 0:60d829a0353a 7020 #define SIM_SCGC4_VREF_MASK 0x100000u
tushki7 0:60d829a0353a 7021 #define SIM_SCGC4_VREF_SHIFT 20
tushki7 0:60d829a0353a 7022 #define SIM_SCGC4_SPI0_MASK 0x400000u
tushki7 0:60d829a0353a 7023 #define SIM_SCGC4_SPI0_SHIFT 22
tushki7 0:60d829a0353a 7024 #define SIM_SCGC4_SPI1_MASK 0x800000u
tushki7 0:60d829a0353a 7025 #define SIM_SCGC4_SPI1_SHIFT 23
tushki7 0:60d829a0353a 7026 /* SCGC5 Bit Fields */
tushki7 0:60d829a0353a 7027 #define SIM_SCGC5_LPTMR_MASK 0x1u
tushki7 0:60d829a0353a 7028 #define SIM_SCGC5_LPTMR_SHIFT 0
tushki7 0:60d829a0353a 7029 #define SIM_SCGC5_PORTA_MASK 0x200u
tushki7 0:60d829a0353a 7030 #define SIM_SCGC5_PORTA_SHIFT 9
tushki7 0:60d829a0353a 7031 #define SIM_SCGC5_PORTB_MASK 0x400u
tushki7 0:60d829a0353a 7032 #define SIM_SCGC5_PORTB_SHIFT 10
tushki7 0:60d829a0353a 7033 #define SIM_SCGC5_PORTC_MASK 0x800u
tushki7 0:60d829a0353a 7034 #define SIM_SCGC5_PORTC_SHIFT 11
tushki7 0:60d829a0353a 7035 #define SIM_SCGC5_PORTD_MASK 0x1000u
tushki7 0:60d829a0353a 7036 #define SIM_SCGC5_PORTD_SHIFT 12
tushki7 0:60d829a0353a 7037 #define SIM_SCGC5_PORTE_MASK 0x2000u
tushki7 0:60d829a0353a 7038 #define SIM_SCGC5_PORTE_SHIFT 13
tushki7 0:60d829a0353a 7039 #define SIM_SCGC5_SLCD_MASK 0x80000u
tushki7 0:60d829a0353a 7040 #define SIM_SCGC5_SLCD_SHIFT 19
tushki7 0:60d829a0353a 7041 #define SIM_SCGC5_LPUART0_MASK 0x100000u
tushki7 0:60d829a0353a 7042 #define SIM_SCGC5_LPUART0_SHIFT 20
tushki7 0:60d829a0353a 7043 #define SIM_SCGC5_LPUART1_MASK 0x200000u
tushki7 0:60d829a0353a 7044 #define SIM_SCGC5_LPUART1_SHIFT 21
tushki7 0:60d829a0353a 7045 #define SIM_SCGC5_FLEXIO_MASK 0x80000000u
tushki7 0:60d829a0353a 7046 #define SIM_SCGC5_FLEXIO_SHIFT 31
tushki7 0:60d829a0353a 7047 /* SCGC6 Bit Fields */
tushki7 0:60d829a0353a 7048 #define SIM_SCGC6_FTF_MASK 0x1u
tushki7 0:60d829a0353a 7049 #define SIM_SCGC6_FTF_SHIFT 0
tushki7 0:60d829a0353a 7050 #define SIM_SCGC6_DMAMUX_MASK 0x2u
tushki7 0:60d829a0353a 7051 #define SIM_SCGC6_DMAMUX_SHIFT 1
tushki7 0:60d829a0353a 7052 #define SIM_SCGC6_I2S_MASK 0x8000u
tushki7 0:60d829a0353a 7053 #define SIM_SCGC6_I2S_SHIFT 15
tushki7 0:60d829a0353a 7054 #define SIM_SCGC6_PIT_MASK 0x800000u
tushki7 0:60d829a0353a 7055 #define SIM_SCGC6_PIT_SHIFT 23
tushki7 0:60d829a0353a 7056 #define SIM_SCGC6_TPM0_MASK 0x1000000u
tushki7 0:60d829a0353a 7057 #define SIM_SCGC6_TPM0_SHIFT 24
tushki7 0:60d829a0353a 7058 #define SIM_SCGC6_TPM1_MASK 0x2000000u
tushki7 0:60d829a0353a 7059 #define SIM_SCGC6_TPM1_SHIFT 25
tushki7 0:60d829a0353a 7060 #define SIM_SCGC6_TPM2_MASK 0x4000000u
tushki7 0:60d829a0353a 7061 #define SIM_SCGC6_TPM2_SHIFT 26
tushki7 0:60d829a0353a 7062 #define SIM_SCGC6_ADC0_MASK 0x8000000u
tushki7 0:60d829a0353a 7063 #define SIM_SCGC6_ADC0_SHIFT 27
tushki7 0:60d829a0353a 7064 #define SIM_SCGC6_RTC_MASK 0x20000000u
tushki7 0:60d829a0353a 7065 #define SIM_SCGC6_RTC_SHIFT 29
tushki7 0:60d829a0353a 7066 #define SIM_SCGC6_DAC0_MASK 0x80000000u
tushki7 0:60d829a0353a 7067 #define SIM_SCGC6_DAC0_SHIFT 31
tushki7 0:60d829a0353a 7068 /* SCGC7 Bit Fields */
tushki7 0:60d829a0353a 7069 #define SIM_SCGC7_DMA_MASK 0x100u
tushki7 0:60d829a0353a 7070 #define SIM_SCGC7_DMA_SHIFT 8
tushki7 0:60d829a0353a 7071 /* CLKDIV1 Bit Fields */
tushki7 0:60d829a0353a 7072 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
tushki7 0:60d829a0353a 7073 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
tushki7 0:60d829a0353a 7074 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
tushki7 0:60d829a0353a 7075 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
tushki7 0:60d829a0353a 7076 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
tushki7 0:60d829a0353a 7077 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
tushki7 0:60d829a0353a 7078 /* FCFG1 Bit Fields */
tushki7 0:60d829a0353a 7079 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
tushki7 0:60d829a0353a 7080 #define SIM_FCFG1_FLASHDIS_SHIFT 0
tushki7 0:60d829a0353a 7081 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
tushki7 0:60d829a0353a 7082 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
tushki7 0:60d829a0353a 7083 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
tushki7 0:60d829a0353a 7084 #define SIM_FCFG1_PFSIZE_SHIFT 24
tushki7 0:60d829a0353a 7085 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
tushki7 0:60d829a0353a 7086 /* FCFG2 Bit Fields */
tushki7 0:60d829a0353a 7087 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
tushki7 0:60d829a0353a 7088 #define SIM_FCFG2_MAXADDR1_SHIFT 16
tushki7 0:60d829a0353a 7089 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
tushki7 0:60d829a0353a 7090 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
tushki7 0:60d829a0353a 7091 #define SIM_FCFG2_MAXADDR0_SHIFT 24
tushki7 0:60d829a0353a 7092 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
tushki7 0:60d829a0353a 7093 /* UIDMH Bit Fields */
tushki7 0:60d829a0353a 7094 #define SIM_UIDMH_UID_MASK 0xFFFFu
tushki7 0:60d829a0353a 7095 #define SIM_UIDMH_UID_SHIFT 0
tushki7 0:60d829a0353a 7096 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
tushki7 0:60d829a0353a 7097 /* UIDML Bit Fields */
tushki7 0:60d829a0353a 7098 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 7099 #define SIM_UIDML_UID_SHIFT 0
tushki7 0:60d829a0353a 7100 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
tushki7 0:60d829a0353a 7101 /* UIDL Bit Fields */
tushki7 0:60d829a0353a 7102 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
tushki7 0:60d829a0353a 7103 #define SIM_UIDL_UID_SHIFT 0
tushki7 0:60d829a0353a 7104 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
tushki7 0:60d829a0353a 7105 /* COPC Bit Fields */
tushki7 0:60d829a0353a 7106 #define SIM_COPC_COPW_MASK 0x1u
tushki7 0:60d829a0353a 7107 #define SIM_COPC_COPW_SHIFT 0
tushki7 0:60d829a0353a 7108 #define SIM_COPC_COPCLKS_MASK 0x2u
tushki7 0:60d829a0353a 7109 #define SIM_COPC_COPCLKS_SHIFT 1
tushki7 0:60d829a0353a 7110 #define SIM_COPC_COPT_MASK 0xCu
tushki7 0:60d829a0353a 7111 #define SIM_COPC_COPT_SHIFT 2
tushki7 0:60d829a0353a 7112 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
tushki7 0:60d829a0353a 7113 #define SIM_COPC_COPSTPEN_MASK 0x10u
tushki7 0:60d829a0353a 7114 #define SIM_COPC_COPSTPEN_SHIFT 4
tushki7 0:60d829a0353a 7115 #define SIM_COPC_COPDBGEN_MASK 0x20u
tushki7 0:60d829a0353a 7116 #define SIM_COPC_COPDBGEN_SHIFT 5
tushki7 0:60d829a0353a 7117 #define SIM_COPC_COPCLKSEL_MASK 0xC0u
tushki7 0:60d829a0353a 7118 #define SIM_COPC_COPCLKSEL_SHIFT 6
tushki7 0:60d829a0353a 7119 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKSEL_SHIFT))&SIM_COPC_COPCLKSEL_MASK)
tushki7 0:60d829a0353a 7120 /* SRVCOP Bit Fields */
tushki7 0:60d829a0353a 7121 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
tushki7 0:60d829a0353a 7122 #define SIM_SRVCOP_SRVCOP_SHIFT 0
tushki7 0:60d829a0353a 7123 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
tushki7 0:60d829a0353a 7124
tushki7 0:60d829a0353a 7125 /*!
tushki7 0:60d829a0353a 7126 * @}
tushki7 0:60d829a0353a 7127 */ /* end of group SIM_Register_Masks */
tushki7 0:60d829a0353a 7128
tushki7 0:60d829a0353a 7129
tushki7 0:60d829a0353a 7130 /* SIM - Peripheral instance base addresses */
tushki7 0:60d829a0353a 7131 /** Peripheral SIM base address */
tushki7 0:60d829a0353a 7132 #define SIM_BASE (0x40047000u)
tushki7 0:60d829a0353a 7133 /** Peripheral SIM base pointer */
tushki7 0:60d829a0353a 7134 #define SIM ((SIM_Type *)SIM_BASE)
tushki7 0:60d829a0353a 7135 #define SIM_BASE_PTR (SIM)
tushki7 0:60d829a0353a 7136 /** Array initializer of SIM peripheral base addresses */
tushki7 0:60d829a0353a 7137 #define SIM_BASE_ADDRS { SIM_BASE }
tushki7 0:60d829a0353a 7138 /** Array initializer of SIM peripheral base pointers */
tushki7 0:60d829a0353a 7139 #define SIM_BASE_PTRS { SIM }
tushki7 0:60d829a0353a 7140
tushki7 0:60d829a0353a 7141 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7142 -- SIM - Register accessor macros
tushki7 0:60d829a0353a 7143 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7144
tushki7 0:60d829a0353a 7145 /*!
tushki7 0:60d829a0353a 7146 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
tushki7 0:60d829a0353a 7147 * @{
tushki7 0:60d829a0353a 7148 */
tushki7 0:60d829a0353a 7149
tushki7 0:60d829a0353a 7150
tushki7 0:60d829a0353a 7151 /* SIM - Register instance definitions */
tushki7 0:60d829a0353a 7152 /* SIM */
tushki7 0:60d829a0353a 7153 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
tushki7 0:60d829a0353a 7154 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
tushki7 0:60d829a0353a 7155 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
tushki7 0:60d829a0353a 7156 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
tushki7 0:60d829a0353a 7157 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
tushki7 0:60d829a0353a 7158 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
tushki7 0:60d829a0353a 7159 #define SIM_SDID SIM_SDID_REG(SIM)
tushki7 0:60d829a0353a 7160 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
tushki7 0:60d829a0353a 7161 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
tushki7 0:60d829a0353a 7162 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
tushki7 0:60d829a0353a 7163 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
tushki7 0:60d829a0353a 7164 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
tushki7 0:60d829a0353a 7165 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
tushki7 0:60d829a0353a 7166 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
tushki7 0:60d829a0353a 7167 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
tushki7 0:60d829a0353a 7168 #define SIM_UIDML SIM_UIDML_REG(SIM)
tushki7 0:60d829a0353a 7169 #define SIM_UIDL SIM_UIDL_REG(SIM)
tushki7 0:60d829a0353a 7170 #define SIM_COPC SIM_COPC_REG(SIM)
tushki7 0:60d829a0353a 7171 #define SIM_SRVCOP SIM_SRVCOP_REG(SIM)
tushki7 0:60d829a0353a 7172
tushki7 0:60d829a0353a 7173 /*!
tushki7 0:60d829a0353a 7174 * @}
tushki7 0:60d829a0353a 7175 */ /* end of group SIM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 7176
tushki7 0:60d829a0353a 7177
tushki7 0:60d829a0353a 7178 /*!
tushki7 0:60d829a0353a 7179 * @}
tushki7 0:60d829a0353a 7180 */ /* end of group SIM_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 7181
tushki7 0:60d829a0353a 7182
tushki7 0:60d829a0353a 7183 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7184 -- SMC Peripheral Access Layer
tushki7 0:60d829a0353a 7185 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7186
tushki7 0:60d829a0353a 7187 /*!
tushki7 0:60d829a0353a 7188 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
tushki7 0:60d829a0353a 7189 * @{
tushki7 0:60d829a0353a 7190 */
tushki7 0:60d829a0353a 7191
tushki7 0:60d829a0353a 7192 /** SMC - Register Layout Typedef */
tushki7 0:60d829a0353a 7193 typedef struct {
tushki7 0:60d829a0353a 7194 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
tushki7 0:60d829a0353a 7195 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
tushki7 0:60d829a0353a 7196 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
tushki7 0:60d829a0353a 7197 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
tushki7 0:60d829a0353a 7198 } SMC_Type, *SMC_MemMapPtr;
tushki7 0:60d829a0353a 7199
tushki7 0:60d829a0353a 7200 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7201 -- SMC - Register accessor macros
tushki7 0:60d829a0353a 7202 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7203
tushki7 0:60d829a0353a 7204 /*!
tushki7 0:60d829a0353a 7205 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
tushki7 0:60d829a0353a 7206 * @{
tushki7 0:60d829a0353a 7207 */
tushki7 0:60d829a0353a 7208
tushki7 0:60d829a0353a 7209
tushki7 0:60d829a0353a 7210 /* SMC - Register accessors */
tushki7 0:60d829a0353a 7211 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
tushki7 0:60d829a0353a 7212 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
tushki7 0:60d829a0353a 7213 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
tushki7 0:60d829a0353a 7214 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
tushki7 0:60d829a0353a 7215
tushki7 0:60d829a0353a 7216 /*!
tushki7 0:60d829a0353a 7217 * @}
tushki7 0:60d829a0353a 7218 */ /* end of group SMC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 7219
tushki7 0:60d829a0353a 7220
tushki7 0:60d829a0353a 7221 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7222 -- SMC Register Masks
tushki7 0:60d829a0353a 7223 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7224
tushki7 0:60d829a0353a 7225 /*!
tushki7 0:60d829a0353a 7226 * @addtogroup SMC_Register_Masks SMC Register Masks
tushki7 0:60d829a0353a 7227 * @{
tushki7 0:60d829a0353a 7228 */
tushki7 0:60d829a0353a 7229
tushki7 0:60d829a0353a 7230 /* PMPROT Bit Fields */
tushki7 0:60d829a0353a 7231 #define SMC_PMPROT_AVLLS_MASK 0x2u
tushki7 0:60d829a0353a 7232 #define SMC_PMPROT_AVLLS_SHIFT 1
tushki7 0:60d829a0353a 7233 #define SMC_PMPROT_ALLS_MASK 0x8u
tushki7 0:60d829a0353a 7234 #define SMC_PMPROT_ALLS_SHIFT 3
tushki7 0:60d829a0353a 7235 #define SMC_PMPROT_AVLP_MASK 0x20u
tushki7 0:60d829a0353a 7236 #define SMC_PMPROT_AVLP_SHIFT 5
tushki7 0:60d829a0353a 7237 /* PMCTRL Bit Fields */
tushki7 0:60d829a0353a 7238 #define SMC_PMCTRL_STOPM_MASK 0x7u
tushki7 0:60d829a0353a 7239 #define SMC_PMCTRL_STOPM_SHIFT 0
tushki7 0:60d829a0353a 7240 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
tushki7 0:60d829a0353a 7241 #define SMC_PMCTRL_STOPA_MASK 0x8u
tushki7 0:60d829a0353a 7242 #define SMC_PMCTRL_STOPA_SHIFT 3
tushki7 0:60d829a0353a 7243 #define SMC_PMCTRL_RUNM_MASK 0x60u
tushki7 0:60d829a0353a 7244 #define SMC_PMCTRL_RUNM_SHIFT 5
tushki7 0:60d829a0353a 7245 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
tushki7 0:60d829a0353a 7246 /* STOPCTRL Bit Fields */
tushki7 0:60d829a0353a 7247 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
tushki7 0:60d829a0353a 7248 #define SMC_STOPCTRL_VLLSM_SHIFT 0
tushki7 0:60d829a0353a 7249 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
tushki7 0:60d829a0353a 7250 #define SMC_STOPCTRL_PORPO_MASK 0x20u
tushki7 0:60d829a0353a 7251 #define SMC_STOPCTRL_PORPO_SHIFT 5
tushki7 0:60d829a0353a 7252 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
tushki7 0:60d829a0353a 7253 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
tushki7 0:60d829a0353a 7254 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
tushki7 0:60d829a0353a 7255 /* PMSTAT Bit Fields */
tushki7 0:60d829a0353a 7256 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
tushki7 0:60d829a0353a 7257 #define SMC_PMSTAT_PMSTAT_SHIFT 0
tushki7 0:60d829a0353a 7258 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
tushki7 0:60d829a0353a 7259
tushki7 0:60d829a0353a 7260 /*!
tushki7 0:60d829a0353a 7261 * @}
tushki7 0:60d829a0353a 7262 */ /* end of group SMC_Register_Masks */
tushki7 0:60d829a0353a 7263
tushki7 0:60d829a0353a 7264
tushki7 0:60d829a0353a 7265 /* SMC - Peripheral instance base addresses */
tushki7 0:60d829a0353a 7266 /** Peripheral SMC base address */
tushki7 0:60d829a0353a 7267 #define SMC_BASE (0x4007E000u)
tushki7 0:60d829a0353a 7268 /** Peripheral SMC base pointer */
tushki7 0:60d829a0353a 7269 #define SMC ((SMC_Type *)SMC_BASE)
tushki7 0:60d829a0353a 7270 #define SMC_BASE_PTR (SMC)
tushki7 0:60d829a0353a 7271 /** Array initializer of SMC peripheral base addresses */
tushki7 0:60d829a0353a 7272 #define SMC_BASE_ADDRS { SMC_BASE }
tushki7 0:60d829a0353a 7273 /** Array initializer of SMC peripheral base pointers */
tushki7 0:60d829a0353a 7274 #define SMC_BASE_PTRS { SMC }
tushki7 0:60d829a0353a 7275
tushki7 0:60d829a0353a 7276 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7277 -- SMC - Register accessor macros
tushki7 0:60d829a0353a 7278 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7279
tushki7 0:60d829a0353a 7280 /*!
tushki7 0:60d829a0353a 7281 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
tushki7 0:60d829a0353a 7282 * @{
tushki7 0:60d829a0353a 7283 */
tushki7 0:60d829a0353a 7284
tushki7 0:60d829a0353a 7285
tushki7 0:60d829a0353a 7286 /* SMC - Register instance definitions */
tushki7 0:60d829a0353a 7287 /* SMC */
tushki7 0:60d829a0353a 7288 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
tushki7 0:60d829a0353a 7289 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
tushki7 0:60d829a0353a 7290 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
tushki7 0:60d829a0353a 7291 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
tushki7 0:60d829a0353a 7292
tushki7 0:60d829a0353a 7293 /*!
tushki7 0:60d829a0353a 7294 * @}
tushki7 0:60d829a0353a 7295 */ /* end of group SMC_Register_Accessor_Macros */
tushki7 0:60d829a0353a 7296
tushki7 0:60d829a0353a 7297
tushki7 0:60d829a0353a 7298 /*!
tushki7 0:60d829a0353a 7299 * @}
tushki7 0:60d829a0353a 7300 */ /* end of group SMC_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 7301
tushki7 0:60d829a0353a 7302
tushki7 0:60d829a0353a 7303 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7304 -- SPI Peripheral Access Layer
tushki7 0:60d829a0353a 7305 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7306
tushki7 0:60d829a0353a 7307 /*!
tushki7 0:60d829a0353a 7308 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
tushki7 0:60d829a0353a 7309 * @{
tushki7 0:60d829a0353a 7310 */
tushki7 0:60d829a0353a 7311
tushki7 0:60d829a0353a 7312 /** SPI - Register Layout Typedef */
tushki7 0:60d829a0353a 7313 typedef struct {
tushki7 0:60d829a0353a 7314 __I uint8_t S; /**< SPI Status Register, offset: 0x0 */
tushki7 0:60d829a0353a 7315 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
tushki7 0:60d829a0353a 7316 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
tushki7 0:60d829a0353a 7317 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
tushki7 0:60d829a0353a 7318 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
tushki7 0:60d829a0353a 7319 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
tushki7 0:60d829a0353a 7320 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
tushki7 0:60d829a0353a 7321 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
tushki7 0:60d829a0353a 7322 uint8_t RESERVED_0[2];
tushki7 0:60d829a0353a 7323 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
tushki7 0:60d829a0353a 7324 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
tushki7 0:60d829a0353a 7325 } SPI_Type, *SPI_MemMapPtr;
tushki7 0:60d829a0353a 7326
tushki7 0:60d829a0353a 7327 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7328 -- SPI - Register accessor macros
tushki7 0:60d829a0353a 7329 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7330
tushki7 0:60d829a0353a 7331 /*!
tushki7 0:60d829a0353a 7332 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
tushki7 0:60d829a0353a 7333 * @{
tushki7 0:60d829a0353a 7334 */
tushki7 0:60d829a0353a 7335
tushki7 0:60d829a0353a 7336
tushki7 0:60d829a0353a 7337 /* SPI - Register accessors */
tushki7 0:60d829a0353a 7338 #define SPI_S_REG(base) ((base)->S)
tushki7 0:60d829a0353a 7339 #define SPI_BR_REG(base) ((base)->BR)
tushki7 0:60d829a0353a 7340 #define SPI_C2_REG(base) ((base)->C2)
tushki7 0:60d829a0353a 7341 #define SPI_C1_REG(base) ((base)->C1)
tushki7 0:60d829a0353a 7342 #define SPI_ML_REG(base) ((base)->ML)
tushki7 0:60d829a0353a 7343 #define SPI_MH_REG(base) ((base)->MH)
tushki7 0:60d829a0353a 7344 #define SPI_DL_REG(base) ((base)->DL)
tushki7 0:60d829a0353a 7345 #define SPI_DH_REG(base) ((base)->DH)
tushki7 0:60d829a0353a 7346 #define SPI_CI_REG(base) ((base)->CI)
tushki7 0:60d829a0353a 7347 #define SPI_C3_REG(base) ((base)->C3)
tushki7 0:60d829a0353a 7348
tushki7 0:60d829a0353a 7349 /*!
tushki7 0:60d829a0353a 7350 * @}
tushki7 0:60d829a0353a 7351 */ /* end of group SPI_Register_Accessor_Macros */
tushki7 0:60d829a0353a 7352
tushki7 0:60d829a0353a 7353
tushki7 0:60d829a0353a 7354 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7355 -- SPI Register Masks
tushki7 0:60d829a0353a 7356 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7357
tushki7 0:60d829a0353a 7358 /*!
tushki7 0:60d829a0353a 7359 * @addtogroup SPI_Register_Masks SPI Register Masks
tushki7 0:60d829a0353a 7360 * @{
tushki7 0:60d829a0353a 7361 */
tushki7 0:60d829a0353a 7362
tushki7 0:60d829a0353a 7363 /* S Bit Fields */
tushki7 0:60d829a0353a 7364 #define SPI_S_RFIFOEF_MASK 0x1u
tushki7 0:60d829a0353a 7365 #define SPI_S_RFIFOEF_SHIFT 0
tushki7 0:60d829a0353a 7366 #define SPI_S_TXFULLF_MASK 0x2u
tushki7 0:60d829a0353a 7367 #define SPI_S_TXFULLF_SHIFT 1
tushki7 0:60d829a0353a 7368 #define SPI_S_TNEAREF_MASK 0x4u
tushki7 0:60d829a0353a 7369 #define SPI_S_TNEAREF_SHIFT 2
tushki7 0:60d829a0353a 7370 #define SPI_S_RNFULLF_MASK 0x8u
tushki7 0:60d829a0353a 7371 #define SPI_S_RNFULLF_SHIFT 3
tushki7 0:60d829a0353a 7372 #define SPI_S_MODF_MASK 0x10u
tushki7 0:60d829a0353a 7373 #define SPI_S_MODF_SHIFT 4
tushki7 0:60d829a0353a 7374 #define SPI_S_SPTEF_MASK 0x20u
tushki7 0:60d829a0353a 7375 #define SPI_S_SPTEF_SHIFT 5
tushki7 0:60d829a0353a 7376 #define SPI_S_SPMF_MASK 0x40u
tushki7 0:60d829a0353a 7377 #define SPI_S_SPMF_SHIFT 6
tushki7 0:60d829a0353a 7378 #define SPI_S_SPRF_MASK 0x80u
tushki7 0:60d829a0353a 7379 #define SPI_S_SPRF_SHIFT 7
tushki7 0:60d829a0353a 7380 /* BR Bit Fields */
tushki7 0:60d829a0353a 7381 #define SPI_BR_SPR_MASK 0xFu
tushki7 0:60d829a0353a 7382 #define SPI_BR_SPR_SHIFT 0
tushki7 0:60d829a0353a 7383 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
tushki7 0:60d829a0353a 7384 #define SPI_BR_SPPR_MASK 0x70u
tushki7 0:60d829a0353a 7385 #define SPI_BR_SPPR_SHIFT 4
tushki7 0:60d829a0353a 7386 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
tushki7 0:60d829a0353a 7387 /* C2 Bit Fields */
tushki7 0:60d829a0353a 7388 #define SPI_C2_SPC0_MASK 0x1u
tushki7 0:60d829a0353a 7389 #define SPI_C2_SPC0_SHIFT 0
tushki7 0:60d829a0353a 7390 #define SPI_C2_SPISWAI_MASK 0x2u
tushki7 0:60d829a0353a 7391 #define SPI_C2_SPISWAI_SHIFT 1
tushki7 0:60d829a0353a 7392 #define SPI_C2_RXDMAE_MASK 0x4u
tushki7 0:60d829a0353a 7393 #define SPI_C2_RXDMAE_SHIFT 2
tushki7 0:60d829a0353a 7394 #define SPI_C2_BIDIROE_MASK 0x8u
tushki7 0:60d829a0353a 7395 #define SPI_C2_BIDIROE_SHIFT 3
tushki7 0:60d829a0353a 7396 #define SPI_C2_MODFEN_MASK 0x10u
tushki7 0:60d829a0353a 7397 #define SPI_C2_MODFEN_SHIFT 4
tushki7 0:60d829a0353a 7398 #define SPI_C2_TXDMAE_MASK 0x20u
tushki7 0:60d829a0353a 7399 #define SPI_C2_TXDMAE_SHIFT 5
tushki7 0:60d829a0353a 7400 #define SPI_C2_SPIMODE_MASK 0x40u
tushki7 0:60d829a0353a 7401 #define SPI_C2_SPIMODE_SHIFT 6
tushki7 0:60d829a0353a 7402 #define SPI_C2_SPMIE_MASK 0x80u
tushki7 0:60d829a0353a 7403 #define SPI_C2_SPMIE_SHIFT 7
tushki7 0:60d829a0353a 7404 /* C1 Bit Fields */
tushki7 0:60d829a0353a 7405 #define SPI_C1_LSBFE_MASK 0x1u
tushki7 0:60d829a0353a 7406 #define SPI_C1_LSBFE_SHIFT 0
tushki7 0:60d829a0353a 7407 #define SPI_C1_SSOE_MASK 0x2u
tushki7 0:60d829a0353a 7408 #define SPI_C1_SSOE_SHIFT 1
tushki7 0:60d829a0353a 7409 #define SPI_C1_CPHA_MASK 0x4u
tushki7 0:60d829a0353a 7410 #define SPI_C1_CPHA_SHIFT 2
tushki7 0:60d829a0353a 7411 #define SPI_C1_CPOL_MASK 0x8u
tushki7 0:60d829a0353a 7412 #define SPI_C1_CPOL_SHIFT 3
tushki7 0:60d829a0353a 7413 #define SPI_C1_MSTR_MASK 0x10u
tushki7 0:60d829a0353a 7414 #define SPI_C1_MSTR_SHIFT 4
tushki7 0:60d829a0353a 7415 #define SPI_C1_SPTIE_MASK 0x20u
tushki7 0:60d829a0353a 7416 #define SPI_C1_SPTIE_SHIFT 5
tushki7 0:60d829a0353a 7417 #define SPI_C1_SPE_MASK 0x40u
tushki7 0:60d829a0353a 7418 #define SPI_C1_SPE_SHIFT 6
tushki7 0:60d829a0353a 7419 #define SPI_C1_SPIE_MASK 0x80u
tushki7 0:60d829a0353a 7420 #define SPI_C1_SPIE_SHIFT 7
tushki7 0:60d829a0353a 7421 /* ML Bit Fields */
tushki7 0:60d829a0353a 7422 #define SPI_ML_Bits_MASK 0xFFu
tushki7 0:60d829a0353a 7423 #define SPI_ML_Bits_SHIFT 0
tushki7 0:60d829a0353a 7424 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
tushki7 0:60d829a0353a 7425 /* MH Bit Fields */
tushki7 0:60d829a0353a 7426 #define SPI_MH_Bits_MASK 0xFFu
tushki7 0:60d829a0353a 7427 #define SPI_MH_Bits_SHIFT 0
tushki7 0:60d829a0353a 7428 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
tushki7 0:60d829a0353a 7429 /* DL Bit Fields */
tushki7 0:60d829a0353a 7430 #define SPI_DL_Bits_MASK 0xFFu
tushki7 0:60d829a0353a 7431 #define SPI_DL_Bits_SHIFT 0
tushki7 0:60d829a0353a 7432 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
tushki7 0:60d829a0353a 7433 /* DH Bit Fields */
tushki7 0:60d829a0353a 7434 #define SPI_DH_Bits_MASK 0xFFu
tushki7 0:60d829a0353a 7435 #define SPI_DH_Bits_SHIFT 0
tushki7 0:60d829a0353a 7436 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
tushki7 0:60d829a0353a 7437 /* CI Bit Fields */
tushki7 0:60d829a0353a 7438 #define SPI_CI_SPRFCI_MASK 0x1u
tushki7 0:60d829a0353a 7439 #define SPI_CI_SPRFCI_SHIFT 0
tushki7 0:60d829a0353a 7440 #define SPI_CI_SPTEFCI_MASK 0x2u
tushki7 0:60d829a0353a 7441 #define SPI_CI_SPTEFCI_SHIFT 1
tushki7 0:60d829a0353a 7442 #define SPI_CI_RNFULLFCI_MASK 0x4u
tushki7 0:60d829a0353a 7443 #define SPI_CI_RNFULLFCI_SHIFT 2
tushki7 0:60d829a0353a 7444 #define SPI_CI_TNEAREFCI_MASK 0x8u
tushki7 0:60d829a0353a 7445 #define SPI_CI_TNEAREFCI_SHIFT 3
tushki7 0:60d829a0353a 7446 #define SPI_CI_RXFOF_MASK 0x10u
tushki7 0:60d829a0353a 7447 #define SPI_CI_RXFOF_SHIFT 4
tushki7 0:60d829a0353a 7448 #define SPI_CI_TXFOF_MASK 0x20u
tushki7 0:60d829a0353a 7449 #define SPI_CI_TXFOF_SHIFT 5
tushki7 0:60d829a0353a 7450 #define SPI_CI_RXFERR_MASK 0x40u
tushki7 0:60d829a0353a 7451 #define SPI_CI_RXFERR_SHIFT 6
tushki7 0:60d829a0353a 7452 #define SPI_CI_TXFERR_MASK 0x80u
tushki7 0:60d829a0353a 7453 #define SPI_CI_TXFERR_SHIFT 7
tushki7 0:60d829a0353a 7454 /* C3 Bit Fields */
tushki7 0:60d829a0353a 7455 #define SPI_C3_FIFOMODE_MASK 0x1u
tushki7 0:60d829a0353a 7456 #define SPI_C3_FIFOMODE_SHIFT 0
tushki7 0:60d829a0353a 7457 #define SPI_C3_RNFULLIEN_MASK 0x2u
tushki7 0:60d829a0353a 7458 #define SPI_C3_RNFULLIEN_SHIFT 1
tushki7 0:60d829a0353a 7459 #define SPI_C3_TNEARIEN_MASK 0x4u
tushki7 0:60d829a0353a 7460 #define SPI_C3_TNEARIEN_SHIFT 2
tushki7 0:60d829a0353a 7461 #define SPI_C3_INTCLR_MASK 0x8u
tushki7 0:60d829a0353a 7462 #define SPI_C3_INTCLR_SHIFT 3
tushki7 0:60d829a0353a 7463 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
tushki7 0:60d829a0353a 7464 #define SPI_C3_RNFULLF_MARK_SHIFT 4
tushki7 0:60d829a0353a 7465 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
tushki7 0:60d829a0353a 7466 #define SPI_C3_TNEAREF_MARK_SHIFT 5
tushki7 0:60d829a0353a 7467
tushki7 0:60d829a0353a 7468 /*!
tushki7 0:60d829a0353a 7469 * @}
tushki7 0:60d829a0353a 7470 */ /* end of group SPI_Register_Masks */
tushki7 0:60d829a0353a 7471
tushki7 0:60d829a0353a 7472
tushki7 0:60d829a0353a 7473 /* SPI - Peripheral instance base addresses */
tushki7 0:60d829a0353a 7474 /** Peripheral SPI0 base address */
tushki7 0:60d829a0353a 7475 #define SPI0_BASE (0x40076000u)
tushki7 0:60d829a0353a 7476 /** Peripheral SPI0 base pointer */
tushki7 0:60d829a0353a 7477 #define SPI0 ((SPI_Type *)SPI0_BASE)
tushki7 0:60d829a0353a 7478 #define SPI0_BASE_PTR (SPI0)
tushki7 0:60d829a0353a 7479 /** Peripheral SPI1 base address */
tushki7 0:60d829a0353a 7480 #define SPI1_BASE (0x40077000u)
tushki7 0:60d829a0353a 7481 /** Peripheral SPI1 base pointer */
tushki7 0:60d829a0353a 7482 #define SPI1 ((SPI_Type *)SPI1_BASE)
tushki7 0:60d829a0353a 7483 #define SPI1_BASE_PTR (SPI1)
tushki7 0:60d829a0353a 7484 /** Array initializer of SPI peripheral base addresses */
tushki7 0:60d829a0353a 7485 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
tushki7 0:60d829a0353a 7486 /** Array initializer of SPI peripheral base pointers */
tushki7 0:60d829a0353a 7487 #define SPI_BASE_PTRS { SPI0, SPI1 }
tushki7 0:60d829a0353a 7488 /** Interrupt vectors for the SPI peripheral type */
tushki7 0:60d829a0353a 7489 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
tushki7 0:60d829a0353a 7490
tushki7 0:60d829a0353a 7491 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7492 -- SPI - Register accessor macros
tushki7 0:60d829a0353a 7493 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7494
tushki7 0:60d829a0353a 7495 /*!
tushki7 0:60d829a0353a 7496 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
tushki7 0:60d829a0353a 7497 * @{
tushki7 0:60d829a0353a 7498 */
tushki7 0:60d829a0353a 7499
tushki7 0:60d829a0353a 7500
tushki7 0:60d829a0353a 7501 /* SPI - Register instance definitions */
tushki7 0:60d829a0353a 7502 /* SPI0 */
tushki7 0:60d829a0353a 7503 #define SPI0_S SPI_S_REG(SPI0)
tushki7 0:60d829a0353a 7504 #define SPI0_BR SPI_BR_REG(SPI0)
tushki7 0:60d829a0353a 7505 #define SPI0_C2 SPI_C2_REG(SPI0)
tushki7 0:60d829a0353a 7506 #define SPI0_C1 SPI_C1_REG(SPI0)
tushki7 0:60d829a0353a 7507 #define SPI0_ML SPI_ML_REG(SPI0)
tushki7 0:60d829a0353a 7508 #define SPI0_MH SPI_MH_REG(SPI0)
tushki7 0:60d829a0353a 7509 #define SPI0_DL SPI_DL_REG(SPI0)
tushki7 0:60d829a0353a 7510 #define SPI0_DH SPI_DH_REG(SPI0)
tushki7 0:60d829a0353a 7511 /* SPI1 */
tushki7 0:60d829a0353a 7512 #define SPI1_S SPI_S_REG(SPI1)
tushki7 0:60d829a0353a 7513 #define SPI1_BR SPI_BR_REG(SPI1)
tushki7 0:60d829a0353a 7514 #define SPI1_C2 SPI_C2_REG(SPI1)
tushki7 0:60d829a0353a 7515 #define SPI1_C1 SPI_C1_REG(SPI1)
tushki7 0:60d829a0353a 7516 #define SPI1_ML SPI_ML_REG(SPI1)
tushki7 0:60d829a0353a 7517 #define SPI1_MH SPI_MH_REG(SPI1)
tushki7 0:60d829a0353a 7518 #define SPI1_DL SPI_DL_REG(SPI1)
tushki7 0:60d829a0353a 7519 #define SPI1_DH SPI_DH_REG(SPI1)
tushki7 0:60d829a0353a 7520 #define SPI1_CI SPI_CI_REG(SPI1)
tushki7 0:60d829a0353a 7521 #define SPI1_C3 SPI_C3_REG(SPI1)
tushki7 0:60d829a0353a 7522
tushki7 0:60d829a0353a 7523 /*!
tushki7 0:60d829a0353a 7524 * @}
tushki7 0:60d829a0353a 7525 */ /* end of group SPI_Register_Accessor_Macros */
tushki7 0:60d829a0353a 7526
tushki7 0:60d829a0353a 7527
tushki7 0:60d829a0353a 7528 /*!
tushki7 0:60d829a0353a 7529 * @}
tushki7 0:60d829a0353a 7530 */ /* end of group SPI_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 7531
tushki7 0:60d829a0353a 7532
tushki7 0:60d829a0353a 7533 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7534 -- TPM Peripheral Access Layer
tushki7 0:60d829a0353a 7535 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7536
tushki7 0:60d829a0353a 7537 /*!
tushki7 0:60d829a0353a 7538 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
tushki7 0:60d829a0353a 7539 * @{
tushki7 0:60d829a0353a 7540 */
tushki7 0:60d829a0353a 7541
tushki7 0:60d829a0353a 7542 /** TPM - Register Layout Typedef */
tushki7 0:60d829a0353a 7543 typedef struct {
tushki7 0:60d829a0353a 7544 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
tushki7 0:60d829a0353a 7545 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
tushki7 0:60d829a0353a 7546 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
tushki7 0:60d829a0353a 7547 struct { /* offset: 0xC, array step: 0x8 */
tushki7 0:60d829a0353a 7548 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
tushki7 0:60d829a0353a 7549 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
tushki7 0:60d829a0353a 7550 } CONTROLS[6];
tushki7 0:60d829a0353a 7551 uint8_t RESERVED_0[20];
tushki7 0:60d829a0353a 7552 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
tushki7 0:60d829a0353a 7553 uint8_t RESERVED_1[28];
tushki7 0:60d829a0353a 7554 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
tushki7 0:60d829a0353a 7555 uint8_t RESERVED_2[16];
tushki7 0:60d829a0353a 7556 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
tushki7 0:60d829a0353a 7557 } TPM_Type, *TPM_MemMapPtr;
tushki7 0:60d829a0353a 7558
tushki7 0:60d829a0353a 7559 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7560 -- TPM - Register accessor macros
tushki7 0:60d829a0353a 7561 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7562
tushki7 0:60d829a0353a 7563 /*!
tushki7 0:60d829a0353a 7564 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
tushki7 0:60d829a0353a 7565 * @{
tushki7 0:60d829a0353a 7566 */
tushki7 0:60d829a0353a 7567
tushki7 0:60d829a0353a 7568
tushki7 0:60d829a0353a 7569 /* TPM - Register accessors */
tushki7 0:60d829a0353a 7570 #define TPM_SC_REG(base) ((base)->SC)
tushki7 0:60d829a0353a 7571 #define TPM_CNT_REG(base) ((base)->CNT)
tushki7 0:60d829a0353a 7572 #define TPM_MOD_REG(base) ((base)->MOD)
tushki7 0:60d829a0353a 7573 #define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
tushki7 0:60d829a0353a 7574 #define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
tushki7 0:60d829a0353a 7575 #define TPM_STATUS_REG(base) ((base)->STATUS)
tushki7 0:60d829a0353a 7576 #define TPM_POL_REG(base) ((base)->POL)
tushki7 0:60d829a0353a 7577 #define TPM_CONF_REG(base) ((base)->CONF)
tushki7 0:60d829a0353a 7578
tushki7 0:60d829a0353a 7579 /*!
tushki7 0:60d829a0353a 7580 * @}
tushki7 0:60d829a0353a 7581 */ /* end of group TPM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 7582
tushki7 0:60d829a0353a 7583
tushki7 0:60d829a0353a 7584 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7585 -- TPM Register Masks
tushki7 0:60d829a0353a 7586 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7587
tushki7 0:60d829a0353a 7588 /*!
tushki7 0:60d829a0353a 7589 * @addtogroup TPM_Register_Masks TPM Register Masks
tushki7 0:60d829a0353a 7590 * @{
tushki7 0:60d829a0353a 7591 */
tushki7 0:60d829a0353a 7592
tushki7 0:60d829a0353a 7593 /* SC Bit Fields */
tushki7 0:60d829a0353a 7594 #define TPM_SC_PS_MASK 0x7u
tushki7 0:60d829a0353a 7595 #define TPM_SC_PS_SHIFT 0
tushki7 0:60d829a0353a 7596 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
tushki7 0:60d829a0353a 7597 #define TPM_SC_CMOD_MASK 0x18u
tushki7 0:60d829a0353a 7598 #define TPM_SC_CMOD_SHIFT 3
tushki7 0:60d829a0353a 7599 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
tushki7 0:60d829a0353a 7600 #define TPM_SC_CPWMS_MASK 0x20u
tushki7 0:60d829a0353a 7601 #define TPM_SC_CPWMS_SHIFT 5
tushki7 0:60d829a0353a 7602 #define TPM_SC_TOIE_MASK 0x40u
tushki7 0:60d829a0353a 7603 #define TPM_SC_TOIE_SHIFT 6
tushki7 0:60d829a0353a 7604 #define TPM_SC_TOF_MASK 0x80u
tushki7 0:60d829a0353a 7605 #define TPM_SC_TOF_SHIFT 7
tushki7 0:60d829a0353a 7606 #define TPM_SC_DMA_MASK 0x100u
tushki7 0:60d829a0353a 7607 #define TPM_SC_DMA_SHIFT 8
tushki7 0:60d829a0353a 7608 /* CNT Bit Fields */
tushki7 0:60d829a0353a 7609 #define TPM_CNT_COUNT_MASK 0xFFFFu
tushki7 0:60d829a0353a 7610 #define TPM_CNT_COUNT_SHIFT 0
tushki7 0:60d829a0353a 7611 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
tushki7 0:60d829a0353a 7612 /* MOD Bit Fields */
tushki7 0:60d829a0353a 7613 #define TPM_MOD_MOD_MASK 0xFFFFu
tushki7 0:60d829a0353a 7614 #define TPM_MOD_MOD_SHIFT 0
tushki7 0:60d829a0353a 7615 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
tushki7 0:60d829a0353a 7616 /* CnSC Bit Fields */
tushki7 0:60d829a0353a 7617 #define TPM_CnSC_DMA_MASK 0x1u
tushki7 0:60d829a0353a 7618 #define TPM_CnSC_DMA_SHIFT 0
tushki7 0:60d829a0353a 7619 #define TPM_CnSC_ELSA_MASK 0x4u
tushki7 0:60d829a0353a 7620 #define TPM_CnSC_ELSA_SHIFT 2
tushki7 0:60d829a0353a 7621 #define TPM_CnSC_ELSB_MASK 0x8u
tushki7 0:60d829a0353a 7622 #define TPM_CnSC_ELSB_SHIFT 3
tushki7 0:60d829a0353a 7623 #define TPM_CnSC_MSA_MASK 0x10u
tushki7 0:60d829a0353a 7624 #define TPM_CnSC_MSA_SHIFT 4
tushki7 0:60d829a0353a 7625 #define TPM_CnSC_MSB_MASK 0x20u
tushki7 0:60d829a0353a 7626 #define TPM_CnSC_MSB_SHIFT 5
tushki7 0:60d829a0353a 7627 #define TPM_CnSC_CHIE_MASK 0x40u
tushki7 0:60d829a0353a 7628 #define TPM_CnSC_CHIE_SHIFT 6
tushki7 0:60d829a0353a 7629 #define TPM_CnSC_CHF_MASK 0x80u
tushki7 0:60d829a0353a 7630 #define TPM_CnSC_CHF_SHIFT 7
tushki7 0:60d829a0353a 7631 /* CnV Bit Fields */
tushki7 0:60d829a0353a 7632 #define TPM_CnV_VAL_MASK 0xFFFFu
tushki7 0:60d829a0353a 7633 #define TPM_CnV_VAL_SHIFT 0
tushki7 0:60d829a0353a 7634 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
tushki7 0:60d829a0353a 7635 /* STATUS Bit Fields */
tushki7 0:60d829a0353a 7636 #define TPM_STATUS_CH0F_MASK 0x1u
tushki7 0:60d829a0353a 7637 #define TPM_STATUS_CH0F_SHIFT 0
tushki7 0:60d829a0353a 7638 #define TPM_STATUS_CH1F_MASK 0x2u
tushki7 0:60d829a0353a 7639 #define TPM_STATUS_CH1F_SHIFT 1
tushki7 0:60d829a0353a 7640 #define TPM_STATUS_CH2F_MASK 0x4u
tushki7 0:60d829a0353a 7641 #define TPM_STATUS_CH2F_SHIFT 2
tushki7 0:60d829a0353a 7642 #define TPM_STATUS_CH3F_MASK 0x8u
tushki7 0:60d829a0353a 7643 #define TPM_STATUS_CH3F_SHIFT 3
tushki7 0:60d829a0353a 7644 #define TPM_STATUS_CH4F_MASK 0x10u
tushki7 0:60d829a0353a 7645 #define TPM_STATUS_CH4F_SHIFT 4
tushki7 0:60d829a0353a 7646 #define TPM_STATUS_CH5F_MASK 0x20u
tushki7 0:60d829a0353a 7647 #define TPM_STATUS_CH5F_SHIFT 5
tushki7 0:60d829a0353a 7648 #define TPM_STATUS_TOF_MASK 0x100u
tushki7 0:60d829a0353a 7649 #define TPM_STATUS_TOF_SHIFT 8
tushki7 0:60d829a0353a 7650 /* POL Bit Fields */
tushki7 0:60d829a0353a 7651 #define TPM_POL_POL0_MASK 0x1u
tushki7 0:60d829a0353a 7652 #define TPM_POL_POL0_SHIFT 0
tushki7 0:60d829a0353a 7653 #define TPM_POL_POL1_MASK 0x2u
tushki7 0:60d829a0353a 7654 #define TPM_POL_POL1_SHIFT 1
tushki7 0:60d829a0353a 7655 #define TPM_POL_POL2_MASK 0x4u
tushki7 0:60d829a0353a 7656 #define TPM_POL_POL2_SHIFT 2
tushki7 0:60d829a0353a 7657 #define TPM_POL_POL3_MASK 0x8u
tushki7 0:60d829a0353a 7658 #define TPM_POL_POL3_SHIFT 3
tushki7 0:60d829a0353a 7659 #define TPM_POL_POL4_MASK 0x10u
tushki7 0:60d829a0353a 7660 #define TPM_POL_POL4_SHIFT 4
tushki7 0:60d829a0353a 7661 #define TPM_POL_POL5_MASK 0x20u
tushki7 0:60d829a0353a 7662 #define TPM_POL_POL5_SHIFT 5
tushki7 0:60d829a0353a 7663 /* CONF Bit Fields */
tushki7 0:60d829a0353a 7664 #define TPM_CONF_DOZEEN_MASK 0x20u
tushki7 0:60d829a0353a 7665 #define TPM_CONF_DOZEEN_SHIFT 5
tushki7 0:60d829a0353a 7666 #define TPM_CONF_DBGMODE_MASK 0xC0u
tushki7 0:60d829a0353a 7667 #define TPM_CONF_DBGMODE_SHIFT 6
tushki7 0:60d829a0353a 7668 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
tushki7 0:60d829a0353a 7669 #define TPM_CONF_GTBSYNC_MASK 0x100u
tushki7 0:60d829a0353a 7670 #define TPM_CONF_GTBSYNC_SHIFT 8
tushki7 0:60d829a0353a 7671 #define TPM_CONF_GTBEEN_MASK 0x200u
tushki7 0:60d829a0353a 7672 #define TPM_CONF_GTBEEN_SHIFT 9
tushki7 0:60d829a0353a 7673 #define TPM_CONF_CSOT_MASK 0x10000u
tushki7 0:60d829a0353a 7674 #define TPM_CONF_CSOT_SHIFT 16
tushki7 0:60d829a0353a 7675 #define TPM_CONF_CSOO_MASK 0x20000u
tushki7 0:60d829a0353a 7676 #define TPM_CONF_CSOO_SHIFT 17
tushki7 0:60d829a0353a 7677 #define TPM_CONF_CROT_MASK 0x40000u
tushki7 0:60d829a0353a 7678 #define TPM_CONF_CROT_SHIFT 18
tushki7 0:60d829a0353a 7679 #define TPM_CONF_CPOT_MASK 0x80000u
tushki7 0:60d829a0353a 7680 #define TPM_CONF_CPOT_SHIFT 19
tushki7 0:60d829a0353a 7681 #define TPM_CONF_TRGPOL_MASK 0x400000u
tushki7 0:60d829a0353a 7682 #define TPM_CONF_TRGPOL_SHIFT 22
tushki7 0:60d829a0353a 7683 #define TPM_CONF_TRGSRC_MASK 0x800000u
tushki7 0:60d829a0353a 7684 #define TPM_CONF_TRGSRC_SHIFT 23
tushki7 0:60d829a0353a 7685 #define TPM_CONF_TRGSEL_MASK 0xF000000u
tushki7 0:60d829a0353a 7686 #define TPM_CONF_TRGSEL_SHIFT 24
tushki7 0:60d829a0353a 7687 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
tushki7 0:60d829a0353a 7688
tushki7 0:60d829a0353a 7689 /*!
tushki7 0:60d829a0353a 7690 * @}
tushki7 0:60d829a0353a 7691 */ /* end of group TPM_Register_Masks */
tushki7 0:60d829a0353a 7692
tushki7 0:60d829a0353a 7693
tushki7 0:60d829a0353a 7694 /* TPM - Peripheral instance base addresses */
tushki7 0:60d829a0353a 7695 /** Peripheral TPM0 base address */
tushki7 0:60d829a0353a 7696 #define TPM0_BASE (0x40038000u)
tushki7 0:60d829a0353a 7697 /** Peripheral TPM0 base pointer */
tushki7 0:60d829a0353a 7698 #define TPM0 ((TPM_Type *)TPM0_BASE)
tushki7 0:60d829a0353a 7699 #define TPM0_BASE_PTR (TPM0)
tushki7 0:60d829a0353a 7700 /** Peripheral TPM1 base address */
tushki7 0:60d829a0353a 7701 #define TPM1_BASE (0x40039000u)
tushki7 0:60d829a0353a 7702 /** Peripheral TPM1 base pointer */
tushki7 0:60d829a0353a 7703 #define TPM1 ((TPM_Type *)TPM1_BASE)
tushki7 0:60d829a0353a 7704 #define TPM1_BASE_PTR (TPM1)
tushki7 0:60d829a0353a 7705 /** Peripheral TPM2 base address */
tushki7 0:60d829a0353a 7706 #define TPM2_BASE (0x4003A000u)
tushki7 0:60d829a0353a 7707 /** Peripheral TPM2 base pointer */
tushki7 0:60d829a0353a 7708 #define TPM2 ((TPM_Type *)TPM2_BASE)
tushki7 0:60d829a0353a 7709 #define TPM2_BASE_PTR (TPM2)
tushki7 0:60d829a0353a 7710 /** Array initializer of TPM peripheral base addresses */
tushki7 0:60d829a0353a 7711 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
tushki7 0:60d829a0353a 7712 /** Array initializer of TPM peripheral base pointers */
tushki7 0:60d829a0353a 7713 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
tushki7 0:60d829a0353a 7714 /** Interrupt vectors for the TPM peripheral type */
tushki7 0:60d829a0353a 7715 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
tushki7 0:60d829a0353a 7716
tushki7 0:60d829a0353a 7717 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7718 -- TPM - Register accessor macros
tushki7 0:60d829a0353a 7719 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7720
tushki7 0:60d829a0353a 7721 /*!
tushki7 0:60d829a0353a 7722 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
tushki7 0:60d829a0353a 7723 * @{
tushki7 0:60d829a0353a 7724 */
tushki7 0:60d829a0353a 7725
tushki7 0:60d829a0353a 7726
tushki7 0:60d829a0353a 7727 /* TPM - Register instance definitions */
tushki7 0:60d829a0353a 7728 /* TPM0 */
tushki7 0:60d829a0353a 7729 #define TPM0_SC TPM_SC_REG(TPM0)
tushki7 0:60d829a0353a 7730 #define TPM0_CNT TPM_CNT_REG(TPM0)
tushki7 0:60d829a0353a 7731 #define TPM0_MOD TPM_MOD_REG(TPM0)
tushki7 0:60d829a0353a 7732 #define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
tushki7 0:60d829a0353a 7733 #define TPM0_C0V TPM_CnV_REG(TPM0,0)
tushki7 0:60d829a0353a 7734 #define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
tushki7 0:60d829a0353a 7735 #define TPM0_C1V TPM_CnV_REG(TPM0,1)
tushki7 0:60d829a0353a 7736 #define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
tushki7 0:60d829a0353a 7737 #define TPM0_C2V TPM_CnV_REG(TPM0,2)
tushki7 0:60d829a0353a 7738 #define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
tushki7 0:60d829a0353a 7739 #define TPM0_C3V TPM_CnV_REG(TPM0,3)
tushki7 0:60d829a0353a 7740 #define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
tushki7 0:60d829a0353a 7741 #define TPM0_C4V TPM_CnV_REG(TPM0,4)
tushki7 0:60d829a0353a 7742 #define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
tushki7 0:60d829a0353a 7743 #define TPM0_C5V TPM_CnV_REG(TPM0,5)
tushki7 0:60d829a0353a 7744 #define TPM0_STATUS TPM_STATUS_REG(TPM0)
tushki7 0:60d829a0353a 7745 #define TPM0_POL TPM_POL_REG(TPM0)
tushki7 0:60d829a0353a 7746 #define TPM0_CONF TPM_CONF_REG(TPM0)
tushki7 0:60d829a0353a 7747 /* TPM1 */
tushki7 0:60d829a0353a 7748 #define TPM1_SC TPM_SC_REG(TPM1)
tushki7 0:60d829a0353a 7749 #define TPM1_CNT TPM_CNT_REG(TPM1)
tushki7 0:60d829a0353a 7750 #define TPM1_MOD TPM_MOD_REG(TPM1)
tushki7 0:60d829a0353a 7751 #define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
tushki7 0:60d829a0353a 7752 #define TPM1_C0V TPM_CnV_REG(TPM1,0)
tushki7 0:60d829a0353a 7753 #define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
tushki7 0:60d829a0353a 7754 #define TPM1_C1V TPM_CnV_REG(TPM1,1)
tushki7 0:60d829a0353a 7755 #define TPM1_STATUS TPM_STATUS_REG(TPM1)
tushki7 0:60d829a0353a 7756 #define TPM1_POL TPM_POL_REG(TPM1)
tushki7 0:60d829a0353a 7757 #define TPM1_CONF TPM_CONF_REG(TPM1)
tushki7 0:60d829a0353a 7758 /* TPM2 */
tushki7 0:60d829a0353a 7759 #define TPM2_SC TPM_SC_REG(TPM2)
tushki7 0:60d829a0353a 7760 #define TPM2_CNT TPM_CNT_REG(TPM2)
tushki7 0:60d829a0353a 7761 #define TPM2_MOD TPM_MOD_REG(TPM2)
tushki7 0:60d829a0353a 7762 #define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
tushki7 0:60d829a0353a 7763 #define TPM2_C0V TPM_CnV_REG(TPM2,0)
tushki7 0:60d829a0353a 7764 #define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
tushki7 0:60d829a0353a 7765 #define TPM2_C1V TPM_CnV_REG(TPM2,1)
tushki7 0:60d829a0353a 7766 #define TPM2_STATUS TPM_STATUS_REG(TPM2)
tushki7 0:60d829a0353a 7767 #define TPM2_POL TPM_POL_REG(TPM2)
tushki7 0:60d829a0353a 7768 #define TPM2_CONF TPM_CONF_REG(TPM2)
tushki7 0:60d829a0353a 7769
tushki7 0:60d829a0353a 7770 /* TPM - Register array accessors */
tushki7 0:60d829a0353a 7771 #define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
tushki7 0:60d829a0353a 7772 #define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
tushki7 0:60d829a0353a 7773 #define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
tushki7 0:60d829a0353a 7774 #define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
tushki7 0:60d829a0353a 7775 #define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
tushki7 0:60d829a0353a 7776 #define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
tushki7 0:60d829a0353a 7777
tushki7 0:60d829a0353a 7778 /*!
tushki7 0:60d829a0353a 7779 * @}
tushki7 0:60d829a0353a 7780 */ /* end of group TPM_Register_Accessor_Macros */
tushki7 0:60d829a0353a 7781
tushki7 0:60d829a0353a 7782
tushki7 0:60d829a0353a 7783 /*!
tushki7 0:60d829a0353a 7784 * @}
tushki7 0:60d829a0353a 7785 */ /* end of group TPM_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 7786
tushki7 0:60d829a0353a 7787
tushki7 0:60d829a0353a 7788 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7789 -- UART Peripheral Access Layer
tushki7 0:60d829a0353a 7790 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7791
tushki7 0:60d829a0353a 7792 /*!
tushki7 0:60d829a0353a 7793 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
tushki7 0:60d829a0353a 7794 * @{
tushki7 0:60d829a0353a 7795 */
tushki7 0:60d829a0353a 7796
tushki7 0:60d829a0353a 7797 /** UART - Register Layout Typedef */
tushki7 0:60d829a0353a 7798 typedef struct {
tushki7 0:60d829a0353a 7799 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
tushki7 0:60d829a0353a 7800 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
tushki7 0:60d829a0353a 7801 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
tushki7 0:60d829a0353a 7802 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
tushki7 0:60d829a0353a 7803 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
tushki7 0:60d829a0353a 7804 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
tushki7 0:60d829a0353a 7805 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
tushki7 0:60d829a0353a 7806 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
tushki7 0:60d829a0353a 7807 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
tushki7 0:60d829a0353a 7808 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
tushki7 0:60d829a0353a 7809 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
tushki7 0:60d829a0353a 7810 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
tushki7 0:60d829a0353a 7811 uint8_t RESERVED_0[12];
tushki7 0:60d829a0353a 7812 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
tushki7 0:60d829a0353a 7813 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
tushki7 0:60d829a0353a 7814 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
tushki7 0:60d829a0353a 7815 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
tushki7 0:60d829a0353a 7816 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
tushki7 0:60d829a0353a 7817 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
tushki7 0:60d829a0353a 7818 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
tushki7 0:60d829a0353a 7819 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
tushki7 0:60d829a0353a 7820 uint8_t RESERVED_1[26];
tushki7 0:60d829a0353a 7821 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
tushki7 0:60d829a0353a 7822 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
tushki7 0:60d829a0353a 7823 union { /* offset: 0x3C */
tushki7 0:60d829a0353a 7824 struct { /* offset: 0x3C */
tushki7 0:60d829a0353a 7825 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
tushki7 0:60d829a0353a 7826 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
tushki7 0:60d829a0353a 7827 } TYPE0;
tushki7 0:60d829a0353a 7828 struct { /* offset: 0x3C */
tushki7 0:60d829a0353a 7829 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
tushki7 0:60d829a0353a 7830 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
tushki7 0:60d829a0353a 7831 } TYPE1;
tushki7 0:60d829a0353a 7832 };
tushki7 0:60d829a0353a 7833 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
tushki7 0:60d829a0353a 7834 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
tushki7 0:60d829a0353a 7835 } UART_Type, *UART_MemMapPtr;
tushki7 0:60d829a0353a 7836
tushki7 0:60d829a0353a 7837 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7838 -- UART - Register accessor macros
tushki7 0:60d829a0353a 7839 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7840
tushki7 0:60d829a0353a 7841 /*!
tushki7 0:60d829a0353a 7842 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
tushki7 0:60d829a0353a 7843 * @{
tushki7 0:60d829a0353a 7844 */
tushki7 0:60d829a0353a 7845
tushki7 0:60d829a0353a 7846
tushki7 0:60d829a0353a 7847 /* UART - Register accessors */
tushki7 0:60d829a0353a 7848 #define UART_BDH_REG(base) ((base)->BDH)
tushki7 0:60d829a0353a 7849 #define UART_BDL_REG(base) ((base)->BDL)
tushki7 0:60d829a0353a 7850 #define UART_C1_REG(base) ((base)->C1)
tushki7 0:60d829a0353a 7851 #define UART_C2_REG(base) ((base)->C2)
tushki7 0:60d829a0353a 7852 #define UART_S1_REG(base) ((base)->S1)
tushki7 0:60d829a0353a 7853 #define UART_S2_REG(base) ((base)->S2)
tushki7 0:60d829a0353a 7854 #define UART_C3_REG(base) ((base)->C3)
tushki7 0:60d829a0353a 7855 #define UART_D_REG(base) ((base)->D)
tushki7 0:60d829a0353a 7856 #define UART_MA1_REG(base) ((base)->MA1)
tushki7 0:60d829a0353a 7857 #define UART_MA2_REG(base) ((base)->MA2)
tushki7 0:60d829a0353a 7858 #define UART_C4_REG(base) ((base)->C4)
tushki7 0:60d829a0353a 7859 #define UART_C5_REG(base) ((base)->C5)
tushki7 0:60d829a0353a 7860 #define UART_C7816_REG(base) ((base)->C7816)
tushki7 0:60d829a0353a 7861 #define UART_IE7816_REG(base) ((base)->IE7816)
tushki7 0:60d829a0353a 7862 #define UART_IS7816_REG(base) ((base)->IS7816)
tushki7 0:60d829a0353a 7863 #define UART_WP7816_REG(base) ((base)->WP7816)
tushki7 0:60d829a0353a 7864 #define UART_WN7816_REG(base) ((base)->WN7816)
tushki7 0:60d829a0353a 7865 #define UART_WF7816_REG(base) ((base)->WF7816)
tushki7 0:60d829a0353a 7866 #define UART_ET7816_REG(base) ((base)->ET7816)
tushki7 0:60d829a0353a 7867 #define UART_TL7816_REG(base) ((base)->TL7816)
tushki7 0:60d829a0353a 7868 #define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
tushki7 0:60d829a0353a 7869 #define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
tushki7 0:60d829a0353a 7870 #define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
tushki7 0:60d829a0353a 7871 #define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
tushki7 0:60d829a0353a 7872 #define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
tushki7 0:60d829a0353a 7873 #define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
tushki7 0:60d829a0353a 7874 #define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
tushki7 0:60d829a0353a 7875 #define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
tushki7 0:60d829a0353a 7876
tushki7 0:60d829a0353a 7877 /*!
tushki7 0:60d829a0353a 7878 * @}
tushki7 0:60d829a0353a 7879 */ /* end of group UART_Register_Accessor_Macros */
tushki7 0:60d829a0353a 7880
tushki7 0:60d829a0353a 7881
tushki7 0:60d829a0353a 7882 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 7883 -- UART Register Masks
tushki7 0:60d829a0353a 7884 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 7885
tushki7 0:60d829a0353a 7886 /*!
tushki7 0:60d829a0353a 7887 * @addtogroup UART_Register_Masks UART Register Masks
tushki7 0:60d829a0353a 7888 * @{
tushki7 0:60d829a0353a 7889 */
tushki7 0:60d829a0353a 7890
tushki7 0:60d829a0353a 7891 /* BDH Bit Fields */
tushki7 0:60d829a0353a 7892 #define UART_BDH_SBR_MASK 0x1Fu
tushki7 0:60d829a0353a 7893 #define UART_BDH_SBR_SHIFT 0
tushki7 0:60d829a0353a 7894 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
tushki7 0:60d829a0353a 7895 #define UART_BDH_RXEDGIE_MASK 0x40u
tushki7 0:60d829a0353a 7896 #define UART_BDH_RXEDGIE_SHIFT 6
tushki7 0:60d829a0353a 7897 /* BDL Bit Fields */
tushki7 0:60d829a0353a 7898 #define UART_BDL_SBR_MASK 0xFFu
tushki7 0:60d829a0353a 7899 #define UART_BDL_SBR_SHIFT 0
tushki7 0:60d829a0353a 7900 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
tushki7 0:60d829a0353a 7901 /* C1 Bit Fields */
tushki7 0:60d829a0353a 7902 #define UART_C1_PT_MASK 0x1u
tushki7 0:60d829a0353a 7903 #define UART_C1_PT_SHIFT 0
tushki7 0:60d829a0353a 7904 #define UART_C1_PE_MASK 0x2u
tushki7 0:60d829a0353a 7905 #define UART_C1_PE_SHIFT 1
tushki7 0:60d829a0353a 7906 #define UART_C1_ILT_MASK 0x4u
tushki7 0:60d829a0353a 7907 #define UART_C1_ILT_SHIFT 2
tushki7 0:60d829a0353a 7908 #define UART_C1_WAKE_MASK 0x8u
tushki7 0:60d829a0353a 7909 #define UART_C1_WAKE_SHIFT 3
tushki7 0:60d829a0353a 7910 #define UART_C1_M_MASK 0x10u
tushki7 0:60d829a0353a 7911 #define UART_C1_M_SHIFT 4
tushki7 0:60d829a0353a 7912 #define UART_C1_RSRC_MASK 0x20u
tushki7 0:60d829a0353a 7913 #define UART_C1_RSRC_SHIFT 5
tushki7 0:60d829a0353a 7914 #define UART_C1_LOOPS_MASK 0x80u
tushki7 0:60d829a0353a 7915 #define UART_C1_LOOPS_SHIFT 7
tushki7 0:60d829a0353a 7916 /* C2 Bit Fields */
tushki7 0:60d829a0353a 7917 #define UART_C2_SBK_MASK 0x1u
tushki7 0:60d829a0353a 7918 #define UART_C2_SBK_SHIFT 0
tushki7 0:60d829a0353a 7919 #define UART_C2_RWU_MASK 0x2u
tushki7 0:60d829a0353a 7920 #define UART_C2_RWU_SHIFT 1
tushki7 0:60d829a0353a 7921 #define UART_C2_RE_MASK 0x4u
tushki7 0:60d829a0353a 7922 #define UART_C2_RE_SHIFT 2
tushki7 0:60d829a0353a 7923 #define UART_C2_TE_MASK 0x8u
tushki7 0:60d829a0353a 7924 #define UART_C2_TE_SHIFT 3
tushki7 0:60d829a0353a 7925 #define UART_C2_ILIE_MASK 0x10u
tushki7 0:60d829a0353a 7926 #define UART_C2_ILIE_SHIFT 4
tushki7 0:60d829a0353a 7927 #define UART_C2_RIE_MASK 0x20u
tushki7 0:60d829a0353a 7928 #define UART_C2_RIE_SHIFT 5
tushki7 0:60d829a0353a 7929 #define UART_C2_TCIE_MASK 0x40u
tushki7 0:60d829a0353a 7930 #define UART_C2_TCIE_SHIFT 6
tushki7 0:60d829a0353a 7931 #define UART_C2_TIE_MASK 0x80u
tushki7 0:60d829a0353a 7932 #define UART_C2_TIE_SHIFT 7
tushki7 0:60d829a0353a 7933 /* S1 Bit Fields */
tushki7 0:60d829a0353a 7934 #define UART_S1_PF_MASK 0x1u
tushki7 0:60d829a0353a 7935 #define UART_S1_PF_SHIFT 0
tushki7 0:60d829a0353a 7936 #define UART_S1_FE_MASK 0x2u
tushki7 0:60d829a0353a 7937 #define UART_S1_FE_SHIFT 1
tushki7 0:60d829a0353a 7938 #define UART_S1_NF_MASK 0x4u
tushki7 0:60d829a0353a 7939 #define UART_S1_NF_SHIFT 2
tushki7 0:60d829a0353a 7940 #define UART_S1_OR_MASK 0x8u
tushki7 0:60d829a0353a 7941 #define UART_S1_OR_SHIFT 3
tushki7 0:60d829a0353a 7942 #define UART_S1_IDLE_MASK 0x10u
tushki7 0:60d829a0353a 7943 #define UART_S1_IDLE_SHIFT 4
tushki7 0:60d829a0353a 7944 #define UART_S1_RDRF_MASK 0x20u
tushki7 0:60d829a0353a 7945 #define UART_S1_RDRF_SHIFT 5
tushki7 0:60d829a0353a 7946 #define UART_S1_TC_MASK 0x40u
tushki7 0:60d829a0353a 7947 #define UART_S1_TC_SHIFT 6
tushki7 0:60d829a0353a 7948 #define UART_S1_TDRE_MASK 0x80u
tushki7 0:60d829a0353a 7949 #define UART_S1_TDRE_SHIFT 7
tushki7 0:60d829a0353a 7950 /* S2 Bit Fields */
tushki7 0:60d829a0353a 7951 #define UART_S2_RAF_MASK 0x1u
tushki7 0:60d829a0353a 7952 #define UART_S2_RAF_SHIFT 0
tushki7 0:60d829a0353a 7953 #define UART_S2_BRK13_MASK 0x4u
tushki7 0:60d829a0353a 7954 #define UART_S2_BRK13_SHIFT 2
tushki7 0:60d829a0353a 7955 #define UART_S2_RWUID_MASK 0x8u
tushki7 0:60d829a0353a 7956 #define UART_S2_RWUID_SHIFT 3
tushki7 0:60d829a0353a 7957 #define UART_S2_RXINV_MASK 0x10u
tushki7 0:60d829a0353a 7958 #define UART_S2_RXINV_SHIFT 4
tushki7 0:60d829a0353a 7959 #define UART_S2_MSBF_MASK 0x20u
tushki7 0:60d829a0353a 7960 #define UART_S2_MSBF_SHIFT 5
tushki7 0:60d829a0353a 7961 #define UART_S2_RXEDGIF_MASK 0x40u
tushki7 0:60d829a0353a 7962 #define UART_S2_RXEDGIF_SHIFT 6
tushki7 0:60d829a0353a 7963 /* C3 Bit Fields */
tushki7 0:60d829a0353a 7964 #define UART_C3_PEIE_MASK 0x1u
tushki7 0:60d829a0353a 7965 #define UART_C3_PEIE_SHIFT 0
tushki7 0:60d829a0353a 7966 #define UART_C3_FEIE_MASK 0x2u
tushki7 0:60d829a0353a 7967 #define UART_C3_FEIE_SHIFT 1
tushki7 0:60d829a0353a 7968 #define UART_C3_NEIE_MASK 0x4u
tushki7 0:60d829a0353a 7969 #define UART_C3_NEIE_SHIFT 2
tushki7 0:60d829a0353a 7970 #define UART_C3_ORIE_MASK 0x8u
tushki7 0:60d829a0353a 7971 #define UART_C3_ORIE_SHIFT 3
tushki7 0:60d829a0353a 7972 #define UART_C3_TXINV_MASK 0x10u
tushki7 0:60d829a0353a 7973 #define UART_C3_TXINV_SHIFT 4
tushki7 0:60d829a0353a 7974 #define UART_C3_TXDIR_MASK 0x20u
tushki7 0:60d829a0353a 7975 #define UART_C3_TXDIR_SHIFT 5
tushki7 0:60d829a0353a 7976 #define UART_C3_T8_MASK 0x40u
tushki7 0:60d829a0353a 7977 #define UART_C3_T8_SHIFT 6
tushki7 0:60d829a0353a 7978 #define UART_C3_R8_MASK 0x80u
tushki7 0:60d829a0353a 7979 #define UART_C3_R8_SHIFT 7
tushki7 0:60d829a0353a 7980 /* D Bit Fields */
tushki7 0:60d829a0353a 7981 #define UART_D_RT_MASK 0xFFu
tushki7 0:60d829a0353a 7982 #define UART_D_RT_SHIFT 0
tushki7 0:60d829a0353a 7983 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
tushki7 0:60d829a0353a 7984 /* MA1 Bit Fields */
tushki7 0:60d829a0353a 7985 #define UART_MA1_MA_MASK 0xFFu
tushki7 0:60d829a0353a 7986 #define UART_MA1_MA_SHIFT 0
tushki7 0:60d829a0353a 7987 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
tushki7 0:60d829a0353a 7988 /* MA2 Bit Fields */
tushki7 0:60d829a0353a 7989 #define UART_MA2_MA_MASK 0xFFu
tushki7 0:60d829a0353a 7990 #define UART_MA2_MA_SHIFT 0
tushki7 0:60d829a0353a 7991 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
tushki7 0:60d829a0353a 7992 /* C4 Bit Fields */
tushki7 0:60d829a0353a 7993 #define UART_C4_BRFA_MASK 0x1Fu
tushki7 0:60d829a0353a 7994 #define UART_C4_BRFA_SHIFT 0
tushki7 0:60d829a0353a 7995 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
tushki7 0:60d829a0353a 7996 #define UART_C4_M10_MASK 0x20u
tushki7 0:60d829a0353a 7997 #define UART_C4_M10_SHIFT 5
tushki7 0:60d829a0353a 7998 #define UART_C4_MAEN2_MASK 0x40u
tushki7 0:60d829a0353a 7999 #define UART_C4_MAEN2_SHIFT 6
tushki7 0:60d829a0353a 8000 #define UART_C4_MAEN1_MASK 0x80u
tushki7 0:60d829a0353a 8001 #define UART_C4_MAEN1_SHIFT 7
tushki7 0:60d829a0353a 8002 /* C5 Bit Fields */
tushki7 0:60d829a0353a 8003 #define UART_C5_RDMAS_MASK 0x20u
tushki7 0:60d829a0353a 8004 #define UART_C5_RDMAS_SHIFT 5
tushki7 0:60d829a0353a 8005 #define UART_C5_TDMAS_MASK 0x80u
tushki7 0:60d829a0353a 8006 #define UART_C5_TDMAS_SHIFT 7
tushki7 0:60d829a0353a 8007 /* C7816 Bit Fields */
tushki7 0:60d829a0353a 8008 #define UART_C7816_ISO_7816E_MASK 0x1u
tushki7 0:60d829a0353a 8009 #define UART_C7816_ISO_7816E_SHIFT 0
tushki7 0:60d829a0353a 8010 #define UART_C7816_TTYPE_MASK 0x2u
tushki7 0:60d829a0353a 8011 #define UART_C7816_TTYPE_SHIFT 1
tushki7 0:60d829a0353a 8012 #define UART_C7816_INIT_MASK 0x4u
tushki7 0:60d829a0353a 8013 #define UART_C7816_INIT_SHIFT 2
tushki7 0:60d829a0353a 8014 #define UART_C7816_ANACK_MASK 0x8u
tushki7 0:60d829a0353a 8015 #define UART_C7816_ANACK_SHIFT 3
tushki7 0:60d829a0353a 8016 #define UART_C7816_ONACK_MASK 0x10u
tushki7 0:60d829a0353a 8017 #define UART_C7816_ONACK_SHIFT 4
tushki7 0:60d829a0353a 8018 /* IE7816 Bit Fields */
tushki7 0:60d829a0353a 8019 #define UART_IE7816_RXTE_MASK 0x1u
tushki7 0:60d829a0353a 8020 #define UART_IE7816_RXTE_SHIFT 0
tushki7 0:60d829a0353a 8021 #define UART_IE7816_TXTE_MASK 0x2u
tushki7 0:60d829a0353a 8022 #define UART_IE7816_TXTE_SHIFT 1
tushki7 0:60d829a0353a 8023 #define UART_IE7816_GTVE_MASK 0x4u
tushki7 0:60d829a0353a 8024 #define UART_IE7816_GTVE_SHIFT 2
tushki7 0:60d829a0353a 8025 #define UART_IE7816_ADTE_MASK 0x8u
tushki7 0:60d829a0353a 8026 #define UART_IE7816_ADTE_SHIFT 3
tushki7 0:60d829a0353a 8027 #define UART_IE7816_INITDE_MASK 0x10u
tushki7 0:60d829a0353a 8028 #define UART_IE7816_INITDE_SHIFT 4
tushki7 0:60d829a0353a 8029 #define UART_IE7816_BWTE_MASK 0x20u
tushki7 0:60d829a0353a 8030 #define UART_IE7816_BWTE_SHIFT 5
tushki7 0:60d829a0353a 8031 #define UART_IE7816_CWTE_MASK 0x40u
tushki7 0:60d829a0353a 8032 #define UART_IE7816_CWTE_SHIFT 6
tushki7 0:60d829a0353a 8033 #define UART_IE7816_WTE_MASK 0x80u
tushki7 0:60d829a0353a 8034 #define UART_IE7816_WTE_SHIFT 7
tushki7 0:60d829a0353a 8035 /* IS7816 Bit Fields */
tushki7 0:60d829a0353a 8036 #define UART_IS7816_RXT_MASK 0x1u
tushki7 0:60d829a0353a 8037 #define UART_IS7816_RXT_SHIFT 0
tushki7 0:60d829a0353a 8038 #define UART_IS7816_TXT_MASK 0x2u
tushki7 0:60d829a0353a 8039 #define UART_IS7816_TXT_SHIFT 1
tushki7 0:60d829a0353a 8040 #define UART_IS7816_GTV_MASK 0x4u
tushki7 0:60d829a0353a 8041 #define UART_IS7816_GTV_SHIFT 2
tushki7 0:60d829a0353a 8042 #define UART_IS7816_ADT_MASK 0x8u
tushki7 0:60d829a0353a 8043 #define UART_IS7816_ADT_SHIFT 3
tushki7 0:60d829a0353a 8044 #define UART_IS7816_INITD_MASK 0x10u
tushki7 0:60d829a0353a 8045 #define UART_IS7816_INITD_SHIFT 4
tushki7 0:60d829a0353a 8046 #define UART_IS7816_BWT_MASK 0x20u
tushki7 0:60d829a0353a 8047 #define UART_IS7816_BWT_SHIFT 5
tushki7 0:60d829a0353a 8048 #define UART_IS7816_CWT_MASK 0x40u
tushki7 0:60d829a0353a 8049 #define UART_IS7816_CWT_SHIFT 6
tushki7 0:60d829a0353a 8050 #define UART_IS7816_WT_MASK 0x80u
tushki7 0:60d829a0353a 8051 #define UART_IS7816_WT_SHIFT 7
tushki7 0:60d829a0353a 8052 /* WP7816 Bit Fields */
tushki7 0:60d829a0353a 8053 #define UART_WP7816_WTX_MASK 0xFFu
tushki7 0:60d829a0353a 8054 #define UART_WP7816_WTX_SHIFT 0
tushki7 0:60d829a0353a 8055 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
tushki7 0:60d829a0353a 8056 /* WN7816 Bit Fields */
tushki7 0:60d829a0353a 8057 #define UART_WN7816_GTN_MASK 0xFFu
tushki7 0:60d829a0353a 8058 #define UART_WN7816_GTN_SHIFT 0
tushki7 0:60d829a0353a 8059 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
tushki7 0:60d829a0353a 8060 /* WF7816 Bit Fields */
tushki7 0:60d829a0353a 8061 #define UART_WF7816_GTFD_MASK 0xFFu
tushki7 0:60d829a0353a 8062 #define UART_WF7816_GTFD_SHIFT 0
tushki7 0:60d829a0353a 8063 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
tushki7 0:60d829a0353a 8064 /* ET7816 Bit Fields */
tushki7 0:60d829a0353a 8065 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
tushki7 0:60d829a0353a 8066 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
tushki7 0:60d829a0353a 8067 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
tushki7 0:60d829a0353a 8068 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
tushki7 0:60d829a0353a 8069 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
tushki7 0:60d829a0353a 8070 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
tushki7 0:60d829a0353a 8071 /* TL7816 Bit Fields */
tushki7 0:60d829a0353a 8072 #define UART_TL7816_TLEN_MASK 0xFFu
tushki7 0:60d829a0353a 8073 #define UART_TL7816_TLEN_SHIFT 0
tushki7 0:60d829a0353a 8074 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
tushki7 0:60d829a0353a 8075 /* AP7816A_T0 Bit Fields */
tushki7 0:60d829a0353a 8076 #define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
tushki7 0:60d829a0353a 8077 #define UART_AP7816A_T0_ADTI_H_SHIFT 0
tushki7 0:60d829a0353a 8078 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
tushki7 0:60d829a0353a 8079 /* AP7816B_T0 Bit Fields */
tushki7 0:60d829a0353a 8080 #define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
tushki7 0:60d829a0353a 8081 #define UART_AP7816B_T0_ADTI_L_SHIFT 0
tushki7 0:60d829a0353a 8082 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
tushki7 0:60d829a0353a 8083 /* WP7816A_T0 Bit Fields */
tushki7 0:60d829a0353a 8084 #define UART_WP7816A_T0_WI_H_MASK 0xFFu
tushki7 0:60d829a0353a 8085 #define UART_WP7816A_T0_WI_H_SHIFT 0
tushki7 0:60d829a0353a 8086 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
tushki7 0:60d829a0353a 8087 /* WP7816B_T0 Bit Fields */
tushki7 0:60d829a0353a 8088 #define UART_WP7816B_T0_WI_L_MASK 0xFFu
tushki7 0:60d829a0353a 8089 #define UART_WP7816B_T0_WI_L_SHIFT 0
tushki7 0:60d829a0353a 8090 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
tushki7 0:60d829a0353a 8091 /* WP7816A_T1 Bit Fields */
tushki7 0:60d829a0353a 8092 #define UART_WP7816A_T1_BWI_H_MASK 0xFFu
tushki7 0:60d829a0353a 8093 #define UART_WP7816A_T1_BWI_H_SHIFT 0
tushki7 0:60d829a0353a 8094 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
tushki7 0:60d829a0353a 8095 /* WP7816B_T1 Bit Fields */
tushki7 0:60d829a0353a 8096 #define UART_WP7816B_T1_BWI_L_MASK 0xFFu
tushki7 0:60d829a0353a 8097 #define UART_WP7816B_T1_BWI_L_SHIFT 0
tushki7 0:60d829a0353a 8098 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
tushki7 0:60d829a0353a 8099 /* WGP7816_T1 Bit Fields */
tushki7 0:60d829a0353a 8100 #define UART_WGP7816_T1_BGI_MASK 0xFu
tushki7 0:60d829a0353a 8101 #define UART_WGP7816_T1_BGI_SHIFT 0
tushki7 0:60d829a0353a 8102 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
tushki7 0:60d829a0353a 8103 #define UART_WGP7816_T1_CWI1_MASK 0xF0u
tushki7 0:60d829a0353a 8104 #define UART_WGP7816_T1_CWI1_SHIFT 4
tushki7 0:60d829a0353a 8105 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
tushki7 0:60d829a0353a 8106 /* WP7816C_T1 Bit Fields */
tushki7 0:60d829a0353a 8107 #define UART_WP7816C_T1_CWI2_MASK 0x1Fu
tushki7 0:60d829a0353a 8108 #define UART_WP7816C_T1_CWI2_SHIFT 0
tushki7 0:60d829a0353a 8109 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
tushki7 0:60d829a0353a 8110
tushki7 0:60d829a0353a 8111 /*!
tushki7 0:60d829a0353a 8112 * @}
tushki7 0:60d829a0353a 8113 */ /* end of group UART_Register_Masks */
tushki7 0:60d829a0353a 8114
tushki7 0:60d829a0353a 8115
tushki7 0:60d829a0353a 8116 /* UART - Peripheral instance base addresses */
tushki7 0:60d829a0353a 8117 /** Peripheral UART2 base address */
tushki7 0:60d829a0353a 8118 #define UART2_BASE (0x4006C000u)
tushki7 0:60d829a0353a 8119 /** Peripheral UART2 base pointer */
tushki7 0:60d829a0353a 8120 #define UART2 ((UART_Type *)UART2_BASE)
tushki7 0:60d829a0353a 8121 #define UART2_BASE_PTR (UART2)
tushki7 0:60d829a0353a 8122 /** Array initializer of UART peripheral base addresses */
tushki7 0:60d829a0353a 8123 #define UART_BASE_ADDRS { UART2_BASE }
tushki7 0:60d829a0353a 8124 /** Array initializer of UART peripheral base pointers */
tushki7 0:60d829a0353a 8125 #define UART_BASE_PTRS { UART2 }
tushki7 0:60d829a0353a 8126 /** Interrupt vectors for the UART peripheral type */
tushki7 0:60d829a0353a 8127 #define UART_RX_TX_IRQS { UART2_FLEXIO_IRQn }
tushki7 0:60d829a0353a 8128 #define UART_ERR_IRQS { UART2_FLEXIO_IRQn }
tushki7 0:60d829a0353a 8129
tushki7 0:60d829a0353a 8130 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8131 -- UART - Register accessor macros
tushki7 0:60d829a0353a 8132 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8133
tushki7 0:60d829a0353a 8134 /*!
tushki7 0:60d829a0353a 8135 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
tushki7 0:60d829a0353a 8136 * @{
tushki7 0:60d829a0353a 8137 */
tushki7 0:60d829a0353a 8138
tushki7 0:60d829a0353a 8139
tushki7 0:60d829a0353a 8140 /* UART - Register instance definitions */
tushki7 0:60d829a0353a 8141 /* UART2 */
tushki7 0:60d829a0353a 8142 #define UART2_BDH UART_BDH_REG(UART2)
tushki7 0:60d829a0353a 8143 #define UART2_BDL UART_BDL_REG(UART2)
tushki7 0:60d829a0353a 8144 #define UART2_C1 UART_C1_REG(UART2)
tushki7 0:60d829a0353a 8145 #define UART2_C2 UART_C2_REG(UART2)
tushki7 0:60d829a0353a 8146 #define UART2_S1 UART_S1_REG(UART2)
tushki7 0:60d829a0353a 8147 #define UART2_S2 UART_S2_REG(UART2)
tushki7 0:60d829a0353a 8148 #define UART2_C3 UART_C3_REG(UART2)
tushki7 0:60d829a0353a 8149 #define UART2_D UART_D_REG(UART2)
tushki7 0:60d829a0353a 8150 #define UART2_MA1 UART_MA1_REG(UART2)
tushki7 0:60d829a0353a 8151 #define UART2_MA2 UART_MA2_REG(UART2)
tushki7 0:60d829a0353a 8152 #define UART2_C4 UART_C4_REG(UART2)
tushki7 0:60d829a0353a 8153 #define UART2_C5 UART_C5_REG(UART2)
tushki7 0:60d829a0353a 8154 #define UART2_C7816 UART_C7816_REG(UART2)
tushki7 0:60d829a0353a 8155 #define UART2_IE7816 UART_IE7816_REG(UART2)
tushki7 0:60d829a0353a 8156 #define UART2_IS7816 UART_IS7816_REG(UART2)
tushki7 0:60d829a0353a 8157 #define UART2_WP7816 UART_WP7816_REG(UART2)
tushki7 0:60d829a0353a 8158 #define UART2_WN7816 UART_WN7816_REG(UART2)
tushki7 0:60d829a0353a 8159 #define UART2_WF7816 UART_WF7816_REG(UART2)
tushki7 0:60d829a0353a 8160 #define UART2_ET7816 UART_ET7816_REG(UART2)
tushki7 0:60d829a0353a 8161 #define UART2_TL7816 UART_TL7816_REG(UART2)
tushki7 0:60d829a0353a 8162 #define UART2_AP7816A_T0 UART_AP7816A_T0_REG(UART2)
tushki7 0:60d829a0353a 8163 #define UART2_AP7816B_T0 UART_AP7816B_T0_REG(UART2)
tushki7 0:60d829a0353a 8164 #define UART2_WP7816A_T0 UART_WP7816A_T0_REG(UART2)
tushki7 0:60d829a0353a 8165 #define UART2_WP7816A_T1 UART_WP7816A_T1_REG(UART2)
tushki7 0:60d829a0353a 8166 #define UART2_WP7816B_T0 UART_WP7816B_T0_REG(UART2)
tushki7 0:60d829a0353a 8167 #define UART2_WP7816B_T1 UART_WP7816B_T1_REG(UART2)
tushki7 0:60d829a0353a 8168 #define UART2_WGP7816_T1 UART_WGP7816_T1_REG(UART2)
tushki7 0:60d829a0353a 8169 #define UART2_WP7816C_T1 UART_WP7816C_T1_REG(UART2)
tushki7 0:60d829a0353a 8170
tushki7 0:60d829a0353a 8171 /*!
tushki7 0:60d829a0353a 8172 * @}
tushki7 0:60d829a0353a 8173 */ /* end of group UART_Register_Accessor_Macros */
tushki7 0:60d829a0353a 8174
tushki7 0:60d829a0353a 8175
tushki7 0:60d829a0353a 8176 /*!
tushki7 0:60d829a0353a 8177 * @}
tushki7 0:60d829a0353a 8178 */ /* end of group UART_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 8179
tushki7 0:60d829a0353a 8180
tushki7 0:60d829a0353a 8181 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8182 -- USB Peripheral Access Layer
tushki7 0:60d829a0353a 8183 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8184
tushki7 0:60d829a0353a 8185 /*!
tushki7 0:60d829a0353a 8186 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
tushki7 0:60d829a0353a 8187 * @{
tushki7 0:60d829a0353a 8188 */
tushki7 0:60d829a0353a 8189
tushki7 0:60d829a0353a 8190 /** USB - Register Layout Typedef */
tushki7 0:60d829a0353a 8191 typedef struct {
tushki7 0:60d829a0353a 8192 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
tushki7 0:60d829a0353a 8193 uint8_t RESERVED_0[3];
tushki7 0:60d829a0353a 8194 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
tushki7 0:60d829a0353a 8195 uint8_t RESERVED_1[3];
tushki7 0:60d829a0353a 8196 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
tushki7 0:60d829a0353a 8197 uint8_t RESERVED_2[3];
tushki7 0:60d829a0353a 8198 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
tushki7 0:60d829a0353a 8199 uint8_t RESERVED_3[15];
tushki7 0:60d829a0353a 8200 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
tushki7 0:60d829a0353a 8201 uint8_t RESERVED_4[99];
tushki7 0:60d829a0353a 8202 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
tushki7 0:60d829a0353a 8203 uint8_t RESERVED_5[3];
tushki7 0:60d829a0353a 8204 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
tushki7 0:60d829a0353a 8205 uint8_t RESERVED_6[3];
tushki7 0:60d829a0353a 8206 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
tushki7 0:60d829a0353a 8207 uint8_t RESERVED_7[3];
tushki7 0:60d829a0353a 8208 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
tushki7 0:60d829a0353a 8209 uint8_t RESERVED_8[3];
tushki7 0:60d829a0353a 8210 __I uint8_t STAT; /**< Status register, offset: 0x90 */
tushki7 0:60d829a0353a 8211 uint8_t RESERVED_9[3];
tushki7 0:60d829a0353a 8212 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
tushki7 0:60d829a0353a 8213 uint8_t RESERVED_10[3];
tushki7 0:60d829a0353a 8214 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
tushki7 0:60d829a0353a 8215 uint8_t RESERVED_11[3];
tushki7 0:60d829a0353a 8216 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
tushki7 0:60d829a0353a 8217 uint8_t RESERVED_12[3];
tushki7 0:60d829a0353a 8218 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
tushki7 0:60d829a0353a 8219 uint8_t RESERVED_13[3];
tushki7 0:60d829a0353a 8220 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
tushki7 0:60d829a0353a 8221 uint8_t RESERVED_14[11];
tushki7 0:60d829a0353a 8222 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
tushki7 0:60d829a0353a 8223 uint8_t RESERVED_15[3];
tushki7 0:60d829a0353a 8224 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
tushki7 0:60d829a0353a 8225 uint8_t RESERVED_16[11];
tushki7 0:60d829a0353a 8226 struct { /* offset: 0xC0, array step: 0x4 */
tushki7 0:60d829a0353a 8227 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
tushki7 0:60d829a0353a 8228 uint8_t RESERVED_0[3];
tushki7 0:60d829a0353a 8229 } ENDPOINT[16];
tushki7 0:60d829a0353a 8230 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
tushki7 0:60d829a0353a 8231 uint8_t RESERVED_17[3];
tushki7 0:60d829a0353a 8232 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
tushki7 0:60d829a0353a 8233 uint8_t RESERVED_18[3];
tushki7 0:60d829a0353a 8234 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
tushki7 0:60d829a0353a 8235 uint8_t RESERVED_19[3];
tushki7 0:60d829a0353a 8236 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
tushki7 0:60d829a0353a 8237 uint8_t RESERVED_20[7];
tushki7 0:60d829a0353a 8238 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
tushki7 0:60d829a0353a 8239 uint8_t RESERVED_21[43];
tushki7 0:60d829a0353a 8240 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
tushki7 0:60d829a0353a 8241 uint8_t RESERVED_22[3];
tushki7 0:60d829a0353a 8242 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
tushki7 0:60d829a0353a 8243 uint8_t RESERVED_23[15];
tushki7 0:60d829a0353a 8244 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
tushki7 0:60d829a0353a 8245 uint8_t RESERVED_24[7];
tushki7 0:60d829a0353a 8246 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
tushki7 0:60d829a0353a 8247 } USB_Type, *USB_MemMapPtr;
tushki7 0:60d829a0353a 8248
tushki7 0:60d829a0353a 8249 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8250 -- USB - Register accessor macros
tushki7 0:60d829a0353a 8251 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8252
tushki7 0:60d829a0353a 8253 /*!
tushki7 0:60d829a0353a 8254 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
tushki7 0:60d829a0353a 8255 * @{
tushki7 0:60d829a0353a 8256 */
tushki7 0:60d829a0353a 8257
tushki7 0:60d829a0353a 8258
tushki7 0:60d829a0353a 8259 /* USB - Register accessors */
tushki7 0:60d829a0353a 8260 #define USB_PERID_REG(base) ((base)->PERID)
tushki7 0:60d829a0353a 8261 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
tushki7 0:60d829a0353a 8262 #define USB_REV_REG(base) ((base)->REV)
tushki7 0:60d829a0353a 8263 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
tushki7 0:60d829a0353a 8264 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
tushki7 0:60d829a0353a 8265 #define USB_ISTAT_REG(base) ((base)->ISTAT)
tushki7 0:60d829a0353a 8266 #define USB_INTEN_REG(base) ((base)->INTEN)
tushki7 0:60d829a0353a 8267 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
tushki7 0:60d829a0353a 8268 #define USB_ERREN_REG(base) ((base)->ERREN)
tushki7 0:60d829a0353a 8269 #define USB_STAT_REG(base) ((base)->STAT)
tushki7 0:60d829a0353a 8270 #define USB_CTL_REG(base) ((base)->CTL)
tushki7 0:60d829a0353a 8271 #define USB_ADDR_REG(base) ((base)->ADDR)
tushki7 0:60d829a0353a 8272 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
tushki7 0:60d829a0353a 8273 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
tushki7 0:60d829a0353a 8274 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
tushki7 0:60d829a0353a 8275 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
tushki7 0:60d829a0353a 8276 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
tushki7 0:60d829a0353a 8277 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
tushki7 0:60d829a0353a 8278 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
tushki7 0:60d829a0353a 8279 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
tushki7 0:60d829a0353a 8280 #define USB_CONTROL_REG(base) ((base)->CONTROL)
tushki7 0:60d829a0353a 8281 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
tushki7 0:60d829a0353a 8282 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
tushki7 0:60d829a0353a 8283 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
tushki7 0:60d829a0353a 8284 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
tushki7 0:60d829a0353a 8285 #define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
tushki7 0:60d829a0353a 8286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
tushki7 0:60d829a0353a 8287
tushki7 0:60d829a0353a 8288 /*!
tushki7 0:60d829a0353a 8289 * @}
tushki7 0:60d829a0353a 8290 */ /* end of group USB_Register_Accessor_Macros */
tushki7 0:60d829a0353a 8291
tushki7 0:60d829a0353a 8292
tushki7 0:60d829a0353a 8293 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8294 -- USB Register Masks
tushki7 0:60d829a0353a 8295 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8296
tushki7 0:60d829a0353a 8297 /*!
tushki7 0:60d829a0353a 8298 * @addtogroup USB_Register_Masks USB Register Masks
tushki7 0:60d829a0353a 8299 * @{
tushki7 0:60d829a0353a 8300 */
tushki7 0:60d829a0353a 8301
tushki7 0:60d829a0353a 8302 /* PERID Bit Fields */
tushki7 0:60d829a0353a 8303 #define USB_PERID_ID_MASK 0x3Fu
tushki7 0:60d829a0353a 8304 #define USB_PERID_ID_SHIFT 0
tushki7 0:60d829a0353a 8305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
tushki7 0:60d829a0353a 8306 /* IDCOMP Bit Fields */
tushki7 0:60d829a0353a 8307 #define USB_IDCOMP_NID_MASK 0x3Fu
tushki7 0:60d829a0353a 8308 #define USB_IDCOMP_NID_SHIFT 0
tushki7 0:60d829a0353a 8309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
tushki7 0:60d829a0353a 8310 /* REV Bit Fields */
tushki7 0:60d829a0353a 8311 #define USB_REV_REV_MASK 0xFFu
tushki7 0:60d829a0353a 8312 #define USB_REV_REV_SHIFT 0
tushki7 0:60d829a0353a 8313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
tushki7 0:60d829a0353a 8314 /* ADDINFO Bit Fields */
tushki7 0:60d829a0353a 8315 #define USB_ADDINFO_IEHOST_MASK 0x1u
tushki7 0:60d829a0353a 8316 #define USB_ADDINFO_IEHOST_SHIFT 0
tushki7 0:60d829a0353a 8317 /* OTGCTL Bit Fields */
tushki7 0:60d829a0353a 8318 #define USB_OTGCTL_DPHIGH_MASK 0x80u
tushki7 0:60d829a0353a 8319 #define USB_OTGCTL_DPHIGH_SHIFT 7
tushki7 0:60d829a0353a 8320 /* ISTAT Bit Fields */
tushki7 0:60d829a0353a 8321 #define USB_ISTAT_USBRST_MASK 0x1u
tushki7 0:60d829a0353a 8322 #define USB_ISTAT_USBRST_SHIFT 0
tushki7 0:60d829a0353a 8323 #define USB_ISTAT_ERROR_MASK 0x2u
tushki7 0:60d829a0353a 8324 #define USB_ISTAT_ERROR_SHIFT 1
tushki7 0:60d829a0353a 8325 #define USB_ISTAT_SOFTOK_MASK 0x4u
tushki7 0:60d829a0353a 8326 #define USB_ISTAT_SOFTOK_SHIFT 2
tushki7 0:60d829a0353a 8327 #define USB_ISTAT_TOKDNE_MASK 0x8u
tushki7 0:60d829a0353a 8328 #define USB_ISTAT_TOKDNE_SHIFT 3
tushki7 0:60d829a0353a 8329 #define USB_ISTAT_SLEEP_MASK 0x10u
tushki7 0:60d829a0353a 8330 #define USB_ISTAT_SLEEP_SHIFT 4
tushki7 0:60d829a0353a 8331 #define USB_ISTAT_RESUME_MASK 0x20u
tushki7 0:60d829a0353a 8332 #define USB_ISTAT_RESUME_SHIFT 5
tushki7 0:60d829a0353a 8333 #define USB_ISTAT_STALL_MASK 0x80u
tushki7 0:60d829a0353a 8334 #define USB_ISTAT_STALL_SHIFT 7
tushki7 0:60d829a0353a 8335 /* INTEN Bit Fields */
tushki7 0:60d829a0353a 8336 #define USB_INTEN_USBRSTEN_MASK 0x1u
tushki7 0:60d829a0353a 8337 #define USB_INTEN_USBRSTEN_SHIFT 0
tushki7 0:60d829a0353a 8338 #define USB_INTEN_ERROREN_MASK 0x2u
tushki7 0:60d829a0353a 8339 #define USB_INTEN_ERROREN_SHIFT 1
tushki7 0:60d829a0353a 8340 #define USB_INTEN_SOFTOKEN_MASK 0x4u
tushki7 0:60d829a0353a 8341 #define USB_INTEN_SOFTOKEN_SHIFT 2
tushki7 0:60d829a0353a 8342 #define USB_INTEN_TOKDNEEN_MASK 0x8u
tushki7 0:60d829a0353a 8343 #define USB_INTEN_TOKDNEEN_SHIFT 3
tushki7 0:60d829a0353a 8344 #define USB_INTEN_SLEEPEN_MASK 0x10u
tushki7 0:60d829a0353a 8345 #define USB_INTEN_SLEEPEN_SHIFT 4
tushki7 0:60d829a0353a 8346 #define USB_INTEN_RESUMEEN_MASK 0x20u
tushki7 0:60d829a0353a 8347 #define USB_INTEN_RESUMEEN_SHIFT 5
tushki7 0:60d829a0353a 8348 #define USB_INTEN_STALLEN_MASK 0x80u
tushki7 0:60d829a0353a 8349 #define USB_INTEN_STALLEN_SHIFT 7
tushki7 0:60d829a0353a 8350 /* ERRSTAT Bit Fields */
tushki7 0:60d829a0353a 8351 #define USB_ERRSTAT_PIDERR_MASK 0x1u
tushki7 0:60d829a0353a 8352 #define USB_ERRSTAT_PIDERR_SHIFT 0
tushki7 0:60d829a0353a 8353 #define USB_ERRSTAT_CRC5_MASK 0x2u
tushki7 0:60d829a0353a 8354 #define USB_ERRSTAT_CRC5_SHIFT 1
tushki7 0:60d829a0353a 8355 #define USB_ERRSTAT_CRC16_MASK 0x4u
tushki7 0:60d829a0353a 8356 #define USB_ERRSTAT_CRC16_SHIFT 2
tushki7 0:60d829a0353a 8357 #define USB_ERRSTAT_DFN8_MASK 0x8u
tushki7 0:60d829a0353a 8358 #define USB_ERRSTAT_DFN8_SHIFT 3
tushki7 0:60d829a0353a 8359 #define USB_ERRSTAT_BTOERR_MASK 0x10u
tushki7 0:60d829a0353a 8360 #define USB_ERRSTAT_BTOERR_SHIFT 4
tushki7 0:60d829a0353a 8361 #define USB_ERRSTAT_DMAERR_MASK 0x20u
tushki7 0:60d829a0353a 8362 #define USB_ERRSTAT_DMAERR_SHIFT 5
tushki7 0:60d829a0353a 8363 #define USB_ERRSTAT_BTSERR_MASK 0x80u
tushki7 0:60d829a0353a 8364 #define USB_ERRSTAT_BTSERR_SHIFT 7
tushki7 0:60d829a0353a 8365 /* ERREN Bit Fields */
tushki7 0:60d829a0353a 8366 #define USB_ERREN_PIDERREN_MASK 0x1u
tushki7 0:60d829a0353a 8367 #define USB_ERREN_PIDERREN_SHIFT 0
tushki7 0:60d829a0353a 8368 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
tushki7 0:60d829a0353a 8369 #define USB_ERREN_CRC5EOFEN_SHIFT 1
tushki7 0:60d829a0353a 8370 #define USB_ERREN_CRC16EN_MASK 0x4u
tushki7 0:60d829a0353a 8371 #define USB_ERREN_CRC16EN_SHIFT 2
tushki7 0:60d829a0353a 8372 #define USB_ERREN_DFN8EN_MASK 0x8u
tushki7 0:60d829a0353a 8373 #define USB_ERREN_DFN8EN_SHIFT 3
tushki7 0:60d829a0353a 8374 #define USB_ERREN_BTOERREN_MASK 0x10u
tushki7 0:60d829a0353a 8375 #define USB_ERREN_BTOERREN_SHIFT 4
tushki7 0:60d829a0353a 8376 #define USB_ERREN_DMAERREN_MASK 0x20u
tushki7 0:60d829a0353a 8377 #define USB_ERREN_DMAERREN_SHIFT 5
tushki7 0:60d829a0353a 8378 #define USB_ERREN_BTSERREN_MASK 0x80u
tushki7 0:60d829a0353a 8379 #define USB_ERREN_BTSERREN_SHIFT 7
tushki7 0:60d829a0353a 8380 /* STAT Bit Fields */
tushki7 0:60d829a0353a 8381 #define USB_STAT_ODD_MASK 0x4u
tushki7 0:60d829a0353a 8382 #define USB_STAT_ODD_SHIFT 2
tushki7 0:60d829a0353a 8383 #define USB_STAT_TX_MASK 0x8u
tushki7 0:60d829a0353a 8384 #define USB_STAT_TX_SHIFT 3
tushki7 0:60d829a0353a 8385 #define USB_STAT_ENDP_MASK 0xF0u
tushki7 0:60d829a0353a 8386 #define USB_STAT_ENDP_SHIFT 4
tushki7 0:60d829a0353a 8387 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
tushki7 0:60d829a0353a 8388 /* CTL Bit Fields */
tushki7 0:60d829a0353a 8389 #define USB_CTL_USBENSOFEN_MASK 0x1u
tushki7 0:60d829a0353a 8390 #define USB_CTL_USBENSOFEN_SHIFT 0
tushki7 0:60d829a0353a 8391 #define USB_CTL_ODDRST_MASK 0x2u
tushki7 0:60d829a0353a 8392 #define USB_CTL_ODDRST_SHIFT 1
tushki7 0:60d829a0353a 8393 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
tushki7 0:60d829a0353a 8394 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
tushki7 0:60d829a0353a 8395 #define USB_CTL_SE0_MASK 0x40u
tushki7 0:60d829a0353a 8396 #define USB_CTL_SE0_SHIFT 6
tushki7 0:60d829a0353a 8397 #define USB_CTL_JSTATE_MASK 0x80u
tushki7 0:60d829a0353a 8398 #define USB_CTL_JSTATE_SHIFT 7
tushki7 0:60d829a0353a 8399 /* ADDR Bit Fields */
tushki7 0:60d829a0353a 8400 #define USB_ADDR_ADDR_MASK 0x7Fu
tushki7 0:60d829a0353a 8401 #define USB_ADDR_ADDR_SHIFT 0
tushki7 0:60d829a0353a 8402 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
tushki7 0:60d829a0353a 8403 /* BDTPAGE1 Bit Fields */
tushki7 0:60d829a0353a 8404 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
tushki7 0:60d829a0353a 8405 #define USB_BDTPAGE1_BDTBA_SHIFT 1
tushki7 0:60d829a0353a 8406 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
tushki7 0:60d829a0353a 8407 /* FRMNUML Bit Fields */
tushki7 0:60d829a0353a 8408 #define USB_FRMNUML_FRM_MASK 0xFFu
tushki7 0:60d829a0353a 8409 #define USB_FRMNUML_FRM_SHIFT 0
tushki7 0:60d829a0353a 8410 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
tushki7 0:60d829a0353a 8411 /* FRMNUMH Bit Fields */
tushki7 0:60d829a0353a 8412 #define USB_FRMNUMH_FRM_MASK 0x7u
tushki7 0:60d829a0353a 8413 #define USB_FRMNUMH_FRM_SHIFT 0
tushki7 0:60d829a0353a 8414 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
tushki7 0:60d829a0353a 8415 /* BDTPAGE2 Bit Fields */
tushki7 0:60d829a0353a 8416 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
tushki7 0:60d829a0353a 8417 #define USB_BDTPAGE2_BDTBA_SHIFT 0
tushki7 0:60d829a0353a 8418 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
tushki7 0:60d829a0353a 8419 /* BDTPAGE3 Bit Fields */
tushki7 0:60d829a0353a 8420 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
tushki7 0:60d829a0353a 8421 #define USB_BDTPAGE3_BDTBA_SHIFT 0
tushki7 0:60d829a0353a 8422 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
tushki7 0:60d829a0353a 8423 /* ENDPT Bit Fields */
tushki7 0:60d829a0353a 8424 #define USB_ENDPT_EPHSHK_MASK 0x1u
tushki7 0:60d829a0353a 8425 #define USB_ENDPT_EPHSHK_SHIFT 0
tushki7 0:60d829a0353a 8426 #define USB_ENDPT_EPSTALL_MASK 0x2u
tushki7 0:60d829a0353a 8427 #define USB_ENDPT_EPSTALL_SHIFT 1
tushki7 0:60d829a0353a 8428 #define USB_ENDPT_EPTXEN_MASK 0x4u
tushki7 0:60d829a0353a 8429 #define USB_ENDPT_EPTXEN_SHIFT 2
tushki7 0:60d829a0353a 8430 #define USB_ENDPT_EPRXEN_MASK 0x8u
tushki7 0:60d829a0353a 8431 #define USB_ENDPT_EPRXEN_SHIFT 3
tushki7 0:60d829a0353a 8432 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
tushki7 0:60d829a0353a 8433 #define USB_ENDPT_EPCTLDIS_SHIFT 4
tushki7 0:60d829a0353a 8434 /* USBCTRL Bit Fields */
tushki7 0:60d829a0353a 8435 #define USB_USBCTRL_PDE_MASK 0x40u
tushki7 0:60d829a0353a 8436 #define USB_USBCTRL_PDE_SHIFT 6
tushki7 0:60d829a0353a 8437 #define USB_USBCTRL_SUSP_MASK 0x80u
tushki7 0:60d829a0353a 8438 #define USB_USBCTRL_SUSP_SHIFT 7
tushki7 0:60d829a0353a 8439 /* OBSERVE Bit Fields */
tushki7 0:60d829a0353a 8440 #define USB_OBSERVE_DMPD_MASK 0x10u
tushki7 0:60d829a0353a 8441 #define USB_OBSERVE_DMPD_SHIFT 4
tushki7 0:60d829a0353a 8442 #define USB_OBSERVE_DPPD_MASK 0x40u
tushki7 0:60d829a0353a 8443 #define USB_OBSERVE_DPPD_SHIFT 6
tushki7 0:60d829a0353a 8444 #define USB_OBSERVE_DPPU_MASK 0x80u
tushki7 0:60d829a0353a 8445 #define USB_OBSERVE_DPPU_SHIFT 7
tushki7 0:60d829a0353a 8446 /* CONTROL Bit Fields */
tushki7 0:60d829a0353a 8447 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
tushki7 0:60d829a0353a 8448 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
tushki7 0:60d829a0353a 8449 /* USBTRC0 Bit Fields */
tushki7 0:60d829a0353a 8450 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
tushki7 0:60d829a0353a 8451 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
tushki7 0:60d829a0353a 8452 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
tushki7 0:60d829a0353a 8453 #define USB_USBTRC0_SYNC_DET_SHIFT 1
tushki7 0:60d829a0353a 8454 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
tushki7 0:60d829a0353a 8455 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
tushki7 0:60d829a0353a 8456 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
tushki7 0:60d829a0353a 8457 #define USB_USBTRC0_USBRESMEN_SHIFT 5
tushki7 0:60d829a0353a 8458 #define USB_USBTRC0_USBRESET_MASK 0x80u
tushki7 0:60d829a0353a 8459 #define USB_USBTRC0_USBRESET_SHIFT 7
tushki7 0:60d829a0353a 8460 /* USBFRMADJUST Bit Fields */
tushki7 0:60d829a0353a 8461 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
tushki7 0:60d829a0353a 8462 #define USB_USBFRMADJUST_ADJ_SHIFT 0
tushki7 0:60d829a0353a 8463 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
tushki7 0:60d829a0353a 8464 /* CLK_RECOVER_CTRL Bit Fields */
tushki7 0:60d829a0353a 8465 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
tushki7 0:60d829a0353a 8466 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
tushki7 0:60d829a0353a 8467 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
tushki7 0:60d829a0353a 8468 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
tushki7 0:60d829a0353a 8469 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
tushki7 0:60d829a0353a 8470 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
tushki7 0:60d829a0353a 8471 /* CLK_RECOVER_IRC_EN Bit Fields */
tushki7 0:60d829a0353a 8472 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
tushki7 0:60d829a0353a 8473 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
tushki7 0:60d829a0353a 8474 /* CLK_RECOVER_INT_EN Bit Fields */
tushki7 0:60d829a0353a 8475 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
tushki7 0:60d829a0353a 8476 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
tushki7 0:60d829a0353a 8477 /* CLK_RECOVER_INT_STATUS Bit Fields */
tushki7 0:60d829a0353a 8478 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
tushki7 0:60d829a0353a 8479 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
tushki7 0:60d829a0353a 8480
tushki7 0:60d829a0353a 8481 /*!
tushki7 0:60d829a0353a 8482 * @}
tushki7 0:60d829a0353a 8483 */ /* end of group USB_Register_Masks */
tushki7 0:60d829a0353a 8484
tushki7 0:60d829a0353a 8485
tushki7 0:60d829a0353a 8486 /* USB - Peripheral instance base addresses */
tushki7 0:60d829a0353a 8487 /** Peripheral USB0 base address */
tushki7 0:60d829a0353a 8488 #define USB0_BASE (0x40072000u)
tushki7 0:60d829a0353a 8489 /** Peripheral USB0 base pointer */
tushki7 0:60d829a0353a 8490 #define USB0 ((USB_Type *)USB0_BASE)
tushki7 0:60d829a0353a 8491 #define USB0_BASE_PTR (USB0)
tushki7 0:60d829a0353a 8492 /** Array initializer of USB peripheral base addresses */
tushki7 0:60d829a0353a 8493 #define USB_BASE_ADDRS { USB0_BASE }
tushki7 0:60d829a0353a 8494 /** Array initializer of USB peripheral base pointers */
tushki7 0:60d829a0353a 8495 #define USB_BASE_PTRS { USB0 }
tushki7 0:60d829a0353a 8496 /** Interrupt vectors for the USB peripheral type */
tushki7 0:60d829a0353a 8497 #define USB_IRQS { USB0_IRQn }
tushki7 0:60d829a0353a 8498
tushki7 0:60d829a0353a 8499 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8500 -- USB - Register accessor macros
tushki7 0:60d829a0353a 8501 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8502
tushki7 0:60d829a0353a 8503 /*!
tushki7 0:60d829a0353a 8504 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
tushki7 0:60d829a0353a 8505 * @{
tushki7 0:60d829a0353a 8506 */
tushki7 0:60d829a0353a 8507
tushki7 0:60d829a0353a 8508
tushki7 0:60d829a0353a 8509 /* USB - Register instance definitions */
tushki7 0:60d829a0353a 8510 /* USB0 */
tushki7 0:60d829a0353a 8511 #define USB0_PERID USB_PERID_REG(USB0)
tushki7 0:60d829a0353a 8512 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
tushki7 0:60d829a0353a 8513 #define USB0_REV USB_REV_REG(USB0)
tushki7 0:60d829a0353a 8514 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
tushki7 0:60d829a0353a 8515 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
tushki7 0:60d829a0353a 8516 #define USB0_ISTAT USB_ISTAT_REG(USB0)
tushki7 0:60d829a0353a 8517 #define USB0_INTEN USB_INTEN_REG(USB0)
tushki7 0:60d829a0353a 8518 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
tushki7 0:60d829a0353a 8519 #define USB0_ERREN USB_ERREN_REG(USB0)
tushki7 0:60d829a0353a 8520 #define USB0_STAT USB_STAT_REG(USB0)
tushki7 0:60d829a0353a 8521 #define USB0_CTL USB_CTL_REG(USB0)
tushki7 0:60d829a0353a 8522 #define USB0_ADDR USB_ADDR_REG(USB0)
tushki7 0:60d829a0353a 8523 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
tushki7 0:60d829a0353a 8524 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
tushki7 0:60d829a0353a 8525 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
tushki7 0:60d829a0353a 8526 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
tushki7 0:60d829a0353a 8527 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
tushki7 0:60d829a0353a 8528 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
tushki7 0:60d829a0353a 8529 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
tushki7 0:60d829a0353a 8530 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
tushki7 0:60d829a0353a 8531 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
tushki7 0:60d829a0353a 8532 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
tushki7 0:60d829a0353a 8533 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
tushki7 0:60d829a0353a 8534 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
tushki7 0:60d829a0353a 8535 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
tushki7 0:60d829a0353a 8536 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
tushki7 0:60d829a0353a 8537 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
tushki7 0:60d829a0353a 8538 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
tushki7 0:60d829a0353a 8539 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
tushki7 0:60d829a0353a 8540 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
tushki7 0:60d829a0353a 8541 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
tushki7 0:60d829a0353a 8542 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
tushki7 0:60d829a0353a 8543 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
tushki7 0:60d829a0353a 8544 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
tushki7 0:60d829a0353a 8545 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
tushki7 0:60d829a0353a 8546 #define USB0_CONTROL USB_CONTROL_REG(USB0)
tushki7 0:60d829a0353a 8547 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
tushki7 0:60d829a0353a 8548 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
tushki7 0:60d829a0353a 8549 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
tushki7 0:60d829a0353a 8550 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
tushki7 0:60d829a0353a 8551 #define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
tushki7 0:60d829a0353a 8552 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
tushki7 0:60d829a0353a 8553
tushki7 0:60d829a0353a 8554 /* USB - Register array accessors */
tushki7 0:60d829a0353a 8555 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
tushki7 0:60d829a0353a 8556
tushki7 0:60d829a0353a 8557 /*!
tushki7 0:60d829a0353a 8558 * @}
tushki7 0:60d829a0353a 8559 */ /* end of group USB_Register_Accessor_Macros */
tushki7 0:60d829a0353a 8560
tushki7 0:60d829a0353a 8561
tushki7 0:60d829a0353a 8562 /*!
tushki7 0:60d829a0353a 8563 * @}
tushki7 0:60d829a0353a 8564 */ /* end of group USB_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 8565
tushki7 0:60d829a0353a 8566
tushki7 0:60d829a0353a 8567 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8568 -- VREF Peripheral Access Layer
tushki7 0:60d829a0353a 8569 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8570
tushki7 0:60d829a0353a 8571 /*!
tushki7 0:60d829a0353a 8572 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
tushki7 0:60d829a0353a 8573 * @{
tushki7 0:60d829a0353a 8574 */
tushki7 0:60d829a0353a 8575
tushki7 0:60d829a0353a 8576 /** VREF - Register Layout Typedef */
tushki7 0:60d829a0353a 8577 typedef struct {
tushki7 0:60d829a0353a 8578 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
tushki7 0:60d829a0353a 8579 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
tushki7 0:60d829a0353a 8580 } VREF_Type, *VREF_MemMapPtr;
tushki7 0:60d829a0353a 8581
tushki7 0:60d829a0353a 8582 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8583 -- VREF - Register accessor macros
tushki7 0:60d829a0353a 8584 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8585
tushki7 0:60d829a0353a 8586 /*!
tushki7 0:60d829a0353a 8587 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
tushki7 0:60d829a0353a 8588 * @{
tushki7 0:60d829a0353a 8589 */
tushki7 0:60d829a0353a 8590
tushki7 0:60d829a0353a 8591
tushki7 0:60d829a0353a 8592 /* VREF - Register accessors */
tushki7 0:60d829a0353a 8593 #define VREF_TRM_REG(base) ((base)->TRM)
tushki7 0:60d829a0353a 8594 #define VREF_SC_REG(base) ((base)->SC)
tushki7 0:60d829a0353a 8595
tushki7 0:60d829a0353a 8596 /*!
tushki7 0:60d829a0353a 8597 * @}
tushki7 0:60d829a0353a 8598 */ /* end of group VREF_Register_Accessor_Macros */
tushki7 0:60d829a0353a 8599
tushki7 0:60d829a0353a 8600
tushki7 0:60d829a0353a 8601 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8602 -- VREF Register Masks
tushki7 0:60d829a0353a 8603 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8604
tushki7 0:60d829a0353a 8605 /*!
tushki7 0:60d829a0353a 8606 * @addtogroup VREF_Register_Masks VREF Register Masks
tushki7 0:60d829a0353a 8607 * @{
tushki7 0:60d829a0353a 8608 */
tushki7 0:60d829a0353a 8609
tushki7 0:60d829a0353a 8610 /* TRM Bit Fields */
tushki7 0:60d829a0353a 8611 #define VREF_TRM_TRIM_MASK 0x3Fu
tushki7 0:60d829a0353a 8612 #define VREF_TRM_TRIM_SHIFT 0
tushki7 0:60d829a0353a 8613 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
tushki7 0:60d829a0353a 8614 #define VREF_TRM_CHOPEN_MASK 0x40u
tushki7 0:60d829a0353a 8615 #define VREF_TRM_CHOPEN_SHIFT 6
tushki7 0:60d829a0353a 8616 /* SC Bit Fields */
tushki7 0:60d829a0353a 8617 #define VREF_SC_MODE_LV_MASK 0x3u
tushki7 0:60d829a0353a 8618 #define VREF_SC_MODE_LV_SHIFT 0
tushki7 0:60d829a0353a 8619 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
tushki7 0:60d829a0353a 8620 #define VREF_SC_VREFST_MASK 0x4u
tushki7 0:60d829a0353a 8621 #define VREF_SC_VREFST_SHIFT 2
tushki7 0:60d829a0353a 8622 #define VREF_SC_ICOMPEN_MASK 0x20u
tushki7 0:60d829a0353a 8623 #define VREF_SC_ICOMPEN_SHIFT 5
tushki7 0:60d829a0353a 8624 #define VREF_SC_REGEN_MASK 0x40u
tushki7 0:60d829a0353a 8625 #define VREF_SC_REGEN_SHIFT 6
tushki7 0:60d829a0353a 8626 #define VREF_SC_VREFEN_MASK 0x80u
tushki7 0:60d829a0353a 8627 #define VREF_SC_VREFEN_SHIFT 7
tushki7 0:60d829a0353a 8628
tushki7 0:60d829a0353a 8629 /*!
tushki7 0:60d829a0353a 8630 * @}
tushki7 0:60d829a0353a 8631 */ /* end of group VREF_Register_Masks */
tushki7 0:60d829a0353a 8632
tushki7 0:60d829a0353a 8633
tushki7 0:60d829a0353a 8634 /* VREF - Peripheral instance base addresses */
tushki7 0:60d829a0353a 8635 /** Peripheral VREF base address */
tushki7 0:60d829a0353a 8636 #define VREF_BASE (0x40074000u)
tushki7 0:60d829a0353a 8637 /** Peripheral VREF base pointer */
tushki7 0:60d829a0353a 8638 #define VREF ((VREF_Type *)VREF_BASE)
tushki7 0:60d829a0353a 8639 #define VREF_BASE_PTR (VREF)
tushki7 0:60d829a0353a 8640 /** Array initializer of VREF peripheral base addresses */
tushki7 0:60d829a0353a 8641 #define VREF_BASE_ADDRS { VREF_BASE }
tushki7 0:60d829a0353a 8642 /** Array initializer of VREF peripheral base pointers */
tushki7 0:60d829a0353a 8643 #define VREF_BASE_PTRS { VREF }
tushki7 0:60d829a0353a 8644
tushki7 0:60d829a0353a 8645 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8646 -- VREF - Register accessor macros
tushki7 0:60d829a0353a 8647 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8648
tushki7 0:60d829a0353a 8649 /*!
tushki7 0:60d829a0353a 8650 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
tushki7 0:60d829a0353a 8651 * @{
tushki7 0:60d829a0353a 8652 */
tushki7 0:60d829a0353a 8653
tushki7 0:60d829a0353a 8654
tushki7 0:60d829a0353a 8655 /* VREF - Register instance definitions */
tushki7 0:60d829a0353a 8656 /* VREF */
tushki7 0:60d829a0353a 8657 #define VREF_TRM VREF_TRM_REG(VREF)
tushki7 0:60d829a0353a 8658 #define VREF_SC VREF_SC_REG(VREF)
tushki7 0:60d829a0353a 8659
tushki7 0:60d829a0353a 8660 /*!
tushki7 0:60d829a0353a 8661 * @}
tushki7 0:60d829a0353a 8662 */ /* end of group VREF_Register_Accessor_Macros */
tushki7 0:60d829a0353a 8663
tushki7 0:60d829a0353a 8664
tushki7 0:60d829a0353a 8665 /*!
tushki7 0:60d829a0353a 8666 * @}
tushki7 0:60d829a0353a 8667 */ /* end of group VREF_Peripheral_Access_Layer */
tushki7 0:60d829a0353a 8668
tushki7 0:60d829a0353a 8669
tushki7 0:60d829a0353a 8670 /*
tushki7 0:60d829a0353a 8671 ** End of section using anonymous unions
tushki7 0:60d829a0353a 8672 */
tushki7 0:60d829a0353a 8673
tushki7 0:60d829a0353a 8674 #if defined(__ARMCC_VERSION)
tushki7 0:60d829a0353a 8675 #pragma pop
tushki7 0:60d829a0353a 8676 #elif defined(__CWCC__)
tushki7 0:60d829a0353a 8677 #pragma pop
tushki7 0:60d829a0353a 8678 #elif defined(__GNUC__)
tushki7 0:60d829a0353a 8679 /* leave anonymous unions enabled */
tushki7 0:60d829a0353a 8680 #elif defined(__IAR_SYSTEMS_ICC__)
tushki7 0:60d829a0353a 8681 #pragma language=default
tushki7 0:60d829a0353a 8682 #else
tushki7 0:60d829a0353a 8683 #error Not supported compiler type
tushki7 0:60d829a0353a 8684 #endif
tushki7 0:60d829a0353a 8685
tushki7 0:60d829a0353a 8686 /*!
tushki7 0:60d829a0353a 8687 * @}
tushki7 0:60d829a0353a 8688 */ /* end of group Peripheral_access_layer */
tushki7 0:60d829a0353a 8689
tushki7 0:60d829a0353a 8690
tushki7 0:60d829a0353a 8691 /* ----------------------------------------------------------------------------
tushki7 0:60d829a0353a 8692 -- Backward Compatibility
tushki7 0:60d829a0353a 8693 ---------------------------------------------------------------------------- */
tushki7 0:60d829a0353a 8694
tushki7 0:60d829a0353a 8695 /*!
tushki7 0:60d829a0353a 8696 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
tushki7 0:60d829a0353a 8697 * @{
tushki7 0:60d829a0353a 8698 */
tushki7 0:60d829a0353a 8699
tushki7 0:60d829a0353a 8700 #define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK
tushki7 0:60d829a0353a 8701 #define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT
tushki7 0:60d829a0353a 8702 #define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK
tushki7 0:60d829a0353a 8703 #define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT
tushki7 0:60d829a0353a 8704 #define I2C_S1_SRW_MASK I2C_S_SRW_MASK
tushki7 0:60d829a0353a 8705 #define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT
tushki7 0:60d829a0353a 8706 #define I2C_S1_RAM_MASK I2C_S_RAM_MASK
tushki7 0:60d829a0353a 8707 #define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT
tushki7 0:60d829a0353a 8708 #define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK
tushki7 0:60d829a0353a 8709 #define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT
tushki7 0:60d829a0353a 8710 #define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK
tushki7 0:60d829a0353a 8711 #define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT
tushki7 0:60d829a0353a 8712 #define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK
tushki7 0:60d829a0353a 8713 #define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT
tushki7 0:60d829a0353a 8714 #define I2C_S1_TCF_MASK I2C_S_TCF_MASK
tushki7 0:60d829a0353a 8715 #define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT
tushki7 0:60d829a0353a 8716 #define I2C_S1_REG(base) I2C_S_REG(base)
tushki7 0:60d829a0353a 8717 #define I2C0_S1 I2C0_S
tushki7 0:60d829a0353a 8718 #define I2C1_S1 I2C1_S
tushki7 0:60d829a0353a 8719 #define ADC_BASES ADC_BASE_PTRS
tushki7 0:60d829a0353a 8720 #define CMP_BASES CMP_BASE_PTRS
tushki7 0:60d829a0353a 8721 #define DAC_BASES DAC_BASE_PTRS
tushki7 0:60d829a0353a 8722 #define DMA_BASES DMA_BASE_PTRS
tushki7 0:60d829a0353a 8723 #define DMAMUX_BASES DMAMUX_BASE_PTRS
tushki7 0:60d829a0353a 8724 #define FLEXIO_BASES FLEXIO_BASE_PTRS
tushki7 0:60d829a0353a 8725 #define FTFA_BASES FTFA_BASE_PTRS
tushki7 0:60d829a0353a 8726 #define GPIO_BASES GPIO_BASE_PTRS
tushki7 0:60d829a0353a 8727 #define I2C_BASES I2C_BASE_PTRS
tushki7 0:60d829a0353a 8728 #define I2S_BASES I2S_BASE_PTRS
tushki7 0:60d829a0353a 8729 #define LCD_BASES LCD_BASE_PTRS
tushki7 0:60d829a0353a 8730 #define LLWU_BASES LLWU_BASE_PTRS
tushki7 0:60d829a0353a 8731 #define LPTMR_BASES LPTMR_BASE_PTRS
tushki7 0:60d829a0353a 8732 #define LPUART_BASES LPUART_BASE_PTRS
tushki7 0:60d829a0353a 8733 #define MCG_BASES MCG_BASE_PTRS
tushki7 0:60d829a0353a 8734 #define MCM_BASES MCM_BASE_PTRS
tushki7 0:60d829a0353a 8735 #define MTB_BASES MTB_BASE_PTRS
tushki7 0:60d829a0353a 8736 #define MTBDWT_BASES MTBDWT_BASE_PTRS
tushki7 0:60d829a0353a 8737 #define NV_BASES NV_BASE_PTRS
tushki7 0:60d829a0353a 8738 #define OSC_BASES OSC_BASE_PTRS
tushki7 0:60d829a0353a 8739 #define PIT_BASES PIT_BASE_PTRS
tushki7 0:60d829a0353a 8740 #define PMC_BASES PMC_BASE_PTRS
tushki7 0:60d829a0353a 8741 #define PORT_BASES PORT_BASE_PTRS
tushki7 0:60d829a0353a 8742 #define RCM_BASES RCM_BASE_PTRS
tushki7 0:60d829a0353a 8743 #define ROM_BASES ROM_BASE_PTRS
tushki7 0:60d829a0353a 8744 #define RTC_BASES RTC_BASE_PTRS
tushki7 0:60d829a0353a 8745 #define SIM_BASES SIM_BASE_PTRS
tushki7 0:60d829a0353a 8746 #define SMC_BASES SMC_BASE_PTRS
tushki7 0:60d829a0353a 8747 #define SPI_BASES SPI_BASE_PTRS
tushki7 0:60d829a0353a 8748 #define TPM_BASES TPM_BASE_PTRS
tushki7 0:60d829a0353a 8749 #define UART_BASES UART_BASE_PTRS
tushki7 0:60d829a0353a 8750 #define USB_BASES USB_BASE_PTRS
tushki7 0:60d829a0353a 8751 #define VREF_BASES VREF_BASE_PTRS
tushki7 0:60d829a0353a 8752 #define PTA_BASE_PTR GPIOA_BASE_PTR
tushki7 0:60d829a0353a 8753 #define PTB_BASE_PTR GPIOB_BASE_PTR
tushki7 0:60d829a0353a 8754 #define PTC_BASE_PTR GPIOC_BASE_PTR
tushki7 0:60d829a0353a 8755 #define PTD_BASE_PTR GPIOD_BASE_PTR
tushki7 0:60d829a0353a 8756 #define PTE_BASE_PTR GPIOE_BASE_PTR
tushki7 0:60d829a0353a 8757 #define PTA_BASE GPIOA_BASE
tushki7 0:60d829a0353a 8758 #define PTB_BASE GPIOB_BASE
tushki7 0:60d829a0353a 8759 #define PTC_BASE GPIOC_BASE
tushki7 0:60d829a0353a 8760 #define PTD_BASE GPIOD_BASE
tushki7 0:60d829a0353a 8761 #define PTE_BASE GPIOE_BASE
tushki7 0:60d829a0353a 8762 #define PTA GPIOA
tushki7 0:60d829a0353a 8763 #define PTB GPIOB
tushki7 0:60d829a0353a 8764 #define PTC GPIOC
tushki7 0:60d829a0353a 8765 #define PTD GPIOD
tushki7 0:60d829a0353a 8766 #define PTE GPIOE
tushki7 0:60d829a0353a 8767 #define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn
tushki7 0:60d829a0353a 8768 #define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK
tushki7 0:60d829a0353a 8769 #define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT
tushki7 0:60d829a0353a 8770 #define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK
tushki7 0:60d829a0353a 8771 #define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT
tushki7 0:60d829a0353a 8772 #define UART0_BASE UART2_BASE
tushki7 0:60d829a0353a 8773 #define UART0 UART2
tushki7 0:60d829a0353a 8774 #define UART0_BASE_PTR UART2_BASE_PTR
tushki7 0:60d829a0353a 8775 #define UART0_BDH UART2_BDH
tushki7 0:60d829a0353a 8776 #define UART0_BDL UART2_BDL
tushki7 0:60d829a0353a 8777 #define UART0_C1 UART2_C1
tushki7 0:60d829a0353a 8778 #define UART0_C2 UART2_C2
tushki7 0:60d829a0353a 8779 #define UART0_S1 UART2_S1
tushki7 0:60d829a0353a 8780 #define UART0_S2 UART2_S2
tushki7 0:60d829a0353a 8781 #define UART0_C3 UART2_C3
tushki7 0:60d829a0353a 8782 #define UART0_D UART2_D
tushki7 0:60d829a0353a 8783 #define UART0_MA1 UART2_MA1
tushki7 0:60d829a0353a 8784 #define UART0_MA2 UART2_MA2
tushki7 0:60d829a0353a 8785 #define UART0_C4 UART2_C4
tushki7 0:60d829a0353a 8786 #define UART0_C5 UART2_C5
tushki7 0:60d829a0353a 8787 #define UART0_ED UART2_ED
tushki7 0:60d829a0353a 8788 #define UART0_MODEM UART2_MODEM
tushki7 0:60d829a0353a 8789 #define UART0_IR UART2_IR
tushki7 0:60d829a0353a 8790 #define UART0_PFIFO UART2_PFIFO
tushki7 0:60d829a0353a 8791 #define UART0_CFIFO UART2_CFIFO
tushki7 0:60d829a0353a 8792 #define UART0_SFIFO UART2_SFIFO
tushki7 0:60d829a0353a 8793 #define UART0_TWFIFO UART2_TWFIFO
tushki7 0:60d829a0353a 8794 #define UART0_TCFIFO UART2_TCFIFO
tushki7 0:60d829a0353a 8795 #define UART0_RWFIFO UART2_RWFIFO
tushki7 0:60d829a0353a 8796 #define UART0_RCFIFO UART2_RCFIFO
tushki7 0:60d829a0353a 8797 #define UART0_C7816 UART2_C7816
tushki7 0:60d829a0353a 8798 #define UART0_IE7816 UART2_IE7816
tushki7 0:60d829a0353a 8799 #define UART0_IS7816 UART2_IS7816
tushki7 0:60d829a0353a 8800 #define UART0_WP7816 UART2_WP7816
tushki7 0:60d829a0353a 8801 #define UART0_WN7816 UART2_WN7816
tushki7 0:60d829a0353a 8802 #define UART0_WF7816 UART2_WF7816
tushki7 0:60d829a0353a 8803 #define UART0_ET7816 UART2_ET7816
tushki7 0:60d829a0353a 8804 #define UART0_TL7816 UART2_TL7816
tushki7 0:60d829a0353a 8805 #define UART0_AP7816A_T0 UART2_AP7816A_T0
tushki7 0:60d829a0353a 8806 #define UART0_AP7816B_T0 UART2_AP7816B_T0
tushki7 0:60d829a0353a 8807 #define UART0_WP7816A_T0 UART2_WP7816A_T0
tushki7 0:60d829a0353a 8808 #define UART0_WP7816A_T1 UART2_WP7816A_T1
tushki7 0:60d829a0353a 8809 #define UART0_WP7816B_T0 UART2_WP7816B_T0
tushki7 0:60d829a0353a 8810 #define UART0_WP7816B_T1 UART2_WP7816B_T1
tushki7 0:60d829a0353a 8811 #define UART0_WGP7816_T1 UART2_WGP7816_T1
tushki7 0:60d829a0353a 8812 #define UART0_WP7816C_T1 UART2_WP7816C_T1
tushki7 0:60d829a0353a 8813 #define I2S0_MDR This_symb_has_been_deprecated
tushki7 0:60d829a0353a 8814 #define I2S_MDR_DIVIDE_MASK This_symb_has_been_deprecated
tushki7 0:60d829a0353a 8815 #define I2S_MDR_DIVIDE_SHIFT This_symb_has_been_deprecated
tushki7 0:60d829a0353a 8816 #define I2S_MDR_DIVIDE(x) This_symb_has_been_deprecated
tushki7 0:60d829a0353a 8817 #define I2S_MDR_FRACT_MASK This_symb_has_been_deprecated
tushki7 0:60d829a0353a 8818 #define I2S_MDR_FRACT_SHIFT This_symb_has_been_deprecated
tushki7 0:60d829a0353a 8819 #define I2S_MDR_FRACT(x) This_symb_has_been_deprecated
tushki7 0:60d829a0353a 8820 #define I2S_MDR_REG(base) This_symb_has_been_deprecated
tushki7 0:60d829a0353a 8821 #define CTL0 OTGCTL
tushki7 0:60d829a0353a 8822 #define USB0_CTL0 USB0_OTGCTL
tushki7 0:60d829a0353a 8823 #define USB_CTL0_REG(base) USB_OTGCTL_REG(base)
tushki7 0:60d829a0353a 8824 #define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK
tushki7 0:60d829a0353a 8825 #define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT
tushki7 0:60d829a0353a 8826 #define CTL1 CTL
tushki7 0:60d829a0353a 8827 #define USB0_CTL1 USB0_CTL
tushki7 0:60d829a0353a 8828 #define USB_CTL1_REG(base) USB_CTL_REG(base)
tushki7 0:60d829a0353a 8829 #define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK
tushki7 0:60d829a0353a 8830 #define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT
tushki7 0:60d829a0353a 8831 #define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK
tushki7 0:60d829a0353a 8832 #define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT
tushki7 0:60d829a0353a 8833 #define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK
tushki7 0:60d829a0353a 8834 #define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
tushki7 0:60d829a0353a 8835 #define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK
tushki7 0:60d829a0353a 8836 #define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT
tushki7 0:60d829a0353a 8837 #define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK
tushki7 0:60d829a0353a 8838 #define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT
tushki7 0:60d829a0353a 8839 #define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK
tushki7 0:60d829a0353a 8840 #define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT
tushki7 0:60d829a0353a 8841
tushki7 0:60d829a0353a 8842 /*!
tushki7 0:60d829a0353a 8843 * @}
tushki7 0:60d829a0353a 8844 */ /* end of group Backward_Compatibility_Symbols */
tushki7 0:60d829a0353a 8845
tushki7 0:60d829a0353a 8846
tushki7 0:60d829a0353a 8847 #else /* #if !defined(MKL43Z4_H_) */
tushki7 0:60d829a0353a 8848 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
tushki7 0:60d829a0353a 8849 #if (MCU_MEM_MAP_VERSION != 0x0100u)
tushki7 0:60d829a0353a 8850 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
tushki7 0:60d829a0353a 8851 #warning There are included two not compatible versions of memory maps. Please check possible differences.
tushki7 0:60d829a0353a 8852 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
tushki7 0:60d829a0353a 8853 #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
tushki7 0:60d829a0353a 8854 #endif /* #if !defined(MKL43Z4_H_) */
tushki7 0:60d829a0353a 8855
tushki7 0:60d829a0353a 8856 /* MKL43Z4.h, eof. */