Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_NRF51822/nrf51.h@0:60d829a0353a, 2015-04-11 (annotated)

Committer:
tushki7
Date:
Sat Apr 11 04:08:13 2015 +0000
Revision:
0:60d829a0353a
A simple 128x32 LCD program to quickstart with LCD on ARM mbed IoT Starter kit. Mbed Application Shield is required if using FRDM-K64F platform.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
tushki7 0:60d829a0353a 2 *
tushki7 0:60d829a0353a 3 * The information contained herein is property of Nordic Semiconductor ASA.
tushki7 0:60d829a0353a 4 * Terms and conditions of usage are described in detail in NORDIC
tushki7 0:60d829a0353a 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
tushki7 0:60d829a0353a 6 *
tushki7 0:60d829a0353a 7 * Licensees are granted free, non-transferable use of the information. NO
tushki7 0:60d829a0353a 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
tushki7 0:60d829a0353a 9 * the file.
tushki7 0:60d829a0353a 10 *
tushki7 0:60d829a0353a 11 */
tushki7 0:60d829a0353a 12
tushki7 0:60d829a0353a 13
tushki7 0:60d829a0353a 14
tushki7 0:60d829a0353a 15 /** @addtogroup Nordic Semiconductor
tushki7 0:60d829a0353a 16 * @{
tushki7 0:60d829a0353a 17 */
tushki7 0:60d829a0353a 18
tushki7 0:60d829a0353a 19 /** @addtogroup nRF51
tushki7 0:60d829a0353a 20 * @{
tushki7 0:60d829a0353a 21 */
tushki7 0:60d829a0353a 22
tushki7 0:60d829a0353a 23 #ifndef NRF51_H
tushki7 0:60d829a0353a 24 #define NRF51_H
tushki7 0:60d829a0353a 25
tushki7 0:60d829a0353a 26 #ifdef __cplusplus
tushki7 0:60d829a0353a 27 extern "C" {
tushki7 0:60d829a0353a 28 #endif
tushki7 0:60d829a0353a 29
tushki7 0:60d829a0353a 30
tushki7 0:60d829a0353a 31 /* ------------------------- Interrupt Number Definition ------------------------ */
tushki7 0:60d829a0353a 32
tushki7 0:60d829a0353a 33 typedef enum {
tushki7 0:60d829a0353a 34 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
tushki7 0:60d829a0353a 35 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
tushki7 0:60d829a0353a 36 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
tushki7 0:60d829a0353a 37 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
tushki7 0:60d829a0353a 38 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
tushki7 0:60d829a0353a 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
tushki7 0:60d829a0353a 40 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
tushki7 0:60d829a0353a 41 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
tushki7 0:60d829a0353a 42 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
tushki7 0:60d829a0353a 43 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
tushki7 0:60d829a0353a 44 RADIO_IRQn = 1, /*!< 1 RADIO */
tushki7 0:60d829a0353a 45 UART0_IRQn = 2, /*!< 2 UART0 */
tushki7 0:60d829a0353a 46 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
tushki7 0:60d829a0353a 47 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
tushki7 0:60d829a0353a 48 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
tushki7 0:60d829a0353a 49 ADC_IRQn = 7, /*!< 7 ADC */
tushki7 0:60d829a0353a 50 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
tushki7 0:60d829a0353a 51 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
tushki7 0:60d829a0353a 52 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
tushki7 0:60d829a0353a 53 RTC0_IRQn = 11, /*!< 11 RTC0 */
tushki7 0:60d829a0353a 54 TEMP_IRQn = 12, /*!< 12 TEMP */
tushki7 0:60d829a0353a 55 RNG_IRQn = 13, /*!< 13 RNG */
tushki7 0:60d829a0353a 56 ECB_IRQn = 14, /*!< 14 ECB */
tushki7 0:60d829a0353a 57 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
tushki7 0:60d829a0353a 58 WDT_IRQn = 16, /*!< 16 WDT */
tushki7 0:60d829a0353a 59 RTC1_IRQn = 17, /*!< 17 RTC1 */
tushki7 0:60d829a0353a 60 QDEC_IRQn = 18, /*!< 18 QDEC */
tushki7 0:60d829a0353a 61 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
tushki7 0:60d829a0353a 62 SWI0_IRQn = 20, /*!< 20 SWI0 */
tushki7 0:60d829a0353a 63 SWI1_IRQn = 21, /*!< 21 SWI1 */
tushki7 0:60d829a0353a 64 SWI2_IRQn = 22, /*!< 22 SWI2 */
tushki7 0:60d829a0353a 65 SWI3_IRQn = 23, /*!< 23 SWI3 */
tushki7 0:60d829a0353a 66 SWI4_IRQn = 24, /*!< 24 SWI4 */
tushki7 0:60d829a0353a 67 SWI5_IRQn = 25 /*!< 25 SWI5 */
tushki7 0:60d829a0353a 68 } IRQn_Type;
tushki7 0:60d829a0353a 69
tushki7 0:60d829a0353a 70
tushki7 0:60d829a0353a 71 /** @addtogroup Configuration_of_CMSIS
tushki7 0:60d829a0353a 72 * @{
tushki7 0:60d829a0353a 73 */
tushki7 0:60d829a0353a 74
tushki7 0:60d829a0353a 75
tushki7 0:60d829a0353a 76 /* ================================================================================ */
tushki7 0:60d829a0353a 77 /* ================ Processor and Core Peripheral Section ================ */
tushki7 0:60d829a0353a 78 /* ================================================================================ */
tushki7 0:60d829a0353a 79
tushki7 0:60d829a0353a 80 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
tushki7 0:60d829a0353a 81 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
tushki7 0:60d829a0353a 82 #define __MPU_PRESENT 0 /*!< MPU present or not */
tushki7 0:60d829a0353a 83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
tushki7 0:60d829a0353a 84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
tushki7 0:60d829a0353a 85 /** @} */ /* End of group Configuration_of_CMSIS */
tushki7 0:60d829a0353a 86
tushki7 0:60d829a0353a 87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
tushki7 0:60d829a0353a 88 #include "system_nrf51822.h" /*!< nRF51 System */
tushki7 0:60d829a0353a 89
tushki7 0:60d829a0353a 90
tushki7 0:60d829a0353a 91 /* ================================================================================ */
tushki7 0:60d829a0353a 92 /* ================ Device Specific Peripheral Section ================ */
tushki7 0:60d829a0353a 93 /* ================================================================================ */
tushki7 0:60d829a0353a 94
tushki7 0:60d829a0353a 95
tushki7 0:60d829a0353a 96 /** @addtogroup Device_Peripheral_Registers
tushki7 0:60d829a0353a 97 * @{
tushki7 0:60d829a0353a 98 */
tushki7 0:60d829a0353a 99
tushki7 0:60d829a0353a 100
tushki7 0:60d829a0353a 101 /* ------------------- Start of section using anonymous unions ------------------ */
tushki7 0:60d829a0353a 102 #if defined(__CC_ARM)
tushki7 0:60d829a0353a 103 #pragma push
tushki7 0:60d829a0353a 104 #pragma anon_unions
tushki7 0:60d829a0353a 105 #elif defined(__ICCARM__)
tushki7 0:60d829a0353a 106 #pragma language=extended
tushki7 0:60d829a0353a 107 #elif defined(__GNUC__)
tushki7 0:60d829a0353a 108 /* anonymous unions are enabled by default */
tushki7 0:60d829a0353a 109 #elif defined(__TMS470__)
tushki7 0:60d829a0353a 110 /* anonymous unions are enabled by default */
tushki7 0:60d829a0353a 111 #elif defined(__TASKING__)
tushki7 0:60d829a0353a 112 #pragma warning 586
tushki7 0:60d829a0353a 113 #else
tushki7 0:60d829a0353a 114 #warning Not supported compiler type
tushki7 0:60d829a0353a 115 #endif
tushki7 0:60d829a0353a 116
tushki7 0:60d829a0353a 117
tushki7 0:60d829a0353a 118 typedef struct {
tushki7 0:60d829a0353a 119 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
tushki7 0:60d829a0353a 120 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
tushki7 0:60d829a0353a 121 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
tushki7 0:60d829a0353a 122 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
tushki7 0:60d829a0353a 123 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
tushki7 0:60d829a0353a 124 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
tushki7 0:60d829a0353a 125 } AMLI_RAMPRI_Type;
tushki7 0:60d829a0353a 126
tushki7 0:60d829a0353a 127 typedef struct {
tushki7 0:60d829a0353a 128 __O uint32_t EN; /*!< Enable channel group. */
tushki7 0:60d829a0353a 129 __O uint32_t DIS; /*!< Disable channel group. */
tushki7 0:60d829a0353a 130 } PPI_TASKS_CHG_Type;
tushki7 0:60d829a0353a 131
tushki7 0:60d829a0353a 132 typedef struct {
tushki7 0:60d829a0353a 133 __IO uint32_t EEP; /*!< Channel event end-point. */
tushki7 0:60d829a0353a 134 __IO uint32_t TEP; /*!< Channel task end-point. */
tushki7 0:60d829a0353a 135 } PPI_CH_Type;
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137
tushki7 0:60d829a0353a 138 /* ================================================================================ */
tushki7 0:60d829a0353a 139 /* ================ POWER ================ */
tushki7 0:60d829a0353a 140 /* ================================================================================ */
tushki7 0:60d829a0353a 141
tushki7 0:60d829a0353a 142
tushki7 0:60d829a0353a 143 /**
tushki7 0:60d829a0353a 144 * @brief Power Control. (POWER)
tushki7 0:60d829a0353a 145 */
tushki7 0:60d829a0353a 146
tushki7 0:60d829a0353a 147 typedef struct { /*!< POWER Structure */
tushki7 0:60d829a0353a 148 __I uint32_t RESERVED0[30];
tushki7 0:60d829a0353a 149 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
tushki7 0:60d829a0353a 150 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
tushki7 0:60d829a0353a 151 __I uint32_t RESERVED1[34];
tushki7 0:60d829a0353a 152 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
tushki7 0:60d829a0353a 153 __I uint32_t RESERVED2[126];
tushki7 0:60d829a0353a 154 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 155 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 156 __I uint32_t RESERVED3[61];
tushki7 0:60d829a0353a 157 __IO uint32_t RESETREAS; /*!< Reset reason. */
tushki7 0:60d829a0353a 158 __I uint32_t RESERVED4[63];
tushki7 0:60d829a0353a 159 __O uint32_t SYSTEMOFF; /*!< System off register. */
tushki7 0:60d829a0353a 160 __I uint32_t RESERVED5[3];
tushki7 0:60d829a0353a 161 __IO uint32_t POFCON; /*!< Power failure configuration. */
tushki7 0:60d829a0353a 162 __I uint32_t RESERVED6[2];
tushki7 0:60d829a0353a 163 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
tushki7 0:60d829a0353a 164 register. */
tushki7 0:60d829a0353a 165 __I uint32_t RESERVED7;
tushki7 0:60d829a0353a 166 __IO uint32_t RAMON; /*!< Ram on/off. */
tushki7 0:60d829a0353a 167 __I uint32_t RESERVED8[7];
tushki7 0:60d829a0353a 168 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
tushki7 0:60d829a0353a 169 is a retained register. */
tushki7 0:60d829a0353a 170 __I uint32_t RESERVED9[12];
tushki7 0:60d829a0353a 171 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
tushki7 0:60d829a0353a 172 } NRF_POWER_Type;
tushki7 0:60d829a0353a 173
tushki7 0:60d829a0353a 174
tushki7 0:60d829a0353a 175 /* ================================================================================ */
tushki7 0:60d829a0353a 176 /* ================ CLOCK ================ */
tushki7 0:60d829a0353a 177 /* ================================================================================ */
tushki7 0:60d829a0353a 178
tushki7 0:60d829a0353a 179
tushki7 0:60d829a0353a 180 /**
tushki7 0:60d829a0353a 181 * @brief Clock control. (CLOCK)
tushki7 0:60d829a0353a 182 */
tushki7 0:60d829a0353a 183
tushki7 0:60d829a0353a 184 typedef struct { /*!< CLOCK Structure */
tushki7 0:60d829a0353a 185 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
tushki7 0:60d829a0353a 186 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
tushki7 0:60d829a0353a 187 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
tushki7 0:60d829a0353a 188 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
tushki7 0:60d829a0353a 189 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
tushki7 0:60d829a0353a 190 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
tushki7 0:60d829a0353a 191 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
tushki7 0:60d829a0353a 192 __I uint32_t RESERVED0[57];
tushki7 0:60d829a0353a 193 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
tushki7 0:60d829a0353a 194 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
tushki7 0:60d829a0353a 195 __I uint32_t RESERVED1;
tushki7 0:60d829a0353a 196 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
tushki7 0:60d829a0353a 197 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
tushki7 0:60d829a0353a 198 __I uint32_t RESERVED2[124];
tushki7 0:60d829a0353a 199 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 200 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 201 __I uint32_t RESERVED3[64];
tushki7 0:60d829a0353a 202 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
tushki7 0:60d829a0353a 203 __I uint32_t RESERVED4[2];
tushki7 0:60d829a0353a 204 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
tushki7 0:60d829a0353a 205 __I uint32_t RESERVED5[63];
tushki7 0:60d829a0353a 206 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
tushki7 0:60d829a0353a 207 __I uint32_t RESERVED6[7];
tushki7 0:60d829a0353a 208 __IO uint32_t CTIV; /*!< Calibration timer interval. */
tushki7 0:60d829a0353a 209 __I uint32_t RESERVED7[5];
tushki7 0:60d829a0353a 210 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
tushki7 0:60d829a0353a 211 } NRF_CLOCK_Type;
tushki7 0:60d829a0353a 212
tushki7 0:60d829a0353a 213
tushki7 0:60d829a0353a 214 /* ================================================================================ */
tushki7 0:60d829a0353a 215 /* ================ MPU ================ */
tushki7 0:60d829a0353a 216 /* ================================================================================ */
tushki7 0:60d829a0353a 217
tushki7 0:60d829a0353a 218
tushki7 0:60d829a0353a 219 /**
tushki7 0:60d829a0353a 220 * @brief Memory Protection Unit. (MPU)
tushki7 0:60d829a0353a 221 */
tushki7 0:60d829a0353a 222
tushki7 0:60d829a0353a 223 typedef struct { /*!< MPU Structure */
tushki7 0:60d829a0353a 224 __I uint32_t RESERVED0[330];
tushki7 0:60d829a0353a 225 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
tushki7 0:60d829a0353a 226 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
tushki7 0:60d829a0353a 227 __I uint32_t RESERVED1[52];
tushki7 0:60d829a0353a 228 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
tushki7 0:60d829a0353a 229 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
tushki7 0:60d829a0353a 230 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
tushki7 0:60d829a0353a 231 } NRF_MPU_Type;
tushki7 0:60d829a0353a 232
tushki7 0:60d829a0353a 233
tushki7 0:60d829a0353a 234 /* ================================================================================ */
tushki7 0:60d829a0353a 235 /* ================ PU ================ */
tushki7 0:60d829a0353a 236 /* ================================================================================ */
tushki7 0:60d829a0353a 237
tushki7 0:60d829a0353a 238
tushki7 0:60d829a0353a 239 /**
tushki7 0:60d829a0353a 240 * @brief Patch unit. (PU)
tushki7 0:60d829a0353a 241 */
tushki7 0:60d829a0353a 242
tushki7 0:60d829a0353a 243 typedef struct { /*!< PU Structure */
tushki7 0:60d829a0353a 244 __I uint32_t RESERVED0[448];
tushki7 0:60d829a0353a 245 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
tushki7 0:60d829a0353a 246 __I uint32_t RESERVED1[24];
tushki7 0:60d829a0353a 247 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
tushki7 0:60d829a0353a 248 __I uint32_t RESERVED2[24];
tushki7 0:60d829a0353a 249 __IO uint32_t PATCHEN; /*!< Patch enable register. */
tushki7 0:60d829a0353a 250 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
tushki7 0:60d829a0353a 251 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
tushki7 0:60d829a0353a 252 } NRF_PU_Type;
tushki7 0:60d829a0353a 253
tushki7 0:60d829a0353a 254
tushki7 0:60d829a0353a 255 /* ================================================================================ */
tushki7 0:60d829a0353a 256 /* ================ AMLI ================ */
tushki7 0:60d829a0353a 257 /* ================================================================================ */
tushki7 0:60d829a0353a 258
tushki7 0:60d829a0353a 259
tushki7 0:60d829a0353a 260 /**
tushki7 0:60d829a0353a 261 * @brief AHB Multi-Layer Interface. (AMLI)
tushki7 0:60d829a0353a 262 */
tushki7 0:60d829a0353a 263
tushki7 0:60d829a0353a 264 typedef struct { /*!< AMLI Structure */
tushki7 0:60d829a0353a 265 __I uint32_t RESERVED0[896];
tushki7 0:60d829a0353a 266 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
tushki7 0:60d829a0353a 267 } NRF_AMLI_Type;
tushki7 0:60d829a0353a 268
tushki7 0:60d829a0353a 269
tushki7 0:60d829a0353a 270 /* ================================================================================ */
tushki7 0:60d829a0353a 271 /* ================ RADIO ================ */
tushki7 0:60d829a0353a 272 /* ================================================================================ */
tushki7 0:60d829a0353a 273
tushki7 0:60d829a0353a 274
tushki7 0:60d829a0353a 275 /**
tushki7 0:60d829a0353a 276 * @brief The radio. (RADIO)
tushki7 0:60d829a0353a 277 */
tushki7 0:60d829a0353a 278
tushki7 0:60d829a0353a 279 typedef struct { /*!< RADIO Structure */
tushki7 0:60d829a0353a 280 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
tushki7 0:60d829a0353a 281 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
tushki7 0:60d829a0353a 282 __O uint32_t TASKS_START; /*!< Start radio. */
tushki7 0:60d829a0353a 283 __O uint32_t TASKS_STOP; /*!< Stop radio. */
tushki7 0:60d829a0353a 284 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
tushki7 0:60d829a0353a 285 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
tushki7 0:60d829a0353a 286 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
tushki7 0:60d829a0353a 287 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
tushki7 0:60d829a0353a 288 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
tushki7 0:60d829a0353a 289 __I uint32_t RESERVED0[55];
tushki7 0:60d829a0353a 290 __IO uint32_t EVENTS_READY; /*!< Ready event. */
tushki7 0:60d829a0353a 291 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
tushki7 0:60d829a0353a 292 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
tushki7 0:60d829a0353a 293 __IO uint32_t EVENTS_END; /*!< End event. */
tushki7 0:60d829a0353a 294 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
tushki7 0:60d829a0353a 295 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
tushki7 0:60d829a0353a 296 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
tushki7 0:60d829a0353a 297 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
tushki7 0:60d829a0353a 298 sample is ready for readout at the RSSISAMPLE register. */
tushki7 0:60d829a0353a 299 __I uint32_t RESERVED1[2];
tushki7 0:60d829a0353a 300 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
tushki7 0:60d829a0353a 301 __I uint32_t RESERVED2[53];
tushki7 0:60d829a0353a 302 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
tushki7 0:60d829a0353a 303 __I uint32_t RESERVED3[64];
tushki7 0:60d829a0353a 304 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 305 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 306 __I uint32_t RESERVED4[61];
tushki7 0:60d829a0353a 307 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
tushki7 0:60d829a0353a 308 __I uint32_t RESERVED5;
tushki7 0:60d829a0353a 309 __I uint32_t RXMATCH; /*!< Received address. */
tushki7 0:60d829a0353a 310 __I uint32_t RXCRC; /*!< Received CRC. */
tushki7 0:60d829a0353a 311 __IO uint32_t DAI; /*!< Device address match index. */
tushki7 0:60d829a0353a 312 __I uint32_t RESERVED6[60];
tushki7 0:60d829a0353a 313 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
tushki7 0:60d829a0353a 314 __IO uint32_t FREQUENCY; /*!< Frequency. */
tushki7 0:60d829a0353a 315 __IO uint32_t TXPOWER; /*!< Output power. */
tushki7 0:60d829a0353a 316 __IO uint32_t MODE; /*!< Data rate and modulation. */
tushki7 0:60d829a0353a 317 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
tushki7 0:60d829a0353a 318 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
tushki7 0:60d829a0353a 319 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
tushki7 0:60d829a0353a 320 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
tushki7 0:60d829a0353a 321 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
tushki7 0:60d829a0353a 322 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
tushki7 0:60d829a0353a 323 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
tushki7 0:60d829a0353a 324 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
tushki7 0:60d829a0353a 325 __IO uint32_t CRCCNF; /*!< CRC configuration. */
tushki7 0:60d829a0353a 326 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
tushki7 0:60d829a0353a 327 __IO uint32_t CRCINIT; /*!< CRC initial value. */
tushki7 0:60d829a0353a 328 __IO uint32_t TEST; /*!< Test features enable register. */
tushki7 0:60d829a0353a 329 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
tushki7 0:60d829a0353a 330 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
tushki7 0:60d829a0353a 331 __I uint32_t RESERVED7;
tushki7 0:60d829a0353a 332 __I uint32_t STATE; /*!< Current radio state. */
tushki7 0:60d829a0353a 333 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
tushki7 0:60d829a0353a 334 __I uint32_t RESERVED8[2];
tushki7 0:60d829a0353a 335 __IO uint32_t BCC; /*!< Bit counter compare. */
tushki7 0:60d829a0353a 336 __I uint32_t RESERVED9[39];
tushki7 0:60d829a0353a 337 __IO uint32_t DAB[8]; /*!< Device address base segment. */
tushki7 0:60d829a0353a 338 __IO uint32_t DAP[8]; /*!< Device address prefix. */
tushki7 0:60d829a0353a 339 __IO uint32_t DACNF; /*!< Device address match configuration. */
tushki7 0:60d829a0353a 340 __I uint32_t RESERVED10[56];
tushki7 0:60d829a0353a 341 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
tushki7 0:60d829a0353a 342 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
tushki7 0:60d829a0353a 343 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
tushki7 0:60d829a0353a 344 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
tushki7 0:60d829a0353a 345 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
tushki7 0:60d829a0353a 346 __I uint32_t RESERVED11[561];
tushki7 0:60d829a0353a 347 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 348 } NRF_RADIO_Type;
tushki7 0:60d829a0353a 349
tushki7 0:60d829a0353a 350
tushki7 0:60d829a0353a 351 /* ================================================================================ */
tushki7 0:60d829a0353a 352 /* ================ UART ================ */
tushki7 0:60d829a0353a 353 /* ================================================================================ */
tushki7 0:60d829a0353a 354
tushki7 0:60d829a0353a 355
tushki7 0:60d829a0353a 356 /**
tushki7 0:60d829a0353a 357 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
tushki7 0:60d829a0353a 358 */
tushki7 0:60d829a0353a 359
tushki7 0:60d829a0353a 360 typedef struct { /*!< UART Structure */
tushki7 0:60d829a0353a 361 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
tushki7 0:60d829a0353a 362 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
tushki7 0:60d829a0353a 363 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
tushki7 0:60d829a0353a 364 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
tushki7 0:60d829a0353a 365 __I uint32_t RESERVED0[3];
tushki7 0:60d829a0353a 366 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
tushki7 0:60d829a0353a 367 __I uint32_t RESERVED1[56];
tushki7 0:60d829a0353a 368 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
tushki7 0:60d829a0353a 369 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
tushki7 0:60d829a0353a 370 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
tushki7 0:60d829a0353a 371 __I uint32_t RESERVED2[4];
tushki7 0:60d829a0353a 372 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
tushki7 0:60d829a0353a 373 __I uint32_t RESERVED3;
tushki7 0:60d829a0353a 374 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
tushki7 0:60d829a0353a 375 __I uint32_t RESERVED4[7];
tushki7 0:60d829a0353a 376 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
tushki7 0:60d829a0353a 377 __I uint32_t RESERVED5[46];
tushki7 0:60d829a0353a 378 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
tushki7 0:60d829a0353a 379 __I uint32_t RESERVED6[63];
tushki7 0:60d829a0353a 380 __IO uint32_t INTEN; /*!< Interrupt enable register. */
tushki7 0:60d829a0353a 381 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 382 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 383 __I uint32_t RESERVED7[93];
tushki7 0:60d829a0353a 384 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
tushki7 0:60d829a0353a 385 __I uint32_t RESERVED8[31];
tushki7 0:60d829a0353a 386 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
tushki7 0:60d829a0353a 387 __I uint32_t RESERVED9;
tushki7 0:60d829a0353a 388 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
tushki7 0:60d829a0353a 389 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
tushki7 0:60d829a0353a 390 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
tushki7 0:60d829a0353a 391 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
tushki7 0:60d829a0353a 392 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
tushki7 0:60d829a0353a 393 Once read the character is consummed. If read when no character
tushki7 0:60d829a0353a 394 available, the UART will stop working. */
tushki7 0:60d829a0353a 395 __O uint32_t TXD; /*!< TXD register. */
tushki7 0:60d829a0353a 396 __I uint32_t RESERVED10;
tushki7 0:60d829a0353a 397 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
tushki7 0:60d829a0353a 398 __I uint32_t RESERVED11[17];
tushki7 0:60d829a0353a 399 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
tushki7 0:60d829a0353a 400 __I uint32_t RESERVED12[675];
tushki7 0:60d829a0353a 401 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 402 } NRF_UART_Type;
tushki7 0:60d829a0353a 403
tushki7 0:60d829a0353a 404
tushki7 0:60d829a0353a 405 /* ================================================================================ */
tushki7 0:60d829a0353a 406 /* ================ SPI ================ */
tushki7 0:60d829a0353a 407 /* ================================================================================ */
tushki7 0:60d829a0353a 408
tushki7 0:60d829a0353a 409
tushki7 0:60d829a0353a 410 /**
tushki7 0:60d829a0353a 411 * @brief SPI master 0. (SPI)
tushki7 0:60d829a0353a 412 */
tushki7 0:60d829a0353a 413
tushki7 0:60d829a0353a 414 typedef struct { /*!< SPI Structure */
tushki7 0:60d829a0353a 415 __I uint32_t RESERVED0[66];
tushki7 0:60d829a0353a 416 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
tushki7 0:60d829a0353a 417 __I uint32_t RESERVED1[126];
tushki7 0:60d829a0353a 418 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 419 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 420 __I uint32_t RESERVED2[125];
tushki7 0:60d829a0353a 421 __IO uint32_t ENABLE; /*!< Enable SPI. */
tushki7 0:60d829a0353a 422 __I uint32_t RESERVED3;
tushki7 0:60d829a0353a 423 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
tushki7 0:60d829a0353a 424 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
tushki7 0:60d829a0353a 425 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
tushki7 0:60d829a0353a 426 __I uint32_t RESERVED4;
tushki7 0:60d829a0353a 427 __IO uint32_t RXD; /*!< RX data. */
tushki7 0:60d829a0353a 428 __IO uint32_t TXD; /*!< TX data. */
tushki7 0:60d829a0353a 429 __I uint32_t RESERVED5;
tushki7 0:60d829a0353a 430 __IO uint32_t FREQUENCY; /*!< SPI frequency */
tushki7 0:60d829a0353a 431 __I uint32_t RESERVED6[11];
tushki7 0:60d829a0353a 432 __IO uint32_t CONFIG; /*!< Configuration register. */
tushki7 0:60d829a0353a 433 __I uint32_t RESERVED7[681];
tushki7 0:60d829a0353a 434 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 435 } NRF_SPI_Type;
tushki7 0:60d829a0353a 436
tushki7 0:60d829a0353a 437
tushki7 0:60d829a0353a 438 /* ================================================================================ */
tushki7 0:60d829a0353a 439 /* ================ TWI ================ */
tushki7 0:60d829a0353a 440 /* ================================================================================ */
tushki7 0:60d829a0353a 441
tushki7 0:60d829a0353a 442
tushki7 0:60d829a0353a 443 /**
tushki7 0:60d829a0353a 444 * @brief Two-wire interface master 0. (TWI)
tushki7 0:60d829a0353a 445 */
tushki7 0:60d829a0353a 446
tushki7 0:60d829a0353a 447 typedef struct { /*!< TWI Structure */
tushki7 0:60d829a0353a 448 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
tushki7 0:60d829a0353a 449 __I uint32_t RESERVED0;
tushki7 0:60d829a0353a 450 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
tushki7 0:60d829a0353a 451 __I uint32_t RESERVED1[2];
tushki7 0:60d829a0353a 452 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
tushki7 0:60d829a0353a 453 __I uint32_t RESERVED2;
tushki7 0:60d829a0353a 454 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
tushki7 0:60d829a0353a 455 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
tushki7 0:60d829a0353a 456 __I uint32_t RESERVED3[56];
tushki7 0:60d829a0353a 457 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
tushki7 0:60d829a0353a 458 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
tushki7 0:60d829a0353a 459 __I uint32_t RESERVED4[4];
tushki7 0:60d829a0353a 460 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
tushki7 0:60d829a0353a 461 __I uint32_t RESERVED5;
tushki7 0:60d829a0353a 462 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
tushki7 0:60d829a0353a 463 __I uint32_t RESERVED6[4];
tushki7 0:60d829a0353a 464 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
tushki7 0:60d829a0353a 465 __I uint32_t RESERVED7[49];
tushki7 0:60d829a0353a 466 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
tushki7 0:60d829a0353a 467 __I uint32_t RESERVED8[64];
tushki7 0:60d829a0353a 468 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 469 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 470 __I uint32_t RESERVED9[110];
tushki7 0:60d829a0353a 471 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
tushki7 0:60d829a0353a 472 __I uint32_t RESERVED10[14];
tushki7 0:60d829a0353a 473 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
tushki7 0:60d829a0353a 474 __I uint32_t RESERVED11;
tushki7 0:60d829a0353a 475 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
tushki7 0:60d829a0353a 476 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
tushki7 0:60d829a0353a 477 __I uint32_t RESERVED12[2];
tushki7 0:60d829a0353a 478 __IO uint32_t RXD; /*!< RX data register. */
tushki7 0:60d829a0353a 479 __IO uint32_t TXD; /*!< TX data register. */
tushki7 0:60d829a0353a 480 __I uint32_t RESERVED13;
tushki7 0:60d829a0353a 481 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
tushki7 0:60d829a0353a 482 __I uint32_t RESERVED14[24];
tushki7 0:60d829a0353a 483 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
tushki7 0:60d829a0353a 484 __I uint32_t RESERVED15[668];
tushki7 0:60d829a0353a 485 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 486 } NRF_TWI_Type;
tushki7 0:60d829a0353a 487
tushki7 0:60d829a0353a 488
tushki7 0:60d829a0353a 489 /* ================================================================================ */
tushki7 0:60d829a0353a 490 /* ================ SPIS ================ */
tushki7 0:60d829a0353a 491 /* ================================================================================ */
tushki7 0:60d829a0353a 492
tushki7 0:60d829a0353a 493
tushki7 0:60d829a0353a 494 /**
tushki7 0:60d829a0353a 495 * @brief SPI slave 1. (SPIS)
tushki7 0:60d829a0353a 496 */
tushki7 0:60d829a0353a 497
tushki7 0:60d829a0353a 498 typedef struct { /*!< SPIS Structure */
tushki7 0:60d829a0353a 499 __I uint32_t RESERVED0[9];
tushki7 0:60d829a0353a 500 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
tushki7 0:60d829a0353a 501 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
tushki7 0:60d829a0353a 502 __I uint32_t RESERVED1[54];
tushki7 0:60d829a0353a 503 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
tushki7 0:60d829a0353a 504 __I uint32_t RESERVED2[8];
tushki7 0:60d829a0353a 505 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
tushki7 0:60d829a0353a 506 __I uint32_t RESERVED3[53];
tushki7 0:60d829a0353a 507 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
tushki7 0:60d829a0353a 508 __I uint32_t RESERVED4[64];
tushki7 0:60d829a0353a 509 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 510 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 511 __I uint32_t RESERVED5[61];
tushki7 0:60d829a0353a 512 __I uint32_t SEMSTAT; /*!< Semaphore status. */
tushki7 0:60d829a0353a 513 __I uint32_t RESERVED6[15];
tushki7 0:60d829a0353a 514 __IO uint32_t STATUS; /*!< Status from last transaction. */
tushki7 0:60d829a0353a 515 __I uint32_t RESERVED7[47];
tushki7 0:60d829a0353a 516 __IO uint32_t ENABLE; /*!< Enable SPIS. */
tushki7 0:60d829a0353a 517 __I uint32_t RESERVED8;
tushki7 0:60d829a0353a 518 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
tushki7 0:60d829a0353a 519 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
tushki7 0:60d829a0353a 520 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
tushki7 0:60d829a0353a 521 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
tushki7 0:60d829a0353a 522 __I uint32_t RESERVED9[7];
tushki7 0:60d829a0353a 523 __IO uint32_t RXDPTR; /*!< RX data pointer. */
tushki7 0:60d829a0353a 524 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
tushki7 0:60d829a0353a 525 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
tushki7 0:60d829a0353a 526 __I uint32_t RESERVED10;
tushki7 0:60d829a0353a 527 __IO uint32_t TXDPTR; /*!< TX data pointer. */
tushki7 0:60d829a0353a 528 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
tushki7 0:60d829a0353a 529 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
tushki7 0:60d829a0353a 530 __I uint32_t RESERVED11;
tushki7 0:60d829a0353a 531 __IO uint32_t CONFIG; /*!< Configuration register. */
tushki7 0:60d829a0353a 532 __I uint32_t RESERVED12;
tushki7 0:60d829a0353a 533 __IO uint32_t DEF; /*!< Default character. */
tushki7 0:60d829a0353a 534 __I uint32_t RESERVED13[24];
tushki7 0:60d829a0353a 535 __IO uint32_t ORC; /*!< Over-read character. */
tushki7 0:60d829a0353a 536 __I uint32_t RESERVED14[654];
tushki7 0:60d829a0353a 537 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 538 } NRF_SPIS_Type;
tushki7 0:60d829a0353a 539
tushki7 0:60d829a0353a 540
tushki7 0:60d829a0353a 541 /* ================================================================================ */
tushki7 0:60d829a0353a 542 /* ================ GPIOTE ================ */
tushki7 0:60d829a0353a 543 /* ================================================================================ */
tushki7 0:60d829a0353a 544
tushki7 0:60d829a0353a 545
tushki7 0:60d829a0353a 546 /**
tushki7 0:60d829a0353a 547 * @brief GPIO tasks and events. (GPIOTE)
tushki7 0:60d829a0353a 548 */
tushki7 0:60d829a0353a 549
tushki7 0:60d829a0353a 550 typedef struct { /*!< GPIOTE Structure */
tushki7 0:60d829a0353a 551 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
tushki7 0:60d829a0353a 552 __I uint32_t RESERVED0[60];
tushki7 0:60d829a0353a 553 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
tushki7 0:60d829a0353a 554 __I uint32_t RESERVED1[27];
tushki7 0:60d829a0353a 555 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
tushki7 0:60d829a0353a 556 __I uint32_t RESERVED2[97];
tushki7 0:60d829a0353a 557 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 558 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 559 __I uint32_t RESERVED3[129];
tushki7 0:60d829a0353a 560 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
tushki7 0:60d829a0353a 561 __I uint32_t RESERVED4[695];
tushki7 0:60d829a0353a 562 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 563 } NRF_GPIOTE_Type;
tushki7 0:60d829a0353a 564
tushki7 0:60d829a0353a 565
tushki7 0:60d829a0353a 566 /* ================================================================================ */
tushki7 0:60d829a0353a 567 /* ================ ADC ================ */
tushki7 0:60d829a0353a 568 /* ================================================================================ */
tushki7 0:60d829a0353a 569
tushki7 0:60d829a0353a 570
tushki7 0:60d829a0353a 571 /**
tushki7 0:60d829a0353a 572 * @brief Analog to digital converter. (ADC)
tushki7 0:60d829a0353a 573 */
tushki7 0:60d829a0353a 574
tushki7 0:60d829a0353a 575 typedef struct { /*!< ADC Structure */
tushki7 0:60d829a0353a 576 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
tushki7 0:60d829a0353a 577 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
tushki7 0:60d829a0353a 578 __I uint32_t RESERVED0[62];
tushki7 0:60d829a0353a 579 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
tushki7 0:60d829a0353a 580 __I uint32_t RESERVED1[128];
tushki7 0:60d829a0353a 581 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 582 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 583 __I uint32_t RESERVED2[61];
tushki7 0:60d829a0353a 584 __I uint32_t BUSY; /*!< ADC busy register. */
tushki7 0:60d829a0353a 585 __I uint32_t RESERVED3[63];
tushki7 0:60d829a0353a 586 __IO uint32_t ENABLE; /*!< ADC enable. */
tushki7 0:60d829a0353a 587 __IO uint32_t CONFIG; /*!< ADC configuration register. */
tushki7 0:60d829a0353a 588 __I uint32_t RESULT; /*!< Result of ADC conversion. */
tushki7 0:60d829a0353a 589 __I uint32_t RESERVED4[700];
tushki7 0:60d829a0353a 590 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 591 } NRF_ADC_Type;
tushki7 0:60d829a0353a 592
tushki7 0:60d829a0353a 593
tushki7 0:60d829a0353a 594 /* ================================================================================ */
tushki7 0:60d829a0353a 595 /* ================ TIMER ================ */
tushki7 0:60d829a0353a 596 /* ================================================================================ */
tushki7 0:60d829a0353a 597
tushki7 0:60d829a0353a 598
tushki7 0:60d829a0353a 599 /**
tushki7 0:60d829a0353a 600 * @brief Timer 0. (TIMER)
tushki7 0:60d829a0353a 601 */
tushki7 0:60d829a0353a 602
tushki7 0:60d829a0353a 603 typedef struct { /*!< TIMER Structure */
tushki7 0:60d829a0353a 604 __O uint32_t TASKS_START; /*!< Start Timer. */
tushki7 0:60d829a0353a 605 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
tushki7 0:60d829a0353a 606 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
tushki7 0:60d829a0353a 607 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
tushki7 0:60d829a0353a 608 __I uint32_t RESERVED0[12];
tushki7 0:60d829a0353a 609 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
tushki7 0:60d829a0353a 610 __I uint32_t RESERVED1[60];
tushki7 0:60d829a0353a 611 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
tushki7 0:60d829a0353a 612 __I uint32_t RESERVED2[44];
tushki7 0:60d829a0353a 613 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
tushki7 0:60d829a0353a 614 __I uint32_t RESERVED3[64];
tushki7 0:60d829a0353a 615 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 616 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 617 __I uint32_t RESERVED4[126];
tushki7 0:60d829a0353a 618 __IO uint32_t MODE; /*!< Timer Mode selection. */
tushki7 0:60d829a0353a 619 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
tushki7 0:60d829a0353a 620 __I uint32_t RESERVED5;
tushki7 0:60d829a0353a 621 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
tushki7 0:60d829a0353a 622 clock frequency is divided by 2^SCALE. */
tushki7 0:60d829a0353a 623 __I uint32_t RESERVED6[11];
tushki7 0:60d829a0353a 624 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
tushki7 0:60d829a0353a 625 __I uint32_t RESERVED7[683];
tushki7 0:60d829a0353a 626 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 627 } NRF_TIMER_Type;
tushki7 0:60d829a0353a 628
tushki7 0:60d829a0353a 629
tushki7 0:60d829a0353a 630 /* ================================================================================ */
tushki7 0:60d829a0353a 631 /* ================ RTC ================ */
tushki7 0:60d829a0353a 632 /* ================================================================================ */
tushki7 0:60d829a0353a 633
tushki7 0:60d829a0353a 634
tushki7 0:60d829a0353a 635 /**
tushki7 0:60d829a0353a 636 * @brief Real time counter 0. (RTC)
tushki7 0:60d829a0353a 637 */
tushki7 0:60d829a0353a 638
tushki7 0:60d829a0353a 639 typedef struct { /*!< RTC Structure */
tushki7 0:60d829a0353a 640 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
tushki7 0:60d829a0353a 641 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
tushki7 0:60d829a0353a 642 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
tushki7 0:60d829a0353a 643 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
tushki7 0:60d829a0353a 644 __I uint32_t RESERVED0[60];
tushki7 0:60d829a0353a 645 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
tushki7 0:60d829a0353a 646 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
tushki7 0:60d829a0353a 647 __I uint32_t RESERVED1[14];
tushki7 0:60d829a0353a 648 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
tushki7 0:60d829a0353a 649 __I uint32_t RESERVED2[109];
tushki7 0:60d829a0353a 650 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 651 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 652 __I uint32_t RESERVED3[13];
tushki7 0:60d829a0353a 653 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
tushki7 0:60d829a0353a 654 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
tushki7 0:60d829a0353a 655 the value of EVTEN. */
tushki7 0:60d829a0353a 656 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
tushki7 0:60d829a0353a 657 gives the value of EVTEN. */
tushki7 0:60d829a0353a 658 __I uint32_t RESERVED4[110];
tushki7 0:60d829a0353a 659 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
tushki7 0:60d829a0353a 660 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
tushki7 0:60d829a0353a 661 Must be written when RTC is STOPed. */
tushki7 0:60d829a0353a 662 __I uint32_t RESERVED5[13];
tushki7 0:60d829a0353a 663 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
tushki7 0:60d829a0353a 664 __I uint32_t RESERVED6[683];
tushki7 0:60d829a0353a 665 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 666 } NRF_RTC_Type;
tushki7 0:60d829a0353a 667
tushki7 0:60d829a0353a 668
tushki7 0:60d829a0353a 669 /* ================================================================================ */
tushki7 0:60d829a0353a 670 /* ================ TEMP ================ */
tushki7 0:60d829a0353a 671 /* ================================================================================ */
tushki7 0:60d829a0353a 672
tushki7 0:60d829a0353a 673
tushki7 0:60d829a0353a 674 /**
tushki7 0:60d829a0353a 675 * @brief Temperature Sensor. (TEMP)
tushki7 0:60d829a0353a 676 */
tushki7 0:60d829a0353a 677
tushki7 0:60d829a0353a 678 typedef struct { /*!< TEMP Structure */
tushki7 0:60d829a0353a 679 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
tushki7 0:60d829a0353a 680 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
tushki7 0:60d829a0353a 681 __I uint32_t RESERVED0[62];
tushki7 0:60d829a0353a 682 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
tushki7 0:60d829a0353a 683 __I uint32_t RESERVED1[128];
tushki7 0:60d829a0353a 684 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 685 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 686 __I uint32_t RESERVED2[127];
tushki7 0:60d829a0353a 687 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
tushki7 0:60d829a0353a 688 __I uint32_t RESERVED3[700];
tushki7 0:60d829a0353a 689 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 690 } NRF_TEMP_Type;
tushki7 0:60d829a0353a 691
tushki7 0:60d829a0353a 692
tushki7 0:60d829a0353a 693 /* ================================================================================ */
tushki7 0:60d829a0353a 694 /* ================ RNG ================ */
tushki7 0:60d829a0353a 695 /* ================================================================================ */
tushki7 0:60d829a0353a 696
tushki7 0:60d829a0353a 697
tushki7 0:60d829a0353a 698 /**
tushki7 0:60d829a0353a 699 * @brief Random Number Generator. (RNG)
tushki7 0:60d829a0353a 700 */
tushki7 0:60d829a0353a 701
tushki7 0:60d829a0353a 702 typedef struct { /*!< RNG Structure */
tushki7 0:60d829a0353a 703 __O uint32_t TASKS_START; /*!< Start the random number generator. */
tushki7 0:60d829a0353a 704 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
tushki7 0:60d829a0353a 705 __I uint32_t RESERVED0[62];
tushki7 0:60d829a0353a 706 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
tushki7 0:60d829a0353a 707 __I uint32_t RESERVED1[63];
tushki7 0:60d829a0353a 708 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
tushki7 0:60d829a0353a 709 __I uint32_t RESERVED2[64];
tushki7 0:60d829a0353a 710 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
tushki7 0:60d829a0353a 711 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
tushki7 0:60d829a0353a 712 __I uint32_t RESERVED3[126];
tushki7 0:60d829a0353a 713 __IO uint32_t CONFIG; /*!< Configuration register. */
tushki7 0:60d829a0353a 714 __I uint32_t VALUE; /*!< RNG random number. */
tushki7 0:60d829a0353a 715 __I uint32_t RESERVED4[700];
tushki7 0:60d829a0353a 716 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 717 } NRF_RNG_Type;
tushki7 0:60d829a0353a 718
tushki7 0:60d829a0353a 719
tushki7 0:60d829a0353a 720 /* ================================================================================ */
tushki7 0:60d829a0353a 721 /* ================ ECB ================ */
tushki7 0:60d829a0353a 722 /* ================================================================================ */
tushki7 0:60d829a0353a 723
tushki7 0:60d829a0353a 724
tushki7 0:60d829a0353a 725 /**
tushki7 0:60d829a0353a 726 * @brief AES ECB Mode Encryption. (ECB)
tushki7 0:60d829a0353a 727 */
tushki7 0:60d829a0353a 728
tushki7 0:60d829a0353a 729 typedef struct { /*!< ECB Structure */
tushki7 0:60d829a0353a 730 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
tushki7 0:60d829a0353a 731 will not initiate a new encryption and the ERRORECB event will
tushki7 0:60d829a0353a 732 be triggered. */
tushki7 0:60d829a0353a 733 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
tushki7 0:60d829a0353a 734 this will will trigger the ERRORECB event. */
tushki7 0:60d829a0353a 735 __I uint32_t RESERVED0[62];
tushki7 0:60d829a0353a 736 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
tushki7 0:60d829a0353a 737 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
tushki7 0:60d829a0353a 738 error. */
tushki7 0:60d829a0353a 739 __I uint32_t RESERVED1[127];
tushki7 0:60d829a0353a 740 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 741 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 742 __I uint32_t RESERVED2[126];
tushki7 0:60d829a0353a 743 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
tushki7 0:60d829a0353a 744 __I uint32_t RESERVED3[701];
tushki7 0:60d829a0353a 745 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 746 } NRF_ECB_Type;
tushki7 0:60d829a0353a 747
tushki7 0:60d829a0353a 748
tushki7 0:60d829a0353a 749 /* ================================================================================ */
tushki7 0:60d829a0353a 750 /* ================ AAR ================ */
tushki7 0:60d829a0353a 751 /* ================================================================================ */
tushki7 0:60d829a0353a 752
tushki7 0:60d829a0353a 753
tushki7 0:60d829a0353a 754 /**
tushki7 0:60d829a0353a 755 * @brief Accelerated Address Resolver. (AAR)
tushki7 0:60d829a0353a 756 */
tushki7 0:60d829a0353a 757
tushki7 0:60d829a0353a 758 typedef struct { /*!< AAR Structure */
tushki7 0:60d829a0353a 759 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
tushki7 0:60d829a0353a 760 data structure. */
tushki7 0:60d829a0353a 761 __I uint32_t RESERVED0;
tushki7 0:60d829a0353a 762 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
tushki7 0:60d829a0353a 763 __I uint32_t RESERVED1[61];
tushki7 0:60d829a0353a 764 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
tushki7 0:60d829a0353a 765 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
tushki7 0:60d829a0353a 766 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
tushki7 0:60d829a0353a 767 __I uint32_t RESERVED2[126];
tushki7 0:60d829a0353a 768 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 769 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 770 __I uint32_t RESERVED3[61];
tushki7 0:60d829a0353a 771 __I uint32_t STATUS; /*!< Resolution status. */
tushki7 0:60d829a0353a 772 __I uint32_t RESERVED4[63];
tushki7 0:60d829a0353a 773 __IO uint32_t ENABLE; /*!< Enable AAR. */
tushki7 0:60d829a0353a 774 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
tushki7 0:60d829a0353a 775 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
tushki7 0:60d829a0353a 776 __I uint32_t RESERVED5;
tushki7 0:60d829a0353a 777 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
tushki7 0:60d829a0353a 778 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
tushki7 0:60d829a0353a 779 resolution. A minimum of 3 bytes must be reserved. */
tushki7 0:60d829a0353a 780 __I uint32_t RESERVED6[697];
tushki7 0:60d829a0353a 781 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 782 } NRF_AAR_Type;
tushki7 0:60d829a0353a 783
tushki7 0:60d829a0353a 784
tushki7 0:60d829a0353a 785 /* ================================================================================ */
tushki7 0:60d829a0353a 786 /* ================ CCM ================ */
tushki7 0:60d829a0353a 787 /* ================================================================================ */
tushki7 0:60d829a0353a 788
tushki7 0:60d829a0353a 789
tushki7 0:60d829a0353a 790 /**
tushki7 0:60d829a0353a 791 * @brief AES CCM Mode Encryption. (CCM)
tushki7 0:60d829a0353a 792 */
tushki7 0:60d829a0353a 793
tushki7 0:60d829a0353a 794 typedef struct { /*!< CCM Structure */
tushki7 0:60d829a0353a 795 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
tushki7 0:60d829a0353a 796 itself when completed. */
tushki7 0:60d829a0353a 797 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
tushki7 0:60d829a0353a 798 completed. */
tushki7 0:60d829a0353a 799 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
tushki7 0:60d829a0353a 800 __I uint32_t RESERVED0[61];
tushki7 0:60d829a0353a 801 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
tushki7 0:60d829a0353a 802 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
tushki7 0:60d829a0353a 803 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
tushki7 0:60d829a0353a 804 __I uint32_t RESERVED1[61];
tushki7 0:60d829a0353a 805 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
tushki7 0:60d829a0353a 806 __I uint32_t RESERVED2[64];
tushki7 0:60d829a0353a 807 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 808 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 809 __I uint32_t RESERVED3[61];
tushki7 0:60d829a0353a 810 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
tushki7 0:60d829a0353a 811 __I uint32_t RESERVED4[63];
tushki7 0:60d829a0353a 812 __IO uint32_t ENABLE; /*!< CCM enable. */
tushki7 0:60d829a0353a 813 __IO uint32_t MODE; /*!< Operation mode. */
tushki7 0:60d829a0353a 814 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
tushki7 0:60d829a0353a 815 __IO uint32_t INPTR; /*!< Pointer to input packet. */
tushki7 0:60d829a0353a 816 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
tushki7 0:60d829a0353a 817 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
tushki7 0:60d829a0353a 818 resolution. A minimum of 43 bytes must be reserved. */
tushki7 0:60d829a0353a 819 __I uint32_t RESERVED5[697];
tushki7 0:60d829a0353a 820 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 821 } NRF_CCM_Type;
tushki7 0:60d829a0353a 822
tushki7 0:60d829a0353a 823
tushki7 0:60d829a0353a 824 /* ================================================================================ */
tushki7 0:60d829a0353a 825 /* ================ WDT ================ */
tushki7 0:60d829a0353a 826 /* ================================================================================ */
tushki7 0:60d829a0353a 827
tushki7 0:60d829a0353a 828
tushki7 0:60d829a0353a 829 /**
tushki7 0:60d829a0353a 830 * @brief Watchdog Timer. (WDT)
tushki7 0:60d829a0353a 831 */
tushki7 0:60d829a0353a 832
tushki7 0:60d829a0353a 833 typedef struct { /*!< WDT Structure */
tushki7 0:60d829a0353a 834 __O uint32_t TASKS_START; /*!< Start the watchdog. */
tushki7 0:60d829a0353a 835 __I uint32_t RESERVED0[63];
tushki7 0:60d829a0353a 836 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
tushki7 0:60d829a0353a 837 __I uint32_t RESERVED1[128];
tushki7 0:60d829a0353a 838 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 839 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 840 __I uint32_t RESERVED2[61];
tushki7 0:60d829a0353a 841 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
tushki7 0:60d829a0353a 842 __I uint32_t REQSTATUS; /*!< Request status. */
tushki7 0:60d829a0353a 843 __I uint32_t RESERVED3[63];
tushki7 0:60d829a0353a 844 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
tushki7 0:60d829a0353a 845 __IO uint32_t RREN; /*!< Reload request enable. */
tushki7 0:60d829a0353a 846 __IO uint32_t CONFIG; /*!< Configuration register. */
tushki7 0:60d829a0353a 847 __I uint32_t RESERVED4[60];
tushki7 0:60d829a0353a 848 __O uint32_t RR[8]; /*!< Reload requests registers. */
tushki7 0:60d829a0353a 849 __I uint32_t RESERVED5[631];
tushki7 0:60d829a0353a 850 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 851 } NRF_WDT_Type;
tushki7 0:60d829a0353a 852
tushki7 0:60d829a0353a 853
tushki7 0:60d829a0353a 854 /* ================================================================================ */
tushki7 0:60d829a0353a 855 /* ================ QDEC ================ */
tushki7 0:60d829a0353a 856 /* ================================================================================ */
tushki7 0:60d829a0353a 857
tushki7 0:60d829a0353a 858
tushki7 0:60d829a0353a 859 /**
tushki7 0:60d829a0353a 860 * @brief Rotary decoder. (QDEC)
tushki7 0:60d829a0353a 861 */
tushki7 0:60d829a0353a 862
tushki7 0:60d829a0353a 863 typedef struct { /*!< QDEC Structure */
tushki7 0:60d829a0353a 864 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
tushki7 0:60d829a0353a 865 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
tushki7 0:60d829a0353a 866 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
tushki7 0:60d829a0353a 867 and clears the ACC registers. */
tushki7 0:60d829a0353a 868 __I uint32_t RESERVED0[61];
tushki7 0:60d829a0353a 869 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
tushki7 0:60d829a0353a 870 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
tushki7 0:60d829a0353a 871 ACC register different than zero. */
tushki7 0:60d829a0353a 872 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
tushki7 0:60d829a0353a 873 __I uint32_t RESERVED1[61];
tushki7 0:60d829a0353a 874 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
tushki7 0:60d829a0353a 875 __I uint32_t RESERVED2[64];
tushki7 0:60d829a0353a 876 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 877 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 878 __I uint32_t RESERVED3[125];
tushki7 0:60d829a0353a 879 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
tushki7 0:60d829a0353a 880 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
tushki7 0:60d829a0353a 881 __IO uint32_t SAMPLEPER; /*!< Sample period. */
tushki7 0:60d829a0353a 882 __I int32_t SAMPLE; /*!< Motion sample value. */
tushki7 0:60d829a0353a 883 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
tushki7 0:60d829a0353a 884 __I int32_t ACC; /*!< Accumulated valid transitions register. */
tushki7 0:60d829a0353a 885 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
tushki7 0:60d829a0353a 886 task. */
tushki7 0:60d829a0353a 887 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
tushki7 0:60d829a0353a 888 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
tushki7 0:60d829a0353a 889 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
tushki7 0:60d829a0353a 890 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
tushki7 0:60d829a0353a 891 __I uint32_t RESERVED4[5];
tushki7 0:60d829a0353a 892 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
tushki7 0:60d829a0353a 893 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
tushki7 0:60d829a0353a 894 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
tushki7 0:60d829a0353a 895 task. */
tushki7 0:60d829a0353a 896 __I uint32_t RESERVED5[684];
tushki7 0:60d829a0353a 897 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 898 } NRF_QDEC_Type;
tushki7 0:60d829a0353a 899
tushki7 0:60d829a0353a 900
tushki7 0:60d829a0353a 901 /* ================================================================================ */
tushki7 0:60d829a0353a 902 /* ================ LPCOMP ================ */
tushki7 0:60d829a0353a 903 /* ================================================================================ */
tushki7 0:60d829a0353a 904
tushki7 0:60d829a0353a 905
tushki7 0:60d829a0353a 906 /**
tushki7 0:60d829a0353a 907 * @brief Wakeup Comparator. (LPCOMP)
tushki7 0:60d829a0353a 908 */
tushki7 0:60d829a0353a 909
tushki7 0:60d829a0353a 910 typedef struct { /*!< LPCOMP Structure */
tushki7 0:60d829a0353a 911 __O uint32_t TASKS_START; /*!< Start the comparator. */
tushki7 0:60d829a0353a 912 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
tushki7 0:60d829a0353a 913 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
tushki7 0:60d829a0353a 914 __I uint32_t RESERVED0[61];
tushki7 0:60d829a0353a 915 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
tushki7 0:60d829a0353a 916 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
tushki7 0:60d829a0353a 917 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
tushki7 0:60d829a0353a 918 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
tushki7 0:60d829a0353a 919 __I uint32_t RESERVED1[60];
tushki7 0:60d829a0353a 920 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
tushki7 0:60d829a0353a 921 __I uint32_t RESERVED2[64];
tushki7 0:60d829a0353a 922 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 923 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 924 __I uint32_t RESERVED3[61];
tushki7 0:60d829a0353a 925 __I uint32_t RESULT; /*!< Result of last compare. */
tushki7 0:60d829a0353a 926 __I uint32_t RESERVED4[63];
tushki7 0:60d829a0353a 927 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
tushki7 0:60d829a0353a 928 __IO uint32_t PSEL; /*!< Input pin select. */
tushki7 0:60d829a0353a 929 __IO uint32_t REFSEL; /*!< Reference select. */
tushki7 0:60d829a0353a 930 __IO uint32_t EXTREFSEL; /*!< External reference select. */
tushki7 0:60d829a0353a 931 __I uint32_t RESERVED5[4];
tushki7 0:60d829a0353a 932 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
tushki7 0:60d829a0353a 933 __I uint32_t RESERVED6[694];
tushki7 0:60d829a0353a 934 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 935 } NRF_LPCOMP_Type;
tushki7 0:60d829a0353a 936
tushki7 0:60d829a0353a 937
tushki7 0:60d829a0353a 938 /* ================================================================================ */
tushki7 0:60d829a0353a 939 /* ================ COMP ================ */
tushki7 0:60d829a0353a 940 /* ================================================================================ */
tushki7 0:60d829a0353a 941
tushki7 0:60d829a0353a 942
tushki7 0:60d829a0353a 943 /**
tushki7 0:60d829a0353a 944 * @brief Comparator. (COMP)
tushki7 0:60d829a0353a 945 */
tushki7 0:60d829a0353a 946
tushki7 0:60d829a0353a 947 typedef struct { /*!< COMP Structure */
tushki7 0:60d829a0353a 948 __O uint32_t TASKS_START; /*!< Start the comparator. */
tushki7 0:60d829a0353a 949 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
tushki7 0:60d829a0353a 950 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
tushki7 0:60d829a0353a 951 __I uint32_t RESERVED0[61];
tushki7 0:60d829a0353a 952 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
tushki7 0:60d829a0353a 953 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
tushki7 0:60d829a0353a 954 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
tushki7 0:60d829a0353a 955 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
tushki7 0:60d829a0353a 956 __I uint32_t RESERVED1[60];
tushki7 0:60d829a0353a 957 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
tushki7 0:60d829a0353a 958 __I uint32_t RESERVED2[64];
tushki7 0:60d829a0353a 959 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
tushki7 0:60d829a0353a 960 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
tushki7 0:60d829a0353a 961 __I uint32_t RESERVED3[61];
tushki7 0:60d829a0353a 962 __I uint32_t RESULT; /*!< Compare result. */
tushki7 0:60d829a0353a 963 __I uint32_t RESERVED4[63];
tushki7 0:60d829a0353a 964 __IO uint32_t ENABLE; /*!< Enable the COMP. */
tushki7 0:60d829a0353a 965 __IO uint32_t PSEL; /*!< Input pin select. */
tushki7 0:60d829a0353a 966 __IO uint32_t REFSEL; /*!< Reference select. */
tushki7 0:60d829a0353a 967 __IO uint32_t EXTREFSEL; /*!< External reference select. */
tushki7 0:60d829a0353a 968 __I uint32_t RESERVED5[8];
tushki7 0:60d829a0353a 969 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
tushki7 0:60d829a0353a 970 __IO uint32_t MODE; /*!< Mode configuration. */
tushki7 0:60d829a0353a 971 __I uint32_t RESERVED6[689];
tushki7 0:60d829a0353a 972 __IO uint32_t POWER; /*!< Peripheral power control. */
tushki7 0:60d829a0353a 973 } NRF_COMP_Type;
tushki7 0:60d829a0353a 974
tushki7 0:60d829a0353a 975
tushki7 0:60d829a0353a 976 /* ================================================================================ */
tushki7 0:60d829a0353a 977 /* ================ SWI ================ */
tushki7 0:60d829a0353a 978 /* ================================================================================ */
tushki7 0:60d829a0353a 979
tushki7 0:60d829a0353a 980
tushki7 0:60d829a0353a 981 /**
tushki7 0:60d829a0353a 982 * @brief SW Interrupts. (SWI)
tushki7 0:60d829a0353a 983 */
tushki7 0:60d829a0353a 984
tushki7 0:60d829a0353a 985 typedef struct { /*!< SWI Structure */
tushki7 0:60d829a0353a 986 __I uint32_t UNUSED; /*!< Unused. */
tushki7 0:60d829a0353a 987 } NRF_SWI_Type;
tushki7 0:60d829a0353a 988
tushki7 0:60d829a0353a 989
tushki7 0:60d829a0353a 990 /* ================================================================================ */
tushki7 0:60d829a0353a 991 /* ================ NVMC ================ */
tushki7 0:60d829a0353a 992 /* ================================================================================ */
tushki7 0:60d829a0353a 993
tushki7 0:60d829a0353a 994
tushki7 0:60d829a0353a 995 /**
tushki7 0:60d829a0353a 996 * @brief Non Volatile Memory Controller. (NVMC)
tushki7 0:60d829a0353a 997 */
tushki7 0:60d829a0353a 998
tushki7 0:60d829a0353a 999 typedef struct { /*!< NVMC Structure */
tushki7 0:60d829a0353a 1000 __I uint32_t RESERVED0[256];
tushki7 0:60d829a0353a 1001 __I uint32_t READY; /*!< Ready flag. */
tushki7 0:60d829a0353a 1002 __I uint32_t RESERVED1[64];
tushki7 0:60d829a0353a 1003 __IO uint32_t CONFIG; /*!< Configuration register. */
tushki7 0:60d829a0353a 1004 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
tushki7 0:60d829a0353a 1005 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
tushki7 0:60d829a0353a 1006 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
tushki7 0:60d829a0353a 1007 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
tushki7 0:60d829a0353a 1008 } NRF_NVMC_Type;
tushki7 0:60d829a0353a 1009
tushki7 0:60d829a0353a 1010
tushki7 0:60d829a0353a 1011 /* ================================================================================ */
tushki7 0:60d829a0353a 1012 /* ================ PPI ================ */
tushki7 0:60d829a0353a 1013 /* ================================================================================ */
tushki7 0:60d829a0353a 1014
tushki7 0:60d829a0353a 1015
tushki7 0:60d829a0353a 1016 /**
tushki7 0:60d829a0353a 1017 * @brief PPI controller. (PPI)
tushki7 0:60d829a0353a 1018 */
tushki7 0:60d829a0353a 1019
tushki7 0:60d829a0353a 1020 typedef struct { /*!< PPI Structure */
tushki7 0:60d829a0353a 1021 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
tushki7 0:60d829a0353a 1022 __I uint32_t RESERVED0[312];
tushki7 0:60d829a0353a 1023 __IO uint32_t CHEN; /*!< Channel enable. */
tushki7 0:60d829a0353a 1024 __IO uint32_t CHENSET; /*!< Channel enable set. */
tushki7 0:60d829a0353a 1025 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
tushki7 0:60d829a0353a 1026 __I uint32_t RESERVED1;
tushki7 0:60d829a0353a 1027 PPI_CH_Type CH[16]; /*!< PPI Channel. */
tushki7 0:60d829a0353a 1028 __I uint32_t RESERVED2[156];
tushki7 0:60d829a0353a 1029 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
tushki7 0:60d829a0353a 1030 } NRF_PPI_Type;
tushki7 0:60d829a0353a 1031
tushki7 0:60d829a0353a 1032
tushki7 0:60d829a0353a 1033 /* ================================================================================ */
tushki7 0:60d829a0353a 1034 /* ================ FICR ================ */
tushki7 0:60d829a0353a 1035 /* ================================================================================ */
tushki7 0:60d829a0353a 1036
tushki7 0:60d829a0353a 1037
tushki7 0:60d829a0353a 1038 /**
tushki7 0:60d829a0353a 1039 * @brief Factory Information Configuration. (FICR)
tushki7 0:60d829a0353a 1040 */
tushki7 0:60d829a0353a 1041
tushki7 0:60d829a0353a 1042 typedef struct { /*!< FICR Structure */
tushki7 0:60d829a0353a 1043 __I uint32_t RESERVED0[4];
tushki7 0:60d829a0353a 1044 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
tushki7 0:60d829a0353a 1045 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
tushki7 0:60d829a0353a 1046 __I uint32_t RESERVED1[4];
tushki7 0:60d829a0353a 1047 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
tushki7 0:60d829a0353a 1048 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
tushki7 0:60d829a0353a 1049 __I uint32_t RESERVED2;
tushki7 0:60d829a0353a 1050 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
tushki7 0:60d829a0353a 1051 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
tushki7 0:60d829a0353a 1052 __I uint32_t RESERVED3[5];
tushki7 0:60d829a0353a 1053 __I uint32_t CONFIGID; /*!< Configuration identifier. */
tushki7 0:60d829a0353a 1054 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
tushki7 0:60d829a0353a 1055 __I uint32_t RESERVED4[6];
tushki7 0:60d829a0353a 1056 __I uint32_t ER[4]; /*!< Encryption root. */
tushki7 0:60d829a0353a 1057 __I uint32_t IR[4]; /*!< Identity root. */
tushki7 0:60d829a0353a 1058 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
tushki7 0:60d829a0353a 1059 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
tushki7 0:60d829a0353a 1060 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
tushki7 0:60d829a0353a 1061 __I uint32_t RESERVED5[15];
tushki7 0:60d829a0353a 1062 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
tushki7 0:60d829a0353a 1063 mode. */
tushki7 0:60d829a0353a 1064 } NRF_FICR_Type;
tushki7 0:60d829a0353a 1065
tushki7 0:60d829a0353a 1066
tushki7 0:60d829a0353a 1067 /* ================================================================================ */
tushki7 0:60d829a0353a 1068 /* ================ UICR ================ */
tushki7 0:60d829a0353a 1069 /* ================================================================================ */
tushki7 0:60d829a0353a 1070
tushki7 0:60d829a0353a 1071
tushki7 0:60d829a0353a 1072 /**
tushki7 0:60d829a0353a 1073 * @brief User Information Configuration. (UICR)
tushki7 0:60d829a0353a 1074 */
tushki7 0:60d829a0353a 1075
tushki7 0:60d829a0353a 1076 typedef struct { /*!< UICR Structure */
tushki7 0:60d829a0353a 1077 __IO uint32_t CLENR0; /*!< Length of code region 0. */
tushki7 0:60d829a0353a 1078 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
tushki7 0:60d829a0353a 1079 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
tushki7 0:60d829a0353a 1080 __I uint32_t RESERVED0;
tushki7 0:60d829a0353a 1081 __I uint32_t FWID; /*!< Firmware ID. */
tushki7 0:60d829a0353a 1082 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
tushki7 0:60d829a0353a 1083 } NRF_UICR_Type;
tushki7 0:60d829a0353a 1084
tushki7 0:60d829a0353a 1085
tushki7 0:60d829a0353a 1086 /* ================================================================================ */
tushki7 0:60d829a0353a 1087 /* ================ GPIO ================ */
tushki7 0:60d829a0353a 1088 /* ================================================================================ */
tushki7 0:60d829a0353a 1089
tushki7 0:60d829a0353a 1090
tushki7 0:60d829a0353a 1091 /**
tushki7 0:60d829a0353a 1092 * @brief General purpose input and output. (GPIO)
tushki7 0:60d829a0353a 1093 */
tushki7 0:60d829a0353a 1094
tushki7 0:60d829a0353a 1095 typedef struct { /*!< GPIO Structure */
tushki7 0:60d829a0353a 1096 __I uint32_t RESERVED0[321];
tushki7 0:60d829a0353a 1097 __IO uint32_t OUT; /*!< Write GPIO port. */
tushki7 0:60d829a0353a 1098 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
tushki7 0:60d829a0353a 1099 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
tushki7 0:60d829a0353a 1100 __I uint32_t IN; /*!< Read GPIO port. */
tushki7 0:60d829a0353a 1101 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
tushki7 0:60d829a0353a 1102 __IO uint32_t DIRSET; /*!< DIR set register. */
tushki7 0:60d829a0353a 1103 __IO uint32_t DIRCLR; /*!< DIR clear register. */
tushki7 0:60d829a0353a 1104 __I uint32_t RESERVED1[120];
tushki7 0:60d829a0353a 1105 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
tushki7 0:60d829a0353a 1106 } NRF_GPIO_Type;
tushki7 0:60d829a0353a 1107
tushki7 0:60d829a0353a 1108
tushki7 0:60d829a0353a 1109 /* -------------------- End of section using anonymous unions ------------------- */
tushki7 0:60d829a0353a 1110 #if defined(__CC_ARM)
tushki7 0:60d829a0353a 1111 #pragma pop
tushki7 0:60d829a0353a 1112 #elif defined(__ICCARM__)
tushki7 0:60d829a0353a 1113 /* leave anonymous unions enabled */
tushki7 0:60d829a0353a 1114 #elif defined(__GNUC__)
tushki7 0:60d829a0353a 1115 /* anonymous unions are enabled by default */
tushki7 0:60d829a0353a 1116 #elif defined(__TMS470__)
tushki7 0:60d829a0353a 1117 /* anonymous unions are enabled by default */
tushki7 0:60d829a0353a 1118 #elif defined(__TASKING__)
tushki7 0:60d829a0353a 1119 #pragma warning restore
tushki7 0:60d829a0353a 1120 #else
tushki7 0:60d829a0353a 1121 #warning Not supported compiler type
tushki7 0:60d829a0353a 1122 #endif
tushki7 0:60d829a0353a 1123
tushki7 0:60d829a0353a 1124
tushki7 0:60d829a0353a 1125
tushki7 0:60d829a0353a 1126
tushki7 0:60d829a0353a 1127 /* ================================================================================ */
tushki7 0:60d829a0353a 1128 /* ================ Peripheral memory map ================ */
tushki7 0:60d829a0353a 1129 /* ================================================================================ */
tushki7 0:60d829a0353a 1130
tushki7 0:60d829a0353a 1131 #define NRF_POWER_BASE 0x40000000UL
tushki7 0:60d829a0353a 1132 #define NRF_CLOCK_BASE 0x40000000UL
tushki7 0:60d829a0353a 1133 #define NRF_MPU_BASE 0x40000000UL
tushki7 0:60d829a0353a 1134 #define NRF_PU_BASE 0x40000000UL
tushki7 0:60d829a0353a 1135 #define NRF_AMLI_BASE 0x40000000UL
tushki7 0:60d829a0353a 1136 #define NRF_RADIO_BASE 0x40001000UL
tushki7 0:60d829a0353a 1137 #define NRF_UART0_BASE 0x40002000UL
tushki7 0:60d829a0353a 1138 #define NRF_SPI0_BASE 0x40003000UL
tushki7 0:60d829a0353a 1139 #define NRF_TWI0_BASE 0x40003000UL
tushki7 0:60d829a0353a 1140 #define NRF_SPI1_BASE 0x40004000UL
tushki7 0:60d829a0353a 1141 #define NRF_TWI1_BASE 0x40004000UL
tushki7 0:60d829a0353a 1142 #define NRF_SPIS1_BASE 0x40004000UL
tushki7 0:60d829a0353a 1143 #define NRF_GPIOTE_BASE 0x40006000UL
tushki7 0:60d829a0353a 1144 #define NRF_ADC_BASE 0x40007000UL
tushki7 0:60d829a0353a 1145 #define NRF_TIMER0_BASE 0x40008000UL
tushki7 0:60d829a0353a 1146 #define NRF_TIMER1_BASE 0x40009000UL
tushki7 0:60d829a0353a 1147 #define NRF_TIMER2_BASE 0x4000A000UL
tushki7 0:60d829a0353a 1148 #define NRF_RTC0_BASE 0x4000B000UL
tushki7 0:60d829a0353a 1149 #define NRF_TEMP_BASE 0x4000C000UL
tushki7 0:60d829a0353a 1150 #define NRF_RNG_BASE 0x4000D000UL
tushki7 0:60d829a0353a 1151 #define NRF_ECB_BASE 0x4000E000UL
tushki7 0:60d829a0353a 1152 #define NRF_AAR_BASE 0x4000F000UL
tushki7 0:60d829a0353a 1153 #define NRF_CCM_BASE 0x4000F000UL
tushki7 0:60d829a0353a 1154 #define NRF_WDT_BASE 0x40010000UL
tushki7 0:60d829a0353a 1155 #define NRF_RTC1_BASE 0x40011000UL
tushki7 0:60d829a0353a 1156 #define NRF_QDEC_BASE 0x40012000UL
tushki7 0:60d829a0353a 1157 #define NRF_LPCOMP_BASE 0x40013000UL
tushki7 0:60d829a0353a 1158 #define NRF_COMP_BASE 0x40013000UL
tushki7 0:60d829a0353a 1159 #define NRF_SWI_BASE 0x40014000UL
tushki7 0:60d829a0353a 1160 #define NRF_NVMC_BASE 0x4001E000UL
tushki7 0:60d829a0353a 1161 #define NRF_PPI_BASE 0x4001F000UL
tushki7 0:60d829a0353a 1162 #define NRF_FICR_BASE 0x10000000UL
tushki7 0:60d829a0353a 1163 #define NRF_UICR_BASE 0x10001000UL
tushki7 0:60d829a0353a 1164 #define NRF_GPIO_BASE 0x50000000UL
tushki7 0:60d829a0353a 1165
tushki7 0:60d829a0353a 1166
tushki7 0:60d829a0353a 1167 /* ================================================================================ */
tushki7 0:60d829a0353a 1168 /* ================ Peripheral declaration ================ */
tushki7 0:60d829a0353a 1169 /* ================================================================================ */
tushki7 0:60d829a0353a 1170
tushki7 0:60d829a0353a 1171 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
tushki7 0:60d829a0353a 1172 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
tushki7 0:60d829a0353a 1173 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
tushki7 0:60d829a0353a 1174 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
tushki7 0:60d829a0353a 1175 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
tushki7 0:60d829a0353a 1176 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
tushki7 0:60d829a0353a 1177 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
tushki7 0:60d829a0353a 1178 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
tushki7 0:60d829a0353a 1179 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
tushki7 0:60d829a0353a 1180 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
tushki7 0:60d829a0353a 1181 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
tushki7 0:60d829a0353a 1182 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
tushki7 0:60d829a0353a 1183 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
tushki7 0:60d829a0353a 1184 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
tushki7 0:60d829a0353a 1185 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
tushki7 0:60d829a0353a 1186 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
tushki7 0:60d829a0353a 1187 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
tushki7 0:60d829a0353a 1188 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
tushki7 0:60d829a0353a 1189 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
tushki7 0:60d829a0353a 1190 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
tushki7 0:60d829a0353a 1191 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
tushki7 0:60d829a0353a 1192 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
tushki7 0:60d829a0353a 1193 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
tushki7 0:60d829a0353a 1194 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
tushki7 0:60d829a0353a 1195 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
tushki7 0:60d829a0353a 1196 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
tushki7 0:60d829a0353a 1197 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
tushki7 0:60d829a0353a 1198 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
tushki7 0:60d829a0353a 1199 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
tushki7 0:60d829a0353a 1200 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
tushki7 0:60d829a0353a 1201 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
tushki7 0:60d829a0353a 1202 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
tushki7 0:60d829a0353a 1203 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
tushki7 0:60d829a0353a 1204 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
tushki7 0:60d829a0353a 1205
tushki7 0:60d829a0353a 1206
tushki7 0:60d829a0353a 1207 /** @} */ /* End of group Device_Peripheral_Registers */
tushki7 0:60d829a0353a 1208 /** @} */ /* End of group nRF51 */
tushki7 0:60d829a0353a 1209 /** @} */ /* End of group Nordic Semiconductor */
tushki7 0:60d829a0353a 1210
tushki7 0:60d829a0353a 1211 #ifdef __cplusplus
tushki7 0:60d829a0353a 1212 }
tushki7 0:60d829a0353a 1213 #endif
tushki7 0:60d829a0353a 1214
tushki7 0:60d829a0353a 1215
tushki7 0:60d829a0353a 1216 #endif /* nRF51_H */