Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_K64F/system_MK64F12.h@0:60d829a0353a, 2015-04-11 (annotated)

Committer:
tushki7
Date:
Sat Apr 11 04:08:13 2015 +0000
Revision:
0:60d829a0353a
A simple 128x32 LCD program to quickstart with LCD on ARM mbed IoT Starter kit. Mbed Application Shield is required if using FRDM-K64F platform.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /*
tushki7 0:60d829a0353a 2 ** ###################################################################
tushki7 0:60d829a0353a 3 ** Processor: MK64FN1M0VMD12
tushki7 0:60d829a0353a 4 ** Compilers: Keil ARM C/C++ Compiler
tushki7 0:60d829a0353a 5 ** Freescale C/C++ for Embedded ARM
tushki7 0:60d829a0353a 6 ** GNU C Compiler
tushki7 0:60d829a0353a 7 ** GNU C Compiler - CodeSourcery Sourcery G++
tushki7 0:60d829a0353a 8 ** IAR ANSI C/C++ Compiler for ARM
tushki7 0:60d829a0353a 9 **
tushki7 0:60d829a0353a 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
tushki7 0:60d829a0353a 11 ** Version: rev. 2.5, 2014-02-10
tushki7 0:60d829a0353a 12 ** Build: b140611
tushki7 0:60d829a0353a 13 **
tushki7 0:60d829a0353a 14 ** Abstract:
tushki7 0:60d829a0353a 15 ** Provides a system configuration function and a global variable that
tushki7 0:60d829a0353a 16 ** contains the system frequency. It configures the device and initializes
tushki7 0:60d829a0353a 17 ** the oscillator (PLL) that is part of the microcontroller device.
tushki7 0:60d829a0353a 18 **
tushki7 0:60d829a0353a 19 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
tushki7 0:60d829a0353a 20 ** All rights reserved.
tushki7 0:60d829a0353a 21 **
tushki7 0:60d829a0353a 22 ** Redistribution and use in source and binary forms, with or without modification,
tushki7 0:60d829a0353a 23 ** are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 24 **
tushki7 0:60d829a0353a 25 ** o Redistributions of source code must retain the above copyright notice, this list
tushki7 0:60d829a0353a 26 ** of conditions and the following disclaimer.
tushki7 0:60d829a0353a 27 **
tushki7 0:60d829a0353a 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
tushki7 0:60d829a0353a 29 ** list of conditions and the following disclaimer in the documentation and/or
tushki7 0:60d829a0353a 30 ** other materials provided with the distribution.
tushki7 0:60d829a0353a 31 **
tushki7 0:60d829a0353a 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
tushki7 0:60d829a0353a 33 ** contributors may be used to endorse or promote products derived from this
tushki7 0:60d829a0353a 34 ** software without specific prior written permission.
tushki7 0:60d829a0353a 35 **
tushki7 0:60d829a0353a 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
tushki7 0:60d829a0353a 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
tushki7 0:60d829a0353a 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7 0:60d829a0353a 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
tushki7 0:60d829a0353a 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
tushki7 0:60d829a0353a 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
tushki7 0:60d829a0353a 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
tushki7 0:60d829a0353a 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
tushki7 0:60d829a0353a 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
tushki7 0:60d829a0353a 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 46 **
tushki7 0:60d829a0353a 47 ** http: www.freescale.com
tushki7 0:60d829a0353a 48 ** mail: support@freescale.com
tushki7 0:60d829a0353a 49 **
tushki7 0:60d829a0353a 50 ** Revisions:
tushki7 0:60d829a0353a 51 ** - rev. 1.0 (2013-08-12)
tushki7 0:60d829a0353a 52 ** Initial version.
tushki7 0:60d829a0353a 53 ** - rev. 2.0 (2013-10-29)
tushki7 0:60d829a0353a 54 ** Register accessor macros added to the memory map.
tushki7 0:60d829a0353a 55 ** Symbols for Processor Expert memory map compatibility added to the memory map.
tushki7 0:60d829a0353a 56 ** Startup file for gcc has been updated according to CMSIS 3.2.
tushki7 0:60d829a0353a 57 ** System initialization updated.
tushki7 0:60d829a0353a 58 ** MCG - registers updated.
tushki7 0:60d829a0353a 59 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
tushki7 0:60d829a0353a 60 ** - rev. 2.1 (2013-10-30)
tushki7 0:60d829a0353a 61 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
tushki7 0:60d829a0353a 62 ** - rev. 2.2 (2013-12-09)
tushki7 0:60d829a0353a 63 ** DMA - EARS register removed.
tushki7 0:60d829a0353a 64 ** AIPS0, AIPS1 - MPRA register updated.
tushki7 0:60d829a0353a 65 ** - rev. 2.3 (2014-01-24)
tushki7 0:60d829a0353a 66 ** Update according to reference manual rev. 2
tushki7 0:60d829a0353a 67 ** ENET, MCG, MCM, SIM, USB - registers updated
tushki7 0:60d829a0353a 68 ** - rev. 2.4 (2014-02-10)
tushki7 0:60d829a0353a 69 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
tushki7 0:60d829a0353a 70 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
tushki7 0:60d829a0353a 71 ** - rev. 2.5 (2014-02-10)
tushki7 0:60d829a0353a 72 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
tushki7 0:60d829a0353a 73 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
tushki7 0:60d829a0353a 74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
tushki7 0:60d829a0353a 75 **
tushki7 0:60d829a0353a 76 ** ###################################################################
tushki7 0:60d829a0353a 77 */
tushki7 0:60d829a0353a 78
tushki7 0:60d829a0353a 79 /*!
tushki7 0:60d829a0353a 80 * @file MK64F12
tushki7 0:60d829a0353a 81 * @version 2.5
tushki7 0:60d829a0353a 82 * @date 2014-02-10
tushki7 0:60d829a0353a 83 * @brief Device specific configuration file for MK64F12 (header file)
tushki7 0:60d829a0353a 84 *
tushki7 0:60d829a0353a 85 * Provides a system configuration function and a global variable that contains
tushki7 0:60d829a0353a 86 * the system frequency. It configures the device and initializes the oscillator
tushki7 0:60d829a0353a 87 * (PLL) that is part of the microcontroller device.
tushki7 0:60d829a0353a 88 */
tushki7 0:60d829a0353a 89
tushki7 0:60d829a0353a 90 #ifndef SYSTEM_MK64F12_H_
tushki7 0:60d829a0353a 91 #define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
tushki7 0:60d829a0353a 92
tushki7 0:60d829a0353a 93 #ifdef __cplusplus
tushki7 0:60d829a0353a 94 extern "C" {
tushki7 0:60d829a0353a 95 #endif
tushki7 0:60d829a0353a 96
tushki7 0:60d829a0353a 97 #include <stdint.h>
tushki7 0:60d829a0353a 98
tushki7 0:60d829a0353a 99
tushki7 0:60d829a0353a 100 #define DISABLE_WDOG 1
tushki7 0:60d829a0353a 101
tushki7 0:60d829a0353a 102 #ifndef CLOCK_SETUP
tushki7 0:60d829a0353a 103 #define CLOCK_SETUP 4
tushki7 0:60d829a0353a 104 #endif
tushki7 0:60d829a0353a 105
tushki7 0:60d829a0353a 106 /* MCG mode constants */
tushki7 0:60d829a0353a 107
tushki7 0:60d829a0353a 108 #define MCG_MODE_FEI 0U
tushki7 0:60d829a0353a 109 #define MCG_MODE_FBI 1U
tushki7 0:60d829a0353a 110 #define MCG_MODE_BLPI 2U
tushki7 0:60d829a0353a 111 #define MCG_MODE_FEE 3U
tushki7 0:60d829a0353a 112 #define MCG_MODE_FBE 4U
tushki7 0:60d829a0353a 113 #define MCG_MODE_BLPE 5U
tushki7 0:60d829a0353a 114 #define MCG_MODE_PBE 6U
tushki7 0:60d829a0353a 115 #define MCG_MODE_PEE 7U
tushki7 0:60d829a0353a 116
tushki7 0:60d829a0353a 117 /* Predefined clock setups
tushki7 0:60d829a0353a 118 0 ... Default part configuration
tushki7 0:60d829a0353a 119 Multipurpose Clock Generator (MCG) in FEI mode.
tushki7 0:60d829a0353a 120 Reference clock source for MCG module: Slow internal reference clock
tushki7 0:60d829a0353a 121 Core clock = 20.97152MHz
tushki7 0:60d829a0353a 122 Bus clock = 20.97152MHz
tushki7 0:60d829a0353a 123 1 ... Maximum achievable clock frequency configuration
tushki7 0:60d829a0353a 124 Multipurpose Clock Generator (MCG) in PEE mode.
tushki7 0:60d829a0353a 125 Reference clock source for MCG module: System oscillator 0 reference clock
tushki7 0:60d829a0353a 126 Core clock = 120MHz
tushki7 0:60d829a0353a 127 Bus clock = 60MHz
tushki7 0:60d829a0353a 128 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
tushki7 0:60d829a0353a 129 Multipurpose Clock Generator (MCG) in BLPI mode.
tushki7 0:60d829a0353a 130 Reference clock source for MCG module: Fast internal reference clock
tushki7 0:60d829a0353a 131 Core clock = 4MHz
tushki7 0:60d829a0353a 132 Bus clock = 4MHz
tushki7 0:60d829a0353a 133 3 ... Chip externally clocked, ready for Very Low Power Run mode.
tushki7 0:60d829a0353a 134 Multipurpose Clock Generator (MCG) in BLPE mode.
tushki7 0:60d829a0353a 135 Reference clock source for MCG module: RTC oscillator reference clock
tushki7 0:60d829a0353a 136 Core clock = 0.032768MHz
tushki7 0:60d829a0353a 137 Bus clock = 0.032768MHz
tushki7 0:60d829a0353a 138 4 ... USB clock setup
tushki7 0:60d829a0353a 139 Multipurpose Clock Generator (MCG) in PEE mode.
tushki7 0:60d829a0353a 140 Reference clock source for MCG module: System oscillator 0 reference clock
tushki7 0:60d829a0353a 141 Core clock = 120MHz
tushki7 0:60d829a0353a 142 Bus clock = 60MHz
tushki7 0:60d829a0353a 143 */
tushki7 0:60d829a0353a 144
tushki7 0:60d829a0353a 145 /* Define clock source values */
tushki7 0:60d829a0353a 146
tushki7 0:60d829a0353a 147 #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 148 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 149 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 150 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 151 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 152
tushki7 0:60d829a0353a 153 /* RTC oscillator setting */
tushki7 0:60d829a0353a 154 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
tushki7 0:60d829a0353a 155 #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
tushki7 0:60d829a0353a 156
tushki7 0:60d829a0353a 157 /* Low power mode enable */
tushki7 0:60d829a0353a 158 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
tushki7 0:60d829a0353a 159 #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
tushki7 0:60d829a0353a 160
tushki7 0:60d829a0353a 161 /* Internal reference clock trim */
tushki7 0:60d829a0353a 162 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
tushki7 0:60d829a0353a 163 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
tushki7 0:60d829a0353a 164 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
tushki7 0:60d829a0353a 165 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
tushki7 0:60d829a0353a 166
tushki7 0:60d829a0353a 167 #if (CLOCK_SETUP == 0)
tushki7 0:60d829a0353a 168 #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
tushki7 0:60d829a0353a 169 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
tushki7 0:60d829a0353a 170 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 171 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
tushki7 0:60d829a0353a 172 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
tushki7 0:60d829a0353a 173 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
tushki7 0:60d829a0353a 174 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
tushki7 0:60d829a0353a 175 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
tushki7 0:60d829a0353a 176 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
tushki7 0:60d829a0353a 177 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
tushki7 0:60d829a0353a 178 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
tushki7 0:60d829a0353a 179 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
tushki7 0:60d829a0353a 180 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
tushki7 0:60d829a0353a 181 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
tushki7 0:60d829a0353a 182 /* MCG_C7: OSCSEL=0 */
tushki7 0:60d829a0353a 183 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
tushki7 0:60d829a0353a 184 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 185 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
tushki7 0:60d829a0353a 186 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 187 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
tushki7 0:60d829a0353a 188 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
tushki7 0:60d829a0353a 189 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 190 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
tushki7 0:60d829a0353a 191 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
tushki7 0:60d829a0353a 192 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 193 #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
tushki7 0:60d829a0353a 194 #elif (CLOCK_SETUP == 1)
tushki7 0:60d829a0353a 195 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
tushki7 0:60d829a0353a 196 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
tushki7 0:60d829a0353a 197 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 198 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
tushki7 0:60d829a0353a 199 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
tushki7 0:60d829a0353a 200 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
tushki7 0:60d829a0353a 201 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
tushki7 0:60d829a0353a 202 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
tushki7 0:60d829a0353a 203 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
tushki7 0:60d829a0353a 204 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
tushki7 0:60d829a0353a 205 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
tushki7 0:60d829a0353a 206 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
tushki7 0:60d829a0353a 207 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
tushki7 0:60d829a0353a 208 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
tushki7 0:60d829a0353a 209 /* MCG_C7: OSCSEL=0 */
tushki7 0:60d829a0353a 210 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
tushki7 0:60d829a0353a 211 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 212 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
tushki7 0:60d829a0353a 213 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 214 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
tushki7 0:60d829a0353a 215 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
tushki7 0:60d829a0353a 216 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 217 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
tushki7 0:60d829a0353a 218 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
tushki7 0:60d829a0353a 219 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 220 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
tushki7 0:60d829a0353a 221 #elif (CLOCK_SETUP == 2)
tushki7 0:60d829a0353a 222 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
tushki7 0:60d829a0353a 223 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
tushki7 0:60d829a0353a 224 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 225 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
tushki7 0:60d829a0353a 226 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
tushki7 0:60d829a0353a 227 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
tushki7 0:60d829a0353a 228 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
tushki7 0:60d829a0353a 229 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
tushki7 0:60d829a0353a 230 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
tushki7 0:60d829a0353a 231 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
tushki7 0:60d829a0353a 232 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
tushki7 0:60d829a0353a 233 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
tushki7 0:60d829a0353a 234 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
tushki7 0:60d829a0353a 235 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
tushki7 0:60d829a0353a 236 /* MCG_C7: OSCSEL=0 */
tushki7 0:60d829a0353a 237 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
tushki7 0:60d829a0353a 238 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 239 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
tushki7 0:60d829a0353a 240 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 241 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
tushki7 0:60d829a0353a 242 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
tushki7 0:60d829a0353a 243 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 244 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
tushki7 0:60d829a0353a 245 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
tushki7 0:60d829a0353a 246 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 247 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
tushki7 0:60d829a0353a 248 #elif (CLOCK_SETUP == 3)
tushki7 0:60d829a0353a 249 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
tushki7 0:60d829a0353a 250 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
tushki7 0:60d829a0353a 251 /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 252 #define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */
tushki7 0:60d829a0353a 253 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
tushki7 0:60d829a0353a 254 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
tushki7 0:60d829a0353a 255 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
tushki7 0:60d829a0353a 256 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
tushki7 0:60d829a0353a 257 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
tushki7 0:60d829a0353a 258 #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
tushki7 0:60d829a0353a 259 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
tushki7 0:60d829a0353a 260 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
tushki7 0:60d829a0353a 261 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
tushki7 0:60d829a0353a 262 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
tushki7 0:60d829a0353a 263 /* MCG_C7: OSCSEL=1 */
tushki7 0:60d829a0353a 264 #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
tushki7 0:60d829a0353a 265 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 266 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
tushki7 0:60d829a0353a 267 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 268 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
tushki7 0:60d829a0353a 269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
tushki7 0:60d829a0353a 270 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 271 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
tushki7 0:60d829a0353a 272 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
tushki7 0:60d829a0353a 273 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 274 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
tushki7 0:60d829a0353a 275 #elif (CLOCK_SETUP == 4)
tushki7 0:60d829a0353a 276 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
tushki7 0:60d829a0353a 277 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
tushki7 0:60d829a0353a 278 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 279 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
tushki7 0:60d829a0353a 280 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
tushki7 0:60d829a0353a 281 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
tushki7 0:60d829a0353a 282 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
tushki7 0:60d829a0353a 283 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
tushki7 0:60d829a0353a 284 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
tushki7 0:60d829a0353a 285 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
tushki7 0:60d829a0353a 286 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
tushki7 0:60d829a0353a 287 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
tushki7 0:60d829a0353a 288 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
tushki7 0:60d829a0353a 289 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
tushki7 0:60d829a0353a 290 /* MCG_C7: OSCSEL=0 */
tushki7 0:60d829a0353a 291 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
tushki7 0:60d829a0353a 292 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 293 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
tushki7 0:60d829a0353a 294 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 295 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
tushki7 0:60d829a0353a 296 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
tushki7 0:60d829a0353a 297 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 298 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
tushki7 0:60d829a0353a 299 #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
tushki7 0:60d829a0353a 300 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
tushki7 0:60d829a0353a 301 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
tushki7 0:60d829a0353a 302 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 303 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
tushki7 0:60d829a0353a 304 #endif
tushki7 0:60d829a0353a 305
tushki7 0:60d829a0353a 306 /**
tushki7 0:60d829a0353a 307 * @brief System clock frequency (core clock)
tushki7 0:60d829a0353a 308 *
tushki7 0:60d829a0353a 309 * The system clock frequency supplied to the SysTick timer and the processor
tushki7 0:60d829a0353a 310 * core clock. This variable can be used by the user application to setup the
tushki7 0:60d829a0353a 311 * SysTick timer or configure other parameters. It may also be used by debugger to
tushki7 0:60d829a0353a 312 * query the frequency of the debug timer or configure the trace clock speed
tushki7 0:60d829a0353a 313 * SystemCoreClock is initialized with a correct predefined value.
tushki7 0:60d829a0353a 314 */
tushki7 0:60d829a0353a 315 extern uint32_t SystemCoreClock;
tushki7 0:60d829a0353a 316
tushki7 0:60d829a0353a 317 /**
tushki7 0:60d829a0353a 318 * @brief Setup the microcontroller system.
tushki7 0:60d829a0353a 319 *
tushki7 0:60d829a0353a 320 * Typically this function configures the oscillator (PLL) that is part of the
tushki7 0:60d829a0353a 321 * microcontroller device. For systems with variable clock speed it also updates
tushki7 0:60d829a0353a 322 * the variable SystemCoreClock. SystemInit is called from startup_device file.
tushki7 0:60d829a0353a 323 */
tushki7 0:60d829a0353a 324 void SystemInit (void);
tushki7 0:60d829a0353a 325
tushki7 0:60d829a0353a 326 /**
tushki7 0:60d829a0353a 327 * @brief Updates the SystemCoreClock variable.
tushki7 0:60d829a0353a 328 *
tushki7 0:60d829a0353a 329 * It must be called whenever the core clock is changed during program
tushki7 0:60d829a0353a 330 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
tushki7 0:60d829a0353a 331 * the current core clock.
tushki7 0:60d829a0353a 332 */
tushki7 0:60d829a0353a 333 void SystemCoreClockUpdate (void);
tushki7 0:60d829a0353a 334
tushki7 0:60d829a0353a 335 #ifdef __cplusplus
tushki7 0:60d829a0353a 336 }
tushki7 0:60d829a0353a 337 #endif
tushki7 0:60d829a0353a 338
tushki7 0:60d829a0353a 339 #endif /* #if !defined(SYSTEM_MK64F12_H_) */