Александр Селифонов / MPU9250_Interface

temprary

register.h@2:a36510ff4272, 2020-01-27 (annotated)

Committer:
turumputum
Date:
Mon Jan 27 10:19:04 2020 +0000
Revision:
2:a36510ff4272
Parent:
1:e16407b5e24f 
turn off while(1) in sensor init

Who changed what in which revision?

UserRevisionLine numberNew contents of line
soulx 0:b502ea2d6ebb 1 // See also MPU-9250 Register Map and Descriptions, Revision 4.0, RM-MPU-9250A-00, Rev. 1.4, 9/9/2013 for registers not listed in
soulx 0:b502ea2d6ebb 2 // above document; the MPU9250 and MPU9150 are virtually identical but the latter has a different register map
soulx 0:b502ea2d6ebb 3 //
soulx 0:b502ea2d6ebb 4 //AD0
dimavb 1:e16407b5e24f 5 #define MPU9250_ADDRESS_68 (0x68<<1)
dimavb 1:e16407b5e24f 6 #define MPU9250_ADDRESS_69 (0x69<<1)
soulx 0:b502ea2d6ebb 7
soulx 0:b502ea2d6ebb 8 //Magnetometer Registers
soulx 0:b502ea2d6ebb 9 #define AK8963_ADDRESS 0x0C<<1
soulx 0:b502ea2d6ebb 10 #define WHO_AM_I_AK8963 0x00 // should return 0x48
soulx 0:b502ea2d6ebb 11 #define INFO 0x01
soulx 0:b502ea2d6ebb 12 #define AK8963_ST1 0x02 // data ready status bit 0
soulx 0:b502ea2d6ebb 13 #define AK8963_XOUT_L 0x03 // data
soulx 0:b502ea2d6ebb 14 #define AK8963_XOUT_H 0x04
soulx 0:b502ea2d6ebb 15 #define AK8963_YOUT_L 0x05
soulx 0:b502ea2d6ebb 16 #define AK8963_YOUT_H 0x06
soulx 0:b502ea2d6ebb 17 #define AK8963_ZOUT_L 0x07
soulx 0:b502ea2d6ebb 18 #define AK8963_ZOUT_H 0x08
soulx 0:b502ea2d6ebb 19 #define AK8963_ST2 0x09 // Data overflow bit 3 and data read error status bit 2
soulx 0:b502ea2d6ebb 20 #define AK8963_CNTL 0x0A // Power down (0000), single-measurement (0001), self-test (1000) and Fuse ROM (1111) modes on bits 3:0
soulx 0:b502ea2d6ebb 21 #define AK8963_ASTC 0x0C // Self test control
soulx 0:b502ea2d6ebb 22 #define AK8963_I2CDIS 0x0F // I2C disable
soulx 0:b502ea2d6ebb 23 #define AK8963_ASAX 0x10 // Fuse ROM x-axis sensitivity adjustment value
soulx 0:b502ea2d6ebb 24 #define AK8963_ASAY 0x11 // Fuse ROM y-axis sensitivity adjustment value
soulx 0:b502ea2d6ebb 25 #define AK8963_ASAZ 0x12 // Fuse ROM z-axis sensitivity adjustment value
soulx 0:b502ea2d6ebb 26
soulx 0:b502ea2d6ebb 27 #define SELF_TEST_X_GYRO 0x00
soulx 0:b502ea2d6ebb 28 #define SELF_TEST_Y_GYRO 0x01
soulx 0:b502ea2d6ebb 29 #define SELF_TEST_Z_GYRO 0x02
soulx 0:b502ea2d6ebb 30
soulx 0:b502ea2d6ebb 31 /*
soulx 0:b502ea2d6ebb 32 #define X_FINE_GAIN 0x03 // [7:0] fine gain
soulx 0:b502ea2d6ebb 33 #define Y_FINE_GAIN 0x04
soulx 0:b502ea2d6ebb 34 #define Z_FINE_GAIN 0x05
soulx 0:b502ea2d6ebb 35 #define XA_OFFSET_H 0x06 // User-defined trim values for accelerometer
soulx 0:b502ea2d6ebb 36 #define XA_OFFSET_L_TC 0x07
soulx 0:b502ea2d6ebb 37 #define YA_OFFSET_H 0x08
soulx 0:b502ea2d6ebb 38 #define YA_OFFSET_L_TC 0x09
soulx 0:b502ea2d6ebb 39 #define ZA_OFFSET_H 0x0A
soulx 0:b502ea2d6ebb 40 #define ZA_OFFSET_L_TC 0x0B
soulx 0:b502ea2d6ebb 41 */
soulx 0:b502ea2d6ebb 42
soulx 0:b502ea2d6ebb 43 #define SELF_TEST_X_ACCEL 0x0D
soulx 0:b502ea2d6ebb 44 #define SELF_TEST_Y_ACCEL 0x0E
soulx 0:b502ea2d6ebb 45 #define SELF_TEST_Z_ACCEL 0x0F
soulx 0:b502ea2d6ebb 46
soulx 0:b502ea2d6ebb 47 #define SELF_TEST_A 0x10
soulx 0:b502ea2d6ebb 48
soulx 0:b502ea2d6ebb 49 #define XG_OFFSET_H 0x13 // User-defined trim values for gyroscope
soulx 0:b502ea2d6ebb 50 #define XG_OFFSET_L 0x14
soulx 0:b502ea2d6ebb 51 #define YG_OFFSET_H 0x15
soulx 0:b502ea2d6ebb 52 #define YG_OFFSET_L 0x16
soulx 0:b502ea2d6ebb 53 #define ZG_OFFSET_H 0x17
soulx 0:b502ea2d6ebb 54 #define ZG_OFFSET_L 0x18
soulx 0:b502ea2d6ebb 55 #define SMPLRT_DIV 0x19
soulx 0:b502ea2d6ebb 56 #define CONFIG 0x1A
soulx 0:b502ea2d6ebb 57 #define GYRO_CONFIG 0x1B
soulx 0:b502ea2d6ebb 58 #define ACCEL_CONFIG 0x1C
soulx 0:b502ea2d6ebb 59 #define ACCEL_CONFIG2 0x1D
soulx 0:b502ea2d6ebb 60 #define LP_ACCEL_ODR 0x1E
soulx 0:b502ea2d6ebb 61 #define WOM_THR 0x1F
soulx 0:b502ea2d6ebb 62
soulx 0:b502ea2d6ebb 63 #define MOT_DUR 0x20 // Duration counter threshold for motion interrupt generation, 1 kHz rate, LSB = 1 ms
soulx 0:b502ea2d6ebb 64 #define ZMOT_THR 0x21 // Zero-motion detection threshold bits [7:0]
soulx 0:b502ea2d6ebb 65 #define ZRMOT_DUR 0x22 // Duration counter threshold for zero motion interrupt generation, 16 Hz rate, LSB = 64 ms
soulx 0:b502ea2d6ebb 66
soulx 0:b502ea2d6ebb 67 #define FIFO_EN 0x23
soulx 0:b502ea2d6ebb 68 #define I2C_MST_CTRL 0x24
soulx 0:b502ea2d6ebb 69 #define I2C_SLV0_ADDR 0x25
soulx 0:b502ea2d6ebb 70 #define I2C_SLV0_REG 0x26
soulx 0:b502ea2d6ebb 71 #define I2C_SLV0_CTRL 0x27
soulx 0:b502ea2d6ebb 72 #define I2C_SLV1_ADDR 0x28
soulx 0:b502ea2d6ebb 73 #define I2C_SLV1_REG 0x29
soulx 0:b502ea2d6ebb 74 #define I2C_SLV1_CTRL 0x2A
soulx 0:b502ea2d6ebb 75 #define I2C_SLV2_ADDR 0x2B
soulx 0:b502ea2d6ebb 76 #define I2C_SLV2_REG 0x2C
soulx 0:b502ea2d6ebb 77 #define I2C_SLV2_CTRL 0x2D
soulx 0:b502ea2d6ebb 78 #define I2C_SLV3_ADDR 0x2E
soulx 0:b502ea2d6ebb 79 #define I2C_SLV3_REG 0x2F
soulx 0:b502ea2d6ebb 80 #define I2C_SLV3_CTRL 0x30
soulx 0:b502ea2d6ebb 81 #define I2C_SLV4_ADDR 0x31
soulx 0:b502ea2d6ebb 82 #define I2C_SLV4_REG 0x32
soulx 0:b502ea2d6ebb 83 #define I2C_SLV4_DO 0x33
soulx 0:b502ea2d6ebb 84 #define I2C_SLV4_CTRL 0x34
soulx 0:b502ea2d6ebb 85 #define I2C_SLV4_DI 0x35
soulx 0:b502ea2d6ebb 86 #define I2C_MST_STATUS 0x36
soulx 0:b502ea2d6ebb 87 #define INT_PIN_CFG 0x37
soulx 0:b502ea2d6ebb 88 #define INT_ENABLE 0x38
soulx 0:b502ea2d6ebb 89 #define DMP_INT_STATUS 0x39 // Check DMP interrupt
soulx 0:b502ea2d6ebb 90 #define INT_STATUS 0x3A
soulx 0:b502ea2d6ebb 91 #define ACCEL_XOUT_H 0x3B
soulx 0:b502ea2d6ebb 92 #define ACCEL_XOUT_L 0x3C
soulx 0:b502ea2d6ebb 93 #define ACCEL_YOUT_H 0x3D
soulx 0:b502ea2d6ebb 94 #define ACCEL_YOUT_L 0x3E
soulx 0:b502ea2d6ebb 95 #define ACCEL_ZOUT_H 0x3F
soulx 0:b502ea2d6ebb 96 #define ACCEL_ZOUT_L 0x40
soulx 0:b502ea2d6ebb 97 #define TEMP_OUT_H 0x41
soulx 0:b502ea2d6ebb 98 #define TEMP_OUT_L 0x42
soulx 0:b502ea2d6ebb 99 #define GYRO_XOUT_H 0x43
soulx 0:b502ea2d6ebb 100 #define GYRO_XOUT_L 0x44
soulx 0:b502ea2d6ebb 101 #define GYRO_YOUT_H 0x45
soulx 0:b502ea2d6ebb 102 #define GYRO_YOUT_L 0x46
soulx 0:b502ea2d6ebb 103 #define GYRO_ZOUT_H 0x47
soulx 0:b502ea2d6ebb 104 #define GYRO_ZOUT_L 0x48
soulx 0:b502ea2d6ebb 105 #define EXT_SENS_DATA_00 0x49
soulx 0:b502ea2d6ebb 106 #define EXT_SENS_DATA_01 0x4A
soulx 0:b502ea2d6ebb 107 #define EXT_SENS_DATA_02 0x4B
soulx 0:b502ea2d6ebb 108 #define EXT_SENS_DATA_03 0x4C
soulx 0:b502ea2d6ebb 109 #define EXT_SENS_DATA_04 0x4D
soulx 0:b502ea2d6ebb 110 #define EXT_SENS_DATA_05 0x4E
soulx 0:b502ea2d6ebb 111 #define EXT_SENS_DATA_06 0x4F
soulx 0:b502ea2d6ebb 112 #define EXT_SENS_DATA_07 0x50
soulx 0:b502ea2d6ebb 113 #define EXT_SENS_DATA_08 0x51
soulx 0:b502ea2d6ebb 114 #define EXT_SENS_DATA_09 0x52
soulx 0:b502ea2d6ebb 115 #define EXT_SENS_DATA_10 0x53
soulx 0:b502ea2d6ebb 116 #define EXT_SENS_DATA_11 0x54
soulx 0:b502ea2d6ebb 117 #define EXT_SENS_DATA_12 0x55
soulx 0:b502ea2d6ebb 118 #define EXT_SENS_DATA_13 0x56
soulx 0:b502ea2d6ebb 119 #define EXT_SENS_DATA_14 0x57
soulx 0:b502ea2d6ebb 120 #define EXT_SENS_DATA_15 0x58
soulx 0:b502ea2d6ebb 121 #define EXT_SENS_DATA_16 0x59
soulx 0:b502ea2d6ebb 122 #define EXT_SENS_DATA_17 0x5A
soulx 0:b502ea2d6ebb 123 #define EXT_SENS_DATA_18 0x5B
soulx 0:b502ea2d6ebb 124 #define EXT_SENS_DATA_19 0x5C
soulx 0:b502ea2d6ebb 125 #define EXT_SENS_DATA_20 0x5D
soulx 0:b502ea2d6ebb 126 #define EXT_SENS_DATA_21 0x5E
soulx 0:b502ea2d6ebb 127 #define EXT_SENS_DATA_22 0x5F
soulx 0:b502ea2d6ebb 128 #define EXT_SENS_DATA_23 0x60
soulx 0:b502ea2d6ebb 129 #define MOT_DETECT_STATUS 0x61
soulx 0:b502ea2d6ebb 130 #define I2C_SLV0_DO 0x63
soulx 0:b502ea2d6ebb 131 #define I2C_SLV1_DO 0x64
soulx 0:b502ea2d6ebb 132 #define I2C_SLV2_DO 0x65
soulx 0:b502ea2d6ebb 133 #define I2C_SLV3_DO 0x66
soulx 0:b502ea2d6ebb 134 #define I2C_MST_DELAY_CTRL 0x67
soulx 0:b502ea2d6ebb 135 #define SIGNAL_PATH_RESET 0x68
soulx 0:b502ea2d6ebb 136 #define MOT_DETECT_CTRL 0x69
soulx 0:b502ea2d6ebb 137 #define USER_CTRL 0x6A // Bit 7 enable DMP, bit 3 reset DMP
soulx 0:b502ea2d6ebb 138 #define PWR_MGMT_1 0x6B // Device defaults to the SLEEP mode
soulx 0:b502ea2d6ebb 139 #define PWR_MGMT_2 0x6C
soulx 0:b502ea2d6ebb 140 #define DMP_BANK 0x6D // Activates a specific bank in the DMP
soulx 0:b502ea2d6ebb 141 #define DMP_RW_PNT 0x6E // Set read/write pointer to a specific start address in specified DMP bank
soulx 0:b502ea2d6ebb 142 #define DMP_REG 0x6F // Register in DMP from which to read or to which to write
soulx 0:b502ea2d6ebb 143 #define DMP_REG_1 0x70
soulx 0:b502ea2d6ebb 144 #define DMP_REG_2 0x71
soulx 0:b502ea2d6ebb 145 #define FIFO_COUNTH 0x72
soulx 0:b502ea2d6ebb 146 #define FIFO_COUNTL 0x73
soulx 0:b502ea2d6ebb 147 #define FIFO_R_W 0x74
soulx 0:b502ea2d6ebb 148 #define WHO_AM_I_MPU9250 0x75 // Should return 0x71
soulx 0:b502ea2d6ebb 149 #define XA_OFFSET_H 0x77
soulx 0:b502ea2d6ebb 150 #define XA_OFFSET_L 0x78
soulx 0:b502ea2d6ebb 151 #define YA_OFFSET_H 0x7A
soulx 0:b502ea2d6ebb 152 #define YA_OFFSET_L 0x7B
soulx 0:b502ea2d6ebb 153 #define ZA_OFFSET_H 0x7D
soulx 0:b502ea2d6ebb 154 #define ZA_OFFSET_L 0x7E
soulx 0:b502ea2d6ebb 155
soulx 0:b502ea2d6ebb 156
soulx 0:b502ea2d6ebb 157 // Using the MSENSR-9250 breakout board, ADO is set to 0
soulx 0:b502ea2d6ebb 158 // Seven-bit device address is 110100 for ADO = 0 and 110101 for ADO = 1
soulx 0:b502ea2d6ebb 159 //mbed uses the eight-bit device address, so shift seven-bit addresses left by one!
soulx 0:b502ea2d6ebb 160 /*#define ADO 0
soulx 0:b502ea2d6ebb 161 #if ADO
soulx 0:b502ea2d6ebb 162 #define MPU9250_ADDRESS 0x69<<1 // Device address when ADO = 1
soulx 0:b502ea2d6ebb 163 #else
soulx 0:b502ea2d6ebb 164 #define MPU9250_ADDRESS 0x68<<1 // Device address when ADO = 0
soulx 0:b502ea2d6ebb 165 #endif*/