Diff: Nucleo_Encoder_16_bits.cpp

Revision:

3:f0450e2b0d47

Parent:

1:e82009479b5c

--- a/Nucleo_Encoder_16_bits.cpp	Wed Jun 08 21:34:36 2016 +0000
+++ b/Nucleo_Encoder_16_bits.cpp	Wed Jun 08 22:07:03 2016 +0000
@@ -1,12 +1,25 @@
 #include "Nucleo_Encoder_16_bits.h"
 
-int32_t Soft_32_Counter_TIM2, Soft_32_Counter_TIM3, Soft_32_Counter_TIM4, Soft_32_Counter_TIM5;
+int32_t Soft_32_Counter_TIM1, Soft_32_Counter_TIM2, Soft_32_Counter_TIM3, Soft_32_Counter_TIM4, Soft_32_Counter_TIM5;
+
+void Overflow_Routine_TIM1()
+{
+    if(TIM1->SR & 0x0001)
+    {
+        printf("Overflow Routine TIM2");
+        TIM1->SR &= 0xfffe;
+        if(!(TIM1->CR1&TIM_CR1_DIR))
+            Soft_32_Counter_TIM1 += 0xffff;
+        else
+            Soft_32_Counter_TIM1 -= 0xffff;
+    }
+}
 
 void Overflow_Routine_TIM2()
 {
     if(TIM2->SR & 0x0001)
     {
-        printf("Overflow Routine");
+        printf("Overflow Routine TIM2");
         TIM2->SR &= 0xfffe;
         if(!(TIM2->CR1&TIM_CR1_DIR))
             Soft_32_Counter_TIM2 += 0xffff;
@@ -19,7 +32,7 @@
 {
     if(TIM3->SR & 0x0001)
     {
-        printf("Overflow Routine");
+        printf("Overflow Routine TIM3");
         TIM3->SR &= 0xfffe;
         if(!(TIM3->CR1&TIM_CR1_DIR))
             Soft_32_Counter_TIM3 += 0xffff;
@@ -31,7 +44,7 @@
 {
     if(TIM4->SR & 0x0001)
     {
-        printf("Overflow Routine");
+        printf("Overflow Routine TIM4");
         TIM4->SR &= 0xfffe;
         if(!(TIM4->CR1&TIM_CR1_DIR))
             Soft_32_Counter_TIM4 += 0xffff;
@@ -43,7 +56,7 @@
 {
     if(TIM5->SR & 0x0001)
     {
-        printf("Overflow Routine");
+        printf("Overflow Routine TIM5");
         TIM5->SR &= 0xfffe;
         if(!(TIM5->CR1&TIM_CR1_DIR))
             Soft_32_Counter_TIM5 += 0xffff;