Tami Farber / microbit-dal

Revised to disable BLE for radio communication as needed.

Dependencies:   BLE_API nRF51822 mbed-dev-bin

Dependents:   microbit

source/asm/CortexContextSwitch.s.armcc@74:26717338739d, 2019-11-26 (annotated)

Committer:
tsfarber
Date:
Tue Nov 26 04:12:46 2019 +0000
Revision:
74:26717338739d
Parent:
12:755087a1ef83 
This program combines samples programs radio TX and radio RX so that both units can send or receive depending on which unit's buttons are pressed. Tested successfully. MicroBitConfig.h has been edited to disable BLE.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jonathan Austin 1:8aa5cdb4ab67 1 ; The MIT License (MIT)
Jonathan Austin 1:8aa5cdb4ab67 2
Jonathan Austin 1:8aa5cdb4ab67 3 ; Copyright (c) 2016 British Broadcasting Corporation.
Jonathan Austin 1:8aa5cdb4ab67 4 ; This software is provided by Lancaster University by arrangement with the BBC.
Jonathan Austin 1:8aa5cdb4ab67 5
Jonathan Austin 1:8aa5cdb4ab67 6 ; Permission is hereby granted, free of charge, to any person obtaining a
Jonathan Austin 1:8aa5cdb4ab67 7 ; copy of this software and associated documentation files (the "Software"),
Jonathan Austin 1:8aa5cdb4ab67 8 ; to deal in the Software without restriction, including without limitation
Jonathan Austin 1:8aa5cdb4ab67 9 ; the rights to use, copy, modify, merge, publish, distribute, sublicense,
Jonathan Austin 1:8aa5cdb4ab67 10 ; and/or sell copies of the Software, and to permit persons to whom the
Jonathan Austin 1:8aa5cdb4ab67 11 ; Software is furnished to do so, subject to the following conditions:
Jonathan Austin 1:8aa5cdb4ab67 12
Jonathan Austin 1:8aa5cdb4ab67 13 ; The above copyright notice and this permission notice shall be included in
Jonathan Austin 1:8aa5cdb4ab67 14 ; all copies or substantial portions of the Software.
Jonathan Austin 1:8aa5cdb4ab67 15
Jonathan Austin 1:8aa5cdb4ab67 16 ; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
Jonathan Austin 1:8aa5cdb4ab67 17 ; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
Jonathan Austin 1:8aa5cdb4ab67 18 ; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
Jonathan Austin 1:8aa5cdb4ab67 19 ; THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
Jonathan Austin 1:8aa5cdb4ab67 20 ; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
Jonathan Austin 1:8aa5cdb4ab67 21 ; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
Jonathan Austin 1:8aa5cdb4ab67 22 ; DEALINGS IN THE SOFTWARE.
Jonathan Austin 1:8aa5cdb4ab67 23
Jonathan Austin 1:8aa5cdb4ab67 24 AREA asm_func, CODE, READONLY
Jonathan Austin 1:8aa5cdb4ab67 25
Jonathan Austin 1:8aa5cdb4ab67 26 ; Export our context switching subroutine as a C function for use in mbed
Jonathan Austin 1:8aa5cdb4ab67 27 EXPORT swap_context
Jonathan Austin 1:8aa5cdb4ab67 28 EXPORT save_context
Jonathan Austin 1:8aa5cdb4ab67 29 EXPORT save_register_context
Jonathan Austin 1:8aa5cdb4ab67 30 EXPORT restore_register_context
Jonathan Austin 1:8aa5cdb4ab67 31
Jonathan Austin 1:8aa5cdb4ab67 32 ALIGN
Jonathan Austin 1:8aa5cdb4ab67 33
Jonathan Austin 1:8aa5cdb4ab67 34 ; R0 Contains a pointer to the TCB of the fibre being scheduled out.
Jonathan Austin 1:8aa5cdb4ab67 35 ; R1 Contains a pointer to the TCB of the fibre being scheduled in.
Jonathan Austin 1:8aa5cdb4ab67 36 ; R2 Contains a pointer to the base of the stack of the fibre being scheduled out.
Jonathan Austin 1:8aa5cdb4ab67 37 ; R3 Contains a pointer to the base of the stack of the fibre being scheduled in.
Jonathan Austin 1:8aa5cdb4ab67 38
Jonathan Austin 1:8aa5cdb4ab67 39 swap_context
Jonathan Austin 1:8aa5cdb4ab67 40
Jonathan Austin 1:8aa5cdb4ab67 41 ; Write our core registers into the TCB
Jonathan Austin 1:8aa5cdb4ab67 42 ; First, store the general registers
Jonathan Austin 1:8aa5cdb4ab67 43
Jonathan Austin 1:8aa5cdb4ab67 44 ; Skip this is we're given a NULL parameter for the TCB
Jonathan Austin 1:8aa5cdb4ab67 45 CMP R0, #0
Jonathan Austin 1:8aa5cdb4ab67 46 BEQ store_context_complete
Jonathan Austin 1:8aa5cdb4ab67 47
Jonathan Austin 1:8aa5cdb4ab67 48 STR R0, [R0,#0]
Jonathan Austin 1:8aa5cdb4ab67 49 STR R1, [R0,#4]
Jonathan Austin 1:8aa5cdb4ab67 50 STR R2, [R0,#8]
Jonathan Austin 1:8aa5cdb4ab67 51 STR R3, [R0,#12]
Jonathan Austin 1:8aa5cdb4ab67 52 STR R4, [R0,#16]
Jonathan Austin 1:8aa5cdb4ab67 53 STR R5, [R0,#20]
Jonathan Austin 1:8aa5cdb4ab67 54 STR R6, [R0,#24]
Jonathan Austin 1:8aa5cdb4ab67 55 STR R7, [R0,#28]
Jonathan Austin 1:8aa5cdb4ab67 56
Jonathan Austin 1:8aa5cdb4ab67 57 ; Now the high general purpose registers
Jonathan Austin 1:8aa5cdb4ab67 58 MOV R4, R8
Jonathan Austin 1:8aa5cdb4ab67 59 STR R4, [R0,#32]
Jonathan Austin 1:8aa5cdb4ab67 60 MOV R4, R9
Jonathan Austin 1:8aa5cdb4ab67 61 STR R4, [R0,#36]
Jonathan Austin 1:8aa5cdb4ab67 62 MOV R4, R10
Jonathan Austin 1:8aa5cdb4ab67 63 STR R4, [R0,#40]
Jonathan Austin 1:8aa5cdb4ab67 64 MOV R4, R11
Jonathan Austin 1:8aa5cdb4ab67 65 STR R4, [R0,#44]
Jonathan Austin 1:8aa5cdb4ab67 66 MOV R4, R12
Jonathan Austin 1:8aa5cdb4ab67 67 STR R4, [R0,#48]
Jonathan Austin 1:8aa5cdb4ab67 68
Jonathan Austin 1:8aa5cdb4ab67 69 ; Now the Stack and Link Register.
Jonathan Austin 1:8aa5cdb4ab67 70 ; As this context is only intended for use with a fiber scheduler,
Jonathan Austin 1:8aa5cdb4ab67 71 ; we don't need the PC.
Jonathan Austin 1:8aa5cdb4ab67 72 MOV R6, SP
Jonathan Austin 1:8aa5cdb4ab67 73 STR R6, [R0,#52]
Jonathan Austin 1:8aa5cdb4ab67 74 MOV R4, LR
Jonathan Austin 1:8aa5cdb4ab67 75 STR R4, [R0,#56]
Jonathan Austin 1:8aa5cdb4ab67 76
Jonathan Austin 1:8aa5cdb4ab67 77 store_context_complete
Jonathan Austin 1:8aa5cdb4ab67 78 ; Finally, Copy the stack. We do this to reduce RAM footprint, as stack is usually very small at the point
Jonathan Austin 1:8aa5cdb4ab67 79 ; of scheduling, but we need a lot of capacity for interrupt handling and other functions.
Jonathan Austin 1:8aa5cdb4ab67 80
Jonathan Austin 1:8aa5cdb4ab67 81 ; Skip this is we're given a NULL parameter for the stack.
Jonathan Austin 1:8aa5cdb4ab67 82 CMP R2, #0
Jonathan Austin 1:8aa5cdb4ab67 83 BEQ store_stack_complete
Jonathan Austin 1:8aa5cdb4ab67 84
Jonathan Austin 1:8aa5cdb4ab67 85 LDR R4, [R0,#60] ; Load R4 with the fiber's defined stack_base.
Jonathan Austin 1:8aa5cdb4ab67 86 store_stack
Jonathan Austin 1:8aa5cdb4ab67 87 SUBS R4, #4
Jonathan Austin 1:8aa5cdb4ab67 88 SUBS R2, #4
Jonathan Austin 1:8aa5cdb4ab67 89
Jonathan Austin 1:8aa5cdb4ab67 90 LDR R5, [R4]
Jonathan Austin 1:8aa5cdb4ab67 91 STR R5, [R2]
Jonathan Austin 1:8aa5cdb4ab67 92
Jonathan Austin 1:8aa5cdb4ab67 93 CMP R4, R6
Jonathan Austin 1:8aa5cdb4ab67 94 BNE store_stack
Jonathan Austin 1:8aa5cdb4ab67 95
Jonathan Austin 1:8aa5cdb4ab67 96 store_stack_complete
Jonathan Austin 1:8aa5cdb4ab67 97
Jonathan Austin 1:8aa5cdb4ab67 98 ;
Jonathan Austin 1:8aa5cdb4ab67 99 ; Now page in the new context.
Jonathan Austin 1:8aa5cdb4ab67 100 ; Update all registers except the PC. We can also safely ignore the STATUS register, as we're just a fiber scheduler.
Jonathan Austin 1:8aa5cdb4ab67 101 ;
Jonathan Austin 1:8aa5cdb4ab67 102 LDR R4, [R1, #56]
Jonathan Austin 1:8aa5cdb4ab67 103 MOV LR, R4
Jonathan Austin 1:8aa5cdb4ab67 104 LDR R6, [R1, #52]
Jonathan Austin 1:8aa5cdb4ab67 105 MOV SP, R6
Jonathan Austin 1:8aa5cdb4ab67 106
Jonathan Austin 1:8aa5cdb4ab67 107 ; Copy the stack in.
Jonathan Austin 1:8aa5cdb4ab67 108 ; n.b. we do this after setting the SP to make comparisons easier.
Jonathan Austin 1:8aa5cdb4ab67 109
Jonathan Austin 1:8aa5cdb4ab67 110 ; Skip this is we're given a NULL parameter for the stack.
Jonathan Austin 1:8aa5cdb4ab67 111 CMP R3, #0
Jonathan Austin 1:8aa5cdb4ab67 112 BEQ restore_stack_complete
Jonathan Austin 1:8aa5cdb4ab67 113
Jonathan Austin 1:8aa5cdb4ab67 114 LDR R4, [R1,#60] ; Load R4 with the fiber's defined stack_base.
Jonathan Austin 1:8aa5cdb4ab67 115
Jonathan Austin 1:8aa5cdb4ab67 116 restore_stack
Jonathan Austin 1:8aa5cdb4ab67 117 SUBS R4, #4
Jonathan Austin 1:8aa5cdb4ab67 118 SUBS R3, #4
Jonathan Austin 1:8aa5cdb4ab67 119
Jonathan Austin 1:8aa5cdb4ab67 120 LDR R5, [R3]
Jonathan Austin 1:8aa5cdb4ab67 121 STR R5, [R4]
Jonathan Austin 1:8aa5cdb4ab67 122
Jonathan Austin 1:8aa5cdb4ab67 123 CMP R4, R6
Jonathan Austin 1:8aa5cdb4ab67 124 BNE restore_stack
Jonathan Austin 1:8aa5cdb4ab67 125
Jonathan Austin 1:8aa5cdb4ab67 126 restore_stack_complete
Jonathan Austin 1:8aa5cdb4ab67 127 LDR R4, [R1, #48]
Jonathan Austin 1:8aa5cdb4ab67 128 MOV R12, R4
Jonathan Austin 1:8aa5cdb4ab67 129 LDR R4, [R1, #44]
Jonathan Austin 1:8aa5cdb4ab67 130 MOV R11, R4
Jonathan Austin 1:8aa5cdb4ab67 131 LDR R4, [R1, #40]
Jonathan Austin 1:8aa5cdb4ab67 132 MOV R10, R4
Jonathan Austin 1:8aa5cdb4ab67 133 LDR R4, [R1, #36]
Jonathan Austin 1:8aa5cdb4ab67 134 MOV R9, R4
Jonathan Austin 1:8aa5cdb4ab67 135 LDR R4, [R1, #32]
Jonathan Austin 1:8aa5cdb4ab67 136 MOV R8, R4
Jonathan Austin 1:8aa5cdb4ab67 137
Jonathan Austin 1:8aa5cdb4ab67 138 LDR R7, [R1, #28]
Jonathan Austin 1:8aa5cdb4ab67 139 LDR R6, [R1, #24]
Jonathan Austin 1:8aa5cdb4ab67 140 LDR R5, [R1, #20]
Jonathan Austin 1:8aa5cdb4ab67 141 LDR R4, [R1, #16]
Jonathan Austin 1:8aa5cdb4ab67 142 LDR R3, [R1, #12]
Jonathan Austin 1:8aa5cdb4ab67 143 LDR R2, [R1, #8]
Jonathan Austin 1:8aa5cdb4ab67 144 LDR R0, [R1, #0]
Jonathan Austin 1:8aa5cdb4ab67 145 LDR R1, [R1, #4]
Jonathan Austin 1:8aa5cdb4ab67 146
Jonathan Austin 1:8aa5cdb4ab67 147 ; Return to caller (scheduler).
Jonathan Austin 1:8aa5cdb4ab67 148 BX LR
Jonathan Austin 1:8aa5cdb4ab67 149
Jonathan Austin 1:8aa5cdb4ab67 150
Jonathan Austin 1:8aa5cdb4ab67 151 ; R0 Contains a pointer to the TCB of the fibre to snapshot
Jonathan Austin 1:8aa5cdb4ab67 152 ; R1 Contains a pointer to the base of the stack of the fibre being snapshotted
Jonathan Austin 1:8aa5cdb4ab67 153
Jonathan Austin 1:8aa5cdb4ab67 154 save_context
Jonathan Austin 1:8aa5cdb4ab67 155
Jonathan Austin 1:8aa5cdb4ab67 156 ; Write our core registers into the TCB
Jonathan Austin 1:8aa5cdb4ab67 157 ; First, store the general registers
Jonathan Austin 1:8aa5cdb4ab67 158
Jonathan Austin 1:8aa5cdb4ab67 159 STR R0, [R0,#0]
Jonathan Austin 1:8aa5cdb4ab67 160 STR R1, [R0,#4]
Jonathan Austin 1:8aa5cdb4ab67 161 STR R2, [R0,#8]
Jonathan Austin 1:8aa5cdb4ab67 162 STR R3, [R0,#12]
Jonathan Austin 1:8aa5cdb4ab67 163 STR R4, [R0,#16]
Jonathan Austin 1:8aa5cdb4ab67 164 STR R5, [R0,#20]
Jonathan Austin 1:8aa5cdb4ab67 165 STR R6, [R0,#24]
Jonathan Austin 1:8aa5cdb4ab67 166 STR R7, [R0,#28]
Jonathan Austin 1:8aa5cdb4ab67 167
Jonathan Austin 1:8aa5cdb4ab67 168 ; Now the high general purpose registers
Jonathan Austin 1:8aa5cdb4ab67 169 MOV R4, R8
Jonathan Austin 1:8aa5cdb4ab67 170 STR R4, [R0,#32]
Jonathan Austin 1:8aa5cdb4ab67 171 MOV R4, R9
Jonathan Austin 1:8aa5cdb4ab67 172 STR R4, [R0,#36]
Jonathan Austin 1:8aa5cdb4ab67 173 MOV R4, R10
Jonathan Austin 1:8aa5cdb4ab67 174 STR R4, [R0,#40]
Jonathan Austin 1:8aa5cdb4ab67 175 MOV R4, R11
Jonathan Austin 1:8aa5cdb4ab67 176 STR R4, [R0,#44]
Jonathan Austin 1:8aa5cdb4ab67 177 MOV R4, R12
Jonathan Austin 1:8aa5cdb4ab67 178 STR R4, [R0,#48]
Jonathan Austin 1:8aa5cdb4ab67 179
Jonathan Austin 1:8aa5cdb4ab67 180 ; Now the Stack and Link Register.
Jonathan Austin 1:8aa5cdb4ab67 181 ; As this context is only intended for use with a fiber scheduler,
Jonathan Austin 1:8aa5cdb4ab67 182 ; we don't need the PC.
Jonathan Austin 1:8aa5cdb4ab67 183 MOV R6, SP
Jonathan Austin 1:8aa5cdb4ab67 184 STR R6, [R0,#52]
Jonathan Austin 1:8aa5cdb4ab67 185 MOV R4, LR
Jonathan Austin 1:8aa5cdb4ab67 186 STR R4, [R0,#56]
Jonathan Austin 1:8aa5cdb4ab67 187
Jonathan Austin 1:8aa5cdb4ab67 188 ; Finally, Copy the stack. We do this to reduce RAM footprint, as stackis usually very small at the point
Jonathan Austin 1:8aa5cdb4ab67 189 ; of sceduling, but we need a lot of capacity for interrupt handling and other functions.
Jonathan Austin 1:8aa5cdb4ab67 190
Jonathan Austin 1:8aa5cdb4ab67 191 LDR R4, [R0,#60] ; Load R4 with the fiber's defined stack_base.
Jonathan Austin 1:8aa5cdb4ab67 192
Jonathan Austin 1:8aa5cdb4ab67 193 store_stack1
Jonathan Austin 1:8aa5cdb4ab67 194 SUBS R4, #4
Jonathan Austin 1:8aa5cdb4ab67 195 SUBS R1, #4
Jonathan Austin 1:8aa5cdb4ab67 196
Jonathan Austin 1:8aa5cdb4ab67 197 LDR R5, [R4]
Jonathan Austin 1:8aa5cdb4ab67 198 STR R5, [R1]
Jonathan Austin 1:8aa5cdb4ab67 199
Jonathan Austin 1:8aa5cdb4ab67 200 CMP R4, R6
Jonathan Austin 1:8aa5cdb4ab67 201 BNE store_stack1
Jonathan Austin 1:8aa5cdb4ab67 202
Jonathan Austin 1:8aa5cdb4ab67 203 ; Restore scratch registers.
Jonathan Austin 1:8aa5cdb4ab67 204
Jonathan Austin 1:8aa5cdb4ab67 205 LDR R7, [R0, #28]
Jonathan Austin 1:8aa5cdb4ab67 206 LDR R6, [R0, #24]
Jonathan Austin 1:8aa5cdb4ab67 207 LDR R5, [R0, #20]
Jonathan Austin 1:8aa5cdb4ab67 208 LDR R4, [R0, #16]
Jonathan Austin 1:8aa5cdb4ab67 209
Jonathan Austin 1:8aa5cdb4ab67 210 ; Return to caller (scheduler).
Jonathan Austin 1:8aa5cdb4ab67 211 BX LR
Jonathan Austin 1:8aa5cdb4ab67 212
Jonathan Austin 1:8aa5cdb4ab67 213
Jonathan Austin 1:8aa5cdb4ab67 214 ; R0 Contains a pointer to the TCB of the fiber to snapshot
Jonathan Austin 1:8aa5cdb4ab67 215 save_register_context
Jonathan Austin 1:8aa5cdb4ab67 216
Jonathan Austin 1:8aa5cdb4ab67 217 ; Write our core registers into the TCB
Jonathan Austin 1:8aa5cdb4ab67 218 ; First, store the general registers
Jonathan Austin 1:8aa5cdb4ab67 219
Jonathan Austin 1:8aa5cdb4ab67 220 STR R0, [R0,#0]
Jonathan Austin 1:8aa5cdb4ab67 221 STR R1, [R0,#4]
Jonathan Austin 1:8aa5cdb4ab67 222 STR R2, [R0,#8]
Jonathan Austin 1:8aa5cdb4ab67 223 STR R3, [R0,#12]
Jonathan Austin 1:8aa5cdb4ab67 224 STR R4, [R0,#16]
Jonathan Austin 1:8aa5cdb4ab67 225 STR R5, [R0,#20]
Jonathan Austin 1:8aa5cdb4ab67 226 STR R6, [R0,#24]
Jonathan Austin 1:8aa5cdb4ab67 227 STR R7, [R0,#28]
Jonathan Austin 1:8aa5cdb4ab67 228
Jonathan Austin 1:8aa5cdb4ab67 229 ; Now the high general purpose registers
Jonathan Austin 1:8aa5cdb4ab67 230 MOV R4, R8
Jonathan Austin 1:8aa5cdb4ab67 231 STR R4, [R0,#32]
Jonathan Austin 1:8aa5cdb4ab67 232 MOV R4, R9
Jonathan Austin 1:8aa5cdb4ab67 233 STR R4, [R0,#36]
Jonathan Austin 1:8aa5cdb4ab67 234 MOV R4, R10
Jonathan Austin 1:8aa5cdb4ab67 235 STR R4, [R0,#40]
Jonathan Austin 1:8aa5cdb4ab67 236 MOV R4, R11
Jonathan Austin 1:8aa5cdb4ab67 237 STR R4, [R0,#44]
Jonathan Austin 1:8aa5cdb4ab67 238 MOV R4, R12
Jonathan Austin 1:8aa5cdb4ab67 239 STR R4, [R0,#48]
Jonathan Austin 1:8aa5cdb4ab67 240
Jonathan Austin 1:8aa5cdb4ab67 241 ; Now the Stack Pointer and Link Register.
Jonathan Austin 1:8aa5cdb4ab67 242 ; As this context is only intended for use with a fiber scheduler,
Jonathan Austin 1:8aa5cdb4ab67 243 ; we don't need the PC.
Jonathan Austin 1:8aa5cdb4ab67 244 MOV R4, SP
Jonathan Austin 1:8aa5cdb4ab67 245 STR R4, [R0,#52]
Jonathan Austin 1:8aa5cdb4ab67 246 MOV R4, LR
Jonathan Austin 1:8aa5cdb4ab67 247 STR R4, [R0,#56]
Jonathan Austin 1:8aa5cdb4ab67 248
Jonathan Austin 1:8aa5cdb4ab67 249 ; Restore scratch registers.
Jonathan Austin 1:8aa5cdb4ab67 250 LDR R4, [R0, #16]
Jonathan Austin 1:8aa5cdb4ab67 251
Jonathan Austin 1:8aa5cdb4ab67 252 ; Return to caller (scheduler).
Jonathan Austin 1:8aa5cdb4ab67 253 BX LR
Jonathan Austin 1:8aa5cdb4ab67 254
Jonathan Austin 1:8aa5cdb4ab67 255
Jonathan Austin 1:8aa5cdb4ab67 256 restore_register_context
Jonathan Austin 1:8aa5cdb4ab67 257
Jonathan Austin 1:8aa5cdb4ab67 258 ;
Jonathan Austin 1:8aa5cdb4ab67 259 ; Now page in the new context.
Jonathan Austin 1:8aa5cdb4ab67 260 ; Update all registers except the PC. We can also safely ignore the STATUS register, as we're just a fiber scheduler.
Jonathan Austin 1:8aa5cdb4ab67 261 ;
Jonathan Austin 1:8aa5cdb4ab67 262 LDR R4, [R0, #56]
Jonathan Austin 1:8aa5cdb4ab67 263 MOV LR, R4
Jonathan Austin 1:8aa5cdb4ab67 264 LDR R4, [R0, #52]
Jonathan Austin 1:8aa5cdb4ab67 265 MOV SP, R4
Jonathan Austin 1:8aa5cdb4ab67 266
Jonathan Austin 1:8aa5cdb4ab67 267 ; High registers...
Jonathan Austin 1:8aa5cdb4ab67 268 LDR R4, [R0, #48]
Jonathan Austin 1:8aa5cdb4ab67 269 MOV R12, R4
Jonathan Austin 1:8aa5cdb4ab67 270 LDR R4, [R0, #44]
Jonathan Austin 1:8aa5cdb4ab67 271 MOV R11, R4
Jonathan Austin 1:8aa5cdb4ab67 272 LDR R4, [R0, #40]
Jonathan Austin 1:8aa5cdb4ab67 273 MOV R10, R4
Jonathan Austin 1:8aa5cdb4ab67 274 LDR R4, [R0, #36]
Jonathan Austin 1:8aa5cdb4ab67 275 MOV R9, R4
Jonathan Austin 1:8aa5cdb4ab67 276 LDR R4, [R0, #32]
Jonathan Austin 1:8aa5cdb4ab67 277 MOV R8, R4
Jonathan Austin 1:8aa5cdb4ab67 278
Jonathan Austin 1:8aa5cdb4ab67 279 ; Low registers...
Jonathan Austin 1:8aa5cdb4ab67 280 LDR R7, [R0, #28]
Jonathan Austin 1:8aa5cdb4ab67 281 LDR R6, [R0, #24]
Jonathan Austin 1:8aa5cdb4ab67 282 LDR R5, [R0, #20]
Jonathan Austin 1:8aa5cdb4ab67 283 LDR R4, [R0, #16]
Jonathan Austin 1:8aa5cdb4ab67 284 LDR R3, [R0, #12]
Jonathan Austin 1:8aa5cdb4ab67 285 LDR R2, [R0, #8]
Jonathan Austin 1:8aa5cdb4ab67 286 LDR R0, [R0, #0]
Jonathan Austin 1:8aa5cdb4ab67 287 LDR R1, [R0, #4]
Jonathan Austin 1:8aa5cdb4ab67 288
Jonathan Austin 1:8aa5cdb4ab67 289 ; Return to caller (normally the scheduler).
Jonathan Austin 1:8aa5cdb4ab67 290 BX LR
Jonathan Austin 1:8aa5cdb4ab67 291
Jonathan Austin 1:8aa5cdb4ab67 292 ALIGN
Jonathan Austin 1:8aa5cdb4ab67 293 END