Darren Ulrich / UniGraphic

Added SPI burst mode to spi 8 bit.

Dependents:   Bicycl_Computer_NUCLEO-F411RE Bicycl_Computer_NUCLEO-L476RG

Fork of UniGraphic by GraphicsDisplay

Added SPI burst mode to this graphics driver. If whoever wants this rolled in to repository let me know. I replaced _spi.write(); with fastWrite(); and clearRX();

SPI8.cpp

// need to re-create SPI firmware to access SPI handle
static SPI_HandleTypeDef SpiHandle;

void SPI8::fastWrite(int data) {
    
      SpiHandle.Instance = SPI1;
    // Check if data is transmitted
    while ((SpiHandle.Instance->SR & SPI_SR_TXE) == 0);
    SpiHandle.Instance->DR = data;
}
    
void SPI8::clearRX( void ) {
        SpiHandle.Instance = SPI1;
    //Check if the RX buffer is busy
    //While busy, keep checking
    while (SpiHandle.Instance->SR & SPI_SR_BSY){   
        // Check RX buffer readable
        while ((SpiHandle.Instance->SR & SPI_SR_RXNE) == 0);
        int dummy = SpiHandle.Instance->DR;
    }
}

Diff: Inits/SSD1306.cpp

Revision:
13:d8c593fa7705
Parent:
12:9c8f3076347c
Child:
15:b9483ba842c8
diff -r 9c8f3076347c -r d8c593fa7705 Inits/SSD1306.cpp
--- a/Inits/SSD1306.cpp	Sun Feb 22 00:05:34 2015 +0000
+++ b/Inits/SSD1306.cpp	Sun Feb 22 16:13:11 2015 +0000
@@ -64,38 +64,38 @@
   //  wr_cmd8(0xE2);   //  sw reset
     wait_ms(15);
     
-    wr_cmd8(SSD1306_DISPLAYOFF);   
-    wr_cmd8(SSD1306_SETDISPLAYCLOCKDIV);   
-    wr_cmd8(0x80); 
-    wr_cmd8(SSD1306_SETMULTIPLEX);
-    wr_cmd8(63);
+    wr_cmd8(SSD1306_DISPLAYOFF);    // no problem in SPI_16 for single byte cmds
+    wr_cmd16((SSD1306_SETDISPLAYCLOCKDIV<<8)|0x80);   // wr_cmd16 for multibyte cmds issue in SPI16 mode
+  //  wr_cmd8(0x80); // in SPI_16 it would become 0xE380 and will break things up
+    wr_cmd16((SSD1306_SETMULTIPLEX<<8)|63);
+ //   wr_cmd8(63);
     
-    wr_cmd8(SSD1306_SETDISPLAYOFFSET);
-    wr_cmd8(0x0);
+    wr_cmd16((SSD1306_SETDISPLAYOFFSET<<8)|0x00);
+ //   wr_cmd8(0x0);
     
     wr_cmd8(SSD1306_SETSTARTLINE | 0x0);            // line #0
 
-    wr_cmd8(SSD1306_CHARGEPUMP);
-    wr_cmd8(0x14);                         // 0x10 
+    wr_cmd16((SSD1306_CHARGEPUMP<<8)|0x14);
+  //  wr_cmd8(0x14);                         // 0x10 
 
-    wr_cmd8(SSD1306_MEMORYMODE);
-    wr_cmd8(0x00);                                  // 0x0 act like ks0108
+    wr_cmd16((SSD1306_MEMORYMODE<<8)|0x00);
+ //   wr_cmd8(0x00);                                  // 0x0 act like ks0108
 
     wr_cmd8(SSD1306_SEGREMAP ); //| 0x1);
 
     wr_cmd8(SSD1306_COMSCANDEC);
 
-    wr_cmd8(SSD1306_SETCOMPINS);
-    wr_cmd8(0x12);                           //        LCDSIZE_Y == 32 ? 0x02 : 0x12);        
+    wr_cmd16((SSD1306_SETCOMPINS<<8)|0x12);
+  //  wr_cmd8(0x12);                           //        LCDSIZE_Y == 32 ? 0x02 : 0x12);        
 
-    wr_cmd8(SSD1306_SETCONTRAST);
-    wr_cmd8(0xCF);                              //  _rawHeight == 32 ? 0x8F : ((vccstate == SSD1306_EXTERNALVCC) ? 0x9F : 0xCF) );
+    wr_cmd16((SSD1306_SETCONTRAST<<8)|0xCF);
+ //   wr_cmd8(0xCF);                              //  _rawHeight == 32 ? 0x8F : ((vccstate == SSD1306_EXTERNALVCC) ? 0x9F : 0xCF) );
 
-    wr_cmd8(SSD1306_SETPRECHARGE);
-    wr_cmd8(0xF1);                               // : 0x22);
+    wr_cmd16((SSD1306_SETPRECHARGE<<8)|0xF1);
+ //   wr_cmd8(0xF1);                               // : 0x22);
 
-    wr_cmd8(SSD1306_SETVCOMDETECT);
-    wr_cmd8(0x40);
+    wr_cmd16((SSD1306_SETVCOMDETECT<<8)|0x40);
+ //   wr_cmd8(0x40);
 
     wr_cmd8(SSD1306_DISPLAYALLON_RESUME);