Added SPI burst mode to spi 8 bit.
Dependents: Bicycl_Computer_NUCLEO-F411RE Bicycl_Computer_NUCLEO-L476RG
Fork of UniGraphic by
Added SPI burst mode to this graphics driver. If whoever wants this rolled in to repository let me know. I replaced _spi.write(); with fastWrite(); and clearRX();
SPI8.cpp
// need to re-create SPI firmware to access SPI handle static SPI_HandleTypeDef SpiHandle; void SPI8::fastWrite(int data) { SpiHandle.Instance = SPI1; // Check if data is transmitted while ((SpiHandle.Instance->SR & SPI_SR_TXE) == 0); SpiHandle.Instance->DR = data; } void SPI8::clearRX( void ) { SpiHandle.Instance = SPI1; //Check if the RX buffer is busy //While busy, keep checking while (SpiHandle.Instance->SR & SPI_SR_BSY){ // Check RX buffer readable while ((SpiHandle.Instance->SR & SPI_SR_RXNE) == 0); int dummy = SpiHandle.Instance->DR; } }
Protocols/SPI8.cpp@34:7eea44b19734, 2017-04-28 (annotated)
- Committer:
- trevieze
- Date:
- Fri Apr 28 01:45:26 2017 +0000
- Revision:
- 34:7eea44b19734
- Parent:
- 33:e3b3181a57e2
Burst for 8 bit spi.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Geremia | 4:12ba0ecc2c1f | 1 | /* mbed UniGraphic library - SPI8 protocol class |
Geremia | 4:12ba0ecc2c1f | 2 | * Copyright (c) 2015 Giuliano Dianda |
Geremia | 4:12ba0ecc2c1f | 3 | * Released under the MIT License: http://mbed.org/license/mit |
Geremia | 4:12ba0ecc2c1f | 4 | * |
Geremia | 4:12ba0ecc2c1f | 5 | * Derived work of: |
Geremia | 4:12ba0ecc2c1f | 6 | * |
Geremia | 4:12ba0ecc2c1f | 7 | * mbed library for 240*320 pixel display TFT based on ILI9341 LCD Controller |
Geremia | 4:12ba0ecc2c1f | 8 | * Copyright (c) 2013 Peter Drescher - DC2PD |
Geremia | 4:12ba0ecc2c1f | 9 | * |
Geremia | 4:12ba0ecc2c1f | 10 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
Geremia | 4:12ba0ecc2c1f | 11 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
Geremia | 4:12ba0ecc2c1f | 12 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
Geremia | 4:12ba0ecc2c1f | 13 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
Geremia | 4:12ba0ecc2c1f | 14 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
Geremia | 4:12ba0ecc2c1f | 15 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
Geremia | 4:12ba0ecc2c1f | 16 | * THE SOFTWARE. |
Geremia | 4:12ba0ecc2c1f | 17 | */ |
Geremia | 4:12ba0ecc2c1f | 18 | |
Geremia | 0:75ec1b3cde17 | 19 | #include "SPI8.h" |
Geremia | 0:75ec1b3cde17 | 20 | |
Geremia | 0:75ec1b3cde17 | 21 | //#define USE_CS |
Geremia | 0:75ec1b3cde17 | 22 | |
Geremia | 1:ff019d22b275 | 23 | SPI8::SPI8(int Hz, PinName mosi, PinName miso, PinName sclk, PinName CS, PinName reset, PinName DC) |
Geremia | 0:75ec1b3cde17 | 24 | : _CS(CS), _spi(mosi, miso, sclk), _reset(reset), _DC(DC) |
Geremia | 0:75ec1b3cde17 | 25 | { |
Geremia | 0:75ec1b3cde17 | 26 | _reset = 1; |
Geremia | 0:75ec1b3cde17 | 27 | _DC=1; |
Geremia | 0:75ec1b3cde17 | 28 | _CS=1; |
Geremia | 0:75ec1b3cde17 | 29 | _spi.format(8,0); // 8 bit spi mode 0 |
Geremia | 0:75ec1b3cde17 | 30 | // _spi.frequency(12000000); // 10 Mhz SPI clock, 12mhz for F411 |
Geremia | 1:ff019d22b275 | 31 | _spi.frequency(Hz); |
Geremia | 0:75ec1b3cde17 | 32 | hw_reset(); |
Geremia | 0:75ec1b3cde17 | 33 | } |
Geremia | 0:75ec1b3cde17 | 34 | |
Geremia | 1:ff019d22b275 | 35 | void SPI8::wr_cmd8(unsigned char cmd) |
Geremia | 0:75ec1b3cde17 | 36 | { |
Geremia | 0:75ec1b3cde17 | 37 | #ifdef USE_CS |
Geremia | 0:75ec1b3cde17 | 38 | _CS = 0; |
Geremia | 0:75ec1b3cde17 | 39 | #endif |
Geremia | 0:75ec1b3cde17 | 40 | _DC.write(0); // 0=cmd |
Geremia | 0:75ec1b3cde17 | 41 | _spi.write(cmd); // write 8bit |
Geremia | 0:75ec1b3cde17 | 42 | #ifdef USE_CS |
Geremia | 0:75ec1b3cde17 | 43 | _CS = 1; |
Geremia | 0:75ec1b3cde17 | 44 | #endif |
Geremia | 0:75ec1b3cde17 | 45 | } |
Geremia | 1:ff019d22b275 | 46 | void SPI8::wr_data8(unsigned char data) |
Geremia | 0:75ec1b3cde17 | 47 | { |
Geremia | 0:75ec1b3cde17 | 48 | #ifdef USE_CS |
Geremia | 0:75ec1b3cde17 | 49 | _CS = 0; |
Geremia | 0:75ec1b3cde17 | 50 | #endif |
Geremia | 0:75ec1b3cde17 | 51 | _DC.write(1); // 1=data |
trevieze | 33:e3b3181a57e2 | 52 | //_spi.write(data); // write 8bit |
trevieze | 33:e3b3181a57e2 | 53 | fastWrite(data); |
trevieze | 33:e3b3181a57e2 | 54 | clearRX(); |
trevieze | 33:e3b3181a57e2 | 55 | |
Geremia | 0:75ec1b3cde17 | 56 | #ifdef USE_CS |
Geremia | 0:75ec1b3cde17 | 57 | _CS = 1; |
Geremia | 0:75ec1b3cde17 | 58 | #endif |
Geremia | 0:75ec1b3cde17 | 59 | } |
Geremia | 1:ff019d22b275 | 60 | void SPI8::wr_cmd16(unsigned short cmd) |
Geremia | 1:ff019d22b275 | 61 | { |
Geremia | 1:ff019d22b275 | 62 | #ifdef USE_CS |
Geremia | 1:ff019d22b275 | 63 | _CS = 0; |
Geremia | 1:ff019d22b275 | 64 | #endif |
Geremia | 1:ff019d22b275 | 65 | _DC.write(0); // 0=cmd |
Geremia | 1:ff019d22b275 | 66 | _spi.write(cmd>>8); // write 8bit |
Geremia | 1:ff019d22b275 | 67 | _spi.write(cmd&0xFF); // write 8bit |
Geremia | 1:ff019d22b275 | 68 | #ifdef USE_CS |
Geremia | 1:ff019d22b275 | 69 | _CS = 1; |
Geremia | 1:ff019d22b275 | 70 | #endif |
Geremia | 1:ff019d22b275 | 71 | } |
Geremia | 1:ff019d22b275 | 72 | void SPI8::wr_data16(unsigned short data) |
Geremia | 1:ff019d22b275 | 73 | { |
Geremia | 1:ff019d22b275 | 74 | #ifdef USE_CS |
Geremia | 1:ff019d22b275 | 75 | _CS = 0; |
Geremia | 1:ff019d22b275 | 76 | #endif |
Geremia | 1:ff019d22b275 | 77 | _DC.write(1); // 1=data |
trevieze | 33:e3b3181a57e2 | 78 | //_spi.write(data>>8); // write 8bit |
trevieze | 33:e3b3181a57e2 | 79 | //_spi.write(data&0xFF); // write 8bit |
trevieze | 33:e3b3181a57e2 | 80 | fastWrite(data>>8); |
trevieze | 33:e3b3181a57e2 | 81 | fastWrite(data&0xFF); |
trevieze | 33:e3b3181a57e2 | 82 | clearRX(); |
Geremia | 1:ff019d22b275 | 83 | #ifdef USE_CS |
Geremia | 1:ff019d22b275 | 84 | _CS = 1; |
Geremia | 1:ff019d22b275 | 85 | #endif |
Geremia | 1:ff019d22b275 | 86 | } |
Geremia | 4:12ba0ecc2c1f | 87 | void SPI8::wr_gram(unsigned short data) |
Geremia | 4:12ba0ecc2c1f | 88 | { |
Geremia | 4:12ba0ecc2c1f | 89 | #ifdef USE_CS |
Geremia | 4:12ba0ecc2c1f | 90 | _CS = 0; |
Geremia | 4:12ba0ecc2c1f | 91 | #endif |
Geremia | 4:12ba0ecc2c1f | 92 | _DC.write(1); // 1=data |
trevieze | 33:e3b3181a57e2 | 93 | //_spi.write(data>>8); // write 8bit |
trevieze | 33:e3b3181a57e2 | 94 | // _spi.write(data&0xFF); // write 8bit |
trevieze | 33:e3b3181a57e2 | 95 | fastWrite(data>>8); |
trevieze | 33:e3b3181a57e2 | 96 | fastWrite(data&0xFF); |
trevieze | 33:e3b3181a57e2 | 97 | clearRX(); |
trevieze | 33:e3b3181a57e2 | 98 | |
Geremia | 4:12ba0ecc2c1f | 99 | #ifdef USE_CS |
Geremia | 4:12ba0ecc2c1f | 100 | _CS = 1; |
Geremia | 4:12ba0ecc2c1f | 101 | #endif |
Geremia | 4:12ba0ecc2c1f | 102 | } |
Geremia | 4:12ba0ecc2c1f | 103 | void SPI8::wr_gram(unsigned short data, unsigned int count) |
Geremia | 1:ff019d22b275 | 104 | { |
Geremia | 1:ff019d22b275 | 105 | #ifdef USE_CS |
Geremia | 1:ff019d22b275 | 106 | _CS = 0; |
Geremia | 1:ff019d22b275 | 107 | #endif |
Geremia | 1:ff019d22b275 | 108 | _DC.write(1); // 1=data |
Geremia | 1:ff019d22b275 | 109 | if((data>>8)==(data&0xFF)) |
Geremia | 1:ff019d22b275 | 110 | { |
Geremia | 1:ff019d22b275 | 111 | count<<=1; |
Geremia | 1:ff019d22b275 | 112 | while(count) |
Geremia | 1:ff019d22b275 | 113 | { |
trevieze | 34:7eea44b19734 | 114 | //_spi.write(data); // write 8bit |
trevieze | 34:7eea44b19734 | 115 | fastWrite(data); |
Geremia | 1:ff019d22b275 | 116 | count--; |
Geremia | 1:ff019d22b275 | 117 | } |
trevieze | 34:7eea44b19734 | 118 | clearRX(); |
Geremia | 1:ff019d22b275 | 119 | } |
Geremia | 1:ff019d22b275 | 120 | else |
Geremia | 1:ff019d22b275 | 121 | { |
Geremia | 1:ff019d22b275 | 122 | while(count) |
Geremia | 1:ff019d22b275 | 123 | { |
trevieze | 33:e3b3181a57e2 | 124 | //_spi.write(data>>8); // write 8bit |
trevieze | 33:e3b3181a57e2 | 125 | //_spi.write(data&0xFF); // write 8bit |
trevieze | 34:7eea44b19734 | 126 | fastWrite(data>>8); |
trevieze | 34:7eea44b19734 | 127 | fastWrite(data&0xFF); |
trevieze | 33:e3b3181a57e2 | 128 | count--; |
Geremia | 1:ff019d22b275 | 129 | } |
trevieze | 34:7eea44b19734 | 130 | clearRX(); |
Geremia | 1:ff019d22b275 | 131 | } |
Geremia | 1:ff019d22b275 | 132 | #ifdef USE_CS |
Geremia | 1:ff019d22b275 | 133 | _CS = 1; |
Geremia | 1:ff019d22b275 | 134 | #endif |
Geremia | 1:ff019d22b275 | 135 | } |
Geremia | 4:12ba0ecc2c1f | 136 | void SPI8::wr_grambuf(unsigned short* data, unsigned int lenght) |
Geremia | 1:ff019d22b275 | 137 | { |
Geremia | 1:ff019d22b275 | 138 | #ifdef USE_CS |
Geremia | 1:ff019d22b275 | 139 | _CS = 0; |
Geremia | 1:ff019d22b275 | 140 | #endif |
Geremia | 1:ff019d22b275 | 141 | _DC.write(1); // 1=data |
Geremia | 1:ff019d22b275 | 142 | while(lenght) |
Geremia | 1:ff019d22b275 | 143 | { |
trevieze | 33:e3b3181a57e2 | 144 | //_spi.write((*data)>>8); // write 8bit |
trevieze | 33:e3b3181a57e2 | 145 | //_spi.write((*data)&0xFF); // write 8bit |
trevieze | 34:7eea44b19734 | 146 | fastWrite(*data>>8); |
trevieze | 34:7eea44b19734 | 147 | fastWrite(*data&0xFF); |
Geremia | 1:ff019d22b275 | 148 | data++; |
Geremia | 0:75ec1b3cde17 | 149 | lenght--; |
Geremia | 0:75ec1b3cde17 | 150 | } |
trevieze | 34:7eea44b19734 | 151 | clearRX(); |
Geremia | 0:75ec1b3cde17 | 152 | #ifdef USE_CS |
Geremia | 0:75ec1b3cde17 | 153 | _CS = 1; |
Geremia | 0:75ec1b3cde17 | 154 | #endif |
Geremia | 0:75ec1b3cde17 | 155 | } |
Geremia | 11:b842b8e332cb | 156 | unsigned short SPI8::rd_gram(bool convert) |
Geremia | 5:b222a9461d6b | 157 | { |
Geremia | 5:b222a9461d6b | 158 | #ifdef USE_CS |
Geremia | 5:b222a9461d6b | 159 | _CS = 0; |
Geremia | 5:b222a9461d6b | 160 | #endif |
Geremia | 5:b222a9461d6b | 161 | unsigned int r=0; |
Geremia | 5:b222a9461d6b | 162 | _DC.write(1); // 1=data |
Geremia | 5:b222a9461d6b | 163 | _spi.write(0); // whole first byte is dummy |
Geremia | 5:b222a9461d6b | 164 | r |= _spi.write(0); |
Geremia | 5:b222a9461d6b | 165 | r <<= 8; |
Geremia | 5:b222a9461d6b | 166 | r |= _spi.write(0); |
Geremia | 11:b842b8e332cb | 167 | if(convert) |
Geremia | 11:b842b8e332cb | 168 | { |
Geremia | 11:b842b8e332cb | 169 | r <<= 8; |
Geremia | 11:b842b8e332cb | 170 | r |= _spi.write(0); |
Geremia | 11:b842b8e332cb | 171 | // gram is 18bit/pixel, if you set 16bit/pixel (cmd 3A), during writing the 16bits are expanded to 18bit |
Geremia | 11:b842b8e332cb | 172 | // during reading, you read the raw 18bit gram |
Geremia | 11:b842b8e332cb | 173 | r = RGB24to16((r&0xFF0000)>>16, (r&0xFF00)>>8, r&0xFF);// 18bit pixel padded to 24bits, rrrrrr00_gggggg00_bbbbbb00, converted to 16bit |
Geremia | 11:b842b8e332cb | 174 | } |
Geremia | 5:b222a9461d6b | 175 | _CS = 1; // force CS HIG to interupt the "read state" |
Geremia | 5:b222a9461d6b | 176 | #ifndef USE_CS //if CS is not used, force fixed LOW again |
Geremia | 5:b222a9461d6b | 177 | _CS = 0; |
Geremia | 5:b222a9461d6b | 178 | #endif |
Geremia | 5:b222a9461d6b | 179 | return (unsigned short)r; |
Geremia | 5:b222a9461d6b | 180 | } |
Geremia | 7:bb0383b91104 | 181 | unsigned int SPI8::rd_reg_data32(unsigned char reg) |
Geremia | 7:bb0383b91104 | 182 | { |
Geremia | 7:bb0383b91104 | 183 | #ifdef USE_CS |
Geremia | 7:bb0383b91104 | 184 | _CS = 0; |
Geremia | 7:bb0383b91104 | 185 | #endif |
Geremia | 7:bb0383b91104 | 186 | wr_cmd8(reg); |
Geremia | 7:bb0383b91104 | 187 | unsigned int r=0; |
Geremia | 7:bb0383b91104 | 188 | _DC.write(1); // 1=data |
Geremia | 7:bb0383b91104 | 189 | |
Geremia | 7:bb0383b91104 | 190 | r |= _spi.write(0); // we get only 7bit valid, first bit was the dummy cycle |
Geremia | 7:bb0383b91104 | 191 | r <<= 8; |
Geremia | 7:bb0383b91104 | 192 | r |= _spi.write(0); |
Geremia | 7:bb0383b91104 | 193 | r <<= 8; |
Geremia | 7:bb0383b91104 | 194 | r |= _spi.write(0); |
Geremia | 7:bb0383b91104 | 195 | r <<= 8; |
Geremia | 7:bb0383b91104 | 196 | r |= _spi.write(0); |
Geremia | 7:bb0383b91104 | 197 | r <<= 1; // 32bits are aligned, now collecting bit_0 |
Geremia | 7:bb0383b91104 | 198 | r |= (_spi.write(0) >> 7); |
Geremia | 7:bb0383b91104 | 199 | // we clocked 7 more bit so ILI waiting for 8th, we need to reset spi bus |
Geremia | 7:bb0383b91104 | 200 | _CS = 1; // force CS HIG to interupt the cmd |
Geremia | 7:bb0383b91104 | 201 | #ifndef USE_CS //if CS is not used, force fixed LOW again |
Geremia | 7:bb0383b91104 | 202 | _CS = 0; |
Geremia | 7:bb0383b91104 | 203 | #endif |
Geremia | 7:bb0383b91104 | 204 | return r; |
Geremia | 7:bb0383b91104 | 205 | } |
Geremia | 7:bb0383b91104 | 206 | unsigned int SPI8::rd_extcreg_data32(unsigned char reg, unsigned char SPIreadenablecmd) |
Geremia | 7:bb0383b91104 | 207 | { |
Geremia | 7:bb0383b91104 | 208 | unsigned int r=0; |
Geremia | 7:bb0383b91104 | 209 | for(int regparam=1; regparam<4; regparam++) // when reading EXTC regs, first parameter is always dummy, so start with 1 |
Geremia | 7:bb0383b91104 | 210 | { |
Geremia | 7:bb0383b91104 | 211 | wr_cmd8(SPIreadenablecmd); // spi-in enable cmd, 0xD9 (ili9341) or 0xFB (ili9488) or don't know |
Geremia | 7:bb0383b91104 | 212 | wr_data8(0xF0|regparam); // in low nibble specify which reg parameter we want |
Geremia | 7:bb0383b91104 | 213 | wr_cmd8(reg); // now send cmd (select register we want to read) |
Geremia | 7:bb0383b91104 | 214 | _DC.write(1); // 1=data |
Geremia | 7:bb0383b91104 | 215 | r <<= 8; |
Geremia | 7:bb0383b91104 | 216 | r |= _spi.write(0); |
Geremia | 7:bb0383b91104 | 217 | // r = _spi.write(0) >> 8; for 16bit |
Geremia | 7:bb0383b91104 | 218 | } |
Geremia | 7:bb0383b91104 | 219 | _CS = 1; // force CS HIG to interupt the cmd |
Geremia | 7:bb0383b91104 | 220 | #ifndef USE_CS //if CS is not used, force fixed LOW again |
Geremia | 7:bb0383b91104 | 221 | _CS = 0; |
Geremia | 7:bb0383b91104 | 222 | #endif |
Geremia | 7:bb0383b91104 | 223 | return r; |
Geremia | 7:bb0383b91104 | 224 | } |
Geremia | 0:75ec1b3cde17 | 225 | void SPI8::hw_reset() |
Geremia | 0:75ec1b3cde17 | 226 | { |
Geremia | 0:75ec1b3cde17 | 227 | wait_ms(15); |
Geremia | 0:75ec1b3cde17 | 228 | _DC = 1; |
Geremia | 0:75ec1b3cde17 | 229 | // _CS = 1; |
Geremia | 0:75ec1b3cde17 | 230 | _CS = 0; |
Geremia | 0:75ec1b3cde17 | 231 | _reset = 0; // display reset |
Geremia | 0:75ec1b3cde17 | 232 | wait_us(50); |
Geremia | 0:75ec1b3cde17 | 233 | _reset = 1; // end reset |
Geremia | 0:75ec1b3cde17 | 234 | wait_ms(15); |
Geremia | 0:75ec1b3cde17 | 235 | #ifndef USE_CS |
Geremia | 0:75ec1b3cde17 | 236 | _CS=0; // put CS low now and forever |
Geremia | 0:75ec1b3cde17 | 237 | #endif |
Geremia | 0:75ec1b3cde17 | 238 | } |
Geremia | 0:75ec1b3cde17 | 239 | void SPI8::BusEnable(bool enable) |
Geremia | 0:75ec1b3cde17 | 240 | { |
Geremia | 0:75ec1b3cde17 | 241 | _CS = enable ? 0:1; |
trevieze | 33:e3b3181a57e2 | 242 | } |
trevieze | 33:e3b3181a57e2 | 243 | |
trevieze | 33:e3b3181a57e2 | 244 | // need to re-create SPI firmware to access SPI handle |
trevieze | 33:e3b3181a57e2 | 245 | static SPI_HandleTypeDef SpiHandle; |
trevieze | 33:e3b3181a57e2 | 246 | |
trevieze | 33:e3b3181a57e2 | 247 | void SPI8::fastWrite(int data) { |
trevieze | 33:e3b3181a57e2 | 248 | |
trevieze | 33:e3b3181a57e2 | 249 | SpiHandle.Instance = SPI1; |
trevieze | 33:e3b3181a57e2 | 250 | // Check if data is transmitted |
trevieze | 33:e3b3181a57e2 | 251 | while ((SpiHandle.Instance->SR & SPI_SR_TXE) == 0); |
trevieze | 33:e3b3181a57e2 | 252 | SpiHandle.Instance->DR = data; |
trevieze | 33:e3b3181a57e2 | 253 | } |
trevieze | 33:e3b3181a57e2 | 254 | |
trevieze | 33:e3b3181a57e2 | 255 | void SPI8::clearRX( void ) { |
trevieze | 33:e3b3181a57e2 | 256 | SpiHandle.Instance = SPI1; |
trevieze | 33:e3b3181a57e2 | 257 | //Check if the RX buffer is busy |
trevieze | 33:e3b3181a57e2 | 258 | //While busy, keep checking |
trevieze | 33:e3b3181a57e2 | 259 | while (SpiHandle.Instance->SR & SPI_SR_BSY){ |
trevieze | 33:e3b3181a57e2 | 260 | // Check RX buffer readable |
trevieze | 33:e3b3181a57e2 | 261 | while ((SpiHandle.Instance->SR & SPI_SR_RXNE) == 0); |
trevieze | 33:e3b3181a57e2 | 262 | int dummy = SpiHandle.Instance->DR; |
trevieze | 33:e3b3181a57e2 | 263 | } |
trevieze | 33:e3b3181a57e2 | 264 | } |